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authorLijian Zhao <lijian.zhao@intel.com>2018-12-06 17:29:55 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 05:32:34 +0000
commit3ef74493928fafa2955e3b0acecb2b625f223d83 (patch)
tree81bce5493c4e66ba65f67f3eec6da64684d799f9
parent6b2c9b17514d10f61106c50580ea6c0f33345e00 (diff)
downloadcoreboot-3ef74493928fafa2955e3b0acecb2b625f223d83.tar.xz
soc/intel/cannonlake: Auto turn on HDA controller
Update HDAenable bit in Fsp memory init UPD data base on devicetree settings. BUG=N/A TEST=N/A Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
-rw-r--r--src/soc/intel/cannonlake/chip.h1
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c8
2 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 962748f561..350217807c 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -133,7 +133,6 @@ struct soc_intel_cannonlake_config {
uint8_t SataPortsDevSlp[8];
/* Audio related */
- uint8_t PchHdaEnable;
uint8_t PchHdaDspEnable;
/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 3e0f92249a..c3a2509063 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -59,6 +59,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->PchIshEnable = 0;
else
m_cfg->PchIshEnable = dev->enabled;
+
+ /* If HDA is enabled, enable HDA elements */
+ dev = dev_find_slot(0, PCH_DEVFN_HDA);
+ if (!dev)
+ m_cfg->PchHdaEnable = 0;
+ else
+ m_cfg->PchHdaEnable = dev->enabled;
+
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)