soc/intel/apollolake: clarify meaning of LPDDR4 density meaning

The 'dram density' is a misnomer because the memory initialization
code treats that input parameter as a per rank density. Therefore,
update the variables to further clarify how it's actually being
used.

BUG=chrome-os-partner:55446

Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15773
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

3 files changed, 33 insertions, 32 deletions

diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index 74ead51bea..f9743b5f34 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -78,16 +78,16 @@ static const struct lpddr4_sku skus[] = {
 	 */
 	[0] = {
 		.speed = LP4_SPEED_2400,
-		.ch0_density = LP4_8Gb_DENSITY,
-		.ch1_density = LP4_8Gb_DENSITY,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
 		.ch0_dual_rank = 1,
 		.ch1_dual_rank = 1,
 	},
 	/* K4F8E304HB-MGCJ - both logical channels  */
 	[1] = {
 		.speed = LP4_SPEED_2400,
-		.ch0_density = LP4_8Gb_DENSITY,
-		.ch1_density = LP4_8Gb_DENSITY,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
 	},
 	/*
 	 * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
@@ -96,22 +96,22 @@ static const struct lpddr4_sku skus[] = {
 	 */
 	[2] = {
 		.speed = LP4_SPEED_2400,
-		.ch0_density = LP4_8Gb_DENSITY,
-		.ch1_density = LP4_8Gb_DENSITY,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
 		.ch0_dual_rank = 1,
 		.ch1_dual_rank = 1,
 	},
 	/* MT53B256M32D1NP-062 WT:C - both logical channels */
 	[3] = {
 		.speed = LP4_SPEED_2400,
-		.ch0_density = LP4_8Gb_DENSITY,
-		.ch1_density = LP4_8Gb_DENSITY,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
 	},
 	/* K4F8E304HB-MGCH - both logical channels */
 	[PROTO_SKU] = {
 		.speed = LP4_SPEED_2400,
-		.ch0_density = LP4_8Gb_DENSITY,
-		.ch1_density = LP4_8Gb_DENSITY,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
 	},
 };
 
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index b619b95642..a7da1ac2bd 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -92,13 +92,13 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed);
  * to the memory reference code.
  */
 void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
-					int device_density, int dual_rank,
+					int rank_density, int dual_rank,
 					const struct lpddr4_swizzle_cfg *scfg);
 
 struct lpddr4_sku {
 	int speed;
-	int ch0_density;
-	int ch1_density;
+	int ch0_rank_density;
+	int ch1_rank_density;
 	int ch0_dual_rank;
 	int ch1_dual_rank;
 };
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 41eb601b41..92b84c80af 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -105,7 +105,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed)
 }
 
 static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
-					int device_density, int dual_rank,
+					int rank_density, int dual_rank,
 					const struct lpddr4_swizzle_cfg *scfg)
 {
 	const struct lpddr4_chan_swizzle_cfg *chan;
@@ -118,8 +118,8 @@ static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
 	 * Physical channel 0 is comprised of the CH0_DQB signals.
 	 * Physical channel 1 is comprised of the CH0_DQA signals.
 	 */
-	cfg->Ch0_DramDensity = device_density;
-	cfg->Ch1_DramDensity = device_density;
+	cfg->Ch0_DramDensity = rank_density;
+	cfg->Ch1_DramDensity = rank_density;
 	/* Enable ranks on both channels depending on dual rank option. */
 	rank_mask = dual_rank ? 0x3 : 0x1;
 	cfg->Ch0_RankEnable = rank_mask;
@@ -150,7 +150,7 @@ static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
 }
 
 static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
-					int device_density, int dual_rank,
+					int rank_density, int dual_rank,
 					const struct lpddr4_swizzle_cfg *scfg)
 {
 	const struct lpddr4_chan_swizzle_cfg *chan;
@@ -163,8 +163,8 @@ static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
 	 * Physical channel 2 is comprised of the CH1_DQB signals.
 	 * Physical channel 3 is comprised of the CH1_DQA signals.
 	 */
-	cfg->Ch2_DramDensity = device_density;
-	cfg->Ch3_DramDensity = device_density;
+	cfg->Ch2_DramDensity = rank_density;
+	cfg->Ch3_DramDensity = rank_density;
 	/* Enable ranks on both channels depending on dual rank option. */
 	rank_mask = dual_rank ? 0x3 : 0x1;
 	cfg->Ch2_RankEnable = rank_mask;
@@ -195,22 +195,21 @@ static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
 }
 
 void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
-					int device_density, int dual_rank,
+					int rank_density, int dual_rank,
 					const struct lpddr4_swizzle_cfg *scfg)
 {
-	if (device_density < LP4_8Gb_DENSITY ||
-		device_density > LP4_16Gb_DENSITY) {
-		printk(BIOS_ERR, "Invalid LPDDR4 density: %d\n",
-			device_density);
+	if (rank_density < LP4_8Gb_DENSITY ||
+		rank_density > LP4_16Gb_DENSITY) {
+		printk(BIOS_ERR, "Invalid LPDDR4 density: %d\n", rank_density);
 		return;
 	}
 
 	switch (logical_chan) {
 	case LP4_LCH0:
-		enable_logical_chan0(cfg, device_density, dual_rank, scfg);
+		enable_logical_chan0(cfg, rank_density, dual_rank, scfg);
 		break;
 	case LP4_LCH1:
-		enable_logical_chan1(cfg, device_density, dual_rank, scfg);
+		enable_logical_chan1(cfg, rank_density, dual_rank, scfg);
 		break;
 	default:
 		printk(BIOS_ERR, "Invalid logical channel: %d\n", logical_chan);
@@ -235,18 +234,20 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
 
 	meminit_lpddr4(cfg, sku->speed);
 
-	if (sku->ch0_density) {
+	if (sku->ch0_rank_density) {
 		printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n",
-			sku->ch0_density);
-		meminit_lpddr4_enable_channel(cfg, LP4_LCH0, sku->ch0_density,
+			sku->ch0_rank_density);
+		meminit_lpddr4_enable_channel(cfg, LP4_LCH0,
+						sku->ch0_rank_density,
 						sku->ch0_dual_rank,
 						lpcfg->swizzle_config);
 	}
 
-	if (sku->ch1_density) {
+	if (sku->ch1_rank_density) {
 		printk(BIOS_INFO, "LPDDR4 Ch1 density = %d\n",
-			sku->ch1_density);
-		meminit_lpddr4_enable_channel(cfg, LP4_LCH1, sku->ch1_density,
+			sku->ch1_rank_density);
+		meminit_lpddr4_enable_channel(cfg, LP4_LCH1,
+						sku->ch1_rank_density,
 						sku->ch1_dual_rank,
 						lpcfg->swizzle_config);
 	}