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| author | Raul E Rangel <rrangel@chromium.org> | 2020-05-07 15:14:09 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 08:35:58 +0000 |
| commit | 4c7e0d734f198d05f668d3a28fd8362f7382b02c (patch) | |
| tree | 5c88e5636a20e0ab7da5593bcc39f9eb155bea94 | |
| parent | 94acba86fa05a5994d8d81da89dee063ab6d34d8 (diff) | |
| download | coreboot-4c7e0d734f198d05f668d3a28fd8362f7382b02c.tar.xz | |
soc/amd/picasso: Move ACP register to acp.h
This is a device specific register, not a northbridge register.
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I97b63571e336f541dcb274e4c8c608f6fc59ff42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41263
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/acp.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/acp.h | 10 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index c2c1022f76..e0b369d65e 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -6,9 +6,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "chip.h" +#include <soc/acp.h> #include <soc/acpi.h> #include <soc/pci_devs.h> -#include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <commonlib/helpers.h> diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h new file mode 100644 index 0000000000..e7ec17ca38 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __PI_PICASSO_ACP_H__ +#define __PI_PICASSO_ACP_H__ + +/* Bus A D0F5 - Audio Processor */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ + +#endif /* __PI_PICASSO_ACP_H__ */ |