diff options
| author | Nico Huber <nico.h@gmx.de> | 2019-02-10 19:35:41 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-02-12 13:34:16 +0000 |
| commit | 4c7eee27447e1a41808a11be8ce55031e97fdccf (patch) | |
| tree | a307d6c4aeaf26d210bcd23b15c01c8cd8493250 | |
| parent | 4dba4975b4e9710e159a000f7afed46a306134b3 (diff) | |
| download | coreboot-4c7eee27447e1a41808a11be8ce55031e97fdccf.tar.xz | |
postcar: Make more use of postcar_frame_add_romcache()
Some similar calls to postcar_frame_add_mtrr() were added in the
meantime or were under review while postcar_frame_add_romcache()
was introduced.
Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/ram_calc.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 3 |
4 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ff729d6285..cfc4a13dd3 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -55,8 +55,7 @@ void platform_enter_postcar(void) if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 3362d93f48..962f3ba6f6 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -81,8 +81,7 @@ void platform_enter_postcar(void) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4b499061e9..8de670038b 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -249,8 +249,7 @@ static void platform_enter_postcar(void) if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index b89d948eba..0cbc8c2ca0 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -47,8 +47,7 @@ static void platform_enter_postcar(void) if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |