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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-07 02:18:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-14 18:16:48 +0000 |
| commit | 542fa6de384d4b79d8964512b4088bcd90863bd2 (patch) | |
| tree | e9afd8b9987de8dabeae90749e06628869a1924c | |
| parent | 8dd2d485b84b103eabae3e01c3b04f529d98ed50 (diff) | |
| download | coreboot-542fa6de384d4b79d8964512b4088bcd90863bd2.tar.xz | |
soc/intel/baytrail: Add SOUTHBRIDGE_INTEL_COMMON_SMBUS
Change-Id: Ie026b8c57046d951752158fd28277e338ed1421c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4e9223750e..1fd9c4072c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP |