mb/hp: Add new port compaq_8200_elite_sff

Add new port based on autoport.

The board uses a NPCD378 SuperIO, that is full of custom hardware.

The 8MiB flash SOIC-8 can be accessed after cutting of a part of the
DIMM slot holder. The flash IC has no diode, powering a part of the
board while flashing externaly, including the Standby-LED.

The following have been tested and is working:
* Native raminit with up to four DIMMs
* Libgfxinit on DisplayPort
* USB
* EHCI debug
* Serial on RS232
* Ethernet
* PCIe on x4
* PCIe on x16
* SATA
* Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload
* Flashing internaly
* PS/2 is working

Untested:
* PCI slot
* LPT port
* VBIOS
* S3 resume

Not working:
* PSU fan managment (runs at 100%)
* Half of SuperIO functionality is unknown

TODO:
* Reverse engineer remaining SuperIO registers
* Reverse engineer SMM

Fixes on follow-up commits:
* Added PSU fan control
* Reverse engineered some of Super IO's HWM registers
* Added SMBIOS tables for IPMI

Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

17 files changed, 972 insertions, 0 deletions

diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig
new file mode 100644
index 0000000000..3b658bf99a
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig
@@ -0,0 +1,64 @@
+if BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select CPU_INTEL_SOCKET_LGA1155
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select USE_NATIVE_RAMINIT
+	select MAINBOARD_HAS_LPC_TPM
+	select TPM
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select SUPERIO_NUVOTON_NPCD378
+	select MAINBOARD_HAS_LIBGFXINIT
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config HAVE_ME_BIN
+	bool
+	default n
+
+config MAINBOARD_DIR
+	string
+	default hp/compaq_8200_elite_sff
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "HP Compaq 8200 Elite SFF PC"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0102.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,0102"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x1495
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x103c
+
+config DRAM_RESET_GATE_GPIO
+	int
+	default 60
+
+config MAX_CPUS
+	int
+	default 8
+
+config USBDEBUG_HCD_INDEX
+	int
+	default 2
+endif
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name
new file mode 100644
index 0000000000..8de7363875
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC
+	bool "Compaq 8200 Elite SFF"
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc
new file mode 100644
index 0000000000..ebe01aea99
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc
@@ -0,0 +1,2 @@
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl
new file mode 100644
index 0000000000..733c4b1a5c
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl
new file mode 100644
index 0000000000..9ec294923a
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+
+#define SUPERIO_SHOW_SP2
+#define SUPERIO_SHOW_KBC
+
+#include <superio/nuvoton/npcd378/acpi/superio.asl>
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c
new file mode 100644
index 0000000000..084e7e5a5f
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	gnvs->tcrt = 100;
+	gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/board_info.txt b/src/mainboard/hp/compaq_8200_elite_sff/board_info.txt
new file mode 100644
index 0000000000..4d6f6f98b7
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://support.hp.com/de-de/product/HP-Compaq-8200-Elite-Small-Form-Factor-PC/5037931
+ROM IC: MX25L6405
+ROM package: SOIC-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2013
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
new file mode 100644
index 0000000000..390d231fb1
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout
new file mode 100644
index 0000000000..e90af85a09
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout
@@ -0,0 +1,112 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392          3       r       0        unused
+395          4       e       6        debug_level
+#399          9       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+
+#411       10       r       0        unused
+421         1       e       9        sata_mode
+#422       10       r       0        unused
+
+# coreboot config options: northbridge
+432         3        e      11        gfx_uma_size
+#435        549       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+9     0     AHCI
+9     1     IDE
+11    0     32M
+11    1     64M
+11    2	    96M
+11    3	    128M
+11    4	    160M
+11    5	    192M
+11    6	    224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
new file mode 100644
index 0000000000..fab4cca483
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
@@ -0,0 +1,226 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+	register "gfx.link_frequency_270_mhz" = "0"
+	register "gfx.ndid" = "3"
+	register "gfx.use_spread_spectrum_clock" = "0"
+	register "gpu_dp_b_hotplug" = "0"
+	register "gpu_dp_c_hotplug" = "0"
+	register "gpu_dp_d_hotplug" = "0"
+
+	device cpu_cluster 0x0 on
+		chip cpu/intel/socket_LGA1155
+			device lapic 0x0 on
+			end
+		end
+		chip cpu/intel/model_206ax
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0xacac off
+			end
+		end
+	end
+
+	register "pci_mmio_size" = "2048"
+
+	device domain 0x0 on
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "c2_latency" = "0x0065"
+			register "docking_supported" = "0"
+			register "gen1_dec" = "0x00fc0601"
+			register "gen2_dec" = "0x00fc0801"
+			register "p_cnt_throttling_supported" = "1"
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x13"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x0"
+			device pci 16.0 on # Management Engine Interface 1
+				subsystemid 0x103c 0x1495
+			end
+			device pci 16.1 off # Management Engine Interface 2
+			end
+			device pci 16.2 off # Management Engine IDE-R
+			end
+			device pci 16.3 on # Management Engine KT
+				subsystemid 0x103c 0x1495
+			end
+			device pci 19.0 on # Intel Gigabit Ethernet
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1b.0 on # High Definition Audio Audio controller
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1c.0 on # PCIe Port #1
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1c.1 off # PCIe Port #2
+			end
+			device pci 1c.2 off # PCIe Port #3
+			end
+			device pci 1c.3 off # PCIe Port #4
+			end
+			device pci 1c.4 on # PCIe Port #5
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1c.5 off # PCIe Port #6
+			end
+			device pci 1c.6 on # PCIe Port #7
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1c.7 on # PCIe Port #8
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1e.0 on # PCI bridge
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				subsystemid 0x103c 0x1495
+				chip superio/nuvoton/npcd378
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# Parallel port
+						# global
+
+						# serialice: Vendor writes:
+						irq 0x14 = 0x9c
+						irq 0x1c = 0xa8
+						irq 0x1d = 0x08
+						irq 0x22 = 0x3f
+						irq 0x1a = 0xb0
+						# dumped from superiotool:
+						irq 0x1b = 0x1e
+						irq 0x27 = 0x04
+						irq 0x2a = 0x00
+						irq 0x2d = 0x01
+						# parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 0x07
+						drq 0x74 = 0x01
+					end
+					device pnp 2e.2 off		# COM1
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.3 on		# COM2, IR
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.4 on		# LED control
+						io 0x60 = 0x600
+						# IOBASE[0h] = bit0 LED red / green
+						# IOBASE[0h] = bit1-4 LED PWM duty cycle
+						# IOBASE[1h] = bit6 SWCC
+
+						io 0x62 = 0x610
+						# IOBASE [0h] = GPES
+						# IOBASE [1h] = GPEE
+						# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
+						# IOBASE [8h:bh] = GPS
+						# IOBASE [ch:fh] = GPE
+					end
+					device pnp 2e.5 on		# Mouse
+						irq 0x70 = 0xc
+					end
+					device pnp 2e.6 on		# Keyboard
+						io 0x60 = 0x0060
+						io 0x62 = 0x0064
+						irq 0x70 = 0x01
+						# serialice: Vendor writes:
+						drq 0xf0 = 0x40
+					end
+					device pnp 2e.7 on		#  WDT ?
+						io 0x60 = 0x620
+					end
+					device pnp 2e.8 on		# HWM
+						io 0x60 = 0x800
+						# IOBASE[0h:feh] HWM page
+						# IOBASE[ffh] bit0-bit3 page selector
+
+						drq 0xf0 = 0x20
+						drq 0xf1 = 0x01
+						drq 0xf2 = 0x40
+						drq 0xf3 = 0x01
+
+						drq 0xf4 = 0x66
+						drq 0xf5 = 0x67
+						drq 0xf6 = 0x66
+						drq 0xf7 = 0x01
+					end
+					device pnp 2e.f on		# GPIO OD ?
+						drq 0xf1 = 0x97
+						drq 0xf2 = 0x01
+						drq 0xf5 = 0x08
+						drq 0xfe = 0x80
+					end
+					device pnp 2e.15 on		# BUS ?
+						io 0x60 = 0x0680
+						io 0x62 = 0x0690
+					end
+					device pnp 2e.1c on		# Suspend Control ?
+						io 0x60 = 0x640
+						# writing to IOBASE[5h]
+						#  0x0: Power off
+						#  0x9: Power off and bricked until CMOS battery removed
+					end
+					device pnp 2e.1e on		# GPIO ?
+						io 0x60 = 0x660
+						drq 0xf4 = 0x01
+						# skip the following, as it
+						# looks like remapped registers
+						#drq 0xf5 = 0x06
+						#drq 0xf6 = 0x60
+						#drq 0xfe = 0x03
+					end
+				end
+			end
+			chip drivers/pc80/tpm
+				device pnp 4e.0 on end		# TPM module
+			end
+			device pci 1f.2 on # SATA Controller 1
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x103c 0x1495
+			end
+			device pci 1f.5 off # SATA Controller 2
+			end
+			device pci 1f.6 off # Thermal
+			end
+		end
+		device pci 00.0 on # Host bridge Host bridge
+			subsystemid 0x103c 0x1495
+		end
+		device pci 01.0 on # PCIe Bridge for discrete graphics
+			subsystemid 0x103c 0x1495
+		end
+		device pci 02.0 on # Internal graphics VGA controller
+			subsystemid 0x103c 0x1495
+		end
+	end
+end
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl
new file mode 100644
index 0000000000..555028cbf4
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20141018	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+	/* global NVS and variables.  */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+}
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads
new file mode 100644
index 0000000000..6d5680d6a9
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads
@@ -0,0 +1,29 @@
+--
+-- Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP2,
+      HDMI2,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gpio.c b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c
new file mode 100644
index 0000000000..8786e2874a
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c
@@ -0,0 +1,209 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio1 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c
new file mode 100644
index 0000000000..4b90aab935
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0662, /* Codec Vendor / Device ID: Realtek */
+	0x103c1495, /* Subsystem ID */
+
+	0x0000000b, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x0, 0x103c1495),
+
+	/* NID 0x14.  */
+	AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
+
+	/* NID 0x15.  */
+	AZALIA_PIN_CFG(0x0, 0x15, 0x99130120),
+
+	/* NID 0x16.  */
+	AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
+
+	/* NID 0x18.  */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x01813c30),
+
+	/* NID 0x19.  */
+	AZALIA_PIN_CFG(0x0, 0x19, 0x02a11c3f),
+
+	/* NID 0x1a.  */
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+	/* NID 0x1b.  */
+	AZALIA_PIN_CFG(0x0, 0x1b, 0x0221101f),
+
+	/* NID 0x1c.  */
+	AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
+
+	/* NID 0x1d.  */
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x40028101),
+
+	/* NID 0x1e.  */
+	AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+	0x80862805, /* Codec Vendor / Device ID: Intel */
+	0x80861495, /* Subsystem ID */
+
+	0x00000004, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x3, 0x80861495),
+
+	/* NID 0x05.  */
+	AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
+
+	/* NID 0x06.  */
+	AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+	/* NID 0x07.  */
+	AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
new file mode 100644
index 0000000000..527b0d1980
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
new file mode 100644
index 0000000000..98d5ef4770
--- /dev/null
+++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <superio/nuvoton/npcd378/npcd378.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
+void pch_enable_lpc(void)
+{
+	/*
+	 * Enable SuperIO, TPM, Keyboard, LPT, COMA
+	 * (COMB can be equip on expansion header)
+	 */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN,
+	    CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |
+	    COMB_LPC_EN | COMA_LPC_EN);
+
+	/* COMA: 3F8h, COMB: 2F8h */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+	{ 1, 0, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	/* BTX mainboard: Reversed mapping */
+	read_spd(&spd[3], 0x50, id_only);
+	read_spd(&spd[2], 0x51, id_only);
+	read_spd(&spd[1], 0x52, id_only);
+	read_spd(&spd[0], 0x53, id_only);
+}