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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-06 08:07:50 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-11-21 22:42:28 +0100 |
| commit | 657d9cd5482835b49d79c7eabeb7baf2dce70dfe (patch) | |
| tree | 7d9146d6fbf76c5ab50cdf74032bd9039516083f | |
| parent | 7f1df8c0c13cf40d2eb74f7b13a3983ba7b3b3f2 (diff) | |
| download | coreboot-657d9cd5482835b49d79c7eabeb7baf2dce70dfe.tar.xz | |
smscsuperio: map interrupt in smscsuperio_enable_serial()
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the
interrupt is unmapped at reset, but for whatever reason the chip is
inaccessible in smscsuperio/superio.c::enable_dev() and thus the
devicetree.cb IRQ information is not applied in ramstage and then
serial console output fails to work for more than the UART FIFO depth
in the OS.
Change-Id: I00998088975569516f7caeb7f4098b48fe437889
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/10807
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/superio/smsc/smscsuperio/early_serial.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 7845ab83be..27e3ef266c 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -51,6 +51,14 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + switch (iobase) { + case 0x03f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + break; + case 0x02f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + break; + } pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } |