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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-16 14:18:21 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-17 21:28:21 +0200 |
| commit | 8c22057b2d905daeb310215fca0c0a67ad95322c (patch) | |
| tree | d2193c414316be8b1d62e98c0ee6ce9632287138 | |
| parent | fe661612d8e94d41dc0129533bb02f7c4faaf11a (diff) | |
| download | coreboot-8c22057b2d905daeb310215fca0c0a67ad95322c.tar.xz | |
gm45: Declare BIOS memory as RAM.
So it's in line with other boards and those addresses are cached for faster
access.
Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6689
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 42561e4d5d..7a4b03837c 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -34,14 +34,12 @@ #include "gm45.h" #include "arch/acpi.h" -/* Reserve everything between A segment and 1MB: +/* Reserve segments A and B: * * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; +static const int legacy_hole_size_k = 128; static int decode_pcie_bar(u32 *const base, u32 *const len) { |