cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK

This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.

This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.

Tested on Google peppy (Acer C720).

Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.

Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

11 files changed, 33 insertions, 77 deletions

diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index b2b915fe76..251714cb8f 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -33,6 +33,11 @@ _cache_as_ram_setup:
 
 bootblock_pre_c_entry:
 
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+	movl	$cache_as_ram, %esp /* return address */
+	jmp	check_mtrr /* Check if CPU properly reset */
+#endif
+
 cache_as_ram:
 	post_code(0x20)
 
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 3aadfdee5a..3fd8bb484a 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -24,10 +24,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP
 	select CPU_INTEL_COMMON
 
-config BOOTBLOCK_CPU_INIT
-	string
-	default "cpu/intel/haswell/bootblock.c"
-
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index 1fa71c9521..3b5229455e 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -21,7 +21,11 @@ ramstage-y += monotonic_timer.c
 smm-y += monotonic_timer.c
 endif
 
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += ../car/non-evict/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += ../../x86/early_reset.S
+bootblock-y += bootblock.c
+
 postcar-y += ../car/non-evict/exit_car.S
 
 subdirs-y += ../../x86/tsc
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 722cc0102e..7baa2a81ec 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -14,7 +14,7 @@
  */
 
 #include <stdint.h>
-#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
@@ -23,41 +23,8 @@
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"
 
-#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
-/* Needed for RCBA access to set Soft Reset Data register */
 #include <southbridge/intel/lynxpoint/pch.h>
-#else
-#error "CPU must be paired with Intel LynxPoint southbridge"
-#endif
-
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
-	unsigned int type)
-
-{
-	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-	/* FIXME: It only support 4G less range */
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
-	msr_t msr;
-
-	disable_cache();
-	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	enable_cache();
-
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
+#include <cpu/intel/car/bootblock.h>
 
 static void set_flex_ratio_to_tdp_nominal(void)
 {
@@ -105,26 +72,8 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	halt();
 }
 
-static void check_for_clean_reset(void)
-{
-	msr_t msr;
-	msr = rdmsr(MTRR_DEF_TYPE_MSR);
-
-	/* Use the MTRR default type MSR as a proxy for detecting INIT#.
-	 * Reset the system if any known bits are set in that MSR. That is
-	 * an indication of the CPU not being properly reset. */
-	if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) {
-		outb(0x0, 0xcf9);
-		outb(0x6, 0xcf9);
-		halt();
-	}
-}
-
-static void bootblock_cpu_init(void)
+void bootblock_early_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	check_for_clean_reset();
-	enable_rom_caching();
-	intel_update_microcode_from_cbfs();
 }
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 082f2d63d9..242ab18c49 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -22,6 +22,8 @@ config NORTHBRIDGE_INTEL_HASWELL
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
+	select C_ENVIRONMENT_BOOTBLOCK
+#	select BOOTBLOCK_CONSOLE TODO: route LPC
 
 if NORTHBRIDGE_INTEL_HASWELL
 
@@ -29,10 +31,6 @@ config VBOOT
 	select VBOOT_OPROM_MATTERS
 	select VBOOT_STARTS_IN_ROMSTAGE
 
-config BOOTBLOCK_NORTHBRIDGE_INIT
-	string
-	default "northbridge/intel/haswell/bootblock.c"
-
 config VGA_BIOS_ID
 	string
 	default "8086,0166"
@@ -63,6 +61,13 @@ config DCACHE_RAM_MRC_VAR_SIZE
 	help
 	  The amount of cache-as-ram region required by the reference code.
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+	help
+	  The amount of anticipated stack usage in CAR by bootblock and
+	  other stages.
+
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	help
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 055c2a8a0d..7abbccacd2 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -15,6 +15,8 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y)
 
+bootblock-y += bootblock.c
+
 ramstage-y += ram_calc.c
 ramstage-y += northbridge.c
 ramstage-y += gma.c
@@ -26,7 +28,6 @@ romstage-y += ram_calc.c
 romstage-y += raminit.c
 romstage-y += early_init.c
 romstage-y += report_platform.c
-romstage-y += ../../../arch/x86/walkcbfs.S
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index e503e01fa1..2c1bd58dde 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -12,11 +12,10 @@
  */
 
 #include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
+#include "haswell.h"
 
-/* Just re-define this instead of including haswell.h. It blows up romcc. */
-#define PCIEXBAR	0x60
-
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
 {
 	uint32_t reg;
 
@@ -33,7 +32,7 @@ static void bootblock_northbridge_init(void)
 	 * 4GiB.
 	 */
 	reg = 0;
-	pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
+	pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg);
 	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
-	pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
+	pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
 }
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 431744f08c..5573ec96ad 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -53,10 +53,6 @@ config EHCI_BAR
 	hex
 	default 0xe8000000
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/intel/lynxpoint/bootblock.c"
-
 config SERIRQ_CONTINUOUS_MODE
 	bool
 	default n
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index b18e6dafc8..62766dfe90 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -15,6 +15,8 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
 
+bootblock-y += bootblock.c
+
 ramstage-y += pch.c
 ramstage-y += azalia.c
 ramstage-y += lpc.c
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 16f4ef90bc..69fdd611d2 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -14,6 +14,7 @@
  */
 
 #include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
 #include "pch.h"
 
 /*
@@ -69,7 +70,7 @@ static void set_spi_speed(void)
 	SPIBAR8(SSFC + 2) = ssfc;
 }
 
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
 {
 	map_rcba();
 	enable_spi_prefetch();
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 3d2d2c48fa..f615507dad 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -116,8 +116,6 @@ int early_pch_init(const void *gpio_map,
 
 	mainboard_config_superio();
 
-	console_init();
-
 	pch_generic_setup();
 
 	/* Enable SMBus for reading SPDs. */