diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-06 13:42:37 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-09 01:32:21 +0200 |
| commit | 9ba069957b1591628ea4d5e2a9ff8553efa52c71 (patch) | |
| tree | 0f370b43773242ce704158c676f964432230cb3b | |
| parent | 0c634159a35ff567fc4897df25dddddd181a1a8c (diff) | |
| download | coreboot-9ba069957b1591628ea4d5e2a9ff8553efa52c71.tar.xz | |
soc/nvidia/tegra132: remove tegra132 support
As no more mainboards are utilizing this SoC support code remove
it. It can be resurrected if ever needed.
BUG=chrome-os-partner:55932
Change-Id: Ic3caf6e6c9b62d012679b996abaa525c8bf679a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16108
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
78 files changed, 0 insertions, 16782 deletions
diff --git a/src/soc/nvidia/tegra132/32bit_reset.S b/src/soc/nvidia/tegra132/32bit_reset.S deleted file mode 100644 index af82eeba3a..0000000000 --- a/src/soc/nvidia/tegra132/32bit_reset.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This code is compiled for both arm64 and arm4, however the code is only - * executed by the armv8 cores coming out of reset. - */ - -#if !defined(__PRE_RAM__) -#define INST .inst -#else -#define INST .word -#endif - -/* - * The Denver cores come up in aarch32 mode. In order to transition to - * 64-bit mode a write to the RMR (reest mangement register) with the - * AA64 bit (0) set while setting RR (reset request bit 1). - */ -.align 6 -.global reset_entry_32bit -reset_entry_32bit: - INST 0xe3a00003 /* mov r0, #3 */ - INST 0xee0c0f50 /* mcr 15, 0, r0, cr12, cr0, {2} */ - INST 0xeafffffe /* b . */ diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig deleted file mode 100644 index b47089268a..0000000000 --- a/src/soc/nvidia/tegra132/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -config SOC_NVIDIA_TEGRA132 - bool - default n - select ARCH_BOOTBLOCK_ARMV4 - select BOOTBLOCK_CUSTOM - select ARCH_VERSTAGE_ARMV4 - select ARCH_ROMSTAGE_ARMV4 - select ARCH_RAMSTAGE_ARMV8_64 - select BOOTBLOCK_CONSOLE - select GIC - select HAVE_MONOTONIC_TIMER - select GENERIC_UDELAY - select HAVE_HARD_RESET - select HAVE_UART_SPECIAL - select GENERIC_GPIO_LIB - select UART_OVERRIDE_REFCLK - -if SOC_NVIDIA_TEGRA132 - -config CHROMEOS - select VBOOT_OPROM_MATTERS - -config MAINBOARD_DO_DSI_INIT - bool "Use dsi graphics interface" - depends on MAINBOARD_DO_NATIVE_VGA_INIT - default n - help - Initialize dsi display - -config MAINBOARD_DO_SOR_INIT - bool "Use dp graphics interface" - depends on MAINBOARD_DO_NATIVE_VGA_INIT - default n - help - Initialize dp display - -config MTS_DIRECTORY - string "Directory where MTS microcode files are located" - default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod" - help - Path to directory where MTS microcode files are located. - -config TRUSTZONE_CARVEOUT_SIZE_MB - hex "Size of Trust Zone region" - default 0x4 - help - Size of Trust Zone area in MiB to reserve in memory map. - -config BOOTROM_SDRAM_INIT - bool "SoC BootROM does SDRAM init with full BCT" - default n - help - Use during Ryu LPDDR3 bringup - -# Default to 700MHz. This value is based on nv bootloader setting. -config PLLX_KHZ - int - default 700000 -endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc deleted file mode 100644 index b48fd3ab90..0000000000 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ /dev/null @@ -1,137 +0,0 @@ -ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132),y) - -bootblock-y += bootblock.c -bootblock-y += bootblock_asm.S -bootblock-y += clock.c -bootblock-y += spi.c -bootblock-y += i2c.c -bootblock-y += dma.c -bootblock-y += monotonic_timer.c -bootblock-y += padconfig.c -bootblock-y += power.c -bootblock-y += funitcfg.c -bootblock-y += reset.c -bootblock-y += ../tegra/gpio.c -bootblock-y += ../tegra/i2c.c -bootblock-y += ../tegra/pingroup.c -bootblock-y += ../tegra/pinmux.c -bootblock-y += ../tegra/apbmisc.c -bootblock-y += ../tegra/usb.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += uart.c -endif - -verstage-y += dma.c -verstage-y += monotonic_timer.c -verstage-y += spi.c -verstage-y += padconfig.c -verstage-y += funitcfg.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c -verstage-y += ../tegra/gpio.c -verstage-y += ../tegra/i2c.c -verstage-y += ../tegra/pinmux.c -verstage-y += clock.c -verstage-y += i2c.c - -romstage-y += 32bit_reset.S -romstage-y += romstage_asm.S -romstage-y += addressmap.c -romstage-y += cbmem.c -romstage-y += ccplex.c -romstage-y += clock.c -romstage-y += cpu.c -romstage-y += reset.c -romstage-y += spi.c -romstage-y += i2c.c -romstage-y += dma.c -romstage-y += monotonic_timer.c -romstage-y += padconfig.c -romstage-y += funitcfg.c -romstage-y += romstage.c -romstage-y += power.c -romstage-y += sdram.c -romstage-y += sdram_lp0.c -romstage-y += ../tegra/gpio.c -romstage-y += ../tegra/i2c.c -romstage-y += ../tegra/pinmux.c -romstage-y += ../tegra/usb.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c - -ramstage-y += 32bit_reset.S -ramstage-y += addressmap.c -ramstage-y += cbmem.c -ramstage-y += cpu.c -ramstage-y += clock.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c -ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c -ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi_dsi.c -ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi.c -ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c -ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c -ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c -ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c - -ramstage-y += soc.c -ramstage-y += spi.c -ramstage-y += i2c.c -ramstage-y += i2c6.c -ramstage-y += power.c -ramstage-y += dma.c -ramstage-y += gic.c -ramstage-y += monotonic_timer.c -ramstage-y += padconfig.c -ramstage-y += funitcfg.c -ramstage-y += reset.c -ramstage-y += ../tegra/apbmisc.c -ramstage-y += ../tegra/gpio.c -ramstage-y += ../tegra/i2c.c -ramstage-y += ../tegra/pinmux.c -ramstage-y += ramstage.c -ramstage-y += mmu_operations.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c -ramstage-y += ../tegra/usb.c -ramstage-y += stage_entry.S - -modules_arm-y += monotonic_timer.c - -CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ -CBOOTIMAGE_OPTS = --soc tegra132 - -# We want to grab the bootblock right before it goes into the image and wrap -# it inside a BCT, but ideally we would do that without making special, one -# use modifications to the main ARM Makefile. We do this in two ways. First, -# we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf -# template rule to turn it into bootblock.raw.bin. This makes sure whatever -# processing is supposed to happen to turn an .elf into a .bin happens. -# -# Second, we add our own rule for creating bootblock.bin from -# bootblock.raw.bin which displaces the template rule. When other rules that -# package up the image pull in bootblock.bin, it will be this wrapped version -# instead of the raw bootblock. - -$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE) - @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" - $(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@ - -BCT_BIN = $(obj)/generated/bct.bin -BCT_WRAPPER = $(obj)/generated/bct.wrapper -MTS_DIR = $(CONFIG_MTS_DIRECTORY) -PREBOOT_MTS_FILE = $(MTS_DIR)/preboot_cr.bin -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) - echo "Version = 1;" > $(BCT_WRAPPER) - echo "Redundancy = 1;" >> $(BCT_WRAPPER) - echo "Bctcopy = 1;" >> $(BCT_WRAPPER) - echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) - echo "MtsPreboot = $(PREBOOT_MTS_FILE),0x4000f000,0x4000f000,Complete;" >> $(BCT_WRAPPER) - echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER) - @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" - $(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@ - -# MTS microcode -MTS_FILE = $(MTS_DIR)/mts_cr.bin -MTS_FILE_CBFS = mts -cbfs-files-y += $(MTS_FILE_CBFS) -$(MTS_FILE_CBFS)-file := $(MTS_FILE) -$(MTS_FILE_CBFS)-type := raw - -endif diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c deleted file mode 100644 index c71c7b2e6a..0000000000 --- a/src/soc/nvidia/tegra132/addressmap.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <arch/io.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/id.h> -#include <soc/mc.h> -#include <soc/sdram.h> -#include <stdlib.h> -#include <symbols.h> - -static uintptr_t tz_base_mib; -static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; - -/* returns total amount of DRAM (in MB) from memory controller registers */ -int sdram_size_mb(void) -{ - struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; - static int total_size = 0; - - if (total_size) - return total_size; - - /* - * This obtains memory size from the External Memory Aperture - * Configuration register. Nvidia confirmed that it is safe to assume - * this value represents the total physical DRAM size. - */ - total_size = (read32(&mc->emem_cfg) >> MC_EMEM_CFG_SIZE_MB_SHIFT) & - MC_EMEM_CFG_SIZE_MB_MASK; - - return total_size; -} - -static void carveout_from_regs(uintptr_t *base_mib, size_t *size_mib, - uint32_t bom, uint32_t bom_hi, uint32_t size) -{ - - /* All size regs of carveouts are in MiB. */ - if (size == 0) - return; - - *size_mib = size; - bom >>= 20; - bom |= bom_hi << (32 - 20); - - *base_mib = bom; -} - -void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib) -{ - *base_mib = 0; - *size_mib = 0; - struct tegra_mc_regs * const mc = (struct tegra_mc_regs *)TEGRA_MC_BASE; - - switch (id) { - case CARVEOUT_TZ: - *base_mib = tz_base_mib; - *size_mib = tz_size_mib; - break; - case CARVEOUT_SEC: - carveout_from_regs(base_mib, size_mib, - read32(&mc->sec_carveout_bom), - read32(&mc->sec_carveout_adr_hi), - read32(&mc->sec_carveout_size_mb)); - break; - case CARVEOUT_MTS: - carveout_from_regs(base_mib, size_mib, - read32(&mc->mts_carveout_bom), - read32(&mc->mts_carveout_adr_hi), - read32(&mc->mts_carveout_size_mb)); - break; - case CARVEOUT_VPR: - carveout_from_regs(base_mib, size_mib, - read32(&mc->video_protect_bom), - read32(&mc->video_protect_bom_adr_hi), - read32(&mc->video_protect_size_mb)); - break; - default: - break; - } -} - -static void memory_in_range(uintptr_t *base_mib, uintptr_t *end_mib, - int ignore_tz) -{ - uintptr_t base; - uintptr_t end; - int i; - - base = (uintptr_t)_dram / MiB; - end = base + sdram_size_mb(); - - /* Requested limits out of range. */ - if (*end_mib <= base || *base_mib >= end) { - *end_mib = *base_mib = 0; - return; - } - - /* Clip region to passed in limits. */ - if (*end_mib < end) - end = *end_mib; - if (*base_mib > base) - base = *base_mib; - - for (i = 0; i < CARVEOUT_NUM; i++) { - uintptr_t carveout_base; - uintptr_t carveout_end; - size_t carveout_size; - - if (i == CARVEOUT_TZ && ignore_tz) - continue; - - carveout_range(i, &carveout_base, &carveout_size); - - if (carveout_size == 0) - continue; - - carveout_end = carveout_base + carveout_size; - - /* Bypass carveouts out of requested range. */ - if (carveout_base >= end || carveout_end <= base) - continue; - - /* - * This is crude, but the assumption is that carveouts live - * at the upper range of physical memory. Therefore, update - * the end address to be equal to the base of the carveout. - */ - end = carveout_base; - } - - *base_mib = base; - *end_mib = end; -} - -void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib) -{ - *base_mib = 0; - *end_mib = 4096; - memory_in_range(base_mib, end_mib, 0); -} - -void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib) -{ - *base_mib = 4096; - *end_mib = ~0UL; - memory_in_range(base_mib, end_mib, 0); -} - -void trustzone_region_init(void) -{ - struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE; - uintptr_t end = 4096; - - /* Already has been initialized. */ - if (tz_size_mib != 0 && tz_base_mib != 0) - return; - - /* - * Get memory layout below 4GiB ignoring the TZ carveout because - * that's the one to initialize. - */ - memory_in_range(&tz_base_mib, &end, 1); - tz_base_mib = end - tz_size_mib; - - /* AVP cannot set the TZ registers proper as it is always non-secure. */ - if (context_avp()) - return; - - /* Set the carveout region. */ - write32(&mc->security_cfg0, tz_base_mib << 20); - write32(&mc->security_cfg1, tz_size_mib); - - /* Enable SMMU translations */ - write32(&mc->smmu_config, MC_SMMU_CONFIG_ENABLE); -} diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c deleted file mode 100644 index 6428441adb..0000000000 --- a/src/soc/nvidia/tegra132/bootblock.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/exception.h> -#include <arch/hlt.h> -#include <bootblock_common.h> -#include <console/console.h> -#include <program_loading.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/nvidia/tegra/apbmisc.h> -#include <soc/power.h> -#include <timestamp.h> - -#define BCT_OFFSET_IN_BIT 0x50 -#define ODMDATA_OFFSET_IN_BCT 0x6A8 -#define TEGRA_SRAM_MAX (TEGRA_SRAM_BASE + TEGRA_SRAM_SIZE) - -static void save_odmdata(void) -{ - struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - uintptr_t bct_offset; - u32 odmdata; - - // pmc.odmdata: [18:19]: console type, [15:17]: UART id. - // TODO(twarren) ODMDATA is stored in the BCT, from bct/odmdata.cfg. - // I use the BCT offset in the BIT in SRAM to locate the BCT, and - // pick up the ODMDATA word at BCT offset 0x6A8. I could use a BCT - // struct header from cbootimage, but it seems like overkill for this. - - bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); - if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { - odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); - write32(&pmc->odmdata, odmdata); - } -} - -void __attribute__((weak)) bootblock_mainboard_early_init(void) -{ - /* Empty default implementation. */ -} - -void main(void) -{ - timestamp_init(0); - timestamp_add_now(TS_START_BOOTBLOCK); - - // enable JTAG at the earliest stage - enable_jtag(); - - clock_early_uart(); - - /* Configure mselect clock. */ - clock_configure_source(mselect, PLLP, 102000); - - /* Enable AVP cache, timer, APB dma, and mselect blocks. */ - clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, - CLK_H_APBDMA, - 0, CLK_V_MSELECT, 0, 0); - - /* Find ODMDATA in IRAM and save it to scratch reg */ - save_odmdata(); - - bootblock_mainboard_early_init(); - - if (CONFIG_BOOTBLOCK_CONSOLE) { - console_init(); - exception_init(); - printk(BIOS_INFO, "T132: Bootblock here\n"); - } - - clock_init(); - - printk(BIOS_INFO, "T132 bootblock: Clock init done\n"); - - pmc_print_rst_status(); - - bootblock_mainboard_init(); - - printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n"); - - run_romstage(); -} diff --git a/src/soc/nvidia/tegra132/bootblock_asm.S b/src/soc/nvidia/tegra132/bootblock_asm.S deleted file mode 100644 index 62554422db..0000000000 --- a/src/soc/nvidia/tegra132/bootblock_asm.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Early initialization code for ARM architecture. - * - * This file is based off of the OMAP3530/ARM Cortex start.S file from Das - * U-Boot, which itself got the file from armboot. - * - * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> - * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> - * Copyright (c) 2013 The Chromium OS Authors - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> - -#include "stack.S" - -ENTRY(_start) - /* - * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data - * aborts may happen early and crash before the abort handlers are - * installed, but at least the problem will show up near the code that - * causes it. - */ - msr cpsr_cxf, #0xdf - - stack_init stack_top=_estack stack_bottom=_stack seed=1 func=main -ENDPROC(_start) diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c deleted file mode 100644 index b7fe6abfce..0000000000 --- a/src/soc/nvidia/tegra132/cbmem.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <soc/addressmap.h> - -void *cbmem_top(void) -{ - static uintptr_t addr; - - if (addr == 0) { - uintptr_t begin_mib; - uintptr_t end_mib; - - memory_in_range_below_4gb(&begin_mib, &end_mib); - /* Make sure we consume everything up to 4GiB. */ - if (end_mib == 4096) - addr = ~(uint32_t)0; - else - addr = end_mib << 20; - } - - return (void *)addr; -} diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c deleted file mode 100644 index 95f91d8f8d..0000000000 --- a/src/soc/nvidia/tegra132/ccplex.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/clk_rst.h> -#include <soc/ccplex.h> -#include <soc/cpu.h> -#include <soc/flow.h> -#include <soc/mc.h> -#include <soc/pmc.h> -#include <soc/power.h> -#include <soc/romstage.h> -#include <string.h> -#include <timer.h> - -#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE) -#define MTS_FILE_NAME "mts" - -static int ccplex_start(void) -{ - struct stopwatch sw; - const long timeout_ms = 1500; - const uint32_t handshake_mask = 1; - const uint32_t cxreset1_mask = 1 << 21; - uint32_t reg; - struct tegra_pmc_regs * const pmc = PMC_REGS; - - /* Set the handshake bit to be knocked down. */ - write32(&pmc->scratch118, handshake_mask); - - /* Assert nCXRSET[1] */ - reg = read32(CLK_RST_REG(rst_cpu_cmplx_set)); - reg |= cxreset1_mask; - write32(CLK_RST_REG(rst_cpu_cmplx_set), reg); - - stopwatch_init_msecs_expire(&sw, timeout_ms); - while (1) { - reg = read32(&pmc->scratch118); - - /* Wait for the bit to be knocked down. */ - if ((reg & handshake_mask) != handshake_mask) - break; - - if (stopwatch_expired(&sw)) { - printk(BIOS_DEBUG, "MTS handshake timeout.\n"); - return -1; - } - } - - printk(BIOS_DEBUG, "MTS handshake took %ld usecs.\n", - stopwatch_duration_usecs(&sw)); - - return 0; -} - -int ccplex_load_mts(void) -{ - ssize_t nread; - struct stopwatch sw; - struct cbfsf mts_file; - struct region_device fh; - - /* - * MTS location is hard coded to this magic address. The hardware will - * take the MTS from this location and place it in the final resting - * place in the carveout region. - */ - void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS; - - stopwatch_init(&sw); - if (cbfs_boot_locate(&mts_file, MTS_FILE_NAME, NULL)) { - printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME); - return -1; - } - - cbfs_file_data(&fh, &mts_file); - - /* Read MTS file into the carveout region. */ - nread = rdev_readat(&fh, mts, 0, region_device_sz(&fh)); - - if (nread != region_device_sz(&fh)) { - printk(BIOS_DEBUG, "MTS bytes read (%zu) != file length(%u)!\n", - nread, region_device_sz(&fh)); - return -1; - } - - printk(BIOS_DEBUG, "MTS: %zu bytes loaded @ %p in %ld usecs.\n", - nread, mts, stopwatch_duration_usecs(&sw)); - - return ccplex_start(); -} - -static void enable_cpu_clocks(void) -{ - clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE | - SET_CLK_ENB_CPULP_ENABLE, 0, 0); -} - -static void enable_cpu_power_partitions(void) -{ - /* Bring up fast cluster, non-CPU, CPU0, and CPU1 partitions. */ - power_ungate_partition(POWER_PARTID_CRAIL); - power_ungate_partition(POWER_PARTID_C0NC); - power_ungate_partition(POWER_PARTID_CE0); - power_ungate_partition(POWER_PARTID_CE1); -} - -static void request_ram_repair(void) -{ - struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE; - const uint32_t req = 1 << 0; - const uint32_t sts = 1 << 1; - uint32_t reg; - struct stopwatch sw; - - printk(BIOS_DEBUG, "Requesting RAM repair.\n"); - - stopwatch_init(&sw); - - /* Perform cluster 0 RAM repair */ - reg = read32(&flow->ram_repair); - reg |= req; - write32(&flow->ram_repair, reg); - while ((read32(&flow->ram_repair) & sts) != sts) - ; - - /* Perform cluster 1 RAM repair */ - reg = read32(&flow->ram_repair_cluster1); - reg |= req; - write32(&flow->ram_repair_cluster1, reg); - while ((read32(&flow->ram_repair_cluster1) & sts) != sts) - ; - - printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n", - stopwatch_duration_usecs(&sw)); -} - -void ccplex_cpu_prepare(void) -{ - enable_cpu_clocks(); - enable_cpu_power_partitions(); - - mainboard_configure_pmc(); - mainboard_enable_vdd_cpu(); - - request_ram_repair(); -} - -static void start_common_clocks(void) -{ - /* Clear fast CPU partition reset. */ - write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU); - - /* Clear reset of L2 and CoreSight components. */ - write32(CLK_RST_REG(rst_cpug_cmplx_clr), - CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); -} - -void ccplex_cpu_start(void *entry_addr) -{ - /* Enable common clocks for the shared resources between the cores. */ - start_common_clocks(); - - start_cpu(0, entry_addr); -} diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h deleted file mode 100644 index ae08636711..0000000000 --- a/src/soc/nvidia/tegra132/chip.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__ -#define __SOC_NVIDIA_TEGRA132_CHIP_H__ -#include <soc/addressmap.h> -#include <stdint.h> -#include <soc/nvidia/tegra/dc.h> - -struct soc_nvidia_tegra132_config { - /* - * panel resolution - * The two parameters below provides dc about panel spec. - */ - u32 xres; /* the width of H display active area */ - u32 yres; /* the height of V display active area */ - u32 framebuffer_bits_per_pixel; - u32 color_depth; /* color format */ - - u64 display_controller; /* dc block base address */ - u32 framebuffer_base; - - /* - * Technically, we can compute this. At the same time, some platforms - * might want to specify a specific size for their own reasons. If it - * is zero the soc code will compute it as - * xres*yres*framebuffer_bits_per_pixel/8 - */ - u32 framebuffer_size; - - /* - * Framebuffer resolution - * The two parameters below provides dc about framebuffer's sdram size. - * When they are not the same as panel resolution, we need to program - * dc's DDA_INCREMENT and some other registers to resize dc output. - */ - u32 display_xres; - u32 display_yres; - - int href_to_sync; /* HSYNC position with respect to line start */ - int hsync_width; /* the width of HSYNC pulses */ - int hback_porch; /* the distance between HSYNC trailing edge to - beginning of H display active area */ - int hfront_porch; /* the distance between end of H display active - area to the leading edge of HSYNC */ - int vref_to_sync; - int vsync_width; - int vback_porch; - int vfront_porch; - int refresh; /* display refresh rate */ - - int pixel_clock; /* dc pixel clock source rate */ - - u32 panel_bits_per_pixel; - - /* dp specific fields */ - struct { - /* pwm to use to set display contrast */ - int pwm; - - /* HPD related timing */ - int vdd_to_hpd_delay_ms; - int hpd_unplug_min_us; - int hpd_plug_min_us; - int hpd_irq_min_us; - - /* The minimum link configuraton settings */ - u32 lane_count; - u32 enhanced_framing; - u32 link_bw; - u32 drive_current; - u32 preemphasis; - u32 postcursor; - } dp; - - int win_opt; - void *dc_data; -}; - -#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c deleted file mode 100644 index be12b856b1..0000000000 --- a/src/soc/nvidia/tegra132/clock.c +++ /dev/null @@ -1,726 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#include <arch/clock.h> -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <stdlib.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/clock.h> -#include <soc/clst_clk.h> -#include <soc/flow.h> -#include <soc/maincpu.h> -#include <soc/pmc.h> -#include <soc/sysctr.h> - -static struct clst_clk_ctlr *clst_clk = (void *)TEGRA_CLUSTER_CLOCK_BASE; -static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; -static struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; -static struct sysctr_regs *sysctr = (void *)TEGRA_SYSCTR0_BASE; - -struct pll_dividers { - u32 n : 10; - u32 m : 8; - u32 p : 4; - u32 cpcon : 4; - u32 lfcon : 4; - u32 : 2; -}; - -/* Some PLLs have more restrictive divider bit lengths or are missing some - * fields. Make sure to use the right struct in the osc_table definition to get - * compile-time checking, but keep the bits aligned with struct pll_dividers so - * they can be used interchangeably at run time. Add new formats as required. */ -struct pllcx_dividers { - u32 n : 8; - u32 : 2; - u32 m : 8; - u32 p : 4; - u32 : 10; -}; -struct pllpad_dividers { - u32 n : 10; - u32 m : 5; - u32 : 3; - u32 p : 3; - u32 : 1; - u32 cpcon : 4; - u32 : 6; -}; -struct pllu_dividers { - u32 n : 10; - u32 m : 5; - u32 : 3; - u32 p : 1; - u32 : 3; - u32 cpcon : 4; - u32 lfcon : 4; - u32 : 2; -}; - -union __attribute__((transparent_union)) pll_fields { - u32 raw; - struct pll_dividers div; - struct pllcx_dividers cx; - struct pllpad_dividers pad; - struct pllu_dividers u; -}; - -/* This table defines the frequency dividers for every PLL to turn the external - * OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h. - * All PLLs have three dividers (n, m and p), with the governing formula for - * the output frequency being CF = (IN / m), VCO = CF * n and OUT = VCO / (2^p). - * All divisor configurations must meet the PLL's constraints for VCO and CF: - * PLLX: 12 MHz < CF < 50 MHz, 700 MHz < VCO < 3000 MHz - * PLLC: 12 MHz < CF < 50 MHz, 600 MHz < VCO < 1400 MHz - * PLLM: 12 MHz < CF < 50 MHz, 400 MHz < VCO < 1066 MHz - * PLLP: 1 MHz < CF < 6 MHz, 200 MHz < VCO < 700 MHz - * PLLD: 1 MHz < CF < 6 MHz, 500 MHz < VCO < 1000 MHz - * PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz - * PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz - * (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */ -struct { - int khz; - struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */ - struct pllcx_dividers pllc; /* target: 600 MHz */ - /* PLLM is set up dynamically by clock_sdram(). */ - /* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */ - struct pllu_dividers pllu; /* target; 960 MHz */ - struct pllcx_dividers plldp; /* target; 270 MHz */ - /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ -} static const osc_table[16] = { - [OSC_FREQ_12]{ - .khz = 12000, - .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, - .pllc = {.n = 50, .m = 1, .p = 0}, - .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, - .plldp = {.n = 90, .m = 1, .p = 3}, - }, - [OSC_FREQ_13]{ - .khz = 13000, - .pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0}, - .pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */ - .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2}, - .plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */ - }, - [OSC_FREQ_16P8]{ - .khz = 16800, - .pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0}, - .pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */ - .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2}, - .plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */ - }, - [OSC_FREQ_19P2]{ - .khz = 19200, - .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, - .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ - .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, - .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ - }, - [OSC_FREQ_26]{ - .khz = 26000, - .pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0}, - .pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */ - .pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2}, - .plldp = {.n = 83, .m = 2, .p = 3}, /* 269.8 MHz */ - }, - /* These oscillators get predivided as PLL inputs... n/m/p divisors for - * 38.4 should always match 19.2, and 48 should always match 12. */ - [OSC_FREQ_38P4]{ - .khz = 38400, - .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, - .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ - .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, - .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ - }, - [OSC_FREQ_48]{ - .khz = 48000, - .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, - .pllc = {.n = 50, .m = 1, .p = 0}, - .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, - .plldp = {.n = 90, .m = 1, .p = 3}, - }, -}; - -/* Get the oscillator frequency, from the corresponding hardware - * configuration field. This is actually a per-soc thing. Avoid the - * temptation to make it common. - */ -static u32 clock_get_osc_bits(void) -{ - return (read32(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; -} - -int clock_get_osc_khz(void) -{ - return osc_table[clock_get_osc_bits()].khz; -} - -int clock_get_pll_input_khz(void) -{ - u32 osc_ctrl = read32(CLK_RST_REG(osc_ctrl)); - u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; - u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; - return osc_table[osc_bits].khz >> pll_ref_div; -} - -void clock_init_arm_generic_timer(void) -{ - uint32_t freq = clock_get_osc_khz() * 1000; - /* Set the cntfrq register. */ - set_cntfrq(freq); - - /* Record the system timer frequency. */ - write32(&sysctr->cntfid0, freq); - /* Enable the system counter. */ - uint32_t cntcr = read32(&sysctr->cntcr); - cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - write32(&sysctr->cntcr, cntcr); -} - -#define SOR0_CLK_SEL0 (1 << 14) -#define SOR0_CLK_SEL1 (1 << 15) - -void sor_clock_stop(void) -{ - /* The Serial Output Resource clock has to be off - * before we start the plldp. Learned the hard way. - * FIXME: this has to be cleaned up a bit more. - * Waiting on some new info from Nvidia. - */ - clrbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1); -} - -void sor_clock_start(void) -{ - /* uses PLLP, has a non-standard bit layout. */ - setbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0); -} - -static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) -{ - u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT | - pll.div.m << PLL_BASE_DIVM_SHIFT | - pll.div.p << PLL_BASE_DIVP_SHIFT; - u32 misc_con = pll.div.cpcon << PLL_MISC_CPCON_SHIFT | - pll.div.lfcon << PLL_MISC_LFCON_SHIFT; - - /* Write dividers but BYPASS the PLL while we're messing with it. */ - write32(base, dividers | PLL_BASE_BYPASS); - /* - * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't - * exist for this PLL) - */ - write32(misc, lock | misc_con); - - /* Enable PLL and take it back out of BYPASS */ - write32(base, dividers | PLL_BASE_ENABLE); - - /* Wait for lock ready */ - while (!(read32(base) & PLL_BASE_LOCK)); -} - -static void init_utmip_pll(void) -{ - int khz = clock_get_pll_input_khz(); - - /* Shut off PLL crystal clock while we mess with it */ - clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ - udelay(1); - - write32(CLK_RST_REG(utmip_pll_cfg0), /* 960MHz * 1 / 80 == 12 MHz */ - 80 << 16 | /* (rst) phy_divn */ - 1 << 8); /* (rst) phy_divm */ - - write32(CLK_RST_REG(utmip_pll_cfg1), - div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ - 0 << 16 | /* PLLU pwrdn */ - 0 << 14 | /* pll_enable pwrdn */ - 0 << 12 | /* pll_active pwrdn */ - div_round_up(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ - - /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - write32(CLK_RST_REG(utmip_pll_cfg2), - 0 << 24 | /* SAMP_D/XDEV pwrdn */ - div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ - div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ - 0 << 4 | /* SAMP_C/USB3 pwrdn */ - 0 << 2 | /* SAMP_B/XHOST pwrdn */ - 0 << 0); /* SAMP_A/USBD pwrdn */ - - setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ -} - -/* Graphics just has to be different. There's a few more bits we - * need to set in here, but it makes sense just to restrict all the - * special bits to this one function. - */ -static void graphics_pll(void) -{ - int osc = clock_get_osc_bits(); - u32 *cfg = CLK_RST_REG(plldp_ss_cfg); - /* the vendor code sets the dither bit (28) - * an undocumented bit (24) - * and clamp while we mess with it (22) - * Dither is pretty important to display port - * so we really do need to handle these bits. - * I'm not willing to not clamp it, even if - * it might "mostly work" with it not set, - * I don't want to find out in a few months - * that it is needed. - */ - u32 scfg = (1 << 28) | (1 << 24) | (1 << 22); - write32(cfg, scfg); - init_pll(CLK_RST_REG(plldp_base), CLK_RST_REG(plldp_misc), - osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); - /* leave dither and undoc bits set, release clamp */ - scfg = (1<<28) | (1<<24); - write32(cfg, scfg); -} - -/* - * Init PLLD clock source. - * - * @frequency: the requested plld frequency - * - * Return the plld frequency if success, otherwise return 0. - */ -u32 clock_configure_plld(u32 frequency) -{ - /** - * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz - * = (cf * n) >> p, where 1MHz < cf < 6MHz - * = ((ref / m) * n) >> p - * - * Iterate the possible values of p (3 bits, 2^7) to find out a minimum - * safe vco, then find best (m, n). since m has only 5 bits, we can - * iterate all possible values. Note Tegra 124 supports 11 bits for n, - * but our pll_fields has only 10 bits for n. - * - * Note, values that undershoot or overshoot the target output frequency - * may not work if the values are not in "safe" range by panel - * specification. - */ - struct pllpad_dividers plld = { 0 }; - u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0; - u32 cf, vco, rounded_rate = frequency; - u32 diff, best_diff; - const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, - mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, - min_cf = 1 * mhz, max_cf = 6 * mhz; - - for (vco = frequency; vco < min_vco && p < max_p; p++) - vco <<= 1; - - if (vco < min_vco || vco > max_vco) { - printk(BIOS_ERR, "%s: Cannot find out a supported VCO" - " for Frequency (%u).\n", __func__, frequency); - return 0; - } - - plld.p = p; - best_diff = vco; - - for (m = 1; m < max_m && best_diff; m++) { - cf = ref / m; - if (cf < min_cf) - break; - if (cf > max_cf) - continue; - - n = vco / cf; - if (n >= max_n) - continue; - - diff = vco - n * cf; - if (n + 1 < max_n && diff > cf / 2) { - n++; - diff = cf - diff; - } - - if (diff >= best_diff) - continue; - - best_diff = diff; - plld.m = m; - plld.n = n; - } - - if (plld.n < 50) - plld.cpcon = 2; - else if (plld.n < 300) - plld.cpcon = 3; - else if (plld.n < 600) - plld.cpcon = 8; - else - plld.cpcon = 12; - - if (best_diff) { - printk(BIOS_WARNING, "%s: Failed to match output frequency %u, " - "best difference is %u.\n", __func__, frequency, - best_diff); - rounded_rate = (ref / plld.m * plld.n) >> plld.p; - } - - printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", - __func__, rounded_rate, ref, plld.m, plld.n, plld.p, plld.cpcon); - - init_pll(CLK_RST_REG(plld_base), CLK_RST_REG(plld_misc), plld, - (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE)); - - if (rounded_rate != frequency) - printk(BIOS_DEBUG, "PLLD rate: %u vs %u\n", rounded_rate, - frequency); - - return rounded_rate; -} - -/* Initialize the UART and put it on CLK_M so we can use it during clock_init(). - * Will later move it to PLLP in clock_config(). The divisor must be very small - * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 - * CLK_SOURCE divider to get more precision. (This might still not be enough for - * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has - * been determined through trial and error (must lead to div 13 at 24MHz). */ -void clock_early_uart(void) -{ - write32(CLK_RST_REG(clk_src_uarta), - CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | - CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); - - clock_enable_clear_reset_l(CLK_L_UARTA); -} - -/* Enable output clock (CLK1~3) for external peripherals. */ -void clock_external_output(int clk_id) -{ - switch (clk_id) { - case 1: - setbits_le32(&pmc->clk_out_cntrl, 1 << 2); - break; - case 2: - setbits_le32(&pmc->clk_out_cntrl, 1 << 10); - break; - case 3: - setbits_le32(&pmc->clk_out_cntrl, 1 << 18); - break; - default: - printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", - clk_id); - break; - } -} - -/* Start PLLM for SDRAM. */ -void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, - u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, - u32 same_freq) -{ - u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) | - (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) | - (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) | - (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)); - u32 misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) | - (kcp << PLLM_MISC2_KCP_SHIFT)); - u32 base; - - if (same_freq) - emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; - else - emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; - - /* - * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and - * PLLM_BASE.ENABLE must be in DISABLE state (both are the default - * values after coldboot reset). - */ - - write32(CLK_RST_REG(pllm_misc1), misc1); - write32(CLK_RST_REG(pllm_misc2), misc2); - - /* PLLM.BASE needs BYPASS=0, different from general init_pll */ - base = read32(CLK_RST_REG(pllm_base)); - base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | - PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); - base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | - (p << PLL_BASE_DIVP_SHIFT)); - write32(CLK_RST_REG(pllm_base), base); - - setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); - /* stable_time is required, before we can start to check lock. */ - udelay(stable_time); - - while (!(read32(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK)) - udelay(1); - - /* - * After PLLM reports being locked, we have to delay 10us before - * enabling PLLM_OUT. - */ - udelay(10); - - /* Put OUT1 out of reset state (start to output). */ - setbits_le32(CLK_RST_REG(pllm_out), PLLM_OUT1_RSTN_RESET_DISABLE); - - /* Enable and start MEM(MC) and EMC. */ - clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); - write32(CLK_RST_REG(clk_src_emc), emc_source); - udelay(IO_STABILIZATION_DELAY); -} - -void clock_cpu0_config(void) -{ - u32 reg; - u32 osc = clock_get_osc_bits(); - u32 timeout = 0; - - /* disable IDDQ */ - reg = read32(&clst_clk->pllx_misc3); - reg &= ~PLLX_IDDQ; - write32(&clst_clk->pllx_misc3, reg); - - /* init pllx */ - init_pll(&clst_clk->pllx_base, &clst_clk->pllx_misc, - osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE); - - /* - * Change CPU clock source to PLLX_OUT0_LJ - * when above pllx programming has taken effect. - */ - do { - if (read32(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) { - write32(&clst_clk->cclk_brst_pol, - (CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28)); - break; - } - - /* wait and try again */ - if (timeout >= CLK_SWITCH_TIMEOUT_US) { - printk(BIOS_ERR, "%s: PLLX programming timeout. " - "Switching CPU clock has falied.\n", - __func__); - break; - } - udelay(10); - timeout += 10; - - } while (1); -} - -void clock_halt_avp(void) -{ - for (;;) - write32(&flow->halt_cop_events, - FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | - FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); -} - -void clock_init(void) -{ - u32 osc = clock_get_osc_bits(); - - /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ - write32(CLK_RST_REG(pllc_misc2), 0x2b << 17 | 0xb << 9); - - /* Max out the AVP clock before everything else (need PLLC for that). */ - init_pll(CLK_RST_REG(pllc_base), CLK_RST_REG(pllc_misc), - osc_table[osc].pllc, PLLC_MISC_LOCK_ENABLE); - - /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA - * features section in the TRM). */ - write32(CLK_RST_REG(clk_sys_rate), /* pclk = hclk = sclk/2 */ - 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); - write32(CLK_RST_REG(pllc_out), - CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_CLKEN | PLL_OUT_RSTN); - write32(CLK_RST_REG(sclk_brst_pol), /* sclk = 300 MHz */ - SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | - SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); - - /* Change the oscillator drive strength (from U-Boot -- why?) */ - clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, - OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); - - /* - * Ambiguous quote from u-boot. TODO: what's this mean? - * "should update same value in PMC_OSC_EDPD_OVER XOFS - * field for warmboot " - */ - clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, - OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); - - /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - write32(CLK_RST_REG(pllp_outa), - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); - write32(CLK_RST_REG(pllp_outb), - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); - - /* init pllu */ - init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc), - osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE); - - init_utmip_pll(); - graphics_pll(); -} - -void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, - u32 *rst_dev_clr_reg) -{ - write32(clk_enb_set_reg, val); - udelay(IO_STABILIZATION_DELAY); - write32(rst_dev_clr_reg, val); -} - -static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { - CLK_RST_REG(clk_enb_l_set), - CLK_RST_REG(clk_enb_h_set), - CLK_RST_REG(clk_enb_u_set), - CLK_RST_REG(clk_enb_v_set), - CLK_RST_REG(clk_enb_w_set), - CLK_RST_REG(clk_enb_x_set), -}; - -static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = { - CLK_RST_REG(clk_enb_l_clr), - CLK_RST_REG(clk_enb_h_clr), - CLK_RST_REG(clk_enb_u_clr), - CLK_RST_REG(clk_enb_v_clr), - CLK_RST_REG(clk_enb_w_clr), - CLK_RST_REG(clk_enb_x_clr), -}; - -static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = { - CLK_RST_REG(rst_dev_l_set), - CLK_RST_REG(rst_dev_h_set), - CLK_RST_REG(rst_dev_u_set), - CLK_RST_REG(rst_dev_v_set), - CLK_RST_REG(rst_dev_w_set), - CLK_RST_REG(rst_dev_x_set), -}; - -static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = { - CLK_RST_REG(rst_dev_l_clr), - CLK_RST_REG(rst_dev_h_clr), - CLK_RST_REG(rst_dev_u_clr), - CLK_RST_REG(rst_dev_v_clr), - CLK_RST_REG(rst_dev_w_clr), - CLK_RST_REG(rst_dev_x_clr), -}; - -static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS], - u32 bits[DEV_CONFIG_BLOCKS]) -{ - int i = 0; - - for (; i < DEV_CONFIG_BLOCKS; i++) - if (bits[i]) - write32(regs[i], bits[i]); -} - -void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]) -{ - clock_write_regs(clk_enb_set_arr, bits); -} - -void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]) -{ - clock_write_regs(clk_enb_clr_arr, bits); -} - -void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]) -{ - clock_write_regs(rst_dev_set_arr, bits); -} - -void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]) -{ - clock_write_regs(rst_dev_clr_arr, bits); -} - -void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) -{ - clock_enable(l, h, u, v, w, x); - - /* Give clocks time to stabilize. */ - udelay(IO_STABILIZATION_DELAY); - - clock_clr_reset(l, h, u, v, w, x); -} - -static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit) -{ - write32(setaddr, bit); - udelay(LOGIC_STABILIZATION_DELAY); - write32(clraddr, bit); -} - -void clock_reset_l(u32 bit) -{ - clock_reset_dev(CLK_RST_REG(rst_dev_l_set), CLK_RST_REG(rst_dev_l_clr), - bit); -} - -void clock_reset_h(u32 bit) -{ - clock_reset_dev(CLK_RST_REG(rst_dev_h_set), CLK_RST_REG(rst_dev_h_clr), - bit); -} - -void clock_reset_u(u32 bit) -{ - clock_reset_dev(CLK_RST_REG(rst_dev_u_set), CLK_RST_REG(rst_dev_u_clr), - bit); -} - -void clock_reset_v(u32 bit) -{ - clock_reset_dev(CLK_RST_REG(rst_dev_v_set), CLK_RST_REG(rst_dev_v_clr), - bit); -} - -void clock_reset_w(u32 bit) -{ - clock_reset_dev(CLK_RST_REG(rst_dev_w_set), CLK_RST_REG(rst_dev_w_clr), - bit); -} - -void clock_reset_x(u32 bit) -{ - clock_reset_dev(CLK_RST_REG(rst_dev_x_set), CLK_RST_REG(rst_dev_x_clr), - bit); -} - -/* Enable/unreset all audio toys under AHUB */ -void clock_enable_audio(void) -{ - /* - * Confirmed by NVIDIA hardware team, we need to take ALL audio devices - * connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out - * of reset and clock-enabled, otherwise reading AHUB devices (in our - * case, I2S/APBIF/AUDIO<XBAR>) will hang. - */ - clock_enable_clear_reset(CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | CLK_L_SPDIF, - 0, 0, - CLK_V_I2S3 | CLK_V_I2S4 | CLK_V_AUDIO | CLK_V_APBIF | - CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2 | CLK_V_EXTPERIPH1, - CLK_W_AMX0 | CLK_W_ADX0, - CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 | CLK_X_AFC2 | - CLK_X_AFC3 | CLK_X_AFC4 | CLK_X_AFC5 | CLK_X_AMX1); -} diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c deleted file mode 100644 index 142e3a45f2..0000000000 --- a/src/soc/nvidia/tegra132/cpu.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/cpu.h> -#include <soc/pmc.h> - -#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100) -#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE) - -static void enable_core_clocks(int cpu) -{ - const uint32_t cpu0_clocks = CRC_RST_CPUG_CLR_CPU0 | - CRC_RST_CPUG_CLR_DBG0 | - CRC_RST_CPUG_CLR_CORE0 | - CRC_RST_CPUG_CLR_CX0; - const uint32_t cpu1_clocks = CRC_RST_CPUG_CLR_CPU1 | - CRC_RST_CPUG_CLR_DBG1 | - CRC_RST_CPUG_CLR_CORE1 | - CRC_RST_CPUG_CLR_CX1; - - /* Clear reset of CPU components. */ - if (cpu == 0) - write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu0_clocks); - else - write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu1_clocks); -} - -static void set_armv8_32bit_reset_vector(uintptr_t entry) -{ - void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR; - write32(evp_cpu_reset_vector, entry); -} - -static void set_armv8_64bit_reset_vector(uintptr_t entry) -{ - struct tegra_pmc_regs * const pmc = PMC_REGS; - - /* Currently assume 32-bit addresses only. */ - write32(&pmc->secure_scratch34, entry); - write32(&pmc->secure_scratch35, 0); -} - -void cpu_prepare_startup(void *entry_64) -{ - /* Warm reset vector is pulled from the PMC scratch registers. */ - set_armv8_64bit_reset_vector((uintptr_t)entry_64); - - /* - * The Denver cores start in 32-bit mode. Therefore a trampoline - * is needed to get into 64-bit mode. Point the cold reset vector - * to the traompoline location. - */ - set_armv8_32bit_reset_vector((uintptr_t)reset_entry_32bit); -} - -void start_cpu_silent(int cpu, void *entry_64) -{ - cpu_prepare_startup(entry_64); - enable_core_clocks(cpu); -} - -void start_cpu(int cpu, void *entry_64) -{ - printk(BIOS_DEBUG, "Starting CPU%d @ %p trampolining to %p.\n", - cpu, reset_entry_32bit, entry_64); - - start_cpu_silent(cpu, entry_64); -} diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c deleted file mode 100644 index 354eb7d25c..0000000000 --- a/src/soc/nvidia/tegra132/dc.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <stdlib.h> -#include <edid.h> -#include <device/device.h> -#include <soc/nvidia/tegra/dc.h> -#include "chip.h" -#include <soc/display.h> - -int dump = 0; -unsigned long READL(void * p) -{ - unsigned long value; - - /* - * In case of hard hung on readl(p), we can set dump > 1 to print out - * the address accessed. - */ - if (dump > 1) - printk(BIOS_SPEW, "readl %p\n", p); - - value = read32(p); - if (dump) - printk(BIOS_SPEW, "readl %p %08lx\n", p, value); - return value; -} - -void WRITEL(unsigned long value, void * p) -{ - if (dump) - printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - write32(p, value); -} - -/* return in 1000ths of a Hertz */ -static int tegra_calc_refresh(const struct soc_nvidia_tegra132_config *config) -{ - int refresh; - int h_total = htotal(config); - int v_total = vtotal(config); - int pclk = config->pixel_clock; - - if (!pclk || !h_total || !v_total) - return 0; - refresh = pclk / h_total; - refresh *= 1000; - refresh /= v_total; - return refresh; -} - -static void print_mode(const struct soc_nvidia_tegra132_config *config) -{ - if (config) { - int refresh = tegra_calc_refresh(config); - printk(BIOS_ERR, - "Panel Mode: %dx%d@%d.%03uHz pclk=%d\n", - config->xres, config->yres, - refresh / 1000, refresh % 1000, - config->pixel_clock); - } -} - -int update_display_mode(struct display_controller *disp_ctrl, - struct soc_nvidia_tegra132_config *config) -{ - print_mode(config); - - printk(BIOS_ERR, "config: xres:yres: %d x %d\n ", - config->xres, config->yres); - printk(BIOS_ERR, " href_sync:vref_sync: %d x %d\n ", - config->href_to_sync, config->vref_to_sync); - printk(BIOS_ERR, " hsyn_width:vsyn_width: %d x %d\n ", - config->hsync_width, config->vsync_width); - printk(BIOS_ERR, " hfnt_porch:vfnt_porch: %d x %d\n ", - config->hfront_porch, config->vfront_porch); - printk(BIOS_ERR, " hbk_porch:vbk_porch: %d x %d\n ", - config->hback_porch, config->vback_porch); - - WRITEL(0x0, &disp_ctrl->disp.disp_timing_opt); - WRITEL(0x0, &disp_ctrl->disp.disp_color_ctrl); - - /* select win opt */ - WRITEL(config->win_opt, &disp_ctrl->disp.disp_win_opt); - - WRITEL(config->vref_to_sync << 16 | config->href_to_sync, - &disp_ctrl->disp.ref_to_sync); - - WRITEL(config->vsync_width << 16 | config->hsync_width, - &disp_ctrl->disp.sync_width); - - - WRITEL((config->vback_porch << 16) | config->hback_porch, - &disp_ctrl->disp.back_porch); - - WRITEL((config->vfront_porch << 16) | config->hfront_porch, - &disp_ctrl->disp.front_porch); - - WRITEL(config->xres | (config->yres << 16), - &disp_ctrl->disp.disp_active); - - /* - * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. - * - * default: Set both shift_clk_div and pixel_clock_div to 1 - */ - update_display_shift_clock_divider(disp_ctrl, SHIFT_CLK_DIVIDER(1)); - - return 0; -} - -void update_display_shift_clock_divider(struct display_controller *disp_ctrl, - u32 shift_clock_div) -{ - WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | - (shift_clock_div & 0xff) << SHIFT_CLK_DIVIDER_SHIFT, - &disp_ctrl->disp.disp_clk_ctrl); - printk(BIOS_DEBUG, "%s: ShiftClockDiv=%u\n", - __func__, shift_clock_div); -} - -/* - * update_window: - * set up window registers and activate window except two: - * frame buffer base address register (WINBUF_START_ADDR) and - * display enable register (_DISP_DISP_WIN_OPTIONS). This is - * because framebuffer is not available until payload stage. - */ -void update_window(const struct soc_nvidia_tegra132_config *config) -{ - struct display_controller *disp_ctrl = - (void *)config->display_controller; - u32 val; - - WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); - - WRITEL(((config->yres << 16) | config->xres), &disp_ctrl->win.size); - - WRITEL(((config->display_yres << 16) | - (config->display_xres * - config->framebuffer_bits_per_pixel / 8)), - &disp_ctrl->win.prescaled_size); - - val = ALIGN_UP((config->display_xres * - config->framebuffer_bits_per_pixel / 8), 64); - WRITEL(val, &disp_ctrl->win.line_stride); - - WRITEL(config->color_depth, &disp_ctrl->win.color_depth); - WRITEL(COLOR_BLACK, &disp_ctrl->disp.blend_background_color); - - WRITEL(((DDA_INC(config->display_yres, config->yres) << 16) | - DDA_INC(config->display_xres, config->xres)), - &disp_ctrl->win.dda_increment); - - WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); - - WRITEL(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); - - WRITEL(0, &disp_ctrl->win.buffer_addr_mode); - - val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; - WRITEL(val, &disp_ctrl->cmd.disp_pow_ctrl); - - val = GENERAL_UPDATE | WIN_A_UPDATE; - WRITEL(val, &disp_ctrl->cmd.state_ctrl); - - val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; - WRITEL(val, &disp_ctrl->cmd.state_ctrl); -} - -int tegra_dc_init(struct display_controller *disp_ctrl) -{ - /* do not accept interrupts during initialization */ - WRITEL(0x00000000, &disp_ctrl->cmd.int_mask); - WRITEL(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, - &disp_ctrl->cmd.state_access); - WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); - WRITEL(0x00000000, &disp_ctrl->win.win_opt); - WRITEL(0x00000000, &disp_ctrl->win.byte_swap); - WRITEL(0x00000000, &disp_ctrl->win.buffer_ctrl); - - WRITEL(0x00000000, &disp_ctrl->win.pos); - WRITEL(0x00000000, &disp_ctrl->win.h_initial_dda); - WRITEL(0x00000000, &disp_ctrl->win.v_initial_dda); - WRITEL(0x00000000, &disp_ctrl->win.dda_increment); - WRITEL(0x00000000, &disp_ctrl->win.dv_ctrl); - - WRITEL(0x01000000, &disp_ctrl->win.blend_layer_ctrl); - WRITEL(0x00000000, &disp_ctrl->win.blend_match_select); - WRITEL(0x00000000, &disp_ctrl->win.blend_nomatch_select); - WRITEL(0x00000000, &disp_ctrl->win.blend_alpha_1bit); - - WRITEL(0x00000000, &disp_ctrl->winbuf.start_addr_hi); - WRITEL(0x00000000, &disp_ctrl->winbuf.addr_h_offset); - WRITEL(0x00000000, &disp_ctrl->winbuf.addr_v_offset); - - WRITEL(0x00000000, &disp_ctrl->com.crc_checksum); - WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[0]); - WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[1]); - WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[2]); - WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[3]); - WRITEL(0x00000000, &disp_ctrl->disp.disp_signal_opt0); - - return 0; -} - -/* - * Save mode to cb tables - */ -void pass_mode_info_to_payload( - struct soc_nvidia_tegra132_config *config) -{ - struct edid edid; - - edid.mode.va = config->display_yres; - edid.mode.ha = config->display_xres; - edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel, 64); - - printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " - " x_res x y_res: %d x %d, size: %d\n", - __func__, edid.bytes_per_line, - edid.framebuffer_bits_per_pixel, - edid.x_resolution, edid.y_resolution, - (edid.bytes_per_line * edid.y_resolution)); - - set_vbe_mode_info_valid(&edid, 0); -} diff --git a/src/soc/nvidia/tegra132/dma.c b/src/soc/nvidia/tegra132/dma.c deleted file mode 100644 index 7dfe92c896..0000000000 --- a/src/soc/nvidia/tegra132/dma.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <inttypes.h> -#include <soc/addressmap.h> -#include <soc/dma.h> -#include <stddef.h> -#include <stdlib.h> - -struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; - -#define APB_DMA_OFFSET(n) \ - (struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n) -struct apb_dma_channel apb_dma_channels[] = { - { .num = 0, .regs = APB_DMA_OFFSET(0x1000) }, - { .num = 1, .regs = APB_DMA_OFFSET(0x1040) }, - { .num = 2, .regs = APB_DMA_OFFSET(0x1080) }, - { .num = 3, .regs = APB_DMA_OFFSET(0x10c0) }, - { .num = 4, .regs = APB_DMA_OFFSET(0x1100) }, - { .num = 5, .regs = APB_DMA_OFFSET(0x1140) }, - { .num = 6, .regs = APB_DMA_OFFSET(0x1180) }, - { .num = 7, .regs = APB_DMA_OFFSET(0x11c0) }, - { .num = 8, .regs = APB_DMA_OFFSET(0x1200) }, - { .num = 9, .regs = APB_DMA_OFFSET(0x1240) }, - { .num = 10, .regs = APB_DMA_OFFSET(0x1280) }, - { .num = 11, .regs = APB_DMA_OFFSET(0x12c0) }, - { .num = 12, .regs = APB_DMA_OFFSET(0x1300) }, - { .num = 13, .regs = APB_DMA_OFFSET(0x1340) }, - { .num = 14, .regs = APB_DMA_OFFSET(0x1380) }, - { .num = 15, .regs = APB_DMA_OFFSET(0x13c0) }, - { .num = 16, .regs = APB_DMA_OFFSET(0x1400) }, - { .num = 17, .regs = APB_DMA_OFFSET(0x1440) }, - { .num = 18, .regs = APB_DMA_OFFSET(0x1480) }, - { .num = 19, .regs = APB_DMA_OFFSET(0x14c0) }, - { .num = 20, .regs = APB_DMA_OFFSET(0x1500) }, - { .num = 21, .regs = APB_DMA_OFFSET(0x1540) }, - { .num = 22, .regs = APB_DMA_OFFSET(0x1580) }, - { .num = 23, .regs = APB_DMA_OFFSET(0x15c0) }, - { .num = 24, .regs = APB_DMA_OFFSET(0x1600) }, - { .num = 25, .regs = APB_DMA_OFFSET(0x1640) }, - { .num = 26, .regs = APB_DMA_OFFSET(0x1680) }, - { .num = 27, .regs = APB_DMA_OFFSET(0x16c0) }, - { .num = 28, .regs = APB_DMA_OFFSET(0x1700) }, - { .num = 29, .regs = APB_DMA_OFFSET(0x1740) }, - { .num = 30, .regs = APB_DMA_OFFSET(0x1780) }, - { .num = 31, .regs = APB_DMA_OFFSET(0x17c0) }, -}; - -int dma_busy(struct apb_dma_channel * const channel) -{ - /* - * In continuous mode, the BSY_n bit in APB_DMA_STATUS and - * BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long - * as the channel is enabled. So for this function we'll use the - * DMA_ACTIVITY bit in case of continuous mode. - * - * However, for ONCE mode, the BSY_n bit in APB_DMA_STATUS will be used - * to determine end of dma operation. - */ - uint32_t bit; - - if (read32(&channel->regs->csr) & APB_CSR_ONCE) - /* Once mode */ - bit = APB_STA_BSY; - else - /* Continuous mode */ - bit = APB_STA_DMA_ACTIVITY; - - return read32(&channel->regs->sta) & bit ? 1 : 0; -} -/* claim a DMA channel */ -struct apb_dma_channel * const dma_claim(void) -{ - int i; - struct apb_dma_channel_regs *regs = NULL; - - /* - * Set global enable bit, otherwise register access to channel - * DMA registers will not be possible. - */ - setbits_le32(&apb_dma->command, APB_COMMAND_GEN); - - for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { - regs = apb_dma_channels[i].regs; - - if (!apb_dma_channels[i].in_use) { - u32 status = read32(®s->sta); - if (status & (1 << i)) { - /* FIXME: should this be fatal? */ - printk(BIOS_DEBUG, "%s: DMA channel %d busy?\n", - __func__, i); - } - break; - } - } - - if (i == ARRAY_SIZE(apb_dma_channels)) - return NULL; - - apb_dma_channels[i].in_use = 1; - return &apb_dma_channels[i]; -} - -/* release a DMA channel */ -void dma_release(struct apb_dma_channel * const channel) -{ - int i; - - /* FIXME: make this "thread" friendly */ - while (dma_busy(channel)) - ; - - channel->in_use = 0; - - /* clear the global enable bit if no channels are in use */ - for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { - if (apb_dma_channels[i].in_use) - return; - } - - clrbits_le32(&apb_dma->command, APB_COMMAND_GEN); -} - -int dma_start(struct apb_dma_channel * const channel) -{ - struct apb_dma_channel_regs *regs = channel->regs; - - /* Set ENB bit for this channel */ - setbits_le32(®s->csr, APB_CSR_ENB); - - return 0; -} - -int dma_stop(struct apb_dma_channel * const channel) -{ - struct apb_dma_channel_regs *regs = channel->regs; - - /* Clear ENB bit for this channel */ - clrbits_le32(®s->csr, APB_CSR_ENB); - - return 0; -} diff --git a/src/soc/nvidia/tegra132/dp.c b/src/soc/nvidia/tegra132/dp.c deleted file mode 100644 index 17118e398a..0000000000 --- a/src/soc/nvidia/tegra132/dp.c +++ /dev/null @@ -1,1663 +0,0 @@ -/* - * drivers/video/tegra/dc/dp.c - * - * Copyright (c) 2011-2015, NVIDIA Corporation. - * Copyright 2014 Google Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/i2c.h> -#include <edid.h> -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/display.h> -#include <soc/nvidia/tegra/i2c.h> -#include <soc/nvidia/tegra/dc.h> -#include <soc/nvidia/tegra/types.h> -#include <soc/nvidia/tegra/pwm.h> -#include <soc/nvidia/tegra/displayport.h> -#include <soc/sor.h> -#include "chip.h" - -#define DO_FAST_LINK_TRAINING 0 - -struct tegra_dc dc_data; - -enum { - DP_LT_SUCCESS = 0, - DP_LT_FAILED = -1, -}; - -struct tegra_dc_dp_data dp_data; - -static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) -{ - void *addr = dp->aux_base + (u32) (reg << 2); - u32 reg_val = READL(addr); - return reg_val; -} - -static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, - u32 reg, u32 val) -{ - void *addr = dp->aux_base + (u32) (reg << 2); - WRITEL(val, addr); -} - -static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp, - u32 reg, u32 mask, u32 exp_val, - u32 poll_interval_us, - u32 timeout_us) -{ - u32 reg_val = 0; - u32 temp = timeout_us; - - do { - udelay(poll_interval_us); - reg_val = tegra_dpaux_readl(dp, reg); - if (timeout_us > poll_interval_us) - timeout_us -= poll_interval_us; - else - break; - } while ((reg_val & mask) != exp_val); - - if ((reg_val & mask) == exp_val) - return 0; /* success */ - printk(BIOS_ERR, - "dpaux_poll_register 0x%x: timeout: " - "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", - reg, reg_val, mask, exp_val); - return temp; -} - -static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) -{ - /* According to DP spec, each aux transaction needs to finish - within 40ms. */ - if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, - DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, - DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, - 100, DP_AUX_TIMEOUT_MS * 1000) != 0) { - printk(BIOS_INFO, "dp: DPAUX transaction timeout\n"); - return -1; - } - return 0; -} - -static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 *data, u32 *size, - u32 *aux_stat) -{ - int i; - u32 reg_val; - u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; - u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; - u32 temp_data; - - if (*size > DP_AUX_MAX_BYTES) - return -1; /* only write one chunk of data */ - - /* Make sure the command is write command */ - switch (cmd) { - case DPAUX_DP_AUXCTL_CMD_I2CWR: - case DPAUX_DP_AUXCTL_CMD_MOTWR: - case DPAUX_DP_AUXCTL_CMD_AUXWR: - break; - default: - printk(BIOS_ERR, "dp: aux write cmd 0x%x is invalid\n", cmd); - return -1; - } - - tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); - for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) { - memcpy(&temp_data, data, 4); - tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data); - data += 4; - } - - reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); - reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; - reg_val |= cmd; - reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; - reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); - - while ((timeout_retries > 0) && (defer_retries > 0)) { - if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || - (defer_retries != DP_AUX_DEFER_MAX_TRIES)) - udelay(1); - - reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; - tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); - - if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_ERR, "dp: aux write transaction timeout\n"); - - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - - if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { - if (timeout_retries-- > 0) { - printk(BIOS_INFO, "dp: aux write retry (0x%x)" - " -- %d\n", - *aux_stat, timeout_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; - } else { - printk(BIOS_ERR, "dp: aux write got error" - " (0x%x)\n", *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || - (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { - if (defer_retries-- > 0) { - printk(BIOS_INFO, "dp: aux write defer (0x%x)" - " -- %d\n", *aux_stat, defer_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; - } else { - printk(BIOS_ERR, "dp: aux write defer exceeds" - " max retries (0x%x)\n", *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == - DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { - *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); - return 0; - } else { - printk(BIOS_ERR, "dp: aux write failed (0x%x)\n", - *aux_stat); - return -1; - } - } - /* Should never come to here */ - return -1; -} - -static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, - u32 addr, u8 *data, u32 *size, - u32 *aux_stat) -{ - u32 reg_val; - u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; - u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; - - if (*size > DP_AUX_MAX_BYTES) - return -1; /* only read one chunk */ - - /* Check to make sure the command is read command */ - switch (cmd) { - case DPAUX_DP_AUXCTL_CMD_I2CRD: - case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT: - case DPAUX_DP_AUXCTL_CMD_MOTRD: - case DPAUX_DP_AUXCTL_CMD_AUXRD: - break; - default: - printk(BIOS_ERR, "dp: aux read cmd 0x%x is invalid\n", cmd); - return -1; - } - - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_SPEW, "dp: HPD is not detected\n"); - return -1; - } - - tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); - - reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); - reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; - reg_val |= cmd; - reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; - reg_val |= ((*size - 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); - while ((timeout_retries > 0) && (defer_retries > 0)) { - if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || - (defer_retries != DP_AUX_DEFER_MAX_TRIES)) - udelay(DP_DPCP_RETRY_SLEEP_NS * 2); - - reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; - tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); - - if (tegra_dpaux_wait_transaction(dp)) - printk(BIOS_INFO, "dp: aux read transaction timeout\n"); - - *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - - if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || - (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { - if (timeout_retries-- > 0) { - printk(BIOS_INFO, "dp: aux read retry (0x%x)" - " -- %d\n", *aux_stat, - timeout_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; /* retry */ - } else { - printk(BIOS_ERR, "dp: aux read got error" - " (0x%x)\n", *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || - (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { - if (defer_retries-- > 0) { - printk(BIOS_INFO, "dp: aux read defer (0x%x)" - " -- %d\n", *aux_stat, defer_retries); - /* clear the error bits */ - tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, - *aux_stat); - continue; - } else { - printk(BIOS_INFO, "dp: aux read defer exceeds" - " max retries (0x%x)\n", *aux_stat); - return -1; - } - } - - if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == - DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { - int i; - u32 temp_data[4]; - - for (i = 0; i < DP_AUX_MAX_BYTES / 4; ++i) - temp_data[i] = tegra_dpaux_readl(dp, - DPAUX_DP_AUXDATA_READ_W(i)); - - *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); - memcpy(data, temp_data, *size); - - return 0; - } else { - printk(BIOS_ERR, "dp: aux read failed (0x%x\n", - *aux_stat); - return -1; - } - } - /* Should never come to here */ - printk(BIOS_ERR, "%s: can't\n", __func__); - return -1; -} - -#if DO_FAST_LINK_TRAINING -static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, - u8 *data, u32 *size, u32 *aux_stat) -{ - u32 finished = 0; - u32 cur_size; - int ret = 0; - - do { - cur_size = *size - finished; - if (cur_size > DP_AUX_MAX_BYTES) - cur_size = DP_AUX_MAX_BYTES; - - ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, - data, &cur_size, aux_stat); - if (ret) - break; - - /* cur_size should be the real size returned */ - addr += cur_size; - data += cur_size; - finished += cur_size; - - } while (*size > finished); - - *size = finished; - return ret; -} -#endif /* DO_FAST_LINK_TRAINING */ - -static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, - u8 *data_ptr) -{ - u32 size = 1; - u32 status = 0; - int ret; - - ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - cmd, data_ptr, &size, &status); - if (ret) - printk(BIOS_ERR, - "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", - cmd, status); - - return ret; -} - -static int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd, - u8 data) -{ - u32 size = 1; - u32 status = 0; - int ret; - - ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, - cmd, &data, &size, &status); - if (ret) - printk(BIOS_ERR, - "dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n", - cmd, status); - return ret; -} - -static int tegra_dc_i2c_aux_read(struct tegra_dc_dp_data *dp, u32 i2c_addr, - u8 addr, u8 *data, u32 *size, u32 *aux_stat) -{ - u32 finished = 0; - int ret = 0; - - do { - u32 cur_size = MIN(DP_AUX_MAX_BYTES, *size - finished); - - u32 len = 1; - ret = tegra_dc_dpaux_write_chunk( - dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr, - &addr, &len, aux_stat); - if (ret) { - printk(BIOS_ERR, "%s: error sending address to read.\n", - __func__); - break; - } - - ret = tegra_dc_dpaux_read_chunk( - dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr, - data, &cur_size, aux_stat); - if (ret) { - printk(BIOS_ERR, "%s: error reading data.\n", __func__); - break; - } - - /* cur_size should be the real size returned */ - addr += cur_size; - data += cur_size; - finished += cur_size; - } while (*size > finished); - - *size = finished; - return ret; -} - -static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp) -{ - /* clear interrupt */ - tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff); - /* do not enable interrupt for now. Enable them when Isr in place */ - tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0); - - tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, - DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 | - DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 | - 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT | - DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE); - - tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, - DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP); -} - -static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp, - const struct tegra_dc_dp_link_config *link_cfg) -{ - printk(BIOS_INFO, "DP config: cfg_name " - "cfg_value\n"); - printk(BIOS_INFO, " Lane Count %d\n", - link_cfg->max_lane_count); - printk(BIOS_INFO, " SupportEnhancedFraming %s\n", - link_cfg->support_enhanced_framing ? "Y" : "N"); - printk(BIOS_INFO, " Bandwidth %d\n", - link_cfg->max_link_bw); - printk(BIOS_INFO, " bpp %d\n", - link_cfg->bits_per_pixel); - printk(BIOS_INFO, " EnhancedFraming %s\n", - link_cfg->enhanced_framing ? "Y" : "N"); - printk(BIOS_INFO, " Scramble_enabled %s\n", - link_cfg->scramble_ena ? "Y" : "N"); - printk(BIOS_INFO, " LinkBW %d\n", - link_cfg->link_bw); - printk(BIOS_INFO, " lane_count %d\n", - link_cfg->lane_count); - printk(BIOS_INFO, " activespolarity %d\n", - link_cfg->activepolarity); - printk(BIOS_INFO, " active_count %d\n", - link_cfg->active_count); - printk(BIOS_INFO, " tu_size %d\n", - link_cfg->tu_size); - printk(BIOS_INFO, " active_frac %d\n", - link_cfg->active_frac); - printk(BIOS_INFO, " watermark %d\n", - link_cfg->watermark); - printk(BIOS_INFO, " hblank_sym %d\n", - link_cfg->hblank_sym); - printk(BIOS_INFO, " vblank_sym %d\n", - link_cfg->vblank_sym); -} - -static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *link_cfg) -{ - - switch (link_cfg->link_bw) { - case SOR_LINK_SPEED_G1_62: - if (link_cfg->max_link_bw > SOR_LINK_SPEED_G1_62) - link_cfg->link_bw = SOR_LINK_SPEED_G2_7; - link_cfg->lane_count /= 2; - break; - case SOR_LINK_SPEED_G2_7: - link_cfg->link_bw = SOR_LINK_SPEED_G1_62; - break; - case SOR_LINK_SPEED_G5_4: - if (link_cfg->lane_count == 1) { - link_cfg->link_bw = SOR_LINK_SPEED_G2_7; - link_cfg->lane_count = link_cfg->max_lane_count; - } else - link_cfg->lane_count /= 2; - break; - default: - printk(BIOS_ERR, "dp: Error link rate %d\n", link_cfg->link_bw); - return DP_LT_FAILED; - } - - return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; -} - -/* Calcuate if given cfg can meet the mode request. */ -/* Return true if mode is possible, false otherwise. */ -static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, - const struct soc_nvidia_tegra132_config *config, - struct tegra_dc_dp_link_config *link_cfg) -{ - const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; - const u64 f = 100000; /* precision factor */ - - u32 num_linkclk_line; /* Number of link clocks per line */ - u64 ratio_f; /* Ratio of incoming to outgoing data rate */ - - u64 frac_f; - u64 activesym_f; /* Activesym per TU */ - u64 activecount_f; - u32 activecount; - u32 activepolarity; - u64 approx_value_f; - u32 activefrac = 0; - u64 accumulated_error_f = 0; - u32 lowest_neg_activecount = 0; - u32 lowest_neg_activepolarity = 0; - u32 lowest_neg_tusize = 64; - u32 num_symbols_per_line; - u64 lowest_neg_activefrac = 0; - u64 lowest_neg_error_f = 64 * f; - u64 watermark_f; - - int i; - int neg; - - printk(BIOS_INFO, "dp: %s\n", __func__); - - if (!link_rate || !link_cfg->lane_count || !config->pixel_clock || - !link_cfg->bits_per_pixel) - return -1; - - if ((u64)config->pixel_clock * link_cfg->bits_per_pixel >= - (u64)link_rate * 8 * link_cfg->lane_count) - return -1; - - num_linkclk_line = (u32)((u64)link_rate * (u64)config->xres / - config->pixel_clock); - - ratio_f = (u64)config->pixel_clock * link_cfg->bits_per_pixel * f; - ratio_f /= 8; - ratio_f = (u64)(ratio_f / (link_rate * link_cfg->lane_count)); - - for (i = 64; i >= 32; --i) { - activesym_f = ratio_f * i; - activecount_f = (u64)(activesym_f / (u32)f) * f; - frac_f = activesym_f - activecount_f; - activecount = (u32)((u64)(activecount_f / (u32)f)); - - if (frac_f < (f / 2)) /* fraction < 0.5 */ - activepolarity = 0; - else { - activepolarity = 1; - frac_f = f - frac_f; - } - - if (frac_f != 0) { - frac_f = (u64)((f * f) / frac_f); /* 1/fraction */ - if (frac_f > (15 * f)) - activefrac = activepolarity ? 1 : 15; - else - activefrac = activepolarity ? - (u32)((u64)(frac_f / (u32)f)) + 1 : - (u32)((u64)(frac_f / (u32)f)); - } - - if (activefrac == 1) - activepolarity = 0; - - if (activepolarity == 1) - approx_value_f = activefrac ? (u64)( - (activecount_f + (activefrac * f - f) * f) / - (activefrac * f)) : - activecount_f + f; - else - approx_value_f = activefrac ? - activecount_f + (u64)(f / activefrac) : - activecount_f; - - if (activesym_f < approx_value_f) { - accumulated_error_f = num_linkclk_line * - (u64)((approx_value_f - activesym_f) / i); - neg = 1; - } else { - accumulated_error_f = num_linkclk_line * - (u64)((activesym_f - approx_value_f) / i); - neg = 0; - } - - if ((neg && (lowest_neg_error_f > accumulated_error_f)) || - (accumulated_error_f == 0)) { - lowest_neg_error_f = accumulated_error_f; - lowest_neg_tusize = i; - lowest_neg_activecount = activecount; - lowest_neg_activepolarity = activepolarity; - lowest_neg_activefrac = activefrac; - - if (accumulated_error_f == 0) - break; - } - } - - if (lowest_neg_activefrac == 0) { - link_cfg->activepolarity = 0; - link_cfg->active_count = lowest_neg_activepolarity ? - lowest_neg_activecount : lowest_neg_activecount - 1; - link_cfg->tu_size = lowest_neg_tusize; - link_cfg->active_frac = 1; - } else { - link_cfg->activepolarity = lowest_neg_activepolarity; - link_cfg->active_count = (u32)lowest_neg_activecount; - link_cfg->tu_size = lowest_neg_tusize; - link_cfg->active_frac = (u32)lowest_neg_activefrac; - } - - watermark_f = (u64)((ratio_f * link_cfg->tu_size * (f - ratio_f)) / f); - link_cfg->watermark = (u32)((u64)((watermark_f + lowest_neg_error_f) / - f)) + link_cfg->bits_per_pixel / 4 - 1; - num_symbols_per_line = (config->xres * link_cfg->bits_per_pixel) / - (8 * link_cfg->lane_count); - - if (link_cfg->watermark > 30) { - printk(BIOS_INFO, - "dp: sor setting: unable to get a good tusize, " - "force watermark to 30.\n"); - link_cfg->watermark = 30; - return -1; - } else if (link_cfg->watermark > num_symbols_per_line) { - printk(BIOS_INFO, - "dp: sor setting: force watermark to the number " - "of symbols in the line.\n"); - link_cfg->watermark = num_symbols_per_line; - return -1; - } - - /* Refer to dev_disp.ref for more information. */ - /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */ - /* SetRasterBlankStart.X - 7) * link_clk / pclk) */ - /* - 3 * enhanced_framing - Y */ - /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */ - link_cfg->hblank_sym = (int)((u64)(((u64)(config->hback_porch + - config->hfront_porch + config->hsync_width - 7) * - link_rate) / config->pixel_clock)) - - 3 * link_cfg->enhanced_framing - - (12 / link_cfg->lane_count); - - if (link_cfg->hblank_sym < 0) - link_cfg->hblank_sym = 0; - - - /* Refer to dev_disp.ref for more information. */ - /* # symbols/vblank = ((SetRasterBlankStart.X - */ - /* SetRasterBlankEen.X - 25) * link_clk / pclk) */ - /* - Y - 1; */ - /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */ - link_cfg->vblank_sym = (int)((u64)((u64)(config->xres - 25) - * link_rate / config->pixel_clock)) - (36 / - link_cfg->lane_count) - 4; - - if (link_cfg->vblank_sym < 0) - link_cfg->vblank_sym = 0; - - link_cfg->is_valid = 1; - tegra_dc_dp_dump_link_cfg(dp, link_cfg); - - return 0; -} - -static int tegra_dc_dp_init_max_link_cfg( - struct soc_nvidia_tegra132_config *config, - struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *link_cfg) -{ - u8 dpcd_data; - int ret; - - printk(BIOS_INFO, "dp: %s\n", __func__); - - CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT, - &dpcd_data)); - link_cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; - link_cfg->tps3_supported = (dpcd_data & - NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ? 1 : 0; - - link_cfg->support_enhanced_framing = - (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? - 1 : 0; - - CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, - &dpcd_data)); - link_cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) - ? 1 : 0; - - CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL, - &link_cfg->aux_rd_interval)); - - CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH, - &link_cfg->max_link_bw)); - - link_cfg->bits_per_pixel = config->panel_bits_per_pixel; - - /* - * Set to a high value for link training and attach. - * Will be re-programmed when dp is enabled. - */ - link_cfg->drive_current = config->dp.drive_current; - link_cfg->preemphasis = config->dp.preemphasis; - link_cfg->postcursor = config->dp.postcursor; - - CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP, - &dpcd_data)); - link_cfg->alt_scramber_reset_cap = - (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? - 1 : 0; - link_cfg->only_enhanced_framing = - (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? - 1 : 0; - - link_cfg->lane_count = link_cfg->max_lane_count; - link_cfg->link_bw = link_cfg->max_link_bw; - link_cfg->enhanced_framing = link_cfg->support_enhanced_framing; - - tegra_dc_dp_calc_config(dp, config, link_cfg); - return 0; -} - -static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, int ena) -{ - int ret; - - u8 dpcd_data = ena ? - NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE : - NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE; - - CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET, - dpcd_data)); - - /* Also reset the scrambler to 0xfffe */ - tegra_dc_sor_set_internal_panel(&dp->sor, ena); - return 0; -} - -static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw) -{ - tegra_dc_sor_set_link_bandwidth(&dp->sor, link_bw); - - /* Sink side */ - return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw); -} - -static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp, - const struct tegra_dc_dp_link_config *link_cfg) -{ - u8 dpcd_data; - int ret; - - /* check if panel support enhanched_framing */ - dpcd_data = link_cfg->lane_count; - if (link_cfg->enhanced_framing) - dpcd_data |= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T; - CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_LANE_COUNT_SET, - dpcd_data)); - - tegra_dc_sor_set_lane_count(&dp->sor, link_cfg->lane_count); - - /* Also power down lanes that will not be used */ - return 0; -} - -#if DO_FAST_LINK_TRAINING -static int tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp, - const struct tegra_dc_dp_link_config *link_cfg) -{ - u32 lane; - u8 mask; - u8 data; - int ret; - - for (lane = 0; lane < link_cfg->lane_count; ++lane) { - CHECK_RET(tegra_dc_dp_dpcd_read(dp, (lane/2) ? - NV_DPCD_LANE2_3_STATUS : NV_DPCD_LANE0_1_STATUS, - &data)); - mask = (lane & 1) ? - NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES | - NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES | - NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES : - NV_DPCD_STATUS_LANEX_CR_DONE_YES | - NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES | - NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES; - if ((data & mask) != mask) - return -1; - } - return 0; -} -#endif /* DO_FAST_LINK_TRAINING */ - -static int tegra_dp_channel_eq_status(struct tegra_dc_dp_data *dp) -{ - u32 cnt; - u32 n_lanes = dp->link_cfg.lane_count; - u8 data; - u8 ce_done = 1; - - for (cnt = 0; cnt < n_lanes / 2; cnt++) { - tegra_dc_dp_dpcd_read(dp, (NV_DPCD_LANE0_1_STATUS + cnt), - &data); - - if (n_lanes == 1) { - ce_done = - (data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) && - (data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)); - break; - } else - if (!(data & (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT)) || - !(data & (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT)) || - !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT)) || - !(data & (0x1 << NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT))) - return 0; - } - - if (ce_done) { - tegra_dc_dp_dpcd_read(dp, NV_DPCD_LANE_ALIGN_STATUS_UPDATED, - &data); - if (!(data & NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES)) - ce_done = 0; - } - - return ce_done; -} - -static u8 tegra_dp_clock_recovery_status(struct tegra_dc_dp_data *dp) -{ - u32 cnt; - u32 n_lanes = dp->link_cfg.lane_count; - u8 data_ptr; - - for (cnt = 0; cnt < n_lanes / 2; cnt++) { - tegra_dc_dp_dpcd_read(dp, - (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr); - - if (n_lanes == 1) - return (data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) ? 1 : 0; - else if (!(data_ptr & NV_DPCD_STATUS_LANEX_CR_DONE_YES) || - !(data_ptr & (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES))) - return 0; - } - - return 1; -} - -static void tegra_dp_lt_adjust(struct tegra_dc_dp_data *dp, - u32 pe[4], u32 vs[4], u32 pc[4], - u8 pc_supported) -{ - size_t cnt; - u8 data_ptr; - u32 n_lanes = dp->link_cfg.lane_count; - - for (cnt = 0; cnt < n_lanes / 2; cnt++) { - tegra_dc_dp_dpcd_read(dp, - (NV_DPCD_LANE0_1_ADJUST_REQ + cnt), &data_ptr); - pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >> - NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT; - vs[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >> - NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT; - pe[1 + 2 * cnt] = - (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >> - NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT; - vs[1 + 2 * cnt] = - (data_ptr & NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >> - NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT; - } - if (pc_supported) { - tegra_dc_dp_dpcd_read(dp, - NV_DPCD_ADJUST_REQ_POST_CURSOR2, &data_ptr); - for (cnt = 0; cnt < n_lanes; cnt++) { - pc[cnt] = (data_ptr >> - NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt)) & - NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK; - } - } -} - -static inline u32 tegra_dp_wait_aux_training(struct tegra_dc_dp_data *dp, - u8 is_clk_recovery) -{ - if (!dp->link_cfg.aux_rd_interval) - is_clk_recovery ? udelay(200) : - udelay(500); - else - mdelay(dp->link_cfg.aux_rd_interval * 4); - - return dp->link_cfg.aux_rd_interval; -} - -static void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes) -{ - u8 data = (tp == training_pattern_disabled) - ? (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F) - : (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T); - - tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, tp, &dp->link_cfg); - tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, data); -} - -static int tegra_dp_link_config(struct tegra_dc_dp_data *dp, - const struct tegra_dc_dp_link_config *link_cfg) -{ - u8 dpcd_data; - u32 retry; - - if (link_cfg->lane_count == 0) { - printk(BIOS_ERR, "dp: error: lane count is 0. " - "Can not set link config.\n"); - return DP_LT_FAILED; - } - - /* Set power state if it is not in normal level */ - if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data)) - return DP_LT_FAILED; - - if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) { - dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL; - - /* DP spec requires 3 retries */ - for (retry = 3; retry > 0; --retry) { - if (tegra_dc_dp_dpcd_write(dp, NV_DPCD_SET_POWER, - dpcd_data)) - break; - if (retry == 1) { - printk(BIOS_ERR, "dp: Failed to set DP panel" - " power\n"); - return DP_LT_FAILED; - } - } - } - - /* Enable ASSR if possible */ - if (link_cfg->alt_scramber_reset_cap) - if (tegra_dc_dp_set_assr(dp, 1)) - return DP_LT_FAILED; - - if (tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw)) { - printk(BIOS_ERR, "dp: Failed to set link bandwidth\n"); - return DP_LT_FAILED; - } - if (tegra_dp_set_lane_count(dp, link_cfg)) { - printk(BIOS_ERR, "dp: Failed to set lane count\n"); - return DP_LT_FAILED; - } - tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, training_pattern_none, - link_cfg); - return DP_LT_SUCCESS; -} - -static int tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *cfg) -{ - struct tegra_dc_dp_link_config tmp_cfg; - - tmp_cfg = dp->link_cfg; - cfg->is_valid = 0; - - if (_tegra_dp_lower_link_config(dp, cfg)) - goto fail; - - if (tegra_dc_dp_calc_config(dp, dp->dc->config, cfg)) - goto fail; - tegra_dp_link_config(dp, cfg); - - return DP_LT_SUCCESS; -fail: - dp->link_cfg = tmp_cfg; - tegra_dp_link_config(dp, &tmp_cfg); - return DP_LT_FAILED; -} - -static void tegra_dp_lt_config(struct tegra_dc_dp_data *dp, - u32 pe[4], u32 vs[4], u32 pc[4]) -{ - struct tegra_dc_sor_data *sor = &dp->sor; - u32 n_lanes = dp->link_cfg.lane_count; - u8 pc_supported = dp->link_cfg.tps3_supported; - u32 cnt; - u32 val; - - for (cnt = 0; cnt < n_lanes; cnt++) { - u32 mask = 0; - u32 pe_reg, vs_reg, pc_reg; - u32 shift = 0; - - switch (cnt) { - case 0: - mask = NV_SOR_PR_LANE2_DP_LANE0_MASK; - shift = NV_SOR_PR_LANE2_DP_LANE0_SHIFT; - break; - case 1: - mask = NV_SOR_PR_LANE1_DP_LANE1_MASK; - shift = NV_SOR_PR_LANE1_DP_LANE1_SHIFT; - break; - case 2: - mask = NV_SOR_PR_LANE0_DP_LANE2_MASK; - shift = NV_SOR_PR_LANE0_DP_LANE2_SHIFT; - break; - case 3: - mask = NV_SOR_PR_LANE3_DP_LANE3_MASK; - shift = NV_SOR_PR_LANE3_DP_LANE3_SHIFT; - break; - default: - printk(BIOS_ERR, - "dp: incorrect lane cnt\n"); - } - - pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]]; - vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]]; - pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]]; - - tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift, - vs_reg << shift, pc_reg << shift, pc_supported); - } - - tegra_dp_disable_tx_pu(&dp->sor); - udelay(20); - - for (cnt = 0; cnt < n_lanes; cnt++) { - u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]); - u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]); - - val = (vs[cnt] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT) | - (max_vs_flag ? - NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T : - NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F) | - (pe[cnt] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | - (max_pe_flag ? - NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T : - NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F); - tegra_dc_dp_dpcd_write(dp, - (NV_DPCD_TRAINING_LANE0_SET + cnt), val); - } - - if (pc_supported) { - for (cnt = 0; cnt < n_lanes / 2; cnt++) { - u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]); - u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]); - val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) | - (max_pc_flag0 ? - NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T : - NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F) | - (pc[cnt + 1] << - NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT) | - (max_pc_flag1 ? - NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T : - NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F); - tegra_dc_dp_dpcd_write(dp, - (NV_DPCD_TRAINING_LANE0_1_SET2 + cnt), val); - } - } -} - -static int _tegra_dp_channel_eq(struct tegra_dc_dp_data *dp, u32 pe[4], - u32 vs[4], u32 pc[4], u8 pc_supported, - u32 n_lanes) -{ - u32 retry_cnt; - - for (retry_cnt = 0; retry_cnt < 4; retry_cnt++) { - if (retry_cnt) { - tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported); - tegra_dp_lt_config(dp, pe, vs, pc); - } - - tegra_dp_wait_aux_training(dp, 0); - - if (!tegra_dp_clock_recovery_status(dp)) { - printk(BIOS_ERR, "dp: CR failed in channel EQ" - " sequence!\n"); - break; - } - - if (tegra_dp_channel_eq_status(dp)) - return DP_LT_SUCCESS; - } - - return DP_LT_FAILED; -} - -static int tegra_dp_channel_eq(struct tegra_dc_dp_data *dp, - u32 pe[4], u32 vs[4], u32 pc[4]) -{ - u32 n_lanes = dp->link_cfg.lane_count; - u8 pc_supported = dp->link_cfg.tps3_supported; - int err; - u32 tp_src = training_pattern_2; - - if (pc_supported) - tp_src = training_pattern_3; - - tegra_dp_tpg(dp, tp_src, n_lanes); - - err = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes); - - tegra_dp_tpg(dp, training_pattern_disabled, n_lanes); - - return err; -} - -static int _tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp, u32 pe[4], - u32 vs[4], u32 pc[4], u8 pc_supported, - u32 n_lanes) -{ - u32 vs_temp[4]; - u32 retry_cnt = 0; - - do { - tegra_dp_lt_config(dp, pe, vs, pc); - tegra_dp_wait_aux_training(dp, 1); - - if (tegra_dp_clock_recovery_status(dp)) - return DP_LT_SUCCESS; - - memcpy(vs_temp, vs, sizeof(vs_temp)); - tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported); - - if (memcmp(vs_temp, vs, sizeof(vs_temp))) - retry_cnt = 0; - else - ++retry_cnt; - } while (retry_cnt < 5); - - return DP_LT_FAILED; -} - -static int tegra_dp_clk_recovery(struct tegra_dc_dp_data *dp, - u32 pe[4], u32 vs[4], u32 pc[4]) -{ - u32 n_lanes = dp->link_cfg.lane_count; - u8 pc_supported = dp->link_cfg.tps3_supported; - int err; - - tegra_dp_tpg(dp, training_pattern_1, n_lanes); - - err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes); - if (err < 0) - tegra_dp_tpg(dp, training_pattern_disabled, n_lanes); - - return err; -} - -static int tegra_dc_dp_full_link_training(struct tegra_dc_dp_data *dp) -{ - struct tegra_dc_sor_data *sor = &dp->sor; - int err; - u32 pe[4], vs[4], pc[4]; - - printk(BIOS_INFO, "dp: %s\n", __func__); - tegra_sor_precharge_lanes(sor); - -retry_cr: - memset(pe, preEmphasis_Disabled, sizeof(pe)); - memset(vs, driveCurrent_Level0, sizeof(vs)); - memset(pc, postCursor2_Level0, sizeof(pc)); - - err = tegra_dp_clk_recovery(dp, pe, vs, pc); - if (err != DP_LT_SUCCESS) { - if (!tegra_dp_lower_link_config(dp, &dp->link_cfg)) - goto retry_cr; - - printk(BIOS_ERR, "dp: clk recovery failed\n"); - goto fail; - } - - err = tegra_dp_channel_eq(dp, pe, vs, pc); - if (err != DP_LT_SUCCESS) { - if (!tegra_dp_lower_link_config(dp, &dp->link_cfg)) - goto retry_cr; - - printk(BIOS_ERR, - "dp: channel equalization failed\n"); - goto fail; - } - - tegra_dc_dp_dump_link_cfg(dp, &dp->link_cfg); - - return 0; - -fail: - return err; -} - -/* - * All link training functions are ported from kernel dc driver. - * See more details at drivers/video/tegra/dc/dp.c - */ -#if DO_FAST_LINK_TRAINING -static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp, - const struct tegra_dc_dp_link_config *link_cfg) -{ - struct tegra_dc_sor_data *sor = &dp->sor; - u8 link_bw; - u8 lane_count; - u16 data16; - u32 data32; - u32 size; - u32 status; - int j; - u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4); - - - printk(BIOS_INFO, "dp: %s\n", __func__); - - tegra_dc_sor_set_lane_parm(sor, link_cfg); - tegra_dc_dp_dpcd_write(dp, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET, - NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B); - - /* Send TP1 */ - tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg); - tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, - NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1); - - for (j = 0; j < link_cfg->lane_count; ++j) - tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j, - 0x24); - udelay(520); - - size = sizeof(data16); - tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - NV_DPCD_LANE0_1_STATUS, (u8 *)&data16, &size, &status); - status = mask & 0x1111; - if ((data16 & status) != status) { - printk(BIOS_ERR, - "dp: Link training error for TP1 (%#x)\n", data16); - return -EFAULT; - } - - /* enable ASSR */ - tegra_dc_dp_set_assr(dp, link_cfg->scramble_ena); - tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg); - - tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, - link_cfg->link_bw == 20 ? 0x23 : 0x22); - for (j = 0; j < link_cfg->lane_count; ++j) - tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j, - 0x24); - udelay(520); - - size = sizeof(data32); - tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, - NV_DPCD_LANE0_1_STATUS, (u8 *)&data32, &size, &status); - if ((data32 & mask) != (0x7777 & mask)) { - printk(BIOS_ERR, - "dp: Link training error for TP2/3 (0x%x)\n", data32); - return -EFAULT; - } - - tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled, - link_cfg); - tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, 0); - - if (tegra_dc_dp_link_trained(dp, link_cfg)) { - tegra_dc_sor_read_link_config(&dp->sor, &link_bw, - &lane_count); - printk(BIOS_ERR, - "Fast link trainging failed, link bw %d, lane # %d\n", - link_bw, lane_count); - return -EFAULT; - } - - printk(BIOS_INFO, - "Fast link trainging succeeded, link bw %d, lane %d\n", - link_cfg->link_bw, link_cfg->lane_count); - - return 0; -} -#endif /* DO_FAST_LINK_TRAINING */ - -static int tegra_dp_do_link_training(struct tegra_dc_dp_data *dp, - const struct tegra_dc_dp_link_config *link_cfg) -{ - u8 link_bw; - u8 lane_count; -#if DO_FAST_LINK_TRAINING - int ret; - - /* Now do the fast link training for eDP */ - ret = tegra_dc_dp_fast_link_training(dp, link_cfg); - if (ret) { - printk(BIOS_ERR, "dp: fast link training failed\n"); - - /* Try full link training then */ - if (tegra_dc_dp_full_link_training(dp)) { - printk(BIOS_ERR, "dp: full link training failed\n"); - return ret; - } - } else { - /* set to a known-good drive setting if fast link succeeded */ - tegra_dc_sor_set_voltage_swing(&dp->sor); - } -#else - if (tegra_dc_dp_full_link_training(dp)) { - printk(BIOS_ERR, "dp: full link training failed\n"); - return -EFAULT; - } -#endif - - /* Everything goes well, double check the link config */ - /* TODO: record edc/c2 data for debugging */ - tegra_dc_sor_read_link_config(&dp->sor, &link_bw, &lane_count); - - if ((link_cfg->link_bw == link_bw) && - (link_cfg->lane_count == lane_count)) - return 0; - else - return -EFAULT; -} - -static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp, - struct tegra_dc_dp_link_config *link_cfg, - const struct soc_nvidia_tegra132_config *config) -{ - struct tegra_dc_dp_link_config temp_cfg; - - if (!config->pixel_clock || !config->xres || !config->yres) { - printk(BIOS_ERR, - "dp: error mode configuration"); - return -EINVAL; - } - if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) { - printk(BIOS_ERR, - "dp: error link configuration"); - return -EINVAL; - } - - link_cfg->is_valid = 0; - - memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg)); - - temp_cfg.link_bw = temp_cfg.max_link_bw; - temp_cfg.lane_count = temp_cfg.max_lane_count; - - /* - * set to max link config - */ - if ((!tegra_dc_dp_calc_config(dp, config, &temp_cfg)) && - (!tegra_dp_link_config(dp, &temp_cfg)) && - (!tegra_dp_do_link_training(dp, &temp_cfg))) - /* the max link cfg is doable */ - memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg)); - - return link_cfg->is_valid ? 0 : -EFAULT; -} - -static void tegra_dp_update_config(struct tegra_dc_dp_data *dp, - struct soc_nvidia_tegra132_config *config) -{ - struct edid edid; - u8 buf[128] = {0}; - u32 size = sizeof(buf), aux_stat = 0; - - printk(BIOS_ERR, "%s: enable r/w dump.\n", - __func__); - - tegra_dc_dpaux_enable(dp); - if (tegra_dc_i2c_aux_read(dp, TEGRA_EDID_I2C_ADDRESS, 0, buf, &size, - &aux_stat)) { - printk(BIOS_ERR, "%s: Failed to read EDID. Use defaults.\n", - __func__); - return; - } - - if (decode_edid(buf, sizeof(buf), &edid)) { - printk(BIOS_ERR, "%s: Failed to decode EDID. Use defaults.\n", - __func__); - return; - } - - config->xres = config->display_xres = edid.mode.ha; - config->yres = config->display_yres = edid.mode.va; - - config->pixel_clock = edid.mode.pixel_clock * 1000; - - config->hfront_porch = edid.mode.hso; - config->hsync_width = edid.mode.hspw; - config->hback_porch = edid.mode.hbl - edid.mode.hso - edid.mode.hspw; - - config->vfront_porch = edid.mode.vso; - config->vsync_width = edid.mode.vspw; - config->vback_porch = edid.mode.vbl - edid.mode.vso - edid.mode.vspw; - - /** - * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32, - * so we should keep the default value in device config. - * - * EDID v1.3 panels may not have color depth info, so we need to check - * if these values are zero before updating config. - */ - if (edid.panel_bits_per_pixel) - config->panel_bits_per_pixel = edid.panel_bits_per_pixel; - if (edid.panel_bits_per_color) - config->color_depth = edid.panel_bits_per_color; - printk(BIOS_SPEW, "%s: configuration updated by EDID.\n", __func__); -} - -void dp_init(void *_config) -{ - struct soc_nvidia_tegra132_config *config = (void *)_config; - struct tegra_dc *dc = config->dc_data; - struct tegra_dc_dp_data *dp = &dp_data; - - /* set up links among config, dc, dp and sor */ - dp->dc = dc; - dc->out = dp; - dp->sor.dc = dc; - - dp->sor.power_is_up = 0; - dp->sor.base = (void *)TEGRA_ARM_SOR; - dp->sor.pmc_base = (void *)TEGRA_PMC_BASE; - dp->sor.portnum = 0; - dp->sor.link_cfg = &dp->link_cfg; - dp->aux_base = (void *)TEGRA_ARM_DPAUX; - dp->link_cfg.is_valid = 0; - dp->enabled = 0; - - tegra_dp_update_config(dp, config); -} - -static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp, - struct soc_nvidia_tegra132_config *config) -{ - u32 val; - - val = config->dp.hpd_plug_min_us | - (config->dp.hpd_unplug_min_us << - DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT); - tegra_dpaux_writel(dp, DPAUX_HPD_CONFIG, val); - - tegra_dpaux_writel(dp, DPAUX_HPD_IRQ_CONFIG, config->dp.hpd_irq_min_us); -} - -static int tegra_dp_hpd_plug(struct tegra_dc_dp_data *dp, int timeout_ms) -{ - u32 val; - u32 timeout = timeout_ms * 1000; - do { - val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); - if (val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED) - return 0; - udelay(100); - timeout -= 100; - } while (timeout > 0); - return -1; -} - -static int tegra_dc_dp_sink_out_of_sync(struct tegra_dc_dp_data *dp, - u32 delay_ms) -{ - u8 dpcd_data; - int out_of_sync; - - mdelay(delay_ms); - tegra_dc_dp_dpcd_read(dp, NV_DPCD_SINK_STATUS, &dpcd_data); - - out_of_sync = ((dpcd_data & NV_DPCD_SINK_STATUS_PORT0_IN_SYNC) != - NV_DPCD_SINK_STATUS_PORT0_IN_SYNC); - - if (out_of_sync) - printk(BIOS_ERR, - "SINK receive port 0 is out of synchronization\n"); - else - printk(BIOS_INFO, - "SINK is in synchronization\n"); - - return out_of_sync; -} - -static void tegra_dc_dp_check_sink(struct tegra_dc_dp_data *dp, - struct soc_nvidia_tegra132_config *config) -{ - - u8 max_retry = 3; - int delay_frame; - - /* DP TCON may skip some main stream frames, thus we need to wait - some delay before reading the DPCD SINK STATUS register, starting - from 5 */ - delay_frame = 5; - - while (tegra_dc_dp_sink_out_of_sync(dp, FRAME_IN_MS * delay_frame) && - max_retry--) { - tegra_dc_detach(&dp->sor); - if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, config)) { - printk(BIOS_ERR, "dp: %s: error to configure link\n", - __func__); - continue; - } - - tegra_dc_sor_set_power_state(&dp->sor, 1); - tegra_dc_sor_attach(&dp->sor); - - /* Increase delay_frame for next try in case the sink is - skipping more frames */ - delay_frame += 10; - } -} - -void dp_enable(void *_dp) -{ - struct tegra_dc_dp_data *dp = _dp; - struct tegra_dc *dc = dp->dc; - struct soc_nvidia_tegra132_config *config = dc->config; - - u8 data; - u32 retry; - int ret; - - tegra_dc_dpaux_enable(dp); - - tegra_dp_hpd_config(dp, config); - if (tegra_dp_hpd_plug(dp, config->dp.vdd_to_hpd_delay_ms) < 0) { - printk(BIOS_ERR, "dp: hpd plug failed\n"); - goto error_enable; - } - - if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) { - printk(BIOS_ERR, "dp: failed to init link configuration\n"); - goto error_enable; - } - - tegra_dc_sor_enable_dp(&dp->sor); - - tegra_dc_sor_set_panel_power(&dp->sor, 1); - - /* Write power on to DPCD */ - data = NV_DPCD_SET_POWER_VAL_D0_NORMAL; - retry = 0; - do { - ret = tegra_dc_dp_dpcd_write(dp, - NV_DPCD_SET_POWER, data); - } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret); - - if (ret || retry >= DP_POWER_ON_MAX_TRIES) { - printk(BIOS_ERR, - "dp: failed to power on panel (0x%x)\n", ret); - goto error_enable; - } - - /* Confirm DP is plugging status */ - if (!(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) & - DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { - printk(BIOS_ERR, "dp: could not detect HPD\n"); - goto error_enable; - } - - /* Check DP version */ - if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision)) - printk(BIOS_ERR, - "dp: failed to read the revision number from sink\n"); - - if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, config)) { - printk(BIOS_ERR, "dp: error to configure link\n"); - goto error_enable; - } - - tegra_dc_sor_set_power_state(&dp->sor, 1); - tegra_dc_sor_attach(&dp->sor); - - tegra_dc_dp_check_sink(dp, config); - - /* - * Power down the unused lanes to save power - * (about hundreds milli-watts, varies from boards). - */ - tegra_dc_sor_power_down_unused_lanes(&dp->sor); - - dp->enabled = 1; -error_enable: - return; -} - -void dp_display_startup(device_t dev) -{ - struct soc_nvidia_tegra132_config *config = dev->chip_info; - struct display_controller *disp_ctrl = - (void *)config->display_controller; - - u32 framebuffer_size_mb = config->framebuffer_size / MiB; - u32 framebuffer_base_mb = config->framebuffer_base / MiB; - - struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; - struct tegra_dc *dc = &dc_data; - u32 plld_rate; - - printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n", - __func__, disp_ctrl); - - if (disp_ctrl == NULL) { - printk(BIOS_ERR, "Error: No dc is assigned by dt.\n"); - return; - } - - dc->base = (void *)disp_ctrl; - dc->config = config; - config->dc_data = dc; - - /* Note dp_init may read EDID and change some config values. */ - dp_init(config); - - if (framebuffer_size_mb == 0) { - framebuffer_size_mb = ALIGN_UP(config->display_xres * - config->display_yres * - (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; - } - - config->framebuffer_size = framebuffer_size_mb * MiB; - config->framebuffer_base = framebuffer_base_mb * MiB; - - /* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER - * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the - * update_display_mode() for detail. - */ - plld_rate = clock_configure_plld(config->pixel_clock * 2); - if (plld_rate == 0) { - printk(BIOS_ERR, "dc: clock init failed\n"); - return; - } else if (plld_rate != config->pixel_clock * 2) { - printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate); - config->pixel_clock = plld_rate / 2; - } - - /* set disp1's clock source to PLLD_OUT0 */ - clock_configure_source(disp1, PLLD, (plld_rate/KHz)/2); - - /* Init dc */ - if (tegra_dc_init(disp_ctrl)) { - printk(BIOS_ERR, "dc: init failed\n"); - return; - } - - /* Configure dc mode */ - if (update_display_mode(disp_ctrl, config)) { - printk(BIOS_ERR, "dc: failed to configure display mode.\n"); - return; - } - - /* Enable dp */ - dp_enable(dc->out); - - /* Set up Tegra PWM n (where n is specified in config->dp.pwm) to drive the - * panel backlight. - */ - printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__); - WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) | - (220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */ - 0x02e), /* frequency divider */ - &pwm->pwm[config->dp.pwm].csr); - - /* Set up window */ - update_window(config); - printk(BIOS_INFO, "%s: display init done.\n", __func__); - - /* Save panel mode to cb tables */ - pass_mode_info_to_payload(config); - - /* - * After this point, it is payload's responsibility to allocate - * framebuffer and sets the base address to dc's - * WINBUF_START_ADDR register and enables window by setting dc's - * DISP_DISP_WIN_OPTIONS register. - */ -} diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c deleted file mode 100644 index f2a2b3c83c..0000000000 --- a/src/soc/nvidia/tegra132/dsi.c +++ /dev/null @@ -1,960 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <lib.h> -#include <stdlib.h> -#include <delay.h> -#include <timer.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <device/device.h> -#include <edid.h> -#include <soc/nvidia/tegra/types.h> -#include <soc/nvidia/tegra/dc.h> -#include "chip.h" -#include <soc/display.h> -#include <soc/mipi_dsi.h> -#include <soc/mipi_display.h> -#include <soc/tegra_dsi.h> -#include <soc/mipi-phy.h> -#include "jdi_25x18_display/panel-jdi-lpm102a188a.h" - -struct tegra_mipi_device mipi_device_data[NUM_DSI]; - -struct tegra_dsi dsi_data[NUM_DSI] = { - { - .regs = (void *)TEGRA_DSIA_BASE, - .channel = 0, - .slave = &dsi_data[DSI_B], - .master = NULL, - .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH, - .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH, - }, - { - .regs = (void *)TEGRA_DSIB_BASE, - .channel = 0, - .slave = NULL, - .master = &dsi_data[DSI_A], - .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH, - .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH, - }, -}; - -static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) -{ - return container_of(host, struct tegra_dsi, host); -} - -/* - * non-burst mode with sync pulses - */ -static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { - [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | - PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | - PKT_LP, - [ 1] = 0, - [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | - PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | - PKT_LP, - [ 3] = 0, - [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | - PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | - PKT_LP, - [ 5] = 0, - [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | - PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), - [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | - PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | - PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), - [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | - PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | - PKT_LP, - [ 9] = 0, - [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | - PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), - [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | - PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | - PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), -}; - -/* - * non-burst mode with sync events - */ -static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { - [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | - PKT_LP, - [ 1] = 0, - [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | - PKT_LP, - [ 3] = 0, - [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | - PKT_LP, - [ 5] = 0, - - [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | - PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), - - [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), - [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | - PKT_LP, - [ 9] = 0, - - [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | - PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | - PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), - - [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), -}; - -static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { - [ 0] = 0, - [ 1] = 0, - [ 2] = 0, - [ 3] = 0, - [ 4] = 0, - [ 5] = 0, - [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, - [ 7] = 0, - [ 8] = 0, - [ 9] = 0, - [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, - [11] = 0, -}; - -static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi) -{ - int err; - - err = mipi_dphy_set_timing(dsi); - if (err < 0) { - printk(BIOS_ERR, "failed to set D-PHY timing: %d\n", err); - return err; - } - - if (dsi->slave) - tegra_dsi_set_phy_timing(dsi->slave); - return 0; -} - -static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, - unsigned int *mulp, unsigned int *divp) -{ - switch (format) { - case MIPI_DSI_FMT_RGB666_PACKED: - case MIPI_DSI_FMT_RGB888: - *mulp = 3; - *divp = 1; - break; - - case MIPI_DSI_FMT_RGB565: - *mulp = 2; - *divp = 1; - break; - - case MIPI_DSI_FMT_RGB666: - *mulp = 9; - *divp = 4; - break; - - default: - return -EINVAL; - } - return 0; -} - -static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, - enum tegra_dsi_format *fmt) -{ - switch (format) { - case MIPI_DSI_FMT_RGB888: - *fmt = TEGRA_DSI_FORMAT_24P; - break; - - case MIPI_DSI_FMT_RGB666: - *fmt = TEGRA_DSI_FORMAT_18NP; - break; - - case MIPI_DSI_FMT_RGB666_PACKED: - *fmt = TEGRA_DSI_FORMAT_18P; - break; - - case MIPI_DSI_FMT_RGB565: - *fmt = TEGRA_DSI_FORMAT_16P; - break; - - default: - return -EINVAL; - } - return 0; -} - -static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, - unsigned int size) -{ - u32 value; - - tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); - tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); - - value = DSI_GANGED_MODE_CONTROL_ENABLE; - tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); -} - -static void tegra_dsi_enable(struct tegra_dsi *dsi) -{ - u32 value; - - value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); - value |= DSI_POWER_CONTROL_ENABLE; - tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); - - if (dsi->slave) - tegra_dsi_enable(dsi->slave); -} - -static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, - const struct soc_nvidia_tegra132_config *mode) -{ - unsigned int hact, hsw, hbp, hfp, i, mul, div; - enum tegra_dsi_format format; - const u32 *pkt_seq; - u32 value; - int err; - - if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { - printk(BIOS_SPEW, "Non-burst video mode with sync pulses\n"); - pkt_seq = pkt_seq_video_non_burst_sync_pulses; - } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { - printk(BIOS_SPEW, "Non-burst video mode with sync events\n"); - pkt_seq = pkt_seq_video_non_burst_sync_events; - } else { - printk(BIOS_SPEW, "Command mode\n"); - pkt_seq = pkt_seq_command_mode; - } - - err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); - if (err < 0) - return err; - - err = tegra_dsi_get_format(dsi->format, &format); - if (err < 0) - return err; - - value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) | - DSI_CONTROL_LANES(dsi->lanes - 1) | - DSI_CONTROL_SOURCE(pipe); - tegra_dsi_writel(dsi, value, DSI_CONTROL); - - tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); - - value = DSI_HOST_CONTROL_HS; - tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); - - value = tegra_dsi_readl(dsi, DSI_CONTROL); - - if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) - value |= DSI_CONTROL_HS_CLK_CTRL; - - value &= ~DSI_CONTROL_TX_TRIG(3); - - /* enable DCS commands for command mode */ - if (dsi->flags & MIPI_DSI_MODE_VIDEO) - value &= ~DSI_CONTROL_DCS_ENABLE; - else - value |= DSI_CONTROL_DCS_ENABLE; - - value |= DSI_CONTROL_VIDEO_ENABLE; - value &= ~DSI_CONTROL_HOST_ENABLE; - tegra_dsi_writel(dsi, value, DSI_CONTROL); - - for (i = 0; i < NUM_PKT_SEQ; i++) - tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); - - if (dsi->flags & MIPI_DSI_MODE_VIDEO) { - /* horizontal active pixels */ - hact = mode->xres * mul / div; - - /* horizontal sync width */ - hsw = (hsync_end(mode) - hsync_start(mode)) * mul / div; - hsw -= 10; - - /* horizontal back porch */ - hbp = (htotal(mode) - hsync_end(mode)) * mul / div; - hbp -= 14; - - /* horizontal front porch */ - hfp = (hsync_start(mode) - mode->xres) * mul / div; - hfp -= 8; - - tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); - tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); - tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); - tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); - - /* set SOL delay (for non-burst mode only) */ - tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); - - /* TODO: implement ganged mode */ - } else { - u16 bytes; - if (dsi->ganged_mode) { - /* - * For ganged mode, assume symmetric left-right mode. - */ - bytes = 1 + (mode->xres / 2) * mul / div; - } else { - /* 1 byte (DCS command) + pixel data */ - bytes = 1 + mode->xres * mul / div; - } - - tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); - tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); - tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); - tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); - - value = MIPI_DCS_WRITE_MEMORY_START << 8 | - MIPI_DCS_WRITE_MEMORY_CONTINUE; - tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); - - /* set SOL delay */ - if (dsi->ganged_mode) { - unsigned long delay, bclk, bclk_ganged; - unsigned int lanes = dsi->ganged_lanes; - - /* SOL to valid, valid to FIFO and FIFO write delay */ - delay = 4 + 4 + 2; - delay = DIV_ROUND_UP(delay * mul, div * lanes); - /* FIFO read delay */ - delay = delay + 6; - - bclk = DIV_ROUND_UP(htotal(mode) * mul, div * lanes); - bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); - value = bclk - bclk_ganged + delay + 20; - } else { - /* TODO: revisit for non-ganged mode */ - value = 8 * mul / div; - } - - tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); - } - - if (dsi->slave) { - err = tegra_dsi_configure(dsi->slave, pipe, mode); - if (err < 0) - return err; - - /* - * enable ganged mode - */ - if (dsi->ganged_mode) { - tegra_dsi_ganged_enable(dsi, mode->xres / 2, - mode->xres / 2); - tegra_dsi_ganged_enable(dsi->slave, 0, mode->xres / 2); - } - } - return 0; -} - -static int tegra_output_dsi_enable(struct tegra_dsi *dsi, - const struct soc_nvidia_tegra132_config *config) -{ - int err; - - if (dsi->enabled) - return 0; - - err = tegra_dsi_configure(dsi, 0, config); - if (err < 0) - return err; - - /* enable DSI controller */ - tegra_dsi_enable(dsi); - - dsi->enabled = true; - return 0; -} - - -static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, - unsigned int vrefresh) -{ - unsigned int timeout; - u32 value; - - /* one frame high-speed transmission timeout */ - timeout = (bclk / vrefresh) / 512; - value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); - tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); - - /* 2 ms peripheral timeout for panel */ - timeout = 2 * bclk / 512 * 1000; - value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); - tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); - - value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); - tegra_dsi_writel(dsi, value, DSI_TO_TALLY); - - if (dsi->slave) - tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); -} - -static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi, - const struct soc_nvidia_tegra132_config *config) -{ - unsigned int mul, div, num_lanes; - unsigned long bclk; - unsigned long pclk = config->pixel_clock; - int plld; - int err; - struct display_controller *disp_ctrl = - (void *)config->display_controller; - unsigned int shift_clk_div; - - err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); - if (err < 0) - return err; - - /* - * In ganged mode, account for the total number of lanes across both - * DSI channels so that the bit clock is properly computed. - */ - if (dsi->ganged_mode) - num_lanes = dsi->ganged_lanes; - else - num_lanes = dsi->lanes; - - /* compute byte clock */ - bclk = (pclk * mul) / (div * num_lanes); - - /* - * Compute bit clock and round up to the next MHz. - */ - plld = DIV_ROUND_UP(bclk * 8, USECS_PER_SEC) * USECS_PER_SEC; - - /* - * the actual rate on PLLD_OUT0 is 1/2 plld - */ - dsi->clk_rate = plld / 2; - if (dsi->slave) - dsi->slave->clk_rate = dsi->clk_rate; - - /* set up plld */ - plld = clock_configure_plld(plld); - if (plld == 0) { - printk(BIOS_ERR, "%s: clock init failed\n", __func__); - return -1; - } - - /* - * Derive pixel clock from bit clock using the shift clock divider. - * Note that this is only half of what we would expect, but we need - * that to make up for the fact that we divided the bit clock by a - * factor of two above. - */ - shift_clk_div = ((8 * mul) / (div * num_lanes)) - 2; - update_display_shift_clock_divider(disp_ctrl, shift_clk_div); - - tegra_dsi_set_timeout(dsi, bclk, config->refresh); - return plld/1000000; -} - - - -static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) -{ - unsigned long value; - - value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); - return 0; -} - -static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) -{ - u32 value; - - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); - - /* start calibration */ - tegra_dsi_pad_enable(dsi); - - value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | - DSI_PAD_OUT_CLK(0x0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); - - return tegra_mipi_calibrate(dsi->mipi); -} - -static const char * const error_report[16] = { - "SoT Error", - "SoT Sync Error", - "EoT Sync Error", - "Escape Mode Entry Command Error", - "Low-Power Transmit Sync Error", - "Peripheral Timeout Error", - "False Control Error", - "Contention Detected", - "ECC Error, single-bit", - "ECC Error, multi-bit", - "Checksum Error", - "DSI Data Type Not Recognized", - "DSI VC ID Invalid", - "Invalid Transmission Length", - "Reserved", - "DSI Protocol Violation", -}; - -static int tegra_dsi_read_response(struct tegra_dsi *dsi, - const struct mipi_dsi_msg *msg, - unsigned int count) -{ - u8 *rx = msg->rx_buf; - unsigned int i, j, k; - size_t size = 0; - u16 errors; - u32 value; - - /* read and parse packet header */ - value = tegra_dsi_readl(dsi, DSI_RD_DATA); - - switch (value & 0x3f) { - case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: - errors = (value >> 8) & 0xffff; - printk(BIOS_ERR, "Acknowledge and error report: %04x\n", - errors); - for (i = 0; i < ARRAY_SIZE(error_report); i++) - if (errors & BIT(i)) - printk(BIOS_INFO, " %2u: %s\n", i, - error_report[i]); - break; - - case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: - rx[0] = (value >> 8) & 0xff; - break; - - case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: - rx[0] = (value >> 8) & 0xff; - rx[1] = (value >> 16) & 0xff; - break; - - case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: - size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); - break; - - case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: - size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); - break; - - default: - printk(BIOS_ERR, "unhandled response type: %02x\n", - value & 0x3f); - break; - } - - size = MIN(size, msg->rx_len); - - if (msg->rx_buf && size > 0) { - for (i = 0, j = 0; i < count - 1; i++, j += 4) { - value = tegra_dsi_readl(dsi, DSI_RD_DATA); - - for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) - rx[j + k] = (value >> (k << 3)) & 0xff; - } - } - return 0; -} - -static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout_ms) -{ - u32 poll_interval_us = 2000; - u32 timeout_us = timeout_ms * 1000; - - tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); - udelay(poll_interval_us); - - do { - u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); - if ((value & DSI_TRIGGER_HOST) == 0) - return 0; - - //usleep_range(1000, 2000); - if (timeout_us > poll_interval_us) - timeout_us -= poll_interval_us; - else - break; - - udelay(poll_interval_us); - } while (1); - - printk(BIOS_ERR, "%s: ERROR: timeout waiting for transmission" - " to complete\n", __func__); - return -ETIMEDOUT; -} - -static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, - unsigned long timeout_ms) -{ - u32 poll_interval_us = 2000; - u32 timeout_us = timeout_ms * 1000; - - do { - u32 value = tegra_dsi_readl(dsi, DSI_STATUS); - u8 count = value & 0x1f; - - if (count > 0) - return count; - - if (timeout_us > poll_interval_us) - timeout_us -= poll_interval_us; - else - break; - - udelay(poll_interval_us); - } while (1); - - printk(BIOS_ERR, "%s: ERROR: timeout\n", __func__); - - return -ETIMEDOUT; -} - -static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, - const struct mipi_dsi_msg *msg) -{ - struct tegra_dsi *dsi = host_to_tegra(host); - const u8 *tx = msg->tx_buf; - unsigned int count, i, j; - u32 value; - int err; - - if (msg->tx_len > dsi->video_fifo_depth * 4) - return -ENOSPC; - - /* reset underflow/overflow flags */ - value = tegra_dsi_readl(dsi, DSI_STATUS); - if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { - value = DSI_HOST_CONTROL_FIFO_RESET; - tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); - udelay(20); // usleep_range(10, 20); - } - - value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); - value |= DSI_POWER_CONTROL_ENABLE; - tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); - - udelay(7000); //usleep_range(5000, 10000); - - value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | - DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; - - if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) - value |= DSI_HOST_CONTROL_HS; - - /* - * The host FIFO has a maximum of 64 words, so larger transmissions - * need to use the video FIFO. - */ - if (msg->tx_len > dsi->host_fifo_depth * 4) - value |= DSI_HOST_CONTROL_FIFO_SEL; - - tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); - - /* - * For reads and messages with explicitly requested ACK, generate a - * BTA sequence after the transmission of the packet. - */ - if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || - (msg->rx_buf && msg->rx_len > 0)) { - value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); - value |= DSI_HOST_CONTROL_PKT_BTA; - tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); - } - - value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; - tegra_dsi_writel(dsi, value, DSI_CONTROL); - - /* write packet header */ - value = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); - - if (tx && msg->tx_len > 0) - value |= tx[0] << 8; - - if (tx && msg->tx_len > 1) - value |= tx[1] << 16; - - tegra_dsi_writel(dsi, value, DSI_WR_DATA); - - /* write payload (if any) */ - if (msg->tx_len > 2) { - for (j = 2; j < msg->tx_len; j += 4) { - value = 0; - - for (i = 0; i < 4 && j + i < msg->tx_len; i++) - value |= tx[j + i] << (i << 3); - - tegra_dsi_writel(dsi, value, DSI_WR_DATA); - } - } - - err = tegra_dsi_transmit(dsi, 250); - if (err < 0) - return err; - - if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || - (msg->rx_buf && msg->rx_len > 0)) { - err = tegra_dsi_wait_for_response(dsi, 250); - if (err < 0) - return err; - - count = err; - - value = tegra_dsi_readl(dsi, DSI_RD_DATA); - switch (value) { - case 0x84: - /* - dev_dbg(dsi->dev, "ACK\n"); - */ - break; - - case 0x87: - /* - dev_dbg(dsi->dev, "ESCAPE\n"); - */ - break; - - default: - printk(BIOS_INFO, "unknown status: %08x\n", value); - break; - } - - if (count > 1) { - err = tegra_dsi_read_response(dsi, msg, count); - if (err < 0) - printk(BIOS_INFO, - "failed to parse response: %d\n", - err); - } - } - return 0; -} - -static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi, - struct tegra_dsi *slave) -{ - /* - * The number of ganged lanes is the sum of lanes of all peripherals - * in the gang. - */ - dsi->slave->ganged_lanes = dsi->lanes + dsi->slave->lanes; - dsi->slave->ganged_mode = 1; - - dsi->ganged_lanes = dsi->lanes + dsi->slave->lanes; - dsi->ganged_mode = 1; - return 0; -} - -static int tegra_dsi_host_attach(struct mipi_dsi_host *host, - struct mipi_dsi_device *device) -{ - struct tegra_dsi *dsi = host_to_tegra(host); - int err; - - dsi->flags = device->mode_flags; - dsi->format = device->format; - dsi->lanes = device->lanes; - - if (dsi->master) { - err = tegra_dsi_ganged_setup(dsi->master, dsi); - if (err < 0) { - printk(BIOS_ERR, "failed to set up ganged mode: %d\n", - err); - return err; - } - } - return 0; -} - -static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { - .attach = tegra_dsi_host_attach, - .transfer = tegra_dsi_host_transfer, -}; - -static int dsi_probe_if(int dsi_index, - struct soc_nvidia_tegra132_config *config) -{ - struct tegra_dsi *dsi = &dsi_data[dsi_index]; - int err; - - /* - * Set default value. Will be taken from attached device once detected - */ - dsi->flags = 0; - dsi->format = MIPI_DSI_FMT_RGB888; - dsi->lanes = 4; - - /* get tegra_mipi_device */ - dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index); - - /* calibrate */ - err = tegra_dsi_pad_calibrate(dsi); - if (err < 0) { - printk(BIOS_ERR, "MIPI calibration failed: %d\n", err); - return err; - } - - dsi->host.ops = &tegra_dsi_host_ops; - err = mipi_dsi_host_register(&dsi->host); - if (err < 0) { - printk(BIOS_ERR, "failed to register DSI host: %d\n", err); - return err; - } - - /* get panel */ - dsi->panel = panel_jdi_dsi_probe((struct mipi_dsi_device *)dsi->host.dev); - if (IS_ERR_PTR(dsi->panel)) { - printk(BIOS_ERR, "failed to get dsi panel\n"); - return -EPTR; - } - dsi->panel->mode = config; - return 0; -} - -static int dsi_probe(struct soc_nvidia_tegra132_config *config) -{ - dsi_probe_if(DSI_A, config); - dsi_probe_if(DSI_B, config); - return 0; -} - -static int dsi_enable(struct soc_nvidia_tegra132_config *config) -{ - struct tegra_dsi *dsi_a = &dsi_data[DSI_A]; - - dsi_probe(config); - - /* set up clock and TimeOutRegisters */ - tegra_output_dsi_setup_clock(dsi_a, config); - - /* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */ - write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI); - - /* configure phy interface timing registers */ - tegra_dsi_set_phy_timing(dsi_a); - - /* prepare panel */ - panel_jdi_prepare(dsi_a->panel); - - /* enable dsi */ - if (tegra_output_dsi_enable(dsi_a, config)) { - printk(BIOS_ERR,"%s: Error: failed to enable dsi output.\n", - __func__); - return -1; - } - - return 0; -} - -void dsi_display_startup(device_t dev) -{ - struct soc_nvidia_tegra132_config *config = dev->chip_info; - struct display_controller *disp_ctrl = - (void *)config->display_controller; - u32 plld_rate; - - u32 framebuffer_size_mb = config->framebuffer_size / MiB; - u32 framebuffer_base_mb= config->framebuffer_base / MiB; - - printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n", - __func__, disp_ctrl); - - if (disp_ctrl == NULL) { - printk(BIOS_ERR, "Error: No dc is assigned by dt.\n"); - return; - } - - if (framebuffer_size_mb == 0){ - framebuffer_size_mb = ALIGN_UP(config->display_xres * - config->display_yres * - (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; - } - - config->framebuffer_size = framebuffer_size_mb * MiB; - config->framebuffer_base = framebuffer_base_mb * MiB; - - /* - * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER - * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the - * update_display_mode() for detail. - */ - /* set default plld */ - plld_rate = clock_configure_plld(config->pixel_clock * 2); - if (plld_rate == 0) { - printk(BIOS_ERR, "dc: clock init failed\n"); - return; - } - - /* set disp1's clock source to PLLD_OUT0 */ - clock_configure_source(disp1, PLLD, (plld_rate/KHz)/2); - - /* Init dc */ - if (tegra_dc_init(disp_ctrl)) { - printk(BIOS_ERR, "dc: init failed\n"); - return; - } - - /* Configure dc mode */ - if (update_display_mode(disp_ctrl, config)) { - printk(BIOS_ERR, "dc: failed to configure display mode.\n"); - return; - } - - /* Configure and enable dsi controller and panel */ - if (dsi_enable(config)) { - printk(BIOS_ERR, "%s: failed to enable dsi controllers.\n", - __func__); - return; - } - - /* Set up window */ - update_window(config); - printk(BIOS_INFO, "%s: display init done.\n", __func__); - - /* Save panel information to cb tables */ - pass_mode_info_to_payload(config); - - /* - * After this point, it is payload's responsibility to allocate - * framebuffer and sets the base address to dc's - * WINBUF_START_ADDR register and enables window by setting dc's - * DISP_DISP_WIN_OPTIONS register. - */ -} diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c deleted file mode 100644 index 9c0c68cded..0000000000 --- a/src/soc/nvidia/tegra132/flow_ctrl.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/addressmap.h> -#include <soc/flow_ctrl.h> - -#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 -#define FLOW_CTRL_WAITEVENT (2 << 29) -#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) -#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) -#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) -#define FLOW_CTRL_CPU0_CSR 0x8 -#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) -#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) -#define FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) -#define FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) -#define FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) -#define FLOW_CTRL_CSR_ENABLE (1 << 0) -#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 -#define FLOW_CTRL_CPU1_CSR 0x18 - -#define HALT_REG_CORE0 (\ - FLOW_CTRL_WAIT_FOR_INTERRUPT | \ - FLOW_CTRL_HALT_LIC_IRQ | \ - FLOW_CTRL_HALT_LIC_FIQ) - -#define HALT_REG_CORE1 FLOW_CTRL_WAITEVENT - -static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE; - -static const uint8_t flowctrl_offset_halt_cpu[] = { - FLOW_CTRL_HALT_CPU0_EVENTS, - FLOW_CTRL_HALT_CPU1_EVENTS -}; - -static const uint8_t flowctrl_offset_cpu_csr[] = { - FLOW_CTRL_CPU0_CSR, - FLOW_CTRL_CPU1_CSR -}; - -static uint32_t flowctrl_read_cpu_csr(int cpu) -{ - return read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); -} - -static void flowctrl_write_cpu_csr(int cpu, uint32_t val) -{ - write32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu], val); - val = read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); -} - -void flowctrl_write_cpu_halt(int cpu, uint32_t val) -{ - write32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu], val); - val = read32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); -} - -static void flowctrl_prepare_cpu_off(int cpu) -{ - uint32_t reg; - - reg = flowctrl_read_cpu_csr(cpu); - reg &= ~FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ - reg &= ~FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ - reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ - reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ - reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu; /* power gating on wfi */ - reg |= FLOW_CTRL_CSR_ENABLE; /* enable power gating */ - flowctrl_write_cpu_csr(cpu, reg); -} - -void flowctrl_cpu_off(int cpu) -{ - uint32_t reg; - - reg = cpu ? HALT_REG_CORE1 : HALT_REG_CORE0; - flowctrl_prepare_cpu_off(cpu); - flowctrl_write_cpu_halt(cpu, reg); -} diff --git a/src/soc/nvidia/tegra132/funitcfg.c b/src/soc/nvidia/tegra132/funitcfg.c deleted file mode 100644 index 6dfad0d95e..0000000000 --- a/src/soc/nvidia/tegra132/funitcfg.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/funitcfg.h> -#include <soc/nvidia/tegra/usb.h> -#include <soc/padconfig.h> -#include <string.h> - -struct clk_dev_control { - uint32_t *clk_enb_set; - uint32_t *rst_dev_clr; -}; - -struct funit_cfg_data { - const char *name; - void *ctlr_base; - uint32_t *clk_src_reg; - const struct clk_dev_control * const dev_control; - uint32_t clk_enb_val; -}; - -enum { - CLK_L_SET = 0, - CLK_H_SET = 1, - CLK_U_SET = 2, - CLK_V_SET = 3, - CLK_W_SET = 4, - CLK_X_SET = 5, -}; - -#define CLK_SET_REGS(x) \ - { \ - CLK_RST_REG(clk_enb_##x##_set), \ - CLK_RST_REG(rst_dev_##x##_clr), \ - } - -static const struct clk_dev_control clk_data_arr[] = { - [CLK_L_SET] = CLK_SET_REGS(l), - [CLK_H_SET] = CLK_SET_REGS(h), - [CLK_U_SET] = CLK_SET_REGS(u), - [CLK_V_SET] = CLK_SET_REGS(v), - [CLK_W_SET] = CLK_SET_REGS(w), - [CLK_X_SET] = CLK_SET_REGS(x), -}; - -#define FUNIT_DATA(funit_, loname_, clk_set_) \ - [FUNIT_INDEX(funit_)] = { \ - .name = STRINGIFY(loname_), \ - .ctlr_base = (void *)(uintptr_t)TEGRA_##funit_##_BASE, \ - .clk_src_reg = CLK_RST_REG(clk_src_##loname_), \ - .dev_control = &clk_data_arr[CLK_##clk_set_##_SET], \ - .clk_enb_val = CLK_##clk_set_##_##funit_, \ - } - -#define FUNIT_DATA_USB(funit_, clk_set_) \ - [FUNIT_INDEX(funit_)] = { \ - .name = STRINGIFY(funit_), \ - .ctlr_base = (void *)(uintptr_t)TEGRA_##funit_##_BASE, \ - .dev_control = &clk_data_arr[CLK_##clk_set_##_SET], \ - .clk_enb_val = CLK_##clk_set_##_##funit_, \ - } - -static const struct funit_cfg_data funit_data[] = { - FUNIT_DATA(SBC1, sbc1, H), - FUNIT_DATA(SBC4, sbc4, U), - FUNIT_DATA(I2C1, i2c1, L), - FUNIT_DATA(I2C2, i2c2, H), - FUNIT_DATA(I2C3, i2c3, U), - FUNIT_DATA(I2C5, i2c5, H), - FUNIT_DATA(I2C6, i2c6, X), - FUNIT_DATA(SDMMC3, sdmmc3, U), - FUNIT_DATA(SDMMC4, sdmmc4, L), - FUNIT_DATA_USB(USBD, L), - FUNIT_DATA_USB(USB2, H), - FUNIT_DATA_USB(USB3, H), - FUNIT_DATA(I2S1, i2s1, L), -}; -_Static_assert(ARRAY_SIZE(funit_data) == FUNIT_INDEX_MAX, - "funit_cfg_data array not filled out!"); - -static inline uint32_t get_clk_src_freq(uint32_t clk_src_freq_id) -{ - uint32_t freq = 0; - - switch (clk_src_freq_id) { - case CLK_M: - freq = TEGRA_CLK_M_KHZ; - break; - case PLLP: - freq = TEGRA_PLLP_KHZ; - break; - default: - printk(BIOS_SPEW, "%s ERROR: Unknown clk_src %d\n", - __func__, clk_src_freq_id); - } - - return freq; -} - -static void configure_clock(const struct funit_cfg * const entry, - const struct funit_cfg_data * const funit) -{ - const char *funit_i2c = "i2c"; - uint32_t clk_div; - uint32_t clk_div_mask; - uint32_t clk_src_freq; - - clk_src_freq = get_clk_src_freq(entry->clk_src_freq_id); - - if (strncmp(funit->name, funit_i2c, strlen(funit_i2c)) == 0) { - /* I2C funit */ - clk_div = get_i2c_clk_div(clk_src_freq, - entry->clk_dev_freq_khz); - clk_div_mask = CLK_DIV_MASK_I2C; - } else { - /* Non I2C */ - clk_div = get_clk_div(clk_src_freq, entry->clk_dev_freq_khz); - clk_div_mask = CLK_DIV_MASK; - } - - _clock_set_div(funit->clk_src_reg, funit->name, clk_div, - clk_div_mask, entry->clk_src_id); -} - -static inline int is_usb(uint32_t idx) -{ - return (idx == FUNIT_USBD || idx == FUNIT_USB2 || idx == FUNIT_USB3); -} - -void soc_configure_funits(const struct funit_cfg * const entries, size_t num) -{ - size_t i; - - for (i = 0; i < num; i++) { - const struct funit_cfg * const entry = &entries[i]; - const struct funit_cfg_data *funit; - const struct clk_dev_control *dev_control; - int funit_usb = is_usb(entry->funit_index); - - if (entry->funit_index >= FUNIT_INDEX_MAX) { - printk(BIOS_ERR, "Error: Index out of bounds\n"); - continue; - } - - funit = &funit_data[entry->funit_index]; - dev_control = funit->dev_control; - - /* USB controllers have a fixed clock source. */ - if (!funit_usb) - configure_clock(entry, funit); - - clock_grp_enable_clear_reset(funit->clk_enb_val, - dev_control->clk_enb_set, - dev_control->rst_dev_clr); - - if (funit_usb) - usb_setup_utmip(funit->ctlr_base); - - soc_configure_pads(entry->pad_cfg,entry->pad_cfg_size); - } -} - -void __attribute__((weak)) usb_setup_utmip(void *usb_base) -{ - /* default empty implementation required if usb.c is not included */ - printk(BIOS_ERR, "USB setup is not supported in current stage\n"); -} diff --git a/src/soc/nvidia/tegra132/gic.c b/src/soc/nvidia/tegra132/gic.c deleted file mode 100644 index 983f39f5bc..0000000000 --- a/src/soc/nvidia/tegra132/gic.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <gic.h> -#include <soc/addressmap.h> - -void *gicd_base(void) -{ - return (void *)(uintptr_t)TEGRA_GICD_BASE; -} - -void *gicc_base(void) -{ - return (void *)(uintptr_t)TEGRA_GICC_BASE; -} diff --git a/src/soc/nvidia/tegra132/i2c.c b/src/soc/nvidia/tegra132/i2c.c deleted file mode 100644 index 35ee77712e..0000000000 --- a/src/soc/nvidia/tegra132/i2c.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/nvidia/tegra/i2c.h> - -struct tegra_i2c_bus_info tegra_i2c_info[] = { - { - .base = (void *)TEGRA_I2C1_BASE, - .reset_bit = CLK_L_I2C1, - .reset_func = &clock_reset_l - }, - { - .base = (void *)TEGRA_I2C2_BASE, - .reset_bit = CLK_H_I2C2, - .reset_func = &clock_reset_h - }, - { - .base = (void *)TEGRA_I2C3_BASE, - .reset_bit = CLK_U_I2C3, - .reset_func = &clock_reset_u - }, - { - .base = (void *)TEGRA_I2C4_BASE, - .reset_bit = CLK_V_I2C4, - .reset_func = &clock_reset_v - }, - { - .base = (void *)TEGRA_I2C5_BASE, - .reset_bit = CLK_H_I2C5, - .reset_func = &clock_reset_h - }, - { - .base = (void *)TEGRA_I2C6_BASE, - .reset_bit = CLK_X_I2C6, - .reset_func = &clock_reset_x - } -}; - -unsigned g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info); diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c deleted file mode 100644 index 890fc7dfe7..0000000000 --- a/src/soc/nvidia/tegra132/i2c6.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2014, NVIDIA CORPORATION. - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/clock.h> -#include <soc/nvidia/tegra/i2c.h> -#include <soc/padconfig.h> -#include <soc/power.h> - -#define I2C6_BUS 5 -#define I2C6_PADCTL 0xC001 -#define DPAUX_HYBRID_PADCTL 0x545C0124 - -static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; - -static int partition_clamp_on(int id) -{ - return read32(&pmc->clamp_status) & (1 << id); -} - -static void remove_clamps(int id) -{ - if (!partition_clamp_on(id)) - return; - - /* Remove clamp */ - write32(&pmc->remove_clamping_cmd, (1 << id)); - - /* Wait for clamp off */ - while (partition_clamp_on(id)) - ; -} - -static void enable_sor_periph_clocks(void) -{ - clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX); - - /* Give clocks time to stabilize. */ - udelay(IO_STABILIZATION_DELAY); -} - -static void disable_sor_periph_clocks(void) -{ - clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX); - - /* Give clocks time to stabilize. */ - udelay(IO_STABILIZATION_DELAY); -} - -static void unreset_sor_periphs(void) -{ - clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX); -} - -void soc_configure_i2c6pad(void) -{ - /* - * I2C6 on Tegra124/132 requires some special init. - * The SOR block must be unpowergated, and a couple of - * display-based peripherals must be clocked and taken - * out of reset so that a DPAUX register can be - * configured to enable the I2C6 mux routing. - * Afterwards, we can disable clocks to the display blocks - * and put Host1X back in reset. DPAUX must remain out of - * reset and the SOR partition must remained unpowergated. - */ - soc_configure_host1x(); - - /* Now we can write the I2C6 mux in DPAUX */ - write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); - - /* - * Delay before turning off Host1X/DPAUX clocks. - * This delay is needed to keep the sequence from - * hanging the system. - */ - udelay(CLOCK_PLL_STABLE_DELAY_US); - - /* Stop Host1X/DPAUX clocks and reset Host1X */ - disable_sor_periph_clocks(); - clock_set_reset_l(CLK_L_HOST1X); -} - -void soc_configure_host1x(void) -{ - power_ungate_partition(POWER_PARTID_SOR); - - /* Host1X needs a valid clock source so DPAUX can be accessed. */ - clock_configure_source(host1x, PLLP, 204000); - - enable_sor_periph_clocks(); - remove_clamps(POWER_PARTID_SOR); - unreset_sor_periphs(); -} diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h deleted file mode 100644 index fee67fe692..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ -#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ - -#include <stddef.h> -#include <stdint.h> - -enum { - TEGRA_SRAM_BASE = 0x40000000, - TEGRA_SRAM_SIZE = 0x40000 -}; - -enum { - TEGRA_ARM_PERIPHBASE = 0x50040000, - TEGRA_GICD_BASE = 0x50041000, - TEGRA_GICC_BASE = 0x50042000, - TEGRA_ARM_DISPLAYA = 0x54200000, - TEGRA_ARM_DISPLAYB = 0x54240000, - TEGRA_DSIA_BASE = 0x54300000, - TEGRA_DSIB_BASE = 0x54400000, - TEGRA_ARM_SOR = 0x54540000, - TEGRA_ARM_DPAUX = 0x545c0000, - TEGRA_PG_UP_BASE = 0x60000000, - TEGRA_TMRUS_BASE = 0x60005010, - TEGRA_CLK_RST_BASE = 0x60006000, - TEGRA_FLOW_BASE = 0x60007000, - TEGRA_GPIO_BASE = 0x6000D000, - TEGRA_EVP_BASE = 0x6000F000, - TEGRA_APB_DMA_BASE = 0x60020000, - TEGRA_APB_MISC_BASE = 0x70000000, - TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, - TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, - TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, - TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, - TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, - TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, - TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, - TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, - TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, - TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000, - TEGRA_I2C1_BASE = TEGRA_APB_MISC_BASE + 0xC000, - TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, - TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400, - TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500, - TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, - TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, - TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, - TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, - TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, - TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, - TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, - TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, - TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, - TEGRA_SBC1_BASE = TEGRA_SPI1_BASE, - TEGRA_SBC2_BASE = TEGRA_SPI2_BASE, - TEGRA_SBC3_BASE = TEGRA_SPI3_BASE, - TEGRA_SBC4_BASE = TEGRA_SPI4_BASE, - TEGRA_SBC5_BASE = TEGRA_SPI5_BASE, - TEGRA_SBC6_BASE = TEGRA_SPI6_BASE, - TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, - TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, - TEGRA_MC_BASE = 0x70019000, - TEGRA_EMC_BASE = 0x7001B000, - TEGRA_CLUSTER_CLOCK_BASE = 0x70040000, - TEGRA_CSITE_BASE = 0x70800000, - TEGRA_SDMMC_BASE = 0x700b0000, - TEGRA_SDMMC1_BASE = TEGRA_SDMMC_BASE + 0x0000, - TEGRA_SDMMC2_BASE = TEGRA_SDMMC_BASE + 0x0200, - TEGRA_SDMMC3_BASE = TEGRA_SDMMC_BASE + 0x0400, - TEGRA_SDMMC4_BASE = TEGRA_SDMMC_BASE + 0x0600, - TEGRA_MIPI_CAL_BASE = 0x700E3000, - TEGRA_SYSCTR0_BASE = 0x700F0000, - TEGRA_I2S1_BASE = 0x70301100, - TEGRA_USBD_BASE = 0x7D000000, - TEGRA_USB2_BASE = 0x7D004000, - TEGRA_USB3_BASE = 0x7D008000, -}; - -enum { - TEGRA_I2C_BASE_COUNT = 6, -}; - -/* Return total size of DRAM memory configured on the platform. */ -int sdram_size_mb(void); - -/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ -void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); -void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); - -enum { - CARVEOUT_TZ, - CARVEOUT_SEC, - CARVEOUT_MTS, - CARVEOUT_VPR, - CARVEOUT_NUM, -}; - -/* Provided the careout id, obtain the base and size in 1MiB units. */ -void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib); - -/* - * There are complications accessing the Trust Zone carveout region. The - * AVP cannot access these registers and the CPU can't access this register - * as a non-secure access. When the page tables live in non-secure memory - * these registers cannot be accessed either. Thus, this function handles - * both the AVP case and non-secured access case by keeping global state. - */ -void trustzone_region_init(void); - -#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/ccplex.h b/src/soc/nvidia/tegra132/include/soc/ccplex.h deleted file mode 100644 index 24b42f0043..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/ccplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_CCPLEX_H__ -#define __SOC_NVIDIA_TEGRA132_CCPLEX_H__ - -#include <stdint.h> - -#define MTS_LOAD_ADDRESS 0x82000000 - -/* Prepare the clocks and rails to start the cpu. */ -void ccplex_cpu_prepare(void); - -/* Loads the MTS microcode. Return 0 on success, < 0 on error. */ -int ccplex_load_mts(void); - -/* Start cpu0 and have it start executing at entry_addr */ -void ccplex_cpu_start(void *entry_addr); - -#endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clk_rst.h b/src/soc/nvidia/tegra132/include/soc/clk_rst.h deleted file mode 100644 index 46ab745eda..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/clk_rst.h +++ /dev/null @@ -1,558 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _TEGRA132_CLK_RST_H_ -#define _TEGRA132_CLK_RST_H_ -#include <stdint.h> -#include <stddef.h> - -/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct __attribute__ ((__packed__)) clk_rst_ctlr { - u32 rst_src; /* _RST_SOURCE, 0x000 */ - u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ - u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ - u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ - u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ - u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ - u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ - u32 _rsv0; /* 0x01c */ - u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ - u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ - u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ - u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ - u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ - u32 _rsv1[3]; /* 0x034-03c */ - u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ - u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ - u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ - u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ - u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ - u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ - u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ - u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ - u32 _rsv2[8]; /* 0x060-07C */ - u32 pllc_base; /* _PLLC_BASE, 0x080 */ - u32 pllc_out; /* _PLLC_OUT, 0x084 */ - u32 pllc_misc2; /* _PLLC_MISC2, 0x088 */ - u32 pllc_misc; /* _PLLC_MISC, 0x08c */ - u32 pllm_base; /* _PLLM_BASE, 0x090 */ - u32 pllm_out; /* _PLLM_OUT, 0x094 */ - u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ - u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ - u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ - u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ - u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ - u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ - u32 plla_base; /* _PLLA_BASE, 0x0b0 */ - u32 plla_out; /* _PLLA_OUT, 0x0b4 */ - u32 _rsv3; /* 0x0b8 */ - u32 plla_misc; /* _PLLA_MISC, 0x0bc */ - u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ - u32 _rsv4[2]; /* 0x0c4-0c8 */ - u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ - u32 plld_base; /* _PLLD_BASE, 0x0d0 */ - u32 _rsv5[2]; /* 0x0d4-0d8 */ - u32 plld_misc; /* _PLLD_MISC, 0x0dc */ - u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ - u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ - u32 plle_base; /* _PLLE_BASE, 0x0e8 */ - u32 plle_misc; /* _PLLE_MISC, 0x0ec */ - u32 plls_base; /* _PLLS_BASE, 0x0f0 */ - u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ - u32 _rsv6[2]; /* 0x0f8-0fc */ - u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ - u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ - u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ - u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ - u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ - u32 _rsv7; /* 0x114 */ - u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ - u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ - u32 _rsv8; /* 0x120 */ - u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ - u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ - u32 _rsv9[2]; /* 0x12c-130 */ - u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ - u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ - u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ - u32 _rsv10[2]; /* 0x140-144 */ - u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ - u32 _rsv11; /* 0x14c */ - u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ - u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ - u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ - u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ - u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ - u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ - u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ - u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ - u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ - u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ - u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ - u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ - u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ - u32 _rsv12[2]; /* 0x184-188 */ - u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ - u32 _rsv13[2]; /* 0x190-194 */ - u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ - u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ - u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ - u32 _rsv14; /* 0x1a4 */ - u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ - u32 _rsv15[2]; /* 0x1ac-1b0 */ - u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ - u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ - u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ - u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ - u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ - u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ - u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ - u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ - u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ - u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ - u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ - u32 _rsv16[4]; /* 0x1e0-1ec */ - u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ - u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ - u32 _rsv17; /* 0x1f8 */ - u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ - u32 _rsv18[32]; /* 0x200-27c */ - u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - u32 rst_dev_x; /* _RST_DEVICES_X_0, 0x28c */ - u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - u32 _rsv19[23]; /* 0x298-2f0 */ - u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - u32 _rsv20[2]; /* 0x2f8-2fc */ - u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ - u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ - u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ - u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ - u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ - u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ - u32 _rsv21[2]; /* 0x318-31c */ - u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ - u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ - u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ - u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ - u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ - u32 clk_enb_u_clr; /* _CLK_ENB_U_CLR 0x334 */ - u32 _rsv22; /* 0x338 */ - u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ - u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ - u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ - u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ - u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ - u32 _rsv23[2]; /* 0x350-354 */ - u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ - u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ - u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ - u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ - u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ - u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ - u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ - u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ - u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ - u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ - u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ - u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ - u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ - u32 _rsv24[9]; /* 0x38c-3ac */ - u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ - u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ - u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ - u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ - u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ - u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ - u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ - u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ - u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ - u32 _rsv25; /* 0x3d4 */ - u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ - u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ - u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ - u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ - u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ - u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ - u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ - u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ - u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ - u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ - u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ - u32 _rsv26[4]; /* 0x404-410 */ - u32 clk_src_sor; /* _CLK_SOURCE_SOR_0, 0x414 */ - u32 _rsv261[2]; /* 0x404-410 */ - u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ - u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ - u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ - u32 _rsv27; /* 0x42c */ - u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ - u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ - u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ - u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ - u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ - u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ - u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ - u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ - u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ - u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ - u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ - u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ - u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ - u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ - u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ - u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ - u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ - u32 _rsv28; /* 0x474 */ - u32 intstatus; /* _INTSTATUS, 0x478 */ - u32 intmask; /* _INTMASK, 0x47c */ - u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ - u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ - u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ - u32 plle_aux; /* _PLLE_AUX, 0x48c */ - u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ - u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ - u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ - u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ - u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ - u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ - u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ - u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ - u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ - u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ - u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ - u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ - u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ - u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ - u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ - u32 _rsv29[7]; /* 0x4cc-4e4 */ - u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ - u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ - u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ - u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ - u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ - u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ - u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ - u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ - u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ - u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ - u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ - u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ - u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ - u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ - u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ - u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ - u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ - u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ - u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ - u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ - u32 _rsv30; /* 0x538 */ - u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ - u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ - u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ - u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ - u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ - u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ - u32 _rsv31; /* 0x554 */ - u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ - u32 spare_reg0; /* _SPARE_REG0, 0x55c */ - u32 _rsv32[4]; /* 0x560-0x56c */ - u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - u32 _rsv32_1[7]; /* 0x574-58c */ - u32 plldp_base; /* _PLLDP_BASE, 0x590 */ - u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ - u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ - u32 _rsrv32_2[25]; - u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ - u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ - u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ - u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ - u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ - u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ - u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ - u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ - u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ - u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ - u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ - u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ - u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ - u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ - u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ - u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ - u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ - u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ - u32 _rsv33[5]; /* 0x648-658 */ - u32 clk_src_i2c6; /* _CLK_SOURCE_I2C6, 0x65c */ -}; -check_member(clk_rst_ctlr, clk_src_i2c6, 0x65C); - -#define CLK_RST_REG(field_) \ - (&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_)) - -/* L, H, U, V, W, X */ -#define DEV_CONFIG_BLOCKS 6 - -#define TEGRA_DEV_L 0 -#define TEGRA_DEV_H 1 -#define TEGRA_DEV_U 2 -#define TEGRA_DEV_V 0 -#define TEGRA_DEV_W 1 - -#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) - -/* Bits to enable/reset modules */ -#define CLK_ENB_CPU (1 << 0) -#define SWR_TRIG_SYS_RST (1 << 2) -#define SWR_CSITE_RST (1 << 9) -#define CLK_ENB_CSITE (1 << 9) - -/* CRC_SUPER_CCLK_DIVIDER_0 0x24 */ -#define SUPER_CDIV_ENB_ENABLE (1 << 31) - -/* CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 */ -#define EN_PPSB_STOPCLK (1 << 0) - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4C) */ -#define CPU3_CLK_STP_SHIFT 11 -#define CPU2_CLK_STP_SHIFT 10 -#define CPU1_CLK_STP_SHIFT 9 -#define CPU0_CLK_STP_SHIFT 8 -#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) - -/* CRC_OSC_CTRL_0 0x50 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT) -#define OSC_PREDIV_SHIFT 26 -#define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT) -#define OSC_XOFS_SHIFT 4 -#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) -#define OSC_DRIVE_STRENGTH 7 -#define OSC_XOBP (1 << 1) -#define OSC_XOE (1 << 0) - -enum { - OSC_FREQ_12 = 8, /* 12.0MHz */ - OSC_FREQ_13 = 0, /* 13.0MHz */ - OSC_FREQ_16P8 = 1, /* 16.8MHz */ - OSC_FREQ_19P2 = 4, /* 19.2MHz */ - OSC_FREQ_26 = 12, /* 26.0MHz */ - OSC_FREQ_38P4 = 5, /* 38.4MHz */ - OSC_FREQ_48 = 9, /* 48.0MHz */ -}; - -/* CLK_RST_CONTROLLER_PLL*_BASE_0 */ -#define PLL_BASE_BYPASS (1U << 31) -#define PLL_BASE_ENABLE (1U << 30) -#define PLL_BASE_REF_DIS (1U << 29) -#define PLL_BASE_OVRRIDE (1U << 28) -#define PLL_BASE_LOCK (1U << 27) - -#define PLL_BASE_DIVP_SHIFT 20 -#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) - -#define PLL_BASE_DIVN_SHIFT 8 -#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) - -#define PLL_BASE_DIVM_SHIFT 0 -#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) - -/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ -#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) -#define PLLM_BASE_DIVP_MASK (0x1U << PLL_BASE_DIVP_SHIFT) -#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) -#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) - -/* PLLM specific registers */ -#define PLLM_MISC1_SETUP_SHIFT 0 -#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 -#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 -#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 -#define PLLM_MISC2_KCP_SHIFT 1 -#define PLLM_MISC2_KVCO_SHIFT 0 -#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) - -/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits - * on the side that we don't particularly care about. */ -#define PLL_BASE_DIV_MASK (0xffffff) - -/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ -#define PLL_OUT_RSTN (1 << 0) -#define PLL_OUT_CLKEN (1 << 1) -#define PLL_OUT_OVR (1 << 2) - -#define PLL_OUT_RATIO_SHIFT 8 -#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) - -#define PLL_OUT1_SHIFT 0 -#define PLL_OUT2_SHIFT 16 -#define PLL_OUT3_SHIFT 0 -#define PLL_OUT4_SHIFT 16 - -/* CLK_RST_CONTROLLER_PLL*_MISC_0 */ -#define PLL_MISC_DCCON (1 << 20) - -#define PLL_MISC_CPCON_SHIFT 8 -#define PLL_MISC_CPCON_MASK (0xfU << PLL_MISC_CPCON_SHIFT) - -#define PLL_MISC_LFCON_SHIFT 4 -#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT) - -/* This bit is different all over the place. Oh joy... */ -#define PLLDPD2_MISC_LOCK_ENABLE (1 << 30) -#define PLLC_MISC_LOCK_ENABLE (1 << 24) -#define PLLUD_MISC_LOCK_ENABLE (1 << 22) -#define PLLD_MISC_CLK_ENABLE (1 << 30) -#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) -#define PLLE_MISC_LOCK_ENABLE (1 << 9) - -#define PLLU_MISC_VCO_FREQ (1 << 20) - -/* PLLX_BASE_0 0xe0 */ -#define PLLX_BASE_PLLX_ENABLE (1 << 30) - -/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ -#define PLLX_IDDQ_SHIFT 3 -#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) - -#define CLK_DIVISOR_MASK (0xffff) - -#define CLK_SOURCE_SHIFT 29 -#define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) - -#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) - -#define CLK_UART_DIV_OVERRIDE (1 << 24) - -/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ -#define SCLK_SYS_STATE_SHIFT 28U -#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) -enum { - SCLK_SYS_STATE_STDBY, - SCLK_SYS_STATE_IDLE, - SCLK_SYS_STATE_RUN, - SCLK_SYS_STATE_IRQ = 4U, - SCLK_SYS_STATE_FIQ = 8U, -}; -#define SCLK_COP_FIQ_MASK (1 << 27) -#define SCLK_CPU_FIQ_MASK (1 << 26) -#define SCLK_COP_IRQ_MASK (1 << 25) -#define SCLK_CPU_IRQ_MASK (1 << 24) - -#define SCLK_FIQ_SHIFT 12 -#define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT) -#define SCLK_IRQ_SHIFT 8 -#define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT) -#define SCLK_RUN_SHIFT 4 -#define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT) -#define SCLK_IDLE_SHIFT 0 -#define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT) -enum { - SCLK_SOURCE_CLKM, - SCLK_SOURCE_PLLC_OUT1, - SCLK_SOURCE_PLLP_OUT4, - SCLK_SOURCE_PLLP_OUT3, - SCLK_SOURCE_PLLP_OUT2, - SCLK_SOURCE_PLLC_OUT0, - SCLK_SOURCE_CLKS, - SCLK_SOURCE_PLLM_OUT1, -}; - -/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */ -#define SCLK_DIV_ENB (1 << 31) -#define SCLK_DIVIDEND_SHIFT 8 -#define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT) -#define SCLK_DIVISOR_SHIFT 0 -#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) - -/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ -#define HCLK_DISABLE (1 << 7) -#define HCLK_DIVISOR_SHIFT 4 -#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) -#define PCLK_DISABLE (1 << 3) -#define PCLK_DIVISOR_SHIFT 0 -#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) - -/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ -#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) - -/* CRC_CLK_ENB_V_SET_0 0x440 */ -#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) -#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) -#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ -#define PLLU_POWERDOWN (1 << 16) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLL_ACTIVE_POWERDOWN (1 << 12) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) - -// CCLK_BRST_POL -enum { - CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, - CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 -}; - -// SUPER_CCLK_DIVIDER -enum { - CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 -}; - -// CLK_CPU_CMPLX_CLR -enum { - CRC_CLK_CLR_CPU0_STP = 0x1 << 8, - CRC_CLK_CLR_CPU1_STP = 0x1 << 9, - CRC_CLK_CLR_CPU2_STP = 0x1 << 10, - CRC_CLK_CLR_CPU3_STP = 0x1 << 11 -}; - -// RST_CPUG_CMPLX_CLR -enum { - CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, - CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, - CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, - CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, - CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, - CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, - CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, - CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, - CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, - CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, - CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, - CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, - CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, - CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, - CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, - CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, - CRC_RST_CPUG_CLR_L2 = 0x1 << 24, - CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, - CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, -}; - -// RST_CPULP_CMPLX_CLR -enum { - CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, - CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, - CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, - CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, - CRC_RST_CPULP_CLR_L2 = 0x1 << 24, - CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, - CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, -}; - -#endif /* _TEGRA132_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h deleted file mode 100644 index e8ae9f26c5..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_CLOCK_H__ -#define __SOC_NVIDIA_TEGRA132_CLOCK_H__ - -#include <arch/hlt.h> -#include <arch/io.h> -#include <console/console.h> -#include <soc/clk_rst.h> -#include <stdint.h> -#include <stdlib.h> - -enum { - CLK_L_CPU = 0x1 << 0, - CLK_L_COP = 0x1 << 1, - CLK_L_TRIG_SYS = 0x1 << 2, - CLK_L_RTC = 0x1 << 4, - CLK_L_TMR = 0x1 << 5, - CLK_L_UARTA = 0x1 << 6, - CLK_L_UARTB = 0x1 << 7, - CLK_L_GPIO = 0x1 << 8, - CLK_L_SDMMC2 = 0x1 << 9, - CLK_L_SPDIF = 0x1 << 10, - CLK_L_I2S1 = 0x1 << 11, - CLK_L_I2C1 = 0x1 << 12, - CLK_L_NDFLASH = 0x1 << 13, - CLK_L_SDMMC1 = 0x1 << 14, - CLK_L_SDMMC4 = 0x1 << 15, - CLK_L_PWM = 0x1 << 17, - CLK_L_I2S2 = 0x1 << 18, - CLK_L_EPP = 0x1 << 19, - CLK_L_VI = 0x1 << 20, - CLK_L_2D = 0x1 << 21, - CLK_L_USBD = 0x1 << 22, - CLK_L_ISP = 0x1 << 23, - CLK_L_3D = 0x1 << 24, - CLK_L_DISP2 = 0x1 << 26, - CLK_L_DISP1 = 0x1 << 27, - CLK_L_HOST1X = 0x1 << 28, - CLK_L_VCP = 0x1 << 29, - CLK_L_I2S0 = 0x1 << 30, - CLK_L_CACHE2 = 0x1 << 31, - - CLK_H_MEM = 0x1 << 0, - CLK_H_AHBDMA = 0x1 << 1, - CLK_H_APBDMA = 0x1 << 2, - CLK_H_KBC = 0x1 << 4, - CLK_H_STAT_MON = 0x1 << 5, - CLK_H_PMC = 0x1 << 6, - CLK_H_FUSE = 0x1 << 7, - CLK_H_KFUSE = 0x1 << 8, - CLK_H_SBC1 = 0x1 << 9, - CLK_H_SNOR = 0x1 << 10, - CLK_H_JTAG2TBC = 0x1 << 11, - CLK_H_SBC2 = 0x1 << 12, - CLK_H_SBC3 = 0x1 << 14, - CLK_H_I2C5 = 0x1 << 15, - CLK_H_DSI = 0x1 << 16, - CLK_H_HSI = 0x1 << 18, - CLK_H_HDMI = 0x1 << 19, - CLK_H_CSI = 0x1 << 20, - CLK_H_I2C2 = 0x1 << 22, - CLK_H_UARTC = 0x1 << 23, - CLK_H_MIPI_CAL = 0x1 << 24, - CLK_H_EMC = 0x1 << 25, - CLK_H_USB2 = 0x1 << 26, - CLK_H_USB3 = 0x1 << 27, - CLK_H_MPE = 0x1 << 28, - CLK_H_VDE = 0x1 << 29, - CLK_H_BSEA = 0x1 << 30, - CLK_H_BSEV = 0x1 << 31, - - CLK_U_UARTD = 0x1 << 1, - CLK_U_UARTE = 0x1 << 2, - CLK_U_I2C3 = 0x1 << 3, - CLK_U_SBC4 = 0x1 << 4, - CLK_U_SDMMC3 = 0x1 << 5, - CLK_U_PCIE = 0x1 << 6, - CLK_U_OWR = 0x1 << 7, - CLK_U_AFI = 0x1 << 8, - CLK_U_CSITE = 0x1 << 9, - CLK_U_PCIEXCLK = 0x1 << 10, - CLK_U_AVPUCQ = 0x1 << 11, - CLK_U_TRACECLKIN = 0x1 << 13, - CLK_U_SOC_THERM = 0x1 << 14, - CLK_U_DTV = 0x1 << 15, - CLK_U_NAND_SPEED = 0x1 << 16, - CLK_U_I2C_SLOW = 0x1 << 17, - CLK_U_DSIB = 0x1 << 18, - CLK_U_TSEC = 0x1 << 19, - CLK_U_IRAMA = 0x1 << 20, - CLK_U_IRAMB = 0x1 << 21, - CLK_U_IRAMC = 0x1 << 22, - - // Clock reset. - CLK_U_EMUCIF = 0x1 << 23, - // Clock enable. - CLK_U_IRAMD = 0x1 << 23, - - CLK_U_CRAM2 = 0x2 << 24, - CLK_U_XUSB_HOST = 0x1 << 25, - CLK_U_MSENC = 0x1 << 27, - CLK_U_SUS_OUT = 0x1 << 28, - CLK_U_DEV2_OUT = 0x1 << 29, - CLK_U_DEV1_OUT = 0x1 << 30, - CLK_U_XUSB_DEV = 0x1 << 31, - - CLK_V_CPUG = 0x1 << 0, - CLK_V_CPULP = 0x1 << 1, - CLK_V_3D2 = 0x1 << 2, - CLK_V_MSELECT = 0x1 << 3, - CLK_V_I2S3 = 0x1 << 5, - CLK_V_I2S4 = 0x1 << 6, - CLK_V_I2C4 = 0x1 << 7, - CLK_V_SBC5 = 0x1 << 8, - CLK_V_SBC6 = 0x1 << 9, - CLK_V_AUDIO = 0x1 << 10, - CLK_V_APBIF = 0x1 << 11, - CLK_V_DAM0 = 0x1 << 12, - CLK_V_DAM1 = 0x1 << 13, - CLK_V_DAM2 = 0x1 << 14, - CLK_V_HDA2CODEC_2X = 0x1 << 15, - CLK_V_ATOMICS = 0x1 << 16, - CLK_V_ACTMON = 0x1 << 23, - CLK_V_EXTPERIPH1 = 0x1 << 24, - CLK_V_SATA = 0x1 << 28, - CLK_V_HDA = 0x1 << 29, - - CLK_W_HDA2HDMICODEC = 0x1 << 0, - CLK_W_SATACOLD = 0x1 << 1, - CLK_W_CEC = 0x1 << 8, - CLK_W_XUSB_PADCTL = 0x1 << 14, - CLK_W_ENTROPY = 0x1 << 21, - CLK_W_DP2 = 0x1 << 24, - CLK_W_AMX0 = 0x1 << 25, - CLK_W_ADX0 = 0x1 << 26, - CLK_W_DVFS = 0x1 << 27, - CLK_W_XUSB_SS = 0x1 << 28, - CLK_W_MC1 = 0x1 << 30, - CLK_W_EMC1 = 0x1 << 31, - - CLK_X_AFC0 = 0x1 << 31, - CLK_X_AFC1 = 0x1 << 30, - CLK_X_AFC2 = 0x1 << 29, - CLK_X_AFC3 = 0x1 << 28, - CLK_X_AFC4 = 0x1 << 27, - CLK_X_AFC5 = 0x1 << 26, - CLK_X_AMX1 = 0x1 << 25, - CLK_X_GPU = 0x1 << 24, - CLK_X_SOR0 = 0x1 << 22, - CLK_X_DPAUX = 0x1 << 21, - CLK_X_ADX1 = 0x1 << 20, - CLK_X_VIC = 0x1 << 18, - CLK_X_CLK72MHZ = 0x1 << 17, - CLK_X_HDMI_AUDIO = 0x1 << 16, - CLK_X_EMC_DLL = 0x1 << 14, - CLK_X_VIM2_CLK = 0x1 << 11, - CLK_X_I2C6 = 0x1 << 6, - CLK_X_CAM_MCLK2 = 0x1 << 5, - CLK_X_CAM_MCLK = 0x1 << 4, - CLK_X_SPARE = 0x1 << 0, -}; - -enum { - PLLP = 0, - PLLC2 = 1, - PLLC = 2, - PLLC3 = 3, - PLLM = 4, - CLK_M = 5, - CLK_S = 6, - PLLE = 7, - PLLA = 8, - PLLD = 9, - PLLD2 = 10, - UNUSED = 100, - UNUSED1 = 101, - UNUSED2 = 102, - UNUSED3 = 103, -}; - -#define CLK_SRC_DEV_ID(dev, src) CLK_SRC_##dev##_##src -#define CLK_SRC_FREQ_ID(dev, src) CLK_SRC_FREQ_##dev##_##src - -#define CLK_SRC_DEVICE(dev, a, b, c, d, e, f, g) \ - CLK_SRC_DEV_ID(dev, a) = 0, \ - CLK_SRC_DEV_ID(dev, b) = 1, \ - CLK_SRC_DEV_ID(dev, c) = 2, \ - CLK_SRC_DEV_ID(dev, d) = 3, \ - CLK_SRC_DEV_ID(dev, e) = 4, \ - CLK_SRC_DEV_ID(dev, f) = 5, \ - CLK_SRC_DEV_ID(dev, g) = 6, \ - CLK_SRC_FREQ_ID(dev, a) = a, \ - CLK_SRC_FREQ_ID(dev, b) = b, \ - CLK_SRC_FREQ_ID(dev, c) = c, \ - CLK_SRC_FREQ_ID(dev, d) = d, \ - CLK_SRC_FREQ_ID(dev, e) = e, \ - CLK_SRC_FREQ_ID(dev, f) = f, \ - CLK_SRC_FREQ_ID(dev, g) = g - -enum { - CLK_SRC_DEVICE(disp1, PLLP, PLLM, PLLD, PLLA, PLLC, PLLD2, CLK_M), - CLK_SRC_DEVICE(host1x, PLLM, PLLC2, PLLC, PLLC3, PLLP, UNUSED, PLLA), - CLK_SRC_DEVICE(I2C1, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(I2C2, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(I2C3, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(I2C5, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(I2C6, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(I2S1, PLLA, UNUSED, CLK_S, UNUSED1, PLLP, UNUSED2, CLK_M), - CLK_SRC_DEVICE(mselect, PLLP, PLLC2, PLLC, PLLC3, PLLM, CLK_S, CLK_M), - CLK_SRC_DEVICE(SBC1, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(SBC4, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(SDMMC3, PLLP, PLLC2, PLLC, PLLC3, PLLM, PLLE, CLK_M), - CLK_SRC_DEVICE(SDMMC4, PLLP, PLLC2, PLLC, PLLC3, PLLM, PLLE, CLK_M), - CLK_SRC_DEVICE(UARTA, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M), - CLK_SRC_DEVICE(i2s1, PLLA, UNUSED, CLK_S, UNUSED1, PLLP, UNUSED2, CLK_M), - CLK_SRC_DEVICE(extperiph1, PLLA, CLK_S, PLLP, CLK_M, PLLE, UNUSED, UNUSED1), -}; - -/* PLL stabilization delay in usec */ -#define CLOCK_PLL_STABLE_DELAY_US 300 - -#define IO_STABILIZATION_DELAY (2) -#define LOGIC_STABILIZATION_DELAY (2) - -/* Calculate clock fractional divider value from ref and target frequencies. - * This is for a U7.1 format. This is not well written up in the book and - * there have been some questions about this macro, so here we go. - * U7.1 format is defined as (ddddddd+1) + (h*.5) - * The lowest order bit is actually a fractional bit. - * Hence, the divider can be thought of as 9 bits. - * So: - * divider = ((ref/freq) << 1 - 1) (upper 7 bits) | - * (ref/freq & 1) (low order half-bit) - * however we can't do fractional arithmetic ... these are integers! - * So we normalize by shifting the result left 1 bit, and extracting - * ddddddd and h directly to the returned u8. - * divider = 2*(ref/freq); - * We want to - * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as - * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely - * situated in the upper 7 bits, and the h is sitting there in the low order - * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number - * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you - * will assign this to a u8, it gets nicely truncated for you. - */ -#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2) - -/* Calculate clock frequency value from reference and clock divider value - * The discussion in the book is pretty lacking. - * The idea is that we need to divide a ref clock by a divisor - * in U7.1 format, where 7 upper bits are the integer - * and lowest order bit is a fraction. - * from the book, U7.1 is (ddddddd+1) + (h*.5) - * To normalize to an actual number, we might do this: - * ((d>>7+1)&0x7f) + (d&1 >> 1) - * but as you might guess, the low order bit would be lost. - * Since we can't express the fractional bit, we need to multiply it all by 2. - * ((d + 2)&0xfe) + (d & 1) - * Since we're just adding +2, the lowest order bit is preserved. Hence - * (d+2) is the same as ((d + 2)&0xfe) + (d & 1) - * - * Since you multiply denominator * 2 (by NOT shifting it), - * you multiply numerator * 2 to cancel it out. - */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) - -static inline void _clock_set_div(u32 *reg, const char *name, u32 div, - u32 div_mask, u32 src) -{ - // The I2C and UART divisors are 16 bit while all the others are 8 bit. - // The I2C clocks are handled by the specialized macro below, but the - // UART clocks aren't. Don't use this function on UART clocks. - if (div & ~div_mask) { - printk(BIOS_ERR, "%s clock divisor overflow!", name); - hlt(); - } - clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - src << CLK_SOURCE_SHIFT | div); -} - -#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1) -#define get_clk_div(src,freq) CLK_DIVIDER(src,freq) -#define CLK_DIV_MASK 0xff -#define CLK_DIV_MASK_I2C 0xffff - -#define clock_configure_source(device, src, freq) \ - _clock_set_div(CLK_RST_REG(clk_src_##device), #device, \ - get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, \ - CLK_SRC_DEV_ID(device, src)) - -/* soc-specific */ -#define TEGRA_CLK_M_KHZ clock_get_osc_khz() -#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ -#define TEGRA_PLLP_KHZ (408000) -#define TEGRA_PLLC_KHZ (600000) -#define TEGRA_PLLD_KHZ (925000) -#define TEGRA_PLLU_KHZ (960000) - -#define clock_enable(l, h, u, v, w, x) \ - do { \ - u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \ - clock_enable_regs(bits); \ - } while (0) - -#define clock_disable(l, h, u, v, w, x) \ - do { \ - u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \ - clock_disable_regs(bits); \ - } while (0) - -#define clock_set_reset(l, h, u, v, w, x) \ - do { \ - u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \ - clock_set_reset_regs(bits); \ - } while (0) - -#define clock_clr_reset(l, h, u, v, w, x) \ - do { \ - u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x}; \ - clock_clr_reset_regs(bits); \ - } while (0) - -#define clock_enable_l(l) clock_enable(l, 0, 0, 0, 0, 0) -#define clock_enable_h(h) clock_enable(0, h, 0, 0, 0, 0) -#define clock_enable_u(u) clock_enable(0, 0, u, 0, 0, 0) -#define clock_enable_v(v) clock_enable(0, 0, 0, v, 0, 0) -#define clock_enable_w(w) clock_enable(0, 0, 0, 0, w, 0) -#define clock_enable_x(x) clock_enable(0, 0, 0, 0, 0, x) - -#define clock_disable_l(l) clock_disable(l, 0, 0, 0, 0, 0) -#define clock_disable_h(h) clock_disable(0, h, 0, 0, 0, 0) -#define clock_disable_u(u) clock_disable(0, 0, u, 0, 0, 0) -#define clock_disable_v(v) clock_disable(0, 0, 0, v, 0, 0) -#define clock_disable_w(w) clock_disable(0, 0, 0, 0, w, 0) -#define clock_disable_x(x) clock_disable(0, 0, 0, 0, 0, x) - -#define clock_set_reset_l(l) clock_set_reset(l, 0, 0, 0, 0, 0) -#define clock_set_reset_h(h) clock_set_reset(0, h, 0, 0, 0, 0) -#define clock_set_reset_u(u) clock_set_reset(0, 0, u, 0, 0, 0) -#define clock_set_reset_v(v) clock_set_reset(0, 0, 0, v, 0, 0) -#define clock_set_reset_w(w) clock_set_reset(0, 0, 0, 0, w, 0) -#define clock_set_reset_x(x) clock_set_reset(0, 0, 0, 0, 0, x) - -#define clock_clr_reset_l(l) clock_clr_reset(l, 0, 0, 0, 0, 0) -#define clock_clr_reset_h(h) clock_clr_reset(0, h, 0, 0, 0, 0) -#define clock_clr_reset_u(u) clock_clr_reset(0, 0, u, 0, 0, 0) -#define clock_clr_reset_v(v) clock_clr_reset(0, 0, 0, v, 0, 0) -#define clock_clr_reset_w(w) clock_clr_reset(0, 0, 0, 0, w, 0) -#define clock_clr_reset_x(x) clock_clr_reset(0, 0, 0, 0, 0, x) - -#define clock_enable_clear_reset_l(l) \ - clock_enable_clear_reset(l, 0, 0, 0, 0, 0) -#define clock_enable_clear_reset_h(h) \ - clock_enable_clear_reset(0, h, 0, 0, 0, 0) -#define clock_enable_clear_reset_u(u) \ - clock_enable_clear_reset(0, 0, u, 0, 0, 0) -#define clock_enable_clear_reset_v(v) \ - clock_enable_clear_reset(0, 0, 0, v, 0, 0) -#define clock_enable_clear_reset_w(w) \ - clock_enable_clear_reset(0, 0, 0, 0, w, 0) -#define clock_enable_clear_reset_x(x) \ - clock_enable_clear_reset(0, 0, 0, 0, 0, x) - -int clock_get_osc_khz(void); -int clock_get_pll_input_khz(void); -/* - * Configure PLLD to requested frequency. Returned value is closest match - * within the PLLD's constraints or 0 if an error. - */ -u32 clock_configure_plld(u32 frequency); -void clock_early_uart(void); -void clock_external_output(int clk_id); -void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, - u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, - u32 same_freq); -void clock_cpu0_config(void); -void clock_halt_avp(void); -void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]); -void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]); -void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); -void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); -void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); -void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg); -void clock_reset_l(u32 l); -void clock_reset_h(u32 h); -void clock_reset_u(u32 u); -void clock_reset_v(u32 v); -void clock_reset_w(u32 w); -void clock_reset_x(u32 x); -void clock_init(void); -void clock_init_arm_generic_timer(void); -void sor_clock_stop(void); -void sor_clock_start(void); -void clock_enable_audio(void); - -#endif /* __SOC_NVIDIA_TEGRA132_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clst_clk.h b/src/soc/nvidia/tegra132/include/soc/clst_clk.h deleted file mode 100644 index 0d5f68133b..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/clst_clk.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _TEGRA132_CLST_CLK_H_ -#define _TEGRA132_CLST_CLK_H_ - -/* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ -struct __attribute__ ((__packed__)) clst_clk_ctlr { - u32 pllx_base; /* _PLLX_BASE, 0x000 */ - u32 pllx_misc; /* _PLLX_MISC, 0x004 */ - u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ - u32 pllx_misc2; /* _PLLX_MISC_2, 0x00c */ - u32 pllx_misc3; /* _PLLX_MISC_3, 0x010 */ - u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x014 */ - u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x018 */ - u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x01c */ - u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ - u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ - u32 _rsv1[10]; /* 0x028-04c */ - u32 shaper; /* _SHAPER, 0x050 */ - u32 shaper1; /* _SHAPER_1, 0x054 */ - u32 _rsv2[80]; /* 0x058-194 */ - u32 misc_ctrl; /* _MISC_CTRL, 0x198 */ -}; -check_member(clst_clk_ctlr, misc_ctrl, 0x198); - -/* CC_CCLK_BRST_POL */ -enum { - CC_CCLK_BRST_POL_PLLX_OUT0_LJ = 0x8, -}; - -/* CC_SUPER_CCLK_DIVIDER */ -enum { - CC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 -}; - -/* PLLX_MISC3 */ -enum { - PLLX_IDDQ = 1 << 3, -}; - -/* MISC_CTRL */ -enum { - CLK_SWITCH_MATCH = 1 << 5, -}; - -#define CLK_SWITCH_TIMEOUT_US 1000 -#endif /* _TEGRA132_CLST_CLK_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/cpu.h b/src/soc/nvidia/tegra132/include/soc/cpu.h deleted file mode 100644 index aebf4e1d60..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/cpu.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_CPU_H__ -#define __SOC_NVIDIA_TEGRA132_CPU_H__ - -/* - * Start a core in 64-bit mode at the entry_64 address. Note that entry_64 - * should be a 32-bit address. - */ -void start_cpu(int cpu, void *entry_64); -/* Start CPU wthout any log messages. */ -void start_cpu_silent(int cpu, void *entry_64); -/* Prepare SoC for starting a CPU. Initialize the global state of the SoC. */ -void cpu_prepare_startup(void *entry_64); - -void reset_entry_32bit(void); - -#endif /* __SOC_NVIDIA_TEGRA132_CPU_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h deleted file mode 100644 index b52c49b904..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/display.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ -#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ - -#define COLOR_WHITE 0xFFFFFF -#define COLOR_BLACK 0x000000 - -#define hsync_start(mode) \ - (mode->xres + mode->hfront_porch) - -#define hsync_end(mode) \ - (mode->xres + mode->hfront_porch + mode->hsync_width) - -#define htotal(mode) \ - (mode->xres + mode->hfront_porch + \ - mode->hsync_width + mode->hback_porch) - -#define vtotal(mode) \ - (mode->yres + mode->vfront_porch + \ - mode->vsync_width + mode->vback_porch) - -enum { - /* norrin64 */ - TEGRA_EDID_I2C_ADDRESS = 0x50, -}; - -/* refresh rate = 60/s */ -#define FRAME_IN_MS 17 - -/* forward declaration */ -struct soc_nvidia_tegra132_config; -struct display_controller; - -void dsi_display_startup(device_t dev); -void dp_display_startup(device_t dev); - -int tegra_dc_init(struct display_controller *disp_ctrl); -int update_display_mode(struct display_controller *disp_ctrl, - struct soc_nvidia_tegra132_config *config); -void update_window(const struct soc_nvidia_tegra132_config *config); -void update_display_shift_clock_divider(struct display_controller *disp_ctrl, - u32 shift_clock_div); -void pass_mode_info_to_payload( - struct soc_nvidia_tegra132_config *config); -#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/dma.h b/src/soc/nvidia/tegra132/include/soc/dma.h deleted file mode 100644 index e3beada7bd..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/dma.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __NVIDIA_TEGRA132_DMA_H__ -#define __NVIDIA_TEGRA132_DMA_H__ - -#include <inttypes.h> -#include <soc/addressmap.h> - -/* - * The DMA engine operates on 4 bytes at a time, so make sure any data - * passed via DMA is aligned to avoid underrun/overrun. - */ -#define TEGRA_DMA_ALIGN_BYTES 4 - -/* - * Note: Many APB DMA controller registers are laid out such that each - * bit controls or represents the status for the corresponding channel. - * So we will not bother to list each individual bit in this case. - */ -#define APB_COMMAND_GEN (1 << 31) - -#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff -#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0 - -/* - * Note: Many APB DMA controller registers are laid out such that each - * bit controls or represents the status for the corresponding channel. - * So we will not bother to list each individual bit in this case. - */ -#define APB_COMMAND_GEN (1 << 31) - -#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff -#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0 -struct apb_dma { - u32 command; /* 0x00 */ - u32 status; /* 0x04 */ - u32 rsvd1[2]; - u32 cntrl_reg; /* 0x10 */ - u32 irq_sta_cpu; /* 0x14 */ - u32 irq_sta_cop; /* 0x18 */ - u32 irq_mask; /* 0x1c */ - u32 irq_mask_set; /* 0x20 */ - u32 irq_mask_clr; /* 0x24 */ - u32 trig_reg; /* 0x28 */ - u32 channel_trig_reg; /* 0x2c */ - u32 dma_status; /* 0x30 */ - u32 channel_en_reg; /* 0x34 */ - u32 security_reg; /* 0x38 */ - u32 channel_swid; /* 0x3c */ - u32 rsvd[1]; - u32 chan_wt_reg0; /* 0x44 */ - u32 chan_wt_reg1; /* 0x48 */ - u32 chan_wt_reg2; /* 0x4c */ - u32 chan_wr_reg3; /* 0x50 */ - u32 channel_swid1; /* 0x54 */ -} __attribute__((packed)); -check_member(apb_dma, channel_swid1, 0x54); - -/* - * Naming in the doc included a superfluous _CHANNEL_n_ for - * each entry and was left out for the sake of conciseness. - */ -#define APB_CSR_ENB (1 << 31) -#define APB_CSR_IE_EOC (1 << 30) -#define APB_CSR_HOLD (1 << 29) -#define APB_CSR_DIR (1 << 28) -#define APB_CSR_ONCE (1 << 27) -#define APB_CSR_FLOW (1 << 21) -#define APB_CSR_REQ_SEL_MASK 0x1f -#define APB_CSR_REQ_SEL_SHIFT 16 - -enum apbdmachan_req_sel { - APBDMA_SLAVE_CNTR_REQ = 0, - APBDMA_SLAVE_APBIF_CH0 = 1, - APBDMA_SLAVE_APBIF_CH1 = 2, - APBDMA_SLAVE_APBIF_CH2 = 3, - APBDMA_SLAVE_APBIF_CH3 = 4, - APBDMA_SLAVE_HSI = 5, - APBDMA_SLAVE_APBIF_CH4 = 6, - APBDMA_SLAVE_APBIF_CH5 = 7, - APBDMA_SLAVE_UART_A = 8, - APBDMA_SLAVE_UART_B = 9, - APBDMA_SLAVE_UART_C = 10, - APBDMA_SLAVE_DTV = 11, - APBDMA_SLAVE_APBIF_CH6 = 12, - APBDMA_SLAVE_APBIF_CH7 = 13, - APBDMA_SLAVE_APBIF_CH8 = 14, - APBDMA_SLAVE_SL2B1 = 15, - APBDMA_SLAVE_SL2B2 = 16, - APBDMA_SLAVE_SL2B3 = 17, - APBDMA_SLAVE_SL2B4 = 18, - APBDMA_SLAVE_UART_D = 19, - APBDMA_SLAVE_UART_E = 20, - APBDMA_SLAVE_I2C = 21, - APBDMA_SLAVE_I2C2 = 22, - APBDMA_SLAVE_I2C3 = 23, - APBDMA_SLAVE_DVC_I2C = 24, - APBDMA_SLAVE_OWR = 25, - APBDMA_SLAVE_I2C4 = 26, - APBDMA_SLAVE_SL2B5 = 27, - APBDMA_SLAVE_SL2B6 = 28, - APBDMA_SLAVE_APBIF_CH9 = 29, - APBDMA_SLAVE_I2C6 = 30, - APBDMA_SLAVE_NA31 = 31, -}; - -#define APB_STA_BSY (1 << 31) -#define APB_STA_ISE_EOC (1 << 30) -#define APB_STA_HALT (1 << 29) -#define APB_STA_PING_PONG_STA (1 << 28) -#define APB_STA_DMA_ACTIVITY (1 << 27) -#define APB_STA_CHANNEL_PAUSE (1 << 26) - -#define APB_CSRE_CHANNEL_PAUSE (1 << 31) -#define APB_CSRE_TRIG_SEL_MASK 0x3f -#define APB_CSRE_TRIG_SEL_SHIFT 14 - -#define AHB_PTR_MASK (0x3fffffff) -#define AHB_PTR_SHIFT 2 - -#define AHB_SEQ_INTR_ENB (1 << 31) -#define AHB_BUS_WIDTH_MASK 0x7 -#define AHB_BUS_WIDTH_SHIFT 28 -#define AHB_DATA_SWAP (1 << 27) -#define AHB_BURST_MASK 0x7 -#define AHB_BURST_SHIFT 24 -#define AHB_SEQ_DBL_BUF (1 << 19) -#define AHB_SEQ_WRAP_MASK 0x7 -#define AHB_SEQ_WRAP_SHIFT 16 - -#define APB_PTR_MASK 0x3fffffff -#define APB_PTR_SHIFT 2 - -#define APB_BUS_WIDTH_MASK 0x7 -#define APB_BUS_WIDTH_SHIFT 28 -#define APB_DATA_SWAP (1 << 27) -#define APB_ADDR_WRAP_MASK 0x7 -#define APB_ADDR_WRAP_SHIFT 16 - -#define APB_WORD_TRANSFER_MASK 0x0fffffff -#define APB_WORD_TRANSFER_SHIFT 2 - -struct apb_dma_channel_regs { - u32 csr; /* 0x00 */ - u32 sta; /* 0x04 */ - u32 dma_byte_sta; /* 0x08 */ - u32 csre; /* 0x0c */ - u32 ahb_ptr; /* 0x10 */ - u32 ahb_seq; /* 0x14 */ - u32 apb_ptr; /* 0x18 */ - u32 apb_seq; /* 0x1c */ - u32 wcount; /* 0x20 */ - u32 word_transfer; /* 0x24 */ -} __attribute__((packed)); -check_member(apb_dma_channel_regs, word_transfer, 0x24); - -struct apb_dma_channel { - const int num; - struct apb_dma_channel_regs *regs; - - /* - * Basic high-level semaphore that can be used to "claim" - * a DMA channel e.g. by SPI, I2C, or other peripheral driver. - */ - int in_use; -}; - -struct apb_dma_channel * const dma_claim(void); -void dma_release(struct apb_dma_channel * const channel); -int dma_start(struct apb_dma_channel * const channel); -int dma_stop(struct apb_dma_channel * const channel); -int dma_busy(struct apb_dma_channel * const channel); - -#endif /* __NVIDIA_TEGRA132_DMA_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/emc.h b/src/soc/nvidia/tegra132/include/soc/emc.h deleted file mode 100644 index 6ede4e002d..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/emc.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_EMC_H__ -#define __SOC_NVIDIA_TEGRA132_EMC_H__ - -#include <stddef.h> -#include <stdint.h> - -enum { - EMC_PIN_RESET_MASK = 1 << 8, - EMC_PIN_RESET_ACTIVE = 0 << 8, - EMC_PIN_RESET_INACTIVE = 1 << 8, - EMC_PIN_DQM_MASK = 1 << 4, - EMC_PIN_DQM_NORMAL = 0 << 4, - EMC_PIN_DQM_INACTIVE = 1 << 4, - EMC_PIN_CKE_MASK = 1 << 0, - EMC_PIN_CKE_POWERDOWN = 0 << 0, - EMC_PIN_CKE_NORMAL = 1 << 0, - - EMC_REF_CMD_MASK = 1 << 0, - EMC_REF_CMD_REFRESH = 1 << 0, - EMC_REF_NORMAL_MASK = 1 << 1, - EMC_REF_NORMAL_INIT = 0 << 1, - EMC_REF_NORMAL_ENABLED = 1 << 1, - EMC_REF_NUM_SHIFT = 8, - EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT, - EMC_REF_DEV_SELECTN_SHIFT = 30, - EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT, - - EMC_REFCTRL_REF_VALID_MASK = 1 << 31, - EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31, - EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31, - - EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1, - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2, - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3, - - EMC_NOP_NOP_CMD_SHIFT = 0, - EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT, - EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30, - EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT, - - EMC_TIMING_CONTROL_TIMING_UPDATE = 1, -}; - -struct tegra_emc_regs { - uint32_t intstatus; /* 0x0 */ - uint32_t intmask; /* 0x4 */ - uint32_t dbg; /* 0x8 */ - uint32_t cfg; /* 0xc */ - uint32_t adr_cfg; /* 0x10 */ - uint32_t rsvd_0x14[3]; /* 0x14 */ - - uint32_t refctrl; /* 0x20 */ - uint32_t pin; /* 0x24 */ - uint32_t timing_control; /* 0x28 */ - uint32_t rc; /* 0x2c */ - uint32_t rfc; /* 0x30 */ - uint32_t ras; /* 0x34 */ - uint32_t rp; /* 0x38 */ - uint32_t r2w; /* 0x3c */ - uint32_t w2r; /* 0x40 */ - uint32_t r2p; /* 0x44 */ - uint32_t w2p; /* 0x48 */ - uint32_t rd_rcd; /* 0x4c */ - uint32_t wr_rcd; /* 0x50 */ - uint32_t rrd; /* 0x54 */ - uint32_t rext; /* 0x58 */ - uint32_t wdv; /* 0x5c */ - uint32_t quse; /* 0x60 */ - uint32_t qrst; /* 0x64 */ - uint32_t qsafe; /* 0x68 */ - uint32_t rdv; /* 0x6c */ - uint32_t refresh; /* 0x70 */ - uint32_t burst_refresh_num; /* 0x74 */ - uint32_t pdex2wr; /* 0x78 */ - uint32_t pdex2rd; /* 0x7c */ - uint32_t pchg2pden; /* 0x80 */ - uint32_t act2pden; /* 0x84 */ - uint32_t ar2pden; /* 0x88 */ - uint32_t rw2pden; /* 0x8c */ - uint32_t txsr; /* 0x90 */ - uint32_t tcke; /* 0x94 */ - uint32_t tfaw; /* 0x98 */ - uint32_t trpab; /* 0x9c */ - uint32_t tclkstable; /* 0xa0 */ - uint32_t tclkstop; /* 0xa4 */ - uint32_t trefbw; /* 0xa8 */ - uint32_t rsvd_0xac[1]; /* 0xac */ - uint32_t odt_write; /* 0xb0 */ - uint32_t odt_read; /* 0xb4 */ - uint32_t wext; /* 0xb8 */ - uint32_t ctt; /* 0xbc */ - uint32_t rfc_slr; /* 0xc0 */ - uint32_t mrs_wait_cnt2; /* 0xc4 */ - uint32_t mrs_wait_cnt; /* 0xc8 */ - uint32_t mrs; /* 0xcc */ - uint32_t emrs; /* 0xd0 */ - uint32_t ref; /* 0xd4 */ - uint32_t pre; /* 0xd8 */ - uint32_t nop; /* 0xdc */ - uint32_t self_ref; /* 0xe0 */ - uint32_t dpd; /* 0xe4 */ - uint32_t mrw; /* 0xe8 */ - uint32_t mrr; /* 0xec */ - uint32_t cmdq; /* 0xf0 */ - uint32_t mc2emcq; /* 0xf4 */ - uint32_t xm2dqspadctrl3; /* 0xf8 */ - uint32_t rsvd_0xfc[1]; /* 0xfc */ - uint32_t fbio_spare; /* 0x100 */ - uint32_t fbio_cfg5; /* 0x104 */ - uint32_t fbio_wrptr_eq_2; /* 0x108 */ - uint32_t rsvd_0x10c[2]; /* 0x10c */ - - uint32_t fbio_cfg6; /* 0x114 */ - uint32_t rsvd_0x118[2]; /* 0x118 */ - - uint32_t cfg_rsv; /* 0x120 */ - uint32_t acpd_control; /* 0x132 */ - uint32_t rsvd_0x128[1]; /* 0x128 */ - uint32_t emrs2; /* 0x12c */ - uint32_t emrs3; /* 0x130 */ - uint32_t mrw2; /* 0x134 */ - uint32_t mrw3; /* 0x138 */ - uint32_t mrw4; /* 0x13c */ - uint32_t clken_override; /* 0x140 */ - uint32_t r2r; /* 0x144 */ - uint32_t w2w; /* 0x148 */ - uint32_t einput; /* 0x14c */ - uint32_t einput_duration; /* 0x150 */ - uint32_t puterm_extra; /* 0x154 */ - uint32_t tckesr; /* 0x158 */ - uint32_t tpd; /* 0x15c */ - uint32_t rsvd_0x160[81]; /* 0x160 */ - - uint32_t auto_cal_config; /* 0x2a4 */ - uint32_t auto_cal_interval; /* 0x2a8 */ - uint32_t auto_cal_status; /* 0x2ac */ - uint32_t req_ctrl; /* 0x2b0 */ - uint32_t status; /* 0x2b4 */ - uint32_t cfg_2; /* 0x2b8 */ - uint32_t cfg_dig_dll; /* 0x2bc */ - uint32_t cfg_dig_dll_period; /* 0x2c0 */ - uint32_t rsvd_0x2c4[1]; /* 0x2c4 */ - uint32_t dig_dll_status; /* 0x2c8 */ - uint32_t rdv_mask; /* 0x2cc */ - uint32_t wdv_mask; /* 0x2d0 */ - uint32_t rsvd_0x2d4[1]; /* 0x2d4 */ - uint32_t ctt_duration; /* 0x2d8 */ - uint32_t ctt_term_ctrl; /* 0x2dc */ - uint32_t zcal_interval; /* 0x2e0 */ - uint32_t zcal_wait_cnt; /* 0x2e4 */ - uint32_t zcal_mrw_cmd; /* 0x2e8 */ - uint32_t zq_cal; /* 0x2ec */ - uint32_t xm2cmdpadctrl; /* 0x2f0 */ - uint32_t xm2cmdpadctrl2; /* 0x2f4 */ - uint32_t xm2dqspadctrl; /* 0x2f8 */ - uint32_t xm2dqspadctrl2; /* 0x2fc */ - uint32_t xm2dqpadctrl; /* 0x300 */ - uint32_t xm2dqpadctrl2; /* 0x304 */ - uint32_t xm2clkpadctrl; /* 0x308 */ - uint32_t xm2comppadctrl; /* 0x30c */ - uint32_t xm2vttgenpadctrl; /* 0x310 */ - uint32_t xm2vttgenpadctrl2; /* 0x314 */ - uint32_t xm2vttgenpadctrl3; /* 0x318 */ - uint32_t emcpaden; /* 0x31c */ - uint32_t xm2dqspadctrl4; /* 0x320 */ - uint32_t scratch0; /* 0x324 */ - uint32_t dll_xform_dqs0; /* 0x328 */ - uint32_t dll_xform_dqs1; /* 0x32c */ - uint32_t dll_xform_dqs2; /* 0x330 */ - uint32_t dll_xform_dqs3; /* 0x334 */ - uint32_t dll_xform_dqs4; /* 0x338 */ - uint32_t dll_xform_dqs5; /* 0x33c */ - uint32_t dll_xform_dqs6; /* 0x340 */ - uint32_t dll_xform_dqs7; /* 0x344 */ - uint32_t dll_xform_quse0; /* 0x348 */ - uint32_t dll_xform_quse1; /* 0x34c */ - uint32_t dll_xform_quse2; /* 0x350 */ - uint32_t dll_xform_quse3; /* 0x354 */ - uint32_t dll_xform_quse4; /* 0x358 */ - uint32_t dll_xform_quse5; /* 0x35c */ - uint32_t dll_xform_quse6; /* 0x360 */ - uint32_t dll_xform_quse7; /* 0x364 */ - uint32_t dll_xform_dq0; /* 0x368 */ - uint32_t dll_xform_dq1; /* 0x36c */ - uint32_t dll_xform_dq2; /* 0x370 */ - uint32_t dll_xform_dq3; /* 0x374 */ - uint32_t dli_rx_trim0; /* 0x378 */ - uint32_t dli_rx_trim1; /* 0x37c */ - uint32_t dli_rx_trim2; /* 0x380 */ - uint32_t dli_rx_trim3; /* 0x384 */ - uint32_t dli_rx_trim4; /* 0x388 */ - uint32_t dli_rx_trim5; /* 0x38c */ - uint32_t dli_rx_trim6; /* 0x390 */ - uint32_t dli_rx_trim7; /* 0x394 */ - uint32_t dli_tx_trim0; /* 0x398 */ - uint32_t dli_tx_trim1; /* 0x39c */ - uint32_t dli_tx_trim2; /* 0x3a0 */ - uint32_t dli_tx_trim3; /* 0x3a4 */ - uint32_t dli_trim_txdqs0; /* 0x3a8 */ - uint32_t dli_trim_txdqs1; /* 0x3ac */ - uint32_t dli_trim_txdqs2; /* 0x3b0 */ - uint32_t dli_trim_txdqs3; /* 0x3b4 */ - uint32_t dli_trim_txdqs4; /* 0x3b8 */ - uint32_t dli_trim_txdqs5; /* 0x3bc */ - uint32_t dli_trim_txdqs6; /* 0x3c0 */ - uint32_t dli_trim_txdqs7; /* 0x3c4 */ - uint32_t rsvd_0x3c8[1]; /* 0x3c8 */ - uint32_t stall_then_exe_after_clkchange; /* 0x3cc */ - uint32_t rsvd_0x3d0[1]; /* 0x3d0 */ - uint32_t auto_cal_clk_status; /* 0x3d4 */ - uint32_t sel_dpd_ctrl; /* 0x3d8 */ - uint32_t pre_refresh_req_cnt; /* 0x3dc */ - uint32_t dyn_self_ref_control; /* 0x3e0 */ - uint32_t txsrdll; /* 0x3e4 */ - uint32_t ccfifo_addr; /* 0x3e8 */ - uint32_t ccfifo_data; /* 0x3ec */ - uint32_t ccfifo_status; /* 0x3f0 */ - uint32_t cdb_cntl_1; /* 0x3f4 */ - uint32_t cdb_cntl_2; /* 0x3f8 */ - uint32_t xm2clkpadctrl2; /* 0x3fc */ - uint32_t swizzle_rank0_byte_cfg; /* 0x400 */ - uint32_t swizzle_rank0_byte0; /* 0x404 */ - uint32_t swizzle_rank0_byte1; /* 0x408 */ - uint32_t swizzle_rank0_byte2; /* 0x40c */ - uint32_t swizzle_rank0_byte3; /* 0x410 */ - uint32_t swizzle_rank1_byte_cfg; /* 0x414 */ - uint32_t swizzle_rank1_byte0; /* 0x418 */ - uint32_t swizzle_rank1_byte1; /* 0x41c */ - uint32_t swizzle_rank1_byte2; /* 0x420 */ - uint32_t swizzle_rank1_byte3; /* 0x424 */ - uint32_t ca_training_start; /* 0x428 */ - uint32_t ca_training_busy; /* 0x42c */ - uint32_t ca_training_cfg; /* 0x430 */ - uint32_t ca_training_timing_cntl1; /* 0x434 */ - uint32_t ca_training_timing_cntl2; /* 0x438 */ - uint32_t ca_training_ca_lead_in; /* 0x43c */ - uint32_t ca_training_ca; /* 0x440 */ - uint32_t ca_training_ca_lead_out; /* 0x444 */ - uint32_t ca_training_result1; /* 0x448 */ - uint32_t ca_training_result2; /* 0x44c */ - uint32_t ca_training_result3; /* 0x450 */ - uint32_t ca_training_result4; /* 0x454 */ - uint32_t auto_cal_config2; /* 0x458 */ - uint32_t auto_cal_config3; /* 0x45c */ - uint32_t auto_cal_status2; /* 0x460 */ - uint32_t xm2cmdpadctrl3; /* 0x464 */ - uint32_t ibdly; /* 0x468 */ - uint32_t dll_xform_addr0; /* 0x46c */ - uint32_t dll_xform_addr1; /* 0x470 */ - uint32_t dll_xform_addr2; /* 0x474 */ - uint32_t dli_addr_trim; /* 0x478 */ - uint32_t dsr_vttgen_drv; /* 0x47c */ - uint32_t txdsrvttgen; /* 0x480 */ - uint32_t xm2cmdpadctrl4; /* 0x484 */ - uint32_t xm2cmdpadctrl5; /* 0x488 */ - uint32_t rsvd_0x48c[5]; /* 0x48c */ - - uint32_t dll_xform_dqs8; /* 0x4a0 */ - uint32_t dll_xform_dqs9; /* 0x4a4 */ - uint32_t dll_xform_dqs10; /* 0x4a8 */ - uint32_t dll_xform_dqs11; /* 0x4ac */ - uint32_t dll_xform_dqs12; /* 0x4b0 */ - uint32_t dll_xform_dqs13; /* 0x4b4 */ - uint32_t dll_xform_dqs14; /* 0x4b8 */ - uint32_t dll_xform_dqs15; /* 0x4bc */ - uint32_t dll_xform_quse8; /* 0x4c0 */ - uint32_t dll_xform_quse9; /* 0x4c4 */ - uint32_t dll_xform_quse10; /* 0x4c8 */ - uint32_t dll_xform_quse11; /* 0x4cc */ - uint32_t dll_xform_quse12; /* 0x4d0 */ - uint32_t dll_xform_quse13; /* 0x4d4 */ - uint32_t dll_xform_quse14; /* 0x4d8 */ - uint32_t dll_xform_quse15; /* 0x4dc */ - uint32_t dll_xform_dq4; /* 0x4e0 */ - uint32_t dll_xform_dq5; /* 0x4e4 */ - uint32_t dll_xform_dq6; /* 0x4e8 */ - uint32_t dll_xform_dq7; /* 0x4ec */ - uint32_t rsvd_0x4f0[12]; /* 0x4f0 */ - - uint32_t dli_trim_txdqs8; /* 0x520 */ - uint32_t dli_trim_txdqs9; /* 0x524 */ - uint32_t dli_trim_txdqs10; /* 0x528 */ - uint32_t dli_trim_txdqs11; /* 0x52c */ - uint32_t dli_trim_txdqs12; /* 0x530 */ - uint32_t dli_trim_txdqs13; /* 0x534 */ - uint32_t dli_trim_txdqs14; /* 0x538 */ - uint32_t dli_trim_txdqs15; /* 0x53c */ - uint32_t cdb_cntl_3; /* 0x540 */ - uint32_t xm2dqspadctrl5; /* 0x544 */ - uint32_t xm2dqspadctrl6; /* 0x548 */ - uint32_t xm2dqpadctrl3; /* 0x54c */ - uint32_t dll_xform_addr3; /* 0x550 */ - uint32_t dll_xform_addr4; /* 0x554 */ - uint32_t dll_xform_addr5; /* 0x558 */ - uint32_t rsvd_0x55c[1]; /* 0x55c */ - uint32_t cfg_pipe; /* 0x560 */ - uint32_t qpop; /* 0x564 */ - uint32_t quse_width; /* 0x568 */ - uint32_t puterm_width; /* 0x56c */ - uint32_t bgbias_ctl0; /* 0x570 */ - uint32_t puterm_adj; /* 0x574 */ -} __attribute__((packed)); - -check_member(tegra_emc_regs, puterm_adj, 0x574); - -#endif /* __SOC_NVIDIA_TEGRA132_EMC_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/flow.h b/src/soc/nvidia/tegra132/include/soc/flow.h deleted file mode 100644 index 6a772a6a33..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/flow.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _TEGRA132_FLOW_H_ -#define _TEGRA132_FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; /* offset 0x00 */ - u32 halt_cop_events; /* offset 0x04 */ - u32 cpu_csr; /* offset 0x08 */ - u32 cop_csr; /* offset 0x0c */ - u32 xrq_events; /* offset 0x10 */ - u32 halt_cpu1_events; /* offset 0x14 */ - u32 cpu1_csr; /* offset 0x18 */ - u32 halt_cpu2_events; /* offset 0x1c */ - u32 cpu2_csr; /* offset 0x20 */ - u32 halt_cpu3_events; /* offset 0x24 */ - u32 cpu3_csr; /* offset 0x28 */ - u32 cluster_control; /* offset 0x2c */ - u32 halt_cop1_events; /* offset 0x30 */ - u32 halt_cop1_csr; /* offset 0x34 */ - u32 cpu_pwr_csr; /* offset 0x38 */ - u32 mpid; /* offset 0x3c */ - u32 ram_repair; /* offset 0x40 */ - u32 flow_dbg_sel; /* offset 0x44 */ - u32 flow_dbg_cnt0; /* offset 0x48 */ - u32 flow_dbg_cnt1; /* offset 0x4c */ - u32 flow_dbg_qual; /* offset 0x50 */ - u32 flow_ctlr_spare; /* offset 0x54 */ - u32 ram_repair_cluster1;/* offset 0x58 */ -}; -check_member(flow_ctlr, ram_repair_cluster1, 0x58); - -enum { - FLOW_MODE_SHIFT = 29, - FLOW_MODE_MASK = 0x7 << FLOW_MODE_SHIFT, - - FLOW_MODE_NONE = 0 << FLOW_MODE_SHIFT, - FLOW_MODE_RUN_AND_INT = 1 << FLOW_MODE_SHIFT, - FLOW_MODE_WAITEVENT = 2 << FLOW_MODE_SHIFT, - FLOW_MODE_WAITEVENT_AND_INT = 3 << FLOW_MODE_SHIFT, - FLOW_MODE_STOP_UNTIL_IRQ = 4 << FLOW_MODE_SHIFT, - FLOW_MODE_STOP_UNTIL_IRQ_AND_INT = 5 << FLOW_MODE_SHIFT, - FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ = 6 << FLOW_MODE_SHIFT, -}; - -/* HALT_COP_EVENTS_0, 0x04 */ -enum { - FLOW_EVENT_GIC_FIQ = 1 << 8, - FLOW_EVENT_GIC_IRQ = 1 << 9, - FLOW_EVENT_LIC_FIQ = 1 << 10, - FLOW_EVENT_LIC_IRQ = 1 << 11, - FLOW_EVENT_IBF = 1 << 12, - FLOW_EVENT_IBE = 1 << 13, - FLOW_EVENT_OBF = 1 << 14, - FLOW_EVENT_OBE = 1 << 15, - FLOW_EVENT_XRQ_A = 1 << 16, - FLOW_EVENT_XRQ_B = 1 << 17, - FLOW_EVENT_XRQ_C = 1 << 18, - FLOW_EVENT_XRQ_D = 1 << 19, - FLOW_EVENT_SMP30 = 1 << 20, - FLOW_EVENT_SMP31 = 1 << 21, - FLOW_EVENT_X_RDY = 1 << 22, - FLOW_EVENT_SEC = 1 << 23, - FLOW_EVENT_MSEC = 1 << 24, - FLOW_EVENT_USEC = 1 << 25, - FLOW_EVENT_X32K = 1 << 26, - FLOW_EVENT_SCLK = 1 << 27, - FLOW_EVENT_JTAG = 1 << 28 -}; - -#endif /* _TEGRA132_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra132/include/soc/flow_ctrl.h deleted file mode 100644 index 4028740814..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/flow_ctrl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _TEGRA132_FLOW_CTRL_H_ -#define _TEGRA132_FLOW_CTRL_H_ - -void flowctrl_cpu_off(int cpu); -void flowctrl_write_cpu_halt(int cpu, uint32_t val); - -#endif diff --git a/src/soc/nvidia/tegra132/include/soc/funitcfg.h b/src/soc/nvidia/tegra132/include/soc/funitcfg.h deleted file mode 100644 index 8c0a56b9cd..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/funitcfg.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H -#define __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H - -#include <soc/clock.h> -#include <soc/padconfig.h> -#include <soc/pinmux.h> -#include <stdint.h> - -#define FUNIT_INDEX(_name) FUNIT_##_name - -enum { - FUNIT_INDEX(SBC1), - FUNIT_INDEX(SBC4), - FUNIT_INDEX(I2C1), - FUNIT_INDEX(I2C2), - FUNIT_INDEX(I2C3), - FUNIT_INDEX(I2C5), - FUNIT_INDEX(I2C6), - FUNIT_INDEX(SDMMC3), - FUNIT_INDEX(SDMMC4), - FUNIT_INDEX(USBD), - FUNIT_INDEX(USB2), - FUNIT_INDEX(USB3), - FUNIT_INDEX(I2S1), - FUNIT_INDEX_MAX, -}; - -/* - * Note: these bus numbers are dependent on the driver implementations, and - * currently the I2C is 0-based and SPI is 1-based in its indexing. - */ -enum { - - I2C1_BUS = 0, - I2C2_BUS = 1, - I2C3_BUS = 2, - I2C5_BUS = 4, - I2CPWR_BUS = I2C5_BUS, - I2C6_BUS = 5, - - SPI1_BUS = 1, - SPI4_BUS = 4, -}; - -struct funit_cfg { - uint32_t funit_index; - uint32_t clk_src_id; - uint32_t clk_src_freq_id; - uint32_t clk_dev_freq_khz; - struct pad_config const* pad_cfg; - size_t pad_cfg_size; -}; - -#define FUNIT_CFG(_funit,_clk_src,_clk_freq,_cfg,_cfg_size) \ - { \ - .funit_index = FUNIT_INDEX(_funit), \ - .clk_src_id = CLK_SRC_DEV_ID(_funit, _clk_src), \ - .clk_src_freq_id = CLK_SRC_FREQ_ID(_funit, _clk_src), \ - .clk_dev_freq_khz = _clk_freq, \ - .pad_cfg = _cfg, \ - .pad_cfg_size = _cfg_size, \ - } - -#define FUNIT_CFG_USB(_funit) \ - { \ - .funit_index = FUNIT_INDEX(_funit), \ - .pad_cfg = NULL, \ - .pad_cfg_size = 0, \ - } - -/* - * Configure the funits associated with entry according to the configuration. - */ -void soc_configure_funits(const struct funit_cfg * const entries, size_t num); - -#endif /* __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H */ diff --git a/src/soc/nvidia/tegra132/include/soc/gpio.h b/src/soc/nvidia/tegra132/include/soc/gpio.h deleted file mode 100644 index aeb2dad744..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_GPIO_H__ -#define __SOC_NVIDIA_TEGRA132_GPIO_H__ - -#include <soc/pinmux.h> - -#endif /* __SOC_NVIDIA_TEGRA132_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/id.h b/src/soc/nvidia/tegra132/include/soc/id.h deleted file mode 100644 index 907285614c..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/id.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__ -#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__ - - -#include <arch/io.h> -#include <soc/addressmap.h> - -static inline int context_avp(void) -{ - const uint32_t avp_id = 0xaaaaaaaa; - void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE; - - return read32(uptag) == avp_id; -} - -#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/maincpu.h b/src/soc/nvidia/tegra132/include/soc/maincpu.h deleted file mode 100644 index 94bc1cf4df..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/maincpu.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_MAINCPU_H__ -#define __SOC_NVIDIA_TEGRA132_MAINCPU_H__ - -#include <stdint.h> - -extern u32 maincpu_stack_pointer; -extern u32 maincpu_entry_point; -void maincpu_setup(void); - -#endif /* __SOC_NVIDIA_TEGRA132_MAINCPU_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/mc.h b/src/soc/nvidia/tegra132/include/soc/mc.h deleted file mode 100644 index 6b22a7fc1f..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/mc.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_MC_H__ -#define __SOC_NVIDIA_TEGRA132_MC_H__ - -#include <stddef.h> -#include <stdint.h> - -// Memory Controller registers we need/care about - -struct tegra_mc_regs { - uint32_t rsvd_0x0[4]; /* 0x00 */ - uint32_t smmu_config; /* 0x10 */ - uint32_t smmu_tlb_config; /* 0x14 */ - uint32_t smmu_ptc_config; /* 0x18 */ - uint32_t smmu_ptb_asid; /* 0x1c */ - uint32_t smmu_ptb_data; /* 0x20 */ - uint32_t rsvd_0x24[3]; /* 0x24 */ - uint32_t smmu_tlb_flush; /* 0x30 */ - uint32_t smmu_ptc_flush; /* 0x34 */ - uint32_t rsvd_0x38[6]; /* 0x38 */ - uint32_t emem_cfg; /* 0x50 */ - uint32_t emem_adr_cfg; /* 0x54 */ - uint32_t emem_adr_cfg_dev0; /* 0x58 */ - uint32_t emem_adr_cfg_dev1; /* 0x5c */ - uint32_t rsvd_0x60[1]; /* 0x60 */ - uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */ - uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */ - uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */ - uint32_t security_cfg0; /* 0x70 */ - uint32_t security_cfg1; /* 0x74 */ - uint32_t rsvd_0x78[6]; /* 0x78 */ - uint32_t emem_arb_cfg; /* 0x90 */ - uint32_t emem_arb_outstanding_req; /* 0x94 */ - uint32_t emem_arb_timing_rcd; /* 0x98 */ - uint32_t emem_arb_timing_rp; /* 0x9c */ - uint32_t emem_arb_timing_rc; /* 0xa0 */ - uint32_t emem_arb_timing_ras; /* 0xa4 */ - uint32_t emem_arb_timing_faw; /* 0xa8 */ - uint32_t emem_arb_timing_rrd; /* 0xac */ - uint32_t emem_arb_timing_rap2pre; /* 0xb0 */ - uint32_t emem_arb_timing_wap2pre; /* 0xb4 */ - uint32_t emem_arb_timing_r2r; /* 0xb8 */ - uint32_t emem_arb_timing_w2w; /* 0xbc */ - uint32_t emem_arb_timing_r2w; /* 0xc0 */ - uint32_t emem_arb_timing_w2r; /* 0xc4 */ - uint32_t rsvd_0xc8[2]; /* 0xc8 */ - uint32_t emem_arb_da_turns; /* 0xd0 */ - uint32_t emem_arb_da_covers; /* 0xd4 */ - uint32_t emem_arb_misc0; /* 0xd8 */ - uint32_t emem_arb_misc1; /* 0xdc */ - uint32_t emem_arb_ring1_throttle; /* 0xe0 */ - uint32_t emem_arb_ring3_throttle; /* 0xe4 */ - uint32_t emem_arb_override; /* 0xe8 */ - uint32_t emem_arb_rsv; /* 0xec */ - uint32_t rsvd_0xf0[1]; /* 0xf0 */ - uint32_t clken_override; /* 0xf4 */ - uint32_t timing_control_dbg; /* 0xf8 */ - uint32_t timing_control; /* 0xfc */ - uint32_t stat_control; /* 0x100 */ - uint32_t rsvd_0x104[65]; /* 0x104 */ - uint32_t emem_arb_isochronous_0; /* 0x208 */ - uint32_t emem_arb_isochronous_1; /* 0x20c */ - uint32_t emem_arb_isochronous_2; /* 0x210 */ - uint32_t rsvd_0x214[38]; /* 0x214 */ - uint32_t dis_extra_snap_levels; /* 0x2ac */ - uint32_t rsvd_0x2b0[90]; /* 0x2b0 */ - uint32_t video_protect_vpr_override; /* 0x418 */ - uint32_t rsvd_0x41c[93]; /* 0x41c */ - uint32_t video_protect_vpr_override1; /* 0x590 */ - uint32_t rsvd_0x594[29]; /* 0x594 */ - uint32_t display_snap_ring; /* 0x608 */ - uint32_t rsvd_0x60c[15]; /* 0x60c */ - uint32_t video_protect_bom; /* 0x648 */ - uint32_t video_protect_size_mb; /* 0x64c */ - uint32_t video_protect_reg_ctrl; /* 0x650 */ - uint32_t rsvd_0x654[4]; /* 0x654 */ - uint32_t emem_cfg_access_ctrl; /* 0x664 */ - uint32_t rsvd_0x668[2]; /* 0x668 */ - uint32_t sec_carveout_bom; /* 0x670 */ - uint32_t sec_carveout_size_mb; /* 0x674 */ - uint32_t sec_carveout_reg_ctrl; /* 0x678 */ - uint32_t rsvd_0x67c[187]; /* 0x67c */ - uint32_t emem_arb_override_1; /* 0x968 */ - uint32_t rsvd_0x96c[3]; /* 0x96c */ - uint32_t video_protect_bom_adr_hi; /* 0x978 */ - uint32_t rsvd_0x97c[2]; /* 0x97c */ - uint32_t video_protect_gpu_override_0; /* 0x984 */ - uint32_t video_protect_gpu_override_1; /* 0x988 */ - uint32_t rsvd_0x98c[5]; /* 0x98c */ - uint32_t mts_carveout_bom; /* 0x9a0 */ - uint32_t mts_carveout_size_mb; /* 0x9a4 */ - uint32_t mts_carveout_adr_hi; /* 0x9a8 */ - uint32_t mts_carveout_reg_ctrl; /* 0x9ac */ - uint32_t rsvd_0x9b0[4]; /* 0x9b0 */ - uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */ - uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */ - uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */ - uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */ - uint32_t rsvd_0x9d0[1]; /* 0x9d0 */ - uint32_t sec_carveout_adr_hi; /* 0x9d4 */ -}; - -enum { - MC_SMMU_CONFIG_ENABLE = 1, - - MC_EMEM_CFG_SIZE_MB_SHIFT = 0, - MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, - - MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, - MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, - - MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1, - - MC_TIMING_CONTROL_TIMING_UPDATE = 1, -}; - -check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4); - -#endif /* __SOC_NVIDIA_TEGRA132_MC_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld deleted file mode 100644 index a8f8a34299..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <memlayout.h> -#include <rules.h> - -#include <arch/header.ld> - -/* - * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, - * so the bootblock loading address must be placed after that. After the - * handoff that area may be reclaimed for other uses, e.g. CBFS cache. - * TODO: Did this change on Tegra132? What's the new valid range? - */ - -SECTIONS -{ - SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - PRERAM_CBFS_CACHE(0x40002000, 36K) - VBOOT2_WORK(0x4000B000, 12K) -#if ENV_ARM64 - STACK(0x4000E000, 3K) -#else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000EC00, 3K) -#endif - TIMESTAMP(0x4000F800, 2K) - BOOTBLOCK(0x40010000, 28K) - VERSTAGE(0x40017000, 64K) - ROMSTAGE(0x40027000, 100K) - SRAM_END(0x40040000) - - DRAM_START(0x80000000) - POSTRAM_CBFS_CACHE(0x80100000, 1M) - RAMSTAGE(0x80200000, 256K) - TTB(0x100000000 - CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB * 1M, 1M) -} diff --git a/src/soc/nvidia/tegra132/include/soc/mipi-phy.h b/src/soc/nvidia/tegra132/include/soc/mipi-phy.h deleted file mode 100644 index 852c5a38af..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/mipi-phy.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _TEGRA_MIPI_PHY_H -#define _TEGRA_MIPI_PHY_H - -#include <stdlib.h> - -/* - * Macros for calculating the phy timings - */ -/* Period of one bit time in nano seconds */ -#define DSI_TBIT_Factorized(Freq) (((1000) * (1000))/(Freq)) -#define DSI_TBIT(Freq) (DSI_TBIT_Factorized(Freq)/(1000)) - -//#define NV_MAX(a,b) (((a) > (b)) ? (a) : (b)) - -/* Period of one byte time in nano seconds */ -#define DSI_TBYTE(Freq) ((DSI_TBIT_Factorized(Freq)) * (8)) -#define DSI_PHY_TIMING_DIV(X, Freq) ((X*1000) / (DSI_TBYTE(Freq))) - -/* - * As per Mipi spec (minimum): - * (3 + MAX(8 * DSI_TBIT, 60 + 4 * DSI_TBIT) / DSI_TBYTE) - */ -#define DSI_THSTRAIL_VAL(Freq) \ - (MAX(((8) * (DSI_TBIT(Freq))), ((60) + ((4) * (DSI_TBIT(Freq)))))) - -int mipi_dphy_set_timing(struct tegra_dsi *dsi); - -#endif diff --git a/src/soc/nvidia/tegra132/include/soc/mipi_display.h b/src/soc/nvidia/tegra132/include/soc/mipi_display.h deleted file mode 100644 index 6499c43361..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/mipi_display.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * Defines for Mobile Industry Processor Interface (MIPI(R)) - * Display Working Group standards: DSI, DCS, DBI, DPI - * - * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> - * Copyright (C) 2006 Nokia Corporation - * Author: Imre Deak <imre.deak@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef MIPI_DISPLAY_H -#define MIPI_DISPLAY_H - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -}; - -/* MIPI DCS pixel formats */ -#define MIPI_DCS_PIXEL_FMT_24BIT 7 -#define MIPI_DCS_PIXEL_FMT_18BIT 6 -#define MIPI_DCS_PIXEL_FMT_16BIT 5 -#define MIPI_DCS_PIXEL_FMT_12BIT 3 -#define MIPI_DCS_PIXEL_FMT_8BIT 2 -#define MIPI_DCS_PIXEL_FMT_3BIT 1 - -#endif diff --git a/src/soc/nvidia/tegra132/include/soc/mipi_dsi.h b/src/soc/nvidia/tegra132/include/soc/mipi_dsi.h deleted file mode 100644 index b8a9a8684e..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/mipi_dsi.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * MIPI DSI Bus - * - * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. - * Andrzej Hajda <a.hajda@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MIPI_DSI_H__ -#define __MIPI_DSI_H__ - -struct mipi_dsi_host; -struct mipi_dsi_device; - -/* request ACK from peripheral */ -#define MIPI_DSI_MSG_REQ_ACK BIT(0) -/* use Low Power Mode to transmit message */ -#define MIPI_DSI_MSG_USE_LPM BIT(1) - -/** - * @brief mipi_dsi_msg - read/write DSI buffer - */ -struct mipi_dsi_msg { - u8 channel; /**< virtual channel id */ - u8 type; /**< payload data type */ - u16 flags; /**< flags controlling this message transmission */ - - size_t tx_len; /**< length of tx_buf */ - const void *tx_buf; /**< data to be written */ - - size_t rx_len; /**< length of rx_buf */ - void *rx_buf; /**< data to be read, or NULL */ -}; - -/** - * @brief mipi_dsi_host_ops - DSI bus operations - * @var mipi_dsi_host_ops::attach - * attach DSI device to DSI host - * @var mipi_dsi_host_ops::detach - * detach DSI device from DSI host - * @var mipi_dsi_host_ops::transfer - * transmit a DSI packet - * - * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg - * structures. This structure contains information about the type of packet - * being transmitted as well as the transmit and receive buffers. When an - * error is encountered during transmission, this function will return a - * negative error code. On success it shall return the number of bytes - * transmitted for write packets or the number of bytes received for read - * packets. - * - * Note that typically DSI packet transmission is atomic, so the .transfer() - * function will seldomly return anything other than the number of bytes - * contained in the transmit buffer on success. - */ -struct mipi_dsi_host_ops { - int (*attach)(struct mipi_dsi_host *host, - struct mipi_dsi_device *dsi); - int (*detach)(struct mipi_dsi_host *host, - struct mipi_dsi_device *dsi); - ssize_t (*transfer)(struct mipi_dsi_host *host, - const struct mipi_dsi_msg *msg); -}; - -/** - * @brief mipi_dsi_host - DSI host device - */ -struct mipi_dsi_host { - //struct device *dev; - void *dev; /**< driver model device node for this DSI host */ - const struct mipi_dsi_host_ops *ops; /**< DSI host operations */ -}; - -int mipi_dsi_host_register(struct mipi_dsi_host *host); - -/* DSI mode flags */ - -/* video mode */ -#define MIPI_DSI_MODE_VIDEO BIT(0) -/* video burst mode */ -#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) -/* video pulse mode */ -#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) -/* enable auto vertical count mode */ -#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) -/* enable hsync-end packets in vsync-pulse and v-porch area */ -#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) -/* disable hfront-porch area */ -#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) -/* disable hback-porch area */ -#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) -/* disable hsync-active area */ -#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) -/* flush display FIFO on vsync pulse */ -#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) -/* disable EoT packets in HS mode */ -#define MIPI_DSI_MODE_EOT_PACKET BIT(9) -/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ -#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) - -enum mipi_dsi_pixel_format { - MIPI_DSI_FMT_RGB888, - MIPI_DSI_FMT_RGB666, - MIPI_DSI_FMT_RGB666_PACKED, - MIPI_DSI_FMT_RGB565, -}; - -struct mipi_dsi_master_ops { - int (*enslave)(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave); - int (*liberate)(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave); -}; - -/** - * @brief mipi_dsi_device - DSI peripheral device - * - * For dual-channel interfaces, the master interface can be identified by the - * fact that it's .slave field is set to non-NULL. The slave interface will - * have the .master field set to non-NULL. - */ -struct mipi_dsi_device { - struct mipi_dsi_host *host; /**< DSI host for this peripheral */ - - unsigned int channel; /**< virtual channel assigned to the peripheral */ - unsigned int lanes; /**< number of active data lanes */ - enum mipi_dsi_pixel_format format; /**< pixel format for video mode */ - unsigned long mode_flags; /**< DSI operation mode related flags */ - - const struct mipi_dsi_master_ops *ops; /**< callbacks for master/slave setup */ - struct mipi_dsi_device *master; /**< master interface for dual-channel peripherals */ - struct mipi_dsi_device *slave; /**< slave interface for dual-channel peripherals */ -}; - -int mipi_dsi_attach(struct mipi_dsi_device *dsi); -int mipi_dsi_detach(struct mipi_dsi_device *dsi); -int mipi_dsi_enslave(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave); -int mipi_dsi_liberate(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave); - -/** - * @brief mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode - * @var mipi_dsi_dcs_tear_mode::MIPI_DSI_DCS_TEAR_MODE_VBLANK - * the TE output line consists of V-Blanking information only - * @var mipi_dsi_dcs_tear_mode::MIPI_DSI_DCS_TEAR_MODE_VHBLANK - * the TE output line consists of both V-Blanking and H-Blanking - * information - */ -enum mipi_dsi_dcs_tear_mode { - MIPI_DSI_DCS_TEAR_MODE_VBLANK, - MIPI_DSI_DCS_TEAR_MODE_VHBLANK, -}; - -#define MIPI_DSI_DCS_POWER_MODE_DISPLAY (1 << 2) -#define MIPI_DSI_DCS_POWER_MODE_NORMAL (1 << 3) -#define MIPI_DSI_DCS_POWER_MODE_SLEEP (1 << 4) -#define MIPI_DSI_DCS_POWER_MODE_PARTIAL (1 << 5) -#define MIPI_DSI_DCS_POWER_MODE_IDLE (1 << 6) - -ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, - const void *data, size_t len); -int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start, - u16 end); -int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, - u16 end); -int mipi_dsi_dcs_set_address_mode(struct mipi_dsi_device *dsi, - bool reverse_page_address, - bool reverse_col_address, - bool reverse_page_col_address, - bool refresh_from_bottom, - bool reverse_rgb, - bool latch_right_to_left, - bool flip_horizontal, - bool flip_vertical); -int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, - enum mipi_dsi_dcs_tear_mode mode); -int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); - -#define MIPI_CAL_CTRL 0x00 -#define MIPI_CAL_CTRL_START (1 << 0) - -#define MIPI_CAL_AUTOCAL_CTRL 0x01 - -#define MIPI_CAL_STATUS 0x02 -#define MIPI_CAL_STATUS_DONE (1 << 16) -#define MIPI_CAL_STATUS_ACTIVE (1 << 0) - -#define MIPI_CAL_CONFIG_CSIA 0x05 -#define MIPI_CAL_CONFIG_CSIB 0x06 -#define MIPI_CAL_CONFIG_CSIC 0x07 -#define MIPI_CAL_CONFIG_CSID 0x08 -#define MIPI_CAL_CONFIG_CSIE 0x09 -#define MIPI_CAL_CONFIG_DSIA 0x0e -#define MIPI_CAL_CONFIG_DSIB 0x0f -#define MIPI_CAL_CONFIG_DSIC 0x10 -#define MIPI_CAL_CONFIG_DSID 0x11 - -#define MIPI_CAL_CONFIG_DSIAB_CLK 0x19 -#define MIPI_CAL_CONFIG_DSICD_CLK 0x1a -#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b -#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c -#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d - -#define MIPI_CAL_CONFIG_SELECT (1 << 21) -#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16) -#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8) -#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0) -#define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8) -#define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0) - -#define MIPI_CAL_BIAS_PAD_CFG0 0x16 -#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1) -#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0) - -#define MIPI_CAL_BIAS_PAD_CFG1 0x17 -#define MIPI_CAL_BIAS_PAD_CFG1_DEFAULT (0x20000) - -#define MIPI_CAL_BIAS_PAD_CFG2 0x18 -#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1) - -struct calibration_regs { - unsigned long data; - unsigned long clk; -}; - -struct tegra_mipi_config { - int calibrate_clk_lane; - int num_pads; - const struct calibration_regs *regs; -}; - -struct tegra_mipi { - void *regs; -}; - -struct tegra_mipi_device { - struct tegra_mipi *mipi; - const struct tegra_mipi_config *config; - unsigned long pads; -}; - -struct tegra_mipi_device *tegra_mipi_request(struct tegra_mipi_device *device, - int device_index); -int tegra_mipi_calibrate(struct tegra_mipi_device *device); -#endif /* __MIPI_DSI_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/mmu_operations.h b/src/soc/nvidia/tegra132/include/soc/mmu_operations.h deleted file mode 100644 index f604c40e25..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/mmu_operations.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ -#define __SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ - -void tegra132_mmu_init(void); - -#endif //__SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ diff --git a/src/soc/nvidia/tegra132/include/soc/padconfig.h b/src/soc/nvidia/tegra132/include/soc/padconfig.h deleted file mode 100644 index 3d5f794c62..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/padconfig.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_PAD_CFG_H -#define __SOC_NVIDIA_TEGRA132_PAD_CFG_H - -#include <stdint.h> -#include <soc/pinmux.h> - -struct pad_config { - uint8_t pinmux_flags; /* PU/PU, OD, INPUT, SFIO, etc */ - uint8_t gpio_index; /* bank, port, index */ - uint16_t pinmux_index:9; - uint16_t unused:1; - uint16_t sfio:1; - uint16_t gpio_out0:1; - uint16_t gpio_out1:1; - uint16_t pad_has_gpio:1; - uint16_t por_pullup:1; -}; - -#define PAD_CFG_GPIO_INPUT(ball_, pinmux_flgs_) \ - { \ - .pinmux_flags = pinmux_flgs_ | PINMUX_INPUT_ENABLE, \ - .gpio_index = PAD_TO_GPIO_##ball_, \ - .pinmux_index = PINMUX_##ball_##_INDEX, \ - .sfio = 0, \ - .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ - } - -#define PAD_CFG_GPIO_OUT0(ball_, pinmux_flgs_) \ - { \ - .pinmux_flags = pinmux_flgs_, \ - .gpio_index = PAD_TO_GPIO_##ball_, \ - .pinmux_index = PINMUX_##ball_##_INDEX, \ - .sfio = 0, \ - .gpio_out0 = 1, \ - .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ - } - -#define PAD_CFG_GPIO_OUT1(ball_, pinmux_flgs_) \ - { \ - .pinmux_flags = pinmux_flgs_, \ - .gpio_index = PAD_TO_GPIO_##ball_, \ - .pinmux_index = PINMUX_##ball_##_INDEX, \ - .sfio = 0, \ - .gpio_out1 = 1, \ - .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ - } - -#define PAD_CFG_SFIO(ball_, pinmux_flgs_, sfio_) \ - { \ - .pinmux_flags = pinmux_flgs_ | \ - PINMUX_##ball_##_FUNC_##sfio_, \ - .gpio_index = PAD_TO_GPIO_##ball_, \ - .pinmux_index = PINMUX_##ball_##_INDEX, \ - .sfio = 1, \ - .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ - } - -#define PAD_CFG_UNUSED(ball_) \ - { \ - .gpio_index = PAD_TO_GPIO_##ball_, \ - .pinmux_index = PINMUX_##ball_##_INDEX, \ - .unused = 1, \ - .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ - } -/* - * Configure the pads associated with entry according to the configuration. - */ -void soc_configure_pads(const struct pad_config * const entries, size_t num); -/* I2C6 requires special init as its pad lives int the SOR/DPAUX block */ -void soc_configure_i2c6pad(void); -void soc_configure_host1x(void); -#endif /* __SOC_NVIDIA_TEGRA132_PAD_CFG_H */ diff --git a/src/soc/nvidia/tegra132/include/soc/pinmux.h b/src/soc/nvidia/tegra132/include/soc/pinmux.h deleted file mode 100644 index d2388af45e..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/pinmux.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_PINMUX_H__ -#define __SOC_NVIDIA_TEGRA132_PINMUX_H__ - -#include <stdint.h> -#include <soc/nvidia/tegra/gpio.h> -#include <soc/nvidia/tegra/pinmux.h> - -enum { - PINMUX_FUNC_MASK = 3 << 0, - - PINMUX_PULL_MASK = 3 << 2, - PINMUX_PULL_NONE = 0 << 2, - PINMUX_PULL_DOWN = 1 << 2, - PINMUX_PULL_UP = 2 << 2, - - PINMUX_TRISTATE = 1 << 4, - PINMUX_INPUT_ENABLE = 1 << 5, - PINMUX_OPEN_DRAIN = 1 << 6, - PINMUX_LOCK = 1 << 7, - PINMUX_IO_RESET = 1 << 8, - PINMUX_RCV_SEL = 1 << 9 -}; - -/* GPIO index constants. */ - -#define GPIO_PORT_CONSTANTS(port) \ - GPIO_##port##0_INDEX, GPIO_##port##1_INDEX, GPIO_##port##2_INDEX, \ - GPIO_##port##3_INDEX, GPIO_##port##4_INDEX, GPIO_##port##5_INDEX, \ - GPIO_##port##6_INDEX, GPIO_##port##7_INDEX - -enum { - GPIO_PORT_CONSTANTS(A), - GPIO_PORT_CONSTANTS(B), - GPIO_PORT_CONSTANTS(C), - GPIO_PORT_CONSTANTS(D), - GPIO_PORT_CONSTANTS(E), - GPIO_PORT_CONSTANTS(F), - GPIO_PORT_CONSTANTS(G), - GPIO_PORT_CONSTANTS(H), - GPIO_PORT_CONSTANTS(I), - GPIO_PORT_CONSTANTS(J), - GPIO_PORT_CONSTANTS(K), - GPIO_PORT_CONSTANTS(L), - GPIO_PORT_CONSTANTS(M), - GPIO_PORT_CONSTANTS(N), - GPIO_PORT_CONSTANTS(O), - GPIO_PORT_CONSTANTS(P), - GPIO_PORT_CONSTANTS(Q), - GPIO_PORT_CONSTANTS(R), - GPIO_PORT_CONSTANTS(S), - GPIO_PORT_CONSTANTS(T), - GPIO_PORT_CONSTANTS(U), - GPIO_PORT_CONSTANTS(V), - GPIO_PORT_CONSTANTS(W), - GPIO_PORT_CONSTANTS(X), - GPIO_PORT_CONSTANTS(Y), - GPIO_PORT_CONSTANTS(Z), - GPIO_PORT_CONSTANTS(AA), - GPIO_PORT_CONSTANTS(BB), - GPIO_PORT_CONSTANTS(CC), - GPIO_PORT_CONSTANTS(DD), - GPIO_PORT_CONSTANTS(EE), - GPIO_PORT_CONSTANTS(FF), - GPIO_NONE_INDEX = 0, -}; - -#define PINMUX_CONSTANTS_GPIO(name, gpio) \ - PINMUX_GPIO_##gpio = PINMUX_##name##_INDEX - -#define PINMUX_CONSTANTS(index, name, por_pu, gpio, has_gpio, \ - func0, func1, func2, func3) \ - PINMUX_##name##_INDEX = index, \ - PINMUX_##name##_FUNC_##func0 = 0, \ - PINMUX_##name##_FUNC_##func1 = 1, \ - PINMUX_##name##_FUNC_##func2 = 2, \ - PINMUX_##name##_FUNC_##func3 = 3, \ - PAD_TO_GPIO_##name = GPIO_##gpio##_INDEX, \ - PAD_HAS_GPIO_##name = has_gpio, \ - PAD_POR_PU_##name = por_pu - -#define PAD_GPIO(index, name, por_pu, gpio, func0, func1, func2, func3) \ - PINMUX_CONSTANTS(index, name, por_pu, gpio, 1, \ - func0, func1, func2, func3), \ - PINMUX_CONSTANTS_GPIO(name, gpio) - -#define PAD_NO_GPIO(index, name, por_pu, func0, func1, func2, func3) \ - PINMUX_CONSTANTS(index, name, por_pu, NONE, 0, \ - func0, func1, func2, func3) - -enum { - /* Power-on-reset pull states. */ - POR_PU = 1, - POR_PD = 0, - POR_NP = 0, - - PAD_GPIO(0, ULPI_DATA0, POR_PU, O1, SPI3, HSI, UA3, ULPI), - PAD_GPIO(1, ULPI_DATA1, POR_PU, O2, SPI3, HSI, UA3, ULPI), - PAD_GPIO(2, ULPI_DATA2, POR_PU, O3, SPI3, HSI, UA3, ULPI), - PAD_GPIO(3, ULPI_DATA3, POR_PU, O4, SPI3, HSI, UA3, ULPI), - PAD_GPIO(4, ULPI_DATA4, POR_PU, O5, SPI2, HSI, UA3, ULPI), - PAD_GPIO(5, ULPI_DATA5, POR_PU, O6, SPI2, HSI, UA3, ULPI), - PAD_GPIO(6, ULPI_DATA6, POR_PU, O7, SPI2, HSI, UA3, ULPI), - PAD_GPIO(7, ULPI_DATA7, POR_PU, O0, SPI2, HSI, UA3, ULPI), - PAD_GPIO(8, ULPI_CLK, POR_NP, Y0, SPI1, SPI5, UD3, ULPI), - PAD_GPIO(9, ULPI_DIR, POR_NP, Y1, SPI1, SPI5, UD3, ULPI), - PAD_GPIO(10, ULPI_NXT, POR_NP, Y2, SPI1, SPI5, UD3, ULPI), - PAD_GPIO(11, ULPI_STP, POR_NP, Y3, SPI1, SPI5, UD3, ULPI), - PAD_GPIO(12, DAP3_FS, POR_PD, P0, I2S2, SPI5, DCA, DCB), - PAD_GPIO(13, DAP3_DIN, POR_PD, P1, I2S2, SPI5, DCA, DCB), - PAD_GPIO(14, DAP3_DOUT, POR_PD, P2, I2S2, SPI5, DCA, RES3), - PAD_GPIO(15, DAP3_SCLK, POR_PD, P3, I2S2, SPI5, RES2, DCB), - PAD_GPIO(16, GPIO_PV0, POR_NP, V0, RES0, RES1, RES2, RES3), - PAD_GPIO(17, GPIO_PV1, POR_NP, V1, RES0, RES1, RES2, RES3), - PAD_GPIO(18, SDMMC1_CLK, POR_PD, Z0, SDMMC1, CLK12M, RES2, RES3), - PAD_GPIO(19, SDMMC1_CMD, POR_PU, Z1, SDMMC1, SPDIF, SPI4, UA3), - PAD_GPIO(20, SDMMC1_DAT3, POR_PU, Y4, SDMMC1, SPDIF, SPI4, UA3), - PAD_GPIO(21, SDMMC1_DAT2, POR_PU, Y5, SDMMC1, PWM0, SPI4, UA3), - PAD_GPIO(22, SDMMC1_DAT1, POR_PU, Y6, SDMMC1, PWM1, SPI4, UA3), - PAD_GPIO(23, SDMMC1_DAT0, POR_PU, Y7, SDMMC1, RES1, SPI4, UA3), - PAD_GPIO(26, CLK2_OUT, POR_PD, W5, EXTPERIPH2, RES1, RES2, RES3), - PAD_GPIO(27, CLK2_REQ, POR_NP, CC5, DAP, RES1, RES2, RES3), - PAD_GPIO(68, HDMI_INT, POR_PD, N7, RES0, RES1, RES2, RES3), - PAD_GPIO(69, DDC_SCL, POR_NP, V4, I2C4, RES1, RES2, RES3), - PAD_GPIO(70, DDC_SDA, POR_NP, V5, I2C4, RES1, RES2, RES3), - PAD_GPIO(89, UART2_RXD, POR_PU, C3, IR3, SPDIF, UA3, SPI4), - PAD_GPIO(90, UART2_TXD, POR_PU, C2, IR3, SPDIF, UA3, SPI4), - PAD_GPIO(91, UART2_RTS_N, POR_PU, J6, UA3, UB3, NOR, SPI4), - PAD_GPIO(92, UART2_CTS_N, POR_PU, J5, UA3, UB3, NOR, SPI4), - PAD_GPIO(93, UART3_TXD, POR_PU, W6, UC3, RES1, NOR, SPI4), - PAD_GPIO(94, UART3_RXD, POR_PU, W7, UC3, RES1, NOR, SPI4), - PAD_GPIO(95, UART3_CTS_N, POR_PU, A1, UC3, SDMMC1, DTV, NOR), - PAD_GPIO(96, UART3_RTS_N, POR_PU, C0, UC3, PWM0, DTV, NOR), - PAD_GPIO(97, GPIO_PU0, POR_NP, U0, OWR, UA3, NOR, RES3), - PAD_GPIO(98, GPIO_PU1, POR_NP, U1, RES0, UA3, NOR, RES3), - PAD_GPIO(99, GPIO_PU2, POR_NP, U2, RES0, UA3, NOR, RES3), - PAD_GPIO(100, GPIO_PU3, POR_NP, U3, PWM0, UA3, NOR, DCB), - PAD_GPIO(101, GPIO_PU4, POR_NP, U4, PWM1, UA3, NOR, DCB), - PAD_GPIO(102, GPIO_PU5, POR_NP, U5, PWM2, UA3, NOR, DCB), - PAD_GPIO(103, GPIO_PU6, POR_NP, U6, PWM3, UA3, RES2, NOR), - PAD_GPIO(104, GEN1_I2C_SDA, POR_NP, C5, I2C1, RES1, RES2, RES3), - PAD_GPIO(105, GEN1_I2C_SCL, POR_NP, C4, I2C1, RES1, RES2, RES3), - PAD_GPIO(106, DAP4_FS, POR_PD, P4, I2S3, NOR, DTV, RES3), - PAD_GPIO(107, DAP4_DIN, POR_PD, P5, I2S3, NOR, RES2, RES3), - PAD_GPIO(108, DAP4_DOUT, POR_PD, P6, I2S3, NOR, DTV, RES3), - PAD_GPIO(109, DAP4_SCLK, POR_PD, P7, I2S3, NOR, RES2, RES3), - PAD_GPIO(110, CLK3_OUT, POR_NP, EE0, EXTPERIPH3, RES1, RES2, RES3), - PAD_GPIO(111, CLK3_REQ, POR_NP, EE1, DEV3, RES1, RES2, RES3), - PAD_GPIO(112, GPIO_PC7, POR_PU, C7, RES0, RES1, NOR_WP_N, NOR_INT1), - PAD_GPIO(113, GPIO_PI5, POR_PU, I5, SDMMC2, RES1, NOR, RES3), - PAD_GPIO(114, GPIO_PI7, POR_PU, I7, RES0, TRACE, NOR, DTV), - PAD_GPIO(115, GPIO_PK0, POR_PU, K0, RES0, SDMMC3, NOR, SOC_THERM), - PAD_GPIO(116, GPIO_PK1, POR_PD, K1, SDMMC2, TRACE, NOR, RES3), - PAD_GPIO(117, GPIO_PJ0, POR_PU, J0, RES0, RES1, NOR, USB), - PAD_GPIO(118, GPIO_PJ2, POR_PU, J2, RES0, RES1, NOR, SOC_THERM), - PAD_GPIO(119, GPIO_PK3, POR_PU, K3, SDMMC2, TRACE, NOR, CCLA), - PAD_GPIO(120, GPIO_PK4, POR_PU, K4, SDMMC2, RES1, NOR_AD22, NOR_INT1), - PAD_GPIO(121, GPIO_PK2, POR_PU, K2, RES0, RES1, NOR, RES3), - PAD_GPIO(122, GPIO_PI3, POR_PU, I3, RES0, RES1, NOR, SPI4), - PAD_GPIO(123, GPIO_PI6, POR_PU, I6, RES0, RES1, NOR, SDMMC2), - PAD_GPIO(124, GPIO_PG0, POR_NP, G0, RES0, RES1, NOR, RES3), - PAD_GPIO(125, GPIO_PG1, POR_NP, G1, RES0, RES1, NOR, RES3), - PAD_GPIO(126, GPIO_PG2, POR_NP, G2, RES0, TRACE, NOR, RES3), - PAD_GPIO(127, GPIO_PG3, POR_NP, G3, RES0, TRACE, NOR, RES3), - PAD_GPIO(128, GPIO_PG4, POR_NP, G4, RES0, TMDS, NOR, SPI4), - PAD_GPIO(129, GPIO_PG5, POR_NP, G5, RES0, RES1, NOR, SPI4), - PAD_GPIO(130, GPIO_PG6, POR_NP, G6, RES0, RES1, NOR, SPI4), - PAD_GPIO(131, GPIO_PG7, POR_NP, G7, RES0, RES1, NOR, SPI4), - PAD_GPIO(132, GPIO_PH0, POR_PD, H0, PWM0, TRACE, NOR, DTV), - PAD_GPIO(133, GPIO_PH1, POR_PD, H1, PWM1, TMDS, NOR, DCA), - PAD_GPIO(134, GPIO_PH2, POR_PD, H2, PWM2, TDMS, NOR, CLDVFS), - PAD_GPIO(135, GPIO_PH3, POR_PD, H3, PWM3, SPI4, NOR, CLDVFS), - PAD_GPIO(136, GPIO_PH4, POR_PU, H4, SDMMC2, RES1, NOR, RES3), - PAD_GPIO(137, GPIO_PH5, POR_PD, H5, SDMMC2, RES1, NOR, RES3), - PAD_GPIO(138, GPIO_PH6, POR_PU, H6, SDMMC2, TRACE, NOR, DTV), - PAD_GPIO(139, GPIO_PH7, POR_PU, H7, SDMMC2, TRACE, NOR, DTV), - PAD_GPIO(140, GPIO_PJ7, POR_NP, J7, UD3, RES1, NOR_AD16, NOR_INT2), - PAD_GPIO(141, GPIO_PB0, POR_NP, B0, UD3, RES1, NOR, RES3), - PAD_GPIO(142, GPIO_PB1, POR_NP, B1, UD3, RES1, NOR, RES3), - PAD_GPIO(143, GPIO_PK7, POR_NP, K7, UD3, RES1, NOR, RES3), - PAD_GPIO(144, GPIO_PI0, POR_PU, I0, RES0, RES1, NOR, RES3), - PAD_GPIO(145, GPIO_PI1, POR_PU, I1, RES0, RES1, NOR, RES3), - PAD_GPIO(146, GPIO_PI2, POR_PU, I2, SDMMC2, TRACE, NOR, RES3), - PAD_GPIO(147, GPIO_PI4, POR_PD, I4, SPI4, TRACE, NOR, DCA), - PAD_GPIO(148, GEN2_I2C_SCL, POR_NP, T5, I2C2, RES1, NOR, RES3), - PAD_GPIO(149, GEN2_I2C_SDA, POR_NP, T6, I2C2, RES1, NOR, RES3), - PAD_GPIO(150, SDMMC4_CLK, POR_PD, CC4, SDMMC4, RES1, NOR, RES3), - PAD_GPIO(151, SDMMC4_CMD, POR_PU, T7, SDMMC4, RES1, NOR, RES3), - PAD_GPIO(152, SDMMC4_DAT0, POR_PU, AA0, SDMMC4, SPI3, NOR, RES3), - PAD_GPIO(153, SDMMC4_DAT1, POR_PU, AA1, SDMMC4, SPI3, NOR, RES3), - PAD_GPIO(154, SDMMC4_DAT2, POR_PU, AA2, SDMMC4, SPI3, NOR, RES3), - PAD_GPIO(155, SDMMC4_DAT3, POR_PU, AA3, SDMMC4, SPI3, NOR, RES3), - PAD_GPIO(156, SDMMC4_DAT4, POR_PU, AA4, SDMMC4, SPI3, NOR, RES3), - PAD_GPIO(157, SDMMC4_DAT5, POR_PU, AA5, SDMMC4, SPI3, RES2, RES3), - PAD_GPIO(158, SDMMC4_DAT6, POR_PU, AA6, SDMMC4, SPI3, NOR, RES3), - PAD_GPIO(159, SDMMC4_DAT7, POR_PU, AA7, SDMMC4, RES1, NOR, RES3), - PAD_GPIO(161, CAM_MCLK, POR_PU, CC0, VIMCLK_PRI, VIMCLK_ALT1, - VIMCLK_ALT3, SDMMC2), - PAD_GPIO(162, GPIO_PCC1, POR_PU, CC1, I2S4, RES1, RES2, SDMMC2), - PAD_GPIO(163, GPIO_PBB0, POR_PD, BB0, VGP6, VIMCLK2_PRI, SDMMC2, VIMCLK2_ALT3), - PAD_GPIO(164, CAM_I2C_SCL, POR_NP, BB1, VGP1, I2C3, RES2, SDMMC2), - PAD_GPIO(165, CAM_I2C_SDA, POR_NP, BB2, VGP2, I2C3, RES2, SDMMC2), - PAD_GPIO(166, GPIO_PBB3, POR_PD, BB3, VGP3, DCA, DCB, SDMMC2), - PAD_GPIO(167, GPIO_PBB4, POR_PD, BB4, VGP4, DCA, DCB, SDMMC2), - PAD_GPIO(168, GPIO_PBB5, POR_PD, BB5, VGP5, DCA, RES2, SDMMC2), - PAD_GPIO(169, GPIO_PBB6, POR_PD, BB6, I2S4, RES1, DCB, SDMMC2), - PAD_GPIO(170, GPIO_PBB7, POR_PD, BB7, I2S4, RES1, RES2, SDMMC2), - PAD_GPIO(171, GPIO_PCC2, POR_PU, CC2, I2S4, RES1, SDMMC3, SDMMC2), - PAD_NO_GPIO(172, JTAG_RTCK, POR_PU, RTCK, RES1, RES2, RES3), - PAD_GPIO(173, PWR_I2C_SCL, POR_NP, Z6, I2CPMU, RES1, RES2, RES3), - PAD_GPIO(174, PWR_I2C_SDA, POR_NP, Z7, I2CPMU, RES1, RES2, RES3), - PAD_GPIO(175, KB_ROW0, POR_PD, R0, RES0, RES1, RES2, RES3), - PAD_GPIO(176, KB_ROW1, POR_PD, R1, RES0, RES1, RES2, RES3), - PAD_GPIO(177, KB_ROW2, POR_PD, R2, RES0, RES1, RES2, RES3), - PAD_GPIO(178, KB_ROW3, POR_NP, R3, RES0, DCA, SYS_CLK, DCB), - PAD_GPIO(179, KB_ROW4, POR_PD, R4, RES0, DCA, RES2, DCB), - PAD_GPIO(180, KB_ROW5, POR_PD, R5, RES0, DCA, RES2, DCB), - PAD_GPIO(181, KB_ROW6, POR_PD, R6, RES0, DCA_LSC0, DCA_LSPII, DCB), - PAD_GPIO(182, KB_ROW7, POR_PD, R7, RES0, RES1, CLDVFS, UA3), - PAD_GPIO(183, KB_ROW8, POR_PD, S0, RES0, RES1, CLDVFS, UA3), - PAD_GPIO(184, KB_ROW9, POR_PD, S1, RES0, RES1, RES2, UA3), - PAD_GPIO(185, KB_ROW10, POR_PD, S2, RES0, RES1, RES2, UA3), - PAD_GPIO(186, KB_ROW11, POR_PD, S3, RES0, RES1, RES2, IR3), - PAD_GPIO(187, KB_ROW12, POR_PD, S4, RES0, RES1, RES2, IR3), - PAD_GPIO(188, KB_ROW13, POR_PD, S5, RES0, RES1, SPI2, RES3), - PAD_GPIO(189, KB_ROW14, POR_PD, S6, RES0, RES1, SPI2, RES3), - PAD_GPIO(190, KB_ROW15, POR_PD, S7, RES0, SOC_THERM, RES2, RES3), - PAD_GPIO(191, KB_COL0, POR_PU, Q0, RES0, RES1, SPI2, RES3), - PAD_GPIO(192, KB_COL1, POR_PU, Q1, RES0, RES1, SPI2, RES3), - PAD_GPIO(193, KB_COL2, POR_PU, Q2, RES0, RES1, SPI2, RES3), - PAD_GPIO(194, KB_COL3, POR_PU, Q3, RES0, DCA, PWM2, UA3), - PAD_GPIO(195, KB_COL4, POR_PU, Q4, RES0, OWR, SDMMC3, UA3), - PAD_GPIO(196, KB_COL5, POR_PU, Q5, RES0, RES1, SDMMC3, RES3), - PAD_GPIO(197, KB_COL6, POR_PU, Q6, RES0, RES1, SPI2, UD3), - PAD_GPIO(198, KB_COL7, POR_PU, Q7, RES0, RES1, SPI2, UD3), - PAD_GPIO(199, CLK_32K_OUT, POR_PD, A0, BLINK, SOC_THERM, RES2, RES3), - PAD_NO_GPIO(201, CORE_PWR_REQ, POR_NP, PWRON, RES1, RES2, RES3), - PAD_NO_GPIO(202, CPU_PWR_REQ, POR_NP, CPU, RES1, RES2, RES3), - PAD_NO_GPIO(203, PWR_INT_N, POR_NP, PMICINTR, RES1, RES2, RES3), - PAD_NO_GPIO(204, CLK_32K_IN, POR_NP, CLK_32K_IN, RES1, RES2, RES3), - PAD_NO_GPIO(205, OWR, POR_NP, OWR, RES1, RES2, RES3), - PAD_GPIO(206, DAP1_FS, POR_PD, N0, I2S0, DAP1, NOR, RES3), - PAD_GPIO(207, DAP1_DIN, POR_PD, N1, I2S0, DAP1, NOR, RES3), - PAD_GPIO(208, DAP1_DOUT, POR_PD, N2, I2S0, DAP1, NOR, SATA), - PAD_GPIO(209, DAP1_SCLK, POR_PD, N3, I2S0, DAP1, NOR, RES3), - PAD_GPIO(210, DAP_MCLK1_REQ, POR_PD, EE2, DAP, DAP1, SATA, RES3), - PAD_GPIO(211, DAP_MCLK1, POR_PD, W4, EXTPERIPH1, DAP2, RES2, RES3), - PAD_GPIO(212, SPDIF_IN, POR_PU, K6, SPDIF, RES1, RES2, I2C3), - PAD_GPIO(213, SPDIF_OUT, POR_PU, K5, SPDIF, RES1, RES2, I2C3), - PAD_GPIO(214, DAP2_FS, POR_PD, A2, I2S1, DAP2, NOR, RES3), - PAD_GPIO(215, DAP2_DIN, POR_PD, A4, I2S1, DAP2, NOR, RES3), - PAD_GPIO(216, DAP2_DOUT, POR_PD, A5, I2S1, DAP2, NOR, RES3), - PAD_GPIO(217, DAP2_SCLK, POR_PD, A3, I2S1, SAP2, NOR, RES3), - PAD_GPIO(218, DVFS_PWM, POR_PD, X0, SPI6, CLDVFS, NOR, RES3), - PAD_GPIO(219, GPIO_X1_AUD, POR_PD, X1, SPI6, RES1, NOR, RES3), - PAD_GPIO(220, GPIO_X3_AUD, POR_PU, X3, SPI6, SPI1, NOR, RES3), - PAD_GPIO(221, DVFS_CLK, POR_PU, X2, SPI6, CLDVFS_CLK, NOR, RES3), - PAD_GPIO(222, GPIO_X4_AUD, POR_PD, X4, NOR, SPI1, SPI2, DAP2), - PAD_GPIO(223, GPIO_X5_AUD, POR_PU, X5, NOR, SPI1, SPI2, RES3), - PAD_GPIO(224, GPIO_X6_AUD, POR_PU, X6, SPI6, SPI1, SPI2, NOR), - PAD_GPIO(225, GPIO_X7_AUD, POR_PD, X7, RES0, SPI1, SPI2, RES3), - PAD_GPIO(228, SDMMC3_CLK, POR_PD, A6, SDMMC3, RES1, RES2, SPI3), - PAD_GPIO(229, SDMMC3_CMD, POR_PU, A7, SDMMC3, PWM3, UA3, SPI3), - PAD_GPIO(230, SDMMC3_DAT0, POR_PU, B7, SDMMC3, RES1, RES2, SPI3), - PAD_GPIO(231, SDMMC3_DAT1, POR_PU, B6, SDMMC3, PWM2, UA3, SPI3), - PAD_GPIO(232, SDMMC3_DAT2, POR_PU, B5, SDMMC3, PWM1, DCA, SPI3), - PAD_GPIO(233, SDMMC3_DAT3, POR_PU, B4, SDMMC3, PWM0, DCB, SPI3), - PAD_GPIO(239, PEX_L0_RST_N, POR_NP, DD1, PE0, RES1, RES2, RES3), - PAD_GPIO(240, PEX_L0_CLKREQ_N, POR_NP, DD2, PE0, RES1, RES2, RES3), - PAD_GPIO(241, PEX_WAKE_N, POR_NP, DD3, PE, RES1, RES2, RES3), - PAD_GPIO(243, PEX_L1_RST_N, POR_NP, DD5, PE1, RES1, RES2, RES3), - PAD_GPIO(244, PEX_L1_CLKREQ_N, POR_NP, DD6, PE1, RES1, RES2, RES3), - PAD_GPIO(248, HDMI_CEC, POR_NP, EE3, CEC, RES1, RES2, RES3), - PAD_GPIO(249, SDMMC1_WP_N, POR_PU, V3, SDMMC1, CLK12M, SPI4, UA3), - PAD_GPIO(250, SDMMC3_CD_N, POR_PU, V2, SDMMC3, OWR, RES2, RES3), - PAD_GPIO(251, GPIO_W2_AUD, POR_PU, W2, SPI6, RES1, SPI2, I2C1), - PAD_GPIO(252, GPIO_W3_AUD, POR_PU, W3, SPI6, SPI1, SPI2, I2C1), - PAD_GPIO(253, USB_VBUS_EN0, POR_NP, N4, USB, RES1, RES2, RES3), - PAD_GPIO(254, USB_VBUS_EN1, POR_NP, N5, USB, RES1, RES2, RES3), - PAD_GPIO(255, SDMMC3_CLK_LB_IN, POR_PD, EE5, SDMMC3, RES1, RES2, RES3), - PAD_GPIO(256, SDMMC3_CLK_LB_OUT, POR_NP, EE4, SDMMC3, RES1, RES2, RES3), - PAD_NO_GPIO(258, RESET_OUT_N, POR_NP, RES0, RES1, RES2, RESET), - PAD_GPIO(259, KB_ROW16, POR_PD, T0, RES0, RES1, RES2, UC3), - PAD_GPIO(260, KB_ROW17, POR_PD, T1, RES0, RES1, RES2, UC3), - PAD_GPIO(261, USB_VBUS_EN2, POR_NP, FF1, USB, RES1, RES2, RES3), - PAD_GPIO(262, GPIO_PFF2, POR_NP, FF2, SATA, RES1, RES2, RES3), - PAD_GPIO(268, DP_HPD, POR_NP, FF0, DP, RES1, RES2, RES3), -}; - -#endif /* __SOC_NVIDIA_TEGRA132_PINMUX_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/pmc.h b/src/soc/nvidia/tegra132/include/soc/pmc.h deleted file mode 100644 index 5012b48c85..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/pmc.h +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _TEGRA132_PMC_H_ -#define _TEGRA132_PMC_H_ - -#include <stdint.h> - -enum { - POWER_PARTID_CRAIL = 0, - POWER_PARTID_TD = 1, - POWER_PARTID_VE = 2, - POWER_PARTID_VDE = 4, - POWER_PARTID_L2C = 5, - POWER_PARTID_MPE = 6, - POWER_PARTID_HEG = 7, - POWER_PARTID_CE1 = 9, - POWER_PARTID_CE2 = 10, - POWER_PARTID_CE3 = 11, - POWER_PARTID_CELP = 12, - POWER_PARTID_CE0 = 14, - POWER_PARTID_C0NC = 15, - POWER_PARTID_C1NC = 16, - POWER_PARTID_SOR = 17, - POWER_PARTID_DIS = 18, - POWER_PARTID_DISB = 19, - POWER_PARTID_XUSBA = 20, - POWER_PARTID_XUSBB = 21, - POWER_PARTID_XUSBC = 22 -}; - -struct tegra_pmc_regs { - u32 cntrl; - u32 sec_disable; - u32 pmc_swrst; - u32 wake_mask; - u32 wake_lvl; - u32 wake_status; - u32 sw_wake_status; - u32 dpd_pads_oride; - u32 dpd_sample; - u32 dpd_enable; - u32 pwrgate_timer_off; - u32 clamp_status; - u32 pwrgate_toggle; - u32 remove_clamping_cmd; - u32 pwrgate_status; - u32 pwrgood_timer; - u32 blink_timer; - u32 no_iopower; - u32 pwr_det; - u32 pwr_det_latch; - u32 scratch0; - u32 scratch1; - u32 scratch2; - u32 scratch3; - u32 scratch4; - u32 scratch5; - u32 scratch6; - u32 scratch7; - u32 scratch8; - u32 scratch9; - u32 scratch10; - u32 scratch11; - u32 scratch12; - u32 scratch13; - u32 scratch14; - u32 scratch15; - u32 scratch16; - u32 scratch17; - u32 scratch18; - u32 scratch19; - u32 odmdata; - u32 scratch21; - u32 scratch22; - u32 scratch23; - u32 secure_scratch0; - u32 secure_scratch1; - u32 secure_scratch2; - u32 secure_scratch3; - u32 secure_scratch4; - u32 secure_scratch5; - u32 cpupwrgood_timer; - u32 cpupwroff_timer; - u32 pg_mask; - u32 pg_mask_1; - u32 auto_wake_lvl; - u32 auto_wake_lvl_mask; - u32 wake_delay; - u32 pwr_det_val; - u32 ddr_pwr; - u32 usb_debounce_del; - u32 usb_a0; - u32 crypto_op; - u32 pllp_wb0_override; - u32 scratch24; - u32 scratch25; - u32 scratch26; - u32 scratch27; - u32 scratch28; - u32 scratch29; - u32 scratch30; - u32 scratch31; - u32 scratch32; - u32 scratch33; - u32 scratch34; - u32 scratch35; - u32 scratch36; - u32 scratch37; - u32 scratch38; - u32 scratch39; - u32 scratch40; - u32 scratch41; - u32 scratch42; - u32 bondout_mirror[3]; - u32 sys_33v_en; - u32 bondout_mirror_access; - u32 gate; - u32 wake2_mask; - u32 wake2_lvl; - u32 wake2_status; - u32 sw_wake2_status; - u32 auto_wake2_lvl_mask; - u32 pg_mask_2; - u32 pg_mask_ce1; - u32 pg_mask_ce2; - u32 pg_mask_ce3; - u32 pwrgate_timer_ce[7]; - u32 pcx_edpd_cntrl; - u32 osc_edpd_over; - u32 clk_out_cntrl; - u32 sata_pwrgt; - u32 sensor_ctrl; - u32 rst_status; - u32 io_dpd_req; - u32 io_dpd_status; - u32 io_dpd2_req; - u32 io_dpd2_status; - u32 sel_dpd_tim; - u32 vddp_sel; - u32 ddr_cfg; - u32 e_no_vttgen; - u8 _rsv0[4]; - u32 pllm_wb0_override_freq; - u32 test_pwrgate; - u32 pwrgate_timer_mult; - u32 dis_sel_dpd; - u32 utmip_uhsic_triggers; - u32 utmip_uhsic_saved_state; - u32 utmip_pad_cfg; - u32 utmip_term_pad_cfg; - u32 utmip_uhsic_sleep_cfg; - u32 utmip_uhsic_sleepwalk_cfg; - u32 utmip_sleepwalk_p[3]; - u32 uhsic_sleepwalk_p0; - u32 utmip_uhsic_status; - u32 utmip_uhsic_fake; - u32 bondout_mirror3[5 - 3]; - u32 secure_scratch6; - u32 secure_scratch7; - u32 scratch43; - u32 scratch44; - u32 scratch45; - u32 scratch46; - u32 scratch47; - u32 scratch48; - u32 scratch49; - u32 scratch50; - u32 scratch51; - u32 scratch52; - u32 scratch53; - u32 scratch54; - u32 scratch55; - u32 scratch0_eco; - u32 por_dpd_ctrl; - u32 scratch2_eco; - u32 utmip_uhsic_line_wakeup; - u32 utmip_bias_master_cntrl; - u32 utmip_master_config; - u32 td_pwrgate_inter_part_timer; - u32 utmip_uhsic2_triggers; - u32 utmip_uhsic2_saved_state; - u32 utmip_uhsic2_sleep_cfg; - u32 utmip_uhsic2_sleepwalk_cfg; - u32 uhsic2_sleepwalk_p1; - u32 utmip_uhsic2_status; - u32 utmip_uhsic2_fake; - u32 utmip_uhsic2_line_wakeup; - u32 utmip_master2_config; - u32 utmip_uhsic_rpd_cfg; - u32 pg_mask_ce0; - u32 pg_mask3[5 - 3]; - u32 pllm_wb0_override2; - u32 tsc_mult; - u32 cpu_vsense_override; - u32 glb_amap_cfg; - u32 sticky_bits; - u32 sec_disable2; - u32 weak_bias; - u32 reg_short; - u32 pg_mask_andor; - u8 _rsv1[0x2c]; - u32 secure_scratch8; - u32 secure_scratch9; - u32 secure_scratch10; - u32 secure_scratch11; - u32 secure_scratch12; - u32 secure_scratch13; - u32 secure_scratch14; - u32 secure_scratch15; - u32 secure_scratch16; - u32 secure_scratch17; - u32 secure_scratch18; - u32 secure_scratch19; - u32 secure_scratch20; - u32 secure_scratch21; - u32 secure_scratch22; - u32 secure_scratch23; - u32 secure_scratch24; - u32 secure_scratch25; - u32 secure_scratch26; - u32 secure_scratch27; - u32 secure_scratch28; - u32 secure_scratch29; - u32 secure_scratch30; - u32 secure_scratch31; - u32 secure_scratch32; - u32 secure_scratch33; - u32 secure_scratch34; - u32 secure_scratch35; - u8 _rsv2[0xd0]; - u32 cntrl2; - u8 _rsv3[0x18]; - u32 io_dpd3_req; - u32 io_dqd3_status; - u32 strapping_opt_a; - u8 _rsv4[0x198]; - u32 scratch56; - u32 scratch57; - u32 scratch58; - u32 scratch59; - u32 scratch60; - u32 scratch61; - u32 scratch62; - u32 scratch63; - u32 scratch64; - u32 scratch65; - u32 scratch66; - u32 scratch67; - u32 scratch68; - u32 scratch69; - u32 scratch70; - u32 scratch71; - u32 scratch72; - u32 scratch73; - u32 scratch74; - u32 scratch75; - u32 scratch76; - u32 scratch77; - u32 scratch78; - u32 scratch79; - u32 scratch80; - u32 scratch81; - u32 scratch82; - u32 scratch83; - u32 scratch84; - u32 scratch85; - u32 scratch86; - u32 scratch87; - u32 scratch88; - u32 scratch89; - u32 scratch90; - u32 scratch91; - u32 scratch92; - u32 scratch93; - u32 scratch94; - u32 scratch95; - u32 scratch96; - u32 scratch97; - u32 scratch98; - u32 scratch99; - u32 scratch100; - u32 scratch101; - u32 scratch102; - u32 scratch103; - u32 scratch104; - u32 scratch105; - u32 scratch106; - u32 scratch107; - u32 scratch108; - u32 scratch109; - u32 scratch110; - u32 scratch111; - u32 scratch112; - u32 scratch113; - u32 scratch114; - u32 scratch115; - u32 scratch116; - u32 scratch117; - u32 scratch118; - u32 scratch119; -}; - -check_member(tegra_pmc_regs, scratch119, 0x6fc); - -enum { - PMC_RST_STATUS_SOURCE_MASK = 0x7, - PMC_RST_STATUS_SOURCE_POR = 0x0, - PMC_RST_STATUS_SOURCE_WATCHDOG = 0x1, - PMC_RST_STATUS_SOURCE_SENSOR = 0x2, - PMC_RST_STATUS_SOURCE_SW_MAIN = 0x3, - PMC_RST_STATUS_SOURCE_LP0 = 0x4, - PMC_RST_STATUS_NUM_SOURCES = 0x5, -}; - -enum { - PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, - PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, - PMC_PWRGATE_TOGGLE_START = 0x1 << 8 -}; - -enum { - PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, - PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, - PMC_CNTRL_RTC_RST = 0x1 << 2, - PMC_CNTRL_KBC_RST = 0x1 << 3, - PMC_CNTRL_MAIN_RST = 0x1 << 4, - PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, - PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, - PMC_CNTRL_BLINK_EN = 0x1 << 7, - PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, - PMC_CNTRL_PWRREQ_OE = 0x1 << 9, - PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, - PMC_CNTRL_SYSCLK_OE = 0x1 << 11, - PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, - PMC_CNTRL_AOINIT = 0x1 << 13, - PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, - PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, - PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, - PMC_CNTRL_INTR_POLARITY = 0x1 << 17, - PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, - PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, - PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, - PMC_CNTRL_CPUPWRGOOD_SEL_MASK = - 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT -}; - -enum { - PMC_DDR_PWR_EMMC_MASK = 1 << 1, - PMC_DDR_PWR_VAL_MASK = 1 << 0, -}; - -enum { - PMC_DDR_CFG_PKG_MASK = 1 << 0, - PMC_DDR_CFG_IF_MASK = 1 << 1, - PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, - PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, -}; - -enum { - PMC_NO_IOPOWER_MEM_MASK = 1 << 7, - PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, -}; - -enum { - PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, - PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, - PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, -}; - -enum { - PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 -}; - -enum { - PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, - PMC_OSC_EDPD_OVER_XOFS_MASK = - 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT -}; - -enum { - PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, - PMC_STRAPPING_OPT_A_RAM_CODE_MASK = - 0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT, -}; - -#endif /* _TEGRA132_PMC_H_ */ diff --git a/src/soc/nvidia/tegra132/include/soc/power.h b/src/soc/nvidia/tegra132/include/soc/power.h deleted file mode 100644 index d6e4198679..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/power.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_POWER_H__ -#define __SOC_NVIDIA_TEGRA132_POWER_H__ - -#include <soc/pmc.h> - -void power_ungate_partition(uint32_t id); - -uint8_t pmc_rst_status(void); -void pmc_print_rst_status(void); - -#endif /* __SOC_NVIDIA_TEGRA132_POWER_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h deleted file mode 100644 index fb25d24596..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/romstage.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ -#define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ - -void romstage(void); -void romstage_mainboard_init(void); - -void mainboard_configure_pmc(void); -void mainboard_enable_vdd_cpu(void); - -#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sdram.h b/src/soc/nvidia/tegra132/include/soc/sdram.h deleted file mode 100644 index d07767bfbd..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/sdram.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_H__ -#define __SOC_NVIDIA_TEGRA132_SDRAM_H__ - -#include <soc/sdram_param.h> - -uint32_t sdram_get_ram_code(void); -void sdram_init(const struct sdram_params *param); - -/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ -void sdram_lp0_save_params(const struct sdram_params *sdram); - -#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_configs.h b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h deleted file mode 100644 index d77bf62f09..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/sdram_configs.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ -#define __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ - -#include <soc/sdram.h> - -/* Loads SDRAM configurations for current system. */ -const struct sdram_params *get_sdram_config(void); - -#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_param.h b/src/soc/nvidia/tegra132/include/soc/sdram_param.h deleted file mode 100644 index ce85058383..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/sdram_param.h +++ /dev/null @@ -1,815 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. The field names are in camel case to ease - * directly converting BCT config files (*.cfg) into C structure. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ -#define __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ - -#include <stddef.h> -#include <stdint.h> - -enum { - /* Specifies the memory type to be undefined */ - NvBootMemoryType_None = 0, - - /* Specifies the memory type to be DDR SDRAM */ - NvBootMemoryType_Ddr = 0, - - /* Specifies the memory type to be LPDDR SDRAM */ - NvBootMemoryType_LpDdr = 0, - - /* Specifies the memory type to be DDR2 SDRAM */ - NvBootMemoryType_Ddr2 = 0, - - /* Specifies the memory type to be LPDDR2 SDRAM */ - NvBootMemoryType_LpDdr2, - - /* Specifies the memory type to be DDR3 SDRAM */ - NvBootMemoryType_Ddr3, - - NvBootMemoryType_Num, - - /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, -}; - -enum { - BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31, - BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0, - BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0, - BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000, - - EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0, -}; - -/** - * Defines the SDRAM parameter structure - */ -struct sdram_params { - - /* Specifies the type of memory device */ - uint32_t MemoryType; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - uint32_t PllMInputDivider; - /* Specifies the N value for PllM */ - uint32_t PllMFeedbackDivider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - uint32_t PllMStableTime; - /* Specifies misc. control bits */ - uint32_t PllMSetupControl; - /* Enables the Div by 2 */ - uint32_t PllMSelectDiv2; - /* Powers down VCO output Level shifter */ - uint32_t PllMPDLshiftPh45; - /* Powers down VCO output Level shifter */ - uint32_t PllMPDLshiftPh90; - /* Powers down VCO output Level shifter */ - uint32_t PllMPDLshiftPh135; - /* Specifies value for Charge Pump Gain Control */ - uint32_t PllMKCP; - /* Specifies VCO gain */ - uint32_t PllMKVCO; - /* Spare BCT param */ - uint32_t EmcBctSpare0; - /* Spare BCT param */ - uint32_t EmcBctSpare1; - /* Spare BCT param */ - uint32_t EmcBctSpare2; - /* Spare BCT param */ - uint32_t EmcBctSpare3; - /* Spare BCT param */ - uint32_t EmcBctSpare4; - /* Spare BCT param */ - uint32_t EmcBctSpare5; - /* Spare BCT param */ - uint32_t EmcBctSpare6; - /* Spare BCT param */ - uint32_t EmcBctSpare7; - /* Spare BCT param */ - uint32_t EmcBctSpare8; - /* Spare BCT param */ - uint32_t EmcBctSpare9; - /* Spare BCT param */ - uint32_t EmcBctSpare10; - /* Spare BCT param */ - uint32_t EmcBctSpare11; - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - uint32_t EmcClockSource; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - uint32_t EmcAutoCalInterval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - uint32_t EmcAutoCalConfig; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - uint32_t EmcAutoCalConfig2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - uint32_t EmcAutoCalConfig3; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - uint32_t EmcAutoCalWait; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - uint32_t EmcAdrCfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - uint32_t EmcPinProgramWait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - uint32_t EmcPinExtraWait; - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - uint32_t EmcTimingControlWait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - uint32_t EmcRc; - /* Specifies the value for EMC_RFC */ - uint32_t EmcRfc; - /* Specifies the value for EMC_RFC_SLR */ - uint32_t EmcRfcSlr; - /* Specifies the value for EMC_RAS */ - uint32_t EmcRas; - /* Specifies the value for EMC_RP */ - uint32_t EmcRp; - /* Specifies the value for EMC_R2R */ - uint32_t EmcR2r; - /* Specifies the value for EMC_W2W */ - uint32_t EmcW2w; - /* Specifies the value for EMC_R2W */ - uint32_t EmcR2w; - /* Specifies the value for EMC_W2R */ - uint32_t EmcW2r; - /* Specifies the value for EMC_R2P */ - uint32_t EmcR2p; - /* Specifies the value for EMC_W2P */ - uint32_t EmcW2p; - /* Specifies the value for EMC_RD_RCD */ - uint32_t EmcRdRcd; - /* Specifies the value for EMC_WR_RCD */ - uint32_t EmcWrRcd; - /* Specifies the value for EMC_RRD */ - uint32_t EmcRrd; - /* Specifies the value for EMC_REXT */ - uint32_t EmcRext; - /* Specifies the value for EMC_WEXT */ - uint32_t EmcWext; - /* Specifies the value for EMC_WDV */ - uint32_t EmcWdv; - /* Specifies the value for EMC_WDV_MASK */ - uint32_t EmcWdvMask; - /* Specifies the value for EMC_QUSE */ - uint32_t EmcQUse; - /* Specifies the value for EMC_QUSE_WIDTH */ - uint32_t EmcQuseWidth; - /* Specifies the value for EMC_IBDLY */ - uint32_t EmcIbdly; - /* Specifies the value for EMC_EINPUT */ - uint32_t EmcEInput; - /* Specifies the value for EMC_EINPUT_DURATION */ - uint32_t EmcEInputDuration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - uint32_t EmcPutermExtra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - uint32_t EmcPutermWidth; - /* Specifies the value for EMC_PUTERM_ADJ */ - uint32_t EmcPutermAdj; - /* Specifies the value for EMC_CDB_CNTL_1 */ - uint32_t EmcCdbCntl1; - /* Specifies the value for EMC_CDB_CNTL_2 */ - uint32_t EmcCdbCntl2; - /* Specifies the value for EMC_CDB_CNTL_3 */ - uint32_t EmcCdbCntl3; - /* Specifies the value for EMC_QRST */ - uint32_t EmcQRst; - /* Specifies the value for EMC_QSAFE */ - uint32_t EmcQSafe; - /* Specifies the value for EMC_RDV */ - uint32_t EmcRdv; - /* Specifies the value for EMC_RDV_MASK */ - uint32_t EmcRdvMask; - /* Specifies the value for EMC_QPOP */ - uint32_t EmcQpop; - /* Specifies the value for EMC_CTT */ - uint32_t EmcCtt; - /* Specifies the value for EMC_CTT_DURATION */ - uint32_t EmcCttDuration; - /* Specifies the value for EMC_REFRESH */ - uint32_t EmcRefresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - uint32_t EmcBurstRefreshNum; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - uint32_t EmcPreRefreshReqCnt; - /* Specifies the value for EMC_PDEX2WR */ - uint32_t EmcPdEx2Wr; - /* Specifies the value for EMC_PDEX2RD */ - uint32_t EmcPdEx2Rd; - /* Specifies the value for EMC_PCHG2PDEN */ - uint32_t EmcPChg2Pden; - /* Specifies the value for EMC_ACT2PDEN */ - uint32_t EmcAct2Pden; - /* Specifies the value for EMC_AR2PDEN */ - uint32_t EmcAr2Pden; - /* Specifies the value for EMC_RW2PDEN */ - uint32_t EmcRw2Pden; - /* Specifies the value for EMC_TXSR */ - uint32_t EmcTxsr; - /* Specifies the value for EMC_TXSRDLL */ - uint32_t EmcTxsrDll; - /* Specifies the value for EMC_TCKE */ - uint32_t EmcTcke; - /* Specifies the value for EMC_TCKESR */ - uint32_t EmcTckesr; - /* Specifies the value for EMC_TPD */ - uint32_t EmcTpd; - /* Specifies the value for EMC_TFAW */ - uint32_t EmcTfaw; - /* Specifies the value for EMC_TRPAB */ - uint32_t EmcTrpab; - /* Specifies the value for EMC_TCLKSTABLE */ - uint32_t EmcTClkStable; - /* Specifies the value for EMC_TCLKSTOP */ - uint32_t EmcTClkStop; - /* Specifies the value for EMC_TREFBW */ - uint32_t EmcTRefBw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - uint32_t EmcFbioCfg5; - /* Specifies the value for EMC_FBIO_CFG6 */ - uint32_t EmcFbioCfg6; - /* Specifies the value for EMC_FBIO_SPARE */ - uint32_t EmcFbioSpare; - - /* Specifies the value for EMC_CFG_RSV */ - uint32_t EmcCfgRsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - uint32_t EmcMrs; - /* Specifies the MP0 command to initialize mode registers */ - uint32_t EmcEmrs; - /* Specifies the MP2 command to initialize mode registers */ - uint32_t EmcEmrs2; - /* Specifies the MP3 command to initialize mode registers */ - uint32_t EmcEmrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - uint32_t EmcMrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - uint32_t EmcMrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - uint32_t EmcMrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - uint32_t EmcMrw4; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - uint32_t EmcMrwExtra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - uint32_t EmcWarmBootMrwExtra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - uint32_t EmcWarmBootExtraModeRegWriteEnable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - uint32_t EmcExtraModeRegWriteEnable; - - /* Specifies the EMC_MRW reset command value */ - uint32_t EmcMrwResetCommand; - /* Specifies the EMC Reset wait time (in microseconds) */ - uint32_t EmcMrwResetNInitWait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - uint32_t EmcMrsWaitCnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - uint32_t EmcMrsWaitCnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - uint32_t EmcCfg; - /* Specifies the value for EMC_CFG_2 */ - uint32_t EmcCfg2; - /* Specifies the pipe bypass controls */ - uint32_t EmcCfgPipe; - /* Specifies the value for EMC_DBG */ - uint32_t EmcDbg; - /* Specifies the value for EMC_CMDQ */ - uint32_t EmcCmdQ; - /* Specifies the value for EMC_MC2EMCQ */ - uint32_t EmcMc2EmcQ; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - uint32_t EmcDynSelfRefControl; - - /* Specifies the value for MEM_INIT_DONE */ - uint32_t AhbArbitrationXbarCtrlMemInitDone; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - uint32_t EmcCfgDigDll; - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - uint32_t EmcCfgDigDllPeriod; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - uint32_t EmcDevSelect; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - uint32_t EmcSelDpdCtrl; - - /* Pads trimmer delays */ - - /* Specifies the value for EMC_DLL_XFORM_DQS0 */ - uint32_t EmcDllXformDqs0; - /* Specifies the value for EMC_DLL_XFORM_DQS1 */ - uint32_t EmcDllXformDqs1; - /* Specifies the value for EMC_DLL_XFORM_DQS2 */ - uint32_t EmcDllXformDqs2; - /* Specifies the value for EMC_DLL_XFORM_DQS3 */ - uint32_t EmcDllXformDqs3; - /* Specifies the value for EMC_DLL_XFORM_DQS4 */ - uint32_t EmcDllXformDqs4; - /* Specifies the value for EMC_DLL_XFORM_DQS5 */ - uint32_t EmcDllXformDqs5; - /* Specifies the value for EMC_DLL_XFORM_DQS6 */ - uint32_t EmcDllXformDqs6; - /* Specifies the value for EMC_DLL_XFORM_DQS7 */ - uint32_t EmcDllXformDqs7; - /* Specifies the value for EMC_DLL_XFORM_DQS8 */ - uint32_t EmcDllXformDqs8; - /* Specifies the value for EMC_DLL_XFORM_DQS9 */ - uint32_t EmcDllXformDqs9; - /* Specifies the value for EMC_DLL_XFORM_DQS10 */ - uint32_t EmcDllXformDqs10; - /* Specifies the value for EMC_DLL_XFORM_DQS11 */ - uint32_t EmcDllXformDqs11; - /* Specifies the value for EMC_DLL_XFORM_DQS12 */ - uint32_t EmcDllXformDqs12; - /* Specifies the value for EMC_DLL_XFORM_DQS13 */ - uint32_t EmcDllXformDqs13; - /* Specifies the value for EMC_DLL_XFORM_DQS14 */ - uint32_t EmcDllXformDqs14; - /* Specifies the value for EMC_DLL_XFORM_DQS15 */ - uint32_t EmcDllXformDqs15; - /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ - uint32_t EmcDllXformQUse0; - /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ - uint32_t EmcDllXformQUse1; - /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ - uint32_t EmcDllXformQUse2; - /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ - uint32_t EmcDllXformQUse3; - /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ - uint32_t EmcDllXformQUse4; - /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ - uint32_t EmcDllXformQUse5; - /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ - uint32_t EmcDllXformQUse6; - /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ - uint32_t EmcDllXformQUse7; - /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ - uint32_t EmcDllXformAddr0; - /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ - uint32_t EmcDllXformAddr1; - /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ - uint32_t EmcDllXformAddr2; - /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ - uint32_t EmcDllXformAddr3; - /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ - uint32_t EmcDllXformAddr4; - /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ - uint32_t EmcDllXformAddr5; - /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ - uint32_t EmcDllXformQUse8; - /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ - uint32_t EmcDllXformQUse9; - /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ - uint32_t EmcDllXformQUse10; - /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ - uint32_t EmcDllXformQUse11; - /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ - uint32_t EmcDllXformQUse12; - /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ - uint32_t EmcDllXformQUse13; - /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ - uint32_t EmcDllXformQUse14; - /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ - uint32_t EmcDllXformQUse15; - /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ - uint32_t EmcDliTrimTxDqs0; - /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ - uint32_t EmcDliTrimTxDqs1; - /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ - uint32_t EmcDliTrimTxDqs2; - /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ - uint32_t EmcDliTrimTxDqs3; - /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ - uint32_t EmcDliTrimTxDqs4; - /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ - uint32_t EmcDliTrimTxDqs5; - /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ - uint32_t EmcDliTrimTxDqs6; - /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ - uint32_t EmcDliTrimTxDqs7; - /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ - uint32_t EmcDliTrimTxDqs8; - /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ - uint32_t EmcDliTrimTxDqs9; - /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ - uint32_t EmcDliTrimTxDqs10; - /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ - uint32_t EmcDliTrimTxDqs11; - /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ - uint32_t EmcDliTrimTxDqs12; - /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ - uint32_t EmcDliTrimTxDqs13; - /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ - uint32_t EmcDliTrimTxDqs14; - /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ - uint32_t EmcDliTrimTxDqs15; - /* Specifies the value for EMC_DLL_XFORM_DQ0 */ - uint32_t EmcDllXformDq0; - /* Specifies the value for EMC_DLL_XFORM_DQ1 */ - uint32_t EmcDllXformDq1; - /* Specifies the value for EMC_DLL_XFORM_DQ2 */ - uint32_t EmcDllXformDq2; - /* Specifies the value for EMC_DLL_XFORM_DQ3 */ - uint32_t EmcDllXformDq3; - /* Specifies the value for EMC_DLL_XFORM_DQ4 */ - uint32_t EmcDllXformDq4; - /* Specifies the value for EMC_DLL_XFORM_DQ5 */ - uint32_t EmcDllXformDq5; - /* Specifies the value for EMC_DLL_XFORM_DQ6 */ - uint32_t EmcDllXformDq6; - /* Specifies the value for EMC_DLL_XFORM_DQ7 */ - uint32_t EmcDllXformDq7; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - uint32_t WarmBootWait; - - /* Specifies the value for EMC_CTT_TERM_CTRL */ - uint32_t EmcCttTermCtrl; - - /* Specifies the value for EMC_ODT_WRITE */ - uint32_t EmcOdtWrite; - /* Specifies the value for EMC_ODT_WRITE */ - uint32_t EmcOdtRead; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - uint32_t EmcZcalInterval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - uint32_t EmcZcalWaitCnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - uint32_t EmcZcalMrwCmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - uint32_t EmcMrsResetDll; - /* Specifies the command for ZQ initialization of device 0 */ - uint32_t EmcZcalInitDev0; - /* Specifies the command for ZQ initialization of device 1 */ - uint32_t EmcZcalInitDev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - uint32_t EmcZcalInitWait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - uint32_t EmcZcalWarmColdBootEnables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - uint32_t EmcMrwLpddr2ZcalWarmBoot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - uint32_t EmcZqCalDdr3WarmBoot; - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - uint32_t EmcZcalWarmBootWait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - uint32_t EmcMrsWarmBootEnable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - uint32_t EmcMrsResetDllWait; - /* Specifies the extra MRS command to initialize mode registers */ - uint32_t EmcMrsExtra; - /* Specifies the extra MRS command at warm boot */ - uint32_t EmcWarmBootMrsExtra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - uint32_t EmcEmrsDdr2DllEnable; - /* Specifies the MRS command to reset the DDR2 DLL */ - uint32_t EmcMrsDdr2DllReset; - /* Specifies the EMRS command to set OCD calibration */ - uint32_t EmcEmrsDdr2OcdCalib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - uint32_t EmcDdr2Wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - uint32_t EmcClkenOverride; - /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ - uint32_t McDisExtraSnapLevels; - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - uint32_t EmcExtraRefreshNum; - /* Specifies the master override for all EMC clocks */ - uint32_t EmcClkenOverrideAllWarmBoot; - /* Specifies the master override for all MC clocks */ - uint32_t McClkenOverrideAllWarmBoot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - uint32_t EmcCfgDigDllPeriodWarmBoot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - uint32_t PmcVddpSel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - uint32_t PmcVddpSelWait; - /* Specifies the value for PMC_DDR_PWR */ - uint32_t PmcDdrPwr; - /* Specifies the value for PMC_DDR_CFG */ - uint32_t PmcDdrCfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - uint32_t PmcIoDpd3Req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - uint32_t PmcIoDpd3ReqWait; - /* Specifies the value for PMC_REG_SHORT */ - uint32_t PmcRegShort; - /* Specifies the value for PMC_NO_IOPOWER */ - uint32_t PmcNoIoPower; - /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ - uint32_t PmcPorDpdCtrlWait; - /* Specifies the value for EMC_XM2CMDPADCTRL */ - uint32_t EmcXm2CmdPadCtrl; - /* Specifies the value for EMC_XM2CMDPADCTRL2 */ - uint32_t EmcXm2CmdPadCtrl2; - /* Specifies the value for EMC_XM2CMDPADCTRL3 */ - uint32_t EmcXm2CmdPadCtrl3; - /* Specifies the value for EMC_XM2CMDPADCTRL4 */ - uint32_t EmcXm2CmdPadCtrl4; - /* Specifies the value for EMC_XM2CMDPADCTRL5 */ - uint32_t EmcXm2CmdPadCtrl5; - /* Specifies the value for EMC_XM2DQSPADCTRL */ - uint32_t EmcXm2DqsPadCtrl; - /* Specifies the value for EMC_XM2DQSPADCTRL2 */ - uint32_t EmcXm2DqsPadCtrl2; - /* Specifies the value for EMC_XM2DQSPADCTRL3 */ - uint32_t EmcXm2DqsPadCtrl3; - /* Specifies the value for EMC_XM2DQSPADCTRL4 */ - uint32_t EmcXm2DqsPadCtrl4; - /* Specifies the value for EMC_XM2DQSPADCTRL5 */ - uint32_t EmcXm2DqsPadCtrl5; - /* Specifies the value for EMC_XM2DQSPADCTRL6 */ - uint32_t EmcXm2DqsPadCtrl6; - /* Specifies the value for EMC_XM2DQPADCTRL */ - uint32_t EmcXm2DqPadCtrl; - /* Specifies the value for EMC_XM2DQPADCTRL2 */ - uint32_t EmcXm2DqPadCtrl2; - /* Specifies the value for EMC_XM2DQPADCTRL3 */ - uint32_t EmcXm2DqPadCtrl3; - /* Specifies the value for EMC_XM2CLKPADCTRL */ - uint32_t EmcXm2ClkPadCtrl; - /* Specifies the value for EMC_XM2CLKPADCTRL2 */ - uint32_t EmcXm2ClkPadCtrl2; - /* Specifies the value for EMC_XM2COMPPADCTRL */ - uint32_t EmcXm2CompPadCtrl; - /* Specifies the value for EMC_XM2VTTGENPADCTRL */ - uint32_t EmcXm2VttGenPadCtrl; - /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ - uint32_t EmcXm2VttGenPadCtrl2; - /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ - uint32_t EmcXm2VttGenPadCtrl3; - /* Specifies the value for EMC_ACPD_CONTROL */ - uint32_t EmcAcpdControl; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ - uint32_t EmcSwizzleRank0ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - uint32_t EmcSwizzleRank0Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - uint32_t EmcSwizzleRank0Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - uint32_t EmcSwizzleRank0Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - uint32_t EmcSwizzleRank0Byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ - uint32_t EmcSwizzleRank1ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - uint32_t EmcSwizzleRank1Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - uint32_t EmcSwizzleRank1Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - uint32_t EmcSwizzleRank1Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - uint32_t EmcSwizzleRank1Byte3; - - /* Specifies the value for EMC_DSR_VTTGEN_DRV */ - uint32_t EmcDsrVttgenDrv; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - uint32_t EmcTxdsrvttgen; - /* Specifies the value for EMC_BGBIAS_CTL */ - uint32_t EmcBgbiasCtl0; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - uint32_t McEmemAdrCfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - uint32_t McEmemAdrCfgDev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - uint32_t McEmemAdrCfgDev1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - uint32_t McEmemAdrCfgBankMask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - uint32_t McEmemAdrCfgBankMask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - uint32_t McEmemAdrCfgBankMask2; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ - uint32_t McEmemAdrCfgBankSwizzle3; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - uint32_t McEmemCfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - uint32_t McEmemArbCfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - uint32_t McEmemArbOutstandingReq; - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - uint32_t McEmemArbTimingRcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - uint32_t McEmemArbTimingRp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - uint32_t McEmemArbTimingRc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - uint32_t McEmemArbTimingRas; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - uint32_t McEmemArbTimingFaw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - uint32_t McEmemArbTimingRrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - uint32_t McEmemArbTimingRap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - uint32_t McEmemArbTimingWap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - uint32_t McEmemArbTimingR2R; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - uint32_t McEmemArbTimingW2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - uint32_t McEmemArbTimingR2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - uint32_t McEmemArbTimingW2R; - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - uint32_t McEmemArbDaTurns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - uint32_t McEmemArbDaCovers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - uint32_t McEmemArbMisc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - uint32_t McEmemArbMisc1; - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - uint32_t McEmemArbRing1Throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - uint32_t McEmemArbOverride; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - uint32_t McEmemArbOverride1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - uint32_t McEmemArbRsv; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - uint32_t McClkenOverride; - - /* Specifies the value for MC_STAT_CONTROL */ - uint32_t McStatControl; - /* Specifies the value for MC_DISPLAY_SNAP_RING */ - uint32_t McDisplaySnapRing; - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - uint32_t McVideoProtectBom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - uint32_t McVideoProtectBomAdrHi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - uint32_t McVideoProtectSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - uint32_t McVideoProtectVprOverride; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - uint32_t McVideoProtectVprOverride1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - uint32_t McVideoProtectGpuOverride0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - uint32_t McVideoProtectGpuOverride1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - uint32_t McSecCarveoutBom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - uint32_t McSecCarveoutAdrHi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - uint32_t McSecCarveoutSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. - VIDEO_PROTECT_WRITE_ACCESS */ - uint32_t McVideoProtectWriteAccess; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. - SEC_CARVEOUT_WRITE_ACCESS */ - uint32_t McSecCarveoutProtectWriteAccess; - - /* Specifies enable for CA training */ - uint32_t EmcCaTrainingEnable; - /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ - uint32_t EmcCaTrainingTimingCntl1; - /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ - uint32_t EmcCaTrainingTimingCntl2; - /* Set if bit 6 select is greater than bit 7 select; uses aremc. - spec packet SWIZZLE_BIT6_GT_BIT7 */ - uint32_t SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot ROM write */ - uint32_t BootRomPatchControl; - /* Specifies data for patched boot ROM write */ - uint32_t BootRomPatchData; - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - uint32_t McMtsCarveoutBom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - uint32_t McMtsCarveoutAdrHi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - uint32_t McMtsCarveoutSizeMb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - uint32_t McMtsCarveoutRegCtrl; - - /* End of generated code by warmboot_code_gen */ -}; - -check_member(sdram_params, McMtsCarveoutRegCtrl, 0x4d0); - -#endif /* __SOC_NVIDIA_TEGRA132_SDRAM_PARAM_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sor.h b/src/soc/nvidia/tegra132/include/soc/sor.h deleted file mode 100644 index 3413af5807..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/sor.h +++ /dev/null @@ -1,930 +0,0 @@ -/* - * drivers/video/tegra/dc/sor_regs.h - * - * Copyright (c) 2011-2014, NVIDIA Corporation. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __TEGRA132_SOR_H__ -#define __TEGRA132_SOR_H__ - -#define NV_SOR_SUPER_STATE0 (0x1) -#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT (0) -#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK (0x1) -#define NV_SOR_SUPER_STATE1 (0x2) -#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT (3) -#define NV_SOR_SUPER_STATE1_ATTACHED_NO (0 << 3) -#define NV_SOR_SUPER_STATE1_ATTACHED_YES (1 << 3) -#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT (2) -#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2) -#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2) -#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT (0) -#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK (0x3) -#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP (0) -#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE (1) -#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE (2) -#define NV_SOR_STATE0 (0x3) -#define NV_SOR_STATE0_UPDATE_SHIFT (0) -#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK (0x1) -#define NV_SOR_STATE1 (0x4) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT (17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17) -#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17) -#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT (15) -#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK (0x3 << 15) -#define NV_SOR_STATE1_ASY_REPLICATE_OFF (0 << 15) -#define NV_SOR_STATE1_ASY_REPLICATE_X2 (1 << 15) -#define NV_SOR_STATE1_ASY_REPLICATE_X4 (2 << 15) -#define NV_SOR_STATE1_ASY_DEPOL_SHIFT (14) -#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK (0x1 << 14) -#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14) -#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14) -#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT (13) -#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK (0x1 << 13) -#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13) -#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13) -#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT (12) -#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK (0x1 << 12) -#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12) -#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12) -#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT (8) -#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8) -#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8) -#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A (8 << 8) -#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B (9 << 8) -#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM (15 << 8) -#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT (6) -#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK (0x3 << 6) -#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6) -#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6) -#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6) -#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT (4) -#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK (0x3 << 4) -#define NV_SOR_STATE1_ASY_SUBOWNER_NONE (0 << 4) -#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4) -#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4) -#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH (3 << 4) -#define NV_SOR_STATE1_ASY_OWNER_SHIFT (0) -#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK (0xf) -#define NV_SOR_STATE1_ASY_OWNER_NONE (0) -#define NV_SOR_STATE1_ASY_OWNER_HEAD0 (1) -#define NV_SOR_STATE1_ASY_OWNER_HEAD1 (2) -#define NV_HEAD_STATE0(i) (0x5) -#define NV_HEAD_STATE0_INTERLACED_SHIFT (4) -#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (0x3 << 4) -#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4) -#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4) -#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT (3) -#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (0x1 << 3) -#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3) -#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3) -#define NV_HEAD_STATE0_DYNRANGE_SHIFT (2) -#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (0x1 << 2) -#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2) -#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2) -#define NV_HEAD_STATE0_COLORSPACE_SHIFT (0) -#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK (0x3) -#define NV_HEAD_STATE0_COLORSPACE_RGB (0) -#define NV_HEAD_STATE0_COLORSPACE_YUV_601 (1) -#define NV_HEAD_STATE0_COLORSPACE_YUV_709 (2) -#define NV_HEAD_STATE1(i) (0x7 + i) -#define NV_HEAD_STATE1_VTOTAL_SHIFT (16) -#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16) -#define NV_HEAD_STATE1_HTOTAL_SHIFT (0) -#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK (0x7fff) -#define NV_HEAD_STATE2(i) (0x9 + i) -#define NV_HEAD_STATE2_VSYNC_END_SHIFT (16) -#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16) -#define NV_HEAD_STATE2_HSYNC_END_SHIFT (0) -#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK (0x7fff) -#define NV_HEAD_STATE3(i) (0xb + i) -#define NV_HEAD_STATE3_VBLANK_END_SHIFT (16) -#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16) -#define NV_HEAD_STATE3_HBLANK_END_SHIFT (0) -#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK (0x7fff) -#define NV_HEAD_STATE4(i) (0xd + i) -#define NV_HEAD_STATE4_VBLANK_START_SHIFT (16) -#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16) -#define NV_HEAD_STATE4_HBLANK_START_SHIFT (0) -#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK (0x7fff) -#define NV_HEAD_STATE5(i) (0xf + i) -#define NV_SOR_CRC_CNTRL (0x11) -#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT (0) -#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO (0) -#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES (1) -#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS (0) -#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN (1) -#define NV_SOR_CLK_CNTRL (0x13) -#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT (0) -#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK (0x3) -#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0) -#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1) -#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2) -#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3) -#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT (2) -#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) -#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2) -#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2) -#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2) -#define NV_SOR_CAP (0x14) -#define NV_SOR_CAP_DP_A_SHIFT (24) -#define NV_SOR_CAP_DP_A_DEFAULT_MASK (0x1 << 24) -#define NV_SOR_CAP_DP_A_FALSE (0 << 24) -#define NV_SOR_CAP_DP_A_TRUE (1 << 24) -#define NV_SOR_CAP_DP_B_SHIFT (25) -#define NV_SOR_CAP_DP_B_DEFAULT_MASK (0x1 << 24) -#define NV_SOR_CAP_DP_B_FALSE (0 << 24) -#define NV_SOR_CAP_DP_B_TRUE (1 << 24) -#define NV_SOR_PWR (0x15) -#define NV_SOR_PWR_SETTING_NEW_SHIFT (31) -#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK (0x1 << 31) -#define NV_SOR_PWR_SETTING_NEW_DONE (0 << 31) -#define NV_SOR_PWR_SETTING_NEW_PENDING (1 << 31) -#define NV_SOR_PWR_SETTING_NEW_TRIGGER (1 << 31) -#define NV_SOR_PWR_MODE_SHIFT (28) -#define NV_SOR_PWR_MODE_DEFAULT_MASK (0x1 << 28) -#define NV_SOR_PWR_MODE_NORMAL (0 << 28) -#define NV_SOR_PWR_MODE_SAFE (1 << 28) -#define NV_SOR_PWR_HALT_DELAY_SHIFT (24) -#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK (0x1 << 24) -#define NV_SOR_PWR_HALT_DELAY_DONE (0 << 24) -#define NV_SOR_PWR_HALT_DELAY_ACTIVE (1 << 24) -#define NV_SOR_PWR_SAFE_START_SHIFT (17) -#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK (0x1 << 17) -#define NV_SOR_PWR_SAFE_START_NORMAL (0 << 17) -#define NV_SOR_PWR_SAFE_START_ALT (1 << 17) -#define NV_SOR_PWR_SAFE_STATE_SHIFT (16) -#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK (0x1 << 16) -#define NV_SOR_PWR_SAFE_STATE_PD (0 << 16) -#define NV_SOR_PWR_SAFE_STATE_PU (1 << 16) -#define NV_SOR_PWR_NORMAL_START_SHIFT (1) -#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK (0x1 << 1) -#define NV_SOR_PWR_NORMAL_START_NORMAL (0 << 16) -#define NV_SOR_PWR_NORMAL_START_ALT (1 << 16) -#define NV_SOR_PWR_NORMAL_STATE_SHIFT (0) -#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK (0x1) -#define NV_SOR_PWR_NORMAL_STATE_PD (0) -#define NV_SOR_PWR_NORMAL_STATE_PU (1) -#define NV_SOR_TEST (0x16) -#define NV_SOR_TEST_TESTMUX_SHIFT (24) -#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK (0xff << 24) -#define NV_SOR_TEST_TESTMUX_AVSS (0 << 24) -#define NV_SOR_TEST_TESTMUX_CLOCKIN (2 << 24) -#define NV_SOR_TEST_TESTMUX_PLL_VOL (4 << 24) -#define NV_SOR_TEST_TESTMUX_SLOWCLKINT (8 << 24) -#define NV_SOR_TEST_TESTMUX_AVDD (16 << 24) -#define NV_SOR_TEST_TESTMUX_VDDREG (32 << 24) -#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG (64 << 24) -#define NV_SOR_TEST_TESTMUX_REGREF_AVDD (128 << 24) -#define NV_SOR_TEST_CRC_SHIFT (23) -#define NV_SOR_TEST_CRC_PRE_SERIALIZE (0 << 23) -#define NV_SOR_TEST_CRC_POST_DESERIALIZE (1 << 23) -#define NV_SOR_TEST_TPAT_SHIFT (20) -#define NV_SOR_TEST_TPAT_DEFAULT_MASK (0x7 << 20) -#define NV_SOR_TEST_TPAT_LO (0 << 20) -#define NV_SOR_TEST_TPAT_TDAT (1 << 20) -#define NV_SOR_TEST_TPAT_RAMP (2 << 20) -#define NV_SOR_TEST_TPAT_WALK (3 << 20) -#define NV_SOR_TEST_TPAT_MAXSTEP (4 << 20) -#define NV_SOR_TEST_TPAT_MINSTEP (5 << 20) -#define NV_SOR_TEST_DSRC_SHIFT (16) -#define NV_SOR_TEST_DSRC_DEFAULT_MASK (0x3 << 16) -#define NV_SOR_TEST_DSRC_NORMAL (0 << 16) -#define NV_SOR_TEST_DSRC_DEBUG (1 << 16) -#define NV_SOR_TEST_DSRC_TGEN (2 << 16) -#define NV_SOR_TEST_HEAD_NUMBER_SHIFT (12) -#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK (0x3 << 12) -#define NV_SOR_TEST_HEAD_NUMBER_NONE (0 << 12) -#define NV_SOR_TEST_HEAD_NUMBER_HEAD0 (1 << 12) -#define NV_SOR_TEST_HEAD_NUMBER_HEAD1 (2 << 12) -#define NV_SOR_TEST_ATTACHED_SHIFT (10) -#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK (0x1 << 10) -#define NV_SOR_TEST_ATTACHED_FALSE (0 << 10) -#define NV_SOR_TEST_ATTACHED_TRUE (1 << 10) -#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT (8) -#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (0x3 << 8) -#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8) -#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8) -#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8) -#define NV_SOR_TEST_INVD_SHIFT (6) -#define NV_SOR_TEST_INVD_DISABLE (0 << 6) -#define NV_SOR_TEST_INVD_ENABLE (1 << 6) -#define NV_SOR_TEST_TEST_ENABLE_SHIFT (1) -#define NV_SOR_TEST_TEST_ENABLE_DISABLE (0 << 1) -#define NV_SOR_TEST_TEST_ENABLE_ENABLE (1 << 1) -#define NV_SOR_PLL0 (0x17) -#define NV_SOR_PLL0_ICHPMP_SHFIT (24) -#define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK (0xf << 24) -#define NV_SOR_PLL0_VCOCAP_SHIFT (8) -#define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK (0xf << 8) -#define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT (6) -#define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK (0x3 << 6) -#define NV_SOR_PLL0_PLLREG_LEVEL_V25 (0 << 6) -#define NV_SOR_PLL0_PLLREG_LEVEL_V15 (1 << 6) -#define NV_SOR_PLL0_PLLREG_LEVEL_V35 (2 << 6) -#define NV_SOR_PLL0_PLLREG_LEVEL_V45 (3 << 6) -#define NV_SOR_PLL0_PULLDOWN_SHIFT (5) -#define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK (0x1 << 5) -#define NV_SOR_PLL0_PULLDOWN_DISABLE (0 << 5) -#define NV_SOR_PLL0_PULLDOWN_ENABLE (1 << 5) -#define NV_SOR_PLL0_RESISTORSEL_SHIFT (4) -#define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK (0x1 << 4) -#define NV_SOR_PLL0_RESISTORSEL_INT (0 << 4) -#define NV_SOR_PLL0_RESISTORSEL_EXT (1 << 4) -#define NV_SOR_PLL0_VCOPD_SHIFT (2) -#define NV_SOR_PLL0_VCOPD_MASK (1 << 2) -#define NV_SOR_PLL0_VCOPD_RESCIND (0 << 2) -#define NV_SOR_PLL0_VCOPD_ASSERT (1 << 2) -#define NV_SOR_PLL0_PWR_SHIFT (0) -#define NV_SOR_PLL0_PWR_MASK (1) -#define NV_SOR_PLL0_PWR_ON (0) -#define NV_SOR_PLL0_PWR_OFF (1) -#define NV_SOR_PLL1_TMDS_TERM_SHIFT (8) -#define NV_SOR_PLL1_TMDS_TERM_DISABLE (0 << 8) -#define NV_SOR_PLL1_TMDS_TERM_ENABLE (1 << 8) -#define NV_SOR_PLL1 (0x18) -#define NV_SOR_PLL1_TERM_COMPOUT_SHIFT (15) -#define NV_SOR_PLL1_TERM_COMPOUT_LOW (0 << 15) -#define NV_SOR_PLL1_TERM_COMPOUT_HIGH (1 << 15) -#define NV_SOR_PLL2 (0x19) -#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT (0) -#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0) -#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW (1 << 0) -#define NV_SOR_PLL2_AUX1_SHIFT (17) -#define NV_SOR_PLL2_AUX1_SEQ_MASK (1 << 17) -#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17) -#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17) -#define NV_SOR_PLL2_AUX2_SHIFT (18) -#define NV_SOR_PLL2_AUX2_MASK (1 << 18) -#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18) -#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN (1 << 18) -#define NV_SOR_PLL2_AUX6_SHIFT (22) -#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22) -#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22) -#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22) -#define NV_SOR_PLL2_AUX7_SHIFT (23) -#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23) -#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23) -#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23) -#define NV_SOR_PLL2_AUX8_SHIFT (24) -#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24) -#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24) -#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24) -#define NV_SOR_PLL2_AUX9_SHIFT (25) -#define NV_SOR_PLL2_AUX9_LVDSEN_ALLOW (0 << 25) -#define NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25) -#define NV_SOR_PLL3 (0x1a) -#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT (13) -#define NV_SOR_PLL3_PLLVDD_MODE_MASK (1 << 13) -#define NV_SOR_PLL3_PLLVDD_MODE_V1_8 (0 << 13) -#define NV_SOR_PLL3_PLLVDD_MODE_V3_3 (1 << 13) -#define NV_SOR_CSTM (0x1b) -#define NV_SOR_CSTM_ROTDAT_SHIFT (28) -#define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK (0x7 << 28) -#define NV_SOR_CSTM_ROTCLK_SHIFT (24) -#define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK (0xf << 24) -#define NV_SOR_CSTM_LVDS_EN_SHIFT (16) -#define NV_SOR_CSTM_LVDS_EN_DISABLE (0 << 16) -#define NV_SOR_CSTM_LVDS_EN_ENABLE (1 << 16) -#define NV_SOR_CSTM_LINKACTB_SHIFT (15) -#define NV_SOR_CSTM_LINKACTB_DISABLE (0 << 15) -#define NV_SOR_CSTM_LINKACTB_ENABLE (1 << 15) -#define NV_SOR_CSTM_LINKACTA_SHIFT (14) -#define NV_SOR_CSTM_LINKACTA_DISABLE (0 << 14) -#define NV_SOR_CSTM_LINKACTA_ENABLE (1 << 14) -#define NV_SOR_LVDS (0x1c) -#define NV_SOR_LVDS_ROTDAT_SHIFT (28) -#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK (0x7 << 28) -#define NV_SOR_LVDS_ROTDAT_RST (0 << 28) -#define NV_SOR_LVDS_ROTCLK_SHIFT (24) -#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK (0xf << 24) -#define NV_SOR_LVDS_ROTCLK_RST (0 << 24) -#define NV_SOR_LVDS_PLLDIV_SHIFT (21) -#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK (0x1 << 21) -#define NV_SOR_LVDS_PLLDIV_BY_7 (0 << 21) -#define NV_SOR_LVDS_BALANCED_SHIFT (19) -#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK (0x1 << 19) -#define NV_SOR_LVDS_BALANCED_DISABLE (0 << 19) -#define NV_SOR_LVDS_BALANCED_ENABLE (1 << 19) -#define NV_SOR_LVDS_NEW_MODE_SHIFT (18) -#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK (0x1 << 18) -#define NV_SOR_LVDS_NEW_MODE_DISABLE (0 << 18) -#define NV_SOR_LVDS_NEW_MODE_ENABLE (1 << 18) -#define NV_SOR_LVDS_DUP_SYNC_SHIFT (17) -#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK (0x1 << 17) -#define NV_SOR_LVDS_DUP_SYNC_DISABLE (0 << 17) -#define NV_SOR_LVDS_DUP_SYNC_ENABLE (1 << 17) -#define NV_SOR_LVDS_LVDS_EN_SHIFT (16) -#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK (0x1 << 16) -#define NV_SOR_LVDS_LVDS_EN_ENABLE (1 << 16) -#define NV_SOR_LVDS_LINKACTB_SHIFT (15) -#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK (0x1 << 15) -#define NV_SOR_LVDS_LINKACTB_DISABLE (0 << 15) -#define NV_SOR_LVDS_LINKACTB_ENABLE (1 << 15) -#define NV_SOR_LVDS_LINKACTA_SHIFT (14) -#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK (0x1 << 14) -#define NV_SOR_LVDS_LINKACTA_ENABLE (1 << 14) -#define NV_SOR_LVDS_MODE_SHIFT (12) -#define NV_SOR_LVDS_MODE_DEFAULT_MASK (0x3 << 12) -#define NV_SOR_LVDS_MODE_LVDS (0 << 12) -#define NV_SOR_LVDS_UPPER_SHIFT (11) -#define NV_SOR_LVDS_UPPER_DEFAULT_MASK (0x1 << 11) -#define NV_SOR_LVDS_UPPER_FALSE (0 << 11) -#define NV_SOR_LVDS_UPPER_TRUE (1 << 11) -#define NV_SOR_LVDS_PD_TXCB_SHIFT (9) -#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK (0x1 << 9) -#define NV_SOR_LVDS_PD_TXCB_ENABLE (0 << 9) -#define NV_SOR_LVDS_PD_TXCB_DISABLE (1 << 9) -#define NV_SOR_LVDS_PD_TXCA_SHIFT (8) -#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK (0x1 << 8) -#define NV_SOR_LVDS_PD_TXCA_ENABLE (0 << 8) -#define NV_SOR_LVDS_PD_TXDB_3_SHIFT (7) -#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK (0x1 << 7) -#define NV_SOR_LVDS_PD_TXDB_3_ENABLE (0 << 7) -#define NV_SOR_LVDS_PD_TXDB_3_DISABLE (1 << 7) -#define NV_SOR_LVDS_PD_TXDB_2_SHIFT (6) -#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK (0x1 << 6) -#define NV_SOR_LVDS_PD_TXDB_2_ENABLE (0 << 6) -#define NV_SOR_LVDS_PD_TXDB_2_DISABLE (1 << 6) -#define NV_SOR_LVDS_PD_TXDB_1_SHIFT (5) -#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK (0x1 << 5) -#define NV_SOR_LVDS_PD_TXDB_1_ENABLE (0 << 5) -#define NV_SOR_LVDS_PD_TXDB_1_DISABLE (1 << 5) -#define NV_SOR_LVDS_PD_TXDB_0_SHIFT (4) -#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK (0x1 << 4) -#define NV_SOR_LVDS_PD_TXDB_0_ENABLE (0 << 4) -#define NV_SOR_LVDS_PD_TXDB_0_DISABLE (1 << 4) -#define NV_SOR_LVDS_PD_TXDA_3_SHIFT (3) -#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK (0x1 << 3) -#define NV_SOR_LVDS_PD_TXDA_3_ENABLE (0 << 3) -#define NV_SOR_LVDS_PD_TXDA_3_DISABLE (1 << 3) -#define NV_SOR_LVDS_PD_TXDA_2_SHIFT (2) -#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK (0x1 << 2) -#define NV_SOR_LVDS_PD_TXDA_2_ENABLE (0 << 2) -#define NV_SOR_LVDS_PD_TXDA_1_SHIFT (1) -#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK (0x1 << 1) -#define NV_SOR_LVDS_PD_TXDA_1_ENABLE (0 << 1) -#define NV_SOR_LVDS_PD_TXDA_0_SHIFT (0) -#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK (0x1) -#define NV_SOR_LVDS_PD_TXDA_0_ENABLE (0) -#define NV_SOR_CRCA (0x1d) -#define NV_SOR_CRCA_VALID_FALSE (0) -#define NV_SOR_CRCA_VALID_TRUE (1) -#define NV_SOR_CRCA_VALID_RST (1) -#define NV_SOR_CRCB (0x1e) -#define NV_SOR_CRCB_CRC_DEFAULT_MASK (0xffffffff) -#define NV_SOR_SEQ_CTL (0x20) -#define NV_SOR_SEQ_CTL_SWITCH_SHIFT (30) -#define NV_SOR_SEQ_CTL_SWITCH_MASK (0x1 << 30) -#define NV_SOR_SEQ_CTL_SWITCH_WAIT (0 << 30) -#define NV_SOR_SEQ_CTL_SWITCH_FORCE (1 << 30) -#define NV_SOR_SEQ_CTL_STATUS_SHIFT (28) -#define NV_SOR_SEQ_CTL_STATUS_MASK (0x1 << 28) -#define NV_SOR_SEQ_CTL_STATUS_STOPPED (0 << 28) -#define NV_SOR_SEQ_CTL_STATUS_RUNNING (1 << 28) -#define NV_SOR_SEQ_CTL_PC_SHIFT (16) -#define NV_SOR_SEQ_CTL_PC_MASK (0xf << 16) -#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT (12) -#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK (0xf << 12) -#define NV_SOR_SEQ_CTL_PD_PC_SHIFT (8) -#define NV_SOR_SEQ_CTL_PD_PC_MASK (0xf << 8) -#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT (4) -#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK (0xf << 4) -#define NV_SOR_SEQ_CTL_PU_PC_SHIFT (0) -#define NV_SOR_SEQ_CTL_PU_PC_MASK (0xf) -#define NV_SOR_LANE_SEQ_CTL (0x21) -#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT (31) -#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK (1 << 31) -#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31) -#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31) -#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31) -#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT (28) -#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28) -#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28) -#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT (20) -#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) -#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) -#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT (16) -#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16) -#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16) -#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT (12) -#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12) -#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT (9) -#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9) -#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9) -#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT (8) -#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8) -#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8) -#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT (7) -#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7) -#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7) -#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT (6) -#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6) -#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6) -#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT (5) -#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5) -#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5) -#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT (4) -#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4) -#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4) -#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT (3) -#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3) -#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3) -#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT (2) -#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2) -#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2) -#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT (1) -#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1) -#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1) -#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT (0) -#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP (0) -#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN (1) -#define NV_SOR_SEQ_INST(i) (0x22 + i) -#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT (31) -#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31) -#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31) -#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT (30) -#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30) -#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30) -#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT (29) -#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29) -#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29) -#define NV_SOR_SEQ_INST_BLANK_V_SHIFT (28) -#define NV_SOR_SEQ_INST_BLANK_V_NORMAL (0 << 28) -#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE (1 << 28) -#define NV_SOR_SEQ_INST_BLANK_H_SHIFT (27) -#define NV_SOR_SEQ_INST_BLANK_H_NORMAL (0 << 27) -#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE (1 << 27) -#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT (26) -#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL (0 << 26) -#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE (1 << 26) -#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT (25) -#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL (0 << 25) -#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK (1 << 25) -#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT (24) -#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24) -#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24) -#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT (23) -#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23) -#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23) -#define NV_SOR_SEQ_INST_PIN_B_SHIFT (22) -#define NV_SOR_SEQ_INST_PIN_B_LOW (0 << 22) -#define NV_SOR_SEQ_INST_PIN_B_HIGH (1 << 22) -#define NV_SOR_SEQ_INST_PIN_A_SHIFT (21) -#define NV_SOR_SEQ_INST_PIN_A_LOW (0 << 21) -#define NV_SOR_SEQ_INST_PIN_A_HIGH (1 << 21) -#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT (19) -#define NV_SOR_SEQ_INST_SEQUENCE_UP (0 << 19) -#define NV_SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19) -#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT (18) -#define NV_SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18) -#define NV_SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18) -#define NV_SOR_SEQ_INST_PDPORT_SHIFT (17) -#define NV_SOR_SEQ_INST_PDPORT_NO (0 << 17) -#define NV_SOR_SEQ_INST_PDPORT_YES (1 << 17) -#define NV_SOR_SEQ_INST_PDPLL_SHIFT (16) -#define NV_SOR_SEQ_INST_PDPLL_NO (0 << 16) -#define NV_SOR_SEQ_INST_PDPLL_YES (1 << 16) -#define NV_SOR_SEQ_INST_HALT_SHIFT (15) -#define NV_SOR_SEQ_INST_HALT_FALSE (0 << 15) -#define NV_SOR_SEQ_INST_HALT_TRUE (1 << 15) -#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT (12) -#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK (0x3 << 12) -#define NV_SOR_SEQ_INST_WAIT_UNITS_US (0 << 12) -#define NV_SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12) -#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12) -#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT (0) -#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK (0x3ff) -#define NV_SOR_PWM_DIV (0x32) -#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK (0xffffff) -#define NV_SOR_PWM_CTL (0x33) -#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT (31) -#define NV_SOR_PWM_CTL_SETTING_NEW_DONE (0 << 31) -#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING (1 << 31) -#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER (1 << 31) -#define NV_SOR_PWM_CTL_CLKSEL_SHIFT (30) -#define NV_SOR_PWM_CTL_CLKSEL_PCLK (0 << 30) -#define NV_SOR_PWM_CTL_CLKSEL_XTAL (1 << 30) -#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT (0) -#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK (0xffffff) -#define NV_SOR_MSCHECK (0x49) -#define NV_SOR_MSCHECK_CTL_SHIFT (31) -#define NV_SOR_MSCHECK_CTL_CLEAR (0 << 31) -#define NV_SOR_MSCHECK_CTL_RUN (1 << 31) -#define NV_SOR_XBAR_CTRL (0x4a) -#define NV_SOR_DP_LINKCTL(i) (0x4c + (i)) -#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT (31) -#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31) -#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31) -#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT (28) -#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28) -#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28) -#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT (16) -#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK (0x1f << 16) -#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO (0 << 16) -#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE (1 << 16) -#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO (3 << 16) -#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR (15 << 16) -#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT (14) -#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14) -#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14) -#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT (10) -#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE (0 << 10) -#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE (1 << 10) -#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT (2) -#define NV_SOR_DP_LINKCTL_TUSIZE_MASK (0x7f << 2) -#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT (0) -#define NV_SOR_DP_LINKCTL_ENABLE_NO (0) -#define NV_SOR_DP_LINKCTL_ENABLE_YES (1) -#define NV_SOR_DC(i) (0x4e + (i)) -#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT (24) -#define NV_SOR_DC_LANE3_DP_LANE3_MASK (0xff << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24) -#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24) -#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT (16) -#define NV_SOR_DC_LANE2_DP_LANE0_MASK (0xff << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16) -#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16) -#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT (8) -#define NV_SOR_DC_LANE1_DP_LANE1_MASK (0xff << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8) -#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8) -#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT (0) -#define NV_SOR_DC_LANE0_DP_LANE2_MASK (0xff) -#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0 (17) -#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 (21) -#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0 (26) -#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0 (34) -#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1 (26) -#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1 (32) -#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1 (39) -#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2 (34) -#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43) -#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51) -#define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i)) -#define NV_SOR_PR(i) (0x52 + (i)) -#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24) -#define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24) -#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24) -#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT (16) -#define NV_SOR_PR_LANE2_DP_LANE0_MASK (0xff << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16) -#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16) -#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT (8) -#define NV_SOR_PR_LANE1_DP_LANE1_MASK (0xff >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8) -#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8) -#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT (0) -#define NV_SOR_PR_LANE0_DP_LANE2_MASK (0xff) -#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0 (0) -#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0 (0) -#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0 (0) -#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0 (0) -#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1 (4) -#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1 (6) -#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1 (17) -#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2 (8) -#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2 (13) -#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3 (17) -#define NV_SOR_LANE4_PREEMPHASIS(i) (0x54 + (i)) -#define NV_SOR_POSTCURSOR(i) (0x56 + (i)) -#define NV_SOR_DP_CONFIG(i) (0x58 + (i)) -#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT (31) -#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31) -#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31) -#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT (28) -#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28) -#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28) -#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT (26) -#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26) -#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26) -#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT (24) -#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24) -#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24) -#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT (16) -#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16) -#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT (8) -#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8) -#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT (0) -#define NV_SOR_DP_CONFIG_WATERMARK_MASK (0x3f) -#define NV_SOR_DP_MN(i) (0x5a + i) -#define NV_SOR_DP_MN_M_MOD_SHIFT (30) -#define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK (0x3 << 30) -#define NV_SOR_DP_MN_M_MOD_NONE (0 << 30) -#define NV_SOR_DP_MN_M_MOD_INC (1 << 30) -#define NV_SOR_DP_MN_M_MOD_DEC (2 << 30) -#define NV_SOR_DP_MN_M_DELTA_SHIFT (24) -#define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24) -#define NV_SOR_DP_MN_N_VAL_SHIFT (0) -#define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK (0xffffff) -#define NV_SOR_DP_PADCTL(i) (0x5c + (i)) -#define NV_SOR_DP_PADCTL_SPARE_SHIFT (25) -#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25) -#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT (24) -#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE (0 << 24) -#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE (1 << 24) -#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT (23) -#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23) -#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23) -#define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22) -#define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22) -#define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) -#define NV_SOR_DP_PADCTL_TX_PU_MASK (1 << 22) -#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20) -#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20) -#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16) -#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16) -#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE (0 << 16) -#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX (1 << 16) -#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16) -#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16) -#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT (8) -#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8) -#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT (7) -#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) -#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7) -#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT (6) -#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6) -#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6) -#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT (5) -#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5) -#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5) -#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT (4) -#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4) -#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4) -#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT (3) -#define NV_SOR_DP_PADCTL_PD_TXD_3_YES (0 << 3) -#define NV_SOR_DP_PADCTL_PD_TXD_3_NO (1 << 3) -#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT (2) -#define NV_SOR_DP_PADCTL_PD_TXD_0_YES (0 << 2) -#define NV_SOR_DP_PADCTL_PD_TXD_0_NO (1 << 2) -#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT (1) -#define NV_SOR_DP_PADCTL_PD_TXD_1_YES (0 << 1) -#define NV_SOR_DP_PADCTL_PD_TXD_1_NO (1 << 1) -#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT (0) -#define NV_SOR_DP_PADCTL_PD_TXD_2_YES (0) -#define NV_SOR_DP_PADCTL_PD_TXD_2_NO (1) -#define NV_SOR_DP_DEBUG(i) (0x5e + i) -#define NV_SOR_DP_SPARE(i) (0x60 + (i)) -#define NV_SOR_DP_SPARE_REG_SHIFT (3) -#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3) -#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT (2) -#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (0x1 << 2) -#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2) -#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2) -#define NV_SOR_DP_SPARE_PANEL_SHIFT (1) -#define NV_SOR_DP_SPARE_PANEL_EXTERNAL (0 << 1) -#define NV_SOR_DP_SPARE_PANEL_INTERNAL (1 << 1) -#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT (0) -#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO (0) -#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES (1) -#define NV_SOR_DP_AUDIO_CTRL (0x62) -#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS (0x63) -#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x1ffff) -#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT (0) -#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS (0x64) -#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1ffff) -#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT (0) -#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER (0x65) -#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i)) -#define NV_SOR_DP_TPG (0x6d) -#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT (30) -#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30) -#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30) -#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT (28) -#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28) -#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28) -#define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT (24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_D102 (4 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM (7 << 24) -#define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24) -#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT (22) -#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22) -#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22) -#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT (20) -#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (0x3 << 20) -#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20) -#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20) -#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20) -#define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT (16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_D102 (4 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM (7 << 16) -#define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16) -#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT (14) -#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14) -#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14) -#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT (12) -#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (0x3 << 12) -#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12) -#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12) -#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12) -#define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT (8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_D102 (4 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM (7 << 8) -#define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8) -#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT (6) -#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6) -#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6) -#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT (4) -#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (0x3 << 4) -#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4) -#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4) -#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4) -#define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT (0) -#define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK (0xf) -#define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN (0) -#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 (1) -#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 (2) -#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 (3) -#define NV_SOR_DP_TPG_LANE0_PATTERN_D102 (4) -#define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE (5) -#define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7 (6) -#define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM (7) -#define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE (8) - -enum { - training_pattern_disabled = 0, - training_pattern_1 = 1, - training_pattern_2 = 2, - training_pattern_3 = 3, - training_pattern_none = 0xff -}; - -enum tegra_dc_sor_protocol { - SOR_DP, - SOR_LVDS, -}; - -#define SOR_LINK_SPEED_G1_62 6 -#define SOR_LINK_SPEED_G2_7 10 -#define SOR_LINK_SPEED_G5_4 20 -#define SOR_LINK_SPEED_LVDS 7 - -/* todo: combine this and the intel_dp struct into one struct. */ -struct tegra_dc_dp_link_config { - int is_valid; - - /* Supported configuration */ - u8 max_link_bw; - u8 max_lane_count; - int downspread; - int support_enhanced_framing; - u32 bits_per_pixel; - int alt_scramber_reset_cap; /* true for eDP */ - int only_enhanced_framing; /* enhanced_frame_en ignored */ - - /* Actual configuration */ - u8 link_bw; - u8 lane_count; - int enhanced_framing; - int scramble_ena; - - u32 activepolarity; - u32 active_count; - u32 tu_size; - u32 active_frac; - u32 watermark; - - s32 hblank_sym; - s32 vblank_sym; - - /* Training data */ - u32 drive_current; - u32 preemphasis; - u32 postcursor; - u8 aux_rd_interval; - u8 tps3_supported; -}; - -/* TODO: just pull these up into one struct? Need to see how this impacts - * having two channels. - */ -struct tegra_dc_sor_data { - struct tegra_dc *dc; - void *base; - void *pmc_base; - u8 portnum; /* 0 or 1 */ - struct tegra_dc_dp_link_config *link_cfg; - int power_is_up; -}; - -#define TEGRA_SOR_TIMEOUT_MS 1000 -#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000 -#define TEGRA_DC_POLL_TIMEOUT_MS 50 - -#define CHECK_RET(x) \ - do { \ - ret = (x); \ - if (ret != 0) \ - return ret; \ - } while (0) - -void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor); -int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd); -void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, - u8 training_pattern, const struct tegra_dc_dp_link_config *link_cfg); -void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw); -void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count); -void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, - int power_up); -void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int); -void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, - u8 *lane_count); -void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); -void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, - const struct tegra_dc_dp_link_config *link_cfg); -void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); -void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor); -void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); -void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); -void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, - u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); -void tegra_dc_detach(struct tegra_dc_sor_data *sor); -#endif /*__TEGRA132_SOR_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/spi.h b/src/soc/nvidia/tegra132/include/soc/spi.h deleted file mode 100644 index d286b32839..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/spi.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __NVIDIA_TEGRA132_SPI_H__ -#define __NVIDIA_TEGRA132_SPI_H__ - -#include <soc/dma.h> -#include <spi-generic.h> -#include <stddef.h> - -struct tegra_spi_regs { - u32 command1; /* 0x000: SPI_COMMAND1 */ - u32 command2; /* 0x004: SPI_COMMAND2 */ - u32 timing1; /* 0x008: SPI_CS_TIM1 */ - u32 timing2; /* 0x00c: SPI_CS_TIM2 */ - u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ - u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ - u32 tx_data; /* 0x018: SPI_TX_DATA */ - u32 rx_data; /* 0x01c: SPI_RX_DATA */ - u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ - u32 dma_blk; /* 0x024: SPI_DMA_BLK */ - u32 rsvd[56]; /* 0x028-0x107: reserved */ - u32 tx_fifo; /* 0x108: SPI_FIFO1 */ - u32 rsvd2[31]; /* 0x10c-0x187 reserved */ - u32 rx_fifo; /* 0x188: SPI_FIFO2 */ - u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ -} __attribute__((packed)); -check_member(tegra_spi_regs, spare_ctl, 0x18c); - -enum spi_xfer_mode { - XFER_MODE_NONE = 0, - XFER_MODE_PIO, - XFER_MODE_DMA, -}; - -struct tegra_spi_channel { - struct tegra_spi_regs *regs; - - /* static configuration */ - struct spi_slave slave; - unsigned int req_sel; - - int dual_mode; /* for x2 transfers with bit interleaving */ - - /* context (used internally) */ - u8 *in_buf, *out_buf; - struct apb_dma_channel *dma_out, *dma_in; - enum spi_xfer_mode xfer_mode; -}; - -struct tegra_spi_channel *tegra_spi_init(unsigned int bus); - -#endif /* __NVIDIA_TEGRA132_SPI_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/sysctr.h b/src/soc/nvidia/tegra132/include/soc/sysctr.h deleted file mode 100644 index a054ca4af7..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/sysctr.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_SYSCTR_H__ -#define __SOC_NVIDIA_TEGRA132_SYSCTR_H__ - -#include <stdint.h> - -enum { - SYSCTR_CNTCR_EN = 1 << 0, - SYSCTR_CNTCR_HDBG = 1 << 1, - SYSCTR_CNTCR_FCREQ = 1 << 8 -}; - -struct sysctr_regs { - uint32_t cntcr; - uint32_t cntsr; - uint32_t cntcv0; - uint32_t cntcv1; - uint8_t _rsv0[0x10]; - uint32_t cntfid0; - uint32_t cntfid1; - uint8_t _rsv1[0xfa8]; - uint32_t counterid4; - uint32_t counterid5; - uint32_t counterid6; - uint32_t counterid7; - uint32_t counterid0; - uint32_t counterid1; - uint32_t counterid2; - uint32_t counterid3; - uint32_t counterid8; - uint32_t counterid9; - uint32_t counterid10; - uint32_t counterid11; -}; -check_member(sysctr_regs, counterid11, 0xffc); - -#endif /* __SOC_NVIDIA_TEGRA132_SYSCTR_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h deleted file mode 100644 index 2e0facb7da..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/tegra_dsi.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __TEGRA_DSI_H__ -#define __TEGRA_DSI_H__ - -#define DSI_INCR_SYNCPT 0x00 -#define DSI_INCR_SYNCPT_CONTROL 0x01 -#define DSI_INCR_SYNCPT_ERROR 0x02 -#define DSI_CTXSW 0x08 -#define DSI_RD_DATA 0x09 -#define DSI_WR_DATA 0x0a -#define DSI_POWER_CONTROL 0x0b -#define DSI_POWER_CONTROL_ENABLE (1 << 0) -#define DSI_INT_ENABLE 0x0c -#define DSI_INT_STATUS 0x0d -#define DSI_INT_MASK 0x0e -#define DSI_HOST_CONTROL 0x0f -#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) -#define DSI_HOST_CONTROL_CRC_RESET (1 << 20) -#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) -#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) -#define DSI_HOST_CONTROL_RAW (1 << 6) -#define DSI_HOST_CONTROL_HS (1 << 5) -#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) -#define DSI_HOST_CONTROL_IMM_BTA (1 << 3) -#define DSI_HOST_CONTROL_PKT_BTA (1 << 2) -#define DSI_HOST_CONTROL_CS (1 << 1) -#define DSI_HOST_CONTROL_ECC (1 << 0) -#define DSI_CONTROL 0x10 -#define DSI_CONTROL_HS_CLK_CTRL (1 << 20) -#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) -#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) -#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) -#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) -#define DSI_CONTROL_DCS_ENABLE (1 << 3) -#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) -#define DSI_CONTROL_VIDEO_ENABLE (1 << 1) -#define DSI_CONTROL_HOST_ENABLE (1 << 0) -#define DSI_SOL_DELAY 0x11 -#define DSI_MAX_THRESHOLD 0x12 -#define DSI_TRIGGER 0x13 -#define DSI_TRIGGER_HOST (1 << 1) -#define DSI_TRIGGER_VIDEO (1 << 0) -#define DSI_TX_CRC 0x14 -#define DSI_STATUS 0x15 -#define DSI_STATUS_IDLE (1 << 10) -#define DSI_STATUS_UNDERFLOW (1 << 9) -#define DSI_STATUS_OVERFLOW (1 << 8) -#define DSI_INIT_SEQ_CONTROL 0x1a -#define DSI_INIT_SEQ_DATA_0 0x1b -#define DSI_INIT_SEQ_DATA_1 0x1c -#define DSI_INIT_SEQ_DATA_2 0x1d -#define DSI_INIT_SEQ_DATA_3 0x1e -#define DSI_INIT_SEQ_DATA_4 0x1f -#define DSI_INIT_SEQ_DATA_5 0x20 -#define DSI_INIT_SEQ_DATA_6 0x21 -#define DSI_INIT_SEQ_DATA_7 0x22 -#define DSI_PKT_SEQ_0_LO 0x23 -#define DSI_PKT_SEQ_0_HI 0x24 -#define DSI_PKT_SEQ_1_LO 0x25 -#define DSI_PKT_SEQ_1_HI 0x26 -#define DSI_PKT_SEQ_2_LO 0x27 -#define DSI_PKT_SEQ_2_HI 0x28 -#define DSI_PKT_SEQ_3_LO 0x29 -#define DSI_PKT_SEQ_3_HI 0x2a -#define DSI_PKT_SEQ_4_LO 0x2b -#define DSI_PKT_SEQ_4_HI 0x2c -#define DSI_PKT_SEQ_5_LO 0x2d -#define DSI_PKT_SEQ_5_HI 0x2e -#define DSI_DCS_CMDS 0x33 -#define DSI_PKT_LEN_0_1 0x34 -#define DSI_PKT_LEN_2_3 0x35 -#define DSI_PKT_LEN_4_5 0x36 -#define DSI_PKT_LEN_6_7 0x37 -#define DSI_PHY_TIMING_0 0x3c -#define DSI_PHY_TIMING_1 0x3d -#define DSI_PHY_TIMING_2 0x3e -#define DSI_BTA_TIMING 0x3f - -#define DSI_TIMING_FIELD(value, period, hwinc) \ - ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff) - -#define DSI_TIMEOUT_0 0x44 -#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) -#define DSI_TIMEOUT_1 0x45 -#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) -#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) -#define DSI_TO_TALLY 0x46 -#define DSI_TALLY_TA(x) (((x) & 0xff) << 16) -#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) -#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) -#define DSI_PAD_CONTROL_0 0x4b -#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) -#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) -#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) -#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) -#define DSI_PAD_CONTROL_CD 0x4c -#define DSI_PAD_CD_STATUS 0x4d -#define DSI_VIDEO_MODE_CONTROL 0x4e -#define DSI_PAD_CONTROL_1 0x4f -#define DSI_PAD_CONTROL_2 0x50 -#define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0) -#define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4) -#define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8) -#define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12) -#define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16) -#define DSI_PAD_CONTROL_3 0x51 -#define DSI_PAD_CONTROL_4 0x52 -#define DSI_GANGED_MODE_CONTROL 0x53 -#define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0) -#define DSI_GANGED_MODE_START 0x54 -#define DSI_GANGED_MODE_SIZE 0x55 -#define DSI_RAW_DATA_BYTE_COUNT 0x56 -#define DSI_ULTRA_LOW_POWER_CONTROL 0x57 -#define DSI_INIT_SEQ_DATA_8 0x58 -#define DSI_INIT_SEQ_DATA_9 0x59 -#define DSI_INIT_SEQ_DATA_10 0x5a -#define DSI_INIT_SEQ_DATA_11 0x5b -#define DSI_INIT_SEQ_DATA_12 0x5c -#define DSI_INIT_SEQ_DATA_13 0x5d -#define DSI_INIT_SEQ_DATA_14 0x5e -#define DSI_INIT_SEQ_DATA_15 0x5f - -#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) -#define PKT_LEN0(len) (((len) & 0x07) << 0) -#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) -#define PKT_LEN1(len) (((len) & 0x07) << 10) -#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) -#define PKT_LEN2(len) (((len) & 0x07) << 20) - -#define PKT_LP (1 << 30) -#define NUM_PKT_SEQ 12 - -#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20) -#define DSIB_MODE_SHIFT 1 -#define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT) -#define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT) - -/* - * pixel format as used in the DSI_CONTROL_FORMAT field - */ -enum tegra_dsi_format { - TEGRA_DSI_FORMAT_16P, - TEGRA_DSI_FORMAT_18NP, - TEGRA_DSI_FORMAT_18P, - TEGRA_DSI_FORMAT_24P, -}; - -enum dsi_dev { - DSI_A = 0, - DSI_B, - NUM_DSI, -}; - -struct panel_jdi; -struct tegra_mipi_device; -struct mipi_dsi_host; -struct mipi_dsi_msg; - -#define MAX_DSI_VIDEO_FIFO_DEPTH 96 -#define MAX_DSI_HOST_FIFO_DEPTH 64 - -struct tegra_dsi { - struct panel_jdi *panel; - //struct tegra_output output; - void *regs; - u8 channel; - unsigned long clk_rate; - - unsigned long flags; - enum mipi_dsi_pixel_format format; - unsigned int lanes; - - struct tegra_mipi_device *mipi; - struct mipi_dsi_host host; - bool enabled; - - unsigned int video_fifo_depth; - unsigned int host_fifo_depth; - - /* for ganged-mode support */ - unsigned int ganged_lanes; - struct tegra_dsi *slave; - int ganged_mode; - - struct tegra_dsi *master; -}; - -static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi, - unsigned long reg) -{ - return read32(dsi->regs + (reg << 2)); -} - -static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value, - unsigned long reg) -{ - write32(dsi->regs + (reg << 2), value); -} - -#endif /* __TEGRA_DSI_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h deleted file mode 100644 index 265c869ed0..0000000000 --- a/src/soc/nvidia/tegra132/include/soc/verstage.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ -#define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ - -#include <vendorcode/google/chromeos/chromeos.h> - -#endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/jdi_25x18_display/panel-jdi-lpm102a188a.c b/src/soc/nvidia/tegra132/jdi_25x18_display/panel-jdi-lpm102a188a.c deleted file mode 100644 index 60f660ff9d..0000000000 --- a/src/soc/nvidia/tegra132/jdi_25x18_display/panel-jdi-lpm102a188a.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <lib.h> -#include <stdlib.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <device/device.h> -#include <soc/nvidia/tegra/types.h> -#include "../chip.h" -#include <soc/display.h> -#include <soc/mipi_dsi.h> -#include <soc/tegra_dsi.h> -#include "panel-jdi-lpm102a188a.h" - -struct panel_jdi jdi_data[NUM_DSI]; - -int panel_jdi_prepare(struct panel_jdi *jdi) -{ - int ret; - u8 data; - - if (jdi->enabled) - return 0; - - ret = mipi_dsi_dcs_set_column_address(jdi->dsi, 0, - jdi->mode->xres / 2 - 1); // 2560/2 - if (ret < 0) - printk(BIOS_ERR, "failed to set column address: %d\n", ret); - - ret = mipi_dsi_dcs_set_column_address(jdi->dsi->slave, 0, - jdi->mode->xres / 2 - 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set column address: %d\n", ret); - - ret = mipi_dsi_dcs_set_page_address(jdi->dsi, 0, - jdi->mode->yres - 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set page address: %d\n", ret); - - ret = mipi_dsi_dcs_set_page_address(jdi->dsi->slave, 0, - jdi->mode->yres - 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set page address: %d\n", ret); - - ret = mipi_dsi_dcs_exit_sleep_mode(jdi->dsi); - if (ret < 0) - printk(BIOS_ERR, "failed to exit sleep mode: %d\n", ret); - - ret = mipi_dsi_dcs_exit_sleep_mode(jdi->dsi->slave); - if (ret < 0) - printk(BIOS_ERR, "failed to exit sleep mode: %d\n", ret); - - ret = mipi_dsi_dcs_set_tear_on(jdi->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret < 0) - printk(BIOS_ERR, "failed to set tear on: %d\n", ret); - - ret = mipi_dsi_dcs_set_tear_on(jdi->dsi->slave, - MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret < 0) - printk(BIOS_ERR, "failed to set tear on: %d\n", ret); - - ret = mipi_dsi_dcs_set_address_mode(jdi->dsi, false, false, false, - false, false, false, false, false); - if (ret < 0) - printk(BIOS_ERR, "failed to set address mode: %d\n", ret); - - ret = mipi_dsi_dcs_set_address_mode(jdi->dsi->slave, false, false, - false, false, false, false, false, false); - if (ret < 0) - printk(BIOS_ERR, "failed to set address mode: %d\n", ret); - - ret = mipi_dsi_dcs_set_pixel_format(jdi->dsi, 0x77); - if (ret < 0) - printk(BIOS_ERR, "failed to set pixel format: %d\n", ret); - - ret = mipi_dsi_dcs_set_pixel_format(jdi->dsi->slave, 0x77); - if (ret < 0) - printk(BIOS_ERR, "failed to set pixel format: %d\n", ret); - - data = 0xFF; - ret = mipi_dsi_dcs_write(jdi->dsi, 0x51, &data, 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set 0x51: %d\n", ret); - - data = 0xFF; - ret = mipi_dsi_dcs_write(jdi->dsi->slave, 0x51, &data, 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set 0x51: %d\n", ret); - - data = 0x24; - ret = mipi_dsi_dcs_write(jdi->dsi, 0x53, &data, 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set 0x53: %d\n", ret); - - data = 0x24; - ret = mipi_dsi_dcs_write(jdi->dsi->slave, 0x53, &data, 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set 0x53: %d\n", ret); - - data = 0x00; - ret = mipi_dsi_dcs_write(jdi->dsi, 0x55, &data, 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set 0x55: %d\n", ret); - - data = 0x00; - ret = mipi_dsi_dcs_write(jdi->dsi->slave, 0x55, &data, 1); - if (ret < 0) - printk(BIOS_ERR, "failed to set 0x55: %d\n", ret); - - ret = mipi_dsi_dcs_set_display_on(jdi->dsi); - if (ret < 0) - printk(BIOS_ERR, "failed to set display on: %d\n", ret); - - ret = mipi_dsi_dcs_set_display_on(jdi->dsi->slave); - if (ret < 0) - printk(BIOS_ERR, "failed to set display on: %d\n", ret); - - jdi->enabled = true; - - return 0; -} - -static int panel_jdi_enslave(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave) -{ - int ret; - - ret = mipi_dsi_attach(master); - if (ret < 0) - return ret; - - return ret; -} - -static int panel_jdi_liberate(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave) -{ - int ret; - - ret = mipi_dsi_detach(master); - if (ret < 0) - return ret; - - return 0; -} - -static const struct mipi_dsi_master_ops panel_jdi_master_ops = { - .enslave = panel_jdi_enslave, - .liberate = panel_jdi_liberate, -}; - -struct panel_jdi *panel_jdi_dsi_probe(struct mipi_dsi_device *dsi) -{ - static int index = 0; - struct panel_jdi *jdi; - int ret; - - if (index >= NUM_DSI) - return (void *)-EPTR; - - jdi = &jdi_data[index++]; - - jdi->dsi = dsi; - - dsi->lanes = 4; - dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = 0; - - if (dsi->master) { - ret = mipi_dsi_attach(dsi); - if (ret < 0) { - printk(BIOS_ERR, "mipi_dsi_attach() failed: %d\n", ret); - return (void *)-EPTR; - } - - ret = mipi_dsi_enslave(dsi->master, dsi); - if (ret < 0) { - printk(BIOS_ERR, "mipi_dsi_enslave() failed: %d\n", - ret); - return (void *)-EPTR; - } - - return jdi; - } - - dsi->ops = &panel_jdi_master_ops; - - jdi->enabled = 0; - jdi->width_mm = 211; - jdi->height_mm = 148; - - return jdi; -} diff --git a/src/soc/nvidia/tegra132/jdi_25x18_display/panel-jdi-lpm102a188a.h b/src/soc/nvidia/tegra132/jdi_25x18_display/panel-jdi-lpm102a188a.h deleted file mode 100644 index f137cdd28c..0000000000 --- a/src/soc/nvidia/tegra132/jdi_25x18_display/panel-jdi-lpm102a188a.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _PANEL_JDI_LPM102A188A_H_ -#define _PANEL_JDI_LPM102A188A_H_ - -#define LP8557_MAX_BRIGHTNESS 0xFFF; - -#define LP8557_COMMAND 0x00 -#define LP8557_COMMAND_ON (1 << 0) - -#define LP8557_BRIGHTNESS_LOW 0x03 -#define LP8557_BRIGHTNESS_LOW_MASK(x) (((x) & 0xF) << 4) - -#define LP8557_BRIGHTNESS_HIGH 0x04 -#define LP8557_BRIGHTNESS_HIGH_MASK(x) (((x) & 0xFF0) >> 4) - -enum lp8557_config_brightness_mode { - LP8557_CONFIG_BRTMODE_PWM = 0x0, - LP8557_CONFIG_BRTMODE_REG, - LP8557_CONFIG_BRTMODE_PWM_REG_SHAPE_PWM, - LP8557_CONFIG_BRTMODE_PWM_REG_SHAPE_BRIGHTNESS, - LP8557_CONFIG_BRTMODE_MAX, -}; -#define LP8557_CONFIG 0x10 -#define LP8557_CONFIG_BRTMODE(x) (((x) & 0x3) << 0) -#define LP8557_CONFIG_AUTO_DETECT_LED (1 << 2) -#define LP8557_CONFIG_PWM_STANDBY (1 << 7) - -enum lp8557_current { - LP8557_CURRENT_5_MA = 0x0, - LP8557_CURRENT_10_MA, - LP8557_CURRENT_13_MA, - LP8557_CURRENT_15_MA, - LP8557_CURRENT_18_MA, - LP8557_CURRENT_20_MA, - LP8557_CURRENT_23_MA, - LP8557_CURRENT_25_MA, - LP8557_CURRENT_MAX, -}; -#define LP8557_CURRENT 0x11 -#define LP8557_CURRENT_MAXCURR(x) (((x) & 0x7) << 0) -#define LP8557_CURRENT_ISET (1 << 7) - -enum lp8557_pgen_frequency { - LP8557_PGEN_FREQ_4_9_KHZ = 0x0, - LP8557_PGEN_FREQ_9_8_KHZ, - LP8557_PGEN_FREQ_14_6_KHZ, - LP8557_PGEN_FREQ_19_5_KHZ, - LP8557_PGEN_FREQ_24_4_KHZ, - LP8557_PGEN_FREQ_29_3_KHZ, - LP8557_PGEN_FREQ_34_2_KHZ, - LP8557_PGEN_FREQ_39_1_KHZ, - LP8557_PGEN_FREQ_MAX, -}; -#define LP8557_PGEN 0x12 -#define LP8557_PGEN_FREQ(x) (((x) & 0x7) << 0) -#define LP8557_PGEN_MAGIC (5 << 3) -#define LP8557_PGEN_FSET (1 << 7) - -enum lp8557_boost_freq { - LP8557_BOOST_FREQ_500_KHZ = 0x0, - LP8557_BOOST_FREQ_1_MHZ, - LP8557_BOOST_FREQ_MAX, -}; -enum lp8557_boost_bcomp { - LP8557_BOOST_BCOMP_OPTION_0 = 0x0, - LP8557_BOOST_BCOMP_OPTION_1, - LP8557_BOOST_BCOMP_MAX, -}; -#define LP8557_BOOST 0x13 -#define LP8557_BOOST_FREQ(x) (((x) & 0x1) << 0) -#define LP8557_BOOST_BCOMP(x) (((x) & 0x1) << 1) -#define LP8557_BOOST_BCSET (1 << 6) -#define LP8557_BOOST_BFSET (1 << 7) - -#define LP8557_LED_ENABLE 0x14 -#define LP8557_LED_ENABLE_SINKS(x) (((x) & 0x3F) << 0) -#define LP8557_LED_ENABLE_MAGIC (2 << 6) - -enum lp8557_step_ramp { - LP8557_STEP_RAMP_0_MS = 0x0, - LP8557_STEP_RAMP_50_MS, - LP8557_STEP_RAMP_100_MS, - LP8557_STEP_RAMP_200_MS, - LP8557_STEP_RAMP_MAX, -}; -enum lp8557_step_smoothing { - LP8557_STEP_SMOOTHING_NONE = 0x0, - LP8557_STEP_SMOOTHING_LIGHT, - LP8557_STEP_SMOOTHING_MEDIUM, - LP8557_STEP_SMOOTHING_HEAVY, - LP8557_STEP_SMOOTHING_MAX, -}; -#define LP8557_STEP 0x15 -#define LP8557_STEP_RAMP(x) (((x) & 0x3) << 0) -#define LP8557_STEP_SMOOTHING(x) (((x) & 0x3) << 6) - -struct mipi_dsi_device; -struct soc_nvidia_tegra132_config; - -struct panel_jdi { - struct mipi_dsi_device *dsi; - const struct soc_nvidia_tegra132_config *mode; - - /* Physical size */ - unsigned int width_mm; - unsigned int height_mm; - - int enabled; -}; - -struct panel_jdi *panel_jdi_dsi_probe(struct mipi_dsi_device *dsi); -int panel_jdi_prepare(struct panel_jdi *jdi); - -#endif diff --git a/src/soc/nvidia/tegra132/lp0/Makefile b/src/soc/nvidia/tegra132/lp0/Makefile deleted file mode 100644 index 34e9396e3f..0000000000 --- a/src/soc/nvidia/tegra132/lp0/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -################################################################################ -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -################################################################################ - -CC = $(GCC_PREFIX)gcc -NM = $(GCC_PREFIX)nm -OBJCOPY = $(GCC_PREFIX)objcopy - -OPENSSL = openssl -DD = dd -CP = cp -MV = mv -RM = rm - -SIGKEY = 00000000000000000000000000000000 - -.PHONY: all -all: tegra_lp0_resume.fw - -tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c - $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ - -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ - -o $@ $(filter %.c,$+) - -tegra_lp0_resume.fw: tegra_lp0_resume.elf - @# Get rid of any files we're about to create. - $(RM) -f $@.nosig $@.sig $@.tosig - @# Convert the ELF image into a binary image. - $(OBJCOPY) -O binary $< $@.nosig - @# Extract the part of the binary which needs to be signed. - $(DD) bs=1 skip=544 if=$@.nosig of=$@.tosig - @# Calculate a signature for that part. - $(OPENSSL) dgst -mac cmac -macopt cipher:aes-128-cbc \ - -macopt hexkey:$(SIGKEY) -md5 -binary \ - $@.tosig > $@.sig - @# Inject the signature into the binary image's header. - $(DD) conv=notrunc bs=1 seek=272 count=16 if=$@.sig of=$@.nosig - @# Copy the signed binary to the target file name. - $(MV) $@.nosig $@ - -clean: - $(RM) -f tegra_lp0_resume.fw tegra_lp0_resume.fw.sig - $(RM) -f tegra_lp0_resume.fw.tosig tegra_lp0_resume.elf diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c deleted file mode 100644 index bd4e5c4218..0000000000 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ /dev/null @@ -1,687 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * Copyright 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include <stdint.h> - -/* Function unit addresses. */ -enum { - UP_TAG_BASE = 0X60000000, - TIMER_BASE = 0X60005000, - CLK_RST_BASE = 0X60006000, - FLOW_CTLR_BASE = 0X60007000, - TEGRA_EVP_BASE = 0x6000f000, - APB_MISC_BASE = 0x70000000, - PMC_CTLR_BASE = 0X7000e400, - MC_CTLR_BASE = 0X70019000, -}; - - - -/* UP tag registers. */ -static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); -enum { - UP_TAG_AVP = 0xaaaaaaaa -}; - - -/* APB Misc JTAG Configuration Register */ -static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24); -enum { - PP_CONFIG_CTL_JTAG = 0x1 << 6 -}; - - -/* Timer registers. */ -static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); - - - -/* Clock and reset controller registers. */ -static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); -enum { - SWR_TRIG_SYS_RST = 0x1 << 2 -}; - -static uint32_t *clk_rst_cclk_burst_policy_ptr = (void *)(CLK_RST_BASE + 0x20); -enum { - CCLK_PLLP_BURST_POLICY = 0x20004444 -}; - -static uint32_t *clk_rst_super_cclk_div_ptr = (void *)(CLK_RST_BASE + 0x24); -enum { - SUPER_CDIV_ENB = 0x1 << 31 -}; - -static uint32_t *clk_rst_osc_ctrl_ptr = (void *)(CLK_RST_BASE + 0x50); -enum { - OSC_XOE = 0x1 << 0, - OSC_XOFS_SHIFT = 4, - OSC_XOFS_MASK = 0x3f << OSC_XOFS_SHIFT, - OSC_FREQ_SHIFT = 28, - OSC_FREQ_MASK = 0xf << OSC_FREQ_SHIFT -}; -enum { - OSC_FREQ_13 = 0, - OSC_FREQ_16P8 = 1, - OSC_FREQ_19P2 = 4, - OSC_FREQ_38P4 = 5, - OSC_FREQ_12 = 8, - OSC_FREQ_48 = 9, - OSC_FREQ_26 = 12 -}; - -static uint32_t *clk_rst_pllu_base_ptr = (void *)(CLK_RST_BASE + 0xc0); -enum { - PLLU_DIVM_SHIFT = 0, - PLLU_DIVN_SHIFT = 8, - PLLU_OVERRIDE = 0x1 << 24, - PLLU_ENABLE = 0x1 << 30, - PLLU_BYPASS = 0x1 << 31 -}; - -static uint32_t *clk_rst_pllu_misc_ptr = (void *)(CLK_RST_BASE + 0xcc); -enum { - PLLU_LFCON_SHIFT = 4, - PLLU_CPCON_SHIFT = 8, - PLLU_LOCK_ENABLE = 22 -}; - -static uint32_t *clk_rst_pllx_base_ptr = (void *)(CLK_RST_BASE + 0xe0); -enum { - PLLX_ENABLE = 0x1 << 30 -}; - -static uint32_t *clk_rst_rst_dev_u_clr_ptr = (void *)(CLK_RST_BASE + 0x314); -enum { - SWR_CSITE_RST = 0x1 << 9 -}; - -static uint32_t *clk_rst_clk_enb_l_set_ptr = (void *)(CLK_RST_BASE + 0x320); -enum { - CLK_ENB_CPU = 0x1 << 0 -}; - -static uint32_t *clk_rst_clk_out_enb_u_set_ptr = - (void *)(CLK_RST_BASE + 0x330); -enum { - CLK_ENB_CSITE = 0x1 << 9 -}; - -static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr = - (void *)(CLK_RST_BASE + 0x388); -enum { - CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0, - CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT -}; - -static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); -enum { - CLK_ENB_CPUG = 0x1 << 0, - CLK_ENB_CPULP = 0x1 << 1, -}; - -static uint32_t *clk_rst_rst_cpulp_cmplx_set_ptr = - (void *)(CLK_RST_BASE + 0x450); -enum { - SET_CXRESET0 = 0x1 << 20, - SET_CXRESET1 = 0x1 << 21 -}; -static uint32_t *clk_rst_rst_cpug_cmplx_clr_ptr = - (void *)(CLK_RST_BASE + 0x454); -enum { - CLR_CPURESET0 = 0x1 << 0, - CLR_CPURESET1 = 0x1 << 1, - CLR_CPURESET2 = 0x1 << 2, - CLR_CPURESET3 = 0x1 << 3, - CLR_DBGRESET0 = 0x1 << 12, - CLR_DBGRESET1 = 0x1 << 13, - CLR_DBGRESET2 = 0x1 << 14, - CLR_DBGRESET3 = 0x1 << 15, - CLR_CORERESET0 = 0x1 << 16, - CLR_CORERESET1 = 0x1 << 17, - CLR_CORERESET2 = 0x1 << 18, - CLR_CORERESET3 = 0x1 << 19, - CLR_CXRESET0 = 0x1 << 20, - CLR_CXRESET1 = 0x1 << 21, - CLR_CXRESET2 = 0x1 << 22, - CLR_CXRESET3 = 0x1 << 23, - CLR_L2RESET = 0x1 << 24, - CLR_NONCPURESET = 0x1 << 29, - CLR_PRESETDBG = 0x1 << 30 -}; - - -/* Reset vector. */ - -static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); - - - -/* Flow controller registers. */ -static uint32_t *flow_ctlr_halt_cop_events_ptr = - (void *)(FLOW_CTLR_BASE + 0x4); -enum { - EVENT_MSEC = 0x1 << 24, - EVENT_JTAG = 0x1 << 28, - FLOW_MODE_SHIFT = 29, - FLOW_MODE_STOP = 2 << FLOW_MODE_SHIFT, -}; - -static uint32_t *flow_ctlr_cluster_control_ptr = - (void *)(FLOW_CTLR_BASE + 0x2c); -enum { - FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0 -}; - -static uint32_t *flow_ctlr_ram_repair_ptr = - (void *)(FLOW_CTLR_BASE + 0x40); -static uint32_t *flow_ctlr_ram_repair_cluster1_ptr = - (void *)(FLOW_CTLR_BASE + 0x58); -enum { - RAM_REPAIR_REQ = 0x1 << 0, - RAM_REPAIR_STS = 0x1 << 1, -}; - - -/* Power management controller registers. */ -enum { - PARTID_CRAIL = 0, - PARTID_CE0 = 14, - PARTID_C0NC = 15, -}; - -static uint32_t *pmc_ctlr_clamp_status_ptr = (void *)(PMC_CTLR_BASE + 0x2c); - -static uint32_t *pmc_ctlr_pwrgate_toggle_ptr = (void *)(PMC_CTLR_BASE + 0x30); -enum { - PWRGATE_TOGGLE_START = 0x1 << 8 -}; - -static uint32_t *pmc_ctlr_pwrgate_status_ptr = (void *)(PMC_CTLR_BASE + 0x38); - -static uint32_t *pmc_ctlr_cpupwrgood_timer_ptr = - (void *)(PMC_CTLR_BASE + 0xc8); - -static uint32_t *pmc_odmdata_ptr = (void *)(PMC_CTLR_BASE + 0xa0); - -static uint32_t *pmc_ctlr_scratch41_ptr = (void *)(PMC_CTLR_BASE + 0x140); -static uint32_t *pmc_ctlr_secure_scratch34_ptr = (void *)(PMC_CTLR_BASE + 0x368); -static uint32_t *pmc_ctlr_secure_scratch35_ptr = (void *)(PMC_CTLR_BASE + 0x36c); - -static uint32_t *pmc_ctlr_osc_edpd_over_ptr = (void *)(PMC_CTLR_BASE + 0x1a4); -enum { - PMC_XOFS_SHIFT = 1, - PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT -}; - - - -/* Memory controller registers. */ -static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); - -static uint32_t *mc_video_protect_reg_ctrl_ptr = - (void *)(MC_CTLR_BASE + 0x650); -enum { - VIDEO_PROTECT_WRITE_ACCESS_DISABLE = 0x1 << 0, - VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 -}; - - -/* Utility functions. */ - -static inline void __attribute__((always_inline)) - __attribute__((noreturn)) halt(void) -{ - for (;;); -} - -static inline uint32_t read32(const void *addr) -{ - return *(volatile uint32_t *)addr; -} - -static inline void write32(void *addr, uint32_t val) -{ - *(volatile uint32_t *)addr = val; -} - -static inline void setbits32(uint32_t bits, void *addr) -{ - write32(addr, read32(addr) | bits); -} - -static inline void clrbits32(uint32_t bits, void *addr) -{ - write32(addr, read32(addr) & ~bits); -} - -static void __attribute__((noreturn)) reset(void) -{ - write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); - halt(); -} - -static void udelay(unsigned usecs) -{ - uint32_t start = read32(timer_us_ptr); - while (read32(timer_us_ptr) - start < usecs) - ; -} - -/* UART related defines */ -static uint32_t *uart_clk_out_enb_regs[4] = { - (uint32_t *)0x60006010, - (uint32_t *)0x60006010, - (uint32_t *)0x60006014, - (uint32_t *)0x60006018 -}; - -static uint32_t *uart_rst_devices_regs[4] = { - (uint32_t *)0x60006004, - (uint32_t *)0x60006004, - (uint32_t *)0x60006008, - (uint32_t *)0x6000600c -}; - -static uint32_t uart_enable_mask[4] = { - 1 << 6, - 1 << 7, - 1 << 23, - 1 << 1 -}; - -static uint32_t *uart_clk_source_regs[4] = { - (uint32_t *)0x60006178, - (uint32_t *)0x6000617c, - (uint32_t *)0x600061a0, - (uint32_t *)0x600061c0, -}; - -static uint32_t *uart_base_regs[4] = { - (uint32_t *)0x70006000, - (uint32_t *)0x70006040, - (uint32_t *)0x70006200, - (uint32_t *)0x70006300, -}; -enum { - UART_THR_DLAB = 0x0, - UART_IER_DLAB = 0x1, - UART_IIR_FCR = 0x2, - UART_LCR = 0x3 -}; -enum { - UART_RATE_115200 = (408000000/115200/16), /* based on 408000000 PLLP */ - FCR_TX_CLR = 0x4, /* bit 2 of FCR : clear TX FIFO */ - FCR_RX_CLR = 0x2, /* bit 1 of FCR : clear RX FIFO */ - FCR_EN_FIFO = 0x1, /* bit 0 of FCR : enable TX & RX FIFO */ - LCR_DLAB = 0x80, /* bit 7 of LCR : Divisor Latch Access Bit */ - LCR_WD_SIZE_8 = 0x3, /* bit 1:0 of LCR : word length of 8 */ -}; - -static void enable_uart(void) -{ - uint32_t *uart_clk_enb_reg; - uint32_t *uart_rst_reg; - uint32_t *uart_clk_source; - uint32_t uart_port; - uint32_t uart_mask; - uint32_t *uart_base; - - /* - * Read odmdata (stored in pmc->odmdata) to determine debug uart port. - * - * Bits 15-17 of odmdata contains debug uart port. - * 0 : UARTA - * 1 : UARTB - * 2 : UARTC - * 3 : UARTD - */ - uart_port = (read32(pmc_odmdata_ptr) >> 15) & 0x7; - - /* Default to UARTA if uart_port is out of range */ - if (uart_port >= 4) - uart_port = 0; - - uart_clk_enb_reg = uart_clk_out_enb_regs[uart_port]; - uart_rst_reg = uart_rst_devices_regs[uart_port]; - uart_mask = uart_enable_mask[uart_port]; - uart_clk_source = uart_clk_source_regs[uart_port]; - uart_base = uart_base_regs[uart_port]; - - /* Enable UART clock */ - setbits32(uart_mask, uart_clk_enb_reg); - - /* Reset and unreset UART */ - setbits32(uart_mask, uart_rst_reg); - clrbits32(uart_mask, uart_rst_reg); - - /* Program UART clock source: PLLP (408000000) */ - write32(uart_clk_source, 0); - - /* Program 115200n8 to the uart port */ - /* baud-rate of 115200 */ - write32((uart_base + UART_LCR), LCR_DLAB); - write32((uart_base + UART_THR_DLAB), (UART_RATE_115200 & 0xff)); - write32((uart_base + UART_IER_DLAB), (UART_RATE_115200 >> 8)); - /* 8-bit and no parity */ - write32((uart_base + UART_LCR), LCR_WD_SIZE_8); - /* enable and clear RX/TX FIFO */ - write32((uart_base + UART_IIR_FCR), - (FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO)); -} - -/* Accessors. */ - -static uint32_t get_wakeup_vector(void) -{ - return read32(pmc_ctlr_scratch41_ptr); -} - -static unsigned get_osc_freq(void) -{ - return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; -} - - -/* Jtag configuration. */ - -static void enable_jtag(void) -{ - write32(misc_pp_config_ctl_ptr, PP_CONFIG_CTL_JTAG); -} - -/* Clock configuration. */ - -static void config_oscillator(void) -{ - // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy - // to OSC_CTRL.XOFS and set XOE. - uint32_t xofs = (read32(pmc_ctlr_osc_edpd_over_ptr) & - PMC_XOFS_MASK) >> PMC_XOFS_SHIFT; - - uint32_t osc_ctrl = read32(clk_rst_osc_ctrl_ptr); - osc_ctrl &= ~OSC_XOFS_MASK; - osc_ctrl |= (xofs << OSC_XOFS_SHIFT); - osc_ctrl |= OSC_XOE; - write32(clk_rst_osc_ctrl_ptr, osc_ctrl); -} - -static void config_pllu(void) -{ - // Figure out what parameters to use for PLLU. - uint32_t divm, divn, cpcon, lfcon; - switch (get_osc_freq()) { - case OSC_FREQ_12: - case OSC_FREQ_48: - divm = 0x0c; - divn = 0x3c0; - cpcon = 0x0c; - lfcon = 0x02; - break; - case OSC_FREQ_16P8: - divm = 0x07; - divn = 0x190; - cpcon = 0x05; - lfcon = 0x02; - break; - case OSC_FREQ_19P2: - case OSC_FREQ_38P4: - divm = 0x04; - divn = 0xc8; - cpcon = 0x03; - lfcon = 0x02; - break; - case OSC_FREQ_26: - divm = 0x1a; - divn = 0x3c0; - cpcon = 0x0c; - lfcon = 0x02; - break; - default: - // Map anything that's not recognized to 13MHz. - divm = 0x0d; - divn = 0x3c0; - cpcon = 0x0c; - lfcon = 0x02; - } - - // Configure PLLU. - uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | - (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - write32(clk_rst_pllu_base_ptr, base); - uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | - (lfcon << PLLU_LFCON_SHIFT); - write32(clk_rst_pllu_misc_ptr, misc); - - // Enable PLLU. - base &= ~PLLU_BYPASS; - base |= PLLU_ENABLE; - write32(clk_rst_pllu_base_ptr, base); - misc |= PLLU_LOCK_ENABLE; - write32(clk_rst_pllu_misc_ptr, misc); -} - -static void enable_cpu_clocks(void) -{ - // Enable the CPU complex clock. - write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); - write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); -} - - - -/* Function unit configuration. */ - -static void config_core_sight(void) -{ - // Enable the CoreSight clock. - write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); - - /* - * De-assert CoreSight reset. - * NOTE: We're leaving the CoreSight clock on the oscillator for - * now. It will be restored to its original clock source - * when the CPU-side restoration code runs. - */ - write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); -} - - -/* Resets. */ - -static void clear_cpu_resets(void) -{ - /* Hold CPU1 in reset */ - setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr); - - write32(clk_rst_rst_cpug_cmplx_clr_ptr, - CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG); - - write32(clk_rst_rst_cpug_cmplx_clr_ptr, - CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); -} - - - -/* RAM repair */ - -void ram_repair(void) -{ - // Request Cluster0 RAM repair. - setbits32(RAM_REPAIR_REQ, flow_ctlr_ram_repair_ptr); - // Poll for Cluster0 RAM repair status. - while (!(read32(flow_ctlr_ram_repair_ptr) & RAM_REPAIR_STS)) - ; - - // Request Cluster1 RAM repair. - setbits32(RAM_REPAIR_REQ, flow_ctlr_ram_repair_cluster1_ptr); - // Poll for Cluster1 RAM repair status. - while (!(read32(flow_ctlr_ram_repair_cluster1_ptr) & RAM_REPAIR_STS)) - ; -} - - -/* Power. */ - -static void power_on_partition(unsigned id) -{ - uint32_t bit = 0x1 << id; - if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { - // Partition is not on. Turn it on. - write32(pmc_ctlr_pwrgate_toggle_ptr, id | PWRGATE_TOGGLE_START); - - // Wait until the partition is powerd on. - while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) - ; - - // Wait until clamp is off. - while (read32(pmc_ctlr_clamp_status_ptr) & bit) - ; - } -} - -static void power_on_main_cpu(void) -{ - /* - * Reprogram PMC_CPUPWRGOOD_TIMER register: - * - * XXX This is a fragile assumption. XXX - * The kernel prepares PMC_CPUPWRGOOD_TIMER based on a 32768Hz clock. - * Note that PMC_CPUPWRGOOD_TIMER is running at pclk. - * - * We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk - * which is at 204Mhz (pclk = sclk = pllp_out2) after BootROM. Multiply - * PMC_CPUPWRGOOD_TIMER by 204M / 32K. - * - * Save the original PMC_CPUPWRGOOD_TIMER register which we need to - * restore after the CPU is powered up. - */ - uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - - write32(pmc_ctlr_cpupwrgood_timer_ptr, - orig_timer * (204000000 / 32768)); - - power_on_partition(PARTID_CRAIL); - power_on_partition(PARTID_C0NC); - power_on_partition(PARTID_CE0); - - // Restore the original PMC_CPUPWRGOOD_TIMER. - write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); -} - - -static void aarch64_trampoline(void) -{ - uint32_t val = 3; /* bit1: to warm reset; bit0: AARCH64*/ - - asm volatile ("mcr p15, 0, %0, c12, c0, 2" : : "r" (val)); - - /* unreachable */ - halt(); -} - - -/* Entry point. */ - -void lp0_resume(void) -{ - // If not on the AVP, reset. - if (read32(up_tag_ptr) != UP_TAG_AVP) - reset(); - - // Enable JTAG - enable_jtag(); - - config_oscillator(); - - // Program SUPER_CCLK_DIVIDER. - write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); - - config_core_sight(); - - enable_uart(); - - config_pllu(); - - /* - * Set the CPU reset vector. - * - * T132 always resets to AARCH32 and SW needs to write RMR_EL3 - * to bootstrap into AARCH64. - */ - write32(pmc_ctlr_secure_scratch34_ptr, get_wakeup_vector()); - write32(pmc_ctlr_secure_scratch35_ptr, 0); - write32(evp_cpu_reset_ptr, (uint32_t)aarch64_trampoline); - - // Select CPU complex clock source. - write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); - - // Disable PLLX since it isn't used as CPU clock source. - clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); - - // Set CAR2PMC_CPU_ACK_WIDTH to 408. - uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); - ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; - ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); - - // Disable VPR. - write32(mc_video_protect_size_mb_ptr, 0); - write32(mc_video_protect_reg_ctrl_ptr, - VIDEO_PROTECT_WRITE_ACCESS_DISABLE); - - enable_cpu_clocks(); - - power_on_main_cpu(); - - // Perform RAM repair after CPU is powered on. - ram_repair(); - - clear_cpu_resets(); - - // Halt the AVP. - while (1) - write32(flow_ctlr_halt_cop_events_ptr, - FLOW_MODE_STOP | EVENT_JTAG); -} - - - -/* Header. */ - -extern uint8_t blob_data; -extern uint8_t blob_data_size; -extern uint8_t blob_total_size; - -struct lp0_header { - uint32_t length_insecure; // Insecure total length. - uint32_t reserved[3]; - uint8_t rsa_modulus[256]; // RSA key modulus. - uint8_t aes_signature[16]; // AES signature. - uint8_t rsa_signature[256]; // RSA-PSS signature. - uint8_t random_aes_block[16]; // Random data, may be zero. - uint32_t length_secure; // Secure total length. - uint32_t destination; // Where to load the blob in iRAM. - uint32_t entry_point; // Entry point for the blob. - uint32_t code_length; // Length of just the data. -} __attribute__((packed)); - -struct lp0_header header __attribute__((section(".header"))) = -{ - .length_insecure = (uintptr_t)&blob_total_size, - .length_secure = (uintptr_t)&blob_total_size, - .destination = (uintptr_t)&blob_data, - .entry_point = (uintptr_t)&lp0_resume, - .code_length = (uintptr_t)&blob_data_size -}; diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.ld b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.ld deleted file mode 100644 index 2b6ff38444..0000000000 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.ld +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) - -PHDRS -{ - to_load PT_LOAD; -} - -ENTRY(lp0_resume) -SECTIONS -{ - . = 0x40020000 - 0x240; - - /* - * The lp0 blob header is built as a static data structure and put - * in the .header section. - */ - .header_start = .; - .header . : { - *(.header); - } : to_load = 0xff - .header_end = .; - - . = 0x40020000; - - /* The actual lp0 blob code. */ - .data_start = .; - .data . : { - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - . = ALIGN(16); - } - .data_end = .; - - /* Some values we need in the header. */ - blob_data = .data_start; - blob_data_size = .data_end - .data_start; - blob_total_size = .data_end - .header_start; - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - } -} diff --git a/src/soc/nvidia/tegra132/mipi-phy.c b/src/soc/nvidia/tegra132/mipi-phy.c deleted file mode 100644 index 001032a591..0000000000 --- a/src/soc/nvidia/tegra132/mipi-phy.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <lib.h> -#include <stdlib.h> - -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <device/device.h> -#include <soc/nvidia/tegra/types.h> -#include <soc/display.h> -#include <soc/mipi_dsi.h> -#include <soc/mipi_display.h> -#include <soc/tegra_dsi.h> -#include <soc/mipi-phy.h> - -int mipi_dphy_set_timing(struct tegra_dsi *dsi) -{ - - u32 freq = (dsi->clk_rate * 2) / 1000000; - - u32 thsdexit = (DSI_PHY_TIMING_DIV(120, (freq))); - u32 thstrial = (((3) + (DSI_PHY_TIMING_DIV((DSI_THSTRAIL_VAL(freq)), - freq)))); - u32 tdatzero = DSI_PHY_TIMING_DIV(((145) + (5 * (DSI_TBIT(freq)))), - (freq)); - u32 thsprepare = DSI_PHY_TIMING_DIV((65 + (5*(DSI_TBIT(freq)))), freq); - u32 tclktrial = (DSI_PHY_TIMING_DIV(80, freq)); - u32 tclkpost = ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq)))), - freq))); - u32 tclkzero = (DSI_PHY_TIMING_DIV(260, freq)); - u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq)) ; - u32 tclkprepare = (DSI_PHY_TIMING_DIV(60, freq)); - u32 tclkpre = 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value - u32 twakeup = 0x7F; //min = 1ms - - u32 ttaget; - u32 ttassure; - u32 ttago; - u32 value; - - if (!ttlpx) { - ttaget = 5; - ttassure = 2; - ttago = 4; - } else { - ttaget = 5 * ttlpx; - ttassure = 2 * ttlpx; - ttago = 4 * ttlpx; - } - - value = (thsdexit << 24) | - (thstrial << 16) | - (tdatzero << 8) | - (thsprepare << 0); - tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); - - value = (tclktrial << 24) | - (tclkpost << 16) | - (tclkzero << 8) | - (ttlpx << 0); - tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); - - value = (tclkprepare << 16) | - (tclkpre << 8) | - (twakeup << 0); - tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); - - value = (ttaget << 16) | - (ttassure << 8) | - (ttago << 0), - tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); - return 0; -} diff --git a/src/soc/nvidia/tegra132/mipi.c b/src/soc/nvidia/tegra132/mipi.c deleted file mode 100644 index 7a402df594..0000000000 --- a/src/soc/nvidia/tegra132/mipi.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <lib.h> -#include <stdlib.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <device/device.h> -#include <soc/nvidia/tegra/types.h> -#include <soc/display.h> -#include <soc/mipi_dsi.h> -#include <soc/tegra_dsi.h> -#include "jdi_25x18_display/panel-jdi-lpm102a188a.h" - -static unsigned long dsi_pads[] = { - 0x060, /* DSIA & DSIB pads */ - 0x180, /* DSIC & DSID pads */ -}; - -static struct tegra_mipi mipi_data = { - .regs = (void *)TEGRA_MIPI_CAL_BASE, -}; - -static inline unsigned long tegra_mipi_readl(struct tegra_mipi *mipi, - unsigned long reg) -{ - return read32(mipi->regs + (reg << 2)); -} - -static inline void tegra_mipi_writel(struct tegra_mipi *mipi, - unsigned long value, unsigned long reg) -{ - write32(mipi->regs + (reg << 2), value); -} - -static const struct calibration_regs tegra124_mipi_calibration_regs[] = { - { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, - { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK }, - { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, - { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK }, - { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK }, - { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIAB_CLK }, - { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIAB_CLK }, -}; -static const struct tegra_mipi_config tegra124_mipi_config = { - .calibrate_clk_lane = 1, - .regs = tegra124_mipi_calibration_regs, - .num_pads = ARRAY_SIZE(tegra124_mipi_calibration_regs), -}; - -struct tegra_mipi_device *tegra_mipi_request(struct tegra_mipi_device *device, - int device_index) -{ - device->mipi = &mipi_data; - device->config = &tegra124_mipi_config; - device->pads = dsi_pads[device_index]; - - return device; -} - -static int tegra_mipi_wait(struct tegra_mipi *mipi) -{ - u32 poll_interval_us = 1000; - u32 timeout_us = 250 * 1000; - unsigned long value; - - do { - value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS); - if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 && - (value & MIPI_CAL_STATUS_DONE) != 0) - return 0; - - if (timeout_us > poll_interval_us) - timeout_us -= poll_interval_us; - else - break; - - udelay(poll_interval_us); - } while (1); - - printk(BIOS_ERR, "%s: ERROR: timeout\n", __func__); - return -ETIMEDOUT; -} - -int tegra_mipi_calibrate(struct tegra_mipi_device *device) -{ - const struct tegra_mipi_config *cfg = device->config; - unsigned long value, clk_value; - unsigned int i; - int err; - - value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0); - value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP; - value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; - tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0); - - tegra_mipi_writel(device->mipi, MIPI_CAL_BIAS_PAD_CFG1_DEFAULT, - MIPI_CAL_BIAS_PAD_CFG1); - - value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); - value &= ~MIPI_CAL_BIAS_PAD_PDVREG; - tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2); - - for (i = 0; i < cfg->num_pads; i++) { - if (device->pads & BIT(i)) { - value = MIPI_CAL_CONFIG_SELECT | - MIPI_CAL_CONFIG_HSPDOS(0) | - MIPI_CAL_CONFIG_HSPUOS(4) | - MIPI_CAL_CONFIG_TERMOS(5); - clk_value = MIPI_CAL_CONFIG_SELECT | - MIPI_CAL_CONFIG_HSCLKPDOSD(0) | - MIPI_CAL_CONFIG_HSCLKPUOSD(4); - } else { - value = 0; - clk_value = 0; - } - - tegra_mipi_writel(device->mipi, value, cfg->regs[i].data); - - if (cfg->calibrate_clk_lane) - tegra_mipi_writel(device->mipi, clk_value, - cfg->regs[i].clk); - } - - value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); - value |= MIPI_CAL_CTRL_START; - tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); - - err = tegra_mipi_wait(device->mipi); - - return err; -} diff --git a/src/soc/nvidia/tegra132/mipi_dsi.c b/src/soc/nvidia/tegra132/mipi_dsi.c deleted file mode 100644 index d273a75419..0000000000 --- a/src/soc/nvidia/tegra132/mipi_dsi.c +++ /dev/null @@ -1,426 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * MIPI DSI Bus - * - * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. - * Andrzej Hajda <a.hajda@samsung.com> - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <lib.h> -#include <stdlib.h> -#include <delay.h> -#include <string.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <device/device.h> -#include <soc/nvidia/tegra/types.h> -#include <soc/display.h> -#include <soc/mipi_dsi.h> -#include <soc/mipi_display.h> -#include <soc/tegra_dsi.h> - -struct mipi_dsi_device mipi_dsi_device_data[NUM_DSI] = { - { - .master = NULL, - .slave = &mipi_dsi_device_data[DSI_B], - }, - { - .master = &mipi_dsi_device_data[DSI_A], - .slave = NULL, - }, -}; - -static struct mipi_dsi_device * -mipi_dsi_device_alloc(struct mipi_dsi_host *host) -{ - static int index = 0; - struct mipi_dsi_device *dsi; - - if (index >= NUM_DSI) - return (void *)-EPTR; - - dsi = &mipi_dsi_device_data[index++]; - dsi->host = host; - return dsi; -} - -static struct mipi_dsi_device * -of_mipi_dsi_device_add(struct mipi_dsi_host *host) -{ - struct mipi_dsi_device *dsi; - u32 reg = 0; - - dsi = mipi_dsi_device_alloc(host); - if (IS_ERR_PTR(dsi)) { - printk(BIOS_ERR, "failed to allocate DSI device\n"); - return dsi; - } - - dsi->channel = reg; - host->dev = (void *)dsi; - - return dsi; -} - -int mipi_dsi_host_register(struct mipi_dsi_host *host) -{ - of_mipi_dsi_device_add(host); - return 0; -} - -/** - * mipi_dsi_attach - attach a DSI device to its DSI host - * @param dsi: DSI peripheral - */ -int mipi_dsi_attach(struct mipi_dsi_device *dsi) -{ - const struct mipi_dsi_host_ops *ops = dsi->host->ops; - - if (!ops || !ops->attach) - return -ENOSYS; - - return ops->attach(dsi->host, dsi); -} - -/** - * mipi_dsi_detach - detach a DSI device from its DSI host - * @param dsi: DSI peripheral - */ -int mipi_dsi_detach(struct mipi_dsi_device *dsi) -{ - const struct mipi_dsi_host_ops *ops = dsi->host->ops; - - if (!ops || !ops->detach) - return -ENOSYS; - - return ops->detach(dsi->host, dsi); -} - -/** - * mipi_dsi_enslave() - use a MIPI DSI peripheral as slave for dual-channel - * operation - * @param master: master DSI peripheral device - * @param slave: slave DSI peripheral device - * - * @return 0 on success or a negative error code on failure. - */ -int mipi_dsi_enslave(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave) -{ - int err = 0; - - slave->master = master; - master->slave = slave; - - if (master->ops && master->ops->enslave) - err = master->ops->enslave(master, slave); - - return err; -} - -/** - * mipi_dsi_liberate() - stop using a MIPI DSI peripheral as slave for dual- - * channel operation - * @param master: master DSI peripheral device - * @param slave: slave DSI peripheral device - * - * @return 0 on success or a negative error code on failure. - */ -int mipi_dsi_liberate(struct mipi_dsi_device *master, - struct mipi_dsi_device *slave) -{ - int err = 0; - - if (master->ops && master->ops->liberate) - err = master->ops->liberate(master, slave); - - master->slave = NULL; - slave->master = NULL; - - return err; -} - -/** - * mipi_dsi_dcs_write() - send DCS write command - * @param dsi: DSI peripheral device - * @param cmd: DCS command - * @param data: buffer containing the command payload - * @param len: command payload length - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * @return The number of bytes successfully transmitted or a negative error code on failure. - */ -ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, - const void *data, size_t len) -{ - struct mipi_dsi_msg msg; - ssize_t err; - size_t size; - - u8 buffer[MAX_DSI_HOST_FIFO_DEPTH + 4]; - u8 *tx = buffer; - - if (len > MAX_DSI_HOST_FIFO_DEPTH) { - printk(BIOS_ERR, "%s: Error: too large payload length: %zu\n", - __func__, len); - - return -EINVAL; - } - - if (len > 0) { - unsigned int offset = 0; - - /* - * DCS long write packets contain the word count in the header - * bytes 1 and 2 and have a payload containing the DCS command - * byte folowed by word count minus one bytes. - * - * DCS short write packets encode the DCS command and up to - * one parameter in header bytes 1 and 2. - */ - if (len > 1) - size = 3 + len; - else - size = 1 + len; - - /* write word count to header for DCS long write packets */ - if (len > 1) { - tx[offset++] = ((1 + len) >> 0) & 0xff; - tx[offset++] = ((1 + len) >> 8) & 0xff; - } - - /* write the DCS command byte followed by the payload */ - tx[offset++] = cmd; - memcpy(tx + offset, data, len); - } else { - tx = &cmd; - size = 1; - } - - memset(&msg, 0, sizeof(msg)); - msg.flags = MIPI_DSI_MSG_USE_LPM; - msg.channel = dsi->channel; - msg.tx_len = size; - msg.tx_buf = tx; - - switch (len) { - case 0: - msg.type = MIPI_DSI_DCS_SHORT_WRITE; - break; - case 1: - msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - default: - msg.type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - - err = dsi->host->ops->transfer(dsi->host, &msg); - - return err; -} - -/** - * mipi_dsi_dcs_exit_sleep_mode() - enable all blocks inside the display - * module - * @param dsi: DSI peripheral device - * - * @return 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi) -{ - ssize_t err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); - if (err < 0) - return err; - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_on() - start displaying the image data on the - * display device - * @param dsi: DSI peripheral device - * - * @return 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi) -{ - ssize_t err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); - if (err < 0) - return err; - - return 0; -} - -/** - * mipi_dsi_dcs_set_column_address() - define the column extent of the frame - * memory accessed by the host processor - * @param dsi: DSI peripheral device - * @param start: first column of frame memory - * @param end: last column of frame memory - * - * @return 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start, - u16 end) -{ - u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; - ssize_t err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, payload, - sizeof(payload)); - if (err < 0) - return err; - - return 0; -} - -/** - * mipi_dsi_dcs_set_page_address() - define the page extent of the frame - * memory accessed by the host processor - * @param dsi: DSI peripheral device - * @param start: first page of frame memory - * @param end: last page of frame memory - * - * @return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, - u16 end) -{ - u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; - ssize_t err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PAGE_ADDRESS, payload, - sizeof(payload)); - if (err < 0) - return err; - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect - * output signal on the TE signal line. - * @param dsi: DSI peripheral device - * @param mode: the Tearing Effect Output Line mode - * - * @return 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, - enum mipi_dsi_dcs_tear_mode mode) -{ - u8 value = mode; - ssize_t err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_ON, &value, - sizeof(value)); - if (err < 0) - return err; - - return 0; -} - -/** - * @brief mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image - * data used by the interface - * @param dsi: DSI peripheral device - * @param format: pixel format - * - * @return 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format) -{ - ssize_t err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PIXEL_FORMAT, &format, - sizeof(format)); - if (err < 0) - return err; - - return 0; -} - -/** - * mipi_dsi_dcs_set_address_mode() - sets the data order for forward transfers - * from the host to the peripheral - * @param dsi: DSI peripheral device - * @param reverse_page_address: reverses the page addressing to bottom->top - * @param reverse_col_address: reverses the column addressing to right->left - * @param reverse_page_col_address: reverses the page/column addressing order - * @param refresh_from_bottom: refresh the display bottom to top - * @param reverse_rgb: send pixel data bgr instead of rgb - * @param latch_right_to_left: latch the incoming display data right to left - * @param flip_horizontal: flip the image horizontally, left to right - * @param flip_vertical: flip the image vertically, top to bottom - * - * @return 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_address_mode(struct mipi_dsi_device *dsi, - bool reverse_page_address, - bool reverse_col_address, - bool reverse_page_col_address, - bool refresh_from_bottom, - bool reverse_rgb, - bool latch_right_to_left, - bool flip_horizontal, - bool flip_vertical) -{ - ssize_t err; - u8 data; - - data = ((flip_vertical ? 1 : 0) << 0) | - ((flip_horizontal ? 1 : 0) << 1) | - ((latch_right_to_left ? 1 : 0) << 2) | - ((reverse_rgb ? 1 : 0) << 3) | - ((refresh_from_bottom ? 1 : 0) << 4) | - ((reverse_page_col_address ? 1 : 0) << 5) | - ((reverse_col_address ? 1 : 0) << 6) | - ((reverse_page_address ? 1 : 0) << 7); - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &data, 1); - if (err < 0) - return err; - - return 0; -} diff --git a/src/soc/nvidia/tegra132/mmu_operations.c b/src/soc/nvidia/tegra132/mmu_operations.c deleted file mode 100644 index 23531bee79..0000000000 --- a/src/soc/nvidia/tegra132/mmu_operations.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/mmu.h> -#include <assert.h> -#include <soc/addressmap.h> -#include <soc/mmu_operations.h> -#include <stdlib.h> -#include <stdint.h> -#include <symbols.h> - -static void tegra132_mmu_config(void) -{ - uint64_t start,end; - const unsigned long devmem = MA_DEV | MA_S | MA_RW; - const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW; - const unsigned long secure_mem = MA_MEM | MA_S | MA_RW; - uintptr_t tz_base_mib; - size_t tz_size_mib; - - memory_in_range_below_4gb(&start,&end); - - /* Device memory below DRAM */ - mmu_config_range((void *)0, start * MiB, devmem); - - /* DRAM */ - mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem); - - memory_in_range_above_4gb(&start,&end); - - mmu_config_range((void *)(start * MiB), (end-start) * MiB, cachedmem); - - /* SRAM */ - mmu_config_range(_sram, _sram_size, cachedmem); - - /* Add TZ carveout. */ - carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); - - mmu_config_range((void *)(tz_base_mib * MiB), - tz_size_mib * MiB, secure_mem); - - /* Ensure page tables are at the base of the trust zone region. */ - assert((uintptr_t)_ttb == tz_base_mib * MiB && - _ttb_size <= tz_size_mib * MiB); -} - -void tegra132_mmu_init(void) -{ - mmu_init(); - tegra132_mmu_config(); - mmu_enable(); -} diff --git a/src/soc/nvidia/tegra132/monotonic_timer.c b/src/soc/nvidia/tegra132/monotonic_timer.c deleted file mode 100644 index e33cce0872..0000000000 --- a/src/soc/nvidia/tegra132/monotonic_timer.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/addressmap.h> -#include <timer.h> - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, read32((void *)TEGRA_TMRUS_BASE)); -} diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c deleted file mode 100644 index 40927d1cc2..0000000000 --- a/src/soc/nvidia/tegra132/padconfig.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/addressmap.h> -#include <soc/padconfig.h> - -static uint32_t * const pinmux_regs = (void *)(uintptr_t)TEGRA_APB_PINMUX_BASE; -static struct gpio_bank * const gpio_regs = (void *)(uintptr_t)TEGRA_GPIO_BASE; - -static inline struct gpio_bank * const get_gpio_bank_regs(int index) -{ - return &gpio_regs[gpio_index_to_bank(index)]; -} - -static inline uint32_t pad_get_pinmux(int index) -{ - return read32(&pinmux_regs[index]); -} - -static inline void pad_set_pinmux(int index, uint32_t reg) -{ - return write32(&pinmux_regs[index], reg); -} - -static inline void pad_set_gpio_out(int gpio_index, int val) -{ - struct gpio_bank * const regs = get_gpio_bank_regs(gpio_index); - int port = gpio_index_to_port(gpio_index); - int bit = gpio_to_bit(gpio_index); - - write32(®s->out_value_mask[port], - (1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit)); - write32(®s->out_enable_mask[port], - (1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit)); -} - -static inline void pad_set_mode(int gpio_index, int sfio_or_gpio) -{ - struct gpio_bank * const regs = get_gpio_bank_regs(gpio_index); - int port = gpio_index_to_port(gpio_index); - int bit = gpio_to_bit(gpio_index); - - write32(®s->config_mask[port], - (1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit)); -} - -static inline void pad_set_gpio_mode(int gpio_index) -{ - pad_set_mode(gpio_index, 1); -} - -static inline void pad_set_sfio_mode(int gpio_index) -{ - pad_set_mode(gpio_index, 0); -} - -static void configure_unused_pad(const struct pad_config * const entry) -{ - uint32_t reg; - - /* - * Tristate the pad and disable input. If power-on-reset state is a - * pullup maintain that. Otherwise enable pulldown. - */ - reg = pad_get_pinmux(entry->pinmux_index); - reg &= ~PINMUX_INPUT_ENABLE; - reg |= PINMUX_TRISTATE; - reg &= ~PINMUX_PULL_MASK; - if (entry->por_pullup) - reg |= PINMUX_PULL_UP; - else - reg |= PINMUX_PULL_DOWN; - pad_set_pinmux(entry->pinmux_index, reg); - - /* - * Set to GPIO mode if GPIO available to bypass collisions of - * controller signals going to more than one pad. - */ - if (entry->pad_has_gpio) - pad_set_gpio_mode(entry->gpio_index); -} - -static void configure_sfio_pad(const struct pad_config * const entry) -{ - pad_set_pinmux(entry->pinmux_index, entry->pinmux_flags); - pad_set_sfio_mode(entry->gpio_index); -} - -static void configure_gpio_pad(const struct pad_config * const entry) -{ - uint32_t reg; - - if (entry->gpio_out0 || entry->gpio_out1) - pad_set_gpio_out(entry->gpio_index, entry->gpio_out1 ? 1 : 0); - - /* Keep the original SFIO selection. */ - reg = pinmux_get_config(entry->pinmux_index); - reg &= PINMUX_FUNC_MASK; - reg |= entry->pinmux_flags; - - pad_set_pinmux(entry->pinmux_index, reg); - pad_set_gpio_mode(entry->gpio_index); -} - -void soc_configure_pads(const struct pad_config * const entries, size_t num) -{ - size_t i; - - for (i = 0; i < num; i++) { - const struct pad_config * const entry = &entries[i]; - - if (entry->unused) { - configure_unused_pad(entry); - } else if (entry->sfio) { - configure_sfio_pad(entry); - } else { - configure_gpio_pad(entry); - } - } -} diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c deleted file mode 100644 index f41dd4bdb1..0000000000 --- a/src/soc/nvidia/tegra132/power.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <assert.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/pmc.h> -#include <soc/power.h> - -static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; - -static int partition_powered(int id) -{ - return read32(&pmc->pwrgate_status) & (0x1 << id); -} - -void power_ungate_partition(uint32_t id) -{ - printk(BIOS_INFO, "Ungating power partition %d.\n", id); - - if (!partition_powered(id)) { - uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); - pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); - pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); - pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - write32(&pmc->pwrgate_toggle, pwrgate_toggle); - - /* Wait for the request to be accepted. */ - while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) - ; - printk(BIOS_DEBUG, "Power gate toggle request accepted.\n"); - - /* Wait for the partition to be powered. */ - while (!partition_powered(id)) - ; - } - - printk(BIOS_INFO, "Ungated power partition %d.\n", id); -} - -uint8_t pmc_rst_status(void) -{ - return read32(&pmc->rst_status) & PMC_RST_STATUS_SOURCE_MASK; -} - -static const char *pmc_rst_status_str[PMC_RST_STATUS_NUM_SOURCES] = { - [PMC_RST_STATUS_SOURCE_POR] = "POR", - [PMC_RST_STATUS_SOURCE_WATCHDOG] = "Watchdog", - [PMC_RST_STATUS_SOURCE_SENSOR] = "Sensor", - [PMC_RST_STATUS_SOURCE_SW_MAIN] = "SW Main", - [PMC_RST_STATUS_SOURCE_LP0] = "LP0", -}; - -void pmc_print_rst_status(void) -{ - uint8_t rst_status = pmc_rst_status(); - assert(rst_status < PMC_RST_STATUS_NUM_SOURCES); - printk(BIOS_INFO, "PMC Reset Status: %s\n", - pmc_rst_status_str[rst_status]); -} diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c deleted file mode 100644 index fec31c4686..0000000000 --- a/src/soc/nvidia/tegra132/ramstage.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/stages.h> -#include <gic.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/mc.h> -#include <soc/mmu_operations.h> - -static void lock_down_vpr(void) -{ - struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; - - write32(®s->video_protect_bom, 0); - write32(®s->video_protect_size_mb, 0); - write32(®s->video_protect_reg_ctrl, 1); -} - -/* Tegra-specific entry point, called from assembly in stage_entry.S */ -void ramstage_entry(void); -void ramstage_entry(void) -{ - /* TODO: Is this still needed? */ - gic_init(); - - /* TODO: Move TrustZone setup to BL31? */ - trustzone_region_init(); - - tegra132_mmu_init(); - - clock_cpu0_config(); - - clock_init_arm_generic_timer(); - - /* Lock down VPR */ - lock_down_vpr(); - - /* Jump to boot state machine in common code. */ - main(); -} diff --git a/src/soc/nvidia/tegra132/reset.c b/src/soc/nvidia/tegra132/reset.c deleted file mode 100644 index 38a97d82cb..0000000000 --- a/src/soc/nvidia/tegra132/reset.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> - -/* - * Promote cpu_reset() to a hard_reset(). A shallower reset can be added, - * if needed, at a later time. - */ -void cpu_reset(void) -{ - hard_reset(); -} diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c deleted file mode 100644 index c5c1392c07..0000000000 --- a/src/soc/nvidia/tegra132/romstage.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/exception.h> -#include <arch/stages.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/cbmem_console.h> -#include <console/console.h> -#include <lib.h> -#include <program_loading.h> -#include <soc/addressmap.h> -#include <soc/ccplex.h> -#include <soc/clock.h> -#include <soc/sdram.h> -#include <soc/sdram_configs.h> -#include <soc/romstage.h> -#include <symbols.h> -#include <timer.h> -#include <timestamp.h> - -void __attribute__((weak)) romstage_mainboard_init(void) -{ - /* Default empty implementation. */ -} - -void romstage(void) -{ - timestamp_add_now(TS_START_ROMSTAGE); - - console_init(); - exception_init(); - - printk(BIOS_INFO, "T132: romstage here\n"); - -#if CONFIG_BOOTROM_SDRAM_INIT - printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", - sdram_get_ram_code()); -#else - sdram_init(get_sdram_config()); - printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); -#endif - - timestamp_add_now(TS_AFTER_INITRAM); - - /* - * Trust Zone needs to be initialized after the DRAM initialization - * because carveout registers are programmed during DRAM init. - * cbmem_initialize() is dependent on the Trust Zone region - * initalization because CBMEM lives right below the Trust Zone which - * needs to be properly identified. - */ - trustzone_region_init(); - - /* - * When romstage is running it's always on the reboot path -- never a - * resume path where cbmem recovery is required. Therefore, always - * initialize the cbmem area to be empty. - */ - cbmem_initialize_empty(); - - ccplex_cpu_prepare(); - printk(BIOS_INFO, "T132 romstage: CPU prepare done\n"); - - ccplex_load_mts(); - printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); - - romstage_mainboard_init(); - - run_ramstage(); -} - -void platform_prog_run(struct prog *prog) -{ - /* We'll switch to a new stack, so validate our old one here. */ - checkstack(_estack, 0); - - ccplex_cpu_start(prog_entry(prog)); - - clock_halt_avp(); -} diff --git a/src/soc/nvidia/tegra132/romstage_asm.S b/src/soc/nvidia/tegra132/romstage_asm.S deleted file mode 100644 index 9bceadb6fc..0000000000 --- a/src/soc/nvidia/tegra132/romstage_asm.S +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> -#include "stack.S" - - .section ".text", "ax", %progbits - -ENTRY(main) - stack_init stack_top=_estack stack_bottom=_stack seed=0 func=romstage -ENDPROC(main) diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c deleted file mode 100644 index 330c96fdfd..0000000000 --- a/src/soc/nvidia/tegra132/sdram.c +++ /dev/null @@ -1,660 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/emc.h> -#include <soc/mc.h> -#include <soc/pmc.h> -#include <soc/sdram.h> -#include <stdlib.h> - -static void sdram_patch(uintptr_t addr, uint32_t value) -{ - if (addr) - write32((uint32_t *)addr, value); -} - -static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) -{ - clrsetbits_le32(addr, mask, (value & mask)); -} - -/* PMC must be configured before clock-enable and de-reset of MC/EMC. */ -static void sdram_configure_pmc(const struct sdram_params *param, - struct tegra_pmc_regs *regs) -{ - /* VDDP Select */ - write32(®s->vddp_sel, param->PmcVddpSel); - udelay(param->PmcVddpSelWait); - - /* Set DDR pad voltage */ - writebits(param->PmcDdrPwr, ®s->ddr_pwr, PMC_DDR_PWR_VAL_MASK); - - /* Set package and DPD pad control */ - writebits(param->PmcDdrCfg, ®s->ddr_cfg, - (PMC_DDR_CFG_PKG_MASK | PMC_DDR_CFG_IF_MASK | - PMC_DDR_CFG_XM0_RESET_TRI_MASK | - PMC_DDR_CFG_XM0_RESET_DPDIO_MASK)); - - /* Turn on MEM IO Power */ - writebits(param->PmcNoIoPower, ®s->no_iopower, - (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); - - write32(®s->reg_short, param->PmcRegShort); -} - -static void sdram_start_clocks(const struct sdram_params *param) -{ - u32 is_same_freq = (param->McEmemArbMisc0 & - MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK) ? 1 : 0; - - clock_sdram(param->PllMInputDivider, param->PllMFeedbackDivider, - param->PllMSelectDiv2, param->PllMSetupControl, - param->PllMPDLshiftPh45, param->PllMPDLshiftPh90, - param->PllMPDLshiftPh135, param->PllMKVCO, - param->PllMKCP, param->PllMStableTime, - param->EmcClockSource, is_same_freq); -} - -static void sdram_deassert_clock_enable_signal(const struct sdram_params *param, - struct tegra_pmc_regs *regs) -{ - clrbits_le32(®s->por_dpd_ctrl, - PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); - udelay(param->PmcPorDpdCtrlWait); -} - -static void sdram_deassert_sel_dpd(const struct sdram_params *param, - struct tegra_pmc_regs *regs) -{ - clrbits_le32(®s->por_dpd_ctrl, - (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | - PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); - /* - * Note NVIDIA recommended to always do 10us delay here and ignore - * BCT.PmcPorDpdCtrlWait. - * */ - udelay(10); -} - -static void sdram_set_swizzle(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - write32(®s->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg); - write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); - write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); - write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); - write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); - write32(®s->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg); - write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); - write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); - write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); - write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); -} - -static void sdram_set_pad_controls(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - /* Program the pad controls */ - write32(®s->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl); - write32(®s->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2); - write32(®s->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3); - write32(®s->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4); - write32(®s->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5); - - write32(®s->xm2dqspadctrl, param->EmcXm2DqsPadCtrl); - write32(®s->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2); - write32(®s->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3); - write32(®s->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4); - write32(®s->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5); - write32(®s->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6); - - write32(®s->xm2dqpadctrl, param->EmcXm2DqPadCtrl); - write32(®s->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2); - write32(®s->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3); - - write32(®s->xm2clkpadctrl, param->EmcXm2ClkPadCtrl); - write32(®s->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2); - - write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); - - write32(®s->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl); - write32(®s->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2); - write32(®s->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3); - - write32(®s->ctt_term_ctrl, param->EmcCttTermCtrl); -} - -static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) -{ - write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); -} - -static void sdram_init_mc(const struct sdram_params *param, - struct tegra_mc_regs *regs) -{ - /* Initialize MC VPR settings */ - write32(®s->display_snap_ring, param->McDisplaySnapRing); - write32(®s->video_protect_bom, param->McVideoProtectBom); - write32(®s->video_protect_bom_adr_hi, - param->McVideoProtectBomAdrHi); - write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); - write32(®s->video_protect_vpr_override, - param->McVideoProtectVprOverride); - write32(®s->video_protect_vpr_override1, - param->McVideoProtectVprOverride1); - write32(®s->video_protect_gpu_override_0, - param->McVideoProtectGpuOverride0); - write32(®s->video_protect_gpu_override_1, - param->McVideoProtectGpuOverride1); - - /* Program SDRAM geometry paarameters */ - write32(®s->emem_adr_cfg, param->McEmemAdrCfg); - write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); - write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); - - /* Program bank swizzling */ - write32(®s->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0); - write32(®s->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1); - write32(®s->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2); - write32(®s->emem_bank_swizzle_cfg3, - param->McEmemAdrCfgBankSwizzle3); - - /* Program external memory aperature (base and size) */ - write32(®s->emem_cfg, param->McEmemCfg); - - /* Program SEC carveout (base and size) */ - write32(®s->sec_carveout_bom, param->McSecCarveoutBom); - write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); - write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); - - /* Program MTS carveout (base and size) */ - write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); - write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); - write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); - - /* Program the memory arbiter */ - write32(®s->emem_arb_cfg, param->McEmemArbCfg); - write32(®s->emem_arb_outstanding_req, - param->McEmemArbOutstandingReq); - write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); - write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); - write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); - write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); - write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); - write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); - write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); - write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); - write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); - write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); - write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); - write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); - write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); - write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); - write32(®s->emem_arb_misc0, param->McEmemArbMisc0); - write32(®s->emem_arb_misc1, param->McEmemArbMisc1); - write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); - write32(®s->emem_arb_override, param->McEmemArbOverride); - write32(®s->emem_arb_override_1, param->McEmemArbOverride1); - write32(®s->emem_arb_rsv, param->McEmemArbRsv); - - /* Program extra snap levels for display client */ - write32(®s->dis_extra_snap_levels, param->McDisExtraSnapLevels); - - /* Trigger MC timing update */ - write32(®s->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE); - - /* Program second-level clock enable overrides */ - write32(®s->clken_override, param->McClkenOverride); - - /* Program statistics gathering */ - write32(®s->stat_control, param->McStatControl); -} - -static void sdram_init_emc(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - /* Program SDRAM geometry parameters */ - write32(®s->adr_cfg, param->EmcAdrCfg); - - /* Program second-level clock enable overrides */ - write32(®s->clken_override, param->EmcClkenOverride); - - /* Program EMC pad auto calibration */ - write32(®s->auto_cal_interval, param->EmcAutoCalInterval); - write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); - write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); - write32(®s->auto_cal_config, param->EmcAutoCalConfig); - udelay(param->EmcAutoCalWait); -} - -static void sdram_set_emc_timing(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - /* Program EMC timing configuration */ - write32(®s->cfg_2, param->EmcCfg2); - write32(®s->cfg_pipe, param->EmcCfgPipe); - write32(®s->dbg, param->EmcDbg); - write32(®s->cmdq, param->EmcCmdQ); - write32(®s->mc2emcq, param->EmcMc2EmcQ); - write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); - write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); - write32(®s->fbio_cfg5, param->EmcFbioCfg5); - write32(®s->rc, param->EmcRc); - write32(®s->rfc, param->EmcRfc); - write32(®s->rfc_slr, param->EmcRfcSlr); - write32(®s->ras, param->EmcRas); - write32(®s->rp, param->EmcRp); - write32(®s->r2r, param->EmcR2r); - write32(®s->w2w, param->EmcW2w); - write32(®s->r2w, param->EmcR2w); - write32(®s->w2r, param->EmcW2r); - write32(®s->r2p, param->EmcR2p); - write32(®s->w2p, param->EmcW2p); - write32(®s->rd_rcd, param->EmcRdRcd); - write32(®s->wr_rcd, param->EmcWrRcd); - write32(®s->rrd, param->EmcRrd); - write32(®s->rext, param->EmcRext); - write32(®s->wext, param->EmcWext); - write32(®s->wdv, param->EmcWdv); - write32(®s->wdv_mask, param->EmcWdvMask); - write32(®s->quse, param->EmcQUse); - write32(®s->quse_width, param->EmcQuseWidth); - write32(®s->ibdly, param->EmcIbdly); - write32(®s->einput, param->EmcEInput); - write32(®s->einput_duration, param->EmcEInputDuration); - write32(®s->puterm_extra, param->EmcPutermExtra); - write32(®s->puterm_width, param->EmcPutermWidth); - write32(®s->puterm_adj, param->EmcPutermAdj); - write32(®s->cdb_cntl_1, param->EmcCdbCntl1); - write32(®s->cdb_cntl_2, param->EmcCdbCntl2); - write32(®s->cdb_cntl_3, param->EmcCdbCntl3); - write32(®s->qrst, param->EmcQRst); - write32(®s->qsafe, param->EmcQSafe); - write32(®s->rdv, param->EmcRdv); - write32(®s->rdv_mask, param->EmcRdvMask); - write32(®s->qpop, param->EmcQpop); - write32(®s->ctt, param->EmcCtt); - write32(®s->ctt_duration, param->EmcCttDuration); - write32(®s->refresh, param->EmcRefresh); - write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); - write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); - write32(®s->pdex2wr, param->EmcPdEx2Wr); - write32(®s->pdex2rd, param->EmcPdEx2Rd); - write32(®s->pchg2pden, param->EmcPChg2Pden); - write32(®s->act2pden, param->EmcAct2Pden); - write32(®s->ar2pden, param->EmcAr2Pden); - write32(®s->rw2pden, param->EmcRw2Pden); - write32(®s->txsr, param->EmcTxsr); - write32(®s->txsrdll, param->EmcTxsrDll); - write32(®s->tcke, param->EmcTcke); - write32(®s->tckesr, param->EmcTckesr); - write32(®s->tpd, param->EmcTpd); - write32(®s->tfaw, param->EmcTfaw); - write32(®s->trpab, param->EmcTrpab); - write32(®s->tclkstable, param->EmcTClkStable); - write32(®s->tclkstop, param->EmcTClkStop); - write32(®s->trefbw, param->EmcTRefBw); - write32(®s->odt_write, param->EmcOdtWrite); - write32(®s->odt_read, param->EmcOdtRead); - write32(®s->fbio_cfg6, param->EmcFbioCfg6); - write32(®s->cfg_dig_dll, param->EmcCfgDigDll); - write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); - - /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ - write32(®s->fbio_spare, param->EmcFbioSpare & 0xfffffffd); - - write32(®s->cfg_rsv, param->EmcCfgRsv); - write32(®s->dll_xform_dqs0, param->EmcDllXformDqs0); - write32(®s->dll_xform_dqs1, param->EmcDllXformDqs1); - write32(®s->dll_xform_dqs2, param->EmcDllXformDqs2); - write32(®s->dll_xform_dqs3, param->EmcDllXformDqs3); - write32(®s->dll_xform_dqs4, param->EmcDllXformDqs4); - write32(®s->dll_xform_dqs5, param->EmcDllXformDqs5); - write32(®s->dll_xform_dqs6, param->EmcDllXformDqs6); - write32(®s->dll_xform_dqs7, param->EmcDllXformDqs7); - write32(®s->dll_xform_dqs8, param->EmcDllXformDqs8); - write32(®s->dll_xform_dqs9, param->EmcDllXformDqs9); - write32(®s->dll_xform_dqs10, param->EmcDllXformDqs10); - write32(®s->dll_xform_dqs11, param->EmcDllXformDqs11); - write32(®s->dll_xform_dqs12, param->EmcDllXformDqs12); - write32(®s->dll_xform_dqs13, param->EmcDllXformDqs13); - write32(®s->dll_xform_dqs14, param->EmcDllXformDqs14); - write32(®s->dll_xform_dqs15, param->EmcDllXformDqs15); - write32(®s->dll_xform_quse0, param->EmcDllXformQUse0); - write32(®s->dll_xform_quse1, param->EmcDllXformQUse1); - write32(®s->dll_xform_quse2, param->EmcDllXformQUse2); - write32(®s->dll_xform_quse3, param->EmcDllXformQUse3); - write32(®s->dll_xform_quse4, param->EmcDllXformQUse4); - write32(®s->dll_xform_quse5, param->EmcDllXformQUse5); - write32(®s->dll_xform_quse6, param->EmcDllXformQUse6); - write32(®s->dll_xform_quse7, param->EmcDllXformQUse7); - write32(®s->dll_xform_quse8, param->EmcDllXformQUse8); - write32(®s->dll_xform_quse9, param->EmcDllXformQUse9); - write32(®s->dll_xform_quse10, param->EmcDllXformQUse10); - write32(®s->dll_xform_quse11, param->EmcDllXformQUse11); - write32(®s->dll_xform_quse12, param->EmcDllXformQUse12); - write32(®s->dll_xform_quse13, param->EmcDllXformQUse13); - write32(®s->dll_xform_quse14, param->EmcDllXformQUse14); - write32(®s->dll_xform_quse15, param->EmcDllXformQUse15); - write32(®s->dll_xform_dq0, param->EmcDllXformDq0); - write32(®s->dll_xform_dq1, param->EmcDllXformDq1); - write32(®s->dll_xform_dq2, param->EmcDllXformDq2); - write32(®s->dll_xform_dq3, param->EmcDllXformDq3); - write32(®s->dll_xform_dq4, param->EmcDllXformDq4); - write32(®s->dll_xform_dq5, param->EmcDllXformDq5); - write32(®s->dll_xform_dq6, param->EmcDllXformDq6); - write32(®s->dll_xform_dq7, param->EmcDllXformDq7); - write32(®s->dll_xform_addr0, param->EmcDllXformAddr0); - write32(®s->dll_xform_addr1, param->EmcDllXformAddr1); - write32(®s->dll_xform_addr2, param->EmcDllXformAddr2); - write32(®s->dll_xform_addr3, param->EmcDllXformAddr3); - write32(®s->dll_xform_addr4, param->EmcDllXformAddr4); - write32(®s->dll_xform_addr5, param->EmcDllXformAddr5); - write32(®s->acpd_control, param->EmcAcpdControl); - write32(®s->dsr_vttgen_drv, param->EmcDsrVttgenDrv); - write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); - write32(®s->bgbias_ctl0, param->EmcBgbiasCtl0); - - /* - * Set pipe bypass enable bits before sending any DRAM commands. - * Note other bits in EMC_CFG must be set AFTER REFCTRL is configured. - */ - writebits(param->EmcCfg, ®s->cfg, - (EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK | - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK | - EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK)); -} - -static void sdram_patch_bootrom(const struct sdram_params *param, - struct tegra_mc_regs *regs) -{ - if (param->BootRomPatchControl & BOOT_ROM_PATCH_CONTROL_ENABLE_MASK) { - uintptr_t addr = ((param->BootRomPatchControl & - BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> - BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); - addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - write32((uint32_t *)addr, param->BootRomPatchData); - write32(®s->timing_control, 1); - } -} - -static void sdram_set_dpd3(const struct sdram_params *param, - struct tegra_pmc_regs *regs) -{ - /* Program DPD request */ - write32(®s->io_dpd3_req, param->PmcIoDpd3Req); - udelay(param->PmcIoDpd3ReqWait); -} - -static void sdram_set_dli_trims(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - /* Program DLI trims */ - write32(®s->dli_trim_txdqs0, param->EmcDliTrimTxDqs0); - write32(®s->dli_trim_txdqs1, param->EmcDliTrimTxDqs1); - write32(®s->dli_trim_txdqs2, param->EmcDliTrimTxDqs2); - write32(®s->dli_trim_txdqs3, param->EmcDliTrimTxDqs3); - write32(®s->dli_trim_txdqs4, param->EmcDliTrimTxDqs4); - write32(®s->dli_trim_txdqs5, param->EmcDliTrimTxDqs5); - write32(®s->dli_trim_txdqs6, param->EmcDliTrimTxDqs6); - write32(®s->dli_trim_txdqs7, param->EmcDliTrimTxDqs7); - write32(®s->dli_trim_txdqs8, param->EmcDliTrimTxDqs8); - write32(®s->dli_trim_txdqs9, param->EmcDliTrimTxDqs9); - write32(®s->dli_trim_txdqs10, param->EmcDliTrimTxDqs10); - write32(®s->dli_trim_txdqs11, param->EmcDliTrimTxDqs11); - write32(®s->dli_trim_txdqs12, param->EmcDliTrimTxDqs12); - write32(®s->dli_trim_txdqs13, param->EmcDliTrimTxDqs13); - write32(®s->dli_trim_txdqs14, param->EmcDliTrimTxDqs14); - write32(®s->dli_trim_txdqs15, param->EmcDliTrimTxDqs15); - - write32(®s->ca_training_timing_cntl1, - param->EmcCaTrainingTimingCntl1); - write32(®s->ca_training_timing_cntl2, - param->EmcCaTrainingTimingCntl2); - - sdram_trigger_emc_timing_update(regs); - udelay(param->EmcTimingControlWait); -} - -static void sdram_set_clock_enable_signal(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - volatile uint32_t dummy = 0; - clrbits_le32(®s->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | - EMC_PIN_CKE_MASK)); - /* - * Assert dummy read of PIN register to ensure above write to PIN - * register went through. 200 is the recommended value by NVIDIA. - */ - dummy |= read32(®s->pin); - udelay(200 + param->EmcPinExtraWait); - - /* Deassert reset */ - setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE); - /* - * Assert dummy read of PIN register to ensure above write to PIN - * register went through. 200 is the recommended value by NVIDIA. - */ - dummy |= read32(®s->pin); - udelay(500 + param->EmcPinExtraWait); - - /* Enable clock enable signal */ - setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL); - /* - * Assert dummy read of PIN register to ensure above write to PIN - * register went through. 200 is the recommended value by NVIDIA. - */ - dummy |= read32(®s->pin); - udelay(param->EmcPinProgramWait); - - if (!dummy) { - die("Failed to program EMC pin."); - } - - /* Send NOP (trigger) */ - writebits(((1 << EMC_NOP_NOP_CMD_SHIFT) | - (param->EmcDevSelect << EMC_NOP_NOP_DEV_SELECTN_SHIFT)), - ®s->nop, - EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK); -} - -static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) -{ - /* Write mode registers */ - write32(®s->emrs2, param->EmcEmrs2); - write32(®s->emrs3, param->EmcEmrs3); - write32(®s->emrs, param->EmcEmrs); - write32(®s->mrs, param->EmcMrs); - - if (param->EmcExtraModeRegWriteEnable) { - write32(®s->mrs, param->EmcMrsExtra); - } - - write32(®s->zq_cal, param->EmcZcalInitDev0); - udelay(param->EmcZcalInitWait); - - if ((param->EmcDevSelect & 2) == 0) { - write32(®s->zq_cal, param->EmcZcalInitDev1); - udelay(param->EmcZcalInitWait); - } -} - -static void sdram_init_lpddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) -{ - /* Precharge all banks. DEV_SELECTN = 0 => Select all devices */ - write32(®s->pre, - ((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1)); - - /* Send Reset MRW command */ - write32(®s->mrw, param->EmcMrwResetCommand); - udelay(param->EmcMrwResetNInitWait); - - write32(®s->mrw, param->EmcZcalInitDev0); - udelay(param->EmcZcalInitWait); - - if ((param->EmcDevSelect & 2) == 0) - { - write32(®s->mrw, param->EmcZcalInitDev1); - udelay(param->EmcZcalInitWait); - } - - /* Write mode registers */ - write32(®s->mrw2, param->EmcMrw2); - write32(®s->mrw, param->EmcMrw1); - write32(®s->mrw3, param->EmcMrw3); - write32(®s->mrw4, param->EmcMrw4); - - if (param->EmcExtraModeRegWriteEnable) { - write32(®s->mrw, param->EmcMrwExtra); - } -} - -static void sdram_init_zq_calibration(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - if ((param->EmcZcalWarmColdBootEnables & - EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) { - /* Need to initialize ZCAL on coldboot. */ - if (param->MemoryType == NvBootMemoryType_Ddr3) - sdram_init_ddr3(param, regs); - else if (param->MemoryType == NvBootMemoryType_LpDdr2) - sdram_init_lpddr3(param, regs); - } else { - /* Wait for DLL stablization time even without ZCAL */ - udelay(param->EmcZcalInitWait); - } -} - -static void sdram_set_zq_calibration(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - /* Start periodic ZQ calibration */ - write32(®s->zcal_interval, param->EmcZcalInterval); - write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); - write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); -} - -static void sdram_set_refresh(const struct sdram_params *param, - struct tegra_emc_regs *regs) -{ - /* Insert burst refresh */ - if (param->EmcExtraRefreshNum > 0) { - uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1; - writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED | - (refresh_num << EMC_REF_NUM_SHIFT) | - (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)), - ®s->ref, (EMC_REF_CMD_MASK | EMC_REF_NORMAL_MASK | - EMC_REF_NUM_MASK | - EMC_REF_DEV_SELECTN_MASK)); - } - - /* Enable refresh */ - write32(®s->refctrl, - (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); - - write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); - write32(®s->cfg, param->EmcCfg); - write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); - - /* Write addr swizzle lock bit */ - write32(®s->fbio_spare, param->EmcFbioSpare); - - /* Re-trigger timing to latch power saving functions */ - sdram_trigger_emc_timing_update(regs); -} - -static void sdram_enable_arbiter(const struct sdram_params *param) -{ - /* TODO(hungte) Move values here to standalone header file. */ - uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0); - setbits_le32(AHB_ARBITRATION_XBAR_CTRL, - param->AhbArbitrationXbarCtrlMemInitDone << 16); -} - -static void sdram_lock_carveouts(const struct sdram_params *param, - struct tegra_mc_regs *regs) -{ - /* Lock carveouts, and emem_cfg registers */ - write32(®s->video_protect_reg_ctrl, - param->McVideoProtectWriteAccess); - write32(®s->emem_cfg_access_ctrl, - MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); - write32(®s->sec_carveout_reg_ctrl, - param->McSecCarveoutProtectWriteAccess); - write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); -} - -void sdram_init(const struct sdram_params *param) -{ - struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE; - struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE; - - printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n", - param->MemoryType, clock_get_pll_input_khz() * - param->PllMFeedbackDivider / param->PllMInputDivider / - (1 + param->PllMSelectDiv2)); - if (param->MemoryType != NvBootMemoryType_Ddr3 && - param->MemoryType != NvBootMemoryType_LpDdr2) - die("Unsupported memory type!\n"); - - sdram_configure_pmc(param, pmc); - sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); - - sdram_start_clocks(param); - sdram_patch(param->EmcBctSpare2, param->EmcBctSpare3); - - sdram_deassert_sel_dpd(param, pmc); - sdram_set_swizzle(param, emc); - sdram_set_pad_controls(param, emc); - sdram_patch(param->EmcBctSpare4, param->EmcBctSpare5); - - sdram_trigger_emc_timing_update(emc); - sdram_init_mc(param, mc); - sdram_init_emc(param, emc); - sdram_patch(param->EmcBctSpare6, param->EmcBctSpare7); - - sdram_set_emc_timing(param, emc); - sdram_patch_bootrom(param, mc); - sdram_set_dpd3(param, pmc); - sdram_set_dli_trims(param, emc); - sdram_deassert_clock_enable_signal(param, pmc); - sdram_set_clock_enable_signal(param, emc); - sdram_init_zq_calibration(param, emc); - sdram_patch(param->EmcBctSpare8, param->EmcBctSpare9); - - sdram_set_zq_calibration(param, emc); - sdram_patch(param->EmcBctSpare10, param->EmcBctSpare11); - - sdram_trigger_emc_timing_update(emc); - sdram_set_refresh(param, emc); - sdram_enable_arbiter(param); - sdram_lock_carveouts(param, mc); - - sdram_lp0_save_params(param); -} - -uint32_t sdram_get_ram_code(void) -{ - struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - return ((read32(&pmc->strapping_opt_a) & - PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> - PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); -} diff --git a/src/soc/nvidia/tegra132/sdram_lp0.c b/src/soc/nvidia/tegra132/sdram_lp0.c deleted file mode 100644 index 92b2957b19..0000000000 --- a/src/soc/nvidia/tegra132/sdram_lp0.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include <arch/cache.h> -#include <console/console.h> -#include <soc/addressmap.h> -#include <soc/clk_rst.h> -#include <soc/pmc.h> -#include <soc/sdram.h> -#include <stdlib.h> - -/* - * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from - * the common BCT format and writes them into PMC scratch registers (where the - * BootROM expects them on LP0 resume). Since those store the same values in a - * different format, we follow a "translation table" taken from Nvidia's U-Boot - * implementation to shift bits into the right position. - * - * Contrary to U-Boot, we transform the same macros directly into hardcoded - * assignments (without any pesky function calls or volatile qualifiers) to give - * the compiler as much room for optimization as possible. For that reason, we - * also intentionally avoid <arch/io.h> read/write macros, under the assumption - * that PMC scratch register accesses should not have side effects and can be - * arbitrarily reordered. For the few accesses that do have side-effects, the - * code must contain explicit memory barriers. - */ -void sdram_lp0_save_params(const struct sdram_params *sdram) -{ - struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE; - struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE; - -#define pack(src, src_bits, dst, dst_bits) { \ - _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ - (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ - _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ - (0 ? dst_bits), "src and dst byte range lengths differ" ); \ - u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ - dst &= ~(mask << (0 ? dst_bits)); \ - dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ -} - -#define s(param, src_bits, pmcreg, dst_bits) \ - pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) - -#define m(clkreg, src_bits, pmcreg, dst_bits) \ - pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits) - -#define c(value, pmcreg, dst_bits) \ - pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) - - s(EmcClockSource, 7:0, scratch6, 15:8); - s(EmcClockSource, 31:29, scratch6, 18:16); - s(EmcClockSource, 26:26, scratch6, 19:19); - s(EmcOdtWrite, 5:0, scratch6, 25:20); - s(EmcOdtWrite, 11:8, scratch6, 29:26); - s(EmcOdtWrite, 30:30, scratch6, 30:30); - s(EmcOdtWrite, 31:31, scratch6, 31:31); - s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20); - s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23); - s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26); - s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29); - s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20); - s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23); - s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26); - s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29); - s(EmcTxsrDll, 11:0, scratch9, 31:20); - c(0, scratch10, 31:0); - s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20); - s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26); - s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29); - s(EmcFbioSpare, 31:24, scratch11, 7:0); - s(EmcFbioSpare, 23:16, scratch11, 15:8); - s(EmcFbioSpare, 15:8, scratch11, 23:16); - s(EmcFbioSpare, 7:0, scratch11, 31:24); - s(EmcCfgRsv, 31:0, scratch12, 31:0); - s(EmcCdbCntl2, 31:0, scratch13, 31:0); - s(McEmemArbDaTurns, 31:0, scratch14, 31:0); - s(EmcCfgDigDll, 0:0, scratch17, 0:0); - s(EmcCfgDigDll, 25:2, scratch17, 24:1); - s(EmcCfgDigDll, 31:27, scratch17, 29:25); - s(EmcCdbCntl1, 29:0, scratch18, 29:0); - s(McEmemArbMisc0, 14:0, scratch19, 14:0); - s(McEmemArbMisc0, 30:16, scratch19, 29:15); - s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0); - s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5); - s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10); - s(EmcRrd, 3:0, scratch22, 31:28); - s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0); - s(EmcRext, 3:0, scratch23, 31:28); - s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0); - s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17); - s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22); - s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23); - s(EmcR2w, 4:0, scratch24, 31:27); - s(EmcCfg, 9:1, scratch25, 8:0); - s(EmcCfg, 26:16, scratch25, 19:9); - s(EmcCfg, 31:28, scratch25, 23:20); - s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24); - s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25); - s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26); - s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29); - s(EmcZcalInterval, 23:10, scratch26, 13:0); - s(EmcZcalInterval, 9:0, scratch26, 23:14); - s(EmcSelDpdCtrl, 5:2, scratch26, 27:24); - s(EmcSelDpdCtrl, 8:8, scratch26, 28:28); - s(EmcSelDpdCtrl, 18:16, scratch26, 31:29); - s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0); - s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23); - s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24); - s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26); - s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28); - s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30); - s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0); - s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6); - s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12); - s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17); - s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18); - s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23); - s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24); - s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26); - s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28); - s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30); - s(McEmemArbDaCovers, 23:0, scratch29, 23:0); - s(McEmemArbRsv, 7:0, scratch29, 31:24); - s(EmcAutoCalConfig, 4:0, scratch30, 4:0); - s(EmcAutoCalConfig, 12:8, scratch30, 9:5); - s(EmcAutoCalConfig, 18:16, scratch30, 12:10); - s(EmcAutoCalConfig, 25:20, scratch30, 18:13); - s(EmcAutoCalConfig, 31:28, scratch30, 22:19); - s(EmcRfc, 8:0, scratch30, 31:23); - s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0); - s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22); - s(EmcAr2Pden, 8:0, scratch31, 31:23); - s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0); - s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1); - s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4); - s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5); - s(EmcRfcSlr, 8:0, scratch32, 31:23); - s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0); - s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1); - s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2); - s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7); - s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12); - s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17); - s(EmcTxsr, 9:0, scratch33, 31:22); - s(McEmemArbCfg, 8:0, scratch40, 8:0); - s(McEmemArbCfg, 20:16, scratch40, 13:9); - s(McEmemArbCfg, 27:24, scratch40, 17:14); - s(McEmemArbCfg, 31:28, scratch40, 21:18); - s(EmcMc2EmcQ, 2:0, scratch40, 24:22); - s(EmcMc2EmcQ, 10:8, scratch40, 27:25); - s(EmcMc2EmcQ, 27:24, scratch40, 31:28); - s(EmcAutoCalInterval, 20:0, scratch42, 20:0); - s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21); - s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30); - s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0); - s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10); - s(EmcTxdsrvttgen, 11:0, scratch44, 31:20); - s(EmcMrsWaitCnt, 9:0, scratch45, 9:0); - s(EmcMrsWaitCnt, 25:16, scratch45, 19:10); - s(EmcCfgPipe, 1:0, scratch45, 21:20); - s(EmcCfgPipe, 9:4, scratch45, 27:22); - s(EmcCfgPipe, 15:12, scratch45, 31:28); - s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0); - s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5); - s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10); - s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15); - s(EmcZcalWaitCnt, 9:0, scratch46, 29:20); - s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0); - s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5); - s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10); - s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15); - s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20); - s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26); - s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0); - s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5); - s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10); - s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15); - s(EmcAutoCalConfig3, 4:0, scratch48, 24:20); - s(EmcAutoCalConfig3, 12:8, scratch48, 29:25); - s(EmcFbioCfg5, 1:0, scratch48, 31:30); - s(EmcDllXformQUse8, 4:0, scratch50, 4:0); - s(EmcDllXformQUse8, 22:8, scratch50, 19:5); - s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20); - s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25); - s(EmcFbioCfg5, 3:2, scratch50, 31:30); - s(EmcDllXformQUse9, 4:0, scratch51, 4:0); - s(EmcDllXformQUse9, 22:8, scratch51, 19:5); - s(EmcCttTermCtrl, 2:0, scratch51, 22:20); - s(EmcCttTermCtrl, 12:8, scratch51, 27:23); - s(EmcCttTermCtrl, 31:31, scratch51, 28:28); - s(EmcFbioCfg6, 2:0, scratch51, 31:29); - s(EmcDllXformQUse10, 4:0, scratch56, 4:0); - s(EmcDllXformQUse10, 22:8, scratch56, 19:5); - s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20); - s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28); - s(EmcPutermAdj, 1:0, scratch56, 30:29); - s(EmcPutermAdj, 7:7, scratch56, 31:31); - s(EmcDllXformQUse11, 4:0, scratch57, 4:0); - s(EmcDllXformQUse11, 22:8, scratch57, 19:5); - s(EmcWdv, 3:0, scratch57, 31:28); - s(EmcDllXformQUse12, 4:0, scratch58, 4:0); - s(EmcDllXformQUse12, 22:8, scratch58, 19:5); - s(EmcBurstRefreshNum, 3:0, scratch58, 31:28); - s(EmcDllXformQUse13, 4:0, scratch59, 4:0); - s(EmcDllXformQUse13, 22:8, scratch59, 19:5); - s(EmcWext, 3:0, scratch59, 31:28); - s(EmcDllXformQUse14, 4:0, scratch60, 4:0); - s(EmcDllXformQUse14, 22:8, scratch60, 19:5); - s(EmcClkenOverride, 3:1, scratch60, 30:28); - s(EmcClkenOverride, 6:6, scratch60, 31:31); - s(EmcDllXformQUse15, 4:0, scratch61, 4:0); - s(EmcDllXformQUse15, 22:8, scratch61, 19:5); - s(EmcR2r, 3:0, scratch61, 31:28); - s(EmcDllXformDq4, 4:0, scratch62, 4:0); - s(EmcDllXformDq4, 22:8, scratch62, 19:5); - s(EmcRc, 6:0, scratch62, 26:20); - s(EmcW2r, 4:0, scratch62, 31:27); - s(EmcDllXformDq5, 4:0, scratch63, 4:0); - s(EmcDllXformDq5, 22:8, scratch63, 19:5); - s(EmcTfaw, 6:0, scratch63, 26:20); - s(EmcR2p, 4:0, scratch63, 31:27); - s(EmcDllXformDq6, 4:0, scratch64, 4:0); - s(EmcDllXformDq6, 22:8, scratch64, 19:5); - s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20); - s(EmcQSafe, 4:0, scratch64, 31:27); - s(EmcDllXformDq7, 4:0, scratch65, 4:0); - s(EmcDllXformDq7, 22:8, scratch65, 19:5); - s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20); - s(EmcTClkStable, 4:0, scratch65, 31:27); - s(EmcAutoCalConfig2, 4:0, scratch66, 4:0); - s(EmcAutoCalConfig2, 12:8, scratch66, 9:5); - s(EmcAutoCalConfig2, 20:16, scratch66, 14:10); - s(EmcAutoCalConfig2, 28:24, scratch66, 19:15); - s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20); - s(EmcTClkStop, 4:0, scratch66, 31:27); - s(McEmemArbMisc1, 1:0, scratch67, 1:0); - s(McEmemArbMisc1, 12:4, scratch67, 10:2); - s(McEmemArbMisc1, 25:21, scratch67, 15:11); - s(McEmemArbMisc1, 31:28, scratch67, 19:16); - s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20); - s(EmcEInputDuration, 4:0, scratch67, 31:27); - s(EmcZcalMrwCmd, 7:0, scratch68, 7:0); - s(EmcZcalMrwCmd, 23:16, scratch68, 15:8); - s(EmcZcalMrwCmd, 31:30, scratch68, 17:16); - s(EmcTRefBw, 13:0, scratch68, 31:18); - s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0); - s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18); - s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25); - s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0); - s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18); - s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25); - s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0); - s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3); - s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6); - s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9); - s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12); - s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15); - s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18); - s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25); - s(EmcCdbCntl3, 17:0, scratch72, 17:0); - s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18); - s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25); - s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0); - s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3); - s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6); - s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9); - s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12); - s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15); - s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18); - s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25); - s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0); - s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3); - s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6); - s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9); - s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12); - s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15); - s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18); - s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25); - s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0); - s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3); - s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6); - s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9); - s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12); - s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15); - s(McEmemArbTimingRp, 6:0, scratch75, 24:18); - s(McEmemArbTimingRc, 6:0, scratch75, 31:25); - s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0); - s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3); - s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6); - s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9); - s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12); - s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15); - s(McEmemArbTimingFaw, 6:0, scratch76, 24:18); - s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25); - s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0); - s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3); - s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6); - s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9); - s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12); - s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15); - s(EmcRas, 5:0, scratch77, 23:18); - s(EmcRp, 5:0, scratch77, 29:24); - s(EmcCfg2, 9:8, scratch77, 31:30); - s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0); - s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3); - s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6); - s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9); - s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12); - s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15); - s(EmcW2p, 5:0, scratch78, 23:18); - s(EmcRdRcd, 5:0, scratch78, 29:24); - s(EmcCfg2, 27:26, scratch78, 31:30); - s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0); - s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3); - s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6); - s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9); - s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12); - s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15); - s(EmcWrRcd, 5:0, scratch79, 23:18); - s(EmcQUse, 5:0, scratch79, 29:24); - s(EmcFbioCfg5, 4:4, scratch79, 31:31); - s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0); - s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3); - s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6); - s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9); - s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12); - s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15); - s(EmcQRst, 5:0, scratch80, 23:18); - s(EmcRdv, 5:0, scratch80, 29:24); - s(EmcFbioCfg5, 6:5, scratch80, 31:30); - s(EmcDynSelfRefControl, 15:0, scratch81, 15:0); - s(EmcDynSelfRefControl, 31:31, scratch81, 16:16); - s(EmcPdEx2Wr, 5:0, scratch81, 22:17); - s(EmcPdEx2Rd, 5:0, scratch81, 28:23); - s(EmcRefresh, 5:0, scratch82, 5:0); - s(EmcRefresh, 15:6, scratch82, 15:6); - s(EmcCmdQ, 4:0, scratch82, 20:16); - s(EmcCmdQ, 10:8, scratch82, 23:21); - s(EmcCmdQ, 14:12, scratch82, 26:24); - s(EmcCmdQ, 28:24, scratch82, 31:27); - s(EmcAcpdControl, 15:0, scratch83, 15:0); - s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16); - s(EmcDllXformDqs0, 4:0, scratch84, 4:0); - s(EmcDllXformDqs0, 22:12, scratch84, 15:5); - s(EmcDllXformDqs1, 4:0, scratch84, 20:16); - s(EmcDllXformDqs1, 22:12, scratch84, 31:21); - s(EmcDllXformDqs2, 4:0, scratch85, 4:0); - s(EmcDllXformDqs2, 22:12, scratch85, 15:5); - s(EmcDllXformDqs3, 4:0, scratch85, 20:16); - s(EmcDllXformDqs3, 22:12, scratch85, 31:21); - s(EmcDllXformDqs4, 4:0, scratch86, 4:0); - s(EmcDllXformDqs4, 22:12, scratch86, 15:5); - s(EmcDllXformDqs5, 4:0, scratch86, 20:16); - s(EmcDllXformDqs5, 22:12, scratch86, 31:21); - s(EmcDllXformDqs6, 4:0, scratch87, 4:0); - s(EmcDllXformDqs6, 22:12, scratch87, 15:5); - s(EmcDllXformDqs7, 4:0, scratch87, 20:16); - s(EmcDllXformDqs7, 22:12, scratch87, 31:21); - s(EmcDllXformDqs8, 4:0, scratch88, 4:0); - s(EmcDllXformDqs8, 22:12, scratch88, 15:5); - s(EmcDllXformDqs9, 4:0, scratch88, 20:16); - s(EmcDllXformDqs9, 22:12, scratch88, 31:21); - s(EmcDllXformDqs10, 4:0, scratch89, 4:0); - s(EmcDllXformDqs10, 22:12, scratch89, 15:5); - s(EmcDllXformDqs11, 4:0, scratch89, 20:16); - s(EmcDllXformDqs11, 22:12, scratch89, 31:21); - s(EmcDllXformDqs12, 4:0, scratch90, 4:0); - s(EmcDllXformDqs12, 22:12, scratch90, 15:5); - s(EmcDllXformDqs13, 4:0, scratch90, 20:16); - s(EmcDllXformDqs13, 22:12, scratch90, 31:21); - s(EmcDllXformDqs14, 4:0, scratch91, 4:0); - s(EmcDllXformDqs14, 22:12, scratch91, 15:5); - s(EmcDllXformDqs15, 4:0, scratch91, 20:16); - s(EmcDllXformDqs15, 22:12, scratch91, 31:21); - s(EmcDllXformQUse0, 4:0, scratch92, 4:0); - s(EmcDllXformQUse0, 22:12, scratch92, 15:5); - s(EmcDllXformQUse1, 4:0, scratch92, 20:16); - s(EmcDllXformQUse1, 22:12, scratch92, 31:21); - s(EmcDllXformQUse2, 4:0, scratch93, 4:0); - s(EmcDllXformQUse2, 22:12, scratch93, 15:5); - s(EmcDllXformQUse3, 4:0, scratch93, 20:16); - s(EmcDllXformQUse3, 22:12, scratch93, 31:21); - s(EmcDllXformQUse4, 4:0, scratch94, 4:0); - s(EmcDllXformQUse4, 22:12, scratch94, 15:5); - s(EmcDllXformQUse5, 4:0, scratch94, 20:16); - s(EmcDllXformQUse5, 22:12, scratch94, 31:21); - s(EmcDllXformQUse6, 4:0, scratch95, 4:0); - s(EmcDllXformQUse6, 22:12, scratch95, 15:5); - s(EmcDllXformQUse7, 4:0, scratch95, 20:16); - s(EmcDllXformQUse7, 22:12, scratch95, 31:21); - s(EmcDllXformDq0, 4:0, scratch96, 4:0); - s(EmcDllXformDq0, 22:12, scratch96, 15:5); - s(EmcDllXformDq1, 4:0, scratch96, 20:16); - s(EmcDllXformDq1, 22:12, scratch96, 31:21); - s(EmcDllXformDq2, 4:0, scratch97, 4:0); - s(EmcDllXformDq2, 22:12, scratch97, 15:5); - s(EmcDllXformDq3, 4:0, scratch97, 20:16); - s(EmcDllXformDq3, 22:12, scratch97, 31:21); - s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0); - s(EmcDllXformAddr0, 4:0, scratch98, 20:16); - s(EmcDllXformAddr0, 22:12, scratch98, 31:21); - s(EmcDllXformAddr1, 4:0, scratch99, 4:0); - s(EmcDllXformAddr1, 22:12, scratch99, 15:5); - s(EmcDllXformAddr2, 4:0, scratch99, 20:16); - s(EmcDllXformAddr2, 22:12, scratch99, 31:21); - s(EmcDllXformAddr3, 4:0, scratch100, 4:0); - s(EmcDllXformAddr3, 22:12, scratch100, 15:5); - s(EmcDllXformAddr4, 4:0, scratch100, 20:16); - s(EmcDllXformAddr4, 22:12, scratch100, 31:21); - s(EmcDllXformAddr5, 4:0, scratch101, 4:0); - s(EmcDllXformAddr5, 22:12, scratch101, 15:5); - s(EmcPChg2Pden, 5:0, scratch102, 5:0); - s(EmcAct2Pden, 5:0, scratch102, 11:6); - s(EmcRw2Pden, 5:0, scratch102, 17:12); - s(EmcTcke, 5:0, scratch102, 23:18); - s(EmcTrpab, 5:0, scratch102, 29:24); - s(EmcFbioCfg5, 8:7, scratch102, 31:30); - s(EmcCtt, 5:0, scratch103, 5:0); - s(EmcEInput, 5:0, scratch103, 11:6); - s(EmcPutermExtra, 21:16, scratch103, 17:12); - s(EmcTckesr, 5:0, scratch103, 23:18); - s(EmcTpd, 5:0, scratch103, 29:24); - s(EmcFbioCfg5, 10:9, scratch103, 31:30); - s(EmcRdvMask, 5:0, scratch104, 5:0); - s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6); - s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7); - s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8); - s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9); - s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10); - s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11); - s(EmcQpop, 5:0, scratch104, 17:12); - s(McEmemArbTimingRcd, 5:0, scratch104, 23:18); - s(McEmemArbTimingRas, 5:0, scratch104, 29:24); - s(EmcFbioCfg5, 12:11, scratch104, 31:30); - s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0); - s(McEmemArbTimingR2W, 5:0, scratch105, 11:6); - s(McEmemArbTimingW2R, 5:0, scratch105, 17:12); - s(EmcIbdly, 4:0, scratch105, 22:18); - s(McEmemArbTimingR2R, 4:0, scratch105, 27:23); - s(EmcW2w, 3:0, scratch105, 31:28); - s(McEmemArbTimingW2W, 4:0, scratch106, 4:0); - s(McEmemArbOverride, 27:27, scratch106, 5:5); - s(McEmemArbOverride, 26:26, scratch106, 6:6); - s(McEmemArbOverride, 16:16, scratch106, 7:7); - s(McEmemArbOverride, 10:10, scratch106, 8:8); - s(McEmemArbOverride, 4:4, scratch106, 9:9); - s(EmcWdvMask, 3:0, scratch106, 13:10); - s(EmcCttDuration, 3:0, scratch106, 17:14); - s(EmcQuseWidth, 3:0, scratch106, 21:18); - s(EmcPutermWidth, 3:0, scratch106, 25:22); - s(EmcBgbiasCtl0, 3:0, scratch106, 29:26); - s(EmcFbioCfg5, 25:24, scratch106, 31:30); - s(McEmemArbTimingRrd, 3:0, scratch107, 3:0); - s(EmcFbioCfg5, 23:20, scratch107, 10:7); - s(EmcFbioCfg5, 15:13, scratch107, 13:11); - s(EmcCfg2, 5:3, scratch107, 16:14); - s(EmcFbioCfg5, 26:26, scratch107, 17:17); - s(EmcFbioCfg5, 28:28, scratch107, 18:18); - s(EmcCfg2, 2:0, scratch107, 21:19); - s(EmcCfg2, 7:6, scratch107, 23:22); - s(EmcCfg2, 15:10, scratch107, 29:24); - s(EmcCfg2, 23:22, scratch107, 31:30); - s(EmcCfg2, 25:24, scratch108, 1:0); - s(EmcCfg2, 31:28, scratch108, 5:2); - s(BootRomPatchData, 31:0, scratch15, 31:0); - s(BootRomPatchControl, 31:0, scratch16, 31:0); - s(EmcDevSelect, 1:0, scratch17, 31:30); - s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30); - s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30); - s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30); - s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31); - s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30); - s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31); - s(EmcTimingControlWait, 7:0, scratch57, 27:20); - s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20); - s(EmcAutoCalWait, 7:0, scratch59, 27:20); - s(WarmBootWait, 7:0, scratch60, 27:20); - s(EmcPinProgramWait, 7:0, scratch61, 27:20); - s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30); - s(EmcExtraRefreshNum, 2:0, scratch81, 31:29); - s(SwizzleRankByteEncode, 15:0, scratch101, 31:16); - s(MemoryType, 2:0, scratch107, 6:4); - - switch (sdram->MemoryType) { - case NvBootMemoryType_LpDdr2: - s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); - s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); - s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); - s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); - s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); - s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); - s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); - s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); - s(EmcMrw1, 7:0, scratch7, 7:0); - s(EmcMrw1, 23:16, scratch7, 15:8); - s(EmcMrw1, 27:26, scratch7, 17:16); - s(EmcMrw1, 31:30, scratch7, 19:18); - s(EmcMrw2, 7:0, scratch8, 7:0); - s(EmcMrw2, 23:16, scratch8, 15:8); - s(EmcMrw2, 27:26, scratch8, 17:16); - s(EmcMrw2, 31:30, scratch8, 19:18); - s(EmcMrw3, 7:0, scratch9, 7:0); - s(EmcMrw3, 23:16, scratch9, 15:8); - s(EmcMrw3, 27:26, scratch9, 17:16); - s(EmcMrw3, 31:30, scratch9, 19:18); - s(EmcMrw4, 7:0, scratch10, 7:0); - s(EmcMrw4, 23:16, scratch10, 15:8); - s(EmcMrw4, 27:26, scratch10, 17:16); - s(EmcMrw4, 31:30, scratch10, 19:18); - break; - case NvBootMemoryType_Ddr3: - s(EmcMrs, 13:0, scratch5, 13:0); - s(EmcEmrs, 13:0, scratch5, 27:14); - s(EmcMrs, 21:20, scratch5, 29:28); - s(EmcMrs, 31:30, scratch5, 31:30); - s(EmcEmrs2, 13:0, scratch7, 13:0); - s(EmcEmrs, 21:20, scratch7, 15:14); - s(EmcEmrs, 31:30, scratch7, 17:16); - s(EmcEmrs2, 21:20, scratch7, 19:18); - s(EmcEmrs3, 13:0, scratch8, 13:0); - s(EmcEmrs2, 31:30, scratch8, 15:14); - s(EmcEmrs3, 21:20, scratch8, 17:16); - s(EmcEmrs3, 31:30, scratch8, 19:18); - s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); - s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14); - s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16); - s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18); - s(EmcMrs, 27:26, scratch10, 1:0); - s(EmcEmrs, 27:26, scratch10, 3:2); - s(EmcEmrs2, 27:26, scratch10, 5:4); - s(EmcEmrs3, 27:26, scratch10, 7:6); - s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); - s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); - s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); - s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); - c(0, scratch116, 31:0); - c(0, scratch117, 31:0); - break; - default: - printk(BIOS_CRIT, "ERROR: %s() unrecognized MemoryType %d!\n", - __func__, sdram->MemoryType); - } - - s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0); - s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0); - s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4); - s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10); - s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20); - s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21); - s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24); - s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28); - s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30); - s(EmcAdrCfg, 0:0, secure_scratch9, 31:31); - s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0); - s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16); - s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0); - s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16); - s(McEmemCfg, 13:0, secure_scratch12, 13:0); - s(McEmemCfg, 31:31, secure_scratch12, 14:14); - s(McVideoProtectBom, 31:20, secure_scratch12, 26:15); - s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27); - s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29); - s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30); - s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0); - s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12); - s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24); - s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27); - s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29); - s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31); - s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0); - s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12); - s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24); - s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26); - s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27); - s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0); - s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12); - s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15); - s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17); - s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21); - s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24); - s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26); - - c(0x1555555, sec_disable2, 25:0); - c(0xff, sec_disable, 19:12); - - c(0, scratch2, 31:0); - m(pllm_base, 15:0, scratch2, 15:0); - m(pllm_base, 20:20, scratch2, 16:16); - m(pllm_misc2, 2:0, scratch2, 19:17); - c(0, scratch35, 31:0); - m(pllm_misc1, 23:0, scratch35, 23:0); - m(pllm_misc1, 30:28, scratch35, 30:28); - c(0, scratch3, 31:0); - s(PllMInputDivider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); - c(0, scratch3, 19:16); - s(PllMKVCO, 0:0, scratch3, 20:20); - s(PllMKCP, 1:0, scratch3, 22:21); - c(0, scratch36, 31:0); - s(PllMSetupControl, 23:0, scratch36, 23:0); - c(0, scratch4, 31:0); - s(PllMStableTime, 9:0, scratch4, 9:0); - s(PllMStableTime, 9:0, scratch4, 19:10); - - s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27); - s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26); - s(PllMKCP, 1:0, pllm_wb0_override2, 25:24); - s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0); - s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8); - s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0); - - c(3, pllp_wb0_override, 12:11); -} diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c deleted file mode 100644 index 40889a7e05..0000000000 --- a/src/soc/nvidia/tegra132/soc.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <arch/cache.h> -#include <cpu/cpu.h> -#include <bootmode.h> -#include <bootstate.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/device.h> -#include <soc/nvidia/tegra/dc.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/cpu.h> -#include <soc/nvidia/tegra/apbmisc.h> -#include <string.h> -#include <timer.h> - -#include "chip.h" - -static void soc_read_resources(device_t dev) -{ - unsigned long index = 0; - int i; uintptr_t begin, end; - size_t size; - - for (i = 0; i < CARVEOUT_NUM; i++) { - carveout_range(i, &begin, &size); - if (size == 0) - continue; - reserved_ram_resource(dev, index++, begin * KiB, size * KiB); - } - - memory_in_range_below_4gb(&begin, &end); - size = end - begin; - ram_resource(dev, index++, begin * KiB, size * KiB); - - memory_in_range_above_4gb(&begin, &end); - size = end - begin; - ram_resource(dev, index++, begin * KiB, size * KiB); -} - -static struct device_operations soc_ops = { - .read_resources = soc_read_resources, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, - .scan_bus = NULL, -}; - -static void enable_tegra132_dev(device_t dev) -{ - if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &soc_ops; - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return; - - if (display_init_required()) - display_startup(dev); - else - printk(BIOS_INFO, "Skipping display init.\n"); -} - -static void tegra132_init(void *chip_info) -{ - struct tegra_revision rev; - - tegra_revision_info(&rev); - - printk(BIOS_INFO, "chip %x rev %02x.%x\n", - rev.chip_id, rev.major, rev.minor); - - printk(BIOS_INFO, "MTS build %u\n", raw_read_aidr_el1()); -} - -struct chip_operations soc_nvidia_tegra132_ops = { - CHIP_NAME("SOC Nvidia Tegra132") - .init = tegra132_init, - .enable_dev = enable_tegra132_dev, -}; - -static void enable_plld(void *unused) -{ - /* - * Configure a conservative 300MHz clock for PLLD. The kernel cannot - * handle PLLD not being configured so enable PLLD unconditionally - * with a default clock rate. - */ - clock_configure_plld(300 * MHz); -} - -/* - * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init() - * is the first thing called. This ensures PLLD is up and functional before - * anything that mainboard can do that implicitly relies on PLLD. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL); diff --git a/src/soc/nvidia/tegra132/sor.c b/src/soc/nvidia/tegra132/sor.c deleted file mode 100644 index baa06853b8..0000000000 --- a/src/soc/nvidia/tegra132/sor.c +++ /dev/null @@ -1,1100 +0,0 @@ -/* - * drivers/video/tegra/dc/sor.c - * - * Copyright (c) 2011-2015, NVIDIA Corporation. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <lib.h> -#include <stdlib.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <device/device.h> -#include <stdlib.h> -#include <string.h> -#include <cpu/cpu.h> -#include <boot/tables.h> -#include <cbmem.h> -#include <soc/nvidia/tegra/dc.h> -#include <soc/nvidia/tegra/types.h> -#include <soc/sor.h> -#include <soc/nvidia/tegra/displayport.h> -#include <soc/clk_rst.h> -#include <soc/clock.h> -#include "chip.h" -#include <soc/display.h> - -#define DEBUG_SOR 0 - -#define APBDEV_PMC_DPD_SAMPLE (0x20) -#define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE (0) -#define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE (1) -#define APBDEV_PMC_SEL_DPD_TIM (0x1c8) -#define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT (0x7f) -#define APBDEV_PMC_IO_DPD2_REQ (0x1c0) -#define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT (25) -#define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25) -#define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25) -#define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT (30) -#define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30) -#define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30) -#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30) -#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30) -#define APBDEV_PMC_IO_DPD2_STATUS (0x1c4) -#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT (25) -#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25) -#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25) - -#define DC_N_WINDOWS 5 - -static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) -{ - void *addr = sor->base + (u32) (reg << 2); - u32 reg_val = READL(addr); - return reg_val; -} - -static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, - u32 reg, u32 val) -{ - void *addr = sor->base + (u32) (reg << 2); - WRITEL(val, addr); -} - -static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, - u32 reg, u32 mask, u32 val) -{ - u32 reg_val = tegra_sor_readl(sor, reg); - reg_val &= ~mask; - reg_val |= val; - tegra_sor_writel(sor, reg, reg_val); -} - -void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor) -{ - tegra_sor_write_field(sor, - NV_SOR_DP_PADCTL(sor->portnum), - NV_SOR_DP_PADCTL_TX_PU_MASK, - NV_SOR_DP_PADCTL_TX_PU_DISABLE); -} - -void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, - u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported) -{ - tegra_sor_write_field(sor, NV_SOR_PR(sor->portnum), - mask, pe_reg); - tegra_sor_write_field(sor, NV_SOR_DC(sor->portnum), - mask, vs_reg); - if (pc_supported) { - tegra_sor_write_field( - sor, NV_SOR_POSTCURSOR(sor->portnum), - mask, pc_reg); - } -} - -static u32 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, - u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) -{ - u32 temp = timeout_us; - u32 reg_val = 0; - - do { - udelay(poll_interval_us); - reg_val = tegra_sor_readl(sor, reg); - if (timeout_us > poll_interval_us) - timeout_us -= poll_interval_us; - else - break; - } while ((reg_val & mask) != exp_val); - - if ((reg_val & mask) == exp_val) - return 0; /* success */ - printk(BIOS_ERR, - "sor_poll_register 0x%x: timeout, " - "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", - reg, reg_val, mask, exp_val); - - return temp; -} - -int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd) -{ - u32 reg_val; - u32 orig_val; - - orig_val = tegra_sor_readl(sor, NV_SOR_PWR); - - reg_val = pu_pd ? NV_SOR_PWR_NORMAL_STATE_PU : - NV_SOR_PWR_NORMAL_STATE_PD; /* normal state only */ - - if (reg_val == orig_val) - return 0; /* No update needed */ - - reg_val |= NV_SOR_PWR_SETTING_NEW_TRIGGER; - tegra_sor_writel(sor, NV_SOR_PWR, reg_val); - - /* Poll to confirm it is done */ - if (tegra_dc_sor_poll_register(sor, NV_SOR_PWR, - NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK, - NV_SOR_PWR_SETTING_NEW_DONE, - 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { - printk(BIOS_ERR, - "dc timeout waiting for SOR_PWR = NEW_DONE\n"); - return -EFAULT; - } - return 0; -} - -void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, - u8 training_pattern, const struct tegra_dc_dp_link_config *link_cfg) -{ - u32 reg_val; - - reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum)); - - if (ena) - reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES; - else - reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO; - - reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK; - reg_val |= (link_cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT); - - if (link_cfg->enhanced_framing) - reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE; - - tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val); - - switch (training_pattern) { - case training_pattern_1: - tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141); - break; - case training_pattern_2: - case training_pattern_3: - reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? - 0x43434343 : 0x42424242; - tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val); - break; - default: - tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050); - break; - } -} - -static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, - int pu, int is_lvds) -{ - u32 reg_val; - - /* SOR lane sequencer */ - if (pu) - reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER | - NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | - NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU; - else - reg_val = NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER | - NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP | - NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD; - - if (is_lvds) - reg_val |= 15 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT; - else - reg_val |= 1 << NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT; - - tegra_sor_writel(sor, NV_SOR_LANE_SEQ_CTL, reg_val); - - if (tegra_dc_sor_poll_register(sor, NV_SOR_LANE_SEQ_CTL, - NV_SOR_LANE_SEQ_CTL_SETTING_MASK, - NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE, - 100, TEGRA_SOR_TIMEOUT_MS*1000)) { - printk(BIOS_ERR, - "dp: timeout while waiting for SOR lane sequencer " - "to power down langes\n"); - return -1; - } - return 0; -} - -static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, - u32 lane_count, int pu) -{ - u32 reg_val; - - reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum)); - - if (pu) { - switch (lane_count) { - case 4: - reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | - NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ - case 2: - reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - case 1: - reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; - break; - default: - printk(BIOS_ERR, - "dp: invalid lane number %d\n", lane_count); - return -1; - } - - tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val); - tegra_dc_sor_set_lane_count(sor, lane_count); - } - return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); -} - -void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, - int power_up) -{ - u32 reg_val; - - reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum)); - - if (power_up) - reg_val &= ~NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN; - else - reg_val |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN; - - tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val); -} - -static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, - u32 pwm_dutycycle) -{ - tegra_sor_writel(sor, NV_SOR_PWM_DIV, pwm_div); - tegra_sor_writel(sor, NV_SOR_PWM_CTL, - (pwm_dutycycle & NV_SOR_PWM_CTL_DUTY_CYCLE_MASK) | - NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER); - - if (tegra_dc_sor_poll_register(sor, NV_SOR_PWM_CTL, - NV_SOR_PWM_CTL_SETTING_NEW_SHIFT, - NV_SOR_PWM_CTL_SETTING_NEW_DONE, - 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { - printk(BIOS_ERR, - "dp: timeout while waiting for SOR PWM setting\n"); - } -} - -static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor, - const struct tegra_dc_dp_link_config *link_cfg) -{ - u32 reg_val; - - tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); - - tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg); - reg_val = tegra_sor_readl(sor, NV_SOR_DP_CONFIG(sor->portnum)); - reg_val &= ~NV_SOR_DP_CONFIG_WATERMARK_MASK; - reg_val |= link_cfg->watermark; - reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK; - reg_val |= (link_cfg->active_count << - NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT); - reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK; - reg_val |= (link_cfg->active_frac << - NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT); - if (link_cfg->activepolarity) - reg_val |= NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; - else - reg_val &= ~NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; - reg_val |= (NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE | - NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE); - - tegra_sor_writel(sor, NV_SOR_DP_CONFIG(sor->portnum), reg_val); - - /* program h/vblank sym */ - tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_HBLANK_SYMBOLS, - NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK, link_cfg->hblank_sym); - - tegra_sor_write_field(sor, NV_SOR_DP_AUDIO_VBLANK_SYMBOLS, - NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK, link_cfg->vblank_sym); -} - -static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor) -{ - tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0); - tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 1); - tegra_sor_writel(sor, NV_SOR_SUPER_STATE0, 0); -} - -static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor) -{ - tegra_sor_writel(sor, NV_SOR_STATE0, 0); - tegra_sor_writel(sor, NV_SOR_STATE0, 1); - tegra_sor_writel(sor, NV_SOR_STATE0, 0); -} - -static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) -{ - u32 reg_val; - void *pmc_base = sor->pmc_base; - - if (up) { - WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE, - pmc_base + APBDEV_PMC_DPD_SAMPLE); - WRITEL(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM); - } - - reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_REQ); - reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON || - APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK); - - reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON | - APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF : - APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF | - APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON; - - WRITEL(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ); - - /* Polling */ - u32 temp = 10*1000; - do { - udelay(20); - reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_STATUS); - if (temp > 20) - temp -= 20; - else - break; - } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0); - - if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) - printk(BIOS_ERR, - "PMC_IO_DPD2 polling failed (0x%x)\n", reg_val); - - if (up) - WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE, - pmc_base + APBDEV_PMC_DPD_SAMPLE); -} - -void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int) -{ - u32 reg_val; - - reg_val = tegra_sor_readl(sor, NV_SOR_DP_SPARE(sor->portnum)); - if (is_int) - reg_val |= NV_SOR_DP_SPARE_PANEL_INTERNAL; - else - reg_val &= ~NV_SOR_DP_SPARE_PANEL_INTERNAL; - - reg_val |= NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK | - NV_SOR_DP_SPARE_SEQ_ENABLE_YES; - tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val); -} - -void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, - u8 *lane_count) -{ - u32 reg_val; - - reg_val = tegra_sor_readl(sor, NV_SOR_CLK_CNTRL); - *link_bw = (reg_val & NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK) - >> NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT; - reg_val = tegra_sor_readl(sor, - NV_SOR_DP_LINKCTL(sor->portnum)); - - switch (reg_val & NV_SOR_DP_LINKCTL_LANECOUNT_MASK) { - case NV_SOR_DP_LINKCTL_LANECOUNT_ZERO: - *lane_count = 0; - break; - case NV_SOR_DP_LINKCTL_LANECOUNT_ONE: - *lane_count = 1; - break; - case NV_SOR_DP_LINKCTL_LANECOUNT_TWO: - *lane_count = 2; - break; - case NV_SOR_DP_LINKCTL_LANECOUNT_FOUR: - *lane_count = 4; - break; - default: - printk(BIOS_ERR, "Unknown lane count\n"); - } -} - -void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw) -{ - tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL, - NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK, - link_bw << NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT); -} - -void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count) -{ - u32 reg_val; - - reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum)); - reg_val &= ~NV_SOR_DP_LINKCTL_LANECOUNT_MASK; - switch (lane_count) { - case 0: - break; - case 1: - reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_ONE; - break; - case 2: - reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_TWO; - break; - case 4: - reg_val |= NV_SOR_DP_LINKCTL_LANECOUNT_FOUR; - break; - default: - /* 0 should be handled earlier. */ - printk(BIOS_ERR, "dp: Invalid lane count %d\n", - lane_count); - return; - } - tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val); -} - -static void tegra_sor_enable_edp_clock(struct tegra_dc_sor_data *sor) -{ - sor_clock_start(); -} - -/* The SOR power sequencer does not work for t124/T132 so SW has to - go through the power sequence manually */ -/* Power up steps from spec: */ -/* STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL */ -/* 1 1 1 1 1 1 1 1 */ -/* 2 1 1 1 1 1 0 1 */ -/* 3 1 1 0 1 1 0 1 */ -/* 4 1 0 0 0 0 0 1 */ -/* 5 0 0 0 0 0 0 1 */ -static void tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, - int is_lvds) -{ - if (sor->power_is_up) - return; - - /* Set link bw */ - tegra_dc_sor_set_link_bandwidth(sor, - is_lvds ? NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS : - NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62); - - /* step 1 */ - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */ - NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */ - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */ - NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE | - NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE | - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE); - tegra_sor_write_field(sor, NV_SOR_PLL0, - NV_SOR_PLL0_PWR_MASK | /* PDPLL */ - NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */ - NV_SOR_PLL0_PWR_OFF | - NV_SOR_PLL0_VCOPD_ASSERT); - tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), - NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */ - NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP); - - /* step 2 */ - tegra_dc_sor_io_set_dpd(sor, 1); - udelay(15); - - /* step 3 */ - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK, - NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); - udelay(25); - - /* step 4 */ - tegra_sor_write_field(sor, NV_SOR_PLL0, - NV_SOR_PLL0_PWR_MASK | /* PDPLL */ - NV_SOR_PLL0_VCOPD_MASK, /* PLLVCOPD */ - NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND); - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */ - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); - udelay(225); - - /* step 5 */ - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, /* PDPORT */ - NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE); - - sor->power_is_up = 1; -} - -#if DEBUG_SOR -static void dump_sor_reg(struct tegra_dc_sor_data *sor) -{ -#define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \ - #a, a, tegra_sor_readl(sor, a)); - - DUMP_REG(NV_SOR_SUPER_STATE0); - DUMP_REG(NV_SOR_SUPER_STATE1); - DUMP_REG(NV_SOR_STATE0); - DUMP_REG(NV_SOR_STATE1); - DUMP_REG(NV_HEAD_STATE0(0)); - DUMP_REG(NV_HEAD_STATE0(1)); - DUMP_REG(NV_HEAD_STATE1(0)); - DUMP_REG(NV_HEAD_STATE1(1)); - DUMP_REG(NV_HEAD_STATE2(0)); - DUMP_REG(NV_HEAD_STATE2(1)); - DUMP_REG(NV_HEAD_STATE3(0)); - DUMP_REG(NV_HEAD_STATE3(1)); - DUMP_REG(NV_HEAD_STATE4(0)); - DUMP_REG(NV_HEAD_STATE4(1)); - DUMP_REG(NV_HEAD_STATE5(0)); - DUMP_REG(NV_HEAD_STATE5(1)); - DUMP_REG(NV_SOR_CRC_CNTRL); - DUMP_REG(NV_SOR_CLK_CNTRL); - DUMP_REG(NV_SOR_CAP); - DUMP_REG(NV_SOR_PWR); - DUMP_REG(NV_SOR_TEST); - DUMP_REG(NV_SOR_PLL0); - DUMP_REG(NV_SOR_PLL1); - DUMP_REG(NV_SOR_PLL2); - DUMP_REG(NV_SOR_PLL3); - DUMP_REG(NV_SOR_CSTM); - DUMP_REG(NV_SOR_LVDS); - DUMP_REG(NV_SOR_CRCA); - DUMP_REG(NV_SOR_CRCB); - DUMP_REG(NV_SOR_SEQ_CTL); - DUMP_REG(NV_SOR_LANE_SEQ_CTL); - DUMP_REG(NV_SOR_SEQ_INST(0)); - DUMP_REG(NV_SOR_SEQ_INST(1)); - DUMP_REG(NV_SOR_SEQ_INST(2)); - DUMP_REG(NV_SOR_SEQ_INST(3)); - DUMP_REG(NV_SOR_SEQ_INST(4)); - DUMP_REG(NV_SOR_SEQ_INST(5)); - DUMP_REG(NV_SOR_SEQ_INST(6)); - DUMP_REG(NV_SOR_SEQ_INST(7)); - DUMP_REG(NV_SOR_SEQ_INST(8)); - DUMP_REG(NV_SOR_PWM_DIV); - DUMP_REG(NV_SOR_PWM_CTL); - DUMP_REG(NV_SOR_MSCHECK); - DUMP_REG(NV_SOR_XBAR_CTRL); - DUMP_REG(NV_SOR_DP_LINKCTL(0)); - DUMP_REG(NV_SOR_DP_LINKCTL(1)); - DUMP_REG(NV_SOR_DC(0)); - DUMP_REG(NV_SOR_DC(1)); - DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0)); - DUMP_REG(NV_SOR_PR(0)); - DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0)); - DUMP_REG(NV_SOR_POSTCURSOR(0)); - DUMP_REG(NV_SOR_DP_CONFIG(0)); - DUMP_REG(NV_SOR_DP_CONFIG(1)); - DUMP_REG(NV_SOR_DP_MN(0)); - DUMP_REG(NV_SOR_DP_MN(1)); - DUMP_REG(NV_SOR_DP_PADCTL(0)); - DUMP_REG(NV_SOR_DP_PADCTL(1)); - DUMP_REG(NV_SOR_DP_DEBUG(0)); - DUMP_REG(NV_SOR_DP_DEBUG(1)); - DUMP_REG(NV_SOR_DP_SPARE(0)); - DUMP_REG(NV_SOR_DP_SPARE(1)); - DUMP_REG(NV_SOR_DP_TPG); - - return; -} -#endif - -static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, - int is_lvds) -{ - const struct tegra_dc *dc = sor->dc; - const struct tegra_dc_dp_data *dp = dc->out; - const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg; - const struct soc_nvidia_tegra132_config *config = dc->config; - - const int head_num = 0; - u32 reg_val = NV_SOR_STATE1_ASY_OWNER_HEAD0 << head_num; - u32 vsync_end, hsync_end; - u32 vblank_end, hblank_end; - u32 vblank_start, hblank_start; - - reg_val |= is_lvds ? NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM : - NV_SOR_STATE1_ASY_PROTOCOL_DP_A; - reg_val |= NV_SOR_STATE1_ASY_SUBOWNER_NONE | - NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER; - - reg_val |= NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE; - reg_val |= NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; - reg_val |= (link_cfg->bits_per_pixel > 18) ? - NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 : - NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444; - - tegra_sor_writel(sor, NV_SOR_STATE1, reg_val); - - /* Skipping programming NV_HEAD_STATE0, assuming: - interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB */ - - tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), - vtotal(config) << NV_HEAD_STATE1_VTOTAL_SHIFT | - htotal(config) << NV_HEAD_STATE1_HTOTAL_SHIFT); - - vsync_end = config->vsync_width - 1; - hsync_end = config->hsync_width - 1; - tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), - vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT | - hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT); - - vblank_end = vsync_end + config->vback_porch; - hblank_end = hsync_end + config->hback_porch; - tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), - vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT | - hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT); - - vblank_start = vblank_end + config->yres; - hblank_start = hblank_end + config->xres; - tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), - vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT | - hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT); - - /* TODO: adding interlace mode support */ - tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); - - tegra_sor_write_field(sor, NV_SOR_CSTM, - NV_SOR_CSTM_ROTCLK_DEFAULT_MASK | - NV_SOR_CSTM_LVDS_EN_ENABLE, - 2 << NV_SOR_CSTM_ROTCLK_SHIFT | - is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE : - NV_SOR_CSTM_LVDS_EN_DISABLE); - - tegra_dc_sor_config_pwm(sor, 1024, 1024); -} - -static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor) -{ - struct tegra_dc *dc = sor->dc; - struct display_controller *disp_ctrl = (void *)dc->base; - - u32 reg_val = READL(&disp_ctrl->cmd.state_access); - - WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); - WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); - - /* Enable DC now - otherwise pure text console may not show. */ - WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); - WRITEL(reg_val, &disp_ctrl->cmd.state_access); -} - -void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor) -{ - const struct tegra_dc_dp_link_config *link_cfg = sor->link_cfg; - - tegra_sor_write_field(sor, NV_SOR_CLK_CNTRL, - NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK, - NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); - - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK, - NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); - udelay(25); - - tegra_sor_write_field(sor, NV_SOR_PLL3, - NV_SOR_PLL3_PLLVDD_MODE_MASK, - NV_SOR_PLL3_PLLVDD_MODE_V3_3); - tegra_sor_writel(sor, NV_SOR_PLL0, - 0xf << NV_SOR_PLL0_ICHPMP_SHFIT | - 0x3 << NV_SOR_PLL0_VCOCAP_SHIFT | - NV_SOR_PLL0_PLLREG_LEVEL_V45 | - NV_SOR_PLL0_RESISTORSEL_EXT | - NV_SOR_PLL0_PWR_ON | NV_SOR_PLL0_VCOPD_RESCIND); - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX1_SEQ_MASK | NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, - NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | - NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE | - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); - tegra_sor_writel(sor, NV_SOR_PLL1, - NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE); - - if (tegra_dc_sor_poll_register(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, - NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, - 100, TEGRA_SOR_TIMEOUT_MS * 1000)) { - printk(BIOS_ERR, "DP failed to lock PLL\n"); - return; - } - - tegra_sor_write_field(sor, NV_SOR_PLL2, - NV_SOR_PLL2_AUX2_MASK | NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK, - NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN | - NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE); - - tegra_dc_sor_power_up(sor, 0); - - /* re-enable SOR clock */ - tegra_sor_enable_edp_clock(sor); /* select pll_dp as clock source */ - - /* Power up lanes */ - tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1); - - tegra_dc_sor_set_dp_mode(sor, link_cfg); - -} - -void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor) -{ - u32 reg_val; - struct display_controller *disp_ctrl = (void *)sor->dc->base; - - tegra_dc_sor_enable_dc(sor); - tegra_dc_sor_config_panel(sor, 0); - - WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl); - WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl); - - WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | - PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, - &disp_ctrl->cmd.disp_pow_ctrl); - - reg_val = tegra_sor_readl(sor, NV_SOR_TEST); - if (reg_val & NV_SOR_TEST_ATTACHED_TRUE) - return; - - tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, - NV_SOR_SUPER_STATE1_ATTACHED_NO); - - /* - * Enable display2sor clock at least 2 cycles before DC start, - * to clear sor internal valid signal. - */ - - /* Stop dc for 3 cycles */ - WRITEL(0, &disp_ctrl->disp.disp_win_opt); - WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); - udelay(FRAME_IN_MS * 1000 * 3); - - /* Attach head */ - tegra_dc_sor_update(sor); - tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, - NV_SOR_SUPER_STATE1_ATTACHED_YES); - tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, - NV_SOR_SUPER_STATE1_ATTACHED_YES | - NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE | - NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL); - tegra_dc_sor_super_update(sor); - - /* wait for another 5 cycles */ - udelay(FRAME_IN_MS * 1000 * 5); - - /* Re-enable dc */ - WRITEL(READ_MUX_ACTIVE | WRITE_MUX_ACTIVE, - &disp_ctrl->cmd.state_access); - WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); - - WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd); - WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); - - if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, - NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, - NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE, - 100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000)) - printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n"); - else - printk(BIOS_INFO, "%s: sor is attached\n", __func__); - -#if DEBUG_SOR - dump_sor_reg(sor); -#endif -} - -void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, - const struct tegra_dc_dp_link_config *link_cfg) -{ - tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), - link_cfg->drive_current); - tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), - link_cfg->preemphasis); - tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum), - link_cfg->postcursor); - tegra_sor_writel(sor, NV_SOR_LVDS, 0); - - tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw); - tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count); - - tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), - NV_SOR_DP_PADCTL_TX_PU_ENABLE | - NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, - NV_SOR_DP_PADCTL_TX_PU_ENABLE | - 2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT); - - /* Precharge */ - tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), - 0xf0, 0xf0); - udelay(20); - - tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), - 0xf0, 0x0); -} - -void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor) -{ - u32 drive_current = 0; - u32 pre_emphasis = 0; - - /* Set to a known-good pre-calibrated setting */ - switch (sor->link_cfg->link_bw) { - case SOR_LINK_SPEED_G1_62: - case SOR_LINK_SPEED_G2_7: - drive_current = 0x13131313; - pre_emphasis = 0; - break; - case SOR_LINK_SPEED_G5_4: - printk(BIOS_WARNING, "T124/T132 does not support 5.4G link" - " clock.\n"); - default: - printk(BIOS_WARNING, "Invalid sor link bandwidth: %d\n", - sor->link_cfg->link_bw); - return; - } - - tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum), - drive_current); - tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis); -} - -void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor) -{ - u32 pad_ctrl = 0; - int err = 0; - - switch (sor->link_cfg->lane_count) { - case 4: - pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO | - NV_SOR_DP_PADCTL_PD_TXD_1_NO | - NV_SOR_DP_PADCTL_PD_TXD_2_NO | - NV_SOR_DP_PADCTL_PD_TXD_3_NO); - break; - case 2: - pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO | - NV_SOR_DP_PADCTL_PD_TXD_1_NO | - NV_SOR_DP_PADCTL_PD_TXD_2_YES | - NV_SOR_DP_PADCTL_PD_TXD_3_YES); - break; - case 1: - pad_ctrl = (NV_SOR_DP_PADCTL_PD_TXD_0_NO | - NV_SOR_DP_PADCTL_PD_TXD_1_YES | - NV_SOR_DP_PADCTL_PD_TXD_2_YES | - NV_SOR_DP_PADCTL_PD_TXD_3_YES); - break; - default: - printk(BIOS_ERR, "Invalid sor lane count: %u\n", - sor->link_cfg->lane_count); - return; - } - - pad_ctrl |= NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN; - tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), pad_ctrl); - - err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); - if (err) { - printk(BIOS_ERR, - "Wait for lane power down failed: %d\n", err); - return; - } -} - -void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) -{ - const struct tegra_dc_dp_link_config *cfg = sor->link_cfg; - u32 val = 0; - - switch (cfg->lane_count) { - case 4: - val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | - NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ - case 2: - val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ - case 1: - val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; - break; - default: - printk(BIOS_ERR, - "dp: invalid lane number %d\n", cfg->lane_count); - return; - } - - tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), - (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), - (val << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT)); - udelay(100); - tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum), - (0xf << NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 0); -} - -static u32 tegra_dc_poll_register(void *reg, - u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) -{ - u32 temp = timeout_us; - u32 reg_val = 0; - - do { - udelay(poll_interval_us); - reg_val = READL(reg); - if (timeout_us > poll_interval_us) - timeout_us -= poll_interval_us; - else - break; - } while ((reg_val & mask) != exp_val); - - if ((reg_val & mask) == exp_val) - return 0; /* success */ - - return temp; -} - -static void tegra_dc_sor_general_act(struct display_controller *disp_ctrl) -{ - WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); - - if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl, - GENERAL_ACT_REQ, 0, 100, - TEGRA_DC_POLL_TIMEOUT_MS*1000)) - printk(BIOS_ERR, - "dc timeout waiting for DC to stop\n"); -} - -static struct tegra_dc_mode min_mode = { - .h_ref_to_sync = 0, - .v_ref_to_sync = 1, - .h_sync_width = 1, - .v_sync_width = 1, - .h_back_porch = 20, - .v_back_porch = 0, - .h_active = 16, - .v_active = 16, - .h_front_porch = 1, - .v_front_porch = 2, -}; - -/* Disable windows and set minimum raster timings */ -static void -tegra_dc_sor_disable_win_short_raster(struct display_controller *disp_ctrl, - int *dc_reg_ctx) -{ - int selected_windows, i; - - selected_windows = READL(&disp_ctrl->cmd.disp_win_header); - - /* Store and clear window options */ - for (i = 0; i < DC_N_WINDOWS; ++i) { - WRITEL(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); - dc_reg_ctx[i] = READL(&disp_ctrl->win.win_opt); - WRITEL(0, &disp_ctrl->win.win_opt); - WRITEL(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); - } - - WRITEL(selected_windows, &disp_ctrl->cmd.disp_win_header); - - /* Store current raster timings and set minimum timings */ - dc_reg_ctx[i++] = READL(&disp_ctrl->disp.ref_to_sync); - WRITEL(min_mode.h_ref_to_sync | (min_mode.v_ref_to_sync << 16), - &disp_ctrl->disp.ref_to_sync); - - dc_reg_ctx[i++] = READL(&disp_ctrl->disp.sync_width); - WRITEL(min_mode.h_sync_width | (min_mode.v_sync_width << 16), - &disp_ctrl->disp.sync_width); - - dc_reg_ctx[i++] = READL(&disp_ctrl->disp.back_porch); - WRITEL(min_mode.h_back_porch | - min_mode.v_back_porch << 16, - &disp_ctrl->disp.back_porch); - - dc_reg_ctx[i++] = READL(&disp_ctrl->disp.front_porch); - WRITEL(min_mode.h_front_porch | - min_mode.v_front_porch << 16, - &disp_ctrl->disp.front_porch); - - dc_reg_ctx[i++] = READL(&disp_ctrl->disp.disp_active); - WRITEL(min_mode.h_active | (min_mode.v_active << 16), - &disp_ctrl->disp.disp_active); - - WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); -} - -/* Restore previous windows status and raster timings */ -static void -tegra_dc_sor_restore_win_and_raster(struct display_controller *disp_ctrl, - int *dc_reg_ctx) -{ - int selected_windows, i; - - selected_windows = READL(&disp_ctrl->cmd.disp_win_header); - - for (i = 0; i < DC_N_WINDOWS; ++i) { - WRITEL(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); - WRITEL(dc_reg_ctx[i], &disp_ctrl->win.win_opt); - WRITEL(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); - } - - WRITEL(selected_windows, &disp_ctrl->cmd.disp_win_header); - - WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync); - WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width); - WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch); - WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch); - WRITEL(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active); - - WRITEL(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl); -} - -static void tegra_dc_sor_enable_sor(struct tegra_dc_sor_data *sor, int enable) -{ - struct display_controller *disp_ctrl = (void *)sor->dc->base; - u32 reg_val = READL(&disp_ctrl->disp.disp_win_opt); - - reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE; - WRITEL(reg_val, &disp_ctrl->disp.disp_win_opt); -} - -void tegra_dc_detach(struct tegra_dc_sor_data *sor) -{ - struct display_controller *disp_ctrl = (void *)sor->dc->base; - int dc_reg_ctx[DC_N_WINDOWS + 5]; - unsigned long dc_int_mask; - - /* Sleep mode */ - tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, - NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP | - NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE | - NV_SOR_SUPER_STATE1_ATTACHED_YES); - tegra_dc_sor_super_update(sor); - - tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx); - - if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST, - NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, - NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP, - 100, TEGRA_SOR_ATTACH_TIMEOUT_MS*1000)) { - printk(BIOS_ERR, - "dc timeout waiting for OPMOD = SLEEP\n"); - } - - tegra_sor_writel(sor, NV_SOR_SUPER_STATE1, - NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP | - NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE | - NV_SOR_SUPER_STATE1_ATTACHED_NO); - - /* Mask DC interrupts during the 2 dummy frames required for detach */ - dc_int_mask = READL(&disp_ctrl->cmd.int_mask); - WRITEL(0, &disp_ctrl->cmd.int_mask); - - /* Stop DC->SOR path */ - tegra_dc_sor_enable_sor(sor, 0); - tegra_dc_sor_general_act(disp_ctrl); - - /* Stop DC */ - WRITEL(DISP_CTRL_MODE_STOP, &disp_ctrl->cmd.disp_cmd); - tegra_dc_sor_general_act(disp_ctrl); - - tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx); - - WRITEL(dc_int_mask, &disp_ctrl->cmd.int_mask); -} diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c deleted file mode 100644 index 8ba44e9c00..0000000000 --- a/src/soc/nvidia/tegra132/spi.c +++ /dev/null @@ -1,915 +0,0 @@ -/* - * NVIDIA Tegra SPI controller (T114 and later) - * - * Copyright (c) 2010-2013 NVIDIA Corporation - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/io.h> -#include <assert.h> -#include <boot_device.h> -#include <cbfs.h> -#include <console/console.h> -#include <delay.h> -#include <inttypes.h> -#include <spi-generic.h> -#include <spi_flash.h> -#include <soc/addressmap.h> -#include <soc/dma.h> -#include <soc/spi.h> -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <symbols.h> -#include <timer.h> - - -#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI -# define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) -#else -# define DEBUG_SPI(x,...) -#endif - -/* - * 64 packets in FIFO mode, BLOCK_SIZE packets in DMA mode. Packets can vary - * in size from 4 to 32 bits. To keep things simple we'll use 8-bit packets. - */ -#define SPI_PACKET_SIZE_BYTES 1 -#define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES) -#define SPI_MAX_TRANSFER_BYTES_DMA (65535 * SPI_PACKET_SIZE_BYTES) - -/* - * This is used to workaround an issue seen where it may take some time for - * packets to show up in the FIFO after they have been received and the - * BLOCK_COUNT has been incremented. - */ -#define SPI_FIFO_XFER_TIMEOUT_US 1000 - -/* COMMAND1 */ -#define SPI_CMD1_GO (1 << 31) -#define SPI_CMD1_M_S (1 << 30) -#define SPI_CMD1_MODE_MASK 0x3 -#define SPI_CMD1_MODE_SHIFT 28 -#define SPI_CMD1_CS_SEL_MASK 0x3 -#define SPI_CMD1_CS_SEL_SHIFT 26 -#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) -#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) -#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) -#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) -#define SPI_CMD1_CS_SW_HW (1 << 21) -#define SPI_CMD1_CS_SW_VAL (1 << 20) -#define SPI_CMD1_IDLE_SDA_MASK 0x3 -#define SPI_CMD1_IDLE_SDA_SHIFT 18 -#define SPI_CMD1_BIDIR (1 << 17) -#define SPI_CMD1_LSBI_FE (1 << 16) -#define SPI_CMD1_LSBY_FE (1 << 15) -#define SPI_CMD1_BOTH_EN_BIT (1 << 14) -#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) -#define SPI_CMD1_RX_EN (1 << 12) -#define SPI_CMD1_TX_EN (1 << 11) -#define SPI_CMD1_PACKED (1 << 5) -#define SPI_CMD1_BIT_LEN_MASK 0x1f -#define SPI_CMD1_BIT_LEN_SHIFT 0 - -/* COMMAND2 */ -#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) -#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) -#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) -#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) - -/* SPI_TRANS_STATUS */ -#define SPI_STATUS_RDY (1 << 30) -#define SPI_STATUS_SLV_IDLE_COUNT_MASK 0xff -#define SPI_STATUS_SLV_IDLE_COUNT_SHIFT 16 -#define SPI_STATUS_BLOCK_COUNT 0xffff -#define SPI_STATUS_BLOCK_COUNT_SHIFT 0 - -/* SPI_FIFO_STATUS */ -#define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31) -#define SPI_FIFO_STATUS_FRAME_END (1 << 30) -#define SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_MASK 0x7f -#define SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_SHIFT 23 -#define SPI_FIFO_STATUS_TX_FIFO_EMPTY_COUNT_MASK 0x7f -#define SPI_FIFO_STATUS_TX_FIFO_EMPTY_COUNT_SHIFT 16 -#define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15) -#define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14) -#define SPI_FIFO_STATUS_ERR (1 << 8) -#define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7) -#define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6) -#define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5) -#define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4) -#define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3) -#define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2) -#define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1) -#define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0) - -/* SPI_DMA_CTL */ -#define SPI_DMA_CTL_DMA (1 << 31) -#define SPI_DMA_CTL_CONT (1 << 30) -#define SPI_DMA_CTL_IE_RX (1 << 29) -#define SPI_DMA_CTL_IE_TX (1 << 28) -#define SPI_DMA_CTL_RX_TRIG_MASK 0x3 -#define SPI_DMA_CTL_RX_TRIG_SHIFT 19 -#define SPI_DMA_CTL_TX_TRIG_MASK 0x3 -#define SPI_DMA_CTL_TX_TRIG_SHIFT 15 - -/* SPI_DMA_BLK */ -#define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xffff -#define SPI_DMA_CTL_BLOCK_SIZE_SHIFT 0 - -static struct tegra_spi_channel tegra_spi_channels[] = { - /* - * Note: Tegra pinmux must be setup for corresponding SPI channel in - * order for its registers to be accessible. If pinmux has not been - * set up, access to the channel's registers will simply hang. - * - * TODO(dhendrix): Clarify or remove this comment (is clock setup - * necessary first, or just pinmux, or both?) - */ - { - .slave = { .bus = 1, }, - .regs = (struct tegra_spi_regs *)TEGRA_SPI1_BASE, - .req_sel = APBDMA_SLAVE_SL2B1, - }, - { - .slave = { .bus = 2, }, - .regs = (struct tegra_spi_regs *)TEGRA_SPI2_BASE, - .req_sel = APBDMA_SLAVE_SL2B2, - }, - { - .slave = { .bus = 3, }, - .regs = (struct tegra_spi_regs *)TEGRA_SPI3_BASE, - .req_sel = APBDMA_SLAVE_SL2B3, - }, - { - .slave = { .bus = 4, }, - .regs = (struct tegra_spi_regs *)TEGRA_SPI4_BASE, - .req_sel = APBDMA_SLAVE_SL2B4, - }, - { - .slave = { .bus = 5, }, - .regs = (struct tegra_spi_regs *)TEGRA_SPI5_BASE, - .req_sel = APBDMA_SLAVE_SL2B5, - }, - { - .slave = { .bus = 6, }, - .regs = (struct tegra_spi_regs *)TEGRA_SPI6_BASE, - .req_sel = APBDMA_SLAVE_SL2B6, - }, -}; - -enum spi_direction { - SPI_SEND, - SPI_RECEIVE, -}; - -struct tegra_spi_channel *tegra_spi_init(unsigned int bus) -{ - int i; - struct tegra_spi_channel *spi = NULL; - - for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) { - if (tegra_spi_channels[i].slave.bus == bus) { - spi = &tegra_spi_channels[i]; - break; - } - } - if (!spi) - return NULL; - - /* software drives chip-select, set value to high */ - setbits_le32(&spi->regs->command1, - SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); - - /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&spi->regs->command1, - SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); - - return spi; -} - -static struct tegra_spi_channel * const to_tegra_spi(int bus) { - return &tegra_spi_channels[bus - 1]; -} - -static unsigned int tegra_spi_speed(unsigned int bus) -{ - /* FIXME: implement this properly, for now use max value (50MHz) */ - return 50000000; -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; - u32 val; - - tegra_spi_init(slave->bus); - - val = read32(®s->command1); - - /* select appropriate chip-select line */ - val &= ~(SPI_CMD1_CS_SEL_MASK << SPI_CMD1_CS_SEL_SHIFT); - val |= (slave->cs << SPI_CMD1_CS_SEL_SHIFT); - - /* drive chip-select with the inverse of the "inactive" value */ - if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) - val &= ~SPI_CMD1_CS_SW_VAL; - else - val |= SPI_CMD1_CS_SW_VAL; - - write32(®s->command1, val); - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; - u32 val; - - val = read32(®s->command1); - - if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) - val |= SPI_CMD1_CS_SW_VAL; - else - val &= ~SPI_CMD1_CS_SW_VAL; - - write32(®s->command1, val); -} - -static void dump_fifo_status(struct tegra_spi_channel *spi) -{ - u32 status = read32(&spi->regs->fifo_status); - - printk(BIOS_INFO, "Raw FIFO status: 0x%08x\n", status); - if (status & SPI_FIFO_STATUS_TX_FIFO_OVF) - printk(BIOS_INFO, "\tTx overflow detected\n"); - if (status & SPI_FIFO_STATUS_TX_FIFO_UNR) - printk(BIOS_INFO, "\tTx underrun detected\n"); - if (status & SPI_FIFO_STATUS_RX_FIFO_OVF) - printk(BIOS_INFO, "\tRx overflow detected\n"); - if (status & SPI_FIFO_STATUS_RX_FIFO_UNR) - printk(BIOS_INFO, "\tRx underrun detected\n"); - - printk(BIOS_INFO, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n", - read32(&spi->regs->tx_fifo), read32(&spi->regs->tx_data)); - printk(BIOS_INFO, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n", - read32(&spi->regs->rx_fifo), read32(&spi->regs->rx_data)); -} - -static void clear_fifo_status(struct tegra_spi_channel *spi) -{ - clrbits_le32(&spi->regs->fifo_status, - SPI_FIFO_STATUS_ERR | - SPI_FIFO_STATUS_TX_FIFO_OVF | - SPI_FIFO_STATUS_TX_FIFO_UNR | - SPI_FIFO_STATUS_RX_FIFO_OVF | - SPI_FIFO_STATUS_RX_FIFO_UNR); -} - -static void dump_spi_regs(struct tegra_spi_channel *spi) -{ - printk(BIOS_INFO, "SPI regs:\n" - "\tdma_blk: 0x%08x\n" - "\tcommand1: 0x%08x\n" - "\tdma_ctl: 0x%08x\n" - "\ttrans_status: 0x%08x\n", - read32(&spi->regs->dma_blk), - read32(&spi->regs->command1), - read32(&spi->regs->dma_ctl), - read32(&spi->regs->trans_status)); -} - -static void dump_dma_regs(struct apb_dma_channel *dma) -{ - printk(BIOS_INFO, "DMA regs:\n" - "\tahb_ptr: 0x%08x\n" - "\tapb_ptr: 0x%08x\n" - "\tahb_seq: 0x%08x\n" - "\tapb_seq: 0x%08x\n" - "\tcsr: 0x%08x\n" - "\tcsre: 0x%08x\n" - "\twcount: 0x%08x\n" - "\tdma_byte_sta: 0x%08x\n" - "\tword_transfer: 0x%08x\n", - read32(&dma->regs->ahb_ptr), - read32(&dma->regs->apb_ptr), - read32(&dma->regs->ahb_seq), - read32(&dma->regs->apb_seq), - read32(&dma->regs->csr), - read32(&dma->regs->csre), - read32(&dma->regs->wcount), - read32(&dma->regs->dma_byte_sta), - read32(&dma->regs->word_transfer)); -} - -static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) -{ - /* FIXME: Make this take total packet size into account */ - return read32(&spi->regs->trans_status) & - (SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT); -} - -/* - * This calls udelay() with a calculated value based on the SPI speed and - * number of bytes remaining to be transferred. It assumes that if the - * calculated delay period is less than MIN_DELAY_US then it is probably - * not worth the overhead of yielding. - */ -#define MIN_DELAY_US 250 -static void spi_delay(struct tegra_spi_channel *spi, - unsigned int bytes_remaining) -{ - unsigned int ns_per_byte, delay_us; - - ns_per_byte = 1000000000 / (tegra_spi_speed(spi->slave.bus) / 8); - delay_us = (ns_per_byte * bytes_remaining) / 1000; - - if (delay_us < MIN_DELAY_US) - return; - - udelay(delay_us); -} - -static void tegra_spi_wait(struct tegra_spi_channel *spi) -{ - unsigned int count, dma_blk; - - dma_blk = 1 + (read32(&spi->regs->dma_blk) & - (SPI_DMA_CTL_BLOCK_SIZE_MASK << SPI_DMA_CTL_BLOCK_SIZE_SHIFT)); - - while ((count = spi_byte_count(spi)) != dma_blk) - spi_delay(spi, dma_blk - count); -} - - -static int fifo_error(struct tegra_spi_channel *spi) -{ - return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; -} - -static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, - unsigned int bytes, enum spi_direction dir) -{ - u8 *p = spi->out_buf; - unsigned int todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_FIFO); - u32 flush_mask, enable_mask; - - if (dir == SPI_SEND) { - flush_mask = SPI_FIFO_STATUS_TX_FIFO_FLUSH; - enable_mask = SPI_CMD1_TX_EN; - } else { - flush_mask = SPI_FIFO_STATUS_RX_FIFO_FLUSH; - enable_mask = SPI_CMD1_RX_EN; - } - - setbits_le32(&spi->regs->fifo_status, flush_mask); - while (read32(&spi->regs->fifo_status) & flush_mask) - ; - - setbits_le32(&spi->regs->command1, enable_mask); - - /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and - * PIO transfers */ - write32(&spi->regs->dma_blk, todo - 1); - - if (dir == SPI_SEND) { - unsigned int to_fifo = bytes; - while (to_fifo) { - write32(&spi->regs->tx_fifo, *p); - p++; - to_fifo--; - } - } - - return todo; -} - -static void tegra_spi_pio_start(struct tegra_spi_channel *spi) -{ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); - /* Make sure the write to command1 completes. */ - read32(&spi->regs->command1); -} - -static inline u32 rx_fifo_count(struct tegra_spi_channel *spi) -{ - return (read32(&spi->regs->fifo_status) >> - SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_SHIFT) & - SPI_FIFO_STATUS_RX_FIFO_FULL_COUNT_MASK; -} - -static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) -{ - u8 *p = spi->in_buf; - struct stopwatch sw; - - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); - - /* - * Allow some time in case the Rx FIFO does not yet have - * all packets pushed into it. See chrome-os-partner:24215. - */ - stopwatch_init_usecs_expire(&sw, SPI_FIFO_XFER_TIMEOUT_US); - do { - if (rx_fifo_count(spi) == spi_byte_count(spi)) - break; - } while (!stopwatch_expired(&sw)); - - while (!(read32(&spi->regs->fifo_status) & - SPI_FIFO_STATUS_RX_FIFO_EMPTY)) { - *p = read8(&spi->regs->rx_fifo); - p++; - } - - if (fifo_error(spi)) { - printk(BIOS_ERR, "%s: ERROR:\n", __func__); - dump_spi_regs(spi); - dump_fifo_status(spi); - return -1; - } - - return 0; -} - -static void setup_dma_params(struct tegra_spi_channel *spi, - struct apb_dma_channel *dma) -{ - /* APB bus width = 8-bits, address wrap for each word */ - clrbits_le32(&dma->regs->apb_seq, - APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); - /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), - * no address wrapping */ - clrsetbits_le32(&dma->regs->ahb_seq, - (AHB_BURST_MASK << AHB_BURST_SHIFT), - 4 << AHB_BURST_SHIFT); - - /* Set ONCE mode to transfer one "block" at a time (64KB) and enable - * flow control. */ - clrbits_le32(&dma->regs->csr, - APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); - setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | - (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); -} - -static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, - unsigned int bytes, enum spi_direction dir) -{ - unsigned int todo, wcount; - - /* - * For DMA we need to think of things in terms of word count. - * AHB width is fixed at 32-bits. To avoid overrunning - * the in/out buffers we must align down. (Note: lowest 2-bits - * in WCOUNT register are ignored, and WCOUNT seems to count - * words starting at n-1) - * - * Example: If "bytes" is 7 and we are transferring 1-byte at a time, - * WCOUNT should be 4. The remaining 3 bytes must be transferred - * using PIO. - */ - todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_DMA - TEGRA_DMA_ALIGN_BYTES); - todo = ALIGN_DOWN(todo, TEGRA_DMA_ALIGN_BYTES); - wcount = ALIGN_DOWN(todo - TEGRA_DMA_ALIGN_BYTES, TEGRA_DMA_ALIGN_BYTES); - - if (dir == SPI_SEND) { - spi->dma_out = dma_claim(); - if (!spi->dma_out) - return -1; - - /* ensure bytes to send will be visible to DMA controller */ - dcache_clean_by_mva(spi->out_buf, bytes); - - write32(&spi->dma_out->regs->apb_ptr, - (uintptr_t)&spi->regs->tx_fifo); - write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); - setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); - setup_dma_params(spi, spi->dma_out); - write32(&spi->dma_out->regs->wcount, wcount); - } else { - spi->dma_in = dma_claim(); - if (!spi->dma_in) - return -1; - - /* avoid data collisions */ - dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - - write32(&spi->dma_in->regs->apb_ptr, - (uintptr_t)&spi->regs->rx_fifo); - write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf); - clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); - setup_dma_params(spi, spi->dma_in); - write32(&spi->dma_in->regs->wcount, wcount); - } - - /* BLOCK_SIZE starts at n-1 */ - write32(&spi->regs->dma_blk, todo - 1); - return todo; -} - -static void tegra_spi_dma_start(struct tegra_spi_channel *spi) -{ - /* - * The RDY bit in SPI_TRANS_STATUS needs to be cleared manually - * (set bit to clear) between each transaction. Otherwise the next - * transaction does not start. - */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - - /* - * The DMA triggers have units of packets. As each packet is currently - * 1 byte the triggers need to be set to 4 packets (0b01) to match - * the AHB 32-bit (4 byte) tranfser. Otherwise the FIFO errors can - * occur. - */ - if (spi->dma_out) { - clrsetbits_le32(&spi->regs->dma_ctl, - SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT, - 1 << SPI_DMA_CTL_TX_TRIG_SHIFT); - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); - } - if (spi->dma_in) { - clrsetbits_le32(&spi->regs->dma_ctl, - SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT, - 1 << SPI_DMA_CTL_RX_TRIG_SHIFT); - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); - } - - /* - * To avoid underrun conditions, enable APB DMA before SPI DMA for - * Tx and enable SPI DMA before APB DMA before Rx. - */ - if (spi->dma_out) - dma_start(spi->dma_out); - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); - if (spi->dma_in) - dma_start(spi->dma_in); - - -} - -static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) -{ - int ret; - unsigned int todo; - - todo = read32(&spi->dma_in->regs->wcount); - - if (spi->dma_in) { - while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || - dma_busy(spi->dma_in)) - ; /* this shouldn't take long, no udelay */ - dma_stop(spi->dma_in); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); - dma_release(spi->dma_in); - } - - if (spi->dma_out) { - while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || - dma_busy(spi->dma_out)) - spi_delay(spi, todo - spi_byte_count(spi)); - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); - dma_stop(spi->dma_out); - dma_release(spi->dma_out); - } - - if (fifo_error(spi)) { - printk(BIOS_ERR, "%s: ERROR:\n", __func__); - dump_dma_regs(spi->dma_out); - dump_dma_regs(spi->dma_in); - dump_spi_regs(spi); - dump_fifo_status(spi); - ret = -1; - goto done; - } - - ret = 0; -done: - spi->dma_in = NULL; - spi->dma_out = NULL; - return ret; -} - -/* - * xfer_setup() prepares a transfer. It does sanity checking, alignment, and - * sets transfer mode used by this channel (if not set already). - * - * A few caveats to watch out for: - * - The number of bytes which can be transferred may be smaller than the - * number of bytes the caller specifies. The number of bytes ready for - * a transfer will be returned (unless an error occurs). - * - * - Only one mode can be used for both RX and TX. The transfer mode of the - * SPI channel (spi->xfer_mode) is checked each time this function is called. - * If conflicting modes are detected, spi->xfer_mode will be set to - * XFER_MODE_NONE and an error will be returned. - * - * Returns bytes ready for transfer if successful, <0 to indicate error. - */ -static int xfer_setup(struct tegra_spi_channel *spi, void *buf, - unsigned int bytes, enum spi_direction dir) -{ - unsigned int line_size = dcache_line_bytes(); - unsigned int align; - int ret = -1; - - if (!bytes) - return 0; - - if (dir == SPI_SEND) - spi->out_buf = buf; - else if (dir == SPI_RECEIVE) - spi->in_buf = buf; - - /* - * Alignment consideratons: - * When we enable caching we'll need to clean/invalidate portions of - * memory. So we need to be careful about memory alignment. Also, DMA - * likes to operate on 4-bytes at a time on the AHB side. So for - * example, if we only want to receive 1 byte, 4 bytes will be be - * written in memory even if those extra 3 bytes are beyond the length - * we want. - * - * For now we'll use PIO to send/receive unaligned bytes. We may - * consider setting aside some space for a kind of bounce buffer to - * stay in DMA mode once we have a chance to benchmark the two - * approaches. - */ - - if (bytes < line_size) { - if (spi->xfer_mode == XFER_MODE_DMA) { - spi->xfer_mode = XFER_MODE_NONE; - ret = -1; - } else { - spi->xfer_mode = XFER_MODE_PIO; - ret = tegra_spi_pio_prepare(spi, bytes, dir); - } - goto done; - } - - /* transfer bytes before the aligned boundary */ - align = line_size - ((uintptr_t)buf % line_size); - if ((align != 0) && (align != line_size)) { - if (spi->xfer_mode == XFER_MODE_DMA) { - spi->xfer_mode = XFER_MODE_NONE; - ret = -1; - } else { - spi->xfer_mode = XFER_MODE_PIO; - ret = tegra_spi_pio_prepare(spi, align, dir); - } - goto done; - } - - /* do aligned DMA transfer */ - align = (((uintptr_t)buf + bytes) % line_size); - if (bytes - align > 0) { - unsigned int dma_bytes = bytes - align; - - if (spi->xfer_mode == XFER_MODE_PIO) { - spi->xfer_mode = XFER_MODE_NONE; - ret = -1; - } else { - spi->xfer_mode = XFER_MODE_DMA; - ret = tegra_spi_dma_prepare(spi, dma_bytes, dir); - } - - goto done; - } - - /* transfer any remaining unaligned bytes */ - if (align) { - if (spi->xfer_mode == XFER_MODE_DMA) { - spi->xfer_mode = XFER_MODE_NONE; - ret = -1; - } else { - spi->xfer_mode = XFER_MODE_PIO; - ret = tegra_spi_pio_prepare(spi, align, dir); - } - goto done; - } - -done: - return ret; -} - -static void xfer_start(struct tegra_spi_channel *spi) -{ - if (spi->xfer_mode == XFER_MODE_DMA) - tegra_spi_dma_start(spi); - else - tegra_spi_pio_start(spi); -} - -static void xfer_wait(struct tegra_spi_channel *spi) -{ - tegra_spi_wait(spi); -} - -static int xfer_finish(struct tegra_spi_channel *spi) -{ - int ret; - - if (spi->xfer_mode == XFER_MODE_DMA) - ret = tegra_spi_dma_finish(spi); - else - ret = tegra_spi_pio_finish(spi); - - spi->xfer_mode = XFER_MODE_NONE; - return ret; -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return buf_len; -} - -int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int out_bytes, void *din, unsigned int in_bytes) -{ - struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); - u8 *out_buf = (u8 *)dout; - u8 *in_buf = (u8 *)din; - unsigned int todo; - int ret = 0; - - /* tegra bus numbers start at 1 */ - ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels)); - - while (out_bytes || in_bytes) { - int x = 0; - - if (out_bytes == 0) - todo = in_bytes; - else if (in_bytes == 0) - todo = out_bytes; - else - todo = MIN(out_bytes, in_bytes); - - if (out_bytes) { - x = xfer_setup(spi, out_buf, todo, SPI_SEND); - if (x < 0) { - if (spi->xfer_mode == XFER_MODE_NONE) { - spi->xfer_mode = XFER_MODE_PIO; - continue; - } else { - ret = -1; - break; - } - } - } - if (in_bytes) { - x = xfer_setup(spi, in_buf, todo, SPI_RECEIVE); - if (x < 0) { - if (spi->xfer_mode == XFER_MODE_NONE) { - spi->xfer_mode = XFER_MODE_PIO; - continue; - } else { - ret = -1; - break; - } - } - } - - /* - * Note: Some devices (such as Chrome EC) are sensitive to - * delays, so be careful when adding debug prints not to - * cause timeouts between transfers. - */ - xfer_start(spi); - xfer_wait(spi); - if (xfer_finish(spi)) { - ret = -1; - break; - } - - /* Post-processing. */ - if (out_bytes) { - out_bytes -= x; - out_buf += x; - } - if (in_bytes) { - in_bytes -= x; - in_buf += x; - } - } - - if (ret < 0) { - printk(BIOS_ERR, "%s: Error detected\n", __func__); - printk(BIOS_ERR, "Transaction size: %u, bytes remaining: " - "%u out / %u in\n", todo, out_bytes, in_bytes); - clear_fifo_status(spi); - } - return ret; -} - -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -#define JEDEC_FAST_READ_DUAL 0x3b -#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05 - -static struct spi_slave *boot_slave; - -static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest, - size_t offset, size_t count) -{ - u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE]; - unsigned int read_cmd_bytes; - int ret = count; - struct tegra_spi_channel *channel; - - channel = to_tegra_spi(boot_slave->bus); - - if (channel->dual_mode) { - /* - * Command 0x3b will interleave data only, command 0xbb will - * interleave the address as well. It's nice to see the address - * plainly when debugging, and we're mostly concerned with - * large transfers so the optimization of using 0xbb isn't - * really worthwhile. - */ - spi_read_cmd[0] = JEDEC_FAST_READ_DUAL; - spi_read_cmd[4] = 0x00; /* dummy byte */ - read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE; - } else { - spi_read_cmd[0] = JEDEC_READ; - read_cmd_bytes = JEDEC_READ_OUTSIZE; - } - spi_read_cmd[1] = (offset >> 16) & 0xff; - spi_read_cmd[2] = (offset >> 8) & 0xff; - spi_read_cmd[3] = offset & 0xff; - - spi_claim_bus(boot_slave); - - if (spi_xfer(boot_slave, spi_read_cmd, - read_cmd_bytes, NULL, 0) < 0) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %zu bytes\n", - __func__, sizeof(spi_read_cmd)); - goto tegra_spi_cbfs_read_exit; - } - - if (channel->dual_mode) { - setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - } - if (spi_xfer(boot_slave, NULL, 0, dest, count)) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %zu bytes\n", - __func__, count); - } - if (channel->dual_mode) - clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - -tegra_spi_cbfs_read_exit: - /* de-assert /CS */ - spi_release_bus(boot_slave); - return ret; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) -{ - struct tegra_spi_channel *channel = to_tegra_spi(bus); - if (!channel) - return NULL; - - return &channel->slave; -} - -static const struct region_device_ops tegra_spi_ops = { - .mmap = mmap_helper_rdev_mmap, - .munmap = mmap_helper_rdev_munmap, - .readat = tegra_spi_readat, -}; - -static struct mmap_helper_region_device mdev = - MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} - -void boot_device_init(void) -{ - struct tegra_spi_channel *boot_chan; - - boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1]; - boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT; - -#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1 - boot_chan->dual_mode = 1; -#endif - boot_slave = &boot_chan->slave; - - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); -} diff --git a/src/soc/nvidia/tegra132/stack.S b/src/soc/nvidia/tegra132/stack.S deleted file mode 100644 index acab70c9ec..0000000000 --- a/src/soc/nvidia/tegra132/stack.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Macro to initialize stack, perform seeding if required and finally call the - * function provided - * @stack_top : First address above the stack - * @stack_bottom : Lowest address on the stack - * @seed : Stack seeding required (1=yes/otherwise=no) - * @func : Function to call after initializing stack - */ -.macro stack_init stack_top, stack_bottom, seed, func - /* Check if stack seeding is required */ - mov r0, #\seed - cmp r0, #1 - bne call_func - /* Stack seeding */ - ldr r0, =\stack_bottom - ldr r1, =\stack_top - ldr r2, =0xdeadbeef -init_stack_loop: - str r2, [r0] - add r0, #4 - cmp r0, r1 - bne init_stack_loop - -call_func: - ldr sp, =\stack_top /* Set up stack pointer */ - bl \func -.endm diff --git a/src/soc/nvidia/tegra132/stage_entry.S b/src/soc/nvidia/tegra132/stage_entry.S deleted file mode 100644 index de89f9514f..0000000000 --- a/src/soc/nvidia/tegra132/stage_entry.S +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/asm.h> - -ENTRY(stage_entry) - /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ - bl arm64_init_cpu - - /* Jump to Tegra-specific C entry point. */ - bl ramstage_entry -ENDPROC(stage_entry) diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c deleted file mode 100644 index a530e2dfa4..0000000000 --- a/src/soc/nvidia/tegra132/uart.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <console/console.h> /* for __console definition */ -#include <console/uart.h> -#include <drivers/uart/uart8250reg.h> -#include <stdint.h> - -/* - * TODO: Use DRIVERS_UART_8250MEM driver instead. - * There is an issue in the IO call functions where x86 and ARM - * ordering is reversed. This 8250MEM driver uses the x86 convention. - * This driver can be replaced once the IO calls are sorted. - */ -struct tegra132_uart { - union { - uint32_t thr; // Transmit holding register. - uint32_t rbr; // Receive buffer register. - uint32_t dll; // Divisor latch lsb. - }; - union { - uint32_t ier; // Interrupt enable register. - uint32_t dlm; // Divisor latch msb. - }; - union { - uint32_t iir; // Interrupt identification register. - uint32_t fcr; // FIFO control register. - }; - uint32_t lcr; // Line control register. - uint32_t mcr; // Modem control register. - uint32_t lsr; // Line status register. - uint32_t msr; // Modem status register. -} __attribute__ ((packed)); - -static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr); -static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr); - -static void tegra132_uart_init(struct tegra132_uart *uart_ptr) -{ - const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 - - uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(), - uart_platform_refclk(), 16); - - tegra132_uart_tx_flush(uart_ptr); - - // Disable interrupts. - write8(&uart_ptr->ier, 0); - // Force DTR and RTS to high. - write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); - // Set line configuration, access divisor latches. - write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); - // Set the divisor. - write8(&uart_ptr->dll, divisor & 0xff); - write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); - // Hide the divisor latches. - write8(&uart_ptr->lcr, line_config); - // Enable FIFOs, and clear receive and transmit. - write8(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | - UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); -} - -static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) -{ - if (!tegra132_uart_tst_byte(uart_ptr)) - return 0; - return read8(&uart_ptr->rbr); -} - -static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data) -{ - while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - write8(&uart_ptr->thr, data); -} - -static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr) -{ - while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT)); -} - -static int tegra132_uart_tst_byte(struct tegra132_uart *uart_ptr) -{ - return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; -} - -/* FIXME: Add mainboard override */ -unsigned int uart_platform_refclk(void) -{ - return 408000000; -} - -uintptr_t uart_platform_base(int idx) -{ - /* Default to UART A */ - unsigned int base = 0x70006000; - /* UARTs A - E are mapped as index 0 - 4 */ - if ((idx < 5) && (idx >= 0)) { - if (idx != 1) { /* Not UART B */ - base += idx * 0x100; - } else { - base += 0x40; - } - } - return base; -} - -void uart_init(int idx) -{ - struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); - tegra132_uart_init(uart_ptr); -} - -unsigned char uart_rx_byte(int idx) -{ - struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); - return tegra132_uart_rx_byte(uart_ptr); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); - tegra132_uart_tx_byte(uart_ptr, data); -} - -void uart_tx_flush(int idx) -{ - struct tegra132_uart *uart_ptr = uart_platform_baseptr(idx); - tegra132_uart_tx_flush(uart_ptr); -} - -#if ENV_RAMSTAGE -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = default_baudrate(); - serial.regwidth = 4; - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} -#endif |