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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-01-25 21:08:42 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-06 19:25:57 +0100 |
| commit | a4d784eeab964a9cdb8e453ae98a14520ce13919 (patch) | |
| tree | db4291e48c59896040d4523da3997dde68adff82 | |
| parent | da8fcf0afeb08d288171bda4022c25c3e5a6ecc4 (diff) | |
| download | coreboot-a4d784eeab964a9cdb8e453ae98a14520ce13919.tar.xz | |
include/types.h: Provide BIT() macro
This macro is controversial for arches where the bits are numbered
MSb first, though we don't support such an arch. We've seen this macro
creep into our tree in different places, so provide it in one place.
Change-Id: I86cd8a16420f34ef31b615aec4e0f7bd3191ca35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8280
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
| -rw-r--r-- | src/include/types.h | 7 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra/dc.h | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/clock.c | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/clock.h | 1 |
4 files changed, 8 insertions, 2 deletions
diff --git a/src/include/types.h b/src/include/types.h index ef5edc1781..24ebfafc54 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -22,6 +22,13 @@ #include <stdint.h> #include <stddef.h> +/* + * This may mean something else on architectures where the bits are numbered + * from the MSB (e.g. PowerPC), but until we cross that bridge, this macro is + * perfectly fine. + */ +#define BIT(x) (1ul << (x)) + /** * Coreboot error codes * diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index c0b1986c4f..ff36a0b589 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -367,7 +367,6 @@ struct display_controller { }; check_member(display_controller, winbuf, 0x800 * 4); -#define BIT(pos) (1U << pos) /* DC_CMD_DISPLAY_COMMAND 0x032 */ #define DISP_COMMAND_RAISE (1 << 0) diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 88056d4923..ee2ed64ffb 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -3,6 +3,7 @@ */ #include <delay.h> +#include <types.h> #include <clock.h> /** diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h index 98f6661e02..d9e783479c 100644 --- a/src/soc/qualcomm/ipq806x/include/clock.h +++ b/src/soc/qualcomm/ipq806x/include/clock.h @@ -40,7 +40,6 @@ /* UART specific definitions */ -#define BIT(s) (1<<s) #define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) #define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) #define Uart_mnd_en_mask BIT(8) * !!(625) |