diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2015-09-08 16:00:46 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-17 14:16:58 +0000 |
| commit | b090a268a2e993fc7fa719ab3b9b7283034c9d10 (patch) | |
| tree | d0e4fc4818f6db1b648976ba509f0236ef303ab9 | |
| parent | 914a21ed9ceb403b178c30bedbc354e816b98e92 (diff) | |
| download | coreboot-b090a268a2e993fc7fa719ab3b9b7283034c9d10.tar.xz | |
intel/skylake: Create "RtcLock" Silicon UPD from coreboot
FSP should not lock CMOS unconditionally. coreboot sends Silicon
UPD parameter "RtcLock" to FSP to take action on CMOS
region locking/un-locking. This patch has CB generic code for
creating the Silicon UPD paramater.
BUG=chrome-os-partner:44484
BRANCH=none
TEST=Build and booted in kunimitsu, tested using below command-
When DIsabled RtcLock from devicetree in coreboot, booted to kernel
and run following commands -
>> crossystem fw_result=success
>> crossystem | grep fw_result
It should reflect the value that is set. Here, success.
If ENabled RtcLock from Coreboot devicetree, The same commands will
fail to update the fw_result status from crossystem utility.
CQ-DEPEND=CL:*229144
Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b
Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297980
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11655
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index afb0ff6b70..fd959b2807 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -94,6 +94,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->DspEnable = config->DspEnable; params->XdciEnable = config->XdciEnable; params->Device4Enable = config->Device4Enable; + params->RtcLock = config->RtcLock; /* Show SPI controller if enabled in devicetree.cb */ dev = dev_find_slot(0, PCH_DEVFN_SPI); @@ -265,6 +266,8 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, params->HsioMessaging); soc_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, params->Heci3Enabled); + soc_display_upd_value("RtcLock", 1, original->RtcLock, + params->RtcLock); } static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 94aa3a4ea9..95f9502f13 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -229,6 +229,7 @@ struct soc_intel_skylake_config { u32 LogoSize; u32 GraphicsConfigPtr; u8 Device4Enable; + u8 RtcLock; }; typedef struct soc_intel_skylake_config config_t; |