* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

  to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
  and drop it from the individual romstage.c files.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>

 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

49 files changed, 33 insertions, 174 deletions

diff --git a/src/console/console.c b/src/console/console.c
index 4f11fbecf8..3178562bb3 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -95,6 +95,10 @@ int console_tst_byte(void)
 
 void console_init(void)
 {
+#if CONFIG_USBDEBUG
+	enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
+	early_usbdebug_init();
+#endif
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index aba31fcb3c..7905401336 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -110,12 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb800_lpc_init();
 
 	uart_init();
-#if CONFIG_USBDEBUG
-	sb800_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index ab43f46bd0..ba9716a318 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -94,11 +94,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 41fa2071ae..e46d4bcdb6 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -93,11 +93,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 7bc96c8f43..a304031457 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 08cf32775e..6627d747e2 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -91,11 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * and it doesn't require any special setup. */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	post_code(0x03);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index fc9d611bba..ce24f03f71 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -105,13 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index ce79e0d204..25822d9e56 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -160,11 +160,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index eaa9edaace..66a2b9ff1c 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -123,10 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_mb_resource_map();
 	uart_init();
 	report_bist_failure(bist);
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 56204fb230..68caa0120b 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 56204fb230..68caa0120b 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 83cd91e72e..db20b832d8 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -288,10 +288,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index da6eb7701e..18187950ae 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -147,10 +147,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
         console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 749b1d9a78..855d755872 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -150,10 +150,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
         console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index d80df62b4e..f0585dbbb0 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -102,11 +102,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_disable_reboot();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 	printk(BIOS_DEBUG, "\n");
 
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 77e73b8c75..694440fbeb 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -106,13 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8718f_disable_reboot();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index e248a27d00..5cd1fe571c 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -239,11 +239,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 18fde1c7b5..772ee8a437 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -107,13 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 6dfc1444bd..748cce7812 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -200,11 +200,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 05b0e8b40a..3fd3972559 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -112,13 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 2cf73e651c..2fdcb74f21 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -337,11 +337,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index fc792e6ad8..16a077f8f2 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -96,11 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 85b2241df6..99540c9214 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -242,11 +242,6 @@ void main(unsigned long bist)
 		uart_init();
 	}
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 7fae43d720..a9eb2736aa 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -139,10 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_mb_resource_map();
 	uart_init();
 	report_bist_failure(bist); /* Halt upon BIST failure. */
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 16baac29a5..d6101a734f 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 3929bf4ea8..62ebfb8087 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -140,10 +140,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 07976998c8..ec8c4996d4 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -272,11 +272,6 @@ void main(unsigned long bist)
 	/* Set up the console */
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	i82801gx_enable_usbdebug(1);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index da0ab06a1a..f34f8342ad 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -125,12 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb7xx_51xx_disable_wideio(0);
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 1106f7caf9..4af8f6ad5d 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -100,11 +100,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 1cead6ca63..0953d4c326 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -95,11 +95,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	it8712f_kill_watchdog();
 	uart_init();
 
-#if CONFIG_USBDEBUG
-	sb600_enable_usbdebug(0);
-	early_usbdebug_init();
-#endif
-
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index f6116f978b..eae4428c49 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -136,10 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
 	console_init();
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index ed3ee8b4b4..3699d09777 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -138,16 +138,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-#if CONFIG_USBDEBUG
-	mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-	early_usbdebug_init();
-#endif
-
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index c32318c102..9b164b3758 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -36,6 +36,10 @@ config EHCI_DEBUG_OFFSET
 	hex
 	default 0xe0
 
+config USBDEBUG_DEFAULT_PORT
+	int
+	default 0
+
 choice
 	prompt "SATA Mode"
 	default SATA_MODE_IDE
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index b4d97b0da2..3671686cb2 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
 	/* TODO: Allow changing the physical USB port used as Debug Port. */
 }
 
-void sb600_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
 
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 0ba107acc7..97a7ad2638 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -40,5 +40,5 @@ void sb600_enable(device_t dev);
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);
 
-void sb600_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif /* SB600_H */
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index b8d584a73c..f263afefea 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -45,7 +45,7 @@ void set_debug_port(unsigned int port)
  * This code currently only supports the first one, i.e., USB Debug devices
  * attached to physical USB ports belonging to the first EHCI device.
  */
-void sb7xx_51xx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 741d244b86..60eea47ee7 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -75,5 +75,5 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void sb7xx_51xx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index d58437a68e..174b0f2aa5 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -43,7 +43,7 @@ void set_debug_port(unsigned int port)
 }
 
 
-void sb800_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5),
 			   EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index caaeee992b..d7a4a38412 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -58,7 +58,7 @@ void sb800_clk_output_48Mhz(void);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void sb800_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #else
 void sb800_enable(device_t dev);
 void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index afee190b2d..f63c12faaf 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,11 +24,19 @@ config SOUTHBRIDGE_INTEL_I82801GX
 	select HAVE_USBDEBUG
 	select USE_WATCHDOG_ON_BOOT
 
+if SOUTHBRIDGE_INTEL_I82801GX
+
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+	default 0xfef00000
 
 config EHCI_DEBUG_OFFSET
 	hex
-	default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+	default 0xa0
+
+config USBDEBUG_DEFAULT_PORT
+	int
+	default 1 
+
+endif
 
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 63c583dea5..9b0bb1ffd3 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -46,7 +46,7 @@ extern void i82801gx_enable(device_t dev);
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 #endif
-void i82801gx_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 
 #define MAINBOARD_POWER_OFF	0
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index 991aa5adaa..ac7d3c2ed9 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -31,7 +31,7 @@ void set_debug_port(unsigned int port)
 	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
 }
 
-void i82801gx_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	u32 dbgctl;
 	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c
index 58e0c330d8..c3cfdedfab 100644
--- a/src/southbridge/intel/sch/usb_debug.c
+++ b/src/southbridge/intel/sch/usb_debug.c
@@ -30,7 +30,7 @@ void set_debug_port(unsigned int port)
 	/* Not needed, the southbridges hardcode physical USB port 1. */
 }
 
-void sch_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	u32 dbgctl;
 	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index b89ae6fa49..e7bf021c8e 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -24,7 +24,7 @@
 #include "chip.h"
 
 void ck804_enable(device_t dev);
-void ck804_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 
 extern struct pci_operations ck804_pci_ops;
 
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 3cccded343..361c672833 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -46,7 +46,7 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void ck804_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 2e78fa1ff6..be122d1c20 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -40,7 +40,7 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void mcp55_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 490a5f78e4..3173c50f39 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -35,7 +35,7 @@ extern struct pci_operations mcp55_pci_ops;
 #else
 #if !defined(__ROMCC__)
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-void mcp55_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 #endif
 
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index fb20c960f3..1be07d641b 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -42,7 +42,7 @@ void set_debug_port(unsigned int port)
 	pci_write_config32(dev, 0x74, dword);
 }
 
-void sis966_enable_usbdebug(unsigned int port)
+void enable_usbdebug(unsigned int port)
 {
 	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 
diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index a451bf7e55..d6624b3062 100644
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -40,7 +40,7 @@ void sis966_enable(device_t dev);
 #endif
 
 #if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void sis966_enable_usbdebug(unsigned int port);
+void enable_usbdebug(unsigned int port);
 #endif
 
 #endif /* SIS966_H */