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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-03-13 16:01:04 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-16 18:56:19 +0100 |
| commit | b4e5c5eb1efd9eb6141e2996845236e154a6ec0d (patch) | |
| tree | 46c829c83764973e69824b09e62b5b6fb478ff3c | |
| parent | 5fa5da1083d064e533b570e67370a7a477f02965 (diff) | |
| download | coreboot-b4e5c5eb1efd9eb6141e2996845236e154a6ec0d.tar.xz | |
cpu/x86: compile earlymtrr.c code for romstage as well
In order to make this work earlymtrr.c needed to be removed
from intel/truxton/romstage.c. It's not a ROMCC board so
there's no reason to be including .c files.
Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/cpu/x86/mtrr/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 1 |
2 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index cecb8269ef..9b7207b9e0 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1 +1,2 @@ ramstage-y += mtrr.c +romstage-y += earlymtrr.c diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 3ea65426d9..36f54953b9 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -26,7 +26,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include <northbridge/intel/i3100/raminit_ep80579.h> #include <superio/intel/i3100/i3100.h> -#include "cpu/x86/mtrr/earlymtrr.c" #include "lib/debug.c" // XXX #include <cpu/x86/bist.h> #include <spd.h> |