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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-27 16:15:02 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-15 12:18:54 +0200 |
| commit | bce9bbdfd4e645e837c53085846da7c99cef455e (patch) | |
| tree | d481f16093c82300a2e005311ab6744b6eb55547 | |
| parent | a2a7e981d68b4cd6bf390a900b5356f058650874 (diff) | |
| download | coreboot-bce9bbdfd4e645e837c53085846da7c99cef455e.tar.xz | |
AGESA: Use common romstage ram stack
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 8 | ||||
| -rw-r--r-- | src/lib/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/oem_s3.c | 4 |
3 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 54e41c1e80..e74c5b3a64 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -21,18 +21,20 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> #include <cbmem.h> +#include <program_loading.h> #include <string.h> #include <halt.h> #include "s3_resume.h" static void move_stack_high_mem(void) { - void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK); - if (high_stack == NULL) + uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + if (!high_stack) halt(); /* TODO: Make the switch with empty stack instead. */ - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); + memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); /* TODO: We only switch stack on BSP. */ #ifdef __x86_64__ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5a8f77f844..1850341992 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -81,6 +81,7 @@ ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c romstage-y += romstage_stack.c +ramstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 8cce0e7d55..4f2788e305 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -17,6 +17,7 @@ #include <spi_flash.h> #include <string.h> #include <cbmem.h> +#include <program_loading.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <AGESA.h> @@ -119,8 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) u32 MTRRStorageSize = 0; uintptr_t pos, size; - if (HIGH_ROMSTAGE_STACK_SIZE) - cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); + romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, ROMSTAGE_STACK_CBMEM); /* To be consumed in AmdInitResume. */ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); |