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| author | Zheng Bao <zheng.bao@amd.com> | 2010-02-26 20:32:08 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-02-26 20:32:08 +0000 |
| commit | be07eb29bc087a97903f72c2253442c285ce5942 (patch) | |
| tree | c8308619b240a9a60fd529cea6cdbc554e07366d | |
| parent | 29336512858f84c23720a85e9174d8f0deaff545 (diff) | |
| download | coreboot-be07eb29bc087a97903f72c2253442c285ce5942.tar.xz | |
Work around stack size breakage observed on fam10.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/arch/i386/coreboot_ram.ld | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld index afdf8a5522..2b603ea796 100644 --- a/src/arch/i386/coreboot_ram.ld +++ b/src/arch/i386/coreboot_ram.ld @@ -104,7 +104,7 @@ SECTIONS .stack . : { /* Reserve a stack for each possible cpu */ /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/ - . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); + . += ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE); } _estack = .; _heap = .; |