diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2013-09-27 16:21:04 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-05 05:23:18 +0100 |
| commit | c04e171467c61668d9ffefebf363858937c3e477 (patch) | |
| tree | 04282930ba0836226f9c3c1c5d8e3e097500aeb1 | |
| parent | 794bddf97c1c07f5fd12f073f4f5da3f476a1f07 (diff) | |
| download | coreboot-c04e171467c61668d9ffefebf363858937c3e477.tar.xz | |
baytrail: Rearrange config options alphanumerically
This is a no-op change for easier maintenance.
BUG=none
TEST=manual
. baitrail coreboot still builds and runs
Change-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171002
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4857
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 29 |
1 files changed, 15 insertions, 14 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 71a40c1ff4..613593edb7 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,24 +8,25 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y - select SMP - select SSE2 - select UDELAY_TSC - select TSC_CONSTANT_RATE - select SMM_TSEG - select SMM_MODULES - select RELOCATABLE_MODULES - select DYNAMIC_CBMEM - select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_SYNC_MFENCE + select CACHE_MRC_SETTINGS + select CACHE_ROM select CAR_MIGRATION + select COLLECT_TIMESTAMPS + select CPU_MICROCODE_IN_CBFS + select DYNAMIC_CBMEM + select HAVE_SMI_HANDLER select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select HAVE_SMI_HANDLER - select CACHE_MRC_SETTINGS - select CACHE_ROM + select RELOCATABLE_MODULES + select SMM_MODULES + select SMM_TSEG + select SMP select SPI_FLASH - select COLLECT_TIMESTAMPS + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_CONSTANT_RATE + select TSC_SYNC_MFENCE + select UDELAY_TSC config BOOTBLOCK_CPU_INIT string |