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| author | Furquan Shaikh <furquan@google.com> | 2020-05-09 14:46:09 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-12 20:04:39 +0000 |
| commit | ca892fe44b287df429215796f85e197f8bf0a968 (patch) | |
| tree | 3194a8b8b8bc6f2787a3b8b0b4f646d5a7f1c27c | |
| parent | 13b8158672d7a6509633d77e753e865db2fe09ef (diff) | |
| download | coreboot-ca892fe44b287df429215796f85e197f8bf0a968.tar.xz | |
soc/amd/common/block/lpc: Set LPC_IO_PORT_DECODE_ENABLE to 0 when disabling decodes
This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of
lpc_disable_decodes() to ensure that the I/O port decodes are also disabled.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/common/block/lpc/lpc_util.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index c9786e7aa2..2c47a8549a 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -182,6 +182,7 @@ void lpc_disable_decodes(void) reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE; pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg); + pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); /* D14F3x48 enables ranges configured in additional registers */ pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0); |