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| author | Maximilian Schander <maxschander@googlemail.com> | 2017-10-28 14:45:48 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-03 16:18:53 +0000 |
| commit | cb2d21d24d15a17a62d332c3cbc3dc1d0fcad01d (patch) | |
| tree | f139f861940ee995e89628f47cacd2146e1adf4f | |
| parent | 8890dccb233a1d77f5a7ff2f70607858d34f24c3 (diff) | |
| download | coreboot-cb2d21d24d15a17a62d332c3cbc3dc1d0fcad01d.tar.xz | |
inteltool: Add southbridge and CPU definitions for Skylake
Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | util/inteltool/inteltool.c | 20 | ||||
| -rw-r--r-- | util/inteltool/inteltool.h | 15 |
2 files changed, 34 insertions, 1 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index f873590031..ff572a31de 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -111,8 +111,11 @@ static const struct { "4th generation (Haswell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M, + "6th generation (Skylake-H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, + "6th generation (Skylake-S/H family) Core Processor (Workstation)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, "6th generation (Skylake-S/H family) Core Processor (Workstation)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -200,7 +203,22 @@ static const struct { "Wildcat Point Low Power SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, + "Sunrise Point Desktop Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q170, "Q170" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q150, "Q150" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B150, "B150" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C236, "C236" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C232, "C232" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM170, "QM170" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM170, "HM170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index d4aa96fc60..59cd6ea00e 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -139,7 +139,21 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 +#define PCI_DEVICE_ID_INTEL_H110 0xa143 +#define PCI_DEVICE_ID_INTEL_H170 0xa144 +#define PCI_DEVICE_ID_INTEL_Z170 0xa145 +#define PCI_DEVICE_ID_INTEL_Q170 0xa146 +#define PCI_DEVICE_ID_INTEL_Q150 0xa147 +#define PCI_DEVICE_ID_INTEL_B150 0xa148 +#define PCI_DEVICE_ID_INTEL_C236 0xa149 +#define PCI_DEVICE_ID_INTEL_C232 0xa14a +#define PCI_DEVICE_ID_INTEL_QM170 0xa14d +#define PCI_DEVICE_ID_INTEL_HM170 0xa14e #define PCI_DEVICE_ID_INTEL_CM236 0xa150 +#define PCI_DEVICE_ID_INTEL_HM175 0xa152 +#define PCI_DEVICE_ID_INTEL_QM175 0xa153 +#define PCI_DEVICE_ID_INTEL_CM238 0xa154 #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 @@ -208,6 +222,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 #if !defined(__DARWIN__) && !defined(__FreeBSD__) |