AMD: Isolate AGESA and PI build environments

To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.

Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.

Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)

50 files changed, 1459 insertions, 62 deletions

diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index 5603f41ef0..ab2d1f2464 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -19,3 +19,4 @@ source src/cpu/amd/geode_lx/Kconfig
 source src/cpu/amd/sc520/Kconfig
 
 source src/cpu/amd/agesa/Kconfig
+source src/cpu/amd/pi/Kconfig
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 85ce7f652a..6257615c65 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -15,3 +15,4 @@ subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
 
 subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
+subdirs-$(CONFIG_CPU_AMD_PI) += pi
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index d288fef177..fcba0cfdb2 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -25,7 +25,6 @@ config CPU_AMD_AGESA
 	default y if CPU_AMD_AGESA_FAMILY15
 	default y if CPU_AMD_AGESA_FAMILY15_TN
 	default y if CPU_AMD_AGESA_FAMILY16_KB
-	default y if CPU_AMD_AGESA_00730F01
 	default n
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_ROMSTAGE_X86_32
@@ -85,5 +84,4 @@ source src/cpu/amd/agesa/family14/Kconfig
 source src/cpu/amd/agesa/family15/Kconfig
 source src/cpu/amd/agesa/family15tn/Kconfig
 source src/cpu/amd/agesa/family16kb/Kconfig
-source src/cpu/amd/agesa/00730F01/Kconfig
 
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 800f8e7452..beba040ef4 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -22,7 +22,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
-subdirs-$(CONFIG_CPU_AMD_AGESA_00730F01) += 00730F01
 
 romstage-y += s3_resume.c
 ramstage-y += s3_resume.c
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index cab03a3096..4fa2e4e8bc 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -31,9 +31,6 @@
 #include <sb_cimx.h>
 #endif
 
-#define NORTHBRIDGE_00700F00 IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
-#define NORTHBRIDGE_00730F01 IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01)
-
 static void agesawrapper_post_device(void *unused)
 {
 	if (acpi_is_wakeup_s3())
@@ -41,7 +38,7 @@ static void agesawrapper_post_device(void *unused)
 
 	AGESAWRAPPER(amdinitlate);
 
-#if (NORTHBRIDGE_00700F00) || (NORTHBRIDGE_00730F01)
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB)
 	device_t dev;
 	u32 value;
 	dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
diff --git a/src/cpu/amd/agesa/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
index ccc44d6c5d..e610ea2ff4 100644
--- a/src/cpu/amd/agesa/00730F01/Kconfig
+++ b/src/cpu/amd/pi/00730F01/Kconfig
@@ -17,12 +17,12 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-config CPU_AMD_AGESA_00730F01
+config CPU_AMD_PI_00730F01
 	bool
 	select PCI_IO_CFG_EXT
 	select X86_AMD_FIXED_MTRRS
 
-if CPU_AMD_AGESA_00730F01
+if CPU_AMD_PI_00730F01
 
 config CPU_ADDR_BITS
 	int
diff --git a/src/cpu/amd/agesa/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
index fba21854e7..fba21854e7 100644
--- a/src/cpu/amd/agesa/00730F01/Makefile.inc
+++ b/src/cpu/amd/pi/00730F01/Makefile.inc
diff --git a/src/cpu/amd/agesa/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl
index dc86df54e0..dc86df54e0 100644
--- a/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
+++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl
diff --git a/src/cpu/amd/agesa/00730F01/chip_name.c b/src/cpu/amd/pi/00730F01/chip_name.c
index 7a1c06ccff..4a2c3eafc7 100644
--- a/src/cpu/amd/agesa/00730F01/chip_name.c
+++ b/src/cpu/amd/pi/00730F01/chip_name.c
@@ -19,6 +19,6 @@
 
 #include <device/device.h>
 
-struct chip_operations cpu_amd_agesa_00730F01_ops = {
+struct chip_operations cpu_amd_pi_00730F01_ops = {
 	CHIP_NAME("AMD CPU Family 16h")
 };
diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 8053fd1f06..8053fd1f06 100644
--- a/src/cpu/amd/agesa/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
new file mode 100644
index 0000000000..366beb41c1
--- /dev/null
+++ b/src/cpu/amd/pi/Kconfig
@@ -0,0 +1,76 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config CPU_AMD_PI
+	bool
+	default y if CPU_AMD_PI_00730F01
+	default n
+	select ARCH_BOOTBLOCK_X86_32
+	select ARCH_ROMSTAGE_X86_32
+	select ARCH_RAMSTAGE_X86_32
+	select TSC_SYNC_LFENCE
+	select UDELAY_LAPIC
+	select LAPIC_MONOTONIC_TIMER
+	select BROKEN_CAR_MIGRATE
+	select SPI_FLASH if HAVE_ACPI_RESUME
+
+if CPU_AMD_PI
+
+config UDELAY_IO
+	bool
+	default n
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+	help
+	  Overwride the default write through caching size as 1M Bytes.
+	  On some AMD platforms, one socket supports 2 or more kinds of
+	  processor family, compiling several CPU families agesa code
+	  will increase the romstage size.
+	  In order to execute romstage in place on the flash ROM,
+	  more space is required to be set as write through caching.
+
+config UDELAY_LAPIC_FIXED_FSB
+	int
+	default 200
+
+# TODO: Sync these with definitions in PI vendorcode.
+# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
+# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
+
+config DCACHE_RAM_BASE
+	hex
+	default 0x30000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+config S3_DATA_POS
+	hex
+	default 0xFFFF0000
+
+config S3_DATA_SIZE
+	int
+	default 32768
+
+endif # CPU_AMD_PI
+
+source src/cpu/amd/pi/00730F01/Kconfig
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
new file mode 100644
index 0000000000..8228b12182
--- /dev/null
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -0,0 +1,45 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
+
+romstage-y += s3_resume.c
+ramstage-y += s3_resume.c
+ramstage-$(CONFIG_SPI_FLASH) += spi.c
+
+cpu_incs += $(src)/cpu/amd/pi/cache_as_ram.inc
+
+romstage-y += heapmanager.c
+ramstage-y += heapmanager.c
+ramstage-y += amd_late_init.c
+
+ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
+
+$(obj)/coreboot_s3nv.rom: $(obj)/config.h
+	echo "    S3 NVRAM   $(CONFIG_S3_DATA_POS) (S3 storage area)"
+	# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
+	printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp
+	mv $@.tmp $@
+
+cbfs-files-y += s3nv
+s3nv-file := $(obj)/coreboot_s3nv.rom
+s3nv-position := $(CONFIG_S3_DATA_POS)
+s3nv-type := raw
+
+endif # CONFIG_HAVE_ACPI_RESUME == y
diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c
new file mode 100644
index 0000000000..efb1667d8c
--- /dev/null
+++ b/src/cpu/amd/pi/amd_late_init.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+
+#include <agesawrapper.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+
+static void agesawrapper_post_device(void *unused)
+{
+	if (acpi_is_wakeup_s3())
+		return;
+
+	AGESAWRAPPER(amdinitlate);
+
+#if (1) /* NORTHBRIDGE_00730F01 */
+	device_t dev;
+	u32 value;
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
+	pci_write_config32(dev, 0xF8, 0);
+	pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
+
+	/* disable No Snoop */
+	dev = dev_find_slot(0, PCI_DEVFN(1, 1));
+	value = pci_read_config32(dev, 0x60);
+	value &= ~(1 << 11);
+	pci_write_config32(dev, 0x60, value);
+#endif
+
+	if (!acpi_s3_resume_allowed())
+		return;
+
+	AGESAWRAPPER(amdS3Save);
+}
+
+BOOT_STATE_INIT_ENTRIES(agesa_bscb) = {
+	BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
+	                      agesawrapper_post_device, NULL),
+};
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
new file mode 100644
index 0000000000..449cf693f2
--- /dev/null
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/******************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * $Workfile:: cache_as_ram.inc
+ *
+ * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
+ *
+ ******************************************************************************
+ */
+
+#include "gcccar.inc"
+#include <cpu/x86/cache.h>
+
+/*
+ * XMM map:
+ *   xmm0: BIST
+ *   xmm1: backup ebx -- cpu_init_detected
+ */
+
+.code32
+.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+
+cache_as_ram_setup:
+
+  post_code(0xa0)
+
+  /* enable SSE2 128bit instructions */
+  /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
+
+  movl %cr4, %eax
+  orl $(3<<9), %eax
+  movl %eax, %cr4
+
+  /* Get the cpu_init_detected */
+  mov $1, %eax
+  cpuid
+  shr $24, %ebx
+
+  /* Save the BIST result */
+  cvtsi2sd  %ebp, %xmm0
+
+  /* for normal part %ebx already contain cpu_init_detected from fallback call */
+
+  /* Save the cpu_init_detected */
+  cvtsi2sd  %ebx, %xmm1
+
+  post_code(0xa1)
+  AMD_ENABLE_STACK
+
+  post_code(0xa1)
+
+  /* Restore the BIST result */
+  cvtsd2si  %xmm0, %edx
+
+  /* Restore the  cpu_init_detected */
+  cvtsd2si  %xmm1, %ebx
+
+  pushl %ebx  /* init detected */
+  pushl %edx  /* bist */
+  call  cache_as_ram_main
+
+  /* Should never see this postcode */
+  post_code(0xaf)
+stop:
+  jmp stop
+
+disable_cache_as_ram:
+  /* Save return stack */
+  movd 0(%esp), %xmm1
+  movd %esp, %xmm0
+
+  /* Disable cache */
+  movl	%cr0, %eax
+  orl	$CR0_CacheDisable, %eax
+  movl	%eax, %cr0
+
+  AMD_DISABLE_STACK
+
+  /* enable cache */
+  movl %cr0, %eax
+  andl $0x9fffffff, %eax
+  movl %eax, %cr0
+  xorl %eax, %eax
+
+  /* Restore the return stack */
+  wbinvd
+  movd %xmm0, %esp
+  movd %xmm1, (%esp)
+  ret
+
+cache_as_ram_setup_out:
diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c
new file mode 100644
index 0000000000..d2c39312d5
--- /dev/null
+++ b/src/cpu/amd/pi/heapmanager.c
@@ -0,0 +1,342 @@
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "heapManager.h"
+
+#include <cbmem.h>
+#include <arch/acpi.h>
+#include <string.h>
+
+UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
+{
+	UINT32 heap = BIOS_HEAP_START_ADDRESS;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Both romstage and ramstage has this S3 detect. */
+	if (acpi_get_sleep_type() == 3)
+		heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
+		 (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
+		  /* himem_heap_base + high_stack_size */
+#endif
+	return heap;
+}
+
+void EmptyHeap(void)
+{
+	void *BiosManagerPtr = (void *) GetHeapBase(NULL);
+	memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE);
+}
+
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+
+#define AGESA_RUNTIME_SIZE 4096
+
+static AGESA_STATUS alloc_cbmem(AGESA_BUFFER_PARAMS *AllocParams) {
+	static unsigned int used = 0;
+	void *p = cbmem_find(CBMEM_ID_AGESA_RUNTIME);
+
+	if ((AGESA_RUNTIME_SIZE - used) < AllocParams->BufferLength) {
+		return AGESA_BOUNDS_CHK;
+	}
+
+	/* first time allocation */
+	if (!p) {
+		p = cbmem_add(CBMEM_ID_AGESA_RUNTIME, AGESA_RUNTIME_SIZE);
+		if (!p)
+			return AGESA_BOUNDS_CHK;
+	}
+
+	AllocParams->BufferPointer = p + used;
+	used += AllocParams->BufferLength;
+	return AGESA_SUCCESS;
+}
+#endif
+
+AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINT32              AvailableHeapSize;
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              CurrNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              BestFitNodeOffset;
+	UINT32              BestFitPrevNodeOffset;
+	UINT32              NextFreeOffset;
+	BIOS_BUFFER_NODE   *CurrNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *BestFitNodePtr;
+	BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
+	BIOS_BUFFER_NODE   *NextFreePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+	AllocParams->BufferPointer = NULL;
+
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+	/* if the allocation is for runtime use simple CBMEM data */
+	if (Data == HEAP_CALLOUT_RUNTIME)
+		return alloc_cbmem(AllocParams);
+#endif
+
+	AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+	BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+	if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+		/* First allocation */
+		CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+		CurrNodePtr->BufferSize = AllocParams->BufferLength;
+		CurrNodePtr->NextNodeOffset = 0;
+		AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+		/* Update the remaining free space */
+		FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+		FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+		FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+		FreedNodePtr->NextNodeOffset = 0;
+
+		/* Update the offsets for Allocated and Freed nodes */
+		BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+		BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+	} else {
+		/* Find out whether BufferHandle has been allocated on the heap.
+		 * If it has, return AGESA_BOUNDS_CHK.
+		 */
+		CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+		while (CurrNodeOffset != 0) {
+			CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+			if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+				return AGESA_BOUNDS_CHK;
+			}
+			CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+			/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+			 * to the end of the allocated nodes list.
+			 */
+		}
+		/* Find the node that best fits the requested buffer size */
+		FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+		PrevNodeOffset = FreedNodeOffset;
+		BestFitNodeOffset = 0;
+		BestFitPrevNodeOffset = 0;
+		while (FreedNodeOffset != 0) {
+			FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+			if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				if (BestFitNodeOffset == 0) {
+					/* First node that fits the requested buffer size */
+					BestFitNodeOffset = FreedNodeOffset;
+					BestFitPrevNodeOffset = PrevNodeOffset;
+				} else {
+					/* Find out whether current node is a better fit than the previous nodes */
+					BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+					if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+						BestFitNodeOffset = FreedNodeOffset;
+						BestFitPrevNodeOffset = PrevNodeOffset;
+					}
+				}
+			}
+			PrevNodeOffset = FreedNodeOffset;
+			FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+		} /* end of while loop */
+
+		if (BestFitNodeOffset == 0) {
+			/* If we could not find a node that fits the requested buffer
+			 * size, return AGESA_BOUNDS_CHK.
+			 */
+			return AGESA_BOUNDS_CHK;
+		} else {
+			BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+			/* If BestFitNode is larger than the requested buffer, fragment the node further */
+			if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+				NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+				NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+				NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+			} else {
+				/* Otherwise, next free node is NextNodeOffset of BestFitNode */
+				NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+			}
+
+			/* If BestFitNode is the first buffer in the list, then update
+			 * StartOfFreedNodes to reflect the new free node.
+			 */
+			if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+				BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+			} else {
+				BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+			}
+
+			/* Add BestFitNode to the list of Allocated nodes */
+			CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+			BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+			BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+			BestFitNodePtr->NextNodeOffset = 0;
+
+			/* Remove BestFitNode from list of Freed nodes */
+			AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+		}
+	}
+
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              AllocNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              NextNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              EndNodeOffset;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_BUFFER_NODE   *PrevNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *NextNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+	/* Find target node to deallocate in list of allocated nodes.
+	 * Return AGESA_BOUNDS_CHK if the BufferHandle is not found.
+	 */
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	PrevNodeOffset = AllocNodeOffset;
+
+	while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			return AGESA_BOUNDS_CHK;
+		}
+		PrevNodeOffset = AllocNodeOffset;
+		AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+		AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	}
+
+	/* Remove target node from list of allocated nodes */
+	PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+	PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+	/* Zero out the buffer, and clear the BufferHandle */
+	LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+	AllocNodePtr->BufferHandle = 0;
+	AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+	/* Add deallocated node in order to the list of freed nodes */
+	FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+	FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+	EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+	if (AllocNodeOffset < FreedNodeOffset) {
+		/* Add to the start of the freed list */
+		if (EndNodeOffset == FreedNodeOffset) {
+			/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+			AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+			/* Clear the BufferSize and NextNodeOffset of the previous first node */
+			FreedNodePtr->BufferSize = 0;
+			FreedNodePtr->NextNodeOffset = 0;
+
+		} else {
+			/* Otherwise, add freed node to the start of the list
+			 * Update NextNodeOffset and BufferSize to include the
+			 * size of BIOS_BUFFER_NODE.
+			 */
+			AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+		}
+		/* Update StartOfFreedNodes to the new first node */
+		BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+	} else {
+		/* Traverse list of freed nodes to find where the deallocated node
+		 * should be placed.
+		 */
+		NextNodeOffset = FreedNodeOffset;
+		NextNodePtr = FreedNodePtr;
+		while (AllocNodeOffset > NextNodeOffset) {
+			PrevNodeOffset = NextNodeOffset;
+			if (NextNodePtr->NextNodeOffset == 0) {
+				break;
+			}
+			NextNodeOffset = NextNodePtr->NextNodeOffset;
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+		}
+
+		/* If deallocated node is adjacent to the next node,
+		 * concatenate both nodes.
+		 */
+		if (NextNodeOffset == EndNodeOffset) {
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+			NextNodePtr->BufferSize = 0;
+			NextNodePtr->NextNodeOffset = 0;
+		} else {
+			/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+			AllocNodePtr->NextNodeOffset = NextNodeOffset;
+		}
+		/* If deallocated node is adjacent to the previous node,
+		 * concatenate both nodes.
+		 */
+		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+		if (AllocNodeOffset == EndNodeOffset) {
+			PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+			PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+			AllocNodePtr->BufferSize = 0;
+			AllocNodePtr->NextNodeOffset = 0;
+		} else {
+			PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+		}
+	}
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINT32              AllocNodeOffset;
+	UINT8               *BiosHeapBaseAddr;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+	while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			AllocParams->BufferPointer = NULL;
+			AllocParams->BufferLength = 0;
+			return AGESA_BOUNDS_CHK;
+		} else {
+			AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+			AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+		}
+	}
+
+	AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+	AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+	return AGESA_SUCCESS;
+
+}
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
new file mode 100644
index 0000000000..fc619f7a34
--- /dev/null
+++ b/src/cpu/amd/pi/s3_resume.c
@@ -0,0 +1,311 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,  MA 02110-1301 USA
+ */
+
+#include <AGESA.h>
+#include <Lib/amdlib.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/car.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cbmem.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <string.h>
+#include "Porting.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "s3_resume.h"
+
+/* The size needs to be 4k aligned, which is the sector size of most flashes. */
+#define S3_DATA_VOLATILE_SIZE		0x6000
+#define S3_DATA_MTRR_SIZE		0x1000
+#define S3_DATA_NONVOLATILE_SIZE	0x1000
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
+	(S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
+#error "Please increase the value of S3_DATA_SIZE"
+#endif
+
+static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
+{
+	/* FIXME: Find file from CBFS. */
+	u32 s3_data = CONFIG_S3_DATA_POS;
+
+	switch (S3DataType) {
+	case S3DataTypeVolatile:
+		*pos = s3_data;
+		*len = S3_DATA_VOLATILE_SIZE;
+		break;
+	case S3DataTypeMTRR:
+		*pos = s3_data + S3_DATA_VOLATILE_SIZE;
+		*len = S3_DATA_MTRR_SIZE;
+		break;
+	case S3DataTypeNonVolatile:
+		*pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE;
+		*len = S3_DATA_NONVOLATILE_SIZE;
+		break;
+	default:
+		*pos = 0;
+		*len = 0;
+		break;
+	}
+}
+
+void restore_mtrr(void)
+{
+	u32 msr;
+	volatile UINT32 *msrPtr;
+	msr_t msr_data;
+
+	printk(BIOS_SPEW, "%s\n", __func__);
+
+	u32 pos, size;
+	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
+	msrPtr = (UINT32 *)(pos + sizeof(UINT32));
+
+	disable_cache();
+
+	/* Enable access to AMD RdDram and WrDram extension bits */
+	msr_data = rdmsr(SYS_CFG);
+	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYS_CFG, msr_data);
+
+	/* Now restore the Fixed MTRRs */
+	msr_data.lo = *msrPtr;
+	msrPtr ++;
+	msr_data.hi = *msrPtr;
+	msrPtr ++;
+	wrmsr(0x250, msr_data);
+
+	msr_data.lo = *msrPtr;
+	msrPtr ++;
+	msr_data.hi = *msrPtr;
+	msrPtr ++;
+	wrmsr(0x258, msr_data);
+
+	msr_data.lo = *msrPtr;
+	msrPtr ++;
+	msr_data.hi = *msrPtr;
+	msrPtr ++;
+	wrmsr(0x259, msr_data);
+
+	for (msr = 0x268; msr <= 0x26F; msr++) {
+		msr_data.lo = *msrPtr;
+		msrPtr ++;
+		msr_data.hi = *msrPtr;
+		msrPtr ++;
+		wrmsr(msr, msr_data);
+	}
+
+	/* Disable access to AMD RdDram and WrDram extension bits */
+	msr_data = rdmsr(SYS_CFG);
+	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYS_CFG, msr_data);
+
+	/* Restore the Variable MTRRs */
+	for (msr = 0x200; msr <= 0x20F; msr++) {
+		msr_data.lo = *msrPtr;
+		msrPtr ++;
+		msr_data.hi = *msrPtr;
+		msrPtr ++;
+		wrmsr(msr, msr_data);
+	}
+
+	/* Restore SYSCFG MTRR */
+	msr_data.lo = *msrPtr;
+	msrPtr ++;
+	msr_data.hi = *msrPtr;
+	msrPtr ++;
+	wrmsr(SYS_CFG, msr_data);
+}
+
+#ifdef __PRE_RAM__
+static void *backup_resume(void)
+{
+	void *resume_backup_memory;
+
+	if (cbmem_recovery(1))
+		return NULL;
+
+	resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+	if (((u32) resume_backup_memory == 0)
+	    || ((u32) resume_backup_memory == -1)) {
+		printk(BIOS_ERR, "Error: resume_backup_memory: %x\n",
+		       (u32) resume_backup_memory);
+		for (;;) ;
+	}
+
+	return resume_backup_memory;
+}
+
+static void move_stack_high_mem(void)
+{
+	void *high_stack;
+
+	high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
+	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
+		(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
+
+	__asm__
+	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
+		      (high_stack - BSP_STACK_BASE_ADDR)
+		      :);
+}
+#endif
+
+#ifndef __PRE_RAM__
+/* FIXME: Why store MTRR in SPI, just use CBMEM ? */
+static u8 mtrr_store[S3_DATA_MTRR_SIZE];
+
+static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
+{
+	msr_t  msr_data;
+	msr_data = rdmsr(idx);
+
+	memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
+	*p_nvram_pos += sizeof(msr_data);
+}
+
+void OemAgesaSaveMtrr(void)
+{
+	msr_t  msr_data;
+	u32 i;
+
+	u8 *nvram_pos = (u8 *) mtrr_store;
+
+	/* Enable access to AMD RdDram and WrDram extension bits */
+	msr_data = rdmsr(SYS_CFG);
+	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYS_CFG, msr_data);
+
+	/* Fixed MTRRs */
+	write_mtrr(&nvram_pos, 0x250);
+	write_mtrr(&nvram_pos, 0x258);
+	write_mtrr(&nvram_pos, 0x259);
+
+	for (i = 0x268; i < 0x270; i++)
+		write_mtrr(&nvram_pos, i);
+
+	/* Disable access to AMD RdDram and WrDram extension bits */
+	msr_data = rdmsr(SYS_CFG);
+	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYS_CFG, msr_data);
+
+	/* Variable MTRRs */
+	for (i = 0x200; i < 0x210; i++)
+		write_mtrr(&nvram_pos, i);
+
+	/* SYS_CFG */
+	write_mtrr(&nvram_pos, 0xC0010010);
+	/* TOM */
+	write_mtrr(&nvram_pos, 0xC001001A);
+	/* TOM2 */
+	write_mtrr(&nvram_pos, 0xC001001D);
+
+#if IS_ENABLED(CONFIG_SPI_FLASH)
+	u32 pos, size;
+	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
+	spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store);
+#endif
+}
+
+u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
+{
+#if IS_ENABLED(CONFIG_SPI_FLASH)
+	u32 pos, size;
+	get_s3nv_data(S3DataType, &pos, &size);
+	spi_SaveS3info(pos, size, Data, DataSize);
+#endif
+	return AGESA_SUCCESS;
+}
+#endif
+
+void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
+{
+	AMD_CONFIG_PARAMS StdHeader;
+
+	u32 pos, size;
+	get_s3nv_data(S3DataType, &pos, &size);
+
+	if (S3DataType == S3DataTypeNonVolatile) {
+		*DataSize = *(UINT32 *) pos;
+		*Data = (void *) (pos + sizeof(UINT32));
+	} else if (S3DataType == S3DataTypeVolatile) {
+		u32 len = *(UINT32 *) pos;
+		void *src = (void *) (pos + sizeof(UINT32));
+		void *dst = (void *) GetHeapBase(&StdHeader);
+		memcpy(dst, src, len);
+		*DataSize = len;
+		*Data = dst;
+	}
+}
+
+#ifdef __PRE_RAM__
+static void set_resume_cache(void)
+{
+	msr_t msr;
+
+	/* disable fixed mtrr for now,  it will be enabled by mtrr restore */
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
+	wrmsr(SYSCFG_MSR, msr);
+
+	/* Enable caching for 0 - coreboot ram using variable mtrr */
+	msr.lo = 0 | MTRR_TYPE_WRBACK;
+	msr.hi = 0;
+	wrmsr(MTRRphysBase_MSR(0), msr);
+	msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid;
+	msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(0), msr);
+
+	/* Set the default memory type and disable fixed and enable variable MTRRs */
+	msr.hi = 0;
+	msr.lo = (1 << 11);
+	wrmsr(MTRRdefType_MSR, msr);
+
+	enable_cache();
+}
+
+void prepare_for_resume(void)
+{
+	printk(BIOS_DEBUG, "Find resume memory location\n");
+	void *resume_backup_memory = backup_resume();
+
+	post_code(0x62);
+	printk(BIOS_DEBUG, "Move CAR stack.\n");
+	move_stack_high_mem();
+	printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
+
+	post_code(0x63);
+	disable_cache_as_ram();
+	printk(BIOS_DEBUG, "CAR disabled.\n");
+	set_resume_cache();
+
+	/*
+	 * Copy the system memory that is in the ramstage area to the
+	 * reserved area.
+	 */
+	if (resume_backup_memory)
+		memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
+
+	printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+}
+#endif
diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h
new file mode 100644
index 0000000000..14984dfc9c
--- /dev/null
+++ b/src/cpu/amd/pi/s3_resume.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,  MA 02110-1301 USA
+ */
+
+#ifndef S3_RESUME_H
+#define S3_RESUME_H
+
+typedef enum {
+	S3DataTypeNonVolatile=0,	///< NonVolatile Data Type
+	S3DataTypeVolatile,		///< Volatile Data Type
+	S3DataTypeMTRR			///< MTRR storage
+} S3_DATA_TYPE;
+
+void restore_mtrr(void);
+void prepare_for_resume(void);
+
+u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
+void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
+void OemAgesaSaveMtrr (void);
+
+void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
+
+#endif
diff --git a/src/cpu/amd/pi/spi.c b/src/cpu/amd/pi/spi.c
new file mode 100644
index 0000000000..1c652fd295
--- /dev/null
+++ b/src/cpu/amd/pi/spi.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,  MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+
+#include "s3_resume.h"
+
+void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
+{
+	struct spi_flash *flash;
+
+	spi_init();
+	flash = spi_flash_probe(0, 0);
+	if (!flash) {
+		printk(BIOS_DEBUG, "Could not find SPI device\n");
+		/* Dont make flow stop. */
+		return;
+	}
+
+	flash->spi->rw = SPI_WRITE_FLAG;
+	spi_claim_bus(flash->spi);
+
+	flash->erase(flash, pos, size);
+	flash->write(flash, pos, sizeof(len), &len);
+	flash->write(flash, pos + sizeof(len), len, buf);
+
+	flash->spi->rw = SPI_WRITE_FLAG;
+	spi_release_bus(flash->spi);
+
+	return;
+}
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index c00310a61f..d86275354b 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -8,7 +8,7 @@ void post_cache_as_ram(void);
 void cache_as_ram_switch_stack(void *stacktop);
 void cache_as_ram_new_stack(void);
 
-#if CONFIG_CPU_AMD_AGESA
+#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI
 void disable_cache_as_ram(void);
 #endif
 
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index cc41ec8631..1d821faf4d 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -19,7 +19,7 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
 #include "Ids.h"
 #include "OptionsIds.h"
 #include "heapManager.h"
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index 883df6c6bb..6191cb1070 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -21,8 +21,8 @@ if BOARD_AMD_OLIVEHILLPLUS
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select CPU_AMD_AGESA_00730F01
-	select NORTHBRIDGE_AMD_AGESA_00730F01
+	select CPU_AMD_PI_00730F01
+	select NORTHBRIDGE_AMD_PI_00730F01
 	select SOUTHBRIDGE_AMD_AGESA_AVALON
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/amd/olivehillplus/agesawrapper.c b/src/mainboard/amd/olivehillplus/agesawrapper.c
index 45670bdce4..9d433db4cc 100644
--- a/src/mainboard/amd/olivehillplus/agesawrapper.c
+++ b/src/mainboard/amd/olivehillplus/agesawrapper.c
@@ -22,7 +22,7 @@
 #include <config.h>
 #include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
 #include "cpuRegisters.h"
 #include "cpuCacheInit.h"
 #include "cpuApicUtilities.h"
@@ -36,7 +36,7 @@
 #include "heapManager.h"
 #include "FchPlatform.h"
 #include "Fch.h"
-#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/amd/pi/s3_resume.h>
 #include <arch/io.h>
 #include <device/device.h>
 #include "hudson.h"
diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb
index a00e2ba823..aec71f9d72 100644
--- a/src/mainboard/amd/olivehillplus/devicetree.cb
+++ b/src/mainboard/amd/olivehillplus/devicetree.cb
@@ -16,18 +16,18 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
-chip northbridge/amd/agesa/00730F01/root_complex
+chip northbridge/amd/pi/00730F01/root_complex
 	device cpu_cluster 0 on
-		chip cpu/amd/agesa/00730F01
+		chip cpu/amd/pi/00730F01
 			device lapic 0 on  end
 		end
 	end
 
 	device domain 0 on
 		subsystemid 0x1022 0x1410 inherit
-		chip northbridge/amd/agesa/00730F01 # CPU side of HT root complex
+		chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
 
-			chip northbridge/amd/agesa/00730F01 # PCI side of HT root complex
+			chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
 				device pci 0.0 on  end # Root Complex
 				device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
 				device pci 1.1 on  end # Internal Multimedia
@@ -37,7 +37,7 @@ chip northbridge/amd/agesa/00730F01/root_complex
 				device pci 2.3 on  end # Realtek NIC
 				device pci 2.4 on  end # Edge Connector
 				device pci 2.5 on  end # Edge Connector
-			end	#chip northbridge/amd/agesa/00730F01
+			end	#chip northbridge/amd/pi/00730F01
 
 			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0
@@ -70,6 +70,6 @@ chip northbridge/amd/agesa/00730F01/root_complex
 				{ {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses
 			}"
 
-		end #chip northbridge/amd/agesa/00730F01 # CPU side of HT root complex
+		end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
 	end #domain
-end #northbridge/amd/agesa/00730F01/root_complex
+end #northbridge/amd/pi/00730F01/root_complex
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
index 15bcd3dfa4..b74dac6218 100644
--- a/src/mainboard/amd/olivehillplus/dsdt.asl
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -40,7 +40,7 @@ DefinitionBlock (
 	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
 
 	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/agesa/00730F01/acpi/cpu.asl>
+	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
 	#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
@@ -65,7 +65,7 @@ DefinitionBlock (
 
 		Device(PCI0) {
 			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/00730F01/acpi/northbridge.asl>
+			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
 
 			/* Describe the AMD Fusion Controller Hub Southbridge */
 			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c
index 6073fd4322..f4fbb92906 100644
--- a/src/mainboard/amd/olivehillplus/mainboard.c
+++ b/src/mainboard/amd/olivehillplus/mainboard.c
@@ -23,8 +23,8 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <arch/acpi.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include <cpu/amd/pi/s3_resume.h>
 #include "agesawrapper.h"
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 5f018a757c..5230f7dfa3 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -31,11 +31,11 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include "agesawrapper.h"
-#include <northbridge/amd/agesa/agesawrapper_call.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
-#include "cpu/amd/agesa/s3_resume.h"
+#include "cpu/amd/pi/s3_resume.h"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig
index 33e19c2a9f..c75e82cdb5 100644
--- a/src/northbridge/amd/Kconfig
+++ b/src/northbridge/amd/Kconfig
@@ -5,6 +5,8 @@ source src/northbridge/amd/amdfam10/Kconfig
 source src/northbridge/amd/lx/Kconfig
 source src/northbridge/amd/agesa/Kconfig
 source src/northbridge/amd/cimx/Kconfig
+source src/northbridge/amd/pi/Kconfig
+
 menu "HyperTransport setup"
 	#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
 	depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index 7e85d08066..edb4038261 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -4,5 +4,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA) += agesa
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI) += pi
 
 subdirs-$(CONFIG_AMD_NB_CIMX) += cimx
diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h
index 60299b792e..feabf9895f 100644
--- a/src/northbridge/amd/agesa/BiosCallOuts.h
+++ b/src/northbridge/amd/agesa/BiosCallOuts.h
@@ -24,7 +24,7 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB || CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 
 #define BIOS_HEAP_START_ADDRESS 	0x010000000
 #define BIOS_HEAP_SIZE			0x30000
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index d557e62607..677e94745c 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -37,7 +37,6 @@ source src/northbridge/amd/agesa/family14/Kconfig
 source src/northbridge/amd/agesa/family15/Kconfig
 source src/northbridge/amd/agesa/family15tn/Kconfig
 source src/northbridge/amd/agesa/family16kb/Kconfig
-source src/northbridge/amd/agesa/00730F01/Kconfig
 
 # TODO: Reservation for heap seems excessive
 config HEAP_SIZE
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index f1be0235b3..8f10664566 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -22,7 +22,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01) += 00730F01
 
 romstage-y += def_callouts.c
 ramstage-y += def_callouts.c
diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c
index ee79be233f..5d1b2be0ee 100644
--- a/src/northbridge/amd/agesa/def_callouts.c
+++ b/src/northbridge/amd/agesa/def_callouts.c
@@ -104,7 +104,7 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	return Status;
 }
 
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB || CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 /* FIXME: we would like GFX disable for fam14 too for headless systems. */
 AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
 {
diff --git a/src/northbridge/amd/agesa/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig
index 36bc0fce07..c0531114c0 100644
--- a/src/northbridge/amd/agesa/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -17,11 +17,11 @@
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
-config NORTHBRIDGE_AMD_AGESA_00730F01
+config NORTHBRIDGE_AMD_PI_00730F01
 	bool
 	select MMCONF_SUPPORT
 
-if NORTHBRIDGE_AMD_AGESA_00730F01
+if NORTHBRIDGE_AMD_PI_00730F01
 
 config HW_MEM_HOLE_SIZEK
 	hex
diff --git a/src/northbridge/amd/agesa/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc
index 4a754995eb..4a754995eb 100644
--- a/src/northbridge/amd/agesa/00730F01/Makefile.inc
+++ b/src/northbridge/amd/pi/00730F01/Makefile.inc
diff --git a/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
index 37aba9a2ea..37aba9a2ea 100644
--- a/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
diff --git a/src/northbridge/amd/agesa/00730F01/chip.h b/src/northbridge/amd/pi/00730F01/chip.h
index 4b6fc2c6b9..aa08cff653 100644
--- a/src/northbridge/amd/agesa/00730F01/chip.h
+++ b/src/northbridge/amd/pi/00730F01/chip.h
@@ -17,12 +17,12 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef _AGESA_00730F01_CHIP_H_
-#define _AGESA_00730F01_CHIP_H_
+#ifndef _PI_00730F01_CHIP_H_
+#define _PI_00730F01_CHIP_H_
 
-struct northbridge_amd_agesa_00730F01_config
+struct northbridge_amd_pi_00730F01_config
 {
 	u8 spdAddrLookup[1][1][2];
 };
 
-#endif	/* _AGESA_00730F01_CHIP_H_ */
+#endif	/* _PI_00730F01_CHIP_H_ */
diff --git a/src/northbridge/amd/agesa/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c
index 4cfbb7fec7..45a1b50d0d 100644
--- a/src/northbridge/amd/agesa/00730F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c
@@ -34,7 +34,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	int spdAddress;
 	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_agesa_00730F01_config *config = dev->chip_info;
+	ROMSTAGE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 03433af5d8..77425bbb9a 100644
--- a/src/northbridge/amd/agesa/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -39,7 +39,7 @@
 #include <cpu/amd/amdfam16.h>
 #include <cpuRegisters.h>
 #include "agesawrapper.h"
-#include <northbridge/amd/agesa/agesawrapper_call.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
 #include "northbridge.h"
 
 #include <cpu/x86/lapic.h>
@@ -494,7 +494,7 @@ static const struct pci_driver family10_northbridge __pci_driver = {
 	.device = PCI_DEVICE_ID_AMD_10H_NB_HT,
 };
 
-struct chip_operations northbridge_amd_agesa_00730F01_ops = {
+struct chip_operations northbridge_amd_pi_00730F01_ops = {
 	CHIP_NAME("AMD FAM16 Northbridge")
 	.enable_dev = 0,
 };
@@ -1129,7 +1129,7 @@ static void root_complex_enable_dev(struct device *dev)
 	}
 }
 
-struct chip_operations northbridge_amd_agesa_00730F01_root_complex_ops = {
+struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = {
 	CHIP_NAME("AMD FAM16 Root Complex")
 	.enable_dev = root_complex_enable_dev,
 };
diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.h b/src/northbridge/amd/pi/00730F01/northbridge.h
index 6fa8164ba9..6fa8164ba9 100644
--- a/src/northbridge/amd/agesa/00730F01/northbridge.h
+++ b/src/northbridge/amd/pi/00730F01/northbridge.h
diff --git a/src/northbridge/amd/pi/BiosCallOuts.h b/src/northbridge/amd/pi/BiosCallOuts.h
new file mode 100644
index 0000000000..feabf9895f
--- /dev/null
+++ b/src/northbridge/amd/pi/BiosCallOuts.h
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011,2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CALLOUTS_AMD_AGESA_H
+#define CALLOUTS_AMD_AGESA_H
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+
+#define BIOS_HEAP_START_ADDRESS 	0x010000000
+#define BIOS_HEAP_SIZE			0x30000
+#define BSP_STACK_BASE_ADDR		0x30000
+
+#else
+
+#define BIOS_HEAP_START_ADDRESS		0x10000 /* HEAP during cold boot */
+#define BIOS_HEAP_SIZE			0x20000
+#define BSP_STACK_BASE_ADDR		0x30000
+
+#endif
+
+typedef struct _BIOS_HEAP_MANAGER {
+	UINT32 StartOfAllocatedNodes;
+	UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+	UINT32 BufferHandle;
+	UINT32 BufferSize;
+	UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+
+UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
+void EmptyHeap(void);
+
+
+AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt);
+
+AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+typedef struct {
+	UINT32 CalloutName;
+	AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+extern const BIOS_CALLOUT_STRUCT BiosCallouts[];
+extern const int BiosCalloutsLen;
+
+#endif /* CALLOUTS_AMD_AGESA_H */
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
new file mode 100644
index 0000000000..8af4872b35
--- /dev/null
+++ b/src/northbridge/amd/pi/Kconfig
@@ -0,0 +1,36 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_PI
+        bool
+        default CPU_AMD_PI
+
+if NORTHBRIDGE_AMD_PI
+
+config CONSOLE_VGA_MULTI
+	bool
+	default n
+
+config S3_VGA_ROM_RUN
+	bool
+	default n
+
+source src/northbridge/amd/pi/00730F01/Kconfig
+
+endif # NORTHBRIDGE_AMD_PI
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
new file mode 100644
index 0000000000..294673c31d
--- /dev/null
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -0,0 +1,23 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
+
+romstage-y += def_callouts.c
+ramstage-y += def_callouts.c
diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h
new file mode 100644
index 0000000000..792c3b1c05
--- /dev/null
+++ b/src/northbridge/amd/pi/agesawrapper_call.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESAWRAPPER_CALL_H_
+#define _AGESAWRAPPER_CALL_H_
+
+#include <stdint.h>
+#include <console/console.h>
+#include "AGESA.h"
+
+/*
+ * Possible AGESA_STATUS values:
+ *
+ * 0x0 = AGESA_SUCCESS
+ * 0x1 = AGESA_UNSUPPORTED
+ * 0x2 = AGESA_BOUNDS_CHK
+ * 0x3 = AGESA_ALERT
+ * 0x4 = AGESA_WARNING
+ * 0x5 = AGESA_ERROR
+ * 0x6 = AGESA_CRITICAL
+ * 0x7 = AGESA_FATAL
+ */
+static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
+{
+	const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
+					"AGESA_BOUNDS_CHK", "AGESA_ALERT",
+					"AGESA_WARNING", "AGESA_ERROR",
+					"AGESA_CRITICAL", "AGESA_FATAL"
+					};
+	if (sret > 7) return "unknown"; /* Non-AGESA error code */
+	return statusStrings[sret];
+}
+
+static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name)
+{
+	AGESA_STATUS ret;
+	printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name);
+	ret = func();
+	printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n",
+			name, decodeAGESA_STATUS(ret));
+	return (u32)ret;
+}
+
+#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func)
+
+#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func()
+
+#endif
diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c
new file mode 100644
index 0000000000..225bf53947
--- /dev/null
+++ b/src/northbridge/amd/pi/def_callouts.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <spd_cache.h>
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "dimmSpd.h"
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINTN i;
+
+	for (i = 0; i < BiosCalloutsLen; i++) {
+		if (BiosCallouts[i].CalloutName == Func)
+			break;
+	}
+	if(i >= BiosCalloutsLen)
+		return AGESA_UNSUPPORTED;
+
+	return BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+}
+
+AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_UNSUPPORTED;
+}
+
+AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	IDS_NV_ITEM *IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+	if (Data == IDS_CALLOUT_INIT)
+		IdsPtr[0].IdsNvValue = IdsPtr[0].IdsNvId = 0xffff;
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS        Status;
+	UINT8                 Value;
+	UINTN               ResetType;
+	AMD_CONFIG_PARAMS   *StdHeader;
+
+	ResetType = Data;
+	StdHeader = ConfigPtr;
+
+	//
+	// Perform the RESET based upon the ResetType. In case of
+	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+	// AmdResetManager. During the critical condition, where reset is required
+	// immediately, the reset will be invoked directly by writing 0x04 to port
+	// 0xCF9 (Reset Port).
+	//
+	switch (ResetType) {
+	case WARM_RESET_WHENEVER:
+	case COLD_RESET_WHENEVER:
+		break;
+
+	case WARM_RESET_IMMEDIATELY:
+	case COLD_RESET_IMMEDIATELY:
+		Value = 0x06;
+		LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+		break;
+
+	default:
+		break;
+	}
+
+	Status = 0;
+	return Status;
+}
+
+AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS        Status;
+
+	Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
+	return Status;
+}
+
+AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
+{
+	GFX_VBIOS_IMAGE_INFO  *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt;
+	pVbiosImageInfo->ImagePtr = cbfs_get_file_content(
+			CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom",
+			CBFS_TYPE_OPTIONROM, NULL);
+	/* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */
+	return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+	Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+#endif
+	return Status;
+}
+
+AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+	if (info->MemChannelId > 0)
+		return AGESA_UNSUPPORTED;
+	if (info->SocketId != 0)
+		return AGESA_UNSUPPORTED;
+	if (info->DimmId != 0)
+		return AGESA_UNSUPPORTED;
+
+	/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
+	if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0)
+		die("No SPD data\n");
+
+	Status = AGESA_SUCCESS;
+#endif
+	return Status;
+}
diff --git a/src/northbridge/amd/pi/dimmSpd.h b/src/northbridge/amd/pi/dimmSpd.h
new file mode 100644
index 0000000000..3af67204aa
--- /dev/null
+++ b/src/northbridge/amd/pi/dimmSpd.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+AGESA_STATUS
+AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
+
+int hudson_readSpd(int spdAddress, char *buf, size_t len);
+
+int smbus_readSpd(int spdAddress, char *buf, size_t len);
+
+#endif
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index df7d76f5de..c969d063a9 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -85,7 +85,7 @@ config HUDSON_GEC_FWM
 
 config HUDSON_PSP
 	bool
-	default y if CPU_AMD_AGESA_00730F01
+	default y if CPU_AMD_PI_00730F01
 
 config HUDSON_XHCI_FWM_FILE
         string "XHCI firmware path and filename"
@@ -138,7 +138,7 @@ endif # HUDSON_FWM
 config AMD_PUBKEY_FILE
         depends on HUDSON_PSP
         string "AMD public Key"
-        default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_AGESA_00730F01
+        default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
 
 config HUDSON_SATA_MODE
         int "SATA Mode"
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 4b1eed696c..5a3a9fd64a 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -101,7 +101,7 @@ HUDSON_IMC_POSITION=0
 endif
 
 HUDSON_PSP_DIRECTORY_POSITION=0
-ifeq ($(CONFIG_CPU_AMD_AGESA_00730F01), y)
+ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
 HUDSON_PSP_DIRECTORY_POSITION=$(call int-add,$(HUDSON_FWM_POSITION) 262144)
 endif
 
@@ -164,7 +164,7 @@ ifeq ($(CONFIG_HUDSON_PSP), y)
 AMDPUBKEY_POS=$(call int-add,$(HUDSON_PSP_DIRECTORY_POSITION) 0x100)   #$(shell printf %u 0xFFb00100)
 AMDPUBKEY_SIZE=$(call file-size,$(CONFIG_AMD_PUBKEY_FILE))
 
-ifeq ($(CONFIG_CPU_AMD_AGESA_00730F01), y)
+ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y)
 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)))
 FIRMWARE_TYPE=
 endif
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig
index 6cc4b2c520..d9ac731275 100644
--- a/src/vendorcode/amd/Kconfig
+++ b/src/vendorcode/amd/Kconfig
@@ -17,7 +17,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-if 	CPU_AMD_AGESA_00730F01
+if CPU_AMD_PI
 
 menu "AMD Platform Initialization"
 
@@ -25,8 +25,7 @@ source src/vendorcode/amd/pi/Kconfig
 
 choice
 	prompt "AGESA source"
-	depends on CPU_AMD_AGESA
-	default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_AGESA_00730F01
+	default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI
 	default CPU_AMD_AGESA_OPENSOURCE
 	help
 	  Select the method for including the AMD Platform Initialization
@@ -50,14 +49,14 @@ config CPU_AMD_AGESA_OPENSOURCE
 
 endchoice
 
+if CPU_AMD_AGESA_BINARY_PI
+
 config AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
 	bool
-	depends on CPU_AMD_AGESA_BINARY_PI
 	default n
 
 config AGESA_BINARY_PI_PATH
 	string "AGESA PI directory path"
-	depends on CPU_AMD_AGESA_BINARY_PI
 	default AGESA_BINARY_PI_PATH_DEFAULT if AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
 	help
 	  Specify where to find the AGESA headers and binary file
@@ -65,29 +64,27 @@ config AGESA_BINARY_PI_PATH
 
 config AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
 	bool
-	depends on CPU_AMD_AGESA_BINARY_PI
 	default n
 
 config AGESA_BINARY_PI_FILE
 	string "AGESA PI binary file name"
-	depends on CPU_AMD_AGESA_BINARY_PI
 	default AGESA_BINARY_PI_FILE_DEFAULT if AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
 	help
 	  Specify the binary file to use for AMD platform initialization.
 
 config AGESA_BINARY_PI_LOCATION_DEFAULT_SELECTED
 	bool
-	depends on CPU_AMD_AGESA_BINARY_PI
 	default n
 
 config AGESA_BINARY_PI_LOCATION
 	string "AGESA PI binary address in ROM"
-	depends on CPU_AMD_AGESA_BINARY_PI
 	default AGESA_BINARY_PI_LOCATION_DEFAULT if AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
 	help
 	  Specify the ROM address at which to store the binary Platform
 	  Initialization code.
 
+endif
+
 endmenu
 
 endif
diff --git a/src/vendorcode/amd/pi/00730F01/Kconfig b/src/vendorcode/amd/pi/00730F01/Kconfig
index 0b3729440a..c630a24e0e 100644
--- a/src/vendorcode/amd/pi/00730F01/Kconfig
+++ b/src/vendorcode/amd/pi/00730F01/Kconfig
@@ -25,32 +25,28 @@
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 
-if CPU_AMD_AGESA_00730F01
+if CPU_AMD_PI_00730F01
 
 config AGESA_BINARY_PI_DEFAULTS # dummy
 	def_bool y
-	depends on CPU_AMD_AGESA_00730F01
 	select AGESA_BINARY_PI_LOCATION_DEFAULT_SELECTED
 	select AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
 	select AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
 
 config AGESA_BINARY_PI_PATH_DEFAULT
 	string
-	depends on CPU_AMD_AGESA_00730F01
 	default "3rdparty/pi/amd/00730F01"
 	help
 	  The default binary file name to use for AMD platform initialization.
 
 config AGESA_BINARY_PI_FILE_DEFAULT
 	string
-	depends on CPU_AMD_AGESA_00730F01
 	default "FT3b/AGESA.bin"
 	help
 	  The default binary file name to use for AMD platform initialization.
 
 config AGESA_BINARY_PI_LOCATION_DEFAULT
 	hex
-	depends on CPU_AMD_AGESA_00730F01
 	default 0xFFE00000
 	help
 	  The default ROM address at which to store the binary Platform
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 0d28d193ec..424e674b2e 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -1 +1 @@
-subdirs-$(CONFIG_CPU_AMD_AGESA_00730F01) += 00730F01
+subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01