diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-13 16:05:15 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 05:29:39 +0000 |
| commit | fd02ff0375d72b7e50d697446c877c3c8ad94efc (patch) | |
| tree | 15a238889c1be0dffc8a1680c04077cf9e2b1a57 | |
| parent | 8fc49096f90b8abe6f58ea1602e606fb80269ba4 (diff) | |
| download | coreboot-fd02ff0375d72b7e50d697446c877c3c8ad94efc.tar.xz | |
soc/intel/cannonlake: Enable CPU flexible ratio
CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.
BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8f6fa2ff54..3e0f92249a 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -45,8 +45,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; - /* Disable Cpu Ratio Override temporary. */ - m_cfg->CpuRatio = 0; m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; /* Disable Vmx if Vt-d is already disabled */ if (config->VtdDisable) |