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author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 15:55:45 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-18 17:20:56 +0000 |
commit | 07462ef3d69e4458110bf27a1ecb1d4379929ff4 (patch) | |
tree | bf657ee843f1b84cfe91b680b1b1f7536b43761b | |
parent | 02a5dddb01a6629aaf64fdc196b996883602a293 (diff) | |
download | coreboot-07462ef3d69e4458110bf27a1ecb1d4379929ff4.tar.xz |
soc/amd/cezanne: add GPIO support
This still uses the common GPIO code that supports setting up SMI/SCI
support for the GPIOs in all stages, which will get removed in future
patches, so for now the SoC's gpio.c needs to be included in all stages.
Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 4 | ||||
-rw-r--r-- | src/soc/amd/cezanne/gpio.c | 54 |
3 files changed, 59 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index a51dc44db8..cb613e3264 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -18,6 +18,7 @@ config SOC_SPECIFIC_OPTIONS select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_SMBUS diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 2852b6a652..5ffe06fa05 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -9,14 +9,18 @@ all-y += config.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += gpio.c bootblock-y += reset.c +verstage_x86-y += gpio.c verstage_x86-y += reset.c +romstage-y += gpio.c romstage-y += reset.c romstage-y += romstage.c ramstage-y += chip.c +ramstage-y += gpio.c ramstage-y += reset.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/gpio.c b/src/soc/amd/cezanne/gpio.c new file mode 100644 index 0000000000..d14f850536 --- /dev/null +++ b/src/soc/amd/cezanne/gpio.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <amdblocks/gpio_banks.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> +#include <soc/gpio.h> +#include <soc/smi.h> + +/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */ +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_7, GEVENT_11 }, + { GPIO_8, GEVENT_23 }, + { GPIO_9, GEVENT_22 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_18, GEVENT_14 }, + { GPIO_21, GEVENT_5 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_15 }, + { GPIO_40, GEVENT_20 }, + { GPIO_84, GEVENT_18 }, + { GPIO_86, GEVENT_9 }, + { GPIO_89, GEVENT_0 }, + { GPIO_90, GEVENT_1 }, + { GPIO_91, GEVENT_6 }, + { GPIO_129, GEVENT_17 }, +}; + +void soc_route_sci(uint8_t event) +{ + smi_write8(SMI_SCI_MAP(event), event); +} + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} + +void soc_gpio_hook(uint8_t gpio, uint8_t mux) +{ + /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ + if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) + soc_route_sci(GPIO_2_EVENT); +} |