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authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-02-26 14:09:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-02 11:39:05 +0000
commit0751d7bded12440e6228e88b12ce212dcbc7d645 (patch)
treec6d8b6ad8aa2f8b14db34c72a17a0d94a4f334ff
parent24a974a8cbbbf0009cbbec3f5dc11aa8e35c26a8 (diff)
downloadcoreboot-0751d7bded12440e6228e88b12ce212dcbc7d645.tar.xz
Documentation: Add tutorial for me_cleaner on Lenovo devices
Add a tutorial how to use ME cleaner, and give some basic steps to strip the ME. Update the Lenovo Sandy Bridge documentation that no issues could be observed on X220 and give an example flash layout. Tested on Lenovo X220 with stripped ME and found no issues: commit: cbc5b99ac9e5856631109b1e7f20e80799beb1e4 * Displayport * VGA * USB * Bluetooth * Wifi * Wifi-kill switch * libgfxinit * SATA * Audio * SD-card * Ethernet * Keyboard * Fn-Keys * Display brightness * ACPI S3 resume * Battery events * CPU temperature reporting * FAN managment * Stress test stable * Youtube videos over Wifi * stress -c 2 -m 1 -d 1 * glxgears Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--Documentation/mainboard/lenovo/Sandy_Bridge_series.md27
-rw-r--r--Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg74
-rw-r--r--Documentation/northbridge/intel/sandybridge/me_cleaner.md66
3 files changed, 163 insertions, 4 deletions
diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md
index 0b833f5cc8..dbbbbeef30 100644
--- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md
+++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md
@@ -33,9 +33,7 @@
usable by coreboot.
* ROM chip size should be set to 8MiB.
-```eval_rst
-Please also have a look at :doc:`../../flash_tutorial/index`.
-```
+Please also have a look at the [flashing tutorial]
## Flash layout
There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions.
@@ -46,3 +44,26 @@ region. The update is then written into the EC once.
[fl]: flashlayout_Sandy_Bridge.svg
+## Reducing Intel Managment Engine firmware size
+
+It is possible to reduce the Intel ME firmware size to free additional
+space for the `bios` region. This is usually refered to as *cleaning the ME* or
+*stripping the ME*.
+After reducing the Intel ME firmware size you must modify the original IFD
+and then write a full ROM using an [external programmer].
+Have a look at the [me_cleaner] for more information.
+
+Tests on Lenovo X220 showed no issues with a stripped ME firmware.
+
+**Modified flash layout:**
+
+![][fl2]
+
+[fl2]: flashlayout_Sandy_Bridge_stripped_me.svg
+
+The overall size of the `gbe`, `me,` `ifd` region is less than 128KiB, leaving
+the remaining space for the `bios` partition.
+
+
+[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
+[external programmer]: ../../flash_tutorial/index.md
diff --git a/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg
new file mode 100644
index 0000000000..d8d8213d12
--- /dev/null
+++ b/Documentation/mainboard/lenovo/flashlayout_Sandy_Bridge_stripped_me.svg
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd">
+<svg width="9cm" height="8cm" viewBox="268 -156 168 158" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
+ <g>
+ <g>
+ <g>
+ <rect style="fill: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="307.888" y="-152.131" width="49.1438" height="30.4667"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="307.888" y="-152.131" width="49.1438" height="30.4667"/>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.46" y="-134.831">
+ <tspan x="332.46" y="-134.831">IFD</tspan>
+ </text>
+ </g>
+ <g>
+ <g>
+ <rect style="fill: #ffffff" x="307.934" y="-56.9106" width="49.1438" height="56.1492"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 0.02; stroke: #ffffff" x="307.934" y="-56.9106" width="49.1438" height="56.1492"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 0.02; stroke: #ffffff" x="307.934" y="-56.9106" width="49.1438" height="56.1492"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="308.096" y="-57.559" width="49.1438" height="57.2839"/>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.182" y="-24.0245">
+ <tspan x="332.182" y="-24.0245">BIOS</tspan>
+ </text>
+ <g>
+ <g>
+ <g>
+ <rect style="fill: #ffffff" x="308" y="-121.59" width="49.1438" height="30.4667"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308" y="-121.59" width="49.1438" height="30.4667"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308" y="-121.59" width="49.1438" height="30.4667"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="308" y="-121.59" width="49.1438" height="30.4667"/>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="332.572" y="-104.29">
+ <tspan x="332.572" y="-104.29">GBE</tspan>
+ </text>
+ </g>
+ <text font-size="7.15705" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="268.961" y="-148.674">
+ <tspan x="268.961" y="-148.674">0x000000</tspan>
+ </text>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="269.152" y="-120.399">
+ <tspan x="269.152" y="-120.399">0x001000</tspan>
+ </text>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="269.155" y="-90.6472">
+ <tspan x="269.155" y="-90.6472">0x003000</tspan>
+ </text>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="269.461" y="-56.4289">
+ <tspan x="269.461" y="-56.4289">0x020000</tspan>
+ </text>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="270.008" y="0.198407">
+ <tspan x="270.008" y="0.198407">0x800000</tspan>
+ </text>
+ <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 380.877 -151.013 C 401.876,-151.013 379.377,-73.513 400.627,-72.513"/>
+ <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 381.377 -0.763268 C 395.238,-0.763268 387.016,-72.763 400.877,-72.763"/>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="406.127" y="-68.513">
+ <tspan x="406.127" y="-68.513">Flash #0</tspan>
+ </text>
+ <g>
+ <g>
+ <g>
+ <rect style="fill: #ffffff" x="308.189" y="-90.5898" width="49.1438" height="33.4161"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308.189" y="-90.5898" width="49.1438" height="33.4161"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="308.189" y="-90.5898" width="49.1438" height="33.4161"/>
+ </g>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x="308.189" y="-90.5898" width="49.1438" height="32.8215"/>
+ <text font-size="6.77323" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="331.572" y="-70.23">
+ <tspan x="331.572" y="-70.23">ME</tspan>
+ </text>
+ </g>
+</svg>
diff --git a/Documentation/northbridge/intel/sandybridge/me_cleaner.md b/Documentation/northbridge/intel/sandybridge/me_cleaner.md
index 1086e7e091..b457dcdd3c 100644
--- a/Documentation/northbridge/intel/sandybridge/me_cleaner.md
+++ b/Documentation/northbridge/intel/sandybridge/me_cleaner.md
@@ -5,7 +5,7 @@ from the ME firmware partition. In this state the ME errors out and doesn't
operate any more.
**Using a 'cleaned' ME partition may lead to issues and its use should be
-carefully evaulated.**
+carefully evaluated.**
## Observations with 'cleaned' ME
@@ -18,3 +18,67 @@ carefully evaulated.**
Always test with unmodified IFD and ME section before reporting bugs to the
coreboot project.
+
+## Tutorial reducing the Intel ME firmware size
+
+By default the cleaned ME firmware will still occupy the same space in
+the firmware image. It's possible to change the firmware partition layout
+and reclaim the space for the use by coreboot.
+With the reduced Intel ME firmware the `ifd`, `gbe` and `me` regions require
+less than 128 KiB of space in the ROM, which leaves the remaining for the
+`bios` region.
+
+This tutorial will guide you through the steps necessary.
+
+### 1. Obtain a full ROM
+
+You need a full and working ROM with a full Intel ME firmware.
+
+### 2. Running me_cleaner
+
+You need to run the *me_cleaner* on a full ROM, here called `fulldump.rom`:
+The full ROM contains:
+* IFD
+* fully working Intel ME
+* GbE (optional)
+* BIOS (any firmware)
+
+Running the command will generate two new files:
+```console
+./util/me_cleaner/me_cleaner.py -D patched_desciptor.bin -M stripped_me.bin fulldump.rom -t -r -S
+```
+
+The generated files are:
+* a patched IFD called `patched_desciptor.bin`
+* stripped Intel ME called `stripped_me.bin`
+
+The patched IFD has the *AltMeDisable* bit set and a modified flash layout.
+
+
+*Note:* coreboot allows to select `CONFIG_ME_CLEANER` as part of the
+build-process, but that doesn't rework the flash layout, it only removes
+files from ME and sets the *AltMeDisable*-bit.
+
+### 3. Build coreboot
+
+1. Now include the two new files from the previous step into coreboot's
+ build system.
+2. Make sure to also increase the CBFS size
+ * 0x7E0000 for a 8MiB ROM
+ * 0xBE0000 for a 12MiB ROM
+ * 0xFE0000 for a 16MiB ROM
+3. Make sure to **not** enable me_cleaner in Kconfig again as
+ you have already run it
+
+### 4. Flashing the ROM
+
+As you have modified the layout you need to write the **full ROM** to flash
+using an [external programmer].
+Make sure to include all partitions into the ROM:
+* IFD
+* EC (might be unused)
+* GbE (might be unused)
+* ME
+* BIOS
+
+[external programmer]: ../../../flash_tutorial/index.md