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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-16 14:29:24 +0100 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-21 02:37:04 +0000 |
| commit | 08d8dd3bd3c08ae99b40ea5ee14c3c54a6546590 (patch) | |
| tree | 249f28499c54dfdb3e6673ffd3ca3c38db9291cb | |
| parent | 9c581a74f6bcf97fbbd8af9c37acebf61acb8bbb (diff) | |
| download | coreboot-08d8dd3bd3c08ae99b40ea5ee14c3c54a6546590.tar.xz | |
soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 8965b3b81f..00623a86af 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -230,8 +230,8 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) configure_dpr(dev); union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; if (dpr.size) { - uint32_t dpr_base_k = (dpr.top - dpr.size) << 10; - uint32_t dpr_size_k = dpr.size << 10; + uint64_t dpr_base_k = (dpr.top - dpr.size) << 10; + uint64_t dpr_size_k = dpr.size << 10; reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k); LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k); } |