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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 17:35:32 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-17 02:36:16 +0100 |
| commit | 1072e7dcc30895f850143450504b78a4135978b6 (patch) | |
| tree | acb2af2ec8ddcce177ca924ed6411e564f2ad3c2 | |
| parent | 6598b91fe34fe9e6e6fbea592ead5e4fc2900551 (diff) | |
| download | coreboot-1072e7dcc30895f850143450504b78a4135978b6.tar.xz | |
soc/intel/braswell: Add int to unsigned
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build for cyan
Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18870
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/lpe.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/pcie.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/southcluster.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/spi.c | 6 |
5 files changed, 9 insertions, 7 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 57590c2ba9..4d7b90688c 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -339,7 +339,8 @@ struct chip_operations soc_intel_braswell_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(device_t dev, unsigned int vendor, + unsigned int device) { printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", __FILE__, __func__, dev_name(dev), vendor, device); diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 4662b4324e..40bda1252c 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -44,7 +44,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(device_t dev, u32 *field, unsigned int index) { struct resource *res; diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 1d70eb06c6..9ea154aab9 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -159,7 +159,8 @@ static void pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(device_t dev, unsigned int vid, + unsigned int did) { printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", __FILE__, __func__, dev_name(dev), vid, did); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 12bc930456..4e4d157714 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -330,7 +330,7 @@ static void hda_work_around(device_t dev) static int place_device_in_d3hot(device_t dev) { - unsigned offset; + unsigned int offset; printk(BIOS_SPEW, "%s/%s ( %s )\n", __FILE__, __func__, dev_name(dev)); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 86b335107b..514e70e418 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -90,7 +90,7 @@ typedef struct ich_spi_controller { uint16_t *optype; uint32_t *addr; uint8_t *data; - unsigned databytes; + unsigned int databytes; uint8_t *status; uint16_t *control; } ich_spi_controller; @@ -290,13 +290,13 @@ typedef struct spi_transaction { uint32_t offset; } spi_transaction; -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) { trans->out += bytes; trans->bytesout -= bytes; } -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) { trans->in += bytes; trans->bytesin -= bytes; |