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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-06 14:00:05 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-06 20:53:45 +0100 |
| commit | 140087f84fbed117686c15e9d0c7c6921d494059 (patch) | |
| tree | 7ca17ca92f87c1d2dd72c15126a37e148a1e0d7e | |
| parent | cd6d281fbee4de59aad1e76f1ed9afeb19ce9a0b (diff) | |
| download | coreboot-140087f84fbed117686c15e9d0c7c6921d494059.tar.xz | |
CPU: Declare cpu_phys_address_size() for all arch
Resource allocator and 64-bit PCI BARs will need it and
PCI use is not really restricted to x86.
Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17733
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 1 | ||||
| -rw-r--r-- | src/arch/x86/postcar_loader.c | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 1 | ||||
| -rw-r--r-- | src/include/cpu/cpu.h | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/ram_calc.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/util.c | 1 |
6 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 578bb07369..a923d8e48e 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -161,7 +161,6 @@ static inline unsigned int cpuid_edx(unsigned int op) int cpu_cpuid_extended_level(void); int cpu_have_cpuid(void); -int cpu_phys_address_size(void); void smm_init(void); void smm_lock(void); diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 948e4459fa..23f33d556d 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -16,6 +16,7 @@ #include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 7eb115ca96..c82f3b9831 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -18,6 +18,7 @@ #include <cbfs.h> #include <console/console.h> #include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 3256a83ec6..dd89a8cc88 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -8,6 +8,7 @@ void cpu_initialize(unsigned int cpu_index); struct bus; void initialize_cpus(struct bus *cpu_bus); void asmlinkage secondary_cpu_init(unsigned int cpu_index); +int cpu_phys_address_size(void); #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver"))) #ifndef __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 026531a250..0253defa8e 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -19,6 +19,7 @@ #include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> +#include <cpu/cpu.h> #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index 2d3a34a63a..3aadd6b54e 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -15,6 +15,7 @@ #include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <stddef.h> |