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authorJamie Chen <jamie.chen@intel.com>2020-02-03 17:39:44 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-04 16:12:51 +0000
commit16a23c0e101ae567b9b32aeb1d643f4b0a992cf0 (patch)
tree1d671332a8018a9b4fc77b7c092a64bafe8168ea
parentbd3c1c7dd87aea3d9f06ed2cce4268104fae9c95 (diff)
downloadcoreboot-16a23c0e101ae567b9b32aeb1d643f4b0a992cf0.tar.xz
mb/google/puff: Enable HECI communication
Set HeciEnabled = 1 on puff device tree to turn on Intel ME communication interface. BUG=b:143232330 BRANCH=None TEST=Build puff and boot up OS. ran lspci and confirmed there is a HECI device. 00:16.0 Communication controller: Intel Corporation Device 02e0 Change-Id: I2debb885022ae31e395869d014a91824b5dd980c Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
-rw-r--r--src/mainboard/google/hatch/variants/puff/overridetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index d84b36986d..4ffbfed2b2 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -1,4 +1,6 @@
chip soc/intel/cannonlake
+ # Enable heci communication
+ register "HeciEnabled" = "1"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,