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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-27 15:27:18 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-22 13:08:57 +0000 |
| commit | 1dce59044795613d957ad59d7faac41ff46ea754 (patch) | |
| tree | 0e1d2a3617454891086f73e818c94d4867850d98 | |
| parent | 105e36824782e7a30b071dc589454b3a8ad720a8 (diff) | |
| download | coreboot-1dce59044795613d957ad59d7faac41ff46ea754.tar.xz | |
mb/intel/d510mo: Use common ramstage driver to configure the ck505
TESTED, the screen doesn't jiggle (caused by wrong clock on reset
default clockgen configuration)
Change-Id: Icfa22daf90f9e2eff13b4fc5994664e96903dd1e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/intel/d510mo/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/d510mo/devicetree.cb | 14 | ||||
| -rw-r--r-- | src/mainboard/intel/d510mo/romstage.c | 5 |
3 files changed, 14 insertions, 6 deletions
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 0f747cc878..b2ce4b650c 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select DRIVERS_I2C_CK505 config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c5b885ff85..473303842e 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -92,7 +92,19 @@ chip northbridge/intel/pineview # Northbridge end device pci 1f.1 off end device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMbus + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 # ICS9EPRS525 + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff }" + register "regs" = "{ 0x61, 0xd9, 0xfe, 0xff, + 0xff, 0x00, 0x00, 0x01, + 0x03, 0x25, 0x83, 0x17, + 0x0d }" + device i2c 69 on end + end + end device pci 1f.4 off end device pci 1f.5 off end device pci 1f.6 off end diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 502d22078e..c6406e6f9f 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -102,9 +102,6 @@ static void rcba_config(void) void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; - const u8 clockgen_block[13] = { 0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00, - 0x00, 0x01, 0x03, 0x25, 0x83, 0x17, - 0x0d }; int cbmem_was_initted; int s3resume = 0; int boot_path; @@ -128,8 +125,6 @@ void mainboard_romstage_entry(unsigned long bist) report_bist_failure(bist); enable_smbus(); - smbus_block_write(0x69, 0, 13, clockgen_block); - pineview_early_initialization(); post_code(0x30); |