diff options
| author | Lin Huang <hl@rock-chips.com> | 2018-01-31 10:28:47 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2018-02-02 22:18:28 +0000 |
| commit | 1df0c570c33f09ba47138d6d9cdec66a742b4e42 (patch) | |
| tree | 23d366a61166d42b0089d5f2ba4cf0d04e573b10 | |
| parent | 1cce10ed5ccabc6d2eb6360cdc1f9051196c484b (diff) | |
| download | coreboot-1df0c570c33f09ba47138d6d9cdec66a742b4e42.tar.xz | |
rockchip/rk3399: extend delay between saradc power up and start command
We found when ambient temperature low, with now saradc frequency and
delay between saradc power up and start command, there may get wrong
adc value, then get the wrong ramid or boardid, so lower the saradc frequency
and add the delay time between power up and start command.
BUG=b:70692504
BRANCH=gru
TEST=test on Dru in 0C temperature, always get right adc value
Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/rockchip/rk3399/saradc.c | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index d70c9667fc..7c25936e20 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -46,20 +46,12 @@ struct rk3399_saradc_regs *rk3399_saradc = (void *)SARADC_BASE; /* SARADC_DATA, 10[0:9] bits */ #define DATA_MASK 0x3FF -/* The max clk is 13 MHz, we also recommended that - * the sample rate(=clk/13) should be > 500KHz. - * So choose 8MHz, that 8MHz/13 = 615.38KHz > 500KHz. - */ -#define SARADC_HZ (8*MHz) - -/* TRM(V0.3 Part 1 Page 366) said there is a delay between - * power up and start command, default value is 2 src clk. - * Let delay 2 src clk here, in ns(udelay). - */ -#define SARADC_DELAY_PU (1 * 1000 * 1000 * 1000 / SARADC_HZ * 2) +#define SARADC_HZ (4*MHz) #define SARADC_MAX_CHANNEL 6 +#define SARADC_DELAY_PU (1 * 1000 * 1000 * 1000 / SARADC_HZ * 4) + u32 get_saradc_value(u32 chn) { u32 adc_value; |