diff options
| author | Morgan Tsai <my_tsai@sis.com> | 2007-11-02 16:09:58 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2007-11-02 16:09:58 +0000 |
| commit | 218c26533dc5864dd33387e75476f7c8daf3570c (patch) | |
| tree | 46d2a55ef0a2914097faabf1d74e74f13d895af4 | |
| parent | 7162cf7278f1489cbe4b56a7fb95b713735387d9 (diff) | |
| download | coreboot-218c26533dc5864dd33387e75476f7c8daf3570c.tar.xz | |
1. vgabios removed, will go to extra repository
2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
src/include/device/pci_ids.h
4. Trim trailing spaces for all files
Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
32 files changed, 867 insertions, 1766 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ac9435ab8d..0e62bfb029 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -312,11 +312,11 @@ #define PCI_DEVICE_ID_NS_CS5535_AUDIO 0x002e #define PCI_DEVICE_ID_NS_CS5535_USB 0x002f #define PCI_DEVICE_ID_NS_CS5535_GX2VGA 0x0030 -#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 -#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 #define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 -#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 -#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 #define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001 @@ -652,7 +652,7 @@ #define PCI_VENDOR_ID_ANIGMA 0x1051 #define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 - + #define PCI_VENDOR_ID_EFAR 0x1055 #define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 @@ -1223,7 +1223,7 @@ #define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 #define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 #define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 - + #define PCI_VENDOR_ID_CYCLONE 0x113c #define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 @@ -1726,7 +1726,7 @@ #define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 #define PCI_VENDOR_ID_ZOLTRIX 0x15b0 -#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 #define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_DEVICE_ID_PDC_1841 0x1841 @@ -1967,26 +1967,26 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 #define PCI_DEVICE_ID_INTEL_82801DBM_1E0 0x2448 -#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc -#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca -#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3 -#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5 +#define PCI_DEVICE_ID_INTEL_82801DBM_1F0 0x24cc +#define PCI_DEVICE_ID_INTEL_82801DBM_1F1 0x24ca +#define PCI_DEVICE_ID_INTEL_82801DBM_1F3 0x24c3 +#define PCI_DEVICE_ID_INTEL_82801DBM_1F5 0x24c5 #define PCI_DEVICE_ID_INTEL_82801DBM_1F6 0x24c6 -#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2 -#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4 +#define PCI_DEVICE_ID_INTEL_82801DBM_1D0 0x24c2 +#define PCI_DEVICE_ID_INTEL_82801DBM_1D1 0x24c4 #define PCI_DEVICE_ID_INTEL_82801DBM_1D2 0x24c7 #define PCI_DEVICE_ID_INTEL_82801DBM_1D7 0x24cd -#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e -#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0 -#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db +#define PCI_DEVICE_ID_INTEL_82801ER_1E0 0x244e +#define PCI_DEVICE_ID_INTEL_82801ER_1F0 0x24d0 +#define PCI_DEVICE_ID_INTEL_82801ER_1F1 0x24db #define PCI_DEVICE_ID_INTEL_82801ER_1F2 0x24d1 -#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df -#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3 -#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5 +#define PCI_DEVICE_ID_INTEL_82801ER_1F2_R 0x24df +#define PCI_DEVICE_ID_INTEL_82801ER_1F3 0x24d3 +#define PCI_DEVICE_ID_INTEL_82801ER_1F5 0x24d5 #define PCI_DEVICE_ID_INTEL_82801ER_1F6 0x24d6 -#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2 -#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4 +#define PCI_DEVICE_ID_INTEL_82801ER_1D0 0x24d2 +#define PCI_DEVICE_ID_INTEL_82801ER_1D1 0x24d4 #define PCI_DEVICE_ID_INTEL_82801ER_1D2 0x24d7 #define PCI_DEVICE_ID_INTEL_82801ER_1D3 0x24de #define PCI_DEVICE_ID_INTEL_82801ER_1D7 0x24dd @@ -2076,55 +2076,33 @@ #define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 #define PCI_VENDOR_ID_SIS 0x1039 +#define PCI_DEVICE_ID_SIS_AGP 0x0002 +#define PCI_DEVICE_ID_SIS_SIS761 0x0761 #define PCI_DEVICE_ID_SIS_SIS966_SB 0x0966 +#define PCI_DEVICE_ID_SIS_SIS966_ISA 0x0966 #define PCI_DEVICE_ID_SIS_SIS966_LPC 0x0966 -#define PCI_DEVICE_ID_SIS_SIS966_SLAVE 0x0361 -#define PCI_DEVICE_ID_SIS_SIS966_LPC_2 0x0362 -#define PCI_DEVICE_ID_SIS_SIS966_LPC_3 0x0363 -#define PCI_DEVICE_ID_SIS_SIS966_LPC_4 0x0364 -#define PCI_DEVICE_ID_SIS_SIS966_LPC_5 0x0365 -#define PCI_DEVICE_ID_SIS_SIS966_LPC_6 0x0366 -#define PCI_DEVICE_ID_SIS_SIS966_PRO 0x0367 #define PCI_DEVICE_ID_SIS_SIS966_SM2 0x0368 -#define PCI_DEVICE_ID_SIS_SIS966_IDE 0x5513 -#define PCI_DEVICE_ID_SIS_SIS966_SATA0 0x1183 -#define PCI_DEVICE_ID_SIS_SIS966_SATA1 0x037F -#define PCI_DEVICE_ID_SIS_SIS966_NIC0 0x190 -#define PCI_DEVICE_ID_SIS_SIS966_NIC1 0x191 -#define PCI_DEVICE_ID_SIS_SIS966_NIC2 0x192 -#define PCI_DEVICE_ID_SIS_SIS966_NIC3 0x193 -#define PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE 0x0373 -#define PCI_DEVICE_ID_SIS_SIS966_AZA 0x7502 +#define PCI_DEVICE_ID_SIS_SIS966_HT 0x0369 #define PCI_DEVICE_ID_SIS_SIS966_PCI 0x0370 +#define PCI_DEVICE_ID_SIS_SIS966_SMB 0x25a4 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_A_B 0x000A #define PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C 0x1002 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_E 0x1003 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_A 0x1004 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_F 0x1005 #define PCI_DEVICE_ID_SIS_SIS966_PCIE_D 0x1006 -#define PCI_DEVICE_ID_SIS_SIS966_HT 0x0369 -#define PCI_DEVICE_ID_SIS_SIS966_TRIM 0x036A -#define PCI_DEVICE_ID_SIS_SIS966_PMU 0x036B -#define PCI_DEVICE_ID_SIS_SIS966_NORTHBRIDGE 0x0756 -#define PCI_DEVICE_ID_SIS_SIS966_ISA 0x0966 #define PCI_DEVICE_ID_SIS_SIS966_AC97_AUDIO 0x7012 #define PCI_DEVICE_ID_SIS_SIS966_AC97_MODEM 0x7013 -#define PCI_DEVICE_ID_SIS_SIS966_EHCI 0x7002 #define PCI_DEVICE_ID_SIS_SIS966_IDE 0x5513 -#define PCI_DEVICE_ID_SIS_SIS966_SMB 0x25a4 +#define PCI_DEVICE_ID_SIS_SIS966_SATA0 0x1183 +#define PCI_DEVICE_ID_SIS_SIS966_NIC0 0x0190 +#define PCI_DEVICE_ID_SIS_SIS966_NIC1 0x0191 +#define PCI_DEVICE_ID_SIS_SIS966_AZA 0x7502 #define PCI_DEVICE_ID_SIS_SIS966_USB 0x7001 -#define PCI_DEVICE_ID_SIS_SIS966_USB2 0x7001 -#define PCI_DEVICE_ID_SIS_SIS966_USB3 0x7001 -#define PCI_DEVICE_ID_SIS_SIS966_SATA 0x1183 -#define PCI_DEVICE_ID_SIS_SIS966_SATA_R 0x1183 -#define PCI_DEVICE_ID_SIS_SIS966_PIC1 0x25ac -#define PCI_DEVICE_ID_SIS_SIS966_BRIDGE1C 0x0966 -#define PCI_DEVICE_ID_SIS_AGP 0x0002 -#define PCI_DEVICE_ID_SIS_SIS761 0x0761 -#define PCI_DEVICE_ID_SIS_SIS756 0x0756 +#define PCI_DEVICE_ID_SIS_SIS966_USB2 0x7002 /* OLD USAGE FOR LINUXBIOS */ -#define PCI_VENDOR_ID_ACER 0x10b9 +#define PCI_VENDOR_ID_ACER 0x10b9 #define PCI_DEVICE_ID_ACER_M1535D 0x1533 #define PCI_DEVICE_ID_AMD_761_0 0x700E diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb index 6974de01bc..e0cf14c5de 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -239,15 +239,12 @@ chip northbridge/amd/amdk8/root_complex # devices on link 0, link 0 == LDT 0 chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge - ################################################# - device pci 1.0 on # AGP bridge + device pci 1.0 on # AGP bridge chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end register "rom_address" = "0xfff80000" end end - ################################################# - ## device pci 1.0 on end # PCIE device pci 2.0 on # LPC chip superio/ite/it8716f device pnp 2e.0 off # Floppy @@ -272,12 +269,12 @@ chip northbridge/amd/amdk8/root_complex io 0x62 = 0x230 irq 0x70 = 9 end - device pnp 2e.5 off # Keyboard + device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 off # Mouse + device pnp 2e.6 on # Mouse irq 0x70 = 12 end device pnp 2e.8 off # MIDI @@ -291,30 +288,27 @@ chip northbridge/amd/amdk8/root_complex end end - device pci 2.5 on end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183) - device pci 6.0 off end # SB PCIE1 (SiS000A) - device pci 7.0 off end # SB PCIE2 (SiS000A) - device pci 9.0 off end # PCI E 6 - device pci a.0 off end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 off end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # Hda + device pci 2.5 off end # IDE (SiS5513) + device pci 2.6 off end # Modem (SiS7013) + device pci 2.7 off end # Audio (SiS7012) + device pci 3.0 on end # USB (SiS7001,USB1.1) + device pci 3.1 on end # USB (SiS7001,USB1.1) + device pci 3.3 on end # USB (SiS7002,USB2.0) + device pci 4.0 on end # NIC (SiS191) + device pci 5.0 on end # SATA (SiS1183,IDE Mode) + device pci 6.0 off end # PCI-E (SiS000A) + device pci 7.0 off end # PCI-E (SiS000A) + device pci a.0 off end + device pci b.0 off end + device pci c.0 off end + device pci d.0 off end + device pci e.0 off end + device pci f.0 off end # HD Audio (SiS7502) - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - #register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - #register "mac_eeprom_addr" = "0x51" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end end # device pci 18.0 device pci 18.0 on end # Link 1 @@ -328,14 +322,14 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/generic/debug # device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io # end end #root_complex diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb index a7832bc078..e081e2b0a2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -1,25 +1,25 @@ -## +## ## This file is part of the LinuxBIOS project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) ## Written by Morgan Tsai <my_tsai@sis.com> for SiS. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE @@ -197,7 +197,7 @@ default LIFT_BSP_APIC_ID=1 #CHIP_NAME ? default CONFIG_CHIP_NAME=1 -#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. +#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000 #1G @@ -253,8 +253,8 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="SiS" -default MAINBOARD_VENDOR="SIS" +default MAINBOARD_PART_NUMBER="ga_2761gxdk" +default MAINBOARD_VENDOR="GIGABYTE" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 @@ -294,7 +294,7 @@ default CONFIG_ROM_PAYLOAD = 1 ### ### Defaults of options that you may want to override in the target config file -### +### ## ## The default compiler @@ -304,7 +304,7 @@ default HOSTCC="gcc" ## ## Disable the gdb stub by default -## +## default CONFIG_GDB_STUB=0 ## @@ -335,15 +335,15 @@ default TTYS0_LCS=0x3 ## ### Select the linuxBIOS loglevel ## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details ## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=8 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c index 7e4eddaa5c..06bb3f26f8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c @@ -27,7 +27,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c index 732027adca..b52f1f2e8f 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -46,7 +46,7 @@ #endif #define DBGP_DEFAULT 7 - + #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -95,7 +95,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #include "southbridge/sis/sis966/sis966_early_ctrl.c" @@ -126,7 +126,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "sdram/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -171,13 +171,13 @@ static void sio_setup(void) uint8_t byte; byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); @@ -237,15 +237,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if HAVE_FAILOVER_BOOT==1 +#if HAVE_FAILOVER_BOOT==1 #if USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); + failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else #if USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); + failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); #endif @@ -281,7 +281,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_mb_resource_map(); uart_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -340,7 +340,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= sis966_early_setup_x(); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { @@ -353,8 +352,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); sis_init_stage1(); - enable_smbus(); - + enable_smbus(); + memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output diff --git a/src/mainboard/gigabyte/ga_2761gxdk/chip.h b/src/mainboard/gigabyte/ga_2761gxdk/chip.h index a93dc54917..66ddb8c353 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/chip.h +++ b/src/mainboard/gigabyte/ga_2761gxdk/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the LinuxBIOS project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) * Written by Morgan Tsai <my_tsai@sis.com> for SiS. * diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout index 84a5c52278..9e79be1721 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout +++ b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the LinuxBIOS project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index d8b0c0ab5a..acab382ac2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned apicid_sis966; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -63,7 +63,7 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned bus_type[256]; +unsigned bus_type[256]; extern void get_sblk_pci1234(void); @@ -96,13 +96,13 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_sis966[i] = 0; } - + for(i=0;i<256; i++) { bus_type[i] = 0; } bus_type[0] = 1; //pci - + bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_type[bus_sis966[0]] = 1; @@ -140,8 +140,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_sis966 = apicid_base+0; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c index c87b9d6954..c19c9ac263 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c @@ -32,7 +32,7 @@ #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> - +#include <device/pci_ids.h> #include <cpu/amd/amdk8_sysconf.h> static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, @@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%x...\n", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -88,8 +88,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->exclusive_irqs = 0; - pirq->rtr_vendor = 0x10de; - pirq->rtr_device = 0x0370; + pirq->rtr_vendor = PCI_VENDOR_ID_SIS; + pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_PCI; pirq->miniport_data = 0; @@ -124,11 +124,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) } printk_debug("Setting Onboard SiS Southbridge\n"); -// dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE) -// pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1 -1 + + /* + * Non-layout for GA-2761GX + * + dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE) + pci_write_config8(dev, 0x3C, 0x0A); + */ + + dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1 pci_write_config8(dev, 0x3C, 0x0B); - dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1 -2 + dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1 pci_write_config8(dev, 0x3C, 0x05); dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0 pci_write_config8(dev, 0x3C, 0x0A); @@ -136,12 +142,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) pci_write_config8(dev, 0x3C, 0x05); dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA) pci_write_config8(dev, 0x3C, 0x0B); -// dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E -// pci_write_config8(dev, 0x3C, 0x0A); -// dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E -// pci_write_config8(dev, 0x3C, 0x0A); + + /* + * Non-layout for GA-2761GX + * + dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E + pci_write_config8(dev, 0x3C, 0x0A); + dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E + pci_write_config8(dev, 0x3C, 0x0A); dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia pci_write_config8(dev, 0x3C, 0x05); + */ } //pci bridge diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c index b8b6a189f9..bc448f136d 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c @@ -1,8 +1,6 @@ /* * This file is part of the LinuxBIOS project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghailu@amd.com> for AMD. * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) * Written by Morgan Tsai <my_tsai@sis.com> for SiS. * diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index ab54d0c361..70dc525add 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -33,7 +33,7 @@ extern unsigned char bus_sis966[8]; //1 extern unsigned apicid_sis966; -extern unsigned bus_type[256]; +extern unsigned bus_type[256]; void *smp_write_config_table(void *v) { @@ -80,7 +80,7 @@ void *smp_write_config_table(void *v) device_t dev; struct resource *res; uint32_t dword; - + dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); @@ -99,7 +99,7 @@ void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sis966, 0x1); @@ -135,7 +135,7 @@ void *smp_write_config_table(void *v) } } - for(j=0; j<2; j++) + for(j=0; j<2; j++) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[1], ((0x06+j)<<2)|i, apicid_sis966, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c index 7e23ad9cc9..8d30b5e052 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/southbridge/sis/sis966/Config.lb b/src/southbridge/sis/sis966/Config.lb index 565de1aa81..77da6f5787 100644 --- a/src/southbridge/sis/sis966/Config.lb +++ b/src/southbridge/sis/sis966/Config.lb @@ -1,27 +1,26 @@ -## +## ## This file is part of the LinuxBIOS project. -## +## ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) ## Written by Morgan Tsai <my_tsai@sis.com> for SiS. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## config chip.h -#driver sis_agp.o -driver sisnb.o +driver sis761.o driver sis966.o driver sis966_usb.o driver sis966_lpc.o diff --git a/src/southbridge/sis/sis966/chip.h b/src/southbridge/sis/sis966/chip.h index 0bda235533..fe31c7ea7a 100644 --- a/src/southbridge/sis/sis966/chip.h +++ b/src/southbridge/sis/sis966/chip.h @@ -1,8 +1,6 @@ /* * This file is part of the LinuxBIOS project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) * Written by Morgan Tsai <my_tsai@sis.com> for SiS. * diff --git a/src/southbridge/sis/sis966/romstrap.inc b/src/southbridge/sis/sis966/romstrap.inc index e1773b6200..49d932ade0 100644 --- a/src/southbridge/sis/sis966/romstrap.inc +++ b/src/southbridge/sis/sis966/romstrap.inc @@ -43,28 +43,16 @@ linkedlist: .long 0xFFFFFFFF // 28h .long 0xFFFFFFFF // 2Ch -// MAC address -------------------------------- 0x7FFC0h .long 0x56341200 // 30h, MAC address low 4 byte ---> keep it in 0xffffffc0 .long 0x00009078 // 34h, MAC address high 4 byte .long 0x002309CE // 38h, UUID low 4 byte .long 0x00E08100 // 3Ch, UUID high 4 byte - -// Firmware Trap -------------------------------- 0x7FFD0h -/* -//Firmware trap for SiS761+966 - .long 0x00402000 - .long 0x6043A800 - .long 0x00180000 - .long 0x1421C402 -*/ - -//Firmware trap for SiS756+966 ---> keep it in 0xffffffd0 - .long 0x00402000 - .long 0xE043A800 - .long 0x00180000 - .long 0x1421C402 + .long 0x00402000 //Firmware trap for SiS761+966 + .long 0xE043A800 + .long 0x00180000 + .long 0x1421C402 rspointers: .long rstables // It will be 0xffffffe0 diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c new file mode 100644 index 0000000000..e622d9f7cf --- /dev/null +++ b/src/southbridge/sis/sis966/sis761.c @@ -0,0 +1,191 @@ +/* + * This file is part of the LinuxBIOS project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Turn off machine check triggers when reading + * pci space where there are no devices. + * This is necessary when scaning the bus for + * devices which is done by the kernel + * + * written in 2003 by Eric Biederman + * + * - Athlon64 workarounds by Stefan Reinauer + * - "reset once" logic by Yinghai Lu + * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) + * Written by Morgan Tsai <my_tsai@sis.com> for SiS. + * + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <part/hard_reset.h> +#include <pc80/mc146818rtc.h> +#include <bitops.h> +#include <cpu/amd/model_fxx_rev.h> + +//#include "amdk8.h" + +#include <arch/io.h> + +/** + * @brief Read resources for AGP aperture + * + * @param + * + * There is only one AGP aperture resource needed. The resoruce is added to + * the northbridge of BSP. + * + * The same trick can be used to augment legacy VGA resources which can + * be detect by generic pci reousrce allocator for VGA devices. + * BAD: it is more tricky than I think, the resource allocation code is + * implemented in a way to NOT DOING legacy VGA resource allcation on + * purpose :-(. + */ + + +typedef struct msr_struct +{ + unsigned lo; + unsigned hi; +} msr_t; + +static inline msr_t rdmsr(unsigned index) +{ + msr_t result; + result.lo = 0; + result.hi = 0; + return result; +} + + + +static void sis761_read_resources(device_t dev) +{ + struct resource *resource; + unsigned char iommu; + /* Read the generic PCI resources */ + printk_debug("sis761_read_resources\n"); + pci_dev_read_resources(dev); + + /* If we are not the first processor don't allocate the gart apeture */ + if (dev->path.u.pci.devfn != PCI_DEVFN(0x0, 0)) { + return; + } + + + return; + + iommu = 1; + get_option(&iommu, "iommu"); + + if (iommu) { + /* Add a Gart apeture resource */ + resource = new_resource(dev, 0x94); + resource->size = iommu?AGP_APERTURE_SIZE:1; + resource->align = log2(resource->size); + resource->gran = log2(resource->size); + resource->limit = 0xffffffff; /* 4G */ + resource->flags = IORESOURCE_MEM; + } +} + +static void set_agp_aperture(device_t dev) +{ + struct resource *resource; + + return; + + resource = probe_resource(dev, 0x94); + if (resource) { + device_t pdev; + uint32_t gart_base, gart_acr; + + /* Remember this resource has been stored */ + resource->flags |= IORESOURCE_STORED; + + /* Find the size of the GART aperture */ + gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0); + + /* Get the base address */ + gart_base = ((resource->base) >> 25) & 0x00007fff; + + /* Update the other northbriges */ + pdev = 0; + while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { + /* Store the GART size but don't enable it */ + pci_write_config32(pdev, 0x90, gart_acr); + + /* Store the GART base address */ + pci_write_config32(pdev, 0x94, gart_base); + + /* Don't set the GART Table base address */ + pci_write_config32(pdev, 0x98, 0); + + /* Report the resource has been stored... */ + report_resource_stored(pdev, resource, " <gart>"); + } + } +} + +static void sis761_set_resources(device_t dev) +{ + printk_debug("sis761_set_resources ------->\n"); + /* Set the gart apeture */ +// set_agp_aperture(dev); + + /* Set the generic PCI resources */ + pci_dev_set_resources(dev); + printk_debug("sis761_set_resources <-------\n"); +} + +static void sis761_init(struct device *dev) +{ + uint32_t cmd, cmd_ref; + int needs_reset; + struct device *f0_dev, *f2_dev; + msr_t msr; + + + needs_reset = 0; + printk_debug("sis761_init: ---------->\n"); + + msr = rdmsr(0xC001001A); + pci_write_config16(dev, 0x8E, msr.lo >> 16); // Topbound + pci_write_config8(dev, 0x7F, 0x08); // ACPI Base + outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function + + printk_debug("sis761_init: <----------\n"); + printk_debug("done.\n"); +} + + +static struct device_operations sis761_ops = { + .read_resources = sis761_read_resources, + .set_resources = sis761_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sis761_init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static const struct pci_driver sis761_driver __pci_driver = { + .ops = &sis761_ops, + .vendor = PCI_VENDOR_ID_SIS, + .device = PCI_DEVICE_ID_SIS_SIS761, +}; diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c index b2ce896699..86033fe3bf 100644 --- a/src/southbridge/sis/sis966/sis966.c +++ b/src/southbridge/sis/sis966/sis966.c @@ -49,7 +49,7 @@ if ((lpc_dev->vendor != PCI_VENDOR_ID_SIS) || ( ) ) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16))) + if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16))) ) { lpc_dev = 0; } @@ -62,19 +62,18 @@ void sis966_enable(device_t dev) { device_t lpc_dev = 0; device_t sm_dev = 0; - unsigned index = 0; - unsigned index2 = 0; + uint16_t index = 0; + uint16_t index2 = 0; uint32_t reg_old, reg; uint8_t byte; - unsigned deviceid; - unsigned vendorid; + uint16_t deviceid; + uint16_t vendorid; + uint16_t devfn; struct southbridge_sis_sis966_config *conf; conf = dev->chip_info; int i; - unsigned devfn; - if(dev->device==0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; @@ -88,25 +87,16 @@ void sis966_enable(device_t dev) switch(deviceid) { case PCI_DEVICE_ID_SIS_SIS966_HT: return; - - case PCI_DEVICE_ID_SIS_SIS966_SM2://? - index = 16; break; case PCI_DEVICE_ID_SIS_SIS966_USB: devfn -= (1<<3); index = 8; break; - case PCI_DEVICE_ID_SIS_SIS966_EHCI: - devfn -= (1<<3); - index = 20; - break; -/* case PCI_DEVICE_ID_SIS_SIS966_USB3: + case PCI_DEVICE_ID_SIS_SIS966_USB2: devfn -= (1<<3); index = 20; break; -*/ - case PCI_DEVICE_ID_SIS_SIS966_NIC1: //two - case PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE://two + case PCI_DEVICE_ID_SIS_SIS966_NIC1: devfn -= (7<<3); index = 10; for(i=0;i<2;i++) { @@ -125,8 +115,7 @@ void sis966_enable(device_t dev) devfn -= (3<<3); index = 14; break; - case PCI_DEVICE_ID_SIS_SIS966_SATA0: //three - case PCI_DEVICE_ID_SIS_SIS966_SATA1: //three + case PCI_DEVICE_ID_SIS_SIS966_SATA0: devfn -= (4<<3); index = 22; i = (dev->path.u.pci.devfn) & 7; @@ -138,11 +127,7 @@ void sis966_enable(device_t dev) devfn -= (5<<3); index = 15; break; -// case PCI_DEVICE_ID_SIS_SIS966_PCIE_A: -// devfn -= (0x9<<3); // to LPC -// index2 = 9; -// break; - case PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C: //two + case PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C: devfn -= (0xa<<3); // to LPC index2 = 8; for(i=0;i<2;i++) { @@ -216,17 +201,8 @@ void sis966_enable(device_t dev) if(!sm_dev) return; final_reg = pci_read_config32(sm_dev, 0xe8); - final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9)); + final_reg &= ~0x0057cf00; pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first -#if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1<<0); - reg &= ~(0x3f<<4); - if (reg != reg_old) { - printk_debug("sis966.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); - } -#endif } if (!dev->enabled) { diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index 98a6aaaeb9..6595660f3b 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -1,8 +1,6 @@ /* * This file is part of the LinuxBIOS project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) * Written by Morgan Tsai <my_tsai@sis.com> for SiS. * @@ -24,6 +22,13 @@ #ifndef SIS966_H #define SIS966_H +#define DEBUG_AZA 0 +#define DEBUG_NIC 0 +#define DEBUG_IDE 0 +#define DEBUG_SATA 0 +#define DEBUG_USB 0 +#define DEBUG_USB2 0 + #include "chip.h" void sis966_enable(device_t dev); diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/sis966_aza.c index bb308a598f..4779099b70 100644 --- a/src/southbridge/sis/sis966/sis966_aza.c +++ b/src/southbridge/sis/sis966/sis966_aza.c @@ -32,10 +32,10 @@ #include "sis966.h" uint8_t SiS_SiS7502_init[7][3]={ -{0x04, 0xFF, 0x07}, -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x91}, +{0x04, 0xFF, 0x07}, +{0x2C, 0xFF, 0x39}, +{0x2D, 0xFF, 0x10}, +{0x2E, 0xFF, 0x91}, {0x2F, 0xFF, 0x01}, {0x04, 0xFF, 0x06}, {0x00, 0x00, 0x00} //End of table @@ -61,7 +61,7 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val) if(!count) return -1; - udelay(540); + udelay(500); return 0; } @@ -71,30 +71,29 @@ static int set_bits(uint8_t *port, uint32_t mask, uint32_t val) uint32_t dword; - + dword = readl(base + 0x68); dword=dword|(unsigned long)0x0002; writel(dword,base + 0x68); - do { - dword = readl(base + 0x68); + do { + dword = readl(base + 0x68); } while ((dword & 1)!=0); writel(verb, base + 0x60); - udelay(500); - dword = readl(base + 0x68); - dword =(dword |0x1); + udelay(500); + dword = readl(base + 0x68); + dword =(dword |0x1); writel(dword, base + 0x68); do { - udelay(120); + udelay(100); dword = readl(base + 0x68); } while ((dword & 3) != 2); dword = readl(base + 0x64); return dword; - + } -#if 1 static int codec_detect(uint8_t *base) { uint32_t dword; @@ -102,97 +101,31 @@ static int codec_detect(uint8_t *base) /* 1 */ // controller reset printk_debug("controller reset\n"); - + set_bits(base + 0x08, 1, 1); - + do{ - dword = readl(base + 0x08)&0x1; + dword = readl(base + 0x08)&0x1; if(idx++>1000) { printk_debug("controller reset fail !!! \n"); break;} } while (dword !=1); - + dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId - + if(dword==0) { printk_debug("No codec!\n"); return 0; } printk_debug("Codec ID = %lx\n", dword); - -#if 0 - /* 2 */ - dword = readl(base + 0x0e); - dword |= 7; - writel(dword, base + 0x0e); - - /* 3 */ - set_bits(base + 0x08, 1, 0); - /* 4 */ - set_bits(base + 0x08, 1, 1); - - /* 5 */ - dword = readl(base + 0xe); - dword &= 7; - - /* 6 */ - if(!dword) { - set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); - return 0; - } -#endif dword=0x1; return dword; } -#else - -static int codec_detect(uint8_t *base) -{ - uint32_t dword; - - /* 1 */ - set_bits(base + 0x08, 1, 1); - - /* 2 */ - dword = readl(base + 0x0e); - dword |= 7; - writel(dword, base + 0x0e); - - /* 3 */ - set_bits(base + 0x08, 1, 0); - - /* 4 */ - set_bits(base + 0x08, 1, 1); - - /* 5 */ - dword = readl(base + 0xe); - dword &= 7; - - /* 6 */ - if(!dword) { - set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); - return 0; - } - return dword; - -} - -#endif - -#if 1 -// For SiS demo board PinConfig static uint32_t verb_data[] = { -#if 0 - 00172083h, - 00172108h, - 001722ECh, - 00172310h, -#endif + //14 0x01471c10, 0x01471d40, @@ -255,79 +188,6 @@ static uint32_t verb_data[] = { 0x01f71f01, }; -#else -// orginal codec pin configuration setting - -static uint32_t verb_data[] = { -#if 0 - 0x00172001, - 0x001721e6, - 0x00172200, - 0x00172300, -#endif - - 0x01471c10, - 0x01471d44, - 0x01471e01, - 0x01471f01, -//1 - 0x01571c12, - 0x01571d14, - 0x01571e01, - 0x01571f01, -//2 - 0x01671c11, - 0x01671d60, - 0x01671e01, - 0x01671f01, -//3 - 0x01771c14, - 0x01771d20, - 0x01771e01, - 0x01771f01, -//4 - 0x01871c30, - 0x01871d9c, - 0x01871ea1, - 0x01871f01, -//5 - 0x01971c40, - 0x01971d9c, - 0x01971ea1, - 0x01971f02, -//6 - 0x01a71c31, - 0x01a71d34, - 0x01a71e81, - 0x01a71f01, -//7 - 0x01b71c1f, - 0x01b71d44, - 0x01b71e21, - 0x01b71f02, -//8 - 0x01c71cf0, - 0x01c71d11, - 0x01c71e11, - 0x01c71f41, -//9 - 0x01d71c3e, - 0x01d71d01, - 0x01d71e83, - 0x01d71f99, -//10 - 0x01e71c20, - 0x01e71d41, - 0x01e71e45, - 0x01e71f01, -//11 - 0x01f71c50, - 0x01f71d91, - 0x01f71ec5, - 0x01f71f01, -}; - -#endif static unsigned find_verb(uint32_t viddid, uint32_t **verb) { if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; @@ -370,17 +230,6 @@ static void codec_init(uint8_t *base, int addr) /* 3 */ for(i=0; i<verb_size; i++) { send_verb(base,verb[i]); -#if 0 - do { - dword = readl(base + 0x68); - } while (dword & 1); - - writel(verb[i], base + 0x60); - - do { - dword = readl(base + 0x68); - } while ((dword & 3) != 2); -#endif } printk_debug("verb loaded!\n"); } @@ -398,45 +247,50 @@ static void codecs_init(uint8_t *base, uint32_t codec_mask) static void aza_init(struct device *dev) { - uint8_t *base; - struct resource *res; - uint32_t codec_mask; + uint8_t *base; + struct resource *res; + uint32_t codec_mask; + print_debug("AZALIA_INIT:---------->\n"); //-------------- enable AZA (SiS7502) ------------------------- { - uint8_t temp8; - int i=0; - while(SiS_SiS7502_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); - temp8 &= SiS_SiS7502_init[i][1]; - temp8 |= SiS_SiS7502_init[i][2]; - pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); - i++; - }; + uint8_t temp8; + int i=0; + while(SiS_SiS7502_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); + temp8 &= SiS_SiS7502_init[i][1]; + temp8 |= SiS_SiS7502_init[i][2]; + pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); + i++; + }; } //----------------------------------------------------------- -// put audio to D0 state -pci_write_config8(dev, 0x54,0x00); + // put audio to D0 state + pci_write_config8(dev, 0x54,0x00); -#if 0 +#if DEBUG_AZA { - int i; - printk_debug("Azalia PCI config \n"); - for(i=0;i<0xFF;i+=4) - { - if((i%16)==0) - { - print_debug("\r\n");print_debug_hex8(i);print_debug(" "); + int i; + + print_debug("****** Azalia PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\r\n"); + print_debug("\r\n"); } -#endif +#endif res = find_resource(dev, 0x10); if(!res) @@ -452,24 +306,7 @@ pci_write_config8(dev, 0x54,0x00); codecs_init(base, codec_mask); } -#if 0 -{ - int i; - printk_debug("Azalia PCI config \n"); - for(i=0;i<0xFF;i+=4) - { - if((i%16)==0) - { - print_debug("\r\n");print_debug_hex8(i);print_debug(" "); - } - outl(0x80000800+i,0xcf8); - print_debug_hex32(inl(0xcfc)); - print_debug(" "); - } - print_debug("\r\n"); -} -#endif - + print_debug("AZALIA_INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/sis966_early_ctrl.c b/src/southbridge/sis/sis966/sis966_early_ctrl.c index 3d6abc7561..b58a7af8f0 100644 --- a/src/southbridge/sis/sis966/sis966_early_ctrl.c +++ b/src/southbridge/sis/sis966/sis966_early_ctrl.c @@ -51,10 +51,10 @@ static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) static void soft_reset(void) { set_bios_reset(); -#if 1 + /* link reset */ outb(0x02, 0x0cf9); outb(0x06, 0x0cf9); -#endif + } diff --git a/src/southbridge/sis/sis966/sis966_early_setup_car.c b/src/southbridge/sis/sis966/sis966_early_setup_car.c index 370951a2d5..951cfe2721 100644 --- a/src/southbridge/sis/sis966/sis966_early_setup_car.c +++ b/src/southbridge/sis/sis966/sis966_early_setup_car.c @@ -21,125 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static int set_ht_link_sis966(uint8_t ht_c_num) -{ - unsigned vendorid = 0x10de; - unsigned val = 0x01610109; - /* Nvidia sis966 hardcode, hw can not set it automatically */ - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); -} - -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) -{ - int i; - - unsigned val; - - val = inl(control); - val &= 0xfffffffe; - outl(val, control); - - outl(0, index); //index - for(i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - - val = inl(control); - val |= 1; - outl(val, control); - -} - -/* SIZE 0x100 */ -#define ANACTRL_IO_BASE 0x2800 -#define ANACTRL_REG_POS 0x68 - -/* SIZE 0x100 */ -#define SYSCTRL_IO_BASE 0x2400 -#define SYSCTRL_REG_POS 0x64 - -/* SIZE 0x100 */ -#define ACPICTRL_IO_BASE 0x2000 -#define ACPICTRL_REG_POS 0x60 - -/* - 16 1 1 1 1 8 :0 - 16 0 4 0 0 8 :1 - 16 0 4 2 2 4 :2 - 4 4 4 4 4 8 :3 - 8 8 4 0 0 8 :4 - 8 0 4 4 4 8 :5 -*/ - -#ifndef SIS966_PCI_E_X_0 - #define SIS966_PCI_E_X_0 4 -#endif -#ifndef SIS966_PCI_E_X_1 - #define SIS966_PCI_E_X_1 4 -#endif -#ifndef SIS966_PCI_E_X_2 - #define SIS966_PCI_E_X_2 4 -#endif -#ifndef SIS966_PCI_E_X_3 - #define SIS966_PCI_E_X_3 4 -#endif - -#ifndef SIS966_USE_NIC - #define SIS966_USE_NIC 0 -#endif - -#ifndef SIS966_USE_AZA - #define SIS966_USE_AZA 0 -#endif - -#define SIS966_CHIP_REV 3 - -static void sis966_early_set_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base) -{ - - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE, - }; - - int j; - for(j = 0; j < sis966_num; j++ ) { - setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), - PCI_DEV(busn[j], devn[j], 0) , io_base[j]); - } -} - -static void sis966_early_clear_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base) -{ - - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, - }; - - int j; - for(j = 0; j < sis966_num; j++ ) { - setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), - PCI_DEV(busn[j], devn[j], 0) , io_base[j]); - } - - -} -static void delayx(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x8000;i++) { - outb(value, 0x80); - } -#endif -} - static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { uint32_t tgio_ctrl; @@ -170,260 +51,13 @@ static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned ana outl(tgio_ctrl, anactrl_io_base + 0xcc); // wait 100us - delayx(1); + udelay(100); dword = pci_read_config32(dev, 0xe4); dword &= ~(0x3f0); // enable pci_write_config32(dev, 0xe4, dword); // need to wait 100ms - delayx(1000); -} - -static void sis966_early_setup(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) -{ - - static const unsigned int ctrl_conf_1[] = { - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000, - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200, - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000, - - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F, - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode - - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF, - RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode - }; - - static const unsigned int ctrl_conf_1_1[] = { - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, - RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, - }; - - - static const unsigned int ctrl_conf_sis966_only[] = { - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000, - -// RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE, -// RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE, - - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570, - RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010, - - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, - RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, - -#if SIS966_USE_AZA == 1 - RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, - -// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14, -#endif -// play a while with GPIO in SIS966 -#ifdef SIS966_MB_SETUP - SIS966_MB_SETUP -#endif - -#if SIS966_USE_AZA == 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2), -#endif - - - }; - - static const unsigned int ctrl_conf_master_only[] = { - - RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, - - //Master SIS966 ????YHLU - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), - - }; - - static const unsigned int ctrl_conf_2[] = { - /* I didn't put pcie related stuff here */ - - RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0, - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000, - - RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, - - -#if SIS966_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20), - - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), -#endif - - }; - - - int j, i; - - for(j=0; j<sis966_num; j++) { - sis966_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); - - setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - for(i=0; i<3; i++) { // three SATA - setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), - PCI_DEV(busn[j], devn[j], i), io_base[j]); - } - if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_sis966_only, sizeof(ctrl_conf_sis966_only)/sizeof(ctrl_conf_sis966_only[0]), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } - - if( (busn[j] == 0) && (sis966_num>1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - } - - setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), - PCI_DEV(busn[j], devn[j], 0), io_base[j]); - - } - -#if 0 - for(j=0; j< sis966_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, - io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, - io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, - io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); - } -#endif - + mdelay(100); } -#ifndef HT_CHAIN_NUM_MAX - -#define HT_CHAIN_NUM_MAX 4 -#define HT_CHAIN_BUSN_D 0x40 -#define HT_CHAIN_IOBASE_D 0x4000 - -#endif - -static int sis966_early_setup_x(void) -{ - /*find out how many sis966 we have */ - unsigned busn[HT_CHAIN_NUM_MAX]; - unsigned devn[HT_CHAIN_NUM_MAX]; - unsigned io_base[HT_CHAIN_NUM_MAX]; - /* - FIXME: May have problem if there is different SIS966 HTX card with different PCI_E lane allocation - Need to use same trick about pci1234 to verify node/link connection - */ - unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {SIS966_PCI_E_X_0, SIS966_PCI_E_X_1, SIS966_PCI_E_X_2, SIS966_PCI_E_X_3 }; - int sis966_num = 0; - unsigned busnx; - unsigned devnx; - int ht_c_index,j; - - /* FIXME: multi pci segment handling */ - - /* Any system that only have IO55 without SIS966? */ - for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) { - busnx = ht_c_index * HT_CHAIN_BUSN_D; - for(devnx=0;devnx<0x20;devnx++) { - uint32_t id; - device_t dev; - dev = PCI_DEV(busnx, devnx, 0); - id = pci_read_config32(dev, PCI_VENDOR_ID); - if(id == 0x036910de) { - busn[sis966_num] = busnx; - devn[sis966_num] = devnx; - io_base[sis966_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than SIS966 - sis966_num++; - if(sis966_num == SIS966_NUM) goto out; - break; // only one SIS966 on one chain - } - } - } - -out: - print_debug("sis966_num:"); print_debug_hex8(sis966_num); print_debug("\r\n"); - - //sis966_early_set_port(sis966_num, busn, devn, io_base); - //sis966_early_setup(sis966_num, busn, devn, io_base, pci_e_x); - - //sis966_early_clear_port(sis966_num, busn, devn, io_base); - -// set_ht_link_sis966(HT_CHAIN_NUM_MAX); - - return 0; - -} - - - diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/sis966_early_smbus.c index 736335a667..f8b8ac6c86 100644 --- a/src/southbridge/sis/sis966/sis966_early_smbus.c +++ b/src/southbridge/sis/sis966/sis966_early_smbus.c @@ -570,14 +570,14 @@ static const uint8_t SiS_SiS1183_init[44][3]={ => Others: Reserved */ void Init_Share_Memory(uint8_t ShareSize) -{ +{ device_t dev; - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5)); } - -/* In: => Aperture size + +/* In: => Aperture size => 00h : 32MBytes => 01h : 64MBytes => 02h : 128MBytes @@ -587,77 +587,24 @@ void Init_Share_Memory(uint8_t ShareSize) */ void Init_Aper_Size(uint8_t AperSize) { - device_t dev; - uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); - pci_write_config8(dev, 0x90, AperSize << 1); - -//pci_write_config32(dev, 0x94, 0x78); -//pci_write_config32(dev, 0x98, 0x0); - -#if 0 -{ -int i; -print_debug("Function3 Config in sis_init_stage2\n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\n"); -} -#endif + device_t dev; + uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; -dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); -pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); + pci_write_config8(dev, 0x90, AperSize << 1); -#if 0 -{ -int i; -dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1101), 0); -print_debug("Function1 Config in sis_init_stage2\n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\n"); -} - - #endif - - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); } - - - - void sis_init_stage1(void) { - device_t dev; - uint8_t temp8; - int i; - uint8_t GUI_En; - -#if 0 -{ -int i; -print_debug("Northbridge PCI Config in sis_init_stage1.0\n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\n"); -} -#endif + device_t dev; + uint8_t temp8; + int i; + uint8_t GUI_En; -// SiS_Chipset_Initialization +// SiS_Chipset_Initialization // ========================== NB ============================= dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); i=0; @@ -669,23 +616,6 @@ print_debug("\n"); i++; }; - -#if 0 -{ -int i; -print_debug("Northbridge PCI Config in sis_init_stage1.1\n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\n"); -} -#endif - - - // ========================== LPC ============================= dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); i=0; @@ -723,16 +653,16 @@ print_debug("\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit temp8 = pci_read_config8(dev, 0x4C); pci_write_config8(dev, 0x4C, temp8 | GUI_En); - - return; + + return; } void sis_init_stage2(void) { - device_t dev; - msr_t msr; + device_t dev; + msr_t msr; int i; uint32_t j; uint8_t temp8; @@ -740,89 +670,56 @@ void sis_init_stage2(void) // ========================== NB_AGP ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit - pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x0002), 0); - i=0; - while(SiS_NBAGP_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); - temp8 &= SiS_NBAGP_init[i][1]; - temp8 |= SiS_NBAGP_init[i][2]; - pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); - i++; - }; - -/* In => Share Memory size - => 00h : 0MBytes - => 02h : 32MBytes - => 03h : 64MBytes - => 04h : 128MBytes - => Others: Reserved -*/ -/* In: => Aperture size - => 00h : 32MBytes - => 01h : 64MBytes - => 02h : 128MBytes - => 03h : 256MBytes - => 04h : 512MBytes - => Others: Reserved -*/ - - Init_Share_Memory(0x02); //0x02 : 32M 0x03 : 64M - Init_Aper_Size(0x01); // 0x1 - -#if 0 -{ -int i; -print_debug("AGP PCI Config in sis_init_stage2\n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\n"); -} -#endif - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit + pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); + i=0; + + while(SiS_NBAGP_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); + temp8 &= SiS_NBAGP_init[i][1]; + temp8 |= SiS_NBAGP_init[i][2]; + pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); + i++; + }; + +/** + * Share Memory size + * => 00h : 0MBytes + * => 02h : 32MBytes + * => 03h : 64MBytes + * => 04h : 128MBytes + * => Others: Reserved + * + * Aperture size + * => 00h : 32MBytes + * => 01h : 64MBytes + * => 02h : 128MBytes + * => 03h : 256MBytes + * => 04h : 512MBytes + * => Others: Reserved + */ + + Init_Share_Memory(0x02); //0x02 : 32M + Init_Aper_Size(0x01); //0x1 : 64M // ========================== NB ============================= - printk_debug("Init NorthBridge sis761 -------->\n"); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - msr = rdmsr(0xC001001A); - printk_debug("Memory Top Bound %lx\n",msr.lo ); -// pci_write_config16(dev, 0x8E, msr.lo >> 16); // Topbound -// pci_write_config16(dev, 0x8E, (msr.lo >> 16) - ((pci_read_config8(dev, 0x4C) & 0xE0) >> 5)); - - temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; - //printk_debug("0x4c = %x\n",temp16); - temp16=0x0001<<(temp16-1); - temp16<<=8; - - printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); - pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); - // pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16); - pci_write_config8(dev, 0x7F, 0x08); // ACPI Base - outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function - -#if 0 -{ -int i; -print_debug("Northbridge PCI Config in sis_init_stage2\n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\n"); -} -#endif - + printk_debug("Init NorthBridge sis761 -------->\n"); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + msr = rdmsr(0xC001001A); + printk_debug("Memory Top Bound %lx\n",msr.lo ); + temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; + temp16=0x0001<<(temp16-1); + temp16<<=8; + printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); + pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); + pci_write_config8(dev, 0x7F, 0x08); // ACPI Base + outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function // ========================== ACPI ============================= i=0; @@ -839,37 +736,20 @@ print_debug("\n"); printk_debug("Init Misc -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_ISA), 0); // PCI Device Enable - pci_write_config8(dev, 0x7C, 0x03); // bit0=0 : enable audio controller(), bit1=1 : disable modem + pci_write_config8(dev, 0x7C, 0x03); // bit0=0 : enable audio controller(), bit1=1 : disable modem pci_write_config8(dev, 0x76, pci_read_config8(dev, 0x76)|0x30); // SM bus enable, PCIEXP Controller 1 and 2 disable - pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable + pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97 outb(temp8, 0x878); // ACPI select AC97 or HDA controller printk_debug("Audio select %x\n",inb(0x878)); - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, 0x1183), 0); - if(!dev){ + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA0), 0); + if(!dev){ print_debug("SiS 1183 does not exist !!"); } // SATA Set Mode pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40); - - -//-------------- enable IDE (SiS1183) ------------------------- -/* -{ - uint8_t temp8; - int i=0; - while(SiS_SiS1183_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; - }; -} - -*/ } @@ -880,16 +760,16 @@ static void enable_smbus(void) device_t dev; uint8_t temp8; printk_debug("enable_smbus -------->\n"); - + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); /* set smbus iobase && enable ACPI Space*/ - pci_write_config16(dev, 0x74, 0x0800); // Set ACPI Base + pci_write_config16(dev, 0x74, 0x0800); // Set ACPI Base temp8=pci_read_config8(dev, 0x40); // Enable ACPI Space pci_write_config8(dev, 0x40, temp8 | 0x80); temp8=pci_read_config8(dev, 0x76); // Enable SMBUS pci_write_config8(dev, 0x76, temp8 | 0x03); - + printk_debug("enable_smbus <--------\n"); } diff --git a/src/southbridge/sis/sis966/sis966_enable_rom.c b/src/southbridge/sis/sis966/sis966_enable_rom.c index f0b1f9f242..2a0f92df5e 100644 --- a/src/southbridge/sis/sis966/sis966_enable_rom.c +++ b/src/southbridge/sis/sis966/sis966_enable_rom.c @@ -32,7 +32,7 @@ static void sis966_enable_rom(void) { device_t addr; - + /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ addr = pci_locate_device(PCI_ID(0x1039, 0x0966), 0); diff --git a/src/southbridge/sis/sis966/sis966_ide.c b/src/southbridge/sis/sis966/sis966_ide.c index 875ccc27ff..f31ed29354 100644 --- a/src/southbridge/sis/sis966/sis966_ide.c +++ b/src/southbridge/sis/sis966/sis966_ide.c @@ -32,44 +32,44 @@ #include "sis966.h" uint8_t SiS_SiS5513_init[49][3]={ -{0x04, 0xFF, 0x05}, -{0x0D, 0xFF, 0x80}, -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x13}, -{0x2F, 0xFF, 0x55}, -{0x50, 0xFF, 0xA2}, -{0x51, 0xFF, 0x21}, -{0x53, 0xFF, 0x21}, -{0x54, 0xFF, 0x2A}, -{0x55, 0xFF, 0x96}, -{0x52, 0xFF, 0xA2}, -{0x56, 0xFF, 0x81}, -{0x57, 0xFF, 0xC0}, -{0x60, 0xFF, 0xFB}, -{0x61, 0xFF, 0xAA}, -{0x62, 0xFF, 0xFB}, -{0x63, 0xFF, 0xAA}, -{0x81, 0xFF, 0xB3}, -{0x82, 0xFF, 0x72}, -{0x83, 0xFF, 0x40}, -{0x85, 0xFF, 0xB3}, -{0x86, 0xFF, 0x72}, -{0x87, 0xFF, 0x40}, -{0x94, 0xFF, 0xC0}, -{0x95, 0xFF, 0x08}, -{0x96, 0xFF, 0xC0}, -{0x97, 0xFF, 0x08}, -{0x98, 0xFF, 0xCC}, -{0x99, 0xFF, 0x04}, -{0x9A, 0xFF, 0x0C}, -{0x9B, 0xFF, 0x14}, -{0xA0, 0xFF, 0x11}, -{0x57, 0xFF, 0xD0}, - -{0xD8, 0xFE, 0x01}, // Com reset -{0xC8, 0xFE, 0x01}, -{0xC4, 0xFF, 0xFF}, // Clear status +{0x04, 0xFF, 0x05}, +{0x0D, 0xFF, 0x80}, +{0x2C, 0xFF, 0x39}, +{0x2D, 0xFF, 0x10}, +{0x2E, 0xFF, 0x13}, +{0x2F, 0xFF, 0x55}, +{0x50, 0xFF, 0xA2}, +{0x51, 0xFF, 0x21}, +{0x53, 0xFF, 0x21}, +{0x54, 0xFF, 0x2A}, +{0x55, 0xFF, 0x96}, +{0x52, 0xFF, 0xA2}, +{0x56, 0xFF, 0x81}, +{0x57, 0xFF, 0xC0}, +{0x60, 0xFF, 0xFB}, +{0x61, 0xFF, 0xAA}, +{0x62, 0xFF, 0xFB}, +{0x63, 0xFF, 0xAA}, +{0x81, 0xFF, 0xB3}, +{0x82, 0xFF, 0x72}, +{0x83, 0xFF, 0x40}, +{0x85, 0xFF, 0xB3}, +{0x86, 0xFF, 0x72}, +{0x87, 0xFF, 0x40}, +{0x94, 0xFF, 0xC0}, +{0x95, 0xFF, 0x08}, +{0x96, 0xFF, 0xC0}, +{0x97, 0xFF, 0x08}, +{0x98, 0xFF, 0xCC}, +{0x99, 0xFF, 0x04}, +{0x9A, 0xFF, 0x0C}, +{0x9B, 0xFF, 0x14}, +{0xA0, 0xFF, 0x11}, +{0x57, 0xFF, 0xD0}, + +{0xD8, 0xFE, 0x01}, // Com reset +{0xC8, 0xFE, 0x01}, +{0xC4, 0xFF, 0xFF}, // Clear status {0xC5, 0xFF, 0xFF}, {0xC6, 0xFF, 0xFF}, {0xC7, 0xFF, 0xFF}, @@ -78,10 +78,10 @@ uint8_t SiS_SiS5513_init[49][3]={ {0xD6, 0xFF, 0xFF}, {0xD7, 0xFF, 0xFF}, - -{0x2C, 0xFF, 0x39}, // set subsystem ID -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x13}, + +{0x2C, 0xFF, 0x39}, // set subsystem ID +{0x2D, 0xFF, 0x10}, +{0x2E, 0xFF, 0x13}, {0x2F, 0xFF, 0x55}, @@ -96,22 +96,23 @@ static void ide_init(struct device *dev) uint16_t word; uint8_t byte; conf = dev->chip_info; - - -printk_debug("ide_init:---------->\n"); + + +print_debug("IDE_INIT:---------->\n"); //-------------- enable IDE (SiS5513) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; while(SiS_SiS5513_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); - temp8 &= SiS_SiS5513_init[i][1]; - temp8 |= SiS_SiS5513_init[i][2]; - pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); - i++; + { + temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); + temp8 &= SiS_SiS5513_init[i][1]; + temp8 |= SiS_SiS5513_init[i][2]; + pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -146,6 +147,26 @@ printk_debug("ide_init:---------->\n"); pci_dev_init(dev); #endif +#if DEBUG_IDE +{ + int i; + + print_debug("****** IDE PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\r\n"); +} +#endif +print_debug("IDE_INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index 7f7197c56a..211b19caed 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -151,81 +151,33 @@ static void lpc_slave_init(device_t dev) lpc_common_init(dev); } -#if 0 -static void enable_hpet(struct device *dev) -{ - unsigned long hpet_address; - - pci_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk_debug("enabling HPET @0x%x\n", hpet_address); -} -#endif static void lpc_usb_legacy_init(device_t dev) { uint16_t acpi_base; acpi_base = (pci_read_config8(dev,0x75) << 8); - //printk_debug("ACPI Base Addr=0x%4.4x\n",acpi_base); - - //printk_debug("acpi_base + 0xbb=%.2x\n", inb(acpi_base + 0xbb)); - //printk_debug("acpi_base + 0xba=%.2x\n", inb(acpi_base + 0xba)); outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb); outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba); - - //printk_debug("acpi_base + 0xbb=%.2x\n", inb(acpi_base + 0xbb)); - //printk_debug("acpi_base + 0xba=%.2x\n", inb(acpi_base + 0xba)); - - return; } static void lpc_init(device_t dev) { - uint8_t byte; - uint8_t byte_old; - int on; - int nmi_option; + uint8_t byte; + uint8_t byte_old; + int on; + int nmi_option; - printk_debug("lpc_init -------->\n"); + printk_debug("LPC_INIT -------->\n"); init_pc_keyboard(0x60, 0x64, 0); -#if 0 - { - int i; - printk_debug("LPC PCI config \n"); - for(i=0;i<0xFF;i+=4) - { - if((i%16)==0) - { - print_debug("\r\n"); - print_debug_hex8(i); - print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\r\n"); - } -#endif - printk_debug("lpc_init <--------\n"); - lpc_usb_legacy_init(dev); - return; - - printk_debug("lpc_init\r\n"); - lpc_common_init(dev); - printk_debug("lpc_init2\r\n"); - - -#if 0 - /* posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); + lpc_usb_legacy_init(dev); + lpc_common_init(dev); -#endif /* power after power fail */ -#if 1 + on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); @@ -235,7 +187,7 @@ static void lpc_init(device_t dev) } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk_info("set power %s after power fail\n", on?"on":"off"); -#endif + /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); @@ -249,44 +201,34 @@ static void lpc_init(device_t dev) printk_debug("Throttling CPU %2d.%1.1d percent.\n", (on*12)+(on>>1),(on&1)*5); } - -#if 0 -// default is enabled - /* Enable Port 92 fast reset */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if( byte != byte_old) { - outb(0x70, byte); - } - - /* Initialize the real time clock */ - rtc_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Initialize the High Precision Event Timers */ -// enable_hpet(dev); + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = inb(0x70); // RTC70 + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + } else { + byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + } + if( byte != byte_old) { + outb(0x70, byte); + } + + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + printk_debug("LPC_INIT <--------\n"); } static void sis966_lpc_read_resources(device_t dev) @@ -403,38 +345,6 @@ static const struct pci_driver lpc_driver __pci_driver = { .device = PCI_DEVICE_ID_SIS_SIS966_LPC, }; -static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_PRO, -}; - -static const struct pci_driver lpc_driver_lpc2 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_LPC_2, -}; -static const struct pci_driver lpc_driver_lpc3 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_LPC_3, -}; -static const struct pci_driver lpc_driver_lpc4 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_LPC_4, -}; -static const struct pci_driver lpc_driver_lpc5 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_LPC_5, -}; -static const struct pci_driver lpc_driver_lpc6 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_LPC_6, -}; - static struct device_operations lpc_slave_ops = { .read_resources = sis966_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -443,9 +353,3 @@ static struct device_operations lpc_slave_ops = { // .enable = sis966_enable, .ops_pci = &lops_pci, }; - -static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_SLAVE, -}; diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c index ce95f7a76b..632c5133cc 100644 --- a/src/southbridge/sis/sis966/sis966_nic.c +++ b/src/southbridge/sis/sis966/sis966_nic.c @@ -35,16 +35,16 @@ uint8_t SiS_SiS191_init[6][3]={ -{0x04, 0xFF, 0x07}, -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x91}, +{0x04, 0xFF, 0x07}, +{0x2C, 0xFF, 0x39}, +{0x2D, 0xFF, 0x10}, +{0x2E, 0xFF, 0x91}, {0x2F, 0xFF, 0x01}, {0x00, 0x00, 0x00} //End of table }; -#if 1 -#define StatusReg 0x1 + +#define StatusReg 0x1 #define SMI_READ 0x0 #define SMI_REQUEST 0x10 #define TRUE 1 @@ -56,7 +56,7 @@ uint16_t MacAddr[3]; void writeApcByte(int addr, uint8_t value) { outb(addr,0x78); - outb(value,0x79); + outb(value,0x79); } uint8_t readApcByte(int addr) { @@ -72,11 +72,11 @@ static void readApcMacAddr(void) // enable APC in south bridge sis966 D2F0 - outl(0x80001048,0xcf8); + outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk_debug("MAC addr in APC = "); - for(i = 0x9 ; i <=0xe ; i++) + for(i = 0x9 ; i <=0xe ; i++) { printk_debug("%2.2x",readApcByte(i)); } @@ -85,9 +85,9 @@ static void readApcMacAddr(void) /* Set APC Reload */ writeApcByte(0x7,readApcByte(0x7)&0xf7); writeApcByte(0x7,readApcByte(0x7)|0x0a); - + /* disable APC in south bridge */ - outl(0x80001048,0xcf8); + outl(0x80001048,0xcf8); outl(inl(0xcfc)&0xffffffbf,0xcfc); } @@ -100,9 +100,9 @@ static void set_apc(struct device *dev) uint8_t bTmp; /* enable APC in south bridge sis966 D2F0 */ - outl(0x80001048,0xcf8); + outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - + for(i = 0 ; i <3; i++) { addr=0x9+2*i; @@ -114,13 +114,13 @@ static void set_apc(struct device *dev) /* Set APC Reload */ writeApcByte(0x7,readApcByte(0x7)&0xf7); writeApcByte(0x7,readApcByte(0x7)|0x0a); - + /* disable APC in south bridge */ - outl(0x80001048,0xcf8); + outl(0x80001048,0xcf8); outl(inl(0xcfc)&0xffffffbf,0xcfc); - // CFG reg0x73 bit=1, tell driver MAC Address load to APC - bTmp = pci_read_config8(dev, 0x73); + // CFG reg0x73 bit=1, tell driver MAC Address load to APC + bTmp = pci_read_config8(dev, 0x73); bTmp|=0x1; pci_write_config8(dev, 0x73, bTmp); } @@ -142,12 +142,12 @@ static unsigned long ReadEEprom( struct device *dev, uint32_t base, uint32_t uint16_t data; uint32_t i; uint32_t ulValue; - - + + ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7 writel( ulValue,base+0x3c); - + mdelay(10); for(i=0 ; i <= LoopNum; i++) @@ -159,15 +159,15 @@ static unsigned long ReadEEprom( struct device *dev, uint32_t base, uint32_t mdelay(100); } - + mdelay(50); if(i==LoopNum) data=0x10000; else{ ulValue=readl(base+0x3c); data = (uint16_t)((ulValue & 0xffff0000) >> 16); - } - + } + return data; } @@ -179,9 +179,9 @@ static int phy_read(uint32_t base, unsigned phy_addr, unsigned phy_reg) uint16_t usData; uint16_t tmp; - - Read_Cmd = ((phy_reg << 11) | + + Read_Cmd = ((phy_reg << 11) | (phy_addr << 6) | SMI_READ | SMI_REQUEST); @@ -189,20 +189,20 @@ static int phy_read(uint32_t base, unsigned phy_addr, unsigned phy_reg) // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC writel( Read_Cmd,base+0x44); //outl( Read_Cmd,tmp+0x44); - + // Polling SMI_REQ bit to be deasserted indicated read command completed do { // Wait 20 usec before checking status //StallAndWait(20); mdelay(20); - ulValue = readl(base+0x44); - //ulValue = inl(tmp+0x44); + ulValue = readl(base+0x44); + //ulValue = inl(tmp+0x44); } while((ulValue & SMI_REQUEST) != 0); - //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); + //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); usData=(ulValue>>16); - + return usData; @@ -216,55 +216,49 @@ static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect() uint32_t Read_Cmd; uint16_t usData; int PhyAddress = 0; - - + + // Scan all PHY address(0 ~ 31) to find a valid PHY for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) - { - usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) - - // Found a valid PHY - + { + usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) + + // Found a valid PHY + if((usData != 0x0) && (usData != 0xffff)) { bFoundPhy = TRUE; break; } } -// printk_debug(" PHY_Addr=%x\n",PhyAddress); - //usData=phy_read(base,PhyAddress,0x0); - //printk_debug("PHY=%x\n",usData); if(!bFoundPhy) { printk_debug("PHY not found !!!! \n"); - // DisableMac(); } *PhyAddr=PhyAddress; - + return bFoundPhy; } static void nic_init(struct device *dev) { - uint32_t dword, old; - uint32_t mac_h, mac_l; - int eeprom_valid = 0; - int val; - uint16_t PhyAddr; - struct southbridge_sis_sis966_config *conf; + uint32_t dword, old; + uint32_t mac_h, mac_l; + int eeprom_valid = 0; + int val; + uint16_t PhyAddr; + struct southbridge_sis_sis966_config *conf; + static uint32_t nic_index = 0; + uint32_t base; + struct resource *res; + uint32_t reg; - static uint32_t nic_index = 0; - uint32_t base; - struct resource *res; - uint32_t reg; - - -printk_debug("SIS NIC init-------->\r\n"); + print_debug("NIC_INIT:---------->\n"); //-------------- enable NIC (SiS19x) ------------------------- @@ -272,121 +266,91 @@ printk_debug("SIS NIC init-------->\r\n"); uint8_t temp8; int i=0; while(SiS_SiS191_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); - temp8 &= SiS_SiS191_init[i][1]; - temp8 |= SiS_SiS191_init[i][2]; - pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); - i++; + { + temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); + temp8 &= SiS_SiS191_init[i][1]; + temp8 |= SiS_SiS191_init[i][2]; + pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- - - - { -unsigned long i; -unsigned long ulValue; - -#if 0 -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); -} -print_debug("\r\n"); -#endif - res = find_resource(dev, 0x10); + unsigned long i; + unsigned long ulValue; - if(!res) return; + res = find_resource(dev, 0x10); + if(!res) + { + printk_debug("NIC Cannot find resource..\r\n"); + return; + } base = res->base; -printk_debug("NIC base address %lx\n",base); - if(!(val=phy_detect(base,&PhyAddr))) - { - printk_debug("PHY detect fail !!!!\r\n"); - return; - } - -#if 0 -//------------ show op registers ---------------------- -{ -//device_t dev; -int i; -//dev = pci_locate_device(PCI_ID(0x1039, 0x5513), 0); -printk_debug("NIC OP Registers \n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(readl(base+i)); - print_debug(" "); -} + printk_debug("NIC base address %lx\n",base); -} + if(!(val=phy_detect(base,&PhyAddr))) + { + printk_debug("PHY detect fail !!!!\r\n"); + return; + } -//---------------------------------------------------- -#endif + ulValue=readl(base + 0x38L); // check EEPROM existing + + if((ulValue & 0x0002)) + { + + // read MAC address from EEPROM at first - ulValue=readl(base + 0x38L); // check EEPROM existing - - if((ulValue & 0x0002)) - { - - // read MAC address from EEPROM at first - // if that is valid we will use that - + printk_debug("EEPROM contents %x \n",ReadEEprom( dev, base, 0LL)); for(i=0;i<3;i++) { //status = smbus_read_byte(dev_eeprom, i); ulValue=ReadEEprom( dev, base, i+3L); - if (ulValue ==0x10000) break; // error - - MacAddr[i] =ulValue & 0xFFFF; - + if (ulValue ==0x10000) break; // error + + MacAddr[i] =ulValue & 0xFFFF; + } - - }else{ - // read MAC address from firmware + }else{ + // read MAC address from firmware printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue); MacAddr[0]=readw(0xffffffc0); // mac address store at here MacAddr[1]=readw(0xffffffc2); MacAddr[2]=readw(0xffffffc4); - } - + } -#if 0 -// read MAC address from EEPROM at first -printk_debug("MAC address in firmware trap \n"); - for( i=0;i<3;i++) - printk_debug(" %4x\n",MacAddr[i]); - printk_debug("\n"); -#endif + set_apc(dev); -set_apc(dev); - -readApcMacAddr(); + readApcMacAddr(); -#if 0 +#if DEBUG_NIC { -//device_t dev; -int i; -//dev = pci_locate_device(PCI_ID(0x1039, 0x5513), 0); -printk_debug("NIC PCI config \n"); -for(i=0;i<0xFF;i+=4) -{ if((i%16)==0) - {print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + int i; + + print_debug("****** NIC PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\r\n"); } -} + #endif } -printk_debug("nic_init<--------\r\n"); +print_debug("NIC_INIT:<----------\n"); return; #define RegStationMgtInf 0x44 @@ -429,161 +393,8 @@ return; } } } -// if that is invalid we will read that from romstrap - if(!eeprom_valid) { - unsigned long mac_pos; - mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds - mac_l = readl(mac_pos) + nic_index; // overflow? - mac_h = readl(mac_pos + 4); - - } -#if 1 -// set that into NIC MMIO -#define NvRegMacAddrA 0xA8 -#define NvRegMacAddrB 0xAC - writel(mac_l, base + NvRegMacAddrA); - writel(mac_h, base + NvRegMacAddrB); -#else -// set that into NIC - pci_write_config32(dev, 0xa8, mac_l); - pci_write_config32(dev, 0xac, mac_h); -#endif - - nic_index++; - -#if CONFIG_PCI_ROM_RUN == 1 - pci_dev_init(dev);// it will init option rom -#endif - -} - - - -#else // orginal code - -tatic int phy_read(uint8_t *base, unsigned phy_addr, unsigned phy_reg) -{ - uint32_t dword; - unsigned loop = 0x100; - writel(0x8000, base+0x190); //Clear MDIO lock bit - mdelay(1); - dword = readl(base+0x190); - if(dword & (1<<15)) return -1; - - writel(1, base+0x180); - writel((phy_addr<<5) | (phy_reg),base + 0x190); - do{ - dword = readl(base + 0x190); - if(--loop==0) return -4; - } while ((dword & (1<<15)) ); - - dword = readl(base + 0x180); - if(dword & 1) return -3; - - dword = readl(base + 0x194); - - return dword; - -} - -static int phy_detect(uint8_t *base) -{ - uint32_t dword; - int i; - int val; - unsigned id; - dword = readl(base+0x188); - dword &= ~(1<<20); - writel(dword, base+0x188); - - phy_read(base, 0, 1); - - for(i=1; i<=32; i++) { - int phyaddr = i & 0x1f; - val = phy_read(base, phyaddr, 1); - if(val<0) continue; - if((val & 0xffff) == 0xfffff) continue; - if((val & 0xffff) == 0) continue; - if(!(val & 1)) { - break; // Ethernet PHY - } - val = phy_read(base, phyaddr, 3); - if (val < 0 || val == 0xffff) continue; - id = val & 0xfc00; - val = phy_read(base, phyaddr, 2); - if (val < 0 || val == 0xffff) continue; - id |= ((val & 0xffff)<<16); - printk_debug("SIS966 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i); -// if((id == 0xe0180000) || (id==0x0032cc00)) - break; - } - - if(i>32) { - printk_debug("SIS966 MAC PHY not found\n"); - } - -} -static void nic_init(struct device *dev) -{ - uint32_t dword, old; - uint32_t mac_h, mac_l; - int eeprom_valid = 0; - struct southbridge_sis_sis966_config *conf; - - static uint32_t nic_index = 0; - - uint8_t *base; - struct resource *res; - - res = find_resource(dev, 0x10); - - if(!res) return; - - base = res->base; - - phy_detect(base); - -#define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 - - writel(PHY_RGMII, base + NvRegPhyInterface); - - conf = dev->chip_info; - - if(conf->mac_eeprom_smbus != 0) { -// read MAC address from EEPROM at first - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); - if(dev_eeprom) { - // if that is valid we will use that - unsigned char dat[6]; - int status; - int i; - for(i=0;i<6;i++) { - status = smbus_read_byte(dev_eeprom, i); - if(status < 0) break; - dat[i] = status & 0xff; - } - if(status >= 0) { - mac_l = 0; - for(i=3;i>=0;i--) { - mac_l <<= 8; - mac_l += dat[i]; - } - if(mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for(i=5;i>=4;i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } - } - } - } -// if that is invalid we will read that from romstrap +// if that is invalid we will read that from romstrap if(!eeprom_valid) { unsigned long mac_pos; mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds @@ -591,17 +402,12 @@ static void nic_init(struct device *dev) mac_h = readl(mac_pos + 4); } -#if 1 -// set that into NIC MMIO + +// set that into NIC MMIO #define NvRegMacAddrA 0xA8 #define NvRegMacAddrB 0xAC writel(mac_l, base + NvRegMacAddrA); writel(mac_h, base + NvRegMacAddrB); -#else -// set that into NIC - pci_write_config32(dev, 0xa8, mac_l); - pci_write_config32(dev, 0xac, mac_h); -#endif nic_index++; @@ -611,7 +417,6 @@ static void nic_init(struct device *dev) } -#endif static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, @@ -636,8 +441,3 @@ static const struct pci_driver nic_driver __pci_driver = { .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_NIC1, }; -static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE, -}; diff --git a/src/southbridge/sis/sis966/sis966_pci.c b/src/southbridge/sis/sis966/sis966_pci.c index 5c618b1b29..d22598fa48 100644 --- a/src/southbridge/sis/sis966/sis966_pci.c +++ b/src/southbridge/sis/sis966/sis966_pci.c @@ -46,19 +46,14 @@ static void pci_init(struct device *dev) dword |= (1<<30); /* Clear possible errors */ pci_write_config32(dev, 0x04, dword); -#if 1 - //only need (a01,xx] word = pci_read_config16(dev, 0x48); word |= (1<<0); /* MRL2MRM */ word |= (1<<2); /* MR2MRM */ pci_write_config16(dev, 0x48, word); -#endif -#if 1 dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ pci_write_config32(dev, 0x4c, dword); -#endif #if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; diff --git a/src/southbridge/sis/sis966/sis966_sata.c b/src/southbridge/sis/sis966/sis966_sata.c index c6254da68c..8d831b975e 100644 --- a/src/southbridge/sis/sis966/sis966_sata.c +++ b/src/southbridge/sis/sis966/sis966_sata.c @@ -32,65 +32,64 @@ #include "sis966.h" #include <arch/io.h> -#if 1 uint8_t SiS_SiS1183_init[68][3]={ -{0x04, 0x00, 0x05}, -{0x09, 0x00, 0x05}, -{0x2C, 0x00, 0x39}, -{0x2D, 0x00, 0x10}, -{0x2E, 0x00, 0x83}, -{0x2F, 0x00, 0x11}, -{0x90, 0x00, 0x40}, -{0x91, 0x00, 0x00}, // set mode -{0x50, 0x00, 0xA2}, -{0x52, 0x00, 0xA2}, -{0x55, 0x00, 0x96}, -{0x52, 0x00, 0xA2}, -{0x55, 0xF7, 0x00}, -{0x56, 0x00, 0xC0}, +{0x04, 0x00, 0x05}, +{0x09, 0x00, 0x05}, +{0x2C, 0x00, 0x39}, +{0x2D, 0x00, 0x10}, +{0x2E, 0x00, 0x83}, +{0x2F, 0x00, 0x11}, +{0x90, 0x00, 0x40}, +{0x91, 0x00, 0x00}, // set mode +{0x50, 0x00, 0xA2}, +{0x52, 0x00, 0xA2}, +{0x55, 0x00, 0x96}, +{0x52, 0x00, 0xA2}, +{0x55, 0xF7, 0x00}, +{0x56, 0x00, 0xC0}, {0x57, 0x00, 0x14}, -{0x67, 0x00, 0x28}, -{0x81, 0x00, 0xB3}, -{0x82, 0x00, 0x72}, -{0x83, 0x00, 0x40}, -{0x85, 0x00, 0xB3}, -{0x86, 0x00, 0x72}, +{0x67, 0x00, 0x28}, +{0x81, 0x00, 0xB3}, +{0x82, 0x00, 0x72}, +{0x83, 0x00, 0x40}, +{0x85, 0x00, 0xB3}, +{0x86, 0x00, 0x72}, {0x87, 0x00, 0x40}, -{0x88, 0x00, 0xDE}, // after set mode -{0x89, 0x00, 0xB3}, -{0x8A, 0x00, 0x72}, -{0x8B, 0x00, 0x40}, -{0x8C, 0x00, 0xDE}, -{0x8D, 0x00, 0xB3}, -{0x8E, 0x00, 0x92}, -{0x8F, 0x00, 0x40}, -{0x93, 0x00, 0x00}, -{0x94, 0x00, 0x80}, -{0x95, 0x00, 0x08}, -{0x96, 0x00, 0x80}, +{0x88, 0x00, 0xDE}, // after set mode +{0x89, 0x00, 0xB3}, +{0x8A, 0x00, 0x72}, +{0x8B, 0x00, 0x40}, +{0x8C, 0x00, 0xDE}, +{0x8D, 0x00, 0xB3}, +{0x8E, 0x00, 0x92}, +{0x8F, 0x00, 0x40}, +{0x93, 0x00, 0x00}, +{0x94, 0x00, 0x80}, +{0x95, 0x00, 0x08}, +{0x96, 0x00, 0x80}, {0x97, 0x00, 0x08}, -{0x9C, 0x00, 0x80}, -{0x9D, 0x00, 0x08}, -{0x9E, 0x00, 0x80}, -{0x9F, 0x00, 0x08}, -{0xA0, 0x00, 0x15}, -{0xA1, 0x00, 0x15}, -{0xA2, 0x00, 0x15}, +{0x9C, 0x00, 0x80}, +{0x9D, 0x00, 0x08}, +{0x9E, 0x00, 0x80}, +{0x9F, 0x00, 0x08}, +{0xA0, 0x00, 0x15}, +{0xA1, 0x00, 0x15}, +{0xA2, 0x00, 0x15}, {0xA3, 0x00, 0x15}, -{0xD8, 0xFE, 0x01}, // Com reset +{0xD8, 0xFE, 0x01}, // Com reset {0xC8, 0xFE, 0x01}, {0xE8, 0xFE, 0x01}, {0xF8, 0xFE, 0x01}, -{0xD8, 0xFE, 0x00}, // Com reset +{0xD8, 0xFE, 0x00}, // Com reset {0xC8, 0xFE, 0x00}, {0xE8, 0xFE, 0x00}, {0xF8, 0xFE, 0x00}, -{0xC4, 0xFF, 0xFF}, // Clear status +{0xC4, 0xFF, 0xFF}, // Clear status {0xC5, 0xFF, 0xFF}, {0xC6, 0xFF, 0xFF}, {0xC7, 0xFF, 0xFF}, @@ -98,7 +97,7 @@ uint8_t SiS_SiS1183_init[68][3]={ {0xD5, 0xFF, 0xFF}, {0xD6, 0xFF, 0xFF}, {0xD7, 0xFF, 0xFF}, -{0xE4, 0xFF, 0xFF}, // Clear status +{0xE4, 0xFF, 0xFF}, // Clear status {0xE5, 0xFF, 0xFF}, {0xE6, 0xFF, 0xFF}, {0xE7, 0xFF, 0xFF}, @@ -110,126 +109,33 @@ uint8_t SiS_SiS1183_init[68][3]={ {0x00, 0x00, 0x00} //End of table }; - -#else -uint8_t SiS_SiS1183_init[5][3]={ - -{0xD8, 0xFE, 0x01}, // Com reset -{0xC8, 0xFE, 0x01}, -{0xE8, 0xFE, 0x01}, -{0xF8, 0xFE, 0x01}, - -{0x00, 0x00, 0x00} -}; //End of table - -uint8_t SiS_SiS1183_init2[21][3]={ -{0xD8, 0xFE, 0x00}, -{0xC8, 0xFE, 0x00}, -{0xE8, 0xFE, 0x00}, -{0xF8, 0xFE, 0x00}, - - -{0xC4, 0xFF, 0xFF}, // Clear status -{0xC5, 0xFF, 0xFF}, -{0xC6, 0xFF, 0xFF}, -{0xC7, 0xFF, 0xFF}, -{0xD4, 0xFF, 0xFF}, -{0xD5, 0xFF, 0xFF}, -{0xD6, 0xFF, 0xFF}, -{0xD7, 0xFF, 0xFF}, -{0xE4, 0xFF, 0xFF}, // Clear status -{0xE5, 0xFF, 0xFF}, -{0xE6, 0xFF, 0xFF}, -{0xE7, 0xFF, 0xFF}, -{0xF4, 0xFF, 0xFF}, -{0xF5, 0xFF, 0xFF}, -{0xF6, 0xFF, 0xFF}, -{0xF7, 0xFF, 0xFF}, - - -{0x00, 0x00, 0x00} //End of table -}; -#endif - - - static void sata_init(struct device *dev) { - uint32_t dword; + uint32_t dword; struct southbridge_sis_sis966_config *conf; - + struct resource *res; uint16_t base; uint8_t temp8; - + conf = dev->chip_info; -printk_debug("SATA(SiS1183)_init-------->\r\n"); + print_debug("SATA_INIT:---------->\n"); -#if 1 -//-------------- enable IDE (SiS5513) ------------------------- -{ - uint8_t temp8; - int i=0; +//-------------- enable IDE (SiS1183) ------------------------- +{ + uint8_t temp8; + int i=0; while(SiS_SiS1183_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; + { + temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); + temp8 &= SiS_SiS1183_init[i][1]; + temp8 |= SiS_SiS1183_init[i][2]; + pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); + i++; }; } -/* -mdelay(5); -{ - uint8_t temp8; - int i=0; - while(SiS_SiS1183_init2[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS1183_init2[i][0]); - temp8 &= SiS_SiS1183_init2[i][1]; - temp8 |= SiS_SiS1183_init2[i][2]; - pci_write_config8(dev, SiS_SiS1183_init2[i][0], temp8); - i++; - }; -} -*/ //----------------------------------------------------------- -#endif - - -#if 0 - - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled */ - dword &= ~((1 << 15) | (1 << 13)); - if(conf) { - if (conf->sata1_enable) { - /* Enable secondary SATA interface */ - dword |= (1<<0); - printk_debug("SATA S \t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface */ - dword |= (1<<1); - printk_debug("SATA P \n"); - } - } else { - dword |= (1<<1) | (1<<0); - printk_debug("SATA P and S \n"); - } - - -#if 1 - dword &= ~(0x1f<<24); - dword |= (0x15<<24); -#endif - pci_write_config32(dev, 0x50, dword); - - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); - -#endif { uint32_t i,j; @@ -239,33 +145,33 @@ for (i=0;i<10;i++){ temp32=0; temp32= pci_read_config32(dev, 0xC0); for ( j=0;j<0xFFFF;j++); - printk_debug("status= %x",temp32); + printk_debug("status= %x\n",temp32); if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break; } -printk_debug("\n"); -} - -#if 0 -res = find_resource(dev, 0x10); -base =(uint16_t ) res->base; -printk_debug("BASE ADDR %x\n",base); -base&=0xFFFE; -printk_debug("SATA status %x\n",inb(base+7)); +} +#if DEBUG_SATA { -int i; -for(i=0;i<0xFF;i+=4) -{ - if((i%16)==0) - { - print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } + int i; + + print_debug("****** SATA PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\r\n"); } #endif -printk_debug("sata_init <--------\r\n"); + + print_debug("SATA_INIT:<----------\n"); } @@ -293,9 +199,3 @@ static const struct pci_driver sata0_driver __pci_driver = { .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_SATA0, }; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_SATA1, -}; diff --git a/src/southbridge/sis/sis966/sis966_smbus.h b/src/southbridge/sis/sis966/sis966_smbus.h index cc0e1db686..503a385e29 100644 --- a/src/southbridge/sis/sis966/sis966_smbus.h +++ b/src/southbridge/sis/sis966/sis966_smbus.h @@ -158,14 +158,14 @@ for(i=0;i<0x1000;i++) } }; - global_status_register = inb(smbus_io_base + 0x00); + global_status_register = inb(smbus_io_base + 0x00); byte = inb(smbus_io_base + 0x08); if (global_status_register != 0x08) { // lose check, otherwise it should be 0 print_debug("Fail");print_debug("\r\t"); return -1; } - print_debug("Success");print_debug("\r\t"); + print_debug("Success");print_debug("\r\t"); return byte; } diff --git a/src/southbridge/sis/sis966/sis966_usb.c b/src/southbridge/sis/sis966/sis966_usb.c index 487561fa09..f0768e8240 100644 --- a/src/southbridge/sis/sis966/sis966_usb.c +++ b/src/southbridge/sis/sis966/sis966_usb.c @@ -30,37 +30,38 @@ #include <device/pci_ops.h> #include "sis966.h" -// From Y.S. -// PCI R47h-R44h=0001AD54h -// PCI R4Bh-R48h=00000271h -uint8_t SiS_SiS7001_init[15][3]={ -{0x04, 0xFF, 0x07}, +uint8_t SiS_SiS7001_init[16][3]={ +{0x04, 0x00, 0x07}, +{0x0C, 0x00, 0x08}, +{0x0D, 0x00, 0x20}, + {0x2C, 0xFF, 0x39}, {0x2D, 0xFF, 0x10}, {0x2E, 0xFF, 0x01}, {0x2F, 0xFF, 0x70}, + {0x44, 0x00, 0x54}, {0x45, 0x00, 0xAD}, {0x46, 0x00, 0x01}, {0x47, 0x00, 0x00}, -{0x48, 0x00, 0x71}, + +{0x48, 0x00, 0x73}, {0x49, 0x00, 0x02}, {0x4A, 0x00, 0x00}, {0x4B, 0x00, 0x00}, -{0x04, 0x00, 0x07}, + {0x00, 0x00, 0x00} //End of table }; static void usb_init(struct device *dev) { + print_debug("USB 1.1 INIT:---------->\n"); //-------------- enable USB1.1 (SiS7001) ------------------------- { uint8_t temp8; int i=0; - printk_debug("USB1.1_Init\n"); - while(SiS_SiS7001_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); temp8 &= SiS_SiS7001_init[i][1]; @@ -71,23 +72,28 @@ static void usb_init(struct device *dev) } //----------------------------------------------------------- -#if 0 +#if DEBUG_USB { - int i; - printk_debug("\nUSB 1.1 PCI config"); - for(i=0;i<0xFF;i+=4) - { - if((i%16)==0) - { - print_debug("\r\n");print_debug_hex8(i);print_debug(": ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + int i; + + print_debug("****** USB 1.1 PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); } print_debug("\r\n"); - } +} #endif - + print_debug("USB 1.1 INIT:<----------\n"); } + static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/sis966_usb2.c index c9e00a908a..6e763953a0 100644 --- a/src/southbridge/sis/sis966/sis966_usb2.c +++ b/src/southbridge/sis/sis966/sis966_usb2.c @@ -36,11 +36,9 @@ extern struct ehci_debug_info dbg_info; -// From Y.S. -// PCI R43h-R40h=00000020h -// PCI R4Bh-R48h=00078010h -uint8_t SiS_SiS7002_init[19][3]={ +uint8_t SiS_SiS7002_init[22][3]={ {0x04, 0x00, 0x06}, +{0x0D, 0x00, 0x00}, {0x2C, 0xFF, 0x39}, {0x2D, 0xFF, 0x10}, @@ -52,12 +50,15 @@ uint8_t SiS_SiS7002_init[19][3]={ {0x76, 0x00, 0x00}, {0x77, 0x00, 0x00}, +{0x7A, 0x00, 0x00}, +{0x7B, 0x00, 0x00}, + {0x40, 0x00, 0x20}, {0x41, 0x00, 0x00}, {0x42, 0x00, 0x00}, {0x43, 0x00, 0x08}, -{0x44, 0x00, 0x64}, +{0x44, 0x00, 0x04}, {0x48, 0x00, 0x10}, {0x49, 0x00, 0x80}, @@ -67,56 +68,58 @@ uint8_t SiS_SiS7002_init[19][3]={ {0x00, 0x00, 0x00} //End of table }; - - static void usb2_init(struct device *dev) { - uint8_t *base; - struct resource *res; - uint32_t temp32; + uint8_t *base; + struct resource *res; + uint32_t temp32; + print_debug("USB 2.0 INIT:---------->\n"); //-------------- enable USB2.0 (SiS7002) ------------------------- { uint8_t temp8; int i=0; - printk_debug("USB2.0_Init\n"); - - while(SiS_SiS7002_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); - temp8 &= SiS_SiS7002_init[i][1]; - temp8 |= SiS_SiS7002_init[i][2]; - pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); - i++; - }; + while(SiS_SiS7002_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); + temp8 &= SiS_SiS7002_init[i][1]; + temp8 |= SiS_SiS7002_init[i][2]; + pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); + i++; + }; } - res = find_resource(dev, 0x10); - if(!res) - return; + res = find_resource(dev, 0x10); + if(!res) + return; - base =(uint8_t *) res->base; - printk_debug("base = %08x\n", base); - writel(0x2,base+0x20); + base =(uint8_t *) res->base; + printk_debug("base = %08x\n", base); + writel(0x2,base+0x20); //----------------------------------------------------------- -#if 0 +#if DEBUG_USB2 { - int i; - printk_debug("\nUSB 2.0 PCI config"); - for(i=0;i<0xFF;i+=4) - { - if((i%16)==0) - { - print_debug("\r\n");print_debug_hex8(i);print_debug(": ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + int i; + + print_debug("****** USB 2.0 PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); } print_debug("\r\n"); - } +} #endif - + print_debug("USB 2.0 INIT:<----------\n"); } static void usb2_set_resources(struct device *dev) @@ -164,5 +167,5 @@ static struct device_operations usb2_ops = { static const struct pci_driver usb2_driver __pci_driver = { .ops = &usb2_ops, .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_EHCI, + .device = PCI_DEVICE_ID_SIS_SIS966_USB2, }; diff --git a/targets/gigabyte/ga_2761gxdk/Config.lb b/targets/gigabyte/ga_2761gxdk/Config.lb index 890d3e3626..77cde390a0 100644 --- a/targets/gigabyte/ga_2761gxdk/Config.lb +++ b/targets/gigabyte/ga_2761gxdk/Config.lb @@ -3,6 +3,8 @@ ## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD. +## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) +## Written by Morgan Tsai <my_tsai@sis.com> for SiS. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -23,38 +25,22 @@ target ga_2761gxdk mainboard gigabyte/ga_2761gxdk romimage "normal" -# 48K for VGA BIOS - option ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 425984 -# 64K for Etherboot -# option ROM_SIZE = 458752 -# 44k for atixx.rom -# option ROM_SIZE = 479232 -# 32k for vbios -# option ROM_SIZE = 491520 +# 32K for VGA BIOS + option ROM_SIZE = (512*1024 - 32*1024) option USE_FAILOVER_IMAGE=0 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../../../../payloads/filo_uda1.elf end -romimage "fallback" +romimage "fallback" option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 -# option ROM_IMAGE_SIZE=0x13800 -# option ROM_IMAGE_SIZE=0x18800 -# option ROM_IMAGE_SIZE=0x19800 - option ROM_IMAGE_SIZE=0x20000 -# option ROM_IMAGE_SIZE=0x15800 - option XIP_ROM_SIZE=0x40000 - option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../../../../payloads/filo_uda1.elf end @@ -66,5 +52,5 @@ romimage "failover" option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" -buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" +# buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" + buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" |