Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

573 files changed, 180355 insertions, 0 deletions

diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc
index 260e2c1b55..bd5557313f 100644
--- a/src/vendorcode/Makefile.inc
+++ b/src/vendorcode/Makefile.inc
@@ -1,3 +1,4 @@
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += $(src)/vendorcode/amd/agesa/f10
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14
 
diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h
new file mode 100755
index 0000000000..c50086deac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/AGESA.h
@@ -0,0 +1,2901 @@
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 47176 $   @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include  "Porting.h"
+#include  "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE              0x00028000
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA                0x00028100
+#define AGESA_DO_RESET                 0x00028101
+#define AGESA_ALLOCATE_BUFFER          0x00028102
+#define AGESA_DEALLOCATE_BUFFER        0x00028103
+#define AGESA_LOCATE_BUFFER            0x00028104
+#define AGESA_RUNFUNC_ONAP             0x00028105
+
+// AGESA ADVANCED CALLOUTS, HyperTransport
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD                 0x00028140
+#define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
+#define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
+#define AGESA_READ_SPD_RECOVERY        0x00028143
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA       0x00028200
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
+
+//------------------------------------------------------------------------
+//
+// HyperTransport Interface
+
+
+
+//-----------------------------------------------------------------------------
+//                         HT DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+
+// Width equates for call backs
+#define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
+#define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
+#define HT_WIDTH_4_BITS              4
+#define HT_WIDTH_2_BITS              2
+#define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
+
+// Frequency Limit equates for call backs which take a frequency supported mask.
+#define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
+#define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
+#define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
+
+// Unit ID Clumping special values
+#define HT_CLUMPING_DISABLE          0x00000000
+#define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
+
+#define HT_LIST_TERMINAL             0xFF             ///< End of list.
+#define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
+#define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
+
+// Event Notify definitions
+
+// Event definitions.
+
+// Coherent subfunction events
+#define HT_EVENT_COH_EVENTS             0x10001000
+#define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+
+// Non-coherent subfunction events
+#define HT_EVENT_NCOH_EVENTS         0x10002000
+#define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+
+// Optimization subfunction events
+#define HT_EVENT_OPT_EVENTS               0x10003000
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+
+// HW Fault events
+#define HT_EVENT_HW_EVENTS           0x10004000
+#define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+
+// The Recovery HT component uses 0x10005000 for events.
+// For consistency, we avoid that range here.
+
+#define HT_MAX_NC_BUIDS 32
+//----------------------------------------------------------------------------
+//                         HT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// Specify the state redundant links are to be left in after match.
+///
+/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
+/// or powered off.
+
+typedef enum {
+  MATCHED,                               ///< The link matches the requested customization.
+                                         ///< When used with IGNORE_LINK,
+                                         ///< this will generally require other software to initialize the link.
+                                         ///< When used with SKIP_REGANG,
+                                         ///< the two unganged links will be available for distribution.
+
+  POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
+                                         ///< Power Off is only supported for coherent links.
+                                         ///< Link power off may occur at a warm reset rather than immediately.
+                                         ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
+
+  UNMATCHED,                             ///< The link should be processed according to normal defaults.
+                                         ///< Effectively, the link does not match the requested customization.
+                                         ///< This can be used to exclude links from a following match any.
+
+  MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
+} FINAL_LINK_STATE;
+
+/// Swap a device from its current id to a new one.
+
+typedef struct {
+  IN       UINT8 FromId;                 ///< The device responding to FromId,
+  IN       UINT8 ToId;                   ///< will be moved to ToId.
+} BUID_SWAP_ITEM;
+
+
+/// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+/// the final in order list of device ids is provided. (There can be more swaps than devices.)
+/// The unused entries in both are filled with 0xFF.
+
+typedef struct {
+  IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
+  IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
+} BUID_SWAP_LIST;
+
+
+/// Control Manual Initialization of Non-Coherent Chains
+///
+/// This interface is checked every time a non-coherent chain is
+/// processed.  BUID assignment may be controlled explicitly on a
+/// non-coherent chain. Provide a swap list.  Swaps controls the
+/// BUID assignment and FinalIds provides the device to device
+/// Linking.  Device orientation can be detected automatically, or
+/// explicitly.  See interface documentation for more details.
+///
+/// If a manual swap list is not supplied,
+/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+/// based on each device's unit count.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                       ///< The Socket on which this chain is located
+  IN       UINT8 Link;                         ///< The Link on the host for this chain
+  // Override fields
+  IN       BUID_SWAP_LIST SwapList;            ///< The swap list
+} MANUAL_BUID_SWAP_LIST;
+
+
+/// Override options for DEVICE_CAP_OVERRIDE.
+///
+/// Specify which override actions should be performed.  For Checks, 1 means to check the item
+/// and 0 means to skip the check.  For the override options, 1 means to apply the override and
+/// 0 means to ignore the override.
+
+typedef struct {
+  IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
+  IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
+  IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
+  IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
+  IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
+  IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
+  IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
+} DEVICE_CAP_OVERRIDE_OPTIONS;
+
+/// Override capabilities of a device.
+///
+/// This interface is checked once for every Link on every IO device.
+/// Provide the width and frequency capability if needed for this device.
+/// This is used along with device capabilities, the limit interfaces, and northbridge
+/// limits to compute the default settings.  The components of the device's PCI config
+/// address are provided, so its settings can be consulted if need be.
+/// The optional callout is a catch all.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
+  // Override fields
+  IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
+  IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
+  IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
+  IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
+  IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
+} DEVICE_CAP_OVERRIDE;
+
+/// Callout param struct for override capabilities of a device.
+///
+/// If the optional callout is implemented this param struct is passed to it.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
+  // Override fields
+     OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
+     OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
+     OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
+     OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
+} DEVICE_CAP_CALLOUT_PARAMS;
+
+///  Limits for CPU to CPU Links.
+///
+///  For each coherent connection this interface is checked once.
+///  Provide the frequency and width if needed for this Link (usually based on board
+///  restriction).  This is used with CPU device capabilities and northbridge limits
+///  to compute the default settings.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Limit fields
+  IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
+  IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
+  IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
+} CPU_TO_CPU_PCB_LIMITS;
+
+///  Get limits for non-coherent Links.
+///
+/// For each non-coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction).  This is used with device capabilities, device overrides, and northbridge limits
+/// to compute the default settings.
+///
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
+  IN       UINT8 HostLink;                 ///< The Link about to be initialized
+  IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
+  // Limit fields
+  IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
+  IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
+  IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
+} IO_PCB_LIMITS;
+
+///  Manually control bus number assignment.
+///
+/// This interface is checked every time a non-coherent chain is processed.
+/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
+/// assignments, this interface can provide explicit control.  For each chain, provide
+/// the bus number range to use.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this chain is located
+  IN       UINT8 Link;                   ///< The Link on the host for this chain
+  // Override fields
+  IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
+  IN       UINT8 SubBus;                 ///< Subordinate Bus number
+} OVERRIDE_BUS_NUMBERS;
+
+
+///  Ignore a Link.
+///
+///  This interface is checked every time a coherent Link is found and then every
+///  time a non-coherent Link from a CPU is found.
+///  Any coherent or non-coherent Link from a CPU can be ignored and not used
+///  for discovery or initialization.  Useful for connection based systems.
+///  (Note: not checked for IO device to IO Device Links.)
+///  (Note: not usable for internal links (MCM processors).)
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this Link is located
+  IN       UINT8 Link;                   ///< The Link about to be initialized
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
+} IGNORE_LINK;
+
+
+///  Skip reganging of subLinks.
+///
+///  This interface is checked whenever two subLinks are both connected to the same CPUs.
+///  Normally, unganged sublinks between the same two CPUs are reganged.
+///  Provide a matching structure to leave the Links unganged.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
+} SKIP_REGANG;
+
+///  The System Socket layout, which sockets are physically connected.
+///
+///  The hardware method for Socket naming is preferred.  Use this software method only
+///  if required.
+
+typedef struct {
+  IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
+  IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
+  IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
+} SYSTEM_PHYSICAL_SOCKET_MAP;
+
+//----------------------------------------------------------------------------
+///
+/// This is the input structure for AmdHtInitialize.
+///
+typedef struct {
+  // Basic level customization
+  IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
+                                         ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
+  IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
+                                         ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
+  IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
+                                         ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUMS}
+
+  // Advanced Level Customization
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
+                                                          ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+  IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
+  IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
+                                                          ///< Use either auto bus numbering or override bus
+                                                          ///< numbers, not both.
+                                                          ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
+
+  IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
+                                                          ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
+  IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
+                                                          ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
+                                                          ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
+
+  // Expert Level Customization
+  IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
+                                                     ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
+  IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
+                                                     ///< The hardware socket naming method is preferred,
+                                                     ///<  If it can't be used, this provides a software method.
+                                                     ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
+} AMD_HT_INTERFACE;
+
+//-----------------------------------------------------------------------------
+//
+// HT Recovery Interface
+//
+
+
+/*-----------------------------------------------------------------------------
+ *              HT Recovery DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+// BBHT subfunction events
+#define HT_EVENT_BB_EVENTS         0x10005000
+#define HT_EVENT_BB_BUID_EXCEED    0x10015000
+#define HT_EVENT_BB_DEVICE_FAILED  0x10055000
+#define HT_EVENT_BB_AUTO_DEPTH     0x10065000
+
+/*----------------------------------------------------------------------------
+ *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/// The Interface structure to Recovery HT.
+
+typedef struct {
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
+                                                       ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+     OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
+                                   ///< else, for manual init unmodified.
+} AMD_HT_RESET_INTERFACE;
+
+/*----------------------------------------------------------------------------
+ *   CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+
+/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+typedef enum {
+  C1eModeDisabled = 0,              ///< Disabled
+  C1eModeHardware = 1,              ///< Hardware method
+  C1eModeMsgBased = 2,              ///< Message-based method
+  MaxC1eMode = 3                    ///< Not a valid value, used for verifying input
+} PLATFORM_C1E_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+  CStateModeDisabled = 0,           ///< Disabled
+  CStateModeC6 = 1,                 ///< C6 State
+  MaxCStateMode = 2                 ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/*----------------------------------------------------------------------------
+ *   GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+
+#define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_DDI_LANES_CONFIGURATION     0x20010005   // DDI lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
+/// PCIe port configuration data
+typedef struct  {
+  IN       UINT8                PortPresent;              ///< Enable PCIe port for initialization.
+  IN       UINT8                ChannelType;              /**< Channel type.
+                                                           *  @li @b 0 - "lowLoss",
+                                                           *  @li @b 1 - "highLoss",
+                                                           *  @li @b 2 - "mob0db",
+                                                           *  @li @b 3 - "mob3db",
+                                                           *  @li @b 4 - "extnd6db"
+                                                           *  @li @b 5 - "extnd8db"
+                                                           */
+  IN       UINT8                DeviceNumber;             /**< PCI Device number for port.
+                                                           *   @li @b 0 - Native port device number
+                                                           *   @li @b N - Port device number (Available device numbers @ref F12PortDevNumberList "Family 0x12",  @ref F14PortDevNumberList "Family 0x14")
+                                                           */
+  IN       UINT8                FunctionNumber;           ///< Reserved for future use
+  IN       UINT8                LinkSpeedCapability;      /**< Advertised link speed/feature capability
+                                                           *  @li @b 0 - Maximum supported by silicon
+                                                           *  @li @b 1 - Gen1
+                                                           *  @li @b 2 - Gen2
+                                                           *  @li @b 3 - Gen3
+                                                           */
+  IN       UINT8                LinkSpeedChangeMode;      /**< Link speed change mode
+                                                           *  @li @b 0 - Autonomous
+                                                           *  @li @b 1 - Advanced
+                                                           */
+
+  IN       UINT8                LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+                                                           *  @li @b 0 - Disabled
+                                                           *  @li @b 1 - L0s only
+                                                           *  @li @b 2 - L1 only
+                                                           *  @li @b 2 - L0s and L1
+                                                           */
+  IN       UINT8                LinkHotplug;              /**< Hotplug control.
+                                                           *  @li @b 0 - Disabled
+                                                           *  @li @b 1 - Basic
+                                                           *  @li @b 2 - Server
+                                                           *  @li @b 3 - Enhanced
+                                                           */
+  IN       UINT8                ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                           *   identification which control reset for given port.
+                                                           *   Each port with unique GPIO should have unique ResetId assigned.
+                                                           *   All ports use same GPIO to control reset should have same ResetId assigned.
+                                                           *   see AgesaPcieSlotResetContol.
+                                                           */
+  IN       UINT8                Compliance;               ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+} PCIe_PORT_DATA;
+
+/// DDI Configuration data
+typedef struct  {
+  IN       UINT8                ConnectorType;            /**< Display Connector Type
+                                                            *  @li @b 0 - DP
+                                                            *  @li @b 1 - eDP
+                                                            *  @li @b 2 - Single Link DVI
+                                                            *  @li @b 3 - Dual  Link DVI
+                                                            *  @li @b 4 - HDMI
+                                                            *  @li @b 5 - Travis DP-to-VGA
+                                                            *  @li @b 6 - Travis DP-to-LVDS
+                                                            *  @li @b 7 - SB900 NutMeg DP-to-VGA
+                                                            */
+  IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
+                                                            *  @li @b 0 - AUX1
+                                                            *  @li @b 1 - AUX2
+                                                            *  @li @b 2 - AUX3
+                                                            *  @li @b 3 - AUX4
+                                                            *  @li @b 4 - AUX5
+                                                            *  @li @b 5 - AUX6
+                                                            */
+  IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
+                                                            *  @li @b 0 - HDP1
+                                                            *  @li @b 1 - HDP2
+                                                            *  @li @b 2 - HDP3
+                                                            *  @li @b 3 - HDP4
+                                                            *  @li @b 4 - HDP5
+                                                            *  @li @b 5 - HDP6
+                                                            */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+  IN       UINT8                EngineType;               /**< Engine type
+                                                           *  @li @b 0 -  Ignore engine configuration
+                                                           *  @li @b 1 -  PCIe port
+                                                           *  @li @b 2 -  DDI
+                                                           */
+  IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12"
+                                                           * @ref F14PcieLaneDescription "Family 0x14".
+                                                           */
+  IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12",
+                                                           * @ref F14PcieLaneDescription "Family 0x14".
+                                                           */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in topology
+                                                           */
+  IN       UINT32               SocketId;                 ///< Socket Id
+  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       VOID                 *Reserved;                ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+  AssertSlotReset,                                        ///< Assert slot reset
+  DeassertSlotReset                                       ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
+  IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+/// Engine descriptor type
+typedef enum {
+  PcieUnusedEngine = 0,                                   ///< Unused descriptor
+  PciePortEngine = 1,                                     ///< PCIe port
+  PcieDdiEngine = 2,                                      ///< DDI
+  MaxPcieEngine                                           ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum  {
+  PcieGenMaxSupported,                                    ///< Maximum supported
+  PcieGen1 = 1,                                           ///< Gen1
+  PcieGen2,                                               ///< Gen2
+  MaxPcieGen                                              ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum  {
+  PsppDisabled,                                           ///< PSPP disabled
+  PsppPerformance = 1,                                    ///< Performance
+  PsppBalanceHigh,                                        ///< Balance-High
+  PsppBalanceLow,                                         ///< Balance-Low
+  PsppPowerSaving,                                        ///< Power Saving
+  MaxPspp
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+  ConnectorTypeDP,                                        ///< DP
+  ConnectorTypeEDP,                                       ///< eDP
+  ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI
+  ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI
+  ConnectorTypeHDMI,                                      ///< HDMI
+  ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
+  ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
+  ConnectorTypeNutmegDpToVga,                             ///< SB900 NutMeg DP-to-VGA
+  MaxConnectorType                                        ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+  ChannelTypeLowLoss,                                     ///< Low Loss
+  ChannelTypeHighLoss,                                    ///< High Loss
+  ChannelTypeMob0db,                                      ///< Mobile 0dB
+  ChannelTypeMob3db,                                      ///< Mobile 3dB
+  ChannelTypeExt6db,                                      ///< Extended 6dB
+  ChannelTypeExt8db,                                      ///< Extended 8dB
+  MaxChannelType                                          ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+  AspmDisabled,                                           ///< Disabled
+  AspmL0s,                                                ///< PCIe L0s link state
+  AspmL1,                                                 ///< PCIe L1 link state
+  AspmL0sL1,                                              ///< PCIe L0s & L1 link state
+  MaxAspm                                                 ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+  HotplugDisabled,                                        ///< Hotplug disable
+  HotplugBasic,                                           ///< Basic Hotplug
+  HotplugServer,                                          ///< Server Hotplug
+  HotplugEnhanced,                                        ///< Enhanced
+  MaxHotplug                                              ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+  PortDisabled,                                           ///< Disable
+  PortEnabled                                             ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+  Aux1,                                                   ///< Aux1
+  Aux2,                                                   ///< Aux2
+  Aux3,                                                   ///< Aux3
+  Aux4,                                                   ///< Aux4
+  Aux5,                                                   ///< Aux5
+  Aux6,                                                   ///< Aux6
+  MaxAux                                                  ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+  Hdp1,                                                   ///< Hdp1
+  Hdp2,                                                   ///< Hdp2
+  Hdp3,                                                   ///< Hdp3
+  Hdp4,                                                   ///< Hdp4
+  Hdp5,                                                   ///< Hdp5
+  Hdp6,                                                   ///< Hdp6
+  MaxHdp                                                  ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+// Macro for statically initialization of various structures
+#define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxGen, mSpeedChangeMode, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxGen, mSpeedChangeMode, mAspm, mHotplug, mResetId }
+#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex}
+
+/*----------------------------------------------------------------------------
+ *   GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// GNB configuration info
+typedef struct {
+  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+                                                        * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
+                                                        * Example of topology definition for single socket system:
+                                                        * @code
+                                                        *  PCIe_PORT_DESCRIPTOR PortList [] = {
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    }
+                                                        *  };
+                                                        *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+                                                        *    },
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+                                                        *    }
+                                                        *  };
+                                                        * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+                                                        *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
+                                                        *   0,  //Socket ID
+                                                        *   &PortList[0],
+                                                        *   &DdiList[0],
+                                                        * }
+                                                        * @endcode
+                                                        */
+  IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
+                                                         *  @li @b 0 - Disabled
+                                                         *  @li @b 1 - Performance
+                                                         *  @li @b 2 - Balance-High
+                                                         *  @li @b 3 - Balance-Low
+                                                         *  @li @b 4 - Power Saving
+                                                         */
+
+} GNB_CONFIGURATION;
+//
+//  MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+//   These Max values are used to define array sizes and associated loop
+//   counts in the code.  They reflect the maximum values that AGESA
+//   currently supports and does not necessarily reflect the hardware
+//   capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
+                                    ///< Eg: UINT16  *RcvEnDlys;
+                                    ///<     UINT8   *WrDqsDlys;
+                                    ///<     UINT8   *RdDqsDlys;
+                                    ///<     UINT8   *WrDatDlys;
+                                    ///<     UINT8   *RdDqsMinDlys;
+                                    ///<     UINT8   *RdDqsMaxDlys;
+                                    ///<     UINT8   *WrDatMinDlys;
+                                    ///<     UINT8   *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES     16   ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
+
+typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
+
+//        AGESA DEFINITIONS
+//
+//        Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
+/// CPU Package Type
+#define PT_L1       0                 ///< L1 Package type
+#define PT_M2       1                 ///< AM Package type
+#define PT_S1       2                 ///< S1 Package type
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+  IN OUT   UINT64 Family;             ///< Indicates logical ID Family
+  IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+  AMD_PLATFORM_SERVER = 0x8000,     ///< Server
+  AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
+  AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+  DDR2_TECHNOLOGY,      ///< DDR2 technology
+  DDR3_TECHNOLOGY       ///< DDR3 technology
+} TECHNOLOGY_TYPE;
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+typedef enum {
+  DDR400_FREQUENCY = 200,     ///< DDR 400
+  DDR533_FREQUENCY = 266,     ///< DDR 533
+  DDR667_FREQUENCY = 333,     ///< DDR 667
+  DDR800_FREQUENCY = 400,     ///< DDR 800
+  DDR1066_FREQUENCY = 533,    ///< DDR 1066
+  DDR1333_FREQUENCY = 667,    ///< DDR 1333
+  DDR1600_FREQUENCY = 800,    ///< DDR 1600
+  DDR1866_FREQUENCY = 933,    ///< DDR 1866
+  UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
+} MEMORY_BUS_SPEED;
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+typedef enum {
+  QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
+  QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
+} QUANDRANK_TYPE;
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+typedef enum {
+  TIMING_MODE_AUTO,           ///< Use best rate possible
+  TIMING_MODE_LIMITED,        ///< Set user top limit
+  TIMING_MODE_SPECIFIC        ///< Set user specified speed
+} USER_MEMORY_TIMING_MODE;
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+typedef enum {
+  POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
+  POWER_DOWN_BY_CHIP_SELECT   ///< Chip select power down mode
+} POWER_DOWN_MODE;
+
+/// Low voltage support
+typedef enum {
+  VOLT1_5,                   ///< 1.5 Volt
+  VOLT1_35,                  ///< 1.35 Volt
+  VOLT1_25,                  ///< 1.25 Volt
+  VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// UMA Mode
+typedef enum {
+  UMA_NONE = 0,              ///< UMA None
+  UMA_SPECIFIED = 1,         ///< UMA Specified
+  UMA_AUTO = 2               ///< UMA Auto
+} UMA_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+  NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
+  UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
+  UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
+  UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+///   Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+  GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
+  GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
+  GsbDramECCDis,             ///< Dram ECC requested but not enabled.
+  GsbSoftHole,               ///< A Node Base gap was created
+  GsbHWHole,                 ///< A HW dram remap was created
+  GsbNodeIntlv,              ///< Node Memory interleaving was enabled
+  GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                     ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+  EsbNoDimms,                  ///< No DIMMs
+  EsbSpdChkSum,                ///< SPD Checksum fail
+  EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
+  EsbDimmMismatchT,            ///< dimm CL/T mismatch
+  EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
+  EsbNoCycTime,                ///< SPD missing byte 23 or 25
+  EsbBkIntDis,                 ///< Bank interleave requested but not enabled
+  EsbDramECCDis,               ///< Dram ECC requested but not enabled
+  EsbSpareDis,                 ///< Online spare requested but not enabled
+  EsbMinimumMode,              ///< Running in Minimum Mode
+  EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
+  EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos,                 ///< No DQS-DQ passing positions
+  EsbSmallDqs,                 ///< DQS-DQ passing window too small
+  EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
+
+  EsbEMPNotSupported,          ///< Processor is not capable for EMP.
+  EsbEMPConflict,               ///< EMP requested but cannot be enabled since
+                               ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis,                   ///< EMP requested but cannot be enabled since
+                               ///< memory size of each DCT is not a power of two.
+
+  EsbEOL                       ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+///  Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+  SbRegistered,                ///< All DIMMs are Registered
+  SbEccDimms,                  ///< All banks ECC capable
+  SbParDimms,                  ///< All banks Addr/CMD Parity capable
+  SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
+  Sb128bitmode,                ///< DCT in 128-bit mode operation
+  Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
+  Sb2TMode,                    ///< 2T CMD timing mode is enabled.
+  SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
+  SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
+
+  SbEOL                        ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG     0xC0010010
+#ifndef TOP_MEM
+  #define TOP_MEM   0xC001001A
+#endif
+#ifndef TOP_MEM2
+  #define TOP_MEM2  0xC001001D
+#endif
+#define HWCR        0xC0010015
+#define NB_CFG      0xC001001F
+
+#define FS_BASE     0xC0000100
+#define IORR0_BASE  0xC0010016
+#define IORR0_MASK  0xC0010017
+#define BU_CFG      0xC0011023
+#define BU_CFG2     0xC001102A
+#define COFVID_STAT 0xC0010071
+#define TSC         0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+  IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
+  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+  OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
+  OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
+                                 ///<  DIMM#  Select Signal
+                                 ///<  0      MA0_CS_L[0, 1]
+                                 ///<  1      MB0_CS_L[0, 1]
+                                 ///<  2      MA1_CS_L[0, 1]
+                                 ///<  3      MB1_CS_L[0, 1]
+                                 ///<  4      MA2_CS_L[0, 1]
+                                 ///<  5      MB2_CS_L[0, 1]
+                                 ///<  6      MA3_CS_L[0, 1]
+                                 ///<  7      MB3_CS_L[0, 1]
+
+  OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+  OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+  OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+                                 ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  OUT UINT8   ChDimmValid;       ///< For each bit n 0..7, 1 = DIMM n is valid and is/will be configured
+                                 ///<
+  OUT UINT8   RegDimmPresent;    ///< For each bit n 0..7, 1 = DIMM n is a registered DIMM
+  OUT UINT8   SODimmPresent;    ///< For each bit n 0..7, 1 = DIMM n is a SO-DIMM
+  OUT UINT8   Loads;             ///< Number of devices loading bus
+  OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
+  OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
+  OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
+                                 ///< FALSE = 1T
+                                 ///< TRUE = 2T
+  ///< The following pointers will be pointed to dynamically allocated buffers.
+  ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ///< Example: If DIMM and Byte based training, then
+  ///< XX is a value in Hex
+  ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
+  OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
+  OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
+  OUT UINT8   *WrDatDlys;       ///< Write Data delays
+  OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
+  OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
+  OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
+  OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
+  OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
+  OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
+  OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
+  OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+  OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+  OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+  OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+  OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
+  OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
+  OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
+  OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
+  OUT UINT8   Pattern;            ///< Current pattern
+  OUT UINT8   DqsDelay;           ///< Current DQS delay value
+  OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT16  DctMaxRdLat;        ///< Max Read Latency (ns) for the DCT
+  OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
+  OUT UINT8   MaxCh;              ///< Max number of CH in system
+  OUT UINT8   Dct;                ///< Dct pointer
+  OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
+  OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
+
+  OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
+  OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
+  OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
+  OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
+  OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+  OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
+  OUT UINT32  NodeSysBase;        ///< for channel interleave usage
+  OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
+  OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
+  OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
+  OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
+  OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
+  OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
+
+  OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
+  OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
+  OUT UINT8   DimmSpdCse;         ///< For each bit n 0..7, 1 = DIMM n SPD checksum error
+  OUT UINT8   DimmExclude;        ///< For each bit n 0..7, 1 = DIMM n gets excluded
+  OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
+  OUT UINT8   Dimmx4Present;      ///< For each bit n 0..7, 1 = DIMM n contains x4 data devices.
+  OUT UINT8   Dimmx8Present;      ///< For each bit n 0..7, 1 = DIMM n contains x8 data devices.
+  OUT UINT8   Dimmx16Present;     ///< For each bit n 0..7, 1 = DIMM n contains x16 data devices.
+
+  OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ///<  base on this array to disable unused MemClk to save power.
+                                  ///<
+                                  ///<  The array must have 8 entries. Each entry, which associates with
+                                  ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+                                  ///<    Example:
+                                  ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+                                  ///<    is like below:
+                                  ///<         Bit AM3/S1g3 pin name
+                                  ///<         0   M[B,A]_CLK_H/L[0]
+                                  ///<         1   M[B,A]_CLK_H/L[1]
+                                  ///<         2   M[B,A]_CLK_H/L[2]
+                                  ///<         3   M[B,A]_CLK_H/L[3]
+                                  ///<         4   M[B,A]_CLK_H/L[4]
+                                  ///<         5   M[B,A]_CLK_H/L[5]
+                                  ///<         6   M[B,A]_CLK_H/L[6]
+                                  ///<         7   M[B,A]_CLK_H/L[7]
+                                  ///<    And platform has the following routing:
+                                  ///<         CS0   M[B,A]_CLK_H/L[4]
+                                  ///<         CS1   M[B,A]_CLK_H/L[2]
+                                  ///<         CS2   M[B,A]_CLK_H/L[3]
+                                  ///<         CS3   M[B,A]_CLK_H/L[5]
+                                  ///<    Then MemClkDisMap should be pointed to the following array:
+                                  ///<               CLK_2 CLK_3 CLK_4 CLK_5
+                                  ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+                                  ///<  Each entry of the array is the bitmask of 8 chip selects.
+
+  OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of CKE pins to the DIMMs' ranks.
+                                  ///<  The array must have 2 entries. Each entry, which associates with
+                                  ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ///<  AGESA will base on this array to disable unused CKE pins to save power.
+
+  OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of ODT pins to the DIMMs' ranks.
+                                  ///<  The array must have 4 entries. Each entry, which associates with
+                                  ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ///<  AGESA will base on this array to disable unused ODT pins to save power.
+
+  OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of chip select pins to the DIMMs' ranks.
+                                  ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ///<  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
+
+  OUT UINT8   Reserved[100];      ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+  OUT UINT16  DctDimmValid;       ///< For each bit n 0..7, 1=DIMM n is valid and is/will be configured
+  OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..7, 1=DIMM n is OnDimmMirror capable
+  OUT UINT16  DimmSpdCse;         ///< For each bit n 0..7, 1=DIMM n SPD checksum error
+  OUT UINT16  DimmExclude;        ///< For each bit n 0..7, 1 = DIMM n gets excluded
+  OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
+  OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
+  OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+  OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
+  OUT UINT16  DIMM1KPage;         ///< For each bit n 0..7, 1=DIMM n contains 1K page devices.
+  OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
+  OUT UINT16  Dimmx4Present;      ///< For each bit n 0..7, 1=DIMM n contains x4 data devices.
+  OUT UINT16  Dimmx8Present;      ///< For each bit n 0..7, 1=DIMM n contains x8 data devices.
+  OUT UINT16  Dimmx16Present;     ///< For each bit n 0..7, 1=DIMM n contains x16 data devices.
+
+  OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
+  OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
+  OUT UINT16  Speed;              ///< DRAM bus speed in MHz
+                                  ///<  400 (MHz)
+                                  ///<  533 (MHz)
+                                  ///<  667 (MHz)
+                                  ///<  800 (MHz)
+                                  ///<  and so on...
+  OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
+  OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
+  OUT UINT8   Trp;                ///< DCT Trp (busclocks)
+  OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
+  OUT UINT8   Tras;               ///< DCT Tras (busclocks)
+  OUT UINT8   Trc;                ///< DCT Trc (busclocks)
+  OUT UINT8   Twr;                ///< DCT Twr (busclocks)
+  OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
+  OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
+  OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
+  OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
+                                  ///<  0 = 75ns (for 256Mb devs)
+                                  ///<  1 = 105ns (for 512Mb devs)
+                                  ///<  2 = 127.5ns (for 1Gb devs)
+                                  ///<  3 = 195ns (for 2Gb devs)
+                                  ///<  4 = 327.5ns (for 4Gb devs)
+  OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
+                                  ///<
+  OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
+                                  ///< FALSE = 1T
+                                  ///< TRUE = 2T
+  OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
+  OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
+  OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
+  OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
+  OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
+  OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
+  OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
+  OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
+  OUT UINT16  MaxRdLat;           ///< Max Read Latency
+  OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
+  OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+  OUT UINT8   Dct;                ///< Current Dct
+  OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
+  OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
+  OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+  /// Advanced:
+
+  OUT UINT8   NodeId;              ///< Node ID of current controller
+  OUT UINT8   SocketId;            ///< Socket ID of this Die
+  OUT UINT8   DieId;               ///< ID of this die relative to the socket
+  OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
+  OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
+                                   ///<  0x0 = AGESA_SUCCESS
+                                   ///<  0x1 = AGESA_UNSUPPORTED
+                                   ///<  0x2 = AGESA_BOUNDS_CHK
+                                   ///<  0x3 = AGESA_ALERT
+                                   ///<  0x4 = AGESA_WARNING
+                                   ///<  0x5 = AGESA_ERROR
+                                   ///<  0x6 = AGESA_CRITICAL
+                                   ///<  0x7 = AGESA_FATAL
+                                   ///<
+  OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
+                                   ///<
+  OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
+                                   ///<
+  OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+                                   ///<
+  OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
+                                   ///<
+  OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+                                   ///<
+  OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
+                                   ///<
+  OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
+                                   ///<   DIMM#  Select Signal
+                                   ///<   0      MA0_CS_L[0, 1]
+                                   ///<   1      MB0_CS_L[0, 1]
+                                   ///<   2      MA1_CS_L[0, 1]
+                                   ///<   3      MB1_CS_L[0, 1]
+                                   ///<   4      MA2_CS_L[0, 1]
+                                   ///<   5      MB2_CS_L[0, 1]
+                                   ///<   6      MA3_CS_L[0, 1]
+                                   ///<   7      MB3_CS_L[0, 1]
+                                   ///<
+  OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+  OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+  OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+                                   ///<
+  OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
+  OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
+                                   ///<  0 in any bit field indicates Channel 0
+                                   ///<  1 in any bit field indicates Channel 1
+  OUT UINT8   Dct;                 ///<  Need to be removed
+                                   ///<  DCT pointer
+  OUT BOOLEAN GangedMode;          ///< Ganged mode
+                                   ///<  0 = disabled
+                                   ///<  1 = enabled
+  OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+                                   ///<
+  OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT8   MLoad;               ///< Need to be removed
+                                   ///< Number of devices loading MAA bus
+                                   ///<
+  OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
+                                   ///<
+  OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
+                                   ///<
+  OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
+                                   ///<
+  OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+  OUT UINT8   DctCount;            ///< Number of DCTs per this Die
+  OUT UINT8   Reserved[16];        ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+     OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
+     OUT   UINT16 Version;             ///< S3 Params version number
+  IN OUT   UINT32 Flags;               ///< Indicates operation
+  IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
+  IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
+  IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
+  IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+  // Basic (Return parameters)
+  // (This section contains the outbound parameters from the memory init code)
+
+  OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
+                                  ///<
+  OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+                                  ///<
+  OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
+                                  ///<
+  OUT UINT32 Sub1THoleBase;       ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+                                  ///<
+  OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
+                                  ///<
+
+  OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
+                                  ///< 0 = 1.5v
+                                  ///< 1 = 1.35v
+                                  ///< 2 = 1.2v
+                                  ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
+                                  ///<        from the system.
+                                  ///<
+
+  OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
+
+  //  Advanced (Optional parameters)
+  //  Optional (all defaults values will be initialized by the
+  //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
+  //  to the IBV/OEM to change the defaults after initialization
+  //  but prior to the main entry to the memory code):
+
+  // Memory Map/Mgt.
+
+  IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
+                                   ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
+                                   ///<
+  IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+  IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+
+  // Dram Timing
+
+  IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
+                                                ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+  IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
+                                                ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+  // Dram Configuration
+
+  IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
+                                   ///<  - FALSE =disable (default)
+                                   ///<  - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+  IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+  IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+  // ECC
+
+  IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+  // Dram Power
+
+  IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
+                                   ///<   - FALSE =disable (default)
+                                   ///<   - TRUE =enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+  // Online Spare
+
+  IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+                                   ///<  - FALSE = disable Spare (default)
+                                   ///<  - TRUE = enable Spare
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+  IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+  IN PSO_TABLE *PlatformMemoryConfiguration;
+                                   ///< A table that contains platform specific settings.
+                                   ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+                                   ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ///< contains default conservative settings. Platform BIOS can either tweak
+                                   ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ///<
+  IN BOOLEAN EnableParity;         ///< Parity control.
+                                   ///<  - TRUE = enable
+                                   ///<  - FALSE = disable (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+  IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+                                   ///<
+
+  IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+
+  // Uma Configuration
+
+  IN UMA_MODE UmaMode;             ///<  Uma Mode
+                                   ///<  0 = None
+                                   ///<  1 = Specified
+                                   ///<  2 = Auto
+  IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
+                                   ///<  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ///<
+  OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
+                                   ///<  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ///<
+
+  /// Memory Restore Feature
+
+  IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
+                                   ///<   FALSE = perform memory init as normal (AMD default)
+                                   ///<   TRUE = restore memory context and skip training. This requires
+                                   ///<          MemContext is valid before AmdInitPost
+                                   ///<
+  IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
+                                   ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ///<   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ///<           expected to call S3Save later in POST if it wants to
+                                   ///<           use memory context restore feature.
+                                   ///<
+  IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+                                   ///< save and restore for memory context restore feature to work.
+                                   ///< It uses the subset of S3Save block to save/restore. Hence platform
+                                   ///< may save only S3 block and uses it for both S3 resume and
+                                   ///< memory context restore.
+                                   ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ///<    before AmdInitPost.
+                                   ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ///<    right after AmdInitPost.
+                                   ///<
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+  // PUBLIC required Internal functions
+
+  IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
+  IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
+
+  // PUBLIC optional functions
+
+  IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
+  IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+  IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
+  IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
+  IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
+  IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
+  IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
+  IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
+  IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
+  IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
+
+  IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+  OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
+
+  OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+  IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+
+  IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
+
+  OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
+
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+  OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
+                                   ///< SocketList is a shortcut for IBVs to retrieve training
+                                   ///< and timing data for each channel indexed by socket/channel,
+                                   ///< eliminating their need to parse die/dct/channel etc.
+                                   ///< It contains pointers to the populated data structures for
+                                   ///< each channel and skips the channel structures that are
+                                   ///< unpopulated. In the case of channels sharing the same DCT,
+                                   ///< the pTimings pointers will point to the same DCT Timing data.
+
+  OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
+  OUT UINT8      DieCount;        ///< Number of MCTs in the system.
+
+  IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
+
+  IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
+
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+  OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
+  OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
+  OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
+  OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
+  OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
+  OUT UINT8 Reserved[3];       ///< Reserved for future usage
+} UMA_INFO;
+
+//  AGESA MEMORY ERRORS
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
+                                                       ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_ECC_DIS 0x04010400                  ///< ECC has been disabled as a result of an internal issue
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x04011600   ///< Returned PRE value during write levelizzation was out of range
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
+                                                        ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED      0x04022500     ///< VDDIO of the dimms on the board is not supported
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                    CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
+#define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
+
+//================================================================
+// CPU General events
+//    Heap allocation                     (AppFunction =      01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
+#define CPU_ERROR_HEAP_IS_FULL                          0x08020100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
+//    BrandId                             (AppFunction =      02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
+//    Micro code patch                    (AppFunction =      03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
+//    Power management                    (AppFunction =      04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
+//    BIST                                (AppFunction =      05h)
+#define CPU_EVENT_BIST_ERROR                            0x08000500
+
+//=================================================================
+// CPU Feature events
+//    Execution cache                     (AppFunction =      21h)
+//        AGESA_CACHE_SIZE_REDUCED                            2101
+//        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
+//        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
+//        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
+//        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
+//        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
+//        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
+//    Core Leveling                       (AppFunction =      22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
+//    HT Assist                           (AppFunction =      23h)
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+  IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
+  IN  UINT64 MsrData;     ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000    0x00000250
+#define AMD_AP_MTRR_FIX16k_80000    0x00000258
+#define AMD_AP_MTRR_FIX16k_A0000    0x00000259
+#define AMD_AP_MTRR_FIX4k_C0000     0x00000268
+#define AMD_AP_MTRR_FIX4k_C8000     0x00000269
+#define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
+#define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
+#define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
+#define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
+#define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
+#define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
+#define CPU_LIST_TERMINAL           0xFFFFFFFF
+
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN        UINT32              BufferLength;   ///< Size of buffer to allocate
+  IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
+  OUT       VOID                *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
+  IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
+  IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
+  IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN        UINT8               SocketId;       ///< Address of SPD - socket ID
+  IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
+  IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
+  IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
+  IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// Buffer Handles
+typedef enum {
+  AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE                  ///< Assign 0x000D008 buffer handle to S3 NB device info
+} AMD_BUFFER_HANDLE;
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+  IN        UINTN               ResetType,
+  IN OUT    AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
+  );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
+  );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
+  );
+
+AGESA_STATUS
+AgesaReadSpd (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN               ApicIdOfCore,
+  IN        AP_EXE_PARAMS       *LaunchApParams
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+ );
+
+/************************************************************************
+ *
+ *  AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration:  The parameters in boot branch function
+ **********************************************************************/
+
+///  The possible platform control flow settings.
+typedef enum  {
+  Nfcm,                                          ///< Normal Flow Control Mode.
+  UmaDr,                                         ///< UMA using Display Refresh flow control.
+  UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
+  Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
+  Iommu,                                         ///< An IOMMU is in use in the system.
+  MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+///  Platform Deemphasis Levels.
+///
+/// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
+/// set based on the level of the far transmitter.
+typedef enum {
+  DeemphasisLevelNone,                           ///< No Deemphasis.
+  DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
+  DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
+  DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
+  DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone = 16,                             ///< No DCV Deemphasis.
+  DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
+  DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
+  DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
+  DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
+  DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
+  DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
+  DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
+  DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
+} PLATFORM_DEEMPHASIS_LEVEL;
+
+///  Provide Deemphasis Levels for HT Links.
+///
+///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
+///  is in the inclusive range HighFreq:LoFreq.
+///  AGESA does not set deemphasis in IO devices, only in processors.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
+  IN       UINT8 Link;                                          ///< The Link on this Processor.
+  IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
+  IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
+  // Value fields
+  IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
+  IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
+} CPU_HT_DEEMPHASIS_LEVEL;
+
+///  The possible platform power policy settings.
+typedef enum  {
+  Performance,                                   ///< Optimize for performance.
+  BatteryLife,                                   ///< Optimize for battery life.
+  MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+///  Platform performance settings for optimized settings.
+///  Several configuration settings for the processor depend upon other parts and
+///  general designer choices for the system. The determination of these data points
+///  is not standard for all platforms, so the host environment needs to provide these
+///  to specify how the system is to be configured.
+typedef struct {
+  IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+  IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
+  IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
+                                                       ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+  IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+                                                       ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+  IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+} PERFORMANCE_PROFILE;
+
+///  Platform settings that describe the voltage regulator modules of the system.
+///  Many power management settings are dependent upon the characteristics of the
+///  on-board voltage regulator module (VRM).  The host environment needs to provide
+///  these to specify how the system is to be configured.
+typedef struct {
+  IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+  IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+  IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+  IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
+  IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+  IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
+} PLATFORM_VRM_CONFIGURATION;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+  IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
+
+  //Build Option Area
+  IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+  IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+  IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+  IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+  IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+  IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+  IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+  IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+  IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+  IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+  IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+  IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+  IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+  IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+  IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+  IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+  IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+  IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+  IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg;    ///< Several configuration settings for the voltage regulator module.
+  IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
+  IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
+  IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
+  IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+  IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
+  IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
+  IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
+  IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+
+  IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
+  IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
+
+  IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+  IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+  IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+  IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+  IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
+  IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
+  IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+  IN BOOLEAN CfgLimitMemoryToBelow1Tb;            ///< Limit memory address space to below 1TB
+  IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
+  IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
+  IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
+  IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+  IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
+  IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
+  IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
+  IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
+  IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
+  IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
+  IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+  IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+  IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+  IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+  IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+  IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+  IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+  IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
+  IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
+  IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
+  IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+  IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
+  IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
+  IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
+  IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
+  IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
+  IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
+  IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
+  IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
+  IN UINT8   CfgAbmSupport;                       ///< Abm Support
+  IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DYNAMIC_REFRESH_RATE}
+  IN UINT8   CfgLcdBackLightControl;              ///< LCD Backlight Control
+  IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+
+  IN BOOLEAN Reserved;                            ///< reserved...
+} BUILD_OPT_CFG;
+
+///  A structure containing platform specific operational characteristics. This
+///  structure is initially populated by the initializer with a copy of the same
+///  structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+  IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
+  IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
+                                                      ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
+  IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
+                                                      ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+  IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
+  IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
+  IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+  IN UINT32              CStatePlatformData;          ///< If CStateMode is C6, specifies a block of 8 free I/O ports to be used for
+                                                      ///< placing the CPU in C6.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+  IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
+  IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
+  IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
+  IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
+  IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
+  IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+  IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
+  IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+  IN PLATFORM_VRM_CONFIGURATION VrmProperties;        ///< Several configuration settings for the voltage regulator module.
+  IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
+  IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
+  IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
+} PLATFORM_CONFIGURATION;
+
+
+/// P-state structure for each state
+typedef struct {
+  IN OUT   UINT32               PStateEnable;                ///< Pstate enable
+  IN OUT   UINT32               CoreFreq;                    ///< MHz
+  IN OUT   UINT32               Power;                       ///< milliWatts
+  IN OUT   UINT32               IddValue;                    ///< Current value field
+  IN OUT   UINT32               IddDiv;                      ///< Current divisor field
+} S_PSTATE_VALUES;
+
+/// P-state structure for each core
+typedef struct {
+  IN OUT   UINT8                PStateMaxValue;              ///< Max p-state number in this core
+  IN OUT   UINT8                HtcPstateLimit;              ///< Htc limit
+  IN OUT   UINT8                HtcCapable;                  ///< Htc capable
+  IN OUT   UINT8                Reserved;                    ///< Reserved
+  IN OUT   S_PSTATE_VALUES      PStateStruct[1];             ///< P state struc
+} S_PSTATE;
+
+/// P-state structure for each node
+typedef struct {
+  IN       UINT8                SetPState0;                  ///< If value = 0x55 (Don't set PState0)
+  IN       UINT8                TotalCoresInNode;            ///< core number per node
+  IN       UINT16               PStateLevelingSizeOfBytes;   ///< Size
+  IN       BOOLEAN              OnlyOneEnabledPState;        ///< Only P0
+  IN       UINT8                InitStruct;                  ///< Init struc
+  IN       BOOLEAN              AllCpusHaveIdenticalPStates; ///< Have Identical p state
+  IN       UINT8                CreateAcpiTables;            ///< Create table flag
+  IN       UINT8                SocketNumber;                ///< Physical socket number of this socket
+  IN       UINT8                Reserved[3];                 ///< Reserved.
+  IN OUT   S_PSTATE             PStateCoreStruct[1];         ///< P state core struc
+} PSTATE_LEVELING;
+
+/// P-state structure for whole system
+typedef struct {
+  IN OUT   UINT32               TotalSocketInSystem;         ///< Total node number in system
+  IN OUT   UINT32               SizeOfBytes;                 ///< Structure size
+  IN OUT   PSTATE_LEVELING      PStateLevelingStruc[1];      ///< P state level structure
+} S_CPU_AMD_PSTATE;
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 0x3
+#define MAX_DIMMS_PER_SOCKET 16
+
+/*  Interface Parameter Structures  */
+/// DMI Type4 - Processor ID
+typedef struct {
+  OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
+  OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+  OUT UINT8                     T4ProcType;             ///< CPU Type
+  OUT UINT8                     T4ProcFamily;           ///< Family 1
+  OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
+  OUT UINT8                     T4Voltage;              ///< Voltage
+  OUT UINT16                    T4ExternalClock;        ///< External clock
+  OUT UINT16                    T4MaxSpeed;             ///< Max speed
+  OUT UINT16                    T4CurrentSpeed;         ///< Current speed
+  OUT UINT8                     T4Status;               ///< Status
+  OUT UINT8                     T4ProcUpgrade;          ///< Up grade
+  OUT UINT8                     T4CoreCount;            ///< Core count
+  OUT UINT8                     T4CoreEnabled;          ///< Core Enable
+  OUT UINT8                     T4ThreadCount;          ///< Thread count
+  OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
+  OUT UINT16                    T4ProcFamily2;          ///< Family 2
+  OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+  OUT UINT16                    T7CacheCfg;             ///< Cache cfg
+  OUT UINT16                    T7MaxCacheSize;         ///< Max size
+  OUT UINT16                    T7InstallSize;          ///< Install size
+  OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
+  OUT UINT16                    T7CurrentSramType;      ///< Current type
+  OUT UINT8                     T7CacheSpeed;           ///< Speed
+  OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
+  OUT UINT8                     T7SystemCacheType;      ///< Cache type
+  OUT UINT8                     T7Associativity;        ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+  OtherLocation = 0x01,                                 ///< Assign 01 to Other
+  UnknownLocation,                                      ///< Assign 02 to Unknown
+  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
+  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
+  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
+  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
+  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
+  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
+  NuBus,                                                ///< Assign 0A to NuBus
+  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+  OtherUse = 0x01,                                      ///< Assign 01 to Other
+  UnknownUse,                                           ///< Assign 02 to Unknown
+  SystemMemory,                                         ///< Assign 03 to system memory
+  VideoMemory,                                          ///< Assign 04 to video memory
+  FlashMemory,                                          ///< Assign 05 to flash memory
+  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
+  CacheMemory                                           ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
+  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
+  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
+  Dmi16Parity,                                          ///< Assign 04 to parity
+  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
+  Dmi16Crc                                              ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
+                                                        ///< whether on the system board or an add-in board.
+  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
+                                                        ///< is used.
+  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                        ///< detection method supported by this memory array.
+  OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
+                                                        ///< for the array.
+  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
+                                                        ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
+  UnknowFormFactor,                                     ///< Assign 02 to Unknown
+  SimmFormFactor,                                       ///< Assign 03 to SIMM
+  SipFormFactor,                                        ///< Assign 04 to SIP
+  ChipFormFactor,                                       ///< Assign 05 to Chip
+  DipFormFactor,                                        ///< Assign 06 to DIP
+  ZipFormFactor,                                        ///< Assign 07 to ZIP
+  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
+  TsopFormFactor,                                       ///< Assign 10 to TSOP
+  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
+  RimmFormFactor,                                       ///< Assign 12 to RIMM
+  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
+  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
+  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+  OtherMemType = 0x01,                                  ///< Assign 01 to Other
+  UnknownMemType,                                       ///< Assign 02 to Unknown
+  DramMemType,                                          ///< Assign 03 to DRAM
+  EdramMemType,                                         ///< Assign 04 to EDRAM
+  VramMemType,                                          ///< Assign 05 to VRAM
+  SramMemType,                                          ///< Assign 06 to SRAM
+  RamMemType,                                           ///< Assign 07 to RAM
+  RomMemType,                                           ///< Assign 08 to ROM
+  FlashMemType,                                         ///< Assign 09 to Flash
+  EepromMemType,                                        ///< Assign 10 to EEPROM
+  FepromMemType,                                        ///< Assign 11 to FEPROM
+  EpromMemType,                                         ///< Assign 12 to EPROM
+  CdramMemType,                                         ///< Assign 13 to CDRAM
+  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
+  SdramMemType,                                         ///< Assign 15 to SDRAM
+  SgramMemType,                                         ///< Assign 16 to SGRAM
+  RdramMemType,                                         ///< Assign 17 to RDRAM
+  DdrMemType,                                           ///< Assign 18 to DDR
+  Ddr2MemType,                                          ///< Assign 19 to DDR2
+  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
+  Fbd2MemType                                           ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
+  OUT UINT16                    StaticColumn:1;         ///< Static column
+  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
+  OUT UINT16                    Rambus:1;               ///< RAMBUS
+  OUT UINT16                    Synchronous:1;          ///< Synchronous
+  OUT UINT16                    Cmos:1;                 ///< CMOS
+  OUT UINT16                    Edo:1;                  ///< EDO
+  OUT UINT16                    WindowDram:1;           ///< Window DRAM
+  OUT UINT16                    CacheDram:1;            ///< Cache Dram
+  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
+  OUT UINT16                    Reserved2:3;            ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
+                                                        ///< Memory Devices that must be populated with all devices of
+                                                        ///< the same type and size, and the set to which this device belongs.
+  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
+  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
+  OUT CHAR8                     PartNumber[19];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 and 20 - for memory use
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT UINT8                     SerialNumber[4];        ///< Serial Number.
+  OUT UINT8                     PartNumber[18];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT8                     Socket:3;               ///< Socket ID
+  OUT UINT8                     Channel:2;              ///< Channel ID
+  OUT UINT8                     Dimm:2;                 ///< DIMM ID
+  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+} MEM_DMI_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                        ///< of a range of memory mapped to the
+                                                        ///< specified physical memory array.
+  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                        ///< last kilobyte of a range of addresses
+                                                        ///< mapped to the specified physical memory array.
+  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                        ///< with the physical memory array to which this
+                                                        ///< address range is mapped.
+  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                        ///< form a single row of memory for the address
+                                                        ///< partition defined by this structure.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+                                                        ///< with the Memory Array Mapped Address structure to
+                                                        ///< which this device address range is mapped.
+  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
+                                                        ///< Device in a row of the address partition.
+  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
+                                                        ///< an interleave.
+  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
+                                                        ///< referenced Memory Device that are accessed in a
+                                                        ///< single interleaved transfer.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+  OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
+  OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
+  OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
+  OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
+  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
+  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+  OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
+  OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+AGESA_STATUS
+CreateAcpiTables (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+
+
+/**********************************************************************
+ * Interface call:  AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS    3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+  IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
+  IN OUT   UINT32               ExeCacheSize;           ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call:  AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
+     OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  );
+
+/// Selection type for core leveling
+typedef enum {
+  CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
+  CORE_LEVEL_TWO,               ///< Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
+  CORE_LEVEL_NONE,              ///< Do no leveling
+  CORE_LEVEL_ONE,               ///< Level to 1 core
+  CORE_LEVEL_THREE,             ///< Level to 3 cores
+  CORE_LEVEL_FOUR,              ///< Level to 4 cores
+  CORE_LEVEL_FIVE,              ///< Level to 5 cores
+  CORE_LEVEL_SIX,               ///< Level to 6 cores
+  CORE_LEVEL_SEVEN,             ///< Level to 7 cores
+  CORE_LEVEL_EIGHT,             ///< Level to 8 cores
+  CORE_LEVEL_NINE,              ///< Level to 9 cores
+  CORE_LEVEL_TEN,               ///< Level to 10 cores
+  CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
+  CORE_LEVEL_TWELVE,            ///< Level to 12 cores
+  CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
+  CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
+  CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
+  CoreLevelModeMax              ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ *  AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call:  AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+  IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
+  IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS     *ResetParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
+  IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS     *EarlyParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS       *EnvParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS       *MidParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
+     OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
+     OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
+     OUT   VOID                   *AcpiSrat;              ///< SRAT Table
+     OUT   VOID                   *AcpiSlit;              ///< SLIT Table
+     OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
+     OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS      *LateParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
+  IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
+  IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
+  IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+  IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS    *ResumeParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+     OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call:  AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Core's Socket.
+  IN       UINT8             Core;             ///< The Core id.
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
+     OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call:  AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Processor's socket
+  IN       UINT8             Module;           ///< The Module in that Processor
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
+     OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT8             Socket;            ///< The current Core's Socket
+     OUT   UINT8             Module;            ///< The current Core's Processor Module
+     OUT   UINT8             Core;              ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call:  AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
+     OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
+     OUT   UINT32            DataParam1;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam2;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam3;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam4;        ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
+  IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
+  OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
+  OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
+  OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+  IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
+  OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+  IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
+  IN OUT UINTN Reserved;              ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  );
+
+
+#define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
+
+/// AGESA IDS NV ID Definitions
+typedef enum {
+  AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                    specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE,                               ///< 0x0001                                   Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                               Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                  Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0004                                   Enable or disable Channel Interleave
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0005                  Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0006                          Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x0007                   Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB,                            ///< 0x0008                  Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB,                            ///< 0x0009                  Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000A           Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000B                                                    Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x000C                             Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x000D                                                    Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x000E                                           Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x000F                               Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0010                                         Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0011                                          Enable or disable DLLShutdown
+
+  AGESA_IDS_NV_PROBEFILTER,                         ///< 0x0012                                          Enable or Disable ProbeFilter
+
+  AGESA_IDS_NV_HDTOUT,                              ///< 0x0013                                       Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x0014                                                         HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT,                          ///< 0x0015                                                           HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x0016                                                      HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x0017                                                       HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x0018                                                      HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x0019                                         Enable or disable GNB HD Audio
+  AGESA_IDS_EXT_ID_END,                             ///< 0x001A                                      specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/f10/AMD.h b/src/vendorcode/amd/agesa/f10/AMD.h
new file mode 100755
index 0000000000..81a97acb37
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/AMD.h
@@ -0,0 +1,478 @@
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 7668 $   @e \$Date: 2008-08-25 18:59:15 -0700 (Mon, 25 Aug 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define AGESA_REVISION  "Arch2008"
+#define AGESA_ID        "AGESA"
+
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY          0xFFFFFFFF
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+  AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
+                                 ///<  Not logged.
+  AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
+                                 ///< Example, memory address not installed, heap buffer handle not found.
+                                 ///< Not Logged.
+  // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT,                   ///< An observed condition, but no loss of function.
+                                 ///<  See log.  Example, HT CRC.
+  AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
+  AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
+  AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
+                                 ///< may not be able to reliably produce log events.
+  AgesaStatusMax                 ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in]        Function      The specific callout function being invoked.
+ * @param[in]        FcnData       Function specific data item.
+ * @param[in,out]    ConfigPtr     Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+  IN       UINT32  Function,
+  IN       UINTN   FcnData,
+  IN OUT   VOID    *ConfigPtr
+  );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+  // AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY = 0x00020000,                           ///< AmdInitRecovery entry point handle
+  AMD_CREATE_STRUCT,                                        ///< AmdCreateStruct handle
+  AMD_INIT_EARLY,                                           ///< AmdInitEarly entry point handle
+  AMD_INIT_ENV,                                             ///< AmdInitEnv entry point handle
+  AMD_INIT_LATE,                                            ///< AmdInitLate entry point handle
+  AMD_INIT_MID,                                             ///< AmdInitMid entry point handle
+  AMD_INIT_POST,                                            ///< AmdInitPost entry point handle
+  AMD_INIT_RESET,                                           ///< AmdInitReset entry point handle
+  AMD_INIT_RESUME,                                          ///< AmdInitResume entry point handle
+  AMD_RELEASE_STRUCT,                                       ///< AmdReleaseStruct handle
+  AMD_S3LATE_RESTORE,                                       ///< AmdS3LateRestore entry point handle
+  AMD_S3_SAVE,                                              ///< AmdS3Save entry point handle
+  AMD_GET_APIC_ID,                                          ///< AmdGetApicId entry point handle
+  AMD_GET_PCI_ADDRESS,                                      ///< AmdGetPciAddress entry point handle
+  AMD_IDENTIFY_CORE,                                        ///< AmdIdentifyCore general service handle
+  AMD_READ_EVENT_LOG,                                       ///< AmdReadEventLog general service handle
+  AMD_LATE_RUN_AP_TASK,                                     ///< AmdLateRunApTask entry point handle
+  AMD_IDENTIFY_DIMMS                                        ///< AmdIdentifyDimm general service handle
+} AGESA_STRUCT_NAME;
+
+  /*  ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       UINT32          Func;             ///< The service desired
+  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
+  IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
+  IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
+  IN       UINT64          HeapBasePtr;      ///< Location of the heap
+  IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
+  IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
+  IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
+  IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
+                                                   ///< The struct to init for ByHost allocation,
+                                                   ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+/// AGESA Binary module header structure
+typedef struct {
+  IN  UINT32  Signature;                          ///< Binary Signature
+  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
+  IN  CHAR8   Version[12];                        ///< 12 characters version
+  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
+  IN  UINT32  EntryPointAddress;                  ///< Entry address
+  IN  UINT32  ImageBase;                          ///< Image base
+  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
+  IN  UINT32  ImageSize;                          ///< Size
+  IN  UINT16  Checksum;                           ///< Checksum
+  IN  UINT8   ImageType;                          ///< Type
+  IN  UINT8   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
+  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
+  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
+  IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
+  IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE  {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+  IN  CHAR8   Signature[8];                       ///< code header Signature
+  IN  CHAR8   ComponentName[8];                   ///< 8 character name of the code module
+  IN  CHAR8   Version[12];                        ///< 12 character version string
+  IN  CHAR8   TerminatorNull;                     ///< null terminated string
+  IN  CHAR8   VerReserved[7];                     ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+  IN OUT  UINT32      Register:12;                ///< Register offset
+  IN OUT  UINT32      Function:3;                 ///< Function number
+  IN OUT  UINT32      Device:5;                   ///< Device number
+  IN OUT  UINT32      Bus:8;                      ///< Bus number
+  IN OUT  UINT32      Segment:4;                  ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+  IN  UINT32          AddressValue;               ///< Formal address
+  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
+} PCI_ADDR;
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function(3-bits)
+//   11:00   Offset  (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct {
+  OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
+  OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
+  OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
+  OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19,                ///< HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX                                ///< Limit check.
+} HT_FREQUENCIES;
+// The minimum HT3 frequency
+#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/f10/Dispatcher.h b/src/vendorcode/amd/agesa/f10/Dispatcher.h
new file mode 100755
index 0000000000..ae4caa12df
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Dispatcher.h
@@ -0,0 +1,51 @@
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h
new file mode 100755
index 0000000000..70211fc383
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/AdvancedApi.h
@@ -0,0 +1,155 @@
+/**
+ * @file
+ *
+ * Advanced API Interface for HT, Memory and CPU
+ *
+ * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
+ * would be required by the basic interface implementations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ***************************************************************************/
+
+
+#ifndef _ADVANCED_API_H_
+#define _ADVANCED_API_H_
+
+/*----------------------------------------------------------------------------
+ *                           HT FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  );
+
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  );
+
+/*----------------------------------------------------------------------------
+ *                        HT Recovery   FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ */
+AGESA_STATUS
+AmdHtResetConstructor (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+/**
+ * Initialize HT at Reset for both Normal and Recovery.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+///----------------------------------------------------------------------------
+///                          MEMORY FUNCTIONS PROTOTYPE
+///
+///----------------------------------------------------------------------------
+
+AGESA_STATUS
+AmdMemRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT  PLATFORM_CONFIGURATION   *PlatFormConfig
+  );
+
+VOID
+memDefRet (
+  IN    VOID
+  );
+
+#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f10/Include/CommonReturns.h
new file mode 100755
index 0000000000..ee168a72ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/CommonReturns.h
@@ -0,0 +1,130 @@
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * Routines which do nothing, returning a result (preferably some version of zero) which
+ * is consistent with "do nothing" or "default".  Useful for function pointer tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+ ***************************************************************************
+*/
+
+#ifndef _COMMON_RETURNS_H_
+#define _COMMON_RETURNS_H_
+
+/**
+* Return False.
+*
+* @retval FALSE    Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse (
+  IN    VOID
+);
+
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 (
+  IN    VOID
+);
+
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 (
+  IN    VOID
+);
+
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 (
+  IN    VOID
+);
+
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL (
+  IN    VOID
+);
+
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess (
+  IN    VOID
+);
+
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid (
+  IN    VOID
+);
+
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert (
+  IN    VOID
+);
+
+#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/f10/Include/DanubeInstall.h
new file mode 100755
index 0000000000..22f6392e2c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/DanubeInstall.h
@@ -0,0 +1,1530 @@
+/**
+ * @file
+ *
+ * Install of build options for a Danube platform solution
+ *
+ * This file generates the defaults tables for the "Danube" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DanNiPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  '0000',
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY10H                          TRUE
+#define OPTION_FAMILY10H_DA                       TRUE
+#define OPTION_FAMILY10H_BL                       TRUE
+#define OPTION_MEMCTLR_DA                         TRUE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       TRUE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        TRUE
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     TRUE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              FALSE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   FALSE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      TRUE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          FALSE
+#define OPTION_PARALLEL_TRAINING        FALSE
+#define OPTION_ONLINE_SPARE             FALSE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     FALSE
+#define OPTION_SLIT                     FALSE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     FALSE
+#define OPTION_DDR3                     TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                FALSE
+#define OPTION_CPU_CORELEVLING          TRUE
+#define OPTION_MSG_BASED_C1E            FALSE
+#define OPTION_CPU_CFOH                 TRUE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                5000
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G             BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G             FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   FALSE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE   FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily10h.h"
+#include  "OptionFamily10hBlInstall.h"
+#include  "OptionFamily10hDaInstall.h"
+#include  "OptionFamily10hHyInstall.h"
+#include  "OptionFamily10hRbInstall.h"
+#include  "OptionFamily10hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionDanubeMicrocodeInstall.h"
+#endif
+
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,   // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+
+  // Probe filter enable
+
+  { 0, NULL }
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+{
+  &F10BrandIdString1ArrayS1g4,
+  &F10BrandIdString1ArrayAsb2
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+{
+  &F10BrandIdString2ArrayS1g4,
+  &F10BrandIdString2ArrayAsb2
+};
+CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
diff --git a/src/vendorcode/amd/agesa/f10/Include/DragonInstall.h b/src/vendorcode/amd/agesa/f10/Include/DragonInstall.h
new file mode 100755
index 0000000000..8053073a9f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/DragonInstall.h
@@ -0,0 +1,1531 @@
+/**
+ * @file
+ *
+ * Install of build options for a Dragon platform solution
+ *
+ * This file generates the defaults tables for the "Dragon" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#include  "cpuRegisters.h"
+#include  "cpuFamRegisters.h"
+#include  "cpuFamilyTranslation.h"
+#include  "AdvancedApi.h"
+#include  "heapManager.h"
+#include  "CreateStruct.h"
+#include  "cpuFeatures.h"
+#include  "Table.h"
+#include  "CommonReturns.h"
+#include  "cpuEarlyInit.h"
+#include  "cpuLateInit.h"
+#include  "GnbInterfaceStub.h"
+
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DragonPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  '0000',
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY10H                          TRUE
+#define OPTION_FAMILY10H_BL                       TRUE
+#define OPTION_FAMILY10H_DA                       TRUE
+#define OPTION_FAMILY10H_HY                       FALSE
+#define OPTION_FAMILY10H_RB                       TRUE
+
+#define OPTION_MEMCTLR_DR                         TRUE
+#define OPTION_MEMCTLR_HY                         FALSE
+#define OPTION_MEMCTLR_OR                         FALSE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   TRUE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    TRUE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     TRUE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              TRUE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   TRUE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      TRUE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          TRUE
+#define OPTION_PARALLEL_TRAINING        TRUE
+#define OPTION_ONLINE_SPARE             TRUE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     TRUE
+#define OPTION_SLIT                     TRUE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     FALSE
+#define OPTION_DDR3                     TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                FALSE
+#define OPTION_CPU_CORELEVLING          TRUE
+#define OPTION_MSG_BASED_C1E            FALSE
+#define OPTION_CPU_CFOH                 TRUE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                2500
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G           FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   FALSE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE   FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily10h.h"
+#include  "OptionFamily10hBlInstall.h"
+#include  "OptionFamily10hDaInstall.h"
+#include  "OptionFamily10hHyInstall.h"
+#include  "OptionFamily10hRbInstall.h"
+#include  "OptionFamily10hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionDragonMicrocodeInstall.h"
+#endif
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,   // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+
+  // Probe filter enable
+
+  { 0, NULL }
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+{
+  &F10BrandIdString1ArrayAm3
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+{
+  &F10BrandIdString2ArrayAm3
+};
+
+CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
diff --git a/src/vendorcode/amd/agesa/f10/Include/Filecode.h b/src/vendorcode/amd/agesa/f10/Include/Filecode.h
new file mode 100755
index 0000000000..b189398286
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/Filecode.h
@@ -0,0 +1,547 @@
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE                                         (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE                               (0xBBBB)
+
+#define PROC_GNB_GNBINITATEARLY_FILECODE                                (0xA001)
+#define PROC_GNB_GNBINITATENV_FILECODE                                  (0xA002)
+#define PROC_GNB_GNBINITATLATE_FILECODE                                 (0xA003)
+#define PROC_GNB_GNBINITATMID_FILECODE                                  (0xA004)
+#define PROC_GNB_GNBINITATPOST_FILECODE                                 (0xA005)
+#define PROC_GNB_GNBINITATRESET_FILECODE                                (0xA006)
+#define PROC_GNB_COMMON_CPUACCLIB_FILECODE                              (0xA010)
+#define PROC_GNB_COMMON_GNBHEAPLIB_FILECODE                             (0xA011)
+#define PROC_GNB_COMMON_GNBLIB_FILECODE                                 (0xA012)
+#define PROC_GNB_COMMON_MEMACCLIB_FILECODE                              (0xA013)
+#define PROC_GNB_COMMON_PCIACCLIB_FILECODE                              (0xA014)
+#define PROC_GNB_COMMON_PCILIB_FILECODE                                 (0xA015)
+#define PROC_GNB_COMMON_IOACCLIB_FILECODE                               (0xA016)
+#define PROC_GNB_GFX_GFXCARDINFO_FILECODE                               (0xA020)
+#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE                             (0xA021)
+#define PROC_GNB_GFX_GFXGMCINIT_FILECODE                                (0xA022)
+#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE                          (0xA023)
+#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE                          (0xA024)
+#define PROC_GNB_GFX_GFXINITATPOST_FILECODE                             (0xA025)
+#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE                (0xA026)
+#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE                            (0xA027)
+#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE                             (0xA028)
+#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE                (0xA029)
+#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE                (0xA02A)
+#define PROC_GNB_NB_NBCONFIGDATA_FILECODE                               (0xA030)
+#define PROC_GNB_NB_NBINIT_FILECODE                                     (0xA031)
+#define PROC_GNB_NB_NBINITATEARLY_FILECODE                              (0xA032)
+#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE                           (0xA033)
+#define PROC_GNB_NB_NBINITATRESET_FILECODE                              (0xA034)
+#define PROC_GNB_NB_NBINITATENV_FILECODE                                (0xA035)
+#define PROC_GNB_NB_NBSMULIB_FILECODE                                   (0xA036)
+#define PROC_GNB_NB_NBSMUSERVICES_FILECODE                              (0xA037)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE                  (0xA038)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE                  (0xA039)
+#define PROC_GNB_PCIE_PCIECONFIGDATA_FILECODE                           (0xA041)
+#define PROC_GNB_PCIE_PCIEINIT_FILECODE                                 (0xA043)
+#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE                      (0xA044)
+#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE                       (0xA045)
+#define PROC_GNB_PCIE_PCIEINPUTPARSER_FILECODE                          (0xA046)
+#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE                             (0xA047)
+#define PROC_GNB_PCIE_PCIEMAPTOPOLOGY_FILECODE                          (0xA048)
+#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE                         (0xA049)
+#define PROC_GNB_PCIE_PCIEPIFSERVICES_FILECODE                          (0xA04A)
+#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE                             (0xA04B)
+#define PROC_GNB_PCIE_PCIEPORTREGACC_FILECODE                           (0xA04C)
+#define PROC_GNB_PCIE_PCIETIMER_FILECODE                                (0xA04D)
+#define PROC_GNB_PCIE_PCIETOPOLOGYSERVICES_FILECODE                     (0xA04E)
+#define PROC_GNB_PCIE_PCIETRAINING_FILECODE                             (0xA04F)
+#define PROC_GNB_PCIE_PCIEUTILITYLIB_FILECODE                           (0xA050)
+#define PROC_GNB_PCIE_PCIEWRAPPERREGACC_FILECODE                        (0xA051)
+#define PROC_GNB_PCIE_PCIEPOWERSAVINGFEATURES_FILECODE                  (0xA052)
+#define PROC_GNB_PCIE_PCIESBLINK_FILECODE                               (0xA053)
+#define PROC_GNB_PCIE_PCIEWORKAROUNDS_FILECODE                          (0xA054)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE         (0xA060)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE       (0xA061)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE           (0xA062)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE       (0xA063)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE         (0xA070)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE       (0xA071)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE           (0xA072)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE       (0xA073)
+#define PROC_GNB_PCIE_FEATURE_PCIEASPM_FILECODE                         (0xA074)
+#define PROC_GNB_PCIE_FEATURE_PCIEASPMEXITLATENCY_FILECODE              (0xA075)
+#define PROC_GNB_GFX_GFXPOWERPLAYTABLE_FILECODE                         (0xA076)
+#define PROC_GNB_GFX_GFXFUSETABLEINIT_FILECODE                          (0xA077)
+#define PROC_GNB_NB_NBPOWERMGMT_FILECODE                                (0xA078)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE                          (0xAE01)
+#define PROC_RECOVERY_GNB_GFXRECOVERY_FILECODE                          (0xAE02)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE                       (0xAE03)
+
+#define LIB_AMDLIB_FILECODE                                              (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE                               (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE                                 (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE                                  (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE            (0xC120)
+#define UEFI_DXE_AMDAGESAS3DRIVER_AMDAGESAS3DRIVER_FILECODE              (0xC121)
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE                (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE      (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE                (0xC142)
+#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE                               (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE                                (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE                                  (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE                                 (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE                                  (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE                                 (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE                             (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE                                (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE                               (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE                            (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE                                   (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE                            (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE                               (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE                                (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE                                 (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE                              (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE                                 (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE                               (0xC401)
+#define PROC_CPU_CPUBRANDID_FILECODE                                     (0xC402)
+#define PROC_CPU_TABLE_FILECODE                                          (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE                                   (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE                                    (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE                           (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE                             (0xC408)
+#define PROC_CPU_CPUINITEARLYTABLE_FILECODE                              (0xC409)
+#define PROC_CPU_CPULATEINIT_FILECODE                                    (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE                              (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE                                   (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE                                    (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE                                        (0xC40E)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE                                    (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE                                   (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE                        (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE                       (0xC432)
+#define PROC_CPU_S3_FILECODE                                             (0xC460)
+
+#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE              (0xC801)
+#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE                      (0xC802)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE                (0xC803)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE             (0xC804)
+#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE                          (0xC805)
+#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE                    (0xC806)
+#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE              (0xC807)
+#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE                  (0xC808)
+#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE                    (0xC809)
+#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE                    (0xC80A)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE                   (0xC80B)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE        (0xC80C)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE                   (0xC80D)
+#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE              (0xC80E)
+#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE                    (0xC80F)
+#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE           (0xC810)
+#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE                       (0xC827)
+#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE                  (0xC811)
+#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE             (0xC812)
+#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE              (0xC813)
+#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE                  (0xC814)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE              (0xC815)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE                  (0xC816)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE              (0xC81A)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE              (0xC81B)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE            (0xC81C)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE           (0xC820)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE       (0xC821)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE  (0xC822)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE             (0xC823)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE      (0xC824)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE             (0xC825)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE      (0xC826)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE           (0xC830)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE       (0xC831)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE  (0xC832)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE             (0xC833)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE      (0xC834)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE             (0xC835)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE      (0xC836)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE           (0xC850)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE       (0xC851)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE  (0xC852)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE             (0xC853)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE      (0xC854)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE             (0xC855)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE              (0xC817)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE            (0xC818)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE               (0xC819)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE           (0xC840)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE        (0xC841)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE       (0xC842)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE  (0xC843)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE             (0xC844)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE      (0xC845)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE             (0xC846)
+#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE              (0XC901)
+#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE                      (0XC902)
+#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE                (0XC903)
+#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE                          (0XC904)
+#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE                    (0xC906)
+#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE                    (0xC907)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE                   (0XC908)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE        (0XC909)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE                   (0XC90A)
+#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE              (0XC90B)
+#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE                    (0XC90C)
+#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE           (0XC90D)
+#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE                       (0XC90E)
+#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE                         (0XC90F)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE            (0xC921)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE       (0xC922)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE           (0xC923)
+#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE              (0XCA01)
+#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE                      (0XCA02)
+#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE                (0XCA03)
+#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE                          (0XCA04)
+#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE                    (0xCA06)
+#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE                    (0xCA07)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE                   (0XCA08)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE        (0XCA09)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE                   (0XCA0A)
+#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE              (0XCA0B)
+#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE                    (0XCA0C)
+#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE           (0XCA0D)
+#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE                       (0XCA0E)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE            (0xCA21)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE       (0xCA22)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE                  (0xCA23)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE           (0xCA24)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE                  (0xCA25)
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE                    (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE                           (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE                                 (0xDC10)
+#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE                     (0xDC20)
+#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE                            (0xDC30)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE                        (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE                      (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE                        (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE                                (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE                                (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE                                (0xDC70)
+#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE                               (0xDC80)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE                             (0xDC81)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE                            (0xDC90)
+#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE                         (0xDCA0)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE                        (0xDCB0)
+#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE                        (0xDCC0)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE                           (0xDE01)
+
+#define PROC_HT_FEATURES_HTFEATSETS_FILECODE                             (0xE001)
+#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE                 (0xE002)
+#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE                          (0xE003)
+#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE                      (0xE004)
+#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE                     (0xE005)
+#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE                          (0xE006)
+#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE                         (0xE007)
+#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE              (0xE008)
+#define PROC_HT_FEATURES_HTIDS_FILECODE                                  (0xE009)
+#define PROC_HT_HTFEAT_FILECODE                                          (0xE021)
+#define PROC_HT_HTINTERFACE_FILECODE                                     (0xE022)
+#define PROC_HT_HTINTERFACECOHERENT_FILECODE                             (0xE023)
+#define PROC_HT_HTINTERFACEGENERAL_FILECODE                              (0xE024)
+#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE                          (0xE025)
+#define PROC_HT_HTMAIN_FILECODE                                          (0xE026)
+#define PROC_HT_HTNOTIFY_FILECODE                                        (0xE027)
+#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE                                 (0xE028)
+#define PROC_HT_HTNB_FILECODE                                            (0xE081)
+#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE                           (0xE082)
+#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE                        (0xE083)
+#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE                       (0xE084)
+#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE                          (0xE085)
+#define PROC_HT_FAM10_HTNBFAM10_FILECODE                                 (0xE0C1)
+#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE                         (0xE0C2)
+#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE                      (0xE0C3)
+#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE                     (0xE0C4)
+#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE                           (0xE0C5)
+#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE                        (0xE0C6)
+#define PROC_HT_FAM12_HTNBFAM12_FILECODE                                 (0xE101)
+#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE                        (0xE102)
+#define PROC_HT_FAM14_HTNBFAM14_FILECODE                                 (0xE141)
+#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE                        (0xE142)
+
+#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE                         (0xE302)
+#define PROC_RECOVERY_HT_HTINITRESET_FILECODE                            (0xE301)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE                                (0xE801)
+#define PROC_IDS_CONTROL_IDSLIB_FILECODE                                 (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE                                 (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE                                   (0xE804)
+#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE                   (0xE805)
+#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE                    (0xE806)
+#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE                    (0xE807)
+#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE                    (0xE808)
+#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE                    (0xE809)
+#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE                   (0xE80A)
+#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE                   (0xE80B)
+
+#define PROC_MEM_ARDK_MA_FILECODE                                    (0xF001)
+#define PROC_MEM_ARDK_DR_MARDR2_FILECODE                             (0xF002)
+#define PROC_MEM_ARDK_DR_MARDR3_FILECODE                             (0xF003)
+#define PROC_MEM_ARDK_HY_MARHY3_FILECODE                             (0xF004)
+#define PROC_MEM_ARDK_LN_MASLN3_FILECODE                             (0xF005)
+#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE                             (0xF006)
+#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE                             (0xF007)
+#define PROC_MEM_ARDK_LN_MAULN3_FILECODE                             (0xF008)
+#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE                             (0xF009)
+#define PROC_MEM_ARDK_DA_MASDA2_FILECODE                             (0xF00A)
+#define PROC_MEM_ARDK_DA_MASDA3_FILECODE                             (0xF00B)
+#define PROC_MEM_ARDK_NI_MASNI3_FILECODE                             (0xF00C)
+#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE                          (0xF00D)
+#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE                          (0xF00E)
+#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE                             (0xF00F)
+#define PROC_MEM_ARDK_ON_MASON3_FILECODE                             (0xF010)
+#define PROC_MEM_ARDK_ON_MAUON3_FILECODE                             (0xF011)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE                         (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE                         (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE                             (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE                             (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE                (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE                   (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE                     (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE                       (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE                       (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE                         (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE                 (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE                         (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE             (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE             (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE                               (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE                           (0xF093)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE                                  (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE                                 (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE                                    (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE                             (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE                                 (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE                         (0xF106)
+#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE                              (0xF107)
+#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE                              (0xF108)
+#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE                              (0xF109)
+#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE                              (0xF10A)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE                      (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE                         (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE                    (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE                    (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE                                   (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE                              (0xF110)
+#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE                              (0xF111)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE                                (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE                               (0xF113)
+#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE                             (0xF114)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE                              (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE                            (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE                          (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE                      (0xF118)
+
+#define PROC_MEM_NB_DR_MNDR_FILECODE                                 (0XF213)
+#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE                             (0XF214)
+#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE                         (0XF216)
+#define PROC_MEM_NB_DR_MNMCTDR_FILECODE                              (0XF217)
+#define PROC_MEM_NB_DR_MNDCTDR_FILECODE                              (0XF218)
+#define PROC_MEM_NB_DR_MNOTDR_FILECODE                               (0XF219)
+#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE                         (0XF21A)
+#define PROC_MEM_NB_DR_MNPROTODR_FILECODE                            (0XF21C)
+#define PROC_MEM_NB_DR_MNS3DR_FILECODE                               (0XF21D)
+#define PROC_MEM_NB_DR_MNREGDR_FILECODE                              (0XF21E)
+#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE                             (0XF233)
+#define PROC_MEM_NB_HY_MNHY_FILECODE                                 (0XF235)
+#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE                         (0XF236)
+#define PROC_MEM_NB_HY_MNMCTHY_FILECODE                              (0XF237)
+#define PROC_MEM_NB_HY_MNDCTHY_FILECODE                              (0XF238)
+#define PROC_MEM_NB_HY_MNOTHY_FILECODE                               (0XF239)
+#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE                         (0XF23A)
+#define PROC_MEM_NB_HY_MNPHYHY_FILECODE                              (0XF23B)
+#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE                            (0XF23C)
+#define PROC_MEM_NB_HY_MNS3HY_FILECODE                               (0XF23D)
+#define PROC_MEM_NB_HY_MNREGHY_FILECODE                              (0XF23E)
+#define PROC_MEM_NB_ON_MNON_FILECODE                                 (0xF240)
+#define PROC_MEM_NB_ON_MNREGON_FILECODE                              (0xF241)
+#define PROC_MEM_NB_ON_MNDCTON_FILECODE                              (0xF242)
+#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE                         (0xF244)
+#define PROC_MEM_NB_ON_MNMCTON_FILECODE                              (0xF245)
+#define PROC_MEM_NB_ON_MNOTON_FILECODE                               (0xF246)
+#define PROC_MEM_NB_ON_MNPHYON_FILECODE                              (0xF247)
+#define PROC_MEM_NB_ON_MNS3ON_FILECODE                               (0xF248)
+#define PROC_MEM_NB_ON_MNFLOWON_FILECODE                             (0xF249)
+#define PROC_MEM_NB_LN_MNDCTLN_FILECODE                              (0XF252)
+#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE                             (0XF253)
+#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE                         (0XF254)
+#define PROC_MEM_NB_LN_MNMCTLN_FILECODE                              (0XF255)
+#define PROC_MEM_NB_LN_MNOTLN_FILECODE                               (0XF256)
+#define PROC_MEM_NB_LN_MNPHYLN_FILECODE                              (0XF257)
+#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE                            (0XF258)
+#define PROC_MEM_NB_LN_MNLN_FILECODE                                 (0XF259)
+#define PROC_MEM_NB_LN_MNS3LN_FILECODE                               (0XF25A)
+#define PROC_MEM_NB_LN_MNREGLN_FILECODE                              (0XF25B)
+#define PROC_MEM_NB_DA_MNDA_FILECODE                                 (0XF260)
+#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE                             (0XF261)
+#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE                         (0XF263)
+#define PROC_MEM_NB_DA_MNMCTDA_FILECODE                              (0XF264)
+#define PROC_MEM_NB_DA_MNDCTDA_FILECODE                              (0XF265)
+#define PROC_MEM_NB_DA_MNOTDA_FILECODE                               (0XF266)
+#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE                         (0XF267)
+#define PROC_MEM_NB_DA_MNPROTODA_FILECODE                            (0XF269)
+#define PROC_MEM_NB_DA_MNS3DA_FILECODE                               (0XF26A)
+#define PROC_MEM_NB_DA_MNREGDA_FILECODE                              (0XF26B)
+#define PROC_MEM_NB_C32_MNC32_FILECODE                               (0XF26C)
+#define PROC_MEM_NB_C32_MNDCTC32_FILECODE                            (0XF26D)
+#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE                           (0XF26E)
+#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE                       (0XF26F)
+#define PROC_MEM_NB_C32_MNMCTC32_FILECODE                            (0XF270)
+#define PROC_MEM_NB_C32_MNOTC32_FILECODE                             (0XF271)
+#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE                       (0XF272)
+#define PROC_MEM_NB_C32_MNPHYC32_FILECODE                            (0XF273)
+#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE                          (0XF274)
+#define PROC_MEM_NB_C32_MNS3C32_FILECODE                             (0XF275)
+#define PROC_MEM_NB_C32_MNREGC32_FILECODE                            (0XF277)
+#define PROC_MEM_NB_MN_FILECODE                                      (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE                                   (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE                                   (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE                                   (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE                                    (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE                                  (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE                                  (0XF282)
+#define PROC_MEM_NB_MNTRAIN2_FILECODE                                (0XF283)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE                                (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE                                   (0XF285)
+#define PROC_MEM_NB_NI_MNNI_FILECODE                                 (0XF286)
+#define PROC_MEM_NB_NI_MNS3NI_FILECODE                               (0XF287)
+
+#define PROC_MEM_PS_MP_FILECODE                                      (0XF401)
+#define PROC_MEM_PS_DR_MPRDR3_FILECODE                               (0XF402)
+#define PROC_MEM_PS_HY_MPRHY3_FILECODE                               (0XF403)
+#define PROC_MEM_PS_LN_MPRLN3_FILECODE                               (0XF404)
+#define PROC_MEM_PS_DR_MPSDR3_FILECODE                               (0XF405)
+#define PROC_MEM_PS_HY_MPSHY3_FILECODE                               (0XF406)
+#define PROC_MEM_PS_LN_MPSLN3_FILECODE                               (0XF407)
+#define PROC_MEM_PS_DR_MPUDR3_FILECODE                               (0XF408)
+#define PROC_MEM_PS_HY_MPUHY3_FILECODE                               (0XF409)
+#define PROC_MEM_PS_LN_MPULN3_FILECODE                               (0XF40A)
+#define PROC_MEM_PS_DA_MPUDA3_FILECODE                               (0XF40B)
+#define PROC_MEM_PS_DA_MPSDA2_FILECODE                               (0XF40C)
+#define PROC_MEM_PS_DA_MPSDA3_FILECODE                               (0XF40D)
+#define PROC_MEM_PS_DR_MPRDR2_FILECODE                               (0XF40E)
+#define PROC_MEM_PS_DR_MPUDR2_FILECODE                               (0XF40F)
+#define PROC_MEM_PS_C32_MPRC32_3_FILECODE                            (0XF410)
+#define PROC_MEM_PS_C32_MPUC32_3_FILECODE                            (0XF411)
+#define PROC_MEM_PS_NI_MPSNI3_FILECODE                               (0XF412)
+#define PROC_MEM_PS_NI_MPUNI3_FILECODE                               (0XF413)
+#define PROC_MEM_PS_ON_MPSON3_FILECODE                               (0XF414)
+#define PROC_MEM_PS_ON_MPUON3_FILECODE                               (0XF415)
+
+#define PROC_MEM_TECH_MT_FILECODE                                    (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE                                 (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE                              (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE                                (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE                                (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE                                 (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE                             (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE                                (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE                         (0XF50C)
+#define PROC_MEM_TECH_DDR2_MT2_FILECODE                              (0XF541)
+#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE                            (0XF543)
+#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE                           (0XF544)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE                              (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE                            (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE                           (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE                           (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE                           (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE                           (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE                          (0XF588)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE                             (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE                            (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE                               (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE                              (0XF804)
+#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE                       (0XF812)
+#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE                    (0XF813)
+#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE                    (0XF821)
+#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE                       (0XF822)
+#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE                    (0XF823)
+#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE                  (0XF825)
+#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE                    (0XF831)
+#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE                    (0XF832)
+#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE                       (0XF833)
+#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE                       (0XF842)
+#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE                    (0XF843)
+#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE                       (0XF845)
+#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE                     (0XF851)
+#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE                  (0XF852)
+#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE                (0XF853)
+#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE                    (0xF861)
+#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE                    (0xF862)
+#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE                       (0xF863)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE                      (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE                      (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE                    (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE                 (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE                 (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE                 (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE                 (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE                            (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE                         (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE                         (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE                      (0XF8CB)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h
new file mode 100755
index 0000000000..1821fe3947
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/GeneralServices.h
@@ -0,0 +1,200 @@
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components.  Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+  AGESA_STATUS EventClass;   ///< The severity of the event, its associated AGESA_STATUS.
+  UINT32   EventInfo;        ///< Uniquely identifies the event.
+  UINT32   DataParam1;       ///< Event specific additional data
+  UINT32   DataParam2;       ///< Event specific additional data
+  UINT32   DataParam3;       ///< Event specific additional data
+  UINT32   DataParam4;       ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f10/Include/GnbInterface.h
new file mode 100755
index 0000000000..92f76e6853
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/GnbInterface.h
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * GNB API definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20270 $   @e \$Date: 2009-10-09 10:09:20 -0700 (Fri, 09 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBINTERFACE_H_
+#define _GNBINTERFACE_H_
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN      AMD_CONFIG_PARAMS       *StdHeader,
+  IN      PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN      GNB_CONFIGURATION       *GnbConfig
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN      AMD_CONFIG_PARAMS       *StdHeader,
+  IN OUT  MEM_PARAMETER_STRUCT    *MemConfig
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h
new file mode 100755
index 0000000000..cd06927ac1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/GnbInterfaceStub.h
@@ -0,0 +1,202 @@
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  GNB
+ * @e \$Revision: 20379 $   @e \$Date: 2009-10-12 23:41:06 -0700 (Mon, 12 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset Stub
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Stub
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @param[in] PlatformConfig  Platform configuration
+ * @param[in] GnbConfig       Gnb configuration
+ * @retval    AGESA_STATUS    Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN      AMD_CONFIG_PARAMS       *StdHeader,
+  IN      PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN      GNB_CONFIGURATION       *GnbConfig
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @param[in,out] MemConfig     Memory configuration
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN       AMD_CONFIG_PARAMS       *StdHeader,
+  IN OUT   MEM_PARAMETER_STRUCT    *MemConfig
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AmdGnbRecovery
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return  AGESA_SUCCESS;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Include/Ids.h b/src/vendorcode/amd/agesa/f10/Include/Ids.h
new file mode 100755
index 0000000000..5de4415e8a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/Ids.h
@@ -0,0 +1,791 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision:  $   @e \$Date: 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ***************************************************************************/
+
+  /* Macros to aid debugging */
+  /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE  1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS;  ///< Status of IDS function.
+#define IDS_SUCCESS         ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED     ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+/**
+ *  IDS Option Hook Points
+ *
+ *  These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum {                        //vv- for debug reference only
+  IDS_INIT_EARLY_BEFORE,              ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+                                          ///<   IDS Object is initialized.
+                                          ///<   Override CPU Core Leveling Mode.
+                                          ///<   Set P-State in Post
+  IDS_INIT_EARLY_AFTER,               ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+  IDS_INIT_LATE_BEFORE,               ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+                                          ///< It will be used to control the following tables.
+                                          ///<   ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+                                          ///<   ACPI SRAT Table
+                                          ///<   ACPI SLIT Table
+                                          ///<   ACPI WHEA Table
+                                          ///<   DMI Table
+  IDS_INIT_LATE_AFTER,                ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+  IDS_INIT_MID_BEFORE,                ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+  IDS_INIT_MID_AFTER,                 ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+  IDS_INIT_POST_BEFORE,               ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+                                          ///<   Control Interleaving and DRAM memory hole
+                                          ///<   Override the setting of ECC Control
+                                          ///<   Override the setting of Online Spare Rank
+  IDS_INIT_POST_AFTER,                ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_INIT_RESET_BEFORE,              ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+  IDS_INIT_RESET_AFTER,               ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+  IDS_INIT_POST_MID,                  ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_BEFORE_S3_SAVE,                 ///< 0b override any settings before S3 save.
+  IDS_BEFORE_S3_RESTORE,              ///< 0c  override any settings before S3 restore
+  IDS_AFTER_S3_SAVE,                  ///< 0d Override any settings after S3 save
+  IDS_AFTER_S3_RESTORE,               ///< 0e Override any settings after S3 restore
+  IDS_BEFORE_DQS_TRAINING,            ///< 0f override any settings before DQS training
+  IDS_BEFORE_DRAM_INIT,               ///< 10 override any settings before Dram initialization
+  IDS_BEFORE_MEM_FREQ_CHG,            ///< 11 override settings before MemClk frequency change
+  IDS_AFTER_WARM_RESET ,              ///< 12 Override PCI or MSR Registers Before Warm Reset
+  IDS_BEFORE_MEM_INIT,                ///< 13 Override PCI or MSR Registers Before Memory Init
+  IDS_BEFORE_PCI_INIT,                ///< 14 Override PCI or MSR Registers Before PCI Init
+  IDS_BEFORE_OS,                      ///< 15 Override PCI or MSR Registers Before booting to OS
+  IDS_UCODE,                          ///< 16 Enable or Disable microcode patching
+
+  IDS_PLATFORM_RSVD1 = 0x38,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD2 = 0x39,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD3 = 0x3a,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD4 = 0x3b,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD5 = 0x3c,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD6 = 0x3d,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD7 = 0x3e,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD8 = 0x3f,          ///< from 0x38 to 0x3f will reserved for platform used
+
+  // All the above timing point is used by BVM, their value should never be changed
+  IDS_HT_CONTROL,                     ///< 40 Override the setting of HT Link Control
+  IDS_HT_TRISTATE,                    ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
+  IDS_INIT_DRAM_TABLE,                ///< 42 Generate override table for Dram Timing
+                                          ///< Dram Controller, Drive Strength and DQS Timing
+  IDS_GET_DRAM_TABLE,                 ///< 43 Generate override table for Dram Timing
+  IDS_GANGING_MODE,                   ///< 44 override Memory Mode Unganged
+  IDS_POWERDOWN_MODE,                 ///< 45 override Power Down Mode
+  IDS_BURST_LENGTH32,                 ///< 46 override Burst Length32
+  IDS_ALL_MEMORY_CLOCK,               ///< 47 override All Memory Clks Enable
+  IDS_ECC,                            ///< 48 override ECC parameter
+  IDS_ECCSYMBOLSIZE,                  ///< 49 override ECC symbol size
+  IDS_CPU_Early_Override,             ///< 4a override CPU early parameter
+  IDS_CACHE_FLUSH_HLT,                ///< 4b override Cache Flush Hlt
+  IDS_CHANNEL_INTERLEAVE,             ///< 4c override Channel Interleave
+  IDS_MEM_ERROR_RECOVERY,             ///< 4d override memory error recovery
+  IDS_MEM_RETRAIN_TIMES,              ///< 4e override memory retrain times
+  IDS_MEM_SIZE_OVERLAY,               ///< 4f Override the syslimit
+  IDS_HT_ASSIST,                      ///< 50 Override Probe Filter
+  IDS_CHECK_NEGATIVE_WL,              ///< 51 Check for negative write leveling result
+  IDS_DLL_SHUT_DOWN,                  ///< 52 Check for Dll Shut Down
+  IDS_POR_MEM_FREQ,                   ///< 53 Entry to enable/disable MemClk frequency enforcement
+  IDS_PHY_DLL_STANDBY_CNTRL,          ///< 54 Enable/Disable Phy DLL standby feature
+  IDS_PLATFORMCFG_OVERRIDE,           ///< 55 Hook for Override PlatformConfig structure
+  IDS_LOADCARD_ERROR_RECOVERY,        ///< 56 Special error handling for load card support
+  IDS_MEM_IGNORE_ERROR,                ///< 57 Ignore error and do not do fatal exit in memory
+  IDS_GNB_PPFUSE_OVERRIDE,         ///< 58 override GNB default PowerPlay fuse table
+  IDS_GNB_INTEGRATED_TABLE_CONFIG, ///<59 override GNB integrated table config
+  IDS_GNB_SMU_SERVICE_CONFIG,          ///< 5a Config GNB SMU service
+  IDS_GNB_PCIE_PLATFORM_CONFIG,      ///< 5b Config PCIE platform
+  IDS_GNB_ORBDYNAMIC_WAKE,                   ///< 5c config GNB dynamic wake
+  IDS_GNB_PLATFORMCFG_OVERRIDE   ///< 5d override ids gnb platform config
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+  #define IDSOPT_IDS_ENABLED        FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+  #define IDSOPT_TRACING_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+  #define IDSOPT_HEAP_CHECKING           FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+  #define IDSOPT_ASSERT_ENABLED         FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED   FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef  IDSOPT_CONTROL_ENABLED
+  #undef  IDSOPT_TRACING_ENABLED
+  #undef  IDSOPT_PERF_ANALYSIS
+  #undef  IDSOPT_HEAP_CHECKING
+  #undef  IDSOPT_ASSERT_ENABLED
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #undef  IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+  #define IDSOPT_TRACING_ENABLED    FALSE
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+  #define IDSOPT_HEAP_CHECKING      FALSE
+  #define IDSOPT_ASSERT_ENABLED     FALSE
+  #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+#endif
+
+/**
+ *  Make a Progress Report to the User.
+ *
+ *  This Macro is always enabled. The default action is to write the TestPoint value
+ *  to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ *  IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ *  in OptionsIds.h in their build tip.
+ *
+ *  @param[in]      TestPoint       The value for display indicating progress
+ *  @param[in,out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
+
+#ifndef IDS_DEBUG_PORT
+  #define IDS_DEBUG_PORT  0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ *  (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ *  Causes the program to halt and display the file number of the source of the
+ *  halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+  #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+  #define STOP_HERE  STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ *  Test an assertion that the given statement is True.
+ *
+ *  The statement is evaluated to a boolean value. If the statement is True,
+ *  then no action is taken (no error). If the statement is False, a error stop
+ *  is generated to halt the program. Used for testing for fatal errors that
+ *  must be resolved before production. This is used to do parameter checks,
+ *  bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in]   conditional    Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+  #if IDSOPT_ASSERT_ENABLED == TRUE
+    #ifdef STOP_CODE
+      #undef STOP_CODE
+    #endif
+    #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+    #define ASSERT(conditional) ((conditional) ? 0 : IdsErrorStop (STOP_CODE));
+  #else
+    #define ASSERT(conditional)
+  #endif
+#endif
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)  //IdsCarCorruptionCheck(StdHeader)
+#else
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+  #define IDS_ERROR_TRAP  IdsErrorStop (STOP_CODE)
+#else
+  #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+  #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+  #define IDS_INITIAL_F10_PM_STEP
+  #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+  #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+  #define IDS_EXTENDED_HEAP_SIZE 0
+  #define IDS_EXT_INCLUDE_F10(file)
+  #define IDS_EXT_INCLUDE(file)
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+  #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
+          AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
+#else
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a *skip* hook for IDS options
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, IDS dispatcher function will be called to perform
+ *  the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in]       IdsOption       IDS Option ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
+          if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
+#else
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a heap manager routine
+ *
+ *  when memory is allocated the heap manager actually allocates two extra dwords of data,
+ *  one dword buffer before the actual memory, and one dword afterwards.
+ *  a complete heap walk and check to be performed at any time.
+ *  it would ASSERT if the heap is corrupt
+ *
+ * @param[in]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_HEAP_CHECKING == TRUE
+    #define SIZE_OF_SENTINEL 4
+    #define SENTINEL_BEFORE_VALUE 0xCCAA5533
+    #define SENTINEL_AFTER_VALUE 0x3355AACC
+    #define SET_SENTINEL_BEFORE(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE)) = SENTINEL_BEFORE_VALUE);
+    #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + NodePtr->BufferSize) = SENTINEL_AFTER_VALUE);
+    #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
+  #else
+    #define SIZE_OF_SENTINEL 0
+    #define SENTINEL_BEFORE_VALUE 0xCCAA5533
+    #define SENTINEL_AFTER_VALUE 0x3355AACC
+    #define SET_SENTINEL_BEFORE(NodePtr)
+    #define SET_SENTINEL_AFTER(NodePtr)
+    #define Heap_Check(stdheader)
+  #endif
+#else
+  #define SIZE_OF_SENTINEL 0
+  #define SENTINEL_BEFORE_VALUE 0xCCAA5533
+  #define SENTINEL_AFTER_VALUE 0x3355AACC
+  #define SET_SENTINEL_BEFORE(NodePtr)
+  #define SET_SENTINEL_AFTER(NodePtr)
+  #define Heap_Check(stdheader)
+#endif
+
+/**
+ *  Macro to add HDT OUT in memory code.
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, the debug information can be displayed in HDT or other
+ *  devices.
+ *
+ *  @param[in]       Command    HDT_OUT command to control the communication between
+ *                              HDT and memory initialization code.
+ *  @param[in]       Data       Data to be sent to HDT.
+ *  @param[in]       Condition  Allow the Data to be output if TRUE.
+ *  @param[in]       NvId       NV ID to control this HDT OUT.
+ *  @param[in,out]   StdHeader  The Pointer of AGESA Header.
+ *
+ **/
+#define OPTION_NON_CONSOLE      0xD0
+#define OPTION_HDT_CONSOLE      0xD1
+#define OPTION_IDS_CONSOLE      OPTION_NON_CONSOLE
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_TRACING_ENABLED == TRUE
+    #undef  OPTION_IDS_CONSOLE
+    #define OPTION_IDS_CONSOLE       OPTION_HDT_CONSOLE
+    #define IDS_FUNCLIST_ADDR        ScriptFuncList
+    #define IDS_FUNCLIST_EXTERN()    extern SCRIPT_FUNCTION ScriptFuncList[]
+    #define IDS_TIMEOUT_CTL(t)       IdsMemTimeOut (t)
+
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #ifdef __GNUC__
+      #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
+        #define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args)
+        ///#define IDS_HDT_CONSOLE(f, s, args...) printk(((MEM_FLOW) - (f) + (BIOS_DEBUG)), s, ##args)
+      #else
+        #define IDS_HDT_CONSOLE(s, args...)
+      #endif
+    #else
+     #define IDS_HDT_CONSOLE(s, args...)
+    #endif
+  #else
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE          1 ? (VOID) 0 : AmdIdsConsolePrint
+    #define IDS_FUNCLIST_ADDR        NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+  #endif
+#else
+  #define IDS_HDT_CONSOLE_INIT(x)
+  #define IDS_HDT_CONSOLE_EXIT(x)
+  #define IDS_HDT_CONSOLE          1 ? (VOID) 0 : AmdIdsConsolePrint
+  #define IDS_FUNCLIST_ADDR        NULL
+  #define IDS_FUNCLIST_EXTERN()
+  #define IDS_TIMEOUT_CTL(t)
+#endif
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)  //IdsPerfTimestamp ((StdHeader), (TestPoint))
+  #define IDS_PERF_ANALYSE(StdHeader)   //IdsPerfAnalyseTimestamp (StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)   //AGESA_TESTPOINT (TpPerfUnit, StdHeader); AGESA_TESTPOINT (TpPerfUnit, StdHeader);
+#else
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL  0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY    TRUE
+#define IDS_ALL_CORES   FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID     PROC_IDS_CONTROL_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT      1       ///< The function data of IDS callout function of initialization.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+  UINT32  FuncAddr;       ///< Function address in ROM
+  CHAR8   FuncName[40];   ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ *  AGESA Test Points
+ *
+ *  These are the values displayed to the user to indicate progress through boot.
+ *  These can be used in a debug environment to stop the debugger at a specific
+ *  test point:
+ *  For SimNow!, this command
+ *      bi 81 w vb 49
+ *  will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+  StartProcessorTestPoints,           ///< 00 Entry used for range testing for @b Processor related TPs
+
+  // Memory test points
+  TpProcMemBeforeMemDataInit,         ///< 01 .. Memory structure initialization (Public interface)
+  TpProcMemBeforeSpdProcessing,       ///< 02 .. SPD Data processing  (Public interface)
+  TpProcMemAmdMemAuto,                ///< 03 .. Memory configuration  (Public interface)
+  TpProcMemDramInit,                  ///< 04 .. DRAM initialization
+  TpProcMemSPDChecking,               ///< 05 ..
+  TpProcMemModeChecking,              ///< 06 ..
+  TpProcMemSpeedTclConfig,            ///< 07 .. Speed and TCL configuration
+  TpProcMemSpdTiming,                 ///< 08 ..
+  TpProcMemDramMapping,               ///< 09 ..
+  TpProcMemPlatformSpecificConfig,    ///< 0A ..
+  TPProcMemPhyCompensation,           ///< 0B ..
+  TpProcMemStartDcts,                 ///< 0C ..
+  TpProcMemBeforeDramInit,            ///< 0D .. (Public interface)
+  TpProcMemPhyFenceTraining,          ///< 0E ..
+  TpProcMemSynchronizeDcts,           ///< 0F ..
+  TpProcMemSystemMemoryMapping,       ///< 10 ..
+  TpProcMemMtrrConfiguration,         ///< 11 ..
+  TpProcMemDramTraining,              ///< 12 ..
+  TpProcMemBeforeAnyTraining,         ///< 13 .. (Public interface)
+  TpProcMemWriteLevelizationTraining, ///< 14 ..
+  TpProcMemWlFirstPass,               ///< 15 .. Below 800Mhz first pass start
+  TpProcMemWlSecondPass,              ///< 16 .. Above 800Mhz second pass start
+  TpProcMemWlDimmConfig,              ///< 17 .. Target DIMM configured
+  TpProcMemWlPrepDimms,               ///< 18 ..  Prepare DIMMS for WL
+  TpProcMemWlConfigDimms,             ///< 19 ..  Configure DIMMS for WL
+  TpProcMemReceiverEnableTraining,    ///< 1A ..
+  TpProcMemRcvrStartSweep,            ///< 1B .. Start sweep loop
+  TpProcMemRcvrSetDelay,              ///< 1C .. Set receiver Delay
+  TpProcMemRcvrWritePattern,          ///< 1D .. Write test pattern
+  TpProcMemRcvrReadPattern,           ///< 1E .. Read test pattern
+  TpProcMemRcvrTestPattern,           ///< 1F .. Compare test pattern
+  TpProcMemRcvrCalcLatency,           ///< 20 .. Calculate MaxRdLatency per channel
+  TpProcMemReceiveDqsTraining,        ///< 21 ..
+  TpProcMemRcvDqsSetDelay,            ///< 22 .. Set Write Data delay
+  TpProcMemRcvDqsWritePattern,        ///< 23 .. Write test pattern
+  TpProcMemRcvDqsStartSweep,          ///< 24 .. Start read sweep
+  TpProcMemRcvDqsSetRcvDelay,         ///< 25 .. Set Receive DQS delay
+  TpProcMemRcvDqsReadPattern,         ///< 26 .. Read Test pattern
+  TpProcMemRcvDqsTstPattern,          ///< 27 .. Compare Test pattern
+  TpProcMemRcvDqsResults,             ///< 28 .. Update results
+  TpProcMemRcvDqsFindWindow,          ///< 29 .. Start Find passing window
+  TpProcMemTransmitDqsTraining,       ///< 2A ..
+  TpProcMemTxDqStartSweep,            ///< 2B .. Start write sweep
+  TpProcMemTxDqSetDelay,              ///< 2C .. Set Transmit DQ delay
+  TpProcMemTxDqWritePattern,          ///< 2D .. Write test pattern
+  TpProcMemTxDqReadPattern,           ///< 2E .. Read Test pattern
+  TpProcMemTxDqTestPattern,           ///< 2F .. Compare Test pattern
+  TpProcMemTxDqResults,               ///< 30 .. Update results
+  TpProcMemTxDqFindWindow,            ///< 31 .. Start Find passing window
+  TpProcMemMaxRdLatencyTraining,      ///< 32 ..
+  TpProcMemMaxRdLatStartSweep,        ///< 33 .. Start sweep
+  TpProcMemMaxRdLatSetDelay,          ///< 34 .. Set delay
+  TpProcMemMaxRdLatWritePattern,      ///< 35 .. Write test pattern
+  TpProcMemMaxRdLatReadPattern,       ///< 36 .. Read Test pattern
+  TpProcMemMaxRdLatTestPattern,       ///< 37 .. Compare Test pattern
+  TpProcMemOnlineSpareInit,           ///< 38 .. Online Spare init
+  TpProcMemBankInterleaveInit,        ///< 39 .. Bank Interleave Init
+  TpProcMemNodeInterleaveInit,        ///< 3A .. Node Interleave Init
+  TpProcMemChannelInterleaveInit,     ///< 3B .. Channel Interleave Init
+  TpProcMemEccInitialization,         ///< 3C .. ECC initialization
+  TpProcMemPlatformSpecificInit,      ///< 3D .. Platform Specific Init
+  TpProcMemBeforeAgesaReadSpd,        ///< 3E .. Before callout for "AgesaReadSpd"
+  TpProcMemAfterAgesaReadSpd,         ///< 3F .. After callout for "AgesaReadSpd"
+  TpProcMemBeforeAgesaHookBeforeDramInit,     ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeDramInit,      ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemAfterAgesaHookBeforeDQSTraining,  ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemBeforeAgesaHookBeforeExitSelfRef,     ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeExitSelfRef,      ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterMemDataInit,          ///< 46 .. After MemDataInit
+  TpProcMemInitializeMCT,             ///< 47 .. Before InitializeMCT
+  TpProcMemLvDdr3,                    ///< 48 .. Before LV DDR3
+  TpProcMemInitMCT,                   ///< 49 .. Before InitMCT
+  TpProcMemOtherTiming,               ///< 4A.. Before OtherTiming
+  TpProcMemUMAMemTyping,              ///< 4B .. Before UMAMemTyping
+  TpProcMemSetDqsEccTmgs,             ///< 4C .. Before SetDqsEccTmgs
+  TpProcMemMemClr,                    ///< 4D .. Before MemClr
+  TpProcMemOnDimmThermal,             ///< 4E .. Before On DIMM Thermal
+  TpProcMemDmi,                       ///< 4F .. Before DMI
+  TpProcMemEnd,                       ///< 50 .. End of memory code
+
+  // CPU test points
+  TpProcCpuEntryDmi,                  ///< 51 .. Entry point CreateDmiRecords
+  TpProcCpuEntryPstate,               ///< 52 .. Entry point CreateAcpiTables
+  TpProcCpuEntryPstateLeveling,       ///< 53 .. Entry point PStateLeveling
+  TpProcCpuEntryPstateGather,         ///< 54 .. Entry point PStateGatherData
+  TpProcCpuEntryWhea,                 ///< 55 .. Entry point CreateAcpiWhea
+  TpProcCpuEntrySrat,                 ///< 56 .. Entry point CreateAcpiSrat
+  TpProcCpuEntrySlit,                 ///< 57 .. Entry point CreateAcpiSlit
+  TpProcCpuProcessRegisterTables,     ///< 58 .. Register table processing
+  TpProcCpuSetBrandID,                ///< 59 .. Set brand ID
+  TpProcCpuLocalApicInit,             ///< 5A .. Initialize local APIC
+  TpProcCpuLoadUcode,                 ///< 5B .. Load microcode patch
+  TpProcCpuPowerMgmtInit,             ///< 5C .. Power Management table processing
+  TpProcCpuEarlyFeatureInit,          ///< 5D .. Early feature dispatch point
+  TpProcCpuCoreLeveling,              ///< 5E .. Core Leveling
+  TpProcCpuApMtrrSync,                ///< 5F .. AP MTRR sync up
+  TpProcCpuPostFeatureInit,           ///< 60 .. POST feature dispatch point
+  TpProcCpuFeatureLeveling,           ///< 61 .. CPU Feature Leveling
+  TpProcCpuBeforeAllocateWheaBuffer,  ///< 62 .. Before the WHEA init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateWheaBuffer,   ///< 63 .. After the WHEA init code calls out to allocate a buffer
+  TpProcCpuBeforeAllocateSratBuffer,  ///< 64 .. Before the SRAT init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSratBuffer,   ///< 65 .. After the SRAT init code calls out to allocate a buffer
+  TpProcCpuBeforeLocateSsdtBuffer,    ///< 66 .. Before the P-state init code calls out to locate a buffer
+  TpProcCpuAfterLocateSsdtBuffer,     ///< 67 .. After the P-state init code calls out to locate a buffer
+  TpProcCpuBeforeAllocateSsdtBuffer,  ///< 68 .. Before the P-state init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSsdtBuffer,   ///< 69 .. After the P-state init code calls out to allocate a buffer
+
+  // HT test points
+  TpProcHtEntry = 0x71,               ///< 71 .. Coherent Discovery begin (Public interface)
+  TpProcHtTopology,                   ///< 72 .. Topology match, routing, begin
+  TpProcHtManualNc,                   ///< 73 .. Manual Non-coherent Init begin
+  TpProcHtAutoNc,                     ///< 74 .. Automatic Non-coherent init begin
+  TpProcHtOptGather,                  ///< 75 .. Optimization: Gather begin
+  TpProcHtOptRegang,                  ///< 76 .. Optimization: Regang begin
+  TpProcHtOptLinks,                   ///< 77 .. Optimization: Link Begin
+  TpProcHtOptSubLinks,                ///< 78 .. Optimization: Sublinks begin
+  TpProcHtOptFinish,                  ///< 79 .. Optimization: Set begin
+  TpProcHtTrafficDist,                ///< 7A .. Traffic Distribution begin
+  TpProcHtTuning,                     ///< 7B .. Misc Tuning Begin
+  TpProcHtDone,                       ///< 7C .. HT Init complete
+  TpProcHtApMapEntry,                 ///< 7D .. AP HT: Init Maps begin
+  TpProcHtApMapDone,                  ///< 7E .. AP HT: Complete
+
+  StartNbTestPoints = 0x90,           ///< 90 Entry used for range testing for @b NorthBridge related TPs
+  TpNbxxx,                            ///< 91 .
+  EndNbTestPoints,                    ///< 92 End of TP range for NB
+
+  StartSbTestPoints = 0xB0,           ///< B0 Entry used for range testing for @b SouthBridge related TPs
+  TpSbxxx,                            ///< B1 .
+  EndSbTestPoints,                    ///< B2 End of TP range for SB
+
+  // Interface test points
+  TpIfAmdInitResetEntry = 0xC0,       ///< C0 .. Entry to AmdInitReset
+  TpIfAmdInitResetExit,               ///< C1 .. Exiting from AmdInitReset
+  TpIfAmdInitRecoveryEntry,           ///< C2 .. Entry to AmdInitRecovery
+  TpIfAmdInitRecoveryExit,            ///< C3 .. Exiting from AmdInitRecovery
+  TpIfAmdInitEarlyEntry,              ///< C4 .. Entry to AmdInitEarly
+  TpIfAmdInitEarlyExit,               ///< C5 .. Exiting from AmdInitEarly
+  TpIfAmdInitPostEntry,               ///< C6 .. Entry to AmdInitPost
+  TpIfAmdInitPostExit,                ///< C7 .. Exiting from AmdInitPost
+  TpIfAmdInitEnvEntry,                ///< C8 .. Entry to AmdInitEnv
+  TpIfAmdInitEnvExit,                 ///< C9 .. Exiting from AmdInitEnv
+  TpIfAmdInitMidEntry,                ///< CA .. Entry to AmdInitMid
+  TpIfAmdInitMidExit,                 ///< CB .. Exiting from AmdInitMid
+  TpIfAmdInitLateEntry,               ///< CC .. Entry to AmdInitLate
+  TpIfAmdInitLateExit,                ///< CD .. Exiting from AmdInitLate
+  TpIfAmdS3SaveEntry,                 ///< CE .. Entry to AmdS3Save
+  TpIfAmdS3SaveExit,                  ///< CF .. Exiting from AmdS3Save
+  TpIfAmdInitResumeEntry,             ///< D0 .. Entry to AmdInitResume
+  TpIfAmdInitResumeExit,              ///< D1 .. Exiting from AmdInitResume
+  TpIfAmdS3LateRestoreEntry,          ///< D2 .. Entry to AmdS3LateRestore
+  TpIfAmdS3LateRestoreExit,           ///< D3 .. Exiting from AmdS3LateRestore
+  TpIfAmdLateRunApTaskEntry,          ///< D4 .. Entry to AmdS3LateRestore
+  TpIfAmdLateRunApTaskExit,           ///< D5 .. Exiting from AmdS3LateRestore
+  TpIfAmdReadEventLogEntry,           ///< D6 .. Entry to AmdReadEventLog
+  TpIfAmdReadEventLogExit,            ///< D7 .. Exiting from AmdReadEventLog
+  TpIfAmdGetApicIdEntry,              ///< D8 .. Entry to AmdGetApicId
+  TpIfAmdGetApicIdExit,               ///< D9 .. Exiting from AmdGetApicId
+  TpIfAmdGetPciAddressEntry,          ///< DA .. Entry to AmdGetPciAddress
+  TpIfAmdGetPciAddressExit,           ///< DB .. Exiting from AmdGetPciAddress
+  TpIfAmdIdentifyCoreEntry,           ///< DC .. Entry to AmdIdentifyCore
+  TpIfAmdIdentifyCoreExit,            ///< DD .. Exiting from AmdIdentifyCore
+  TpIfBeforeRunApFromIds,             ///< DE .. After IDS calls out to run code on an AP
+  TpIfAfterRunApFromIds,              ///< DF .. After IDS calls out to run code on an AP
+  TpIfBeforeGetIdsData,               ///< E0 .. Before IDS calls out to get IDS data
+  TpIfAfterGetIdsData,                ///< E1 .. After IDS calls out to get IDS data
+  TpIfBeforeAllocateHeapBuffer,       ///< E2 .. Before the heap manager calls out to allocate a buffer
+  TpIfAfterAllocateHeapBuffer,        ///< E3 .. After the heap manager calls out to allocate a buffer
+  TpIfBeforeDeallocateHeapBuffer,     ///< E4 .. Before the heap manager calls out to deallocate a buffer
+  TpIfAfterDeallocateHeapBuffer,      ///< E5 .. After the heap manager calls out to deallocate a buffer
+  TpIfBeforeLocateHeapBuffer,         ///< E6 .. Before the heap manager calls out to locate a buffer
+  TpIfAfterLocateHeapBuffer,          ///< E7 .. After the heap manager calls out to locate a buffer
+  TpIfBeforeRunApFromAllAps,          ///< E8 .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllAps,           ///< E9 .. After the BSP calls out to run code on an AP
+  TpIfBeforeRunApFromAllCore0s,       ///< EA .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllCore0s,        ///< EB .. After the BSP calls out to run code on an AP
+  TpIfBeforeAllocateS3SaveBuffer,     ///< EC .. Before the S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateS3SaveBuffer,      ///< ED .. After the S3 save code calls out to allocate a buffer
+  TpIfBeforeAllocateMemoryS3SaveBuffer,  ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateMemoryS3SaveBuffer,   ///< EF .. After the memory S3 save code calls out to allocate a buffer
+  TpIfBeforeLocateS3PciBuffer,        ///< F0 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3PciBuffer,         ///< F1 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CPciBuffer,       ///< F2 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CPciBuffer,        ///< F3 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3MsrBuffer,        ///< F4 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3MsrBuffer,         ///< F5 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CMsrBuffer,       ///< F6 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CMsrBuffer,        ///< F7 .. After the memory code calls out to locate a buffer
+  TpPerfUnit,                              ///< F8 .. The Unit of performance measure.
+  EndAgesaTps = 0xFF,                 ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+  IDS_FEAT_UCODE_UPDATE = 0x0000,   ///< Feat for Ucode Update
+  IDS_FEAT_TARGET_PSTATE,           ///< Feat for Target Pstate
+  IDS_FEAT_POSTPSTATE,              ///< Feat for Post Pstate
+  IDS_FEAT_ECC_CTRL,                ///< Feat for Ecc Control
+  IDS_FEAT_ECC_SYMBOL_SIZE,         ///< Feat for Ecc symbol size
+  IDS_FEAT_DCT_ALLMEMCLK,           ///< Feat for all memory clock
+  IDS_FEAT_DCT_GANGMODE,            ///< Feat for Dct gang mode
+  IDS_FEAT_DCT_BURSTLENGTH,         ///< Feat for dct burst length
+  IDS_FEAT_DCT_POWERDOWN,           ///< Feat for dct power down
+  IDS_FEAT_DCT_DLLSHUTDOWN,         ///< Feat for dct dll shut down
+  IDS_FEAT_PROBE_FILTER,            ///< Feat for probe filter
+  IDS_FEAT_HDTOUT,                  ///< Feat for hdt out
+  IDS_FEAT_HT_SETTING,              ///< Feat for Ht setting
+  IDS_FEAT_GNB_PLATFORMCFG,                 ///< Feat for override GNB platform config
+  IDS_FEAT_END                      ///< End of Common feat
+} IDS_FEAT;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef  struct _IDS_FEAT_STRUCT {
+  IDS_FEAT  IdsFeat;      ///< Ids Feat ID
+  BOOLEAN IsBsp;          ///< swith for Bsp check
+  AGESA_IDS_OPTION IdsOption;   ///< IDS option
+  UINT64 CpuFamily;      ///<
+  PIDS_COMMON_FUNC  pf_idsoption;     ///<pointer to function
+} IDS_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef  struct _IDS_OPTION_STRUCT {
+  AGESA_IDS_OPTION idsoption;   ///< IDS option
+  PIDS_COMMON_FUNC  pf_idsoption;     ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+  UINT8 version;      ///<Version of IDS option table
+  UINT16 size;        ///<Size of IDS option table
+  CONST IDS_OPTION_STRUCT  *pIdsOptionStruct; ///<pointer to array of  structure
+} IDS_OPTION_STRUCT_TBL;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsConsoleInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsConsolePrint (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsConsoleExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsMemTimeOut (
+  IN OUT   VOID *DataPtr
+  );
+
+VOID
+IdsAgesaTestPoint (
+  IN      AGESA_TP TestPoint,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+  IN      UINT32 FileCode
+  );
+
+VOID
+IdsDelay (
+  IN	VOID
+);
+
+BOOLEAN
+AmdHeapIntactCheck (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsCarCorruptionCheck (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/IdsHt.h b/src/vendorcode/amd/agesa/f10/Include/IdsHt.h
new file mode 100755
index 0000000000..6096684dc4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/IdsHt.h
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Definitions
+ *
+ * Contains AMD AGESA Integrated Debug HT related items.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_HT_H_
+#define _IDS_HT_H_
+
+// Frequency equates for call backs which take an actual frequency setting
+#define HT_FREQUENCY_200M            0
+#define HT_FREQUENCY_400M            2
+#define HT_FREQUENCY_600M            4
+#define HT_FREQUENCY_800M            5
+#define HT_FREQUENCY_1000M           6
+#define HT_FREQUENCY_1200M           7
+#define HT_FREQUENCY_1400M           8
+#define HT_FREQUENCY_1600M           9
+#define HT_FREQUENCY_1800M           10
+#define HT_FREQUENCY_2000M           11
+#define HT_FREQUENCY_2200M           12
+#define HT_FREQUENCY_2400M           13
+#define HT_FREQUENCY_2600M           14
+#define HT_FREQUENCY_2800M           17
+#define HT_FREQUENCY_3000M           18
+#define HT_FREQUENCY_3200M           19
+#define HT_FREQUENCY_3600M           20
+
+/**
+ * HT IDS: HT Link Port Override params.
+ *
+ * Provide an absolute override of HT Link Port settings.  No checking is done that
+ * the settings obey limits or capabilities, this responsibility rests with the user.
+ *
+ * Rules for values of structure items:
+ * - Socket
+ *   - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
+ *   - HT_LIST_MATCH_ANY == Match Any Socket
+ *   - 0 .. 7 == The matching socket
+ * - Link
+ *   - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
+ *   - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
+ *   - 0 .. 7 == The matching package link.  0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
+ * - Frequency
+ *   - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
+ *   - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
+ * - Widthin
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ * - Widthout
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ */
+typedef struct {
+  // Match Fields
+  UINT8       Socket;      ///< The Socket which this port is on.
+  UINT8       Link;        ///< The port for this package link on that socket.
+  // Override fields
+  UINT8       Frequency;   ///< Absolutely override the port's frequency.
+  UINT8       WidthIn;     ///< Absolutely override the port's width.
+  UINT8       WidthOut;    ///< Absolutely override the port's width.
+} HTIDS_PORT_OVERRIDE;
+
+/**
+ * A list of port overrides to search.
+ */
+typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+
+typedef
+VOID
+F_HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
+#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/f10/Include/LynxInstall.h b/src/vendorcode/amd/agesa/f10/Include/LynxInstall.h
new file mode 100755
index 0000000000..859ff88f87
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/LynxInstall.h
@@ -0,0 +1,1535 @@
+/**
+ * @file
+ *
+ * Install of build options for a Lynx platform solution
+ *
+ * This file generates the defaults tables for the "Lynx" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DanNiPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'L', 'y', 'n', 'x', 'P', 'I', ' ', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '1', '.', '0', 'X', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  '0000',
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY12H                          TRUE
+#define OPTION_FAMILY12H_LN                       TRUE
+#define OPTION_MEMCTLR_LN                         TRUE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     TRUE
+#define OPTION_HW_DQS_REC_EN_TRAINING           TRUE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        TRUE
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     TRUE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              FALSE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   FALSE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      FALSE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          FALSE
+#define OPTION_PARALLEL_TRAINING        FALSE
+#define OPTION_ONLINE_SPARE             FALSE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     FALSE
+#define OPTION_SLIT                     FALSE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     FALSE
+#define OPTION_DDR3                     TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                FALSE
+#define OPTION_CPU_CORELEVLING          FALSE
+#define OPTION_MSG_BASED_C1E            FALSE
+#define OPTION_C6_STATE                 TRUE
+#define OPTION_CPU_CFOH                 FALSE
+#define OPTION_S3SCRIPT                 TRUE
+#define OPTION_GFX_RECOVERY             TRUE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_C6_STATE
+  #if  BLDOPT_REMOVE_C6_STATE == TRUE
+    #undef  OPTION_C6_STATE
+    #define OPTION_C6_STATE      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_GFX_RECOVERY
+  #if  BLDOPT_REMOVE_GFX_RECOVERY == TRUE
+    #undef  OPTION_GFX_RECOVERY
+    #define OPTION_GFX_RECOVERY         FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                5000
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G             BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G             FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   FALSE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE   FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily12h.h"
+#include  "OptionFamily12hLnInstall.h"
+#include  "OptionFamily12hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#include  "OptionGfxRecovery.h"
+#include  "OptionGfxRecoveryInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionLynxMicrocodeInstall.h"
+#endif
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,   // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F12_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+
+  // Probe filter enable
+
+  { 0, NULL }
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] =
+{
+  NULL
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] =
+{
+  NULL
+};
+
+CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0]));
+CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0]));
diff --git a/src/vendorcode/amd/agesa/f10/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f10/Include/MaranelloInstall.h
new file mode 100755
index 0000000000..570fda24cf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/MaranelloInstall.h
@@ -0,0 +1,1541 @@
+/**
+ * @file
+ *
+ * Install of build options for a Maranello platform solution
+ *
+ * This file generates the defaults tables for the "Maranello" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 55154 $   @e \$Date: 2011-06-16 16:53:35 -0600 (Thu, 16 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _MARANELLOINSTALL_H_
+#define _MARANELLOINSTALL_H_
+
+#include  "AGESA.h"
+#include  "cpuRegisters.h"
+#include  "cpuFamRegisters.h"
+#include  "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "MarG34PI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'M', 'a', 'r', 'G', '3', '4', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '8', ' ', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  Int32FromChar ('0', '0', '0', '0'),
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY10H                          TRUE
+#define OPTION_FAMILY10H_BL                       FALSE
+#define OPTION_FAMILY10H_DA                       FALSE
+#define OPTION_FAMILY10H_HY                       TRUE
+#define OPTION_FAMILY10H_RB                       FALSE
+
+#define OPTION_MEMCTLR_DA                         FALSE
+#define OPTION_MEMCTLR_LN                         FALSE
+#define OPTION_MEMCTLR_ON                         FALSE
+#define OPTION_MEMCTLR_Or                         FALSE
+#define OPTION_MEMCTLR_DR                         FALSE
+#define OPTION_MEMCTLR_HY                         TRUE
+#define OPTION_MEMCTLR_OR                         FALSE
+#define OPTION_MEMCTLR_C32                        FALSE
+
+#define OPTION_EMP                                FALSE
+#define OPTION_C6_STATE                           FALSE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   TRUE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        TRUE
+
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     TRUE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              TRUE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   TRUE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      TRUE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          TRUE
+#define OPTION_PARALLEL_TRAINING        TRUE
+#define OPTION_ONLINE_SPARE             TRUE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     TRUE
+#define OPTION_SLIT                     TRUE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     FALSE
+#define OPTION_DDR3                     TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                TRUE
+#define OPTION_CPU_CORELEVLING          TRUE
+#define OPTION_MSG_BASED_C1E            TRUE
+#define OPTION_CPU_CFOH                 TRUE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                2500
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0xFF
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0x10
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0x10
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0x12
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G           FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   FALSE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE   FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily10h.h"
+#include  "OptionFamily10hBlInstall.h"
+#include  "OptionFamily10hDaInstall.h"
+#include  "OptionFamily10hHyInstall.h"
+#include  "OptionFamily10hRbInstall.h"
+#include  "OptionFamily10hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionMaranelloMicrocodeInstall.h"
+#endif
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,         // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, 0}
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+  CPU_DMI_AP_GET_TYPE4_TYPE7
+  // Probe filter enable
+  HT_ASSIST_AP_DISABLE_CACHE
+  HT_ASSIST_AP_ENABLE_CACHE
+
+  { 0, NULL }
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+{
+  &F10BrandIdString1ArrayG34
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+{
+  &F10BrandIdString2ArrayG34
+};
+
+CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/NileInstall.h b/src/vendorcode/amd/agesa/f10/Include/NileInstall.h
new file mode 100755
index 0000000000..c2511a1ab2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/NileInstall.h
@@ -0,0 +1,1527 @@
+/**
+ * @file
+ *
+ * Install of build options for a Nile platform solution
+ *
+ * This file generates the defaults tables for the "Nile" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#include  "cpuRegisters.h"
+#include  "cpuFamRegisters.h"
+#include  "cpuFamilyTranslation.h"
+#include  "AdvancedApi.h"
+#include  "heapManager.h"
+#include  "CreateStruct.h"
+#include  "cpuFeatures.h"
+#include  "Table.h"
+#include  "CommonReturns.h"
+#include  "cpuEarlyInit.h"
+#include  "cpuLateInit.h"
+#include  "GnbInterfaceStub.h"
+
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "DanNiPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher(VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  '0000',
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY10H                          TRUE
+#define OPTION_FAMILY10H_DA                       TRUE
+#define OPTION_FAMILY10H_BL                       TRUE
+#define OPTION_MEMCTLR_DA                         TRUE
+#define OPTION_MEMCTLR_Ni                         TRUE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       TRUE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        TRUE
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     TRUE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              FALSE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   FALSE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      TRUE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          FALSE
+#define OPTION_PARALLEL_TRAINING        FALSE
+#define OPTION_ONLINE_SPARE             FALSE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     FALSE
+#define OPTION_SLIT                     FALSE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     FALSE
+#define OPTION_DDR3                     TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                FALSE
+#define OPTION_CPU_CORELEVLING          TRUE
+#define OPTION_MSG_BASED_C1E            FALSE
+#define OPTION_CPU_CFOH                 TRUE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                5000
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G             BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G             FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   FALSE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE   FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily10h.h"
+#include  "OptionFamily10hBlInstall.h"
+#include  "OptionFamily10hDaInstall.h"
+#include  "OptionFamily10hHyInstall.h"
+#include  "OptionFamily10hRbInstall.h"
+#include  "OptionFamily10hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionNileMicrocodeInstall.h"
+#endif
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,   // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+
+  // Probe filter enable
+
+  { 0, NULL }
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+{
+  &F10BrandIdString1ArrayAsb2
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+{
+  &F10BrandIdString2ArrayAsb2
+};
+
+CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f10/Include/OptionC6Install.h
new file mode 100755
index 0000000000..ee9e14e636
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionC6Install.h
@@ -0,0 +1,84 @@
+/**
+ * @file
+ *
+ * Install of build option: C6 C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_C6_STATE_INSTALL_H_
+#define _OPTION_C6_STATE_INSTALL_H_
+
+#include "cpuC6State.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_C6_STATE_FEAT
+#define F12_C6_STATE_SUPPORT
+#if OPTION_C6_STATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
+          #undef F12_C6_STATE_SUPPORT
+          #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
+{
+  F12_C6_STATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
+{
+  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &C6FamilyServiceArray[0]
+};
+
+#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h
new file mode 100755
index 0000000000..966624c65f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * Install of build option: CPU Cache Flush On Halt
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 17487 $   @e \$Date: 2009-08-06 14:17:58 -0500 (Thu, 06 Aug 2009) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+
+#include "cpuPostInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+#define F10_BL_CPU_CFOH_SUPPORT
+#define F10_DA_CPU_CFOH_SUPPORT
+#define F10_CPU_CFOH_SUPPORT
+
+#if OPTION_CPU_CFOH == TRUE
+  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY10H_BL == TRUE
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
+          #undef F10_BL_CPU_CFOH_SUPPORT
+          #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
+        #endif
+
+        #if OPTION_FAMILY10H_DA == TRUE
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
+          #undef F10_DA_CPU_CFOH_SUPPORT
+          #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
+        #endif
+
+        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE)
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
+          #undef F10_CPU_CFOH_SUPPORT
+          #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY, &F10CacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
+{
+  F10_BL_CPU_CFOH_SUPPORT
+  F10_DA_CPU_CFOH_SUPPORT
+  F10_CPU_CFOH_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
+{
+  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CacheFlushOnHaltFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionCpuCoreLevelingInstall.h
new file mode 100755
index 0000000000..a826a2dddb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionCpuCoreLevelingInstall.h
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Install of build option: CPU Core Leveling
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 17487 $   @e \$Date: 2009-08-06 14:17:58 -0500 (Thu, 06 Aug 2009) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
+#define _OPTION_CPU_CORELEVELING_INSTALL_H_
+
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CORE_LEVELING_FEAT
+#define F10_REVD_CPU_CORELEVELING_SUPPORT
+#define F10_REVC_CPU_CORELEVELING_SUPPORT
+
+#if OPTION_CPU_CORELEVLING == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+        #undef OPTION_CPU_CORE_LEVELING_FEAT
+        #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+
+        #if OPTION_FAMILY10H_HY == TRUE
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
+          #undef F10_REVD_CPU_CORELEVELING_SUPPORT
+          #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
+        #endif
+
+        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
+          extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
+          #undef F10_REVC_CPU_CORELEVELING_SUPPORT
+          #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
+{
+  F10_REVD_CPU_CORELEVELING_SUPPORT
+  F10_REVC_CPU_CORELEVELING_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
+{
+  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CoreLevelingFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionCpuFeaturesInstall.h
new file mode 100755
index 0000000000..b048cc55ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionCpuFeaturesInstall.h
@@ -0,0 +1,67 @@
+/**
+ * @file
+ *
+ * Install of multiple CPU features.
+ *
+ * Aggregates enabled CPU features into a list for the dispatcher to process.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
+#define _OPTION_CPU_FEATURES_INSTALL_H_
+
+#include "OptionHwC1eInstall.h"
+#include "OptionMsgBasedC1eInstall.h"
+#include "OptionHtAssistInstall.h"
+#include "OptionCpuCoreLevelingInstall.h"
+#include "OptionC6Install.h"
+#include "OptionCpuCacheFlushOnHaltInstall.h"
+#include "OptionPreserveMailboxInstall.h"
+
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+{
+  OPTION_HW_C1E_FEAT
+  OPTION_MSG_BASED_C1E_FEAT
+  OPTION_HT_ASSIST_FEAT
+  OPTION_CPU_CORE_LEVELING_FEAT
+  OPTION_C6_STATE_FEAT
+  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+  OPTION_PRESERVE_MAILBOX_FEAT
+  NULL
+};
+
+
+#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDanubeMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDanubeMicrocodeInstall.h
new file mode 100755
index 0000000000..195e9ff55f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionDanubeMicrocodeInstall.h
@@ -0,0 +1,63 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a Danube platform solution
+ *
+ * This file generates the defaults tables for the "Danube" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_DANUBE_MICROCODE_INSTALL_H_
+#define _OPTION_DANUBE_MICROCODE_INSTALL_H_
+
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6;
+
+// 'NULL' must be put at the end of MicroCodePatchArray[]
+CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f10/Include/OptionDmi.h
new file mode 100755
index 0000000000..007254dff4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionDmi.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * AMD DMI option API.
+ *
+ * Contains structures and values used to control the DMI option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_DMI_H_
+#define _OPTION_DMI_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_DMI_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   DMI_INFO             **DmiPtr
+  );
+
+typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define DMI_STRUCT_VERSION  0x01
+
+/// DMI option configuration. Determine the item of structure when compiling.
+typedef struct  {
+  UINT16              OptDmiVersion;      ///< Dmi version.
+  OPTION_DMI_FEATURE  *DmiFeature;        ///< Feature main routine, otherwise dummy.
+  OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
+  UINT16              NumEntries;         ///< Number of entry.
+  VOID                *((*FamilyList)[]); ///< Family service.
+} OPTION_DMI_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h
new file mode 100755
index 0000000000..796da3ea9f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h
@@ -0,0 +1,140 @@
+/**
+ * @file
+ *
+ * Install of build option: DMI
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_DMI_INSTALL_H_
+#define _OPTION_DMI_INSTALL_H_
+
+#include "cpuLateInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_DMI
+    #error  BLDOPT: Option not defined: "OPTION_DMI"
+  #endif
+  #if OPTION_DMI == TRUE
+    OPTION_DMI_FEATURE          GetDmiInfoMain;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
+    #define USER_DMI_OPTION     &GetDmiInfoMain
+    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
+
+    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+    #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
+
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
+        #define FAM10_DMI_SUPPORT FAM10_ENABLED,
+        #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
+      #else
+        #define FAM10_DMI_SUPPORT
+        #define FAM10_DMI_TABLE
+      #endif
+    #else
+      #define FAM10_DMI_SUPPORT
+      #define FAM10_DMI_TABLE
+    #endif
+
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
+        #define FAM12_DMI_SUPPORT FAM12_ENABLED,
+        #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
+      #else
+        #define FAM12_DMI_SUPPORT
+        #define FAM12_DMI_TABLE
+      #endif
+    #else
+      #define FAM12_DMI_SUPPORT
+      #define FAM12_DMI_TABLE
+    #endif
+  #else
+    OPTION_DMI_FEATURE          GetDmiInfoStub;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
+    #define USER_DMI_OPTION     GetDmiInfoStub
+    #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+    #define FAM10_DMI_SUPPORT
+    #define FAM10_DMI_TABLE
+    #define FAM12_DMI_SUPPORT
+    #define FAM12_DMI_TABLE
+    #define CPU_DMI_AP_GET_TYPE4_TYPE7
+  #endif
+#else
+  OPTION_DMI_FEATURE          GetDmiInfoStub;
+  OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
+  #define USER_DMI_OPTION     GetDmiInfoStub
+  #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+  #define FAM10_DMI_SUPPORT
+  #define FAM10_DMI_TABLE
+  #define FAM12_DMI_SUPPORT
+  #define FAM12_DMI_TABLE
+  #define CPU_DMI_AP_GET_TYPE4_TYPE7
+#endif
+
+/// DMI supported families enum
+typedef enum {
+  FAM10_DMI_SUPPORT                   ///< Conditionally define F10 support
+  FAM12_DMI_SUPPORT                   ///< Conditionally define F12 support
+  NUM_DMI_FAMILIES                    ///< Number of installed families
+} AGESA_DMI_SUPPORTED_FAM;
+
+/*  Declare the Family List. An array of pointers to tables that each describe a family  */
+CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
+  FAM10_DMI_TABLE
+  FAM12_DMI_TABLE
+  NULL
+};
+
+/*  Declare the instance of the DMI option configuration structure  */
+CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
+  DMI_STRUCT_VERSION,
+  USER_DMI_OPTION,
+  USER_DMI_RELEASE_BUFFER,
+  NUM_DMI_FAMILIES,
+  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
+};
+
+#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDragonMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDragonMicrocodeInstall.h
new file mode 100755
index 0000000000..3755f497ad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionDragonMicrocodeInstall.h
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a Dragon platform solution
+ *
+ * This file generates the defaults tables for the "Dragon" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_DRAGON_MICROCODE_INSTALL_H_
+#define _OPTION_DRAGON_MICROCODE_INSTALL_H_
+
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000086;
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6;
+
+// 'NULL' must be put at the end of MicroCodePatchArray[]
+CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch01000086,
+  &CpuF10MicrocodePatch01000085,
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10h.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10h.h
new file mode 100755
index 0000000000..d9d723dc40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10h.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ *
+ * Structures and definitions for family 10h support
+ *
+ * This file defines the structures and definitions needed for installation
+ * of family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+
+#ifndef _OPTION_FAMILY_10H_H_
+#define _OPTION_FAMILY_10H_H_
+
+#ifdef OPTION_FAMILY10H
+  #if OPTION_FAMILY10H == TRUE
+
+    extern F_CPU_GET_PSTATE_POWER F10GetPstatePower;
+    extern F_CPU_GET_PSTATE_FREQ F10GetPstateFrequency;
+    extern F_CPU_DISABLE_PSTATE F10DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F10GetTscRate;
+    extern F_CPU_PSTATE_TRANSITION_LATENCY F10GetPstateTransLatency;
+    extern F_CPU_GET_PSTATE_REGISTER_INFO F10GetPstateRegisterInfo;
+    extern F_CPU_GET_PSTATE_MAX_STATE F10GetPstateMaxState;
+    extern F_CPU_SET_PSTATE_LEVELING_REG F10PstateLevelingCoreMsrModify;
+    extern F_CPU_GET_NB_FREQ F10GetNbFrequency;
+    extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
+    extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
+    extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
+    extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SAVE_FEATURES F10SaveFeatures;
+    extern F_CPU_WRITE_FEATURES F10WriteFeatures;
+    extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
+    //extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+    extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
+    extern F_DOES_LINK_HAVE_HTFPY_FEATS F10DoesLinkHaveHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
+    extern F_GET_HT_LINK_FEATURES F10GetHtLinkFeatures;
+    extern F_DO_TABLE_ENTRY F10SetRegisterForHtLinkTokenEntry;
+    extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
+    extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
+  #endif  // OPTION_FAMILY10H == TRUE
+#endif  //  defined (OPTION_FAMILY10H)
+
+#endif  // _OPTION_FAMILY_10H_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hBlInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hBlInstall.h
new file mode 100755
index 0000000000..f78e188124
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hBlInstall.h
@@ -0,0 +1,354 @@
+/**
+ * @file
+ *
+ * Install of family 10h model 5 support
+ *
+ * This file generates the defaults tables for family 10h model 5 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifdef OPTION_FAMILY10H
+  #if OPTION_FAMILY10H == TRUE
+    #ifdef OPTION_FAMILY10H_BL
+      #if OPTION_FAMILY10H_BL == TRUE
+        extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
+        extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+        extern F_CPU_GET_NB_FREQ F10CommonRevCGetNbFrequency;
+        extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+        extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+        extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
+          {
+            #if BASE_FAMILY_PCI == TRUE
+              &F10PciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10SingleLinkPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10RevCPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10BlPciRegisterTable,
+            #endif
+            #if BASE_FAMILY_MSR == TRUE
+              &F10MsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10RevCMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10BlMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10HtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10RevCHtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10BlHtPhyRegisterTable,
+            #endif
+            // the end.
+            NULL
+          };
+        #endif
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
+          {
+            {MSRREGISTER, SetRegisterForMsrEntry},
+            {PCIREGISTER, SetRegisterForPciEntry},
+            {ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
+            {HtPhyRegister, SetRegisterForHtPhyEntry},
+            {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+            {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+            {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+            {HtHostPciRegister, SetRegisterForHtHostEntry},
+            {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+            {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+            {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+            {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+            {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+            // End
+            {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+          };
+        #endif
+
+        CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
+        {
+          0,
+          #if GET_PSTATE_POWER == TRUE
+            F10GetPstatePower,
+          #else
+            (PF_CPU_GET_PSTATE_POWER) CommonAssert,
+          #endif
+          #if GET_PSTATE_FREQ == TRUE
+            F10GetPstateFrequency,
+          #else
+            (PF_CPU_GET_PSTATE_FREQ) CommonAssert,
+          #endif
+          #if DISABLE_PSTATE == TRUE
+            F10DisablePstate,
+          #else
+            (PF_CPU_DISABLE_PSTATE) CommonAssert,
+          #endif
+          #if TRANSITION_PSTATE == TRUE
+            F10TransitionPstate,
+          #else
+            (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+          #endif
+          #if PROC_IDD_MAX == TRUE
+            F10CommonRevCGetProcIddMax,
+          #else
+            (PF_CPU_GET_IDD_MAX) CommonAssert,
+          #endif
+          #if GET_TSC_RATE == TRUE
+            F10GetTscRate,
+          #else
+            (PF_CPU_GET_TSC_RATE) CommonAssert,
+          #endif
+          #if PSTATE_TRANSITION_LATENCY == TRUE
+            F10GetPstateTransLatency,
+          #else
+            (PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
+          #endif
+          #if GET_PSTATE_REGISTER_INFO == TRUE
+            F10GetPstateRegisterInfo,
+          #else
+            (PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
+          #endif
+          #if GET_PSTATE_MAX_STATE == TRUE
+            F10GetPstateMaxState,
+          #else
+            (PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
+          #endif
+          #if SET_PSTATE_LEVELING_REG == TRUE
+            F10PstateLevelingCoreMsrModify,
+          #else
+            (PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
+          #endif
+          #if GET_NB_FREQ == TRUE
+            F10CommonRevCGetNbFrequency,
+          #else
+            (PF_CPU_GET_NB_FREQ) CommonAssert,
+          #endif
+          #if IS_NBCOF_INIT_NEEDED == TRUE
+            F10CommonRevCGetNbCofVidUpdate,
+          #else
+            (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+          #endif
+          #if AP_INITIAL_LAUNCH == TRUE
+            F10LaunchApCore,
+          #else
+            (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+          #endif
+          #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+            F10CommonRevCGetNumberOfCoresForBrandstring,
+          #else
+            (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+          #endif
+          #if GET_AP_MAILBOX_FROM_HW == TRUE
+            F10GetApMailboxFromHardware,
+          #else
+            (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+          #endif
+          #if SET_AP_CORE_NUMBER == TRUE
+            F10SetApCoreNumber,
+          #else
+            (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if GET_AP_CORE_NUMBER == TRUE
+            F10GetApCoreNumber,
+          #else
+            (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if TRANSFER_AP_CORE_NUMBER == TRUE
+            F10TransferApCoreNumber,
+          #else
+            (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if ID_POSITION_INITIAL_APICID == TRUE
+            F10CpuAmdCoreIdPositionInInitialApicId,
+          #else
+            (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+          #endif
+          #if SAVE_FEATURES == TRUE
+            F10SaveFeatures,
+          #else
+            (PF_CPU_SAVE_FEATURES) CommonAssert,
+          #endif
+          #if WRITE_FEATURES == TRUE
+            F10WriteFeatures,
+          #else
+            (PF_CPU_WRITE_FEATURES) CommonAssert,
+          #endif
+          #if SET_WARM_RESET_FLAG == TRUE
+            F10SetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if GET_WARM_RESET_FLAG == TRUE
+            F10GetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if BRAND_STRING1 == TRUE
+            GetF10BrandIdString1,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if BRAND_STRING2 == TRUE
+            GetF10BrandIdString2,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES == TRUE
+            GetF10BlMicroCodePatchesStruct,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+            GetF10BlMicrocodeEquivalenceTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_CACHE_INFO == TRUE
+            GetF10CacheInfo,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_SYSTEM_PM_TABLE == TRUE
+            GetF10SysPmTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_WHEA_INIT == TRUE
+            GetF10WheaInitData,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+            F10GetPlatformTypeSpecificInfo,
+          #else
+            (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+          #endif
+          #if IS_NB_PSTATE_ENABLED == TRUE
+            F10CommonRevCIsNbPstateEnabled,
+          #else
+            (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10DoesLinkHaveHtPhyFeats,
+          #else
+            (PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10SetHtPhyRegister,
+          #else
+            (PF_SET_HT_PHY_REGISTER) CommonAssert,
+          #endif
+          #if BASE_FAMILY_PCI == TRUE
+            F10GetHtLinkFeatures,
+          #else
+            (PF_GET_HT_LINK_FEATURES) CommonAssert,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (REGISTER_TABLE **) F10BlRegisterTables,
+          #else
+            NULL,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
+          #else
+            NULL,
+          #endif
+          NULL,
+          #if AGESA_ENTRY_INIT_EARLY == TRUE
+            GetCommonEarlyInitOnCoreTable
+          #else
+            (PF_GET_EARLY_INIT_TABLE) CommonVoid
+          #endif
+        };
+
+        #define BL_SOCKETS 1
+        #define BL_MODULES 1
+        #define BL_RECOVERY_SOCKETS 1
+        #define BL_RECOVERY_MODULES 1
+        extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
+        #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
+        #ifndef ADVCFG_PLATFORM_SOCKETS
+          #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+        #else
+          #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
+            #undef ADVCFG_PLATFORM_SOCKETS
+            #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+          #endif
+        #endif
+        #ifndef ADVCFG_PLATFORM_MODULES
+          #define ADVCFG_PLATFORM_MODULES BL_MODULES
+        #else
+          #if ADVCFG_PLATFORM_MODULES < BL_MODULES
+            #undef ADVCFG_PLATFORM_MODULES
+            #define ADVCFG_PLATFORM_MODULES BL_MODULES
+          #endif
+        #endif
+        #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
+      #else
+        #define OPT_F10_BL_CPU
+        #define OPT_F10_BL_ID
+      #endif
+    #else
+      #define OPT_F10_BL_CPU
+      #define OPT_F10_BL_ID
+    #endif
+  #else
+    #define OPT_F10_BL_CPU
+    #define OPT_F10_BL_ID
+  #endif
+#else
+  #define OPT_F10_BL_CPU
+  #define OPT_F10_BL_ID
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hDaInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hDaInstall.h
new file mode 100755
index 0000000000..b92735cabd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hDaInstall.h
@@ -0,0 +1,354 @@
+/**
+ * @file
+ *
+ * Install of family 10h model 6 support
+ *
+ * This file generates the defaults tables for family 10h model 6 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifdef OPTION_FAMILY10H
+  #if OPTION_FAMILY10H == TRUE
+    #ifdef OPTION_FAMILY10H_DA
+      #if OPTION_FAMILY10H_DA == TRUE
+        extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
+        extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+        extern F_CPU_GET_NB_FREQ F10CommonRevCGetNbFrequency;
+        extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+        extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+        extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
+          {
+            #if BASE_FAMILY_PCI == TRUE
+              &F10PciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10SingleLinkPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10RevCPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10DaPciRegisterTable,
+            #endif
+            #if BASE_FAMILY_MSR == TRUE
+              &F10MsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10RevCMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10DaMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10HtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10RevCHtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10DaHtPhyRegisterTable,
+            #endif
+            // the end.
+            NULL
+          };
+        #endif
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
+          {
+            {MsrRegister, SetRegisterForMsrEntry},
+            {PciRegister, SetRegisterForPciEntry},
+            {ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
+            {HtPhyRegister, SetRegisterForHtPhyEntry},
+            {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+            {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+            {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+            {HtHostPciRegister, SetRegisterForHtHostEntry},
+            {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+            {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+            {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+            {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+            {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+            // End
+            {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+          };
+        #endif
+
+        CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
+        {
+          0,
+          #if GET_PSTATE_POWER == TRUE
+            F10GetPstatePower,
+          #else
+            (PF_CPU_GET_PSTATE_POWER) CommonAssert,
+          #endif
+          #if GET_PSTATE_FREQ == TRUE
+            F10GetPstateFrequency,
+          #else
+            (PF_CPU_GET_PSTATE_FREQ) CommonAssert,
+          #endif
+          #if DISABLE_PSTATE == TRUE
+            F10DisablePstate,
+          #else
+            (PF_CPU_DISABLE_PSTATE) CommonAssert,
+          #endif
+          #if TRANSITION_PSTATE == TRUE
+            F10TransitionPstate,
+          #else
+            (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+          #endif
+          #if PROC_IDD_MAX == TRUE
+            F10CommonRevCGetProcIddMax,
+          #else
+            (PF_CPU_GET_IDD_MAX) CommonAssert,
+          #endif
+          #if GET_TSC_RATE == TRUE
+            F10GetTscRate,
+          #else
+            (PF_CPU_GET_TSC_RATE) CommonAssert,
+          #endif
+          #if PSTATE_TRANSITION_LATENCY == TRUE
+            F10GetPstateTransLatency,
+          #else
+            (PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
+          #endif
+          #if GET_PSTATE_REGISTER_INFO == TRUE
+            F10GetPstateRegisterInfo,
+          #else
+            (PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
+          #endif
+          #if GET_PSTATE_MAX_STATE == TRUE
+            F10GetPstateMaxState,
+          #else
+            (PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
+          #endif
+          #if SET_PSTATE_LEVELING_REG == TRUE
+            F10PstateLevelingCoreMsrModify,
+          #else
+            (PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
+          #endif
+          #if GET_NB_FREQ == TRUE
+            F10CommonRevCGetNbFrequency,
+          #else
+            (PF_CPU_GET_NB_FREQ) CommonAssert,
+          #endif
+          #if IS_NBCOF_INIT_NEEDED == TRUE
+            F10CommonRevCGetNbCofVidUpdate,
+          #else
+            (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+          #endif
+          #if AP_INITIAL_LAUNCH == TRUE
+            F10LaunchApCore,
+          #else
+            (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+          #endif
+          #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+            F10CommonRevCGetNumberOfCoresForBrandstring,
+          #else
+            (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+          #endif
+          #if GET_AP_MAILBOX_FROM_HW == TRUE
+            F10GetApMailboxFromHardware,
+          #else
+            (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+          #endif
+          #if SET_AP_CORE_NUMBER == TRUE
+            F10SetApCoreNumber,
+          #else
+            (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if GET_AP_CORE_NUMBER == TRUE
+            F10GetApCoreNumber,
+          #else
+            (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if TRANSFER_AP_CORE_NUMBER == TRUE
+            F10TransferApCoreNumber,
+          #else
+            (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if ID_POSITION_INITIAL_APICID == TRUE
+            F10CpuAmdCoreIdPositionInInitialApicId,
+          #else
+            (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+          #endif
+          #if SAVE_FEATURES == TRUE
+            F10SaveFeatures,
+          #else
+            (PF_CPU_SAVE_FEATURES) CommonAssert,
+          #endif
+          #if WRITE_FEATURES == TRUE
+            F10WriteFeatures,
+          #else
+            (PF_CPU_WRITE_FEATURES) CommonAssert,
+          #endif
+          #if SET_WARM_RESET_FLAG == TRUE
+            F10SetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if GET_WARM_RESET_FLAG == TRUE
+            F10GetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if BRAND_STRING1 == TRUE
+            GetF10BrandIdString1,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if BRAND_STRING2 == TRUE
+            GetF10BrandIdString2,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES == TRUE
+            GetF10DaMicroCodePatchesStruct,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+            GetF10DaMicrocodeEquivalenceTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_CACHE_INFO == TRUE
+            GetF10CacheInfo,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_SYSTEM_PM_TABLE == TRUE
+            GetF10SysPmTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_WHEA_INIT == TRUE
+            GetF10WheaInitData,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+            F10GetPlatformTypeSpecificInfo,
+          #else
+            (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+          #endif
+          #if IS_NB_PSTATE_ENABLED == TRUE
+            F10CommonRevCIsNbPstateEnabled,
+          #else
+            (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10DoesLinkHaveHtPhyFeats,
+          #else
+            (PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10SetHtPhyRegister,
+          #else
+            (PF_SET_HT_PHY_REGISTER) CommonAssert,
+          #endif
+          #if BASE_FAMILY_PCI == TRUE
+            F10GetHtLinkFeatures,
+          #else
+            (PF_GET_HT_LINK_FEATURES) CommonAssert,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (REGISTER_TABLE **) F10DaRegisterTables,
+          #else
+            NULL,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
+          #else
+            NULL,
+          #endif
+          NULL,
+          #if AGESA_ENTRY_INIT_EARLY == TRUE
+            GetCommonEarlyInitOnCoreTable
+          #else
+            (PF_GET_EARLY_INIT_TABLE) CommonVoid
+          #endif
+        };
+
+        #define DA_SOCKETS 1
+        #define DA_MODULES 1
+        #define DA_RECOVERY_SOCKETS 1
+        #define DA_RECOVERY_MODULES 1
+        extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
+        #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
+        #ifndef ADVCFG_PLATFORM_SOCKETS
+          #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+        #else
+          #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
+            #undef ADVCFG_PLATFORM_SOCKETS
+            #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+          #endif
+        #endif
+        #ifndef ADVCFG_PLATFORM_MODULES
+          #define ADVCFG_PLATFORM_MODULES DA_MODULES
+        #else
+          #if ADVCFG_PLATFORM_MODULES < DA_MODULES
+            #undef ADVCFG_PLATFORM_MODULES
+            #define ADVCFG_PLATFORM_MODULES DA_MODULES
+          #endif
+        #endif
+        #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
+      #else
+        #define OPT_F10_DA_CPU
+        #define OPT_F10_DA_ID
+      #endif
+    #else
+      #define OPT_F10_DA_CPU
+      #define OPT_F10_DA_ID
+    #endif
+  #else
+    #define OPT_F10_DA_CPU
+    #define OPT_F10_DA_ID
+  #endif
+#else
+  #define OPT_F10_DA_CPU
+  #define OPT_F10_DA_ID
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hHyInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hHyInstall.h
new file mode 100755
index 0000000000..b195d5c556
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hHyInstall.h
@@ -0,0 +1,353 @@
+/**
+ * @file
+ *
+ * Install of family 10h model 9 support
+ *
+ * This file generates the defaults tables for family 10h model 9 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifdef OPTION_FAMILY10H
+  #if OPTION_FAMILY10H == TRUE
+    #ifdef OPTION_FAMILY10H_HY
+      #if OPTION_FAMILY10H_HY == TRUE
+        extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
+        extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
+        extern F_CPU_GET_NB_FREQ F10CommonRevDGetNbFrequency;
+        extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
+        extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
+        extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevDGetNumberOfCoresForBrandstring;
+        extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
+          {
+            #if BASE_FAMILY_PCI == TRUE
+              &F10PciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10MultiLinkPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10HyPciRegisterTable,
+            #endif
+            #if BASE_FAMILY_MSR == TRUE
+              &F10MsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10HyMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10HtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10HyHtPhyRegisterTable,
+            #endif
+            // the end.
+            NULL
+          };
+        #endif
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
+          {
+            {MSRREGISTER, SetRegisterForMsrEntry},
+            {PCIREGISTER, SetRegisterForPciEntry},
+            {ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
+            {HtPhyRegister, SetRegisterForHtPhyEntry},
+            {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+            {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+            {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+            {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+            {HtHostPciRegister, SetRegisterForHtHostEntry},
+            {HtTokenPciRegister, F10SetRegisterForHtLinkTokenEntry},
+            {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+            {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+            {TokenPciRegister, SetRegisterForTokenPciEntry},
+            {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+            {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+            // End
+            {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+          };
+        #endif
+
+        CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
+        {
+          0,
+          #if GET_PSTATE_POWER == TRUE
+            F10GetPstatePower,
+          #else
+            (PF_CPU_GET_PSTATE_POWER) CommonAssert,
+          #endif
+          #if GET_PSTATE_FREQ == TRUE
+            F10GetPstateFrequency,
+          #else
+            (PF_CPU_GET_PSTATE_FREQ) CommonAssert,
+          #endif
+          #if DISABLE_PSTATE == TRUE
+            F10DisablePstate,
+          #else
+            (PF_CPU_DISABLE_PSTATE) CommonAssert,
+          #endif
+          #if TRANSITION_PSTATE == TRUE
+            F10TransitionPstate,
+          #else
+            (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+          #endif
+          #if PROC_IDD_MAX == TRUE
+            F10CommonRevDGetProcIddMax,
+          #else
+            (PF_CPU_GET_IDD_MAX) CommonAssert,
+          #endif
+          #if GET_TSC_RATE == TRUE
+            F10GetTscRate,
+          #else
+            (PF_CPU_GET_TSC_RATE) CommonAssert,
+          #endif
+          #if PSTATE_TRANSITION_LATENCY == TRUE
+            F10GetPstateTransLatency,
+          #else
+            (PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
+          #endif
+          #if GET_PSTATE_REGISTER_INFO == TRUE
+            F10GetPstateRegisterInfo,
+          #else
+            (PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
+          #endif
+          #if GET_PSTATE_MAX_STATE == TRUE
+            F10GetPstateMaxState,
+          #else
+            (PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
+          #endif
+          #if SET_PSTATE_LEVELING_REG == TRUE
+            F10PstateLevelingCoreMsrModify,
+          #else
+            (PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
+          #endif
+          #if GET_NB_FREQ == TRUE
+            F10CommonRevDGetNbFrequency,
+          #else
+            (PF_CPU_GET_NB_FREQ) CommonAssert,
+          #endif
+          #if IS_NBCOF_INIT_NEEDED == TRUE
+            F10CommonRevDGetNbCofVidUpdate,
+          #else
+            (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+          #endif
+          #if AP_INITIAL_LAUNCH == TRUE
+            F10LaunchApCore,
+          #else
+            (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+          #endif
+          #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+            F10CommonRevDGetNumberOfCoresForBrandstring,
+          #else
+            (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+          #endif
+          #if GET_AP_MAILBOX_FROM_HW == TRUE
+            F10GetApMailboxFromHardware,
+          #else
+            (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+          #endif
+          #if SET_AP_CORE_NUMBER == TRUE
+            F10SetApCoreNumber,
+          #else
+            (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if GET_AP_CORE_NUMBER == TRUE
+            F10GetApCoreNumber,
+          #else
+            (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if TRANSFER_AP_CORE_NUMBER == TRUE
+            F10TransferApCoreNumber,
+          #else
+            (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if ID_POSITION_INITIAL_APICID == TRUE
+            F10CpuAmdCoreIdPositionInInitialApicId,
+          #else
+            (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+          #endif
+          #if SAVE_FEATURES == TRUE
+            F10SaveFeatures,
+          #else
+            (PF_CPU_SAVE_FEATURES) CommonAssert,
+          #endif
+          #if WRITE_FEATURES == TRUE
+            F10WriteFeatures,
+          #else
+            (PF_CPU_WRITE_FEATURES) CommonAssert,
+          #endif
+          #if SET_WARM_RESET_FLAG == TRUE
+            F10SetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if GET_WARM_RESET_FLAG == TRUE
+            F10GetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if BRAND_STRING1 == TRUE
+            GetF10BrandIdString1,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if BRAND_STRING2 == TRUE
+            GetF10BrandIdString2,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES == TRUE
+            GetF10HyMicroCodePatchesStruct,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+            GetF10HyMicrocodeEquivalenceTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_CACHE_INFO == TRUE
+            GetF10CacheInfo,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_SYSTEM_PM_TABLE == TRUE
+            GetF10SysPmTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_WHEA_INIT == TRUE
+            GetF10WheaInitData,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+            F10GetPlatformTypeSpecificInfo,
+          #else
+            (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+          #endif
+          #if IS_NB_PSTATE_ENABLED == TRUE
+            (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+          #else
+            (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10DoesLinkHaveHtPhyFeats,
+          #else
+            (PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10SetHtPhyRegister,
+          #else
+            (PF_SET_HT_PHY_REGISTER) CommonAssert,
+          #endif
+          #if BASE_FAMILY_PCI == TRUE
+            F10GetHtLinkFeatures,
+          #else
+            (PF_GET_HT_LINK_FEATURES) CommonAssert,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (REGISTER_TABLE **) F10HyRegisterTables,
+          #else
+            NULL,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
+          #else
+            NULL,
+          #endif
+          #if MODEL_SPECIFIC_HT_PCI == TRUE
+            (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
+          #else
+            NULL,
+          #endif
+          #if AGESA_ENTRY_INIT_EARLY == TRUE
+            #if OPTION_MEMCTLR_C32 == TRUE
+              GetF10HyEarlyInitOnCoreTable
+            #else
+              GetCommonEarlyInitOnCoreTable
+            #endif
+          #else
+            (PF_GET_EARLY_INIT_TABLE) CommonVoid
+          #endif
+        };
+
+        #define HY_SOCKETS 8
+        #define HY_MODULES 2
+        #define HY_RECOVERY_SOCKETS 1
+        #define HY_RECOVERY_MODULES 1
+        extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
+        #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
+        #ifndef ADVCFG_PLATFORM_SOCKETS
+          #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+        #else
+          #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
+            #undef ADVCFG_PLATFORM_SOCKETS
+            #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+          #endif
+        #endif
+        #ifndef ADVCFG_PLATFORM_MODULES
+          #define ADVCFG_PLATFORM_MODULES HY_MODULES
+        #else
+          #if ADVCFG_PLATFORM_MODULES < HY_MODULES
+            #undef ADVCFG_PLATFORM_MODULES
+            #define ADVCFG_PLATFORM_MODULES HY_MODULES
+          #endif
+        #endif
+        #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
+      #else
+        #define OPT_F10_HY_CPU
+        #define OPT_F10_HY_ID
+      #endif
+    #else
+      #define OPT_F10_HY_CPU
+      #define OPT_F10_HY_ID
+    #endif
+  #else
+    #define OPT_F10_HY_CPU
+    #define OPT_F10_HY_ID
+  #endif
+#else
+  #define OPT_F10_HY_CPU
+  #define OPT_F10_HY_ID
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h
new file mode 100755
index 0000000000..13374e149e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hInstall.h
@@ -0,0 +1,345 @@
+/**
+ * @file
+ *
+ * Install of family 10h support
+ *
+ * This file generates the defaults tables for family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifdef OPTION_FAMILY10H
+  #if OPTION_FAMILY10H == TRUE
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if BASE_FAMILY_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if OPTION_MULTISOCKET == TRUE
+          #if MODEL_SPECIFIC_PCI == TRUE
+            &F10MultiLinkPciRegisterTable,
+          #endif
+        #endif
+        #if OPTION_MULTISOCKET == FALSE
+          #if MODEL_SPECIFIC_PCI == TRUE
+            &F10SingleLinkPciRegisterTable,
+          #endif
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
+      {
+        {MSRREGISTER, SetRegisterForMsrEntry},
+        {PCIREGISTER, SetRegisterForPciEntry},
+        {ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
+    {
+      0,
+      #if GET_PSTATE_POWER == TRUE
+        F10GetPstatePower,
+      #else
+        (PF_CPU_GET_PSTATE_POWER) CommonAssert,
+      #endif
+      #if GET_PSTATE_FREQ == TRUE
+        F10GetPstateFrequency,
+      #else
+        (PF_CPU_GET_PSTATE_FREQ) CommonAssert,
+      #endif
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if PSTATE_TRANSITION_LATENCY == TRUE
+        F10GetPstateTransLatency,
+      #else
+        (PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
+      #endif
+      #if GET_PSTATE_REGISTER_INFO == TRUE
+        F10GetPstateRegisterInfo,
+      #else
+        (PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
+      #endif
+      #if GET_PSTATE_MAX_STATE == TRUE
+        F10GetPstateMaxState,
+      #else
+        (PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
+      #endif
+      #if SET_PSTATE_LEVELING_REG == TRUE
+        F10PstateLevelingCoreMsrModify,
+      #else
+        (PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
+      #else
+        (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetEmptyArray,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetEmptyArray,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10DoesLinkHaveHtPhyFeats,
+      #else
+        (PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonVoid,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonVoid,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetHtLinkFeatures,
+      #else
+        (PF_GET_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10UnknownRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetCommonEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    // Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+    #if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+      #undef  FAMILY_MMIO_BASE_MASK
+      #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+    #endif
+
+    #define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
+    #define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
+  #else
+    #define OPT_F10_ID_TABLE
+    #define OPT_F10_BL_CPU
+    #define OPT_F10_BL_ID
+    #define OPT_F10_DA_CPU
+    #define OPT_F10_DA_ID
+    #define OPT_F10_HY_CPU
+    #define OPT_F10_HY_ID
+    #define OPT_F10_RB_CPU
+    #define OPT_F10_RB_ID
+    #define OPT_F10_UNKNOWN_CPU
+  #endif
+#else
+  #define OPT_F10_ID_TABLE
+  #define OPT_F10_BL_CPU
+  #define OPT_F10_BL_ID
+  #define OPT_F10_DA_CPU
+  #define OPT_F10_DA_ID
+  #define OPT_F10_HY_CPU
+  #define OPT_F10_HY_ID
+  #define OPT_F10_RB_CPU
+  #define OPT_F10_RB_ID
+  #define OPT_F10_UNKNOWN_CPU
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
+{
+  OPT_F10_BL_CPU
+  OPT_F10_DA_CPU
+  OPT_F10_HY_CPU
+  OPT_F10_RB_CPU
+  OPT_F10_UNKNOWN_CPU
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
+{
+  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpuSupportedFamiliesArray[0]
+};
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
+{
+  OPT_F10_BL_ID
+  OPT_F10_DA_ID
+  OPT_F10_HY_ID
+  OPT_F10_RB_ID
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hRbInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hRbInstall.h
new file mode 100755
index 0000000000..2b900b4462
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionFamily10hRbInstall.h
@@ -0,0 +1,355 @@
+/**
+ * @file
+ *
+ * Install of family 10h model 4 support
+ *
+ * This file generates the defaults tables for family 10h model 4 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifdef OPTION_FAMILY10H
+  #if OPTION_FAMILY10H == TRUE
+    #ifdef OPTION_FAMILY10H_RB
+      #if OPTION_FAMILY10H_RB == TRUE
+        extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
+        extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
+        extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
+        extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+        extern F_CPU_GET_NB_FREQ F10CommonRevCGetNbFrequency;
+        extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+        extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+        extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
+          {
+            #if BASE_FAMILY_PCI == TRUE
+              &F10PciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10MultiLinkPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10RevCPciRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_PCI == TRUE
+              &F10RbPciRegisterTable,
+            #endif
+            #if BASE_FAMILY_MSR == TRUE
+              &F10MsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10RevCMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_MSR == TRUE
+              &F10RbMsrRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10HtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10RevCHtPhyRegisterTable,
+            #endif
+            #if MODEL_SPECIFIC_HT_PCI == TRUE
+              &F10RbHtPhyRegisterTable,
+            #endif
+            // the end.
+            NULL
+          };
+        #endif
+
+        #if USES_REGISTER_TABLES == TRUE
+          CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
+          {
+            {MsrRegister, SetRegisterForMsrEntry},
+            {PciRegister, SetRegisterForPciEntry},
+            {ErrataWorkaround, SetRegisterForErrataWorkaroundEntry},
+            {HtPhyRegister, SetRegisterForHtPhyEntry},
+            {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+            {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+            {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+            {HtHostPciRegister, SetRegisterForHtHostEntry},
+            {HtTokenPciRegister, F10SetRegisterForHtLinkTokenEntry},
+            {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+            {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+            {TokenPciRegister, SetRegisterForTokenPciEntry},
+            {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+            {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+            // End
+            {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+          };
+        #endif
+
+        CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
+        {
+          0,
+          #if GET_PSTATE_POWER == TRUE
+            F10GetPstatePower,
+          #else
+            (PF_CPU_GET_PSTATE_POWER) CommonAssert,
+          #endif
+          #if GET_PSTATE_FREQ == TRUE
+            F10GetPstateFrequency,
+          #else
+            (PF_CPU_GET_PSTATE_FREQ) CommonAssert,
+          #endif
+          #if DISABLE_PSTATE == TRUE
+            F10DisablePstate,
+          #else
+            (PF_CPU_DISABLE_PSTATE) CommonAssert,
+          #endif
+          #if TRANSITION_PSTATE == TRUE
+            F10TransitionPstate,
+          #else
+            (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+          #endif
+          #if PROC_IDD_MAX == TRUE
+            F10CommonRevCGetProcIddMax,
+          #else
+            (PF_CPU_GET_IDD_MAX) CommonAssert,
+          #endif
+          #if GET_TSC_RATE == TRUE
+            F10GetTscRate,
+          #else
+            (PF_CPU_GET_TSC_RATE) CommonAssert,
+          #endif
+          #if PSTATE_TRANSITION_LATENCY == TRUE
+            F10GetPstateTransLatency,
+          #else
+            (PF_CPU_PSTATE_TRANSITION_LATENCY) CommonAssert,
+          #endif
+          #if GET_PSTATE_REGISTER_INFO == TRUE
+            F10GetPstateRegisterInfo,
+          #else
+            (PF_CPU_GET_PSTATE_REGISTER_INFO) CommonAssert,
+          #endif
+          #if GET_PSTATE_MAX_STATE == TRUE
+            F10GetPstateMaxState,
+          #else
+            (PF_CPU_GET_PSTATE_MAX_STATE) CommonAssert,
+          #endif
+          #if SET_PSTATE_LEVELING_REG == TRUE
+            F10PstateLevelingCoreMsrModify,
+          #else
+            (PF_CPU_SET_PSTATE_LEVELING_REG) CommonAssert,
+          #endif
+          #if GET_NB_FREQ == TRUE
+            F10CommonRevCGetNbFrequency,
+          #else
+            (PF_CPU_GET_NB_FREQ) CommonAssert,
+          #endif
+          #if IS_NBCOF_INIT_NEEDED == TRUE
+            F10CommonRevCGetNbCofVidUpdate,
+          #else
+            (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+          #endif
+          #if AP_INITIAL_LAUNCH == TRUE
+            F10LaunchApCore,
+          #else
+            (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+          #endif
+          #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+            F10CommonRevCGetNumberOfCoresForBrandstring,
+          #else
+            (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+          #endif
+          #if GET_AP_MAILBOX_FROM_HW == TRUE
+            F10GetApMailboxFromHardware,
+          #else
+            (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+          #endif
+          #if SET_AP_CORE_NUMBER == TRUE
+            F10SetApCoreNumber,
+          #else
+            (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if GET_AP_CORE_NUMBER == TRUE
+            F10GetApCoreNumber,
+          #else
+            (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if TRANSFER_AP_CORE_NUMBER == TRUE
+            F10TransferApCoreNumber,
+          #else
+            (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+          #endif
+          #if ID_POSITION_INITIAL_APICID == TRUE
+            F10CpuAmdCoreIdPositionInInitialApicId,
+          #else
+            (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+          #endif
+          #if SAVE_FEATURES == TRUE
+            F10SaveFeatures,
+          #else
+            (PF_CPU_SAVE_FEATURES) CommonAssert,
+          #endif
+          #if WRITE_FEATURES == TRUE
+            F10WriteFeatures,
+          #else
+            (PF_CPU_WRITE_FEATURES) CommonAssert,
+          #endif
+          #if SET_WARM_RESET_FLAG == TRUE
+            F10SetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if GET_WARM_RESET_FLAG == TRUE
+            F10GetAgesaWarmResetFlag,
+          #else
+            (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+          #endif
+          #if BRAND_STRING1 == TRUE
+            GetF10BrandIdString1,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if BRAND_STRING2 == TRUE
+            GetF10BrandIdString2,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES == TRUE
+            GetF10RbMicroCodePatchesStruct,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+            GetF10RbMicrocodeEquivalenceTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_CACHE_INFO == TRUE
+            GetF10CacheInfo,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_SYSTEM_PM_TABLE == TRUE
+            GetF10SysPmTable,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_WHEA_INIT == TRUE
+            GetF10WheaInitData,
+          #else
+            (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+          #endif
+          #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+            F10GetPlatformTypeSpecificInfo,
+          #else
+            (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+          #endif
+          #if IS_NB_PSTATE_ENABLED == TRUE
+            F10CommonRevCIsNbPstateEnabled,
+          #else
+            (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10DoesLinkHaveHtPhyFeats,
+          #else
+            (PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
+          #endif
+          #if (BASE_FAMILY_HT_PCI == TRUE)
+            F10SetHtPhyRegister,
+          #else
+            (PF_SET_HT_PHY_REGISTER) CommonAssert,
+          #endif
+          #if BASE_FAMILY_PCI == TRUE
+            F10GetHtLinkFeatures,
+          #else
+            (PF_GET_HT_LINK_FEATURES) CommonAssert,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (REGISTER_TABLE **) F10RbRegisterTables,
+          #else
+            NULL,
+          #endif
+          #if USES_REGISTER_TABLES == TRUE
+            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
+          #else
+            NULL,
+          #endif
+          NULL,
+          #if AGESA_ENTRY_INIT_EARLY == TRUE
+            GetCommonEarlyInitOnCoreTable
+          #else
+            (PF_GET_EARLY_INIT_TABLE) CommonVoid
+          #endif
+        };
+
+        #define RB_SOCKETS 8
+        #define RB_MODULES 1
+        #define RB_RECOVERY_SOCKETS 1
+        #define RB_RECOVERY_MODULES 1
+        extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
+        #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
+        #ifndef ADVCFG_PLATFORM_SOCKETS
+          #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+        #else
+          #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
+            #undef ADVCFG_PLATFORM_SOCKETS
+            #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+          #endif
+        #endif
+        #ifndef ADVCFG_PLATFORM_MODULES
+          #define ADVCFG_PLATFORM_MODULES RB_MODULES
+        #else
+          #if ADVCFG_PLATFORM_MODULES < RB_MODULES
+            #undef ADVCFG_PLATFORM_MODULES
+            #define ADVCFG_PLATFORM_MODULES RB_MODULES
+          #endif
+        #endif
+        #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
+      #else
+        #define OPT_F10_RB_CPU
+        #define OPT_F10_RB_ID
+      #endif
+    #else
+      #define OPT_F10_RB_CPU
+      #define OPT_F10_RB_ID
+    #endif
+  #else
+    #define OPT_F10_RB_CPU
+    #define OPT_F10_RB_ID
+  #endif
+#else
+  #define OPT_F10_RB_CPU
+  #define OPT_F10_RB_ID
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h
new file mode 100755
index 0000000000..e5dfb470e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ *
+ * Install of build option: HT Assist
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HT_ASSIST_INSTALL_H_
+#define _OPTION_HT_ASSIST_INSTALL_H_
+
+#include "cpuHtAssist.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_HT_ASSIST_FEAT
+#define F10_HT_ASSIST_SUPPORT
+#define HT_ASSIST_AP_DISABLE_CACHE
+#define HT_ASSIST_AP_ENABLE_CACHE
+#if OPTION_HT_ASSIST == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_HY == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
+          #undef OPTION_HT_ASSIST_FEAT
+          #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
+          extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
+          #undef F10_HT_ASSIST_SUPPORT
+          #define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
+        #endif
+      #endif
+    #endif
+    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
+    {
+      F10_HT_ASSIST_SUPPORT
+      {0, NULL}
+    };
+    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
+    {
+      (sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+      &HtAssistFamilyServiceArray[0]
+    };
+
+    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+    #undef HT_ASSIST_AP_DISABLE_CACHE
+    #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
+    #undef HT_ASSIST_AP_ENABLE_CACHE
+    #define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
+  #endif
+#endif
+
+#endif  // _OPTION_HT_ASSIST_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHtInstall.h
new file mode 100755
index 0000000000..eaf1121a77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionHtInstall.h
@@ -0,0 +1,310 @@
+/**
+ * @file
+ *
+ * Install of build option: Ht
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HT_INSTALL_H_
+#define _OPTION_HT_INSTALL_H_
+
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htTopologies.h"
+/*
+ * Advanced Option only, hardware socket naming is the preferred method.
+ */
+#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
+#else
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
+#endif
+
+/*
+ * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
+ */
+#ifndef OPTION_IS_RECOVERY_HT
+  #define OPTION_IS_RECOVERY_HT TRUE
+#endif
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition.
+ */
+
+#ifndef OPTION_MULTISOCKET
+  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+#ifndef OPTION_FAMILY10H
+  #ifndef OPTION_FAMILY12H
+    #ifndef OPTION_FAMILY14H
+      #error  BLDOPT: No supported Family is defined (OPTION_FAMILYnnH)
+    #endif
+    #define OPTION_FAMILY12H FALSE
+  #endif
+  #define OPTION_FAMILY10H FALSE
+#endif
+#ifndef OPTION_FAMILY12H
+  #define OPTION_FAMILY12H FALSE
+#endif
+#ifndef OPTION_FAMILY14H
+  #define OPTION_FAMILY14H FALSE
+#endif
+
+/*
+ * Based on user level options, set Ht internal options.
+ * For now, Family 10h support will assume single module.  For multi module,
+ * this will have to be changed to not set non-coherent only.
+ */
+#define OPTION_HT_NON_COHERENT_ONLY FALSE
+
+#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+/* Fusion Families do not need a non-coherent only option. */
+#else
+  #if OPTION_MULTISOCKET == FALSE
+    #if OPTION_FAMILY10H == TRUE
+      #undef OPTION_HT_NON_COHERENT_ONLY
+      #define OPTION_HT_NON_COHERENT_ONLY TRUE
+    #endif
+  #endif
+#endif
+
+/*
+ * Macros will generate the correct item reference based on options
+ */
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #if OPTION_HT_NON_COHERENT_ONLY == FALSE
+    #if OPTION_FAMILY10H == FALSE
+      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+      #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
+      #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
+    #else
+      #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesDefault
+      #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceDefault
+    #endif
+    #if OPTION_FAMILY10H == TRUE
+      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbDefault, &HtFam10RevDNbDefault,
+    #else
+      #define INTERNAL_HT_OPTION_FAM10_NB
+    #endif
+    #if OPTION_FAMILY12H == TRUE
+      #define INTERNAL_HT_OPTION_FAM12_NB     &HtFam12Nb,
+    #else
+      #define INTERNAL_HT_OPTION_FAM12_NB
+    #endif
+    #if OPTION_FAMILY14H == TRUE
+      #define INTERNAL_HT_OPTION_FAM14_NB     &HtFam14Nb,
+    #else
+      #define INTERNAL_HT_OPTION_FAM14_NB
+    #endif
+  #else
+    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+    #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+      #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
+      #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
+    #else
+      #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNonCoherentOnly
+      #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceNonCoherentOnly
+    #endif
+    #if OPTION_FAMILY10H == TRUE
+      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbNonCoherentOnly,
+    #else
+      #define INTERNAL_HT_OPTION_FAM10_NB
+    #endif
+    #if OPTION_FAMILY12H == TRUE
+      #define INTERNAL_HT_OPTION_FAM12_NB     &HtFam12Nb,
+    #else
+      #define INTERNAL_HT_OPTION_FAM12_NB
+    #endif
+    #if OPTION_FAMILY14H == TRUE
+      #define INTERNAL_HT_OPTION_FAM14_NB     &HtFam14Nb,
+    #else
+      #define INTERNAL_HT_OPTION_FAM14_NB
+    #endif
+  #endif
+
+  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
+  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
+    #undef INTERNAL_ONLY_NB_LIST_ITEM
+    #define INTERNAL_ONLY_NB_LIST_ITEM
+  #endif
+
+  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
+   * is ok to have a comma because the final item (NULL) is added below.
+   */
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
+                                             INTERNAL_ONLY_NB_LIST_ITEM \
+                                             INTERNAL_HT_OPTION_FAM10_NB \
+                                             INTERNAL_HT_OPTION_FAM12_NB \
+                                             INTERNAL_HT_OPTION_FAM14_NB
+
+#else
+  #define INTERNAL_HT_OPTION_FEATURES     NULL
+  #define INTERNAL_HT_OPTION_INTERFACE    NULL
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
+  #define HT_OPTIONS_PLATFORM             NULL
+  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+#endif
+
+#ifdef AGESA_ENTRY_INIT_EARLY
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+
+    extern HT_FEATURES HtFeaturesDefault;
+    extern HT_FEATURES HtFeaturesNonCoherentOnly;
+    extern HT_FEATURES HtFeaturesNone;
+    extern HT_INTERFACE HtInterfaceDefault;
+    extern HT_INTERFACE HtInterfaceNonCoherentOnly;
+    extern HT_INTERFACE HtInterfaceMapsOnly;
+    extern HT_INTERFACE HtInterfaceNone;
+    extern NORTHBRIDGE HtFam10NbDefault;
+    extern NORTHBRIDGE HtFam10RevDNbDefault;
+    extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam12Nb;
+    extern NORTHBRIDGE HtFam14Nb;
+    extern NORTHBRIDGE HtFam10NbNone;
+
+    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
+      INTERNAL_HT_OPTION_SUPPORTED_NBS
+      NULL
+    };
+
+    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
+    {
+      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
+      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
+      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
+      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
+      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
+      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
+      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
+      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
+    };
+    #ifndef HT_OPTIONS_PLATFORM
+      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
+    #endif
+
+    /**
+     * A list of all the supported topologies.
+     *
+     */
+    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
+      {
+        amdHtTopologySingleNode,
+        amdHtTopologyDualNode,
+        amdHtTopologyThreeLine,
+        amdHtTopologyTriangle,
+        amdHtTopologyFourLine,
+        amdHtTopologyFourStar,
+        amdHtTopologyFourDegenerate,
+        amdHtTopologyFourSquare,
+        amdHtTopologyFourKite,
+        amdHtTopologyFourFully,
+        amdHtTopologyFiveFully,
+        amdHtTopologyFiveTwistedLadder,
+        amdHtTopologySixFully,
+        amdHtTopologySixDoubloonLower,
+        amdHtTopologySixDoubloonUpper,
+        amdHtTopologySixTwistedLadder,
+        amdHtTopologySevenFully,
+        amdHtTopologySevenTwistedLadder,
+        amdHtTopologyEightFully,
+        amdHtTopologyEightDoubloon,
+        amdHtTopologyEightTwistedLadder,
+        amdHtTopologyEightStraightLadder,
+        amdHtTopologySixTwinTriangles,
+        amdHtTopologyEightTwinFullyFourWays,
+        NULL
+      };
+      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
+    #endif
+
+    /**
+     * Declare the instance of the Ht option configuration structure
+     */
+    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
+      OPTION_IS_RECOVERY_HT,
+      CFG_SET_HTCRC_SYNC_FLOOD,
+      CFG_USE_UNIT_ID_CLUMPING,
+      HT_OPTIONS_PLATFORM,
+      INTERNAL_HT_OPTION_INTERFACE,
+      INTERNAL_HT_OPTION_FEATURES,
+      &HtInstalledFamilyNorthbridgeList,
+      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+    };
+
+  #endif
+#endif
+
+#ifndef OPTION_HT_INIIT_RESET_ENTRY
+
+  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+
+  #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY NULL
+  #endif
+
+  #if OPTION_FAMILY10H == TRUE
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+  #endif
+
+#endif
+
+#ifdef AGESA_ENTRY_INIT_RESET
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+
+    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      0                                            // Unused by options
+    };
+
+    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
+      OPTION_HT_INIIT_RESET_ENTRY
+    };
+  #endif
+
+#endif
+
+#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHwC1eInstall.h
new file mode 100755
index 0000000000..874e3444c8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionHwC1eInstall.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * Install of build option: HW C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HW_C1E_INSTALL_H_
+#define _OPTION_HW_C1E_INSTALL_H_
+
+#include "cpuHwC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_HW_C1E_FEAT
+#define F10_HW_C1E_SUPPORT
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE)
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
+        #undef OPTION_HW_C1E_FEAT
+        #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
+        extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
+        #undef F10_HW_C1E_SUPPORT
+        #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB), &F10HwC1e},
+      #endif
+    #endif
+  #endif
+  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
+  {
+    F10_HW_C1E_SUPPORT
+    {0, NULL}
+  };
+  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
+  {
+    (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+    &HwC1eFamilyServiceArray[0]
+  };
+#endif
+
+#endif  // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionIdsInstall.h
new file mode 100755
index 0000000000..8cb5b7f80b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionIdsInstall.h
@@ -0,0 +1,320 @@
+/**
+ * @file
+ *
+ * IDS Option Install File
+ *
+ * This file generates the defaults tables for family 10h model 5 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_INSTALL_H_
+#define _OPTION_IDS_INSTALL_H_
+#include "Ids.h"
+#include "IdsHt.h"
+#include "IdsLib.h"
+#ifdef __IDS_EXTENDED__
+  #include IDS_EXT_INCLUDE (OptionIdsInternalInstall)
+#endif
+
+
+#define IDS_LATE_RUN_AP_TASK
+
+#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    // Check for all families which include HT Features.
+    #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
+      #undef M_HTIDS_PORT_OVERRIDE_HOOK
+      #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
+    #endif
+  #endif
+#endif // OPTION_IDS_LEVEL
+CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
+
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+    #undef IDS_LATE_RUN_AP_TASK
+    #define IDS_LATE_RUN_AP_TASK  {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate},
+  #endif
+#endif // OPTION_IDS_LEVEL
+
+#if (IDSOPT_TRACING_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+    #include <mu.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+      { (UINT32) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+      { (UINT32) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
+    };
+  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+    #include <mru.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+      { (UINT32) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
+      { (UINT32) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
+    };
+  #else
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) CommonReturnFalse, "DefRet()"},
+      { (UINT32) CommonReturnFalse,  "DefRet()"},
+      { (UINT32) CommonReturnFalse,    "DefRet()"}
+    };
+  #endif
+#endif
+
+
+///Ids Feat Options
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+
+    #ifndef OPTION_IDS_EXTEND_FEATS
+      #define OPTION_IDS_EXTEND_FEATS
+    #endif
+
+    #define OPTION_IDS_FEAT_ECCCTRL\
+                OPTION_IDS_FEAT_ECCCTRL_F10 \
+                OPTION_IDS_FEAT_ECCCTRL_F12
+
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE
+    #define OPTION_IDS_FEAT_ECCCTRL_F10
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+//Ecc symbol size
+        CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlock =
+        {
+          IDS_FEAT_ECC_SYMBOL_SIZE,
+          IDS_BSP_ONLY,
+          IDS_ECCSYMBOLSIZE,
+          AMD_FAMILY_10,
+          IdsSubEccSymbolSize
+        };
+        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE
+        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE &IdsFeatEccSymbolSizeBlock,
+
+//ECC scrub control
+        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F10
+        #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
+      #endif
+    #endif
+
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlock;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFG
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFG &IdsFeatGnbPlatformCfgBlock,
+      #endif
+    #endif
+
+//Ids Feat for F12 only
+    #define OPTION_IDS_FEAT_ECCCTRL_F12
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        //ECC scrub control
+        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F12
+        #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
+      #endif
+    #endif
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
+    {
+      IDS_FEAT_UCODE_UPDATE,
+      IDS_ALL_CORES,
+      IDS_UCODE,
+      IDS_FAMILY_ALL,
+      IdsSubUCode
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
+    {
+      IDS_FEAT_TARGET_PSTATE,
+      IDS_BSP_ONLY,
+      IDS_INIT_LATE_AFTER,
+      IDS_FAMILY_ALL,
+      IdsSubTargetPstate
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
+    {
+      IDS_FEAT_POSTPSTATE,
+      IDS_ALL_CORES,
+      IDS_CPU_Early_Override,
+      IDS_FAMILY_ALL,
+      IdsSubPostPState
+    };
+
+    //Dram controller Features
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
+    {
+      IDS_FEAT_DCT_ALLMEMCLK,
+      IDS_BSP_ONLY,
+      IDS_ALL_MEMORY_CLOCK,
+      AMD_FAMILY_10,
+      IdsSubAllMemClkEn
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
+    {
+      IDS_FEAT_DCT_GANGMODE,
+      IDS_BSP_ONLY,
+      IDS_GANGING_MODE,
+      AMD_FAMILY_10,
+      IdsSubGangingMode
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
+    {
+      IDS_FEAT_DCT_BURSTLENGTH,
+      IDS_BSP_ONLY,
+      IDS_BURST_LENGTH32,
+      AMD_FAMILY_10,
+      IdsSubBurstLength32
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_INIT_POST_BEFORE,
+      AMD_FAMILY_10,
+      IdsSubPowerDownCtrl
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
+    {
+      IDS_FEAT_DCT_DLLSHUTDOWN,
+      IDS_BSP_ONLY,
+      IDS_DLL_SHUT_DOWN,
+      AMD_FAMILY_10,
+      IdsSubDllShutDownSR
+    };
+
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_POWERDOWN_MODE,
+      AMD_FAMILY_10,
+      IdsSubPowerDownMode
+    };
+
+    //Misc Features
+    #define OPTION_IDS_FEAT_PROBEFILTER
+    #ifdef OPTION_FAMILY10H_HY
+      #if OPTION_FAMILY10H_HY == TRUE
+        #undef OPTION_IDS_FEAT_PROBEFILTER
+        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockPlatformCfg;
+        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockEarlyBefore;
+        extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockLateBefore;
+
+        #define OPTION_IDS_FEAT_PROBEFILTER \
+                    &IdsFeatProbeFilterBlockPlatformCfg, \
+                    &IdsFeatProbeFilterBlockEarlyBefore, \
+                    &IdsFeatProbeFilterBlockLateBefore,
+      #endif
+    #endif
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
+    {
+      IDS_FEAT_HDTOUT,
+      IDS_BSP_ONLY,
+      IDS_INIT_EARLY_BEFORE,
+      AMD_FAMILY_10,
+      IdsSubHdtOut
+    };
+
+    CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
+    {
+      IDS_FEAT_HT_SETTING,
+      IDS_BSP_ONLY,
+      IDS_HT_CONTROL,
+      IDS_FAMILY_ALL,
+      IdsSubHtLinkControl
+    };
+
+    CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
+    {
+      &IdsFeatUcodeBlock,
+
+      &IdsFeatTargetPstateBlock,
+
+      &IdsFeatPostPstateBlock,
+
+      OPTION_IDS_FEAT_ECCSYMBOLSIZE
+
+      OPTION_IDS_FEAT_ECCCTRL
+
+      &IdsFeatDctAllMemClkBlock,
+
+      &IdsFeatDctGangModeBlock,
+
+      &IdsFeatDctBurstLengthBlock,
+
+      &IdsFeatDctPowerDownCtrlBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      OPTION_IDS_FEAT_PROBEFILTER
+
+      &IdsFeatHdtOutBlock,
+
+      &IdsFeatHtSettingBlock,
+
+      OPTION_IDS_FEAT_GNB_PLATFORMCFG
+
+      OPTION_IDS_EXTEND_FEATS
+
+      NULL
+    };
+  #else
+    CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
+    {
+      NULL
+    };
+  #endif//IDSOPT_CONTROL_ENABLED
+#else
+  CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
+  {
+    NULL
+  };
+#endif// IDSOPT_IDS_ENABLED
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h
new file mode 100755
index 0000000000..cb1bbdb275
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionLynxMicrocodeInstall.h
@@ -0,0 +1,51 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a Lynx platform solution
+ *
+ * This file generates the defaults tables for the "Lynx" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_LYNX_MICROCODE_INSTALL_H_
+#define _OPTION_LYNX_MICROCODE_INSTALL_H_
+
+// Code goes here
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMaranelloMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMaranelloMicrocodeInstall.h
new file mode 100755
index 0000000000..818b4475ce
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMaranelloMicrocodeInstall.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a Maranello platform solution
+ *
+ * This file generates the defaults tables for the "Maranello" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MARANELLO_MICROCODE_INSTALL_H_
+#define _OPTION_MARANELLO_MICROCODE_INSTALL_H_
+
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
+
+// 'NULL' must be put at the end of MicroCodePatchArray[]
+CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000c4,
+  NULL
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f10/Include/OptionMemory.h
new file mode 100755
index 0000000000..516829f8ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMemory.h
@@ -0,0 +1,269 @@
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_H_
+#define _OPTION_MEMORY_H_
+
+/* Memory Includes */
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mp.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MAX_FF_TYPES      6   ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+* STANDARD MEMORY FEATURE FUNCTION POINTER
+*/
+
+typedef BOOLEAN OPTION_MEM_FEATURE_NB (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+typedef BOOLEAN MEM_TECH_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+typedef UINT8 MEM_TABLE_FEAT (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+
+#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION  0x01
+
+/**
+ *  MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Northbridge devices supported by
+ *  AGESA.
+ */
+typedef struct _MEM_FEAT_BLOCK_NB {
+  UINT16              OptMemFeatVersion; ///< Version of memory feature block.
+  OPTION_MEM_FEATURE_NB  *OnlineSpare; ///< Online spare support.
+  OPTION_MEM_FEATURE_NB  *InterleaveBanks; ///< Bank (Chip select) interleaving support.
+  OPTION_MEM_FEATURE_NB  *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
+  OPTION_MEM_FEATURE_NB  *CheckInterleaveNodes; ///< Check for Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveNodes; ///< Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveChannels; ///< Channel interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveRegion;  ///< Interleave Region support.
+  OPTION_MEM_FEATURE_NB  *CheckEcc; ///< Check for ECC support.
+  OPTION_MEM_FEATURE_NB  *InitEcc; ///< ECC support.
+  OPTION_MEM_FEATURE_NB  *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
+  OPTION_MEM_FEATURE_NB  *LvDdr3; ///< Low voltage DDR3 dimm support
+  OPTION_MEM_FEATURE_NB  *OnDimmThermal; ///< On-Dimm thermal management
+  MEM_TECH_FEAT  *DramInit; ///< Choose the type of Dram init (hardware based or software based).
+  OPTION_MEM_FEATURE_NB  *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_NB  *InitCPG; ///< Continuous pattern generation.
+} MEM_FEAT_BLOCK_NB;
+
+typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+typedef BOOLEAN MEM_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *mmSharedPtr,     ///< Pointer to Memory scratchpad
+  IN       UINT8 NodeID
+  );
+
+typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+typedef VOID MEM_INITIALIZER (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+ );
+
+typedef AGESA_STATUS MEM_PLATFORM_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN UINT8 SocketID,
+  IN CH_DEF_STRUCT *CurrentChannel
+  );
+
+typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_TECH_TRAINING_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION  0x01
+
+/**
+ * MAIN FEATURE BLOCK - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_BLOCK_MAIN {
+  UINT16              OptMemFeatVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
+  OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
+  OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
+  OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
+  OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
+  OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
+  OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
+  OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
+  OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
+  OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
+} MEM_FEAT_BLOCK_MAIN;
+
+#define MEM_NB_SUPPORT_STRUCT_VERSION  0x01
+#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION  0x01
+/**
+ *  MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_FEAT_BLOCK {
+  UINT16  OptMemTechFeatVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
+  MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
+  MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
+  MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
+  MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
+  MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
+  MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
+  MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
+} MEM_TECH_FEAT_BLOCK;
+
+
+/**
+ * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
+ * options together in a list to provide a single access point for all code to use
+ * and to ensure that everything corresponding to the same NB type is grouped together.
+ *
+ * The Technology Block pointers are not included in this structure because DRAM technology
+ * needs to be decoupled from the northbridge type.
+ *
+ */
+typedef struct _MEM_NB_SUPPORT {
+  UINT16              MemNBSupportVersion; ///< Version of northbridge support.
+  MEM_NB_CONSTRUCTOR  *MemConstructNBBlock; ///< NorthBridge block constructor.
+  MEM_INITIALIZER     *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
+  MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
+  MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
+  MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
+} MEM_NB_SUPPORT;
+
+/*
+ *  MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
+ *  memory non-training feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology devices supported by
+ *  AGESA.
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+/* Feature Default Return */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN MemMDefRet (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+/* Table Feature Default Return */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+/* S3 Feature Default Return */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemProcessConditionalOverrides (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 PsoAction,
+  IN       UINT8 Dimm
+   );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h
new file mode 100755
index 0000000000..e277f5dca9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryInstall.h
@@ -0,0 +1,2683 @@
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_INSTALL_H_
+#define _OPTION_MEMORY_INSTALL_H_
+
+/*-------------------------------------------------------------------------------
+ *  This option file is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+/*----------------------------------------------------------------------------------
+ * FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return FALSE;
+}
+
+BOOLEAN MemMDefRet (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return TRUE;
+}
+
+STATIC BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == FALSE
+STATIC BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return FALSE;
+}
+#endif
+
+/*----------------------------------------------------------------------------------
+ * TABLE FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  )
+{
+  return 0;
+}
+/*----------------------------------------------------------------------------------
+ * FEATURE S3 BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return TRUE;
+}
+
+#if (OPTION_MEMCTLR_DR == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
+    #endif
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
+    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
+  #else
+    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_DA == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      #if (OPTION_MEMCTLR_Ni == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockNi
+      #else
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
+      #endif
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
+    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
+  #else
+    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_OR == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
+    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
+  #else
+    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_HY == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
+    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
+  #else
+    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_C32 == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
+    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
+  #else
+    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_LN == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN;
+    #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN
+  #else
+    #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_ON == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
+    #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
+  #else
+    #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+/*----------------------------------------------------------------------------------
+ * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
+ *
+ *----------------------------------------------------------------------------------
+*/
+#define MEM_NB_SUPPORT_DR
+#define MEM_NB_SUPPORT_DA
+#define MEM_NB_SUPPORT_HY
+#define MEM_NB_SUPPORT_LN
+#define MEM_NB_SUPPORT_OR
+#define MEM_NB_SUPPORT_C32
+#define MEM_NB_SUPPORT_ON
+#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
+
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+  /*----------------------------------------------------------------------------------
+   * FLOW CONTROL FUNCTION
+   *
+   *  This section selects the function that controls the memory initialization sequence
+   *  based upon the number of processor families that the BIOS will support.
+   */
+
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    extern MEM_MAIN_FLOW_CONTROL MemMFlowDr;
+    #define MEM_MAIN_FLOW_CONTROL_PTR MemMFlowDr
+  #elif (OPTION_MEMCTLR_DA == TRUE)
+    extern MEM_MAIN_FLOW_CONTROL MemMFlowDA;
+    #define MEM_MAIN_FLOW_CONTROL_PTR MemMFlowDA
+  #elif (OPTION_MEMCTLR_HY == TRUE)
+    extern MEM_MAIN_FLOW_CONTROL MemMFlowHy;
+    #define MEM_MAIN_FLOW_CONTROL_PTR MemMFlowHy
+  #elif (OPTION_MEMCTLR_LN == TRUE)
+    extern MEM_MAIN_FLOW_CONTROL MemMFlowLN;
+    #define MEM_MAIN_FLOW_CONTROL_PTR MemMFlowLN
+  #elif (OPTION_MEMCTLR_ON == TRUE)
+    extern MEM_MAIN_FLOW_CONTROL MemMFlowON;
+    #define MEM_MAIN_FLOW_CONTROL_PTR MemMFlowON
+  #elif (OPTION_MEMCTLR_C32 == TRUE)
+    extern MEM_MAIN_FLOW_CONTROL MemMFlowC32;
+    #define MEM_MAIN_FLOW_CONTROL_PTR MemMFlowC32
+  #else
+    #error "Unknown memory initialization sequence for this processor family."
+  #endif
+  MEM_MAIN_FLOW_CONTROL* MemMainFlowControlPtr = MEM_MAIN_FLOW_CONTROL_PTR;
+
+  #if (OPTION_ONLINE_SPARE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
+    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
+    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
+  #else
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
+    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
+  #endif
+
+  #if (OPTION_MEM_RESTORE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
+    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
+  #else
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
+  #endif
+
+  #if (OPTION_BANK_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
+    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
+  #else
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
+  #endif
+
+  #if (OPTION_NODE_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
+    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
+  #else
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
+  #endif
+
+  #if (OPTION_DCT_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
+  #else
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
+  #endif
+
+  #if (OPTION_ECC == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
+    #define MEM_MAIN_FEATURE_ECC  MemMEcc
+    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
+    extern OPTION_MEM_FEATURE_NB MemFInitECC;
+    #define MEM_FEATURE_CK_ECC   MemFCheckECC
+    #define MEM_FEATURE_ECC   MemFInitECC
+  #else
+    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
+    #define MEM_FEATURE_CK_ECC   MemFDefRet
+    #define MEM_FEATURE_ECC   MemFDefRet
+  #endif
+
+  #if (OPTION_EMP == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInitEMP;
+    #define MEM_FEATURE_EMP   MemFInitEMP
+  #else
+    #define MEM_FEATURE_EMP   MemFDefRet
+  #endif
+
+  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
+  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
+
+  #if (OPTION_DMI == TRUE)
+    #if (OPTION_DDR3 == TRUE)
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
+    #else
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
+    #endif
+  #else
+    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
+  #endif
+
+  #if (OPTION_DDR3 == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
+    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
+    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
+    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
+  #else
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
+    #define MEM_FEATURE_LVDDR3 MemFDefRet
+  #endif
+
+  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
+  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
+
+  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
+  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
+
+  #if (OPTION_PARALLEL_TRAINING == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
+  #else
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+  #endif
+
+  #if (OPTION_DIMM_EXCLUDE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
+    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
+  #else
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
+  #endif
+
+  /*----------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
+   *
+   *----------------------------------------------------------------------------------
+  */
+  #if OPTION_DDR2 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
+    #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR2
+  #endif
+  #if OPTION_DDR3 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
+    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+//      extern MEM_TECH_FEAT MemTDramInitSw3;
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+  /*---------------------------------------------------------------------------------------------------
+   * FEATURE BLOCKS
+   *
+   *  This section instantiates a feature block structure for each memory controller installed
+   *  by the platform solution install file.
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEERHOUND FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGNb;
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGNb
+    #else
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MemFDefRet,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_TECH_FEATURE_CPG
+    };
+
+    #undef MEM_NB_SUPPORT_DR
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
+    extern MEM_INITIALIZER MemNInitDefaultsDR;
+
+
+    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
+  #endif // OPTION_MEMCTRL_DR
+
+  /*---------------------------------------------------------------------------------------------------
+   * DASHOUND FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGNb;
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGNb
+    #else
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    #if (OPTION_MEMCTLR_Ni == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MEM_TECH_FEATURE_CPG
+      };
+
+      #undef MEM_NB_SUPPORT_DA
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
+      extern MEM_INITIALIZER MemNInitDefaultsNi;
+
+      #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
+    #else
+      MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MEM_TECH_FEATURE_CPG
+      };
+
+      #undef MEM_NB_SUPPORT_DA
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
+      extern MEM_INITIALIZER MemNInitDefaultsDA;
+
+
+      #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
+    #endif
+  #endif // OPTION_MEMCTRL_DA
+
+  /*---------------------------------------------------------------------------------------------------
+   * HYDRA FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGNb;
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGNb
+    #else
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_TECH_FEATURE_CPG
+    };
+
+    #undef MEM_NB_SUPPORT_HY
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
+    extern MEM_INITIALIZER MemNInitDefaultsHY;
+    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
+  #endif // OPTION_MEMCTRL_HY
+  /*---------------------------------------------------------------------------------------------------
+   * LLANO FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_LN == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
+    #else
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockLn = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MemFDefRet,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MemFDefRet,
+      MemFDefRet,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MEM_FEATURE_REGION_INTERLEAVE,
+      MEM_FEATURE_CK_ECC,
+      MemFDefRet,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_TECH_FEATURE_CPG
+    };
+    #undef MEM_NB_SUPPORT_LN
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN;
+    extern MEM_INITIALIZER MemNInitDefaultsLN;
+    #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
+
+  #endif // OPTION_MEMCTRL_LN
+
+  /*---------------------------------------------------------------------------------------------------
+   * ONTARIO FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_ON == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
+    #else
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockOn = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MemFDefRet,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet,
+      MemFDefRet,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_TECH_FEATURE_CPG
+    };
+
+    #undef MEM_NB_SUPPORT_ON
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
+    extern MEM_INITIALIZER MemNInitDefaultsON;
+    #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
+
+  #endif // OPTION_MEMCTRL_ON
+
+  /*---------------------------------------------------------------------------------------------------
+   * OROCHI FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_FEATURE_TRAINING
+    #if (OPTION_PARALLEL_TRAINING == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemFParallelTrainingOr;
+      #define MEM_FEATURE_TRAINING  MemFParallelTrainingOr
+    #else
+      extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+      #define MEM_FEATURE_TRAINING  MemFStandardTraining
+    #endif
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECCX8,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet
+    };
+
+    #undef MEM_NB_SUPPORT_OR
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
+    extern MEM_INITIALIZER MemNInitDefaultsOR;
+    #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
+
+  #endif // OPTION_MEMCTRL_OR
+
+  /*---------------------------------------------------------------------------------------------------
+   * C32 FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGNb;
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGNb
+    #else
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_TECH_FEATURE_CPG
+    };
+
+    #undef MEM_NB_SUPPORT_C32
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
+    extern MEM_INITIALIZER MemNInitDefaultsC32;
+    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
+  #endif // OPTION_MEMCTRL_C32
+
+  /*---------------------------------------------------------------------------------------------------
+   * MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
+    MEM_MAIN_FEATURE_TRAINING,
+    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
+    MEM_MAIN_FEATURE_ONLINE_SPARE,
+    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
+    MEM_MAIN_FEATURE_ECC,
+    MEM_MAIN_FEATURE_MEM_CLEAR,
+    MEM_MAIN_FEATURE_MEM_DMI,
+    MEM_MAIN_FEATURE_LVDDR3,
+    MEM_MAIN_FEATURE_UMAALLOC,
+    MEM_MAIN_FEATURE_MEM_SAVE,
+    MEM_MAIN_FEATURE_MEM_RESTORE
+  };
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * Technology Training SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
+  #if OPTION_MEMCTLR_DR
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #endif
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDefNb
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_DA
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #endif
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDefNb
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_HY
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #endif
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+//      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDefNb
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_C32
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #endif
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDefNb
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_LN
+    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDefNb
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_OR
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #endif
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_ON
+    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #define NB_TRAIN_FLOW_DDR2    MemNDefNb
+    #if OPTION_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDefNb
+    #endif
+  #endif
+
+  MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
+    MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+    TECH_TRAIN_ENTER_HW_TRN_DDR2,
+    TECH_TRAIN_SW_WL_DDR2,
+    TECH_TRAIN_HW_WL_P1_DDR2,
+    TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+    TECH_TRAIN_HW_WL_P2_DDR2,
+    TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+    TECH_TRAIN_EXIT_HW_TRN_DDR2,
+    TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+    TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+    TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+    TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+    TECH_TRAIN_MAX_RD_LAT_DDR2
+  };
+
+  MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
+    MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+    TECH_TRAIN_ENTER_HW_TRN_DDR3,
+    TECH_TRAIN_SW_WL_DDR3,
+    TECH_TRAIN_HW_WL_P1_DDR3,
+    TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+    TECH_TRAIN_HW_WL_P2_DDR3,
+    TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+    TECH_TRAIN_EXIT_HW_TRN_DDR3,
+    TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+    TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+    TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+    TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+    TECH_TRAIN_MAX_RD_LAT_DDR3
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NB_TRAIN_FLOW_DDR2,
+    NB_TRAIN_FLOW_DDR3,
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+    MEM_TECH_CONSTRUCTOR_DDR2
+    MEM_TECH_CONSTRUCTOR_DDR3
+    NULL
+  };
+   /*---------------------------------------------------------------------------------------------------
+   * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if  OPTION_MEMCTLR_HY
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUHy2,
+      #else
+        #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUHy3,
+      #else
+        #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsRHy2,
+      #else
+        #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsRHy3,
+      #else
+        #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsSHy2,
+      #else
+        #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsSHy3,
+      #else
+        #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
+    PLAT_SP_HY_FF_UDIMM2
+    PLAT_SP_HY_FF_RDIMM2
+    PLAT_SP_HY_FF_SDIMM2
+    PLAT_SP_HY_FF_UDIMM3
+    PLAT_SP_HY_FF_RDIMM3
+    PLAT_SP_HY_FF_SDIMM3
+  };
+
+  #if OPTION_MEMCTLR_DR
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDr2,
+      #else
+        #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDr3,
+      #else
+        #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsRDr2,
+      #else
+        #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsRDr3,
+      #else
+        #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsSDr3,
+      #else
+        #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
+    PLAT_SP_DR_FF_UDIMM2
+    PLAT_SP_DR_FF_RDIMM2
+    PLAT_SP_DR_FF_SDIMM2
+    PLAT_SP_DR_FF_UDIMM3
+    PLAT_SP_DR_FF_RDIMM3
+    PLAT_SP_DR_FF_SDIMM3
+  };
+
+  #if OPTION_MEMCTLR_DA
+    #if OPTION_MEMCTLR_Ni
+      #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSNi3,
+      #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUNi3,
+    #else
+      #if OPTION_UDIMMS
+        #if OPTION_DDR2
+          #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+        #else
+          #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+        #endif
+        #if OPTION_DDR3
+          #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDA3,
+        #else
+          #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
+        #endif
+      #else
+        #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+        #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+      #if OPTION_RDIMMS
+        #if OPTION_DDR2
+          #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+        #else
+          #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+        #endif
+        #if OPTION_DDR3
+          #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+        #else
+          #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+        #endif
+      #else
+        #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+        #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+      #if OPTION_SODIMMS
+        #if OPTION_DDR2
+          #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsSDA2,
+        #else
+          #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+        #endif
+        #if OPTION_DDR3
+          #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSDA3,
+        #else
+          #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
+        #endif
+      #else
+        #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+        #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+    #endif
+  #else
+    #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
+    PLAT_SP_DA_FF_UDIMM2
+    PLAT_SP_DA_FF_RDIMM2
+    PLAT_SP_DA_FF_SDIMM2
+    PLAT_SP_DA_FF_UDIMM3
+    PLAT_SP_DA_FF_RDIMM3
+    PLAT_SP_DA_FF_SDIMM3
+  };
+
+  #if OPTION_MEMCTLR_Or
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_OR_FF_UDIMM2    MemPConstructPsUOr2,
+      #else
+        #define PLAT_SP_OR_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_OR_FF_UDIMM3    MemPConstructPsUOr3,
+      #else
+        #define PLAT_SP_OR_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_OR_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_OR_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_OR_FF_RDIMM2    MemPConstructPsROr2,
+      #else
+        #define PLAT_SP_OR_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_OR_FF_RDIMM3    MemPConstructPsROr3,
+      #else
+        #define PLAT_SP_OR_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_OR_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_OR_FF_RDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_OR_FF_SDIMM2    MemPConstructPsSOr2,
+      #else
+        #define PLAT_SP_OR_FF_SDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_OR_FF_SDIMM3    MemPConstructPsSOr3,
+      #else
+        #define PLAT_SP_OR_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_OR_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_OR_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_OR_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_OR_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_OR_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_OR_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_OR_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_OR_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
+    PLAT_SP_OR_FF_UDIMM2
+    PLAT_SP_OR_FF_RDIMM2
+    PLAT_SP_OR_FF_SDIMM2
+    PLAT_SP_OR_FF_UDIMM3
+    PLAT_SP_OR_FF_RDIMM3
+    PLAT_SP_OR_FF_SDIMM3
+  };
+
+  #if OPTION_MEMCTLR_LN
+    #if OPTION_UDIMMS
+      #if OPTION_DDR3
+        #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsULN3,
+      #else
+        #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR3
+        #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsSLN3,
+      #else
+        #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = {
+    PLAT_SP_LN_FF_SDIMM3
+    PLAT_SP_LN_FF_UDIMM3
+    NULL
+  };
+
+  #if  OPTION_MEMCTLR_C32
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUC32_2,
+      #else
+        #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUC32_3,
+      #else
+        #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsRC32_2,
+      #else
+        #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsRC32_3,
+      #else
+        #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
+    PLAT_SP_C32_FF_UDIMM2
+    PLAT_SP_C32_FF_RDIMM2
+    PLAT_SP_C32_FF_SDIMM2
+    PLAT_SP_C32_FF_UDIMM3
+    PLAT_SP_C32_FF_RDIMM3
+    PLAT_SP_C32_FF_SDIMM3
+  };
+
+  #if OPTION_MEMCTLR_ON
+    #if OPTION_UDIMMS
+      #if OPTION_DDR3
+        #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUON3,
+      #else
+        #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR3
+        #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsSON3,
+      #else
+        #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = {
+    PLAT_SP_ON_FF_SDIMM3
+    PLAT_SP_ON_FF_UDIMM3
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * PLATFORM-SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  #if OPTION_MEMCTLR_DR
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_DR_UDIMM_DDR2     //MemAGetPsCfgUDr2
+      #else
+        #define PSC_DR_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_DR_UDIMM_DDR3    MemAGetPsCfgUDr3,
+      #else
+        #define PSC_DR_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_DR_RDIMM_DDR2    MemAGetPsCfgRDr2,
+      #else
+        #define PSC_DR_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_DR_RDIMM_DDR3    MemAGetPsCfgRDr3,
+      #else
+        #define PSC_DR_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_DR_SODIMM_DDR2    //MemAGetPsCfgSDr2
+      #else
+        #define PSC_DR_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_DR_SODIMM_DDR3    //MemAGetPsCfgSDr3
+      #else
+        #define PSC_DR_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_DA
+    #if OPTION_MEMCTLR_Ni
+      #define PSC_DA_UDIMM_DDR2
+      #define PSC_DA_UDIMM_DDR3     MemAGetPsCfgUNi3,
+      #define PSC_DA_RDIMM_DDR2
+      #define PSC_DA_RDIMM_DDR3
+      #define PSC_DA_SODIMM_DDR2
+      #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSNi3,
+    #else
+      #if OPTION_UDIMMS
+        #if OPTION_DDR2
+          #define PSC_DA_UDIMM_DDR2     //MemAGetPsCfgUDr2
+        #else
+          #define PSC_DA_UDIMM_DDR2
+        #endif
+        #if OPTION_DDR3
+          #define PSC_DA_UDIMM_DDR3    MemAGetPsCfgUDA3,
+        #else
+          #define PSC_DA_UDIMM_DDR3
+        #endif
+      #endif
+      #if OPTION_RDIMMS
+        #if OPTION_DDR2
+          #define PSC_DA_RDIMM_DDR2
+        #else
+          #define PSC_DA_RDIMM_DDR2
+        #endif
+        #if OPTION_DDR3
+          #define PSC_DA_RDIMM_DDR3
+        #else
+          #define PSC_DA_RDIMM_DDR3
+        #endif
+      #endif
+      #if OPTION_SODIMMS
+        #if OPTION_DDR2
+          #define PSC_DA_SODIMM_DDR2    MemAGetPsCfgSDA2,
+        #else
+          #define PSC_DA_SODIMM_DDR2
+        #endif
+        #if OPTION_DDR3
+          #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSDA3,
+        #else
+          #define PSC_DA_SODIMM_DDR3
+        #endif
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_HY
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_HY_UDIMM_DDR2     //MemAGetPsCfgUDr2,
+      #else
+        #define PSC_HY_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_HY_UDIMM_DDR3    MemAGetPsCfgUHy3,
+      #else
+        #define PSC_HY_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_HY_RDIMM_DDR2
+      #else
+        #define PSC_HY_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_HY_RDIMM_DDR3    MemAGetPsCfgRHy3,
+      #else
+        #define PSC_HY_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_HY_SODIMM_DDR2    //MemAGetPsCfgSHy2,
+      #else
+        #define PSC_HY_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_HY_SODIMM_DDR3    //MemAGetPsCfgSHy3,
+      #else
+        #define PSC_HY_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_C32
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_C32_UDIMM_DDR2     //MemAGetPsCfgUDr2,
+      #else
+        #define PSC_C32_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_C32_UDIMM_DDR3    MemAGetPsCfgUC32_3,
+      #else
+        #define PSC_C32_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_C32_RDIMM_DDR2
+      #else
+        #define PSC_C32_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_C32_RDIMM_DDR3    MemAGetPsCfgRC32_3,
+      #else
+        #define PSC_C32_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_C32_SODIMM_DDR2    //MemAGetPsCfgSC32_2,
+      #else
+        #define PSC_C32_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_C32_SODIMM_DDR3    //MemAGetPsCfgSC32_3,
+      #else
+        #define PSC_C32_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_LN
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_LN_UDIMM_DDR2     //MemAGetPsCfgULN2,
+      #else
+        #define PSC_LN_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_LN_UDIMM_DDR3    MemAGetPsCfgULN3,
+      #else
+        #define PSC_LN_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_LN_RDIMM_DDR2
+      #else
+        #define PSC_LN_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_LN_RDIMM_DDR3    //MemAGetPsCfgRLN3,
+      #else
+        #define PSC_LN_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_LN_SODIMM_DDR2    //MemAGetPsCfgSLN2,
+      #else
+        #define PSC_LN_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_LN_SODIMM_DDR3   MemAGetPsCfgSLN3,
+      #else
+        #define PSC_LN_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_OR
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_OR_UDIMM_DDR2     //MemAGetPsCfgUOr2,
+      #else
+        #define PSC_OR_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_OR_UDIMM_DDR3    MemAGetPsCfgUOr3,
+      #else
+        #define PSC_OR_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_OR_RDIMM_DDR2
+      #else
+        #define PSC_OR_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_OR_RDIMM_DDR3    MemAGetPsCfgROr3,
+      #else
+        #define PSC_OR_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_OR_SODIMM_DDR2    //MemAGetPsCfgSOr2,
+      #else
+        #define PSC_OR_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_OR_SODIMM_DDR3    //MemAGetPsCfgSOr3,
+      #else
+        #define PSC_OR_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_ON
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_ON_UDIMM_DDR2     //MemAGetPsCfgUON2,
+      #else
+        #define PSC_ON_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_ON_UDIMM_DDR3    MemAGetPsCfgUON3,
+      #else
+        #define PSC_ON_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_ON_RDIMM_DDR2
+      #else
+        #define PSC_ON_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_ON_RDIMM_DDR3    //MemAGetPsCfgRON3,
+      #else
+        #define PSC_ON_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_ON_SODIMM_DDR2    //MemAGetPsCfgSON2,
+      #else
+        #define PSC_ON_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_ON_SODIMM_DDR3   MemAGetPsCfgSON3,
+      #else
+        #define PSC_ON_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+
+  #ifndef PSC_DR_UDIMM_DDR2
+    #define PSC_DR_UDIMM_DDR2
+  #endif
+  #ifndef PSC_DR_RDIMM_DDR2
+    #define PSC_DR_RDIMM_DDR2
+  #endif
+  #ifndef PSC_DR_SODIMM_DDR2
+    #define PSC_DR_SODIMM_DDR2
+  #endif
+  #ifndef PSC_DR_UDIMM_DDR3
+    #define PSC_DR_UDIMM_DDR3
+  #endif
+  #ifndef PSC_DR_RDIMM_DDR3
+    #define PSC_DR_RDIMM_DDR3
+  #endif
+  #ifndef PSC_DR_SODIMM_DDR3
+    #define PSC_DR_SODIMM_DDR3
+  #endif
+  #ifndef PSC_DA_UDIMM_DDR2
+    #define PSC_DA_UDIMM_DDR2
+  #endif
+  #ifndef PSC_DA_RDIMM_DDR2
+    #define PSC_DA_RDIMM_DDR2
+  #endif
+  #ifndef PSC_DA_SODIMM_DDR2
+    #define PSC_DA_SODIMM_DDR2
+  #endif
+  #ifndef PSC_DA_UDIMM_DDR3
+    #define PSC_DA_UDIMM_DDR3
+  #endif
+  #ifndef PSC_DA_RDIMM_DDR3
+    #define PSC_DA_RDIMM_DDR3
+  #endif
+  #ifndef PSC_DA_SODIMM_DDR3
+    #define PSC_DA_SODIMM_DDR3
+  #endif
+  #ifndef PSC_HY_UDIMM_DDR2
+    #define PSC_HY_UDIMM_DDR2
+  #endif
+  #ifndef PSC_HY_RDIMM_DDR2
+    #define PSC_HY_RDIMM_DDR2
+  #endif
+  #ifndef PSC_HY_SODIMM_DDR2
+    #define PSC_HY_SODIMM_DDR2
+  #endif
+  #ifndef PSC_HY_UDIMM_DDR3
+    #define PSC_HY_UDIMM_DDR3
+  #endif
+  #ifndef PSC_HY_RDIMM_DDR3
+    #define PSC_HY_RDIMM_DDR3
+  #endif
+  #ifndef PSC_HY_SODIMM_DDR3
+    #define PSC_HY_SODIMM_DDR3
+  #endif
+  #ifndef PSC_LN_UDIMM_DDR2
+    #define PSC_LN_UDIMM_DDR2
+  #endif
+  #ifndef PSC_LN_RDIMM_DDR2
+    #define PSC_LN_RDIMM_DDR2
+  #endif
+  #ifndef PSC_LN_SODIMM_DDR2
+    #define PSC_LN_SODIMM_DDR2
+  #endif
+  #ifndef PSC_LN_UDIMM_DDR3
+    #define PSC_LN_UDIMM_DDR3
+  #endif
+  #ifndef PSC_LN_RDIMM_DDR3
+    #define PSC_LN_RDIMM_DDR3
+  #endif
+  #ifndef PSC_LN_SODIMM_DDR3
+    #define PSC_LN_SODIMM_DDR3
+  #endif
+  #ifndef PSC_OR_UDIMM_DDR2
+    #define PSC_OR_UDIMM_DDR2
+  #endif
+  #ifndef PSC_OR_RDIMM_DDR2
+    #define PSC_OR_RDIMM_DDR2
+  #endif
+  #ifndef PSC_OR_SODIMM_DDR2
+    #define PSC_OR_SODIMM_DDR2
+  #endif
+  #ifndef PSC_OR_UDIMM_DDR3
+    #define PSC_OR_UDIMM_DDR3
+  #endif
+  #ifndef PSC_OR_RDIMM_DDR3
+    #define PSC_OR_RDIMM_DDR3
+  #endif
+  #ifndef PSC_OR_SODIMM_DDR3
+    #define PSC_OR_SODIMM_DDR3
+  #endif
+  #ifndef PSC_C32_UDIMM_DDR3
+    #define PSC_C32_UDIMM_DDR3
+  #endif
+  #ifndef PSC_C32_RDIMM_DDR3
+    #define PSC_C32_RDIMM_DDR3
+  #endif
+  #ifndef PSC_ON_UDIMM_DDR2
+    #define PSC_ON_UDIMM_DDR2
+  #endif
+  #ifndef PSC_ON_RDIMM_DDR2
+    #define PSC_ON_RDIMM_DDR2
+  #endif
+  #ifndef PSC_ON_SODIMM_DDR2
+    #define PSC_ON_SODIMM_DDR2
+  #endif
+  #ifndef PSC_ON_UDIMM_DDR3
+    #define PSC_ON_UDIMM_DDR3
+  #endif
+  #ifndef PSC_ON_RDIMM_DDR3
+    #define PSC_ON_RDIMM_DDR3
+  #endif
+  #ifndef PSC_ON_SODIMM_DDR3
+    #define PSC_ON_SODIMM_DDR3
+  #endif
+
+  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+    PSC_DR_UDIMM_DDR2
+    PSC_DR_RDIMM_DDR2
+    PSC_DR_SODIMM_DDR2
+    PSC_DR_UDIMM_DDR3
+    PSC_DR_RDIMM_DDR3
+    PSC_DR_SODIMM_DDR3
+    PSC_DA_SODIMM_DDR2
+    PSC_DA_UDIMM_DDR3
+    PSC_DA_SODIMM_DDR3
+    PSC_HY_UDIMM_DDR3
+    PSC_HY_RDIMM_DDR3
+    PSC_HY_SODIMM_DDR3
+    PSC_LN_UDIMM_DDR3
+    PSC_LN_RDIMM_DDR3
+    PSC_LN_SODIMM_DDR3
+    PSC_OR_UDIMM_DDR3
+    PSC_OR_RDIMM_DDR3
+    PSC_OR_SODIMM_DDR3
+    PSC_C32_UDIMM_DDR3
+    PSC_C32_RDIMM_DDR3
+    PSC_ON_UDIMM_DDR3
+    PSC_ON_RDIMM_DDR3
+    PSC_ON_SODIMM_DDR3
+    NULL
+  };
+  CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
+
+#else
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY MAP
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT NORTHBRIDGE SUPPORT LIST
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    #undef MEM_NB_SUPPORT_DR
+    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    #undef MEM_NB_SUPPORT_DA
+    #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    #undef MEM_NB_SUPPORT_HY
+    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    #undef MEM_NB_SUPPORT_C32
+    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
+  #endif
+  #if (OPTION_MEMCTLR_LN == TRUE)
+    #undef MEM_NB_SUPPORT_LN
+    #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
+  #endif
+  #if (OPTION_MEMCTLR_ON == TRUE)
+    #undef MEM_NB_SUPPORT_ON
+    #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
+  #endif
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT Technology Training
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if OPTION_DDR2
+    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
+      NULL
+    };
+  #endif
+  #if OPTION_DDR3
+    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
+      NULL
+    };
+  #endif
+    /*---------------------------------------------------------------------------------------------------
+     * DEFAULT Platform Specific list
+     *
+     *
+     *---------------------------------------------------------------------------------------------------
+     */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_LN == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_Or == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_ON == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+    NULL
+  };
+#endif
+
+/*---------------------------------------------------------------------------------------------------
+ * NORTHBRIDGE SUPPORT LIST
+ *
+ *
+ *---------------------------------------------------------------------------------------------------
+ */
+MEM_NB_SUPPORT memNBInstalled[] = {
+  MEM_NB_SUPPORT_DR
+  MEM_NB_SUPPORT_DA
+  MEM_NB_SUPPORT_HY
+  MEM_NB_SUPPORT_LN
+  MEM_NB_SUPPORT_OR
+  MEM_NB_SUPPORT_C32
+  MEM_NB_SUPPORT_ON
+  MEM_NB_SUPPORT_END
+};
+
+#endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryRecovery.h
new file mode 100755
index 0000000000..dcddc5f59e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryRecovery.h
@@ -0,0 +1,62 @@
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_RECOVERY_H_
+#define _OPTION_MEMORY_RECOVERY_H_
+
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+
+typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_REC_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryRecoveryInstall.h
new file mode 100755
index 0000000000..e5db0f1d2b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMemoryRecoveryInstall.h
@@ -0,0 +1,132 @@
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
+#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
+
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+
+  #define MEM_REC_NB_SUPPORT_OR
+
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
+    #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
+  #else
+    #define MEM_REC_NB_SUPPORT_DR
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
+    #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
+  #else
+    #define MEM_REC_NB_SUPPORT_DA
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
+    #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
+  #else
+    #define MEM_REC_NB_SUPPORT_HY
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
+    #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
+  #else
+    #define MEM_REC_NB_SUPPORT_C32
+  #endif
+  #if (OPTION_MEMCTLR_LN == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
+    #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
+  #else
+    #define MEM_REC_NB_SUPPORT_LN
+  #endif
+  #if (OPTION_MEMCTLR_ON == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
+    #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
+  #else
+    #define MEM_REC_NB_SUPPORT_ON
+  #endif
+
+  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
+    MEM_REC_NB_SUPPORT_DR
+    MEM_REC_NB_SUPPORT_DA
+    MEM_REC_NB_SUPPORT_HY
+    MEM_REC_NB_SUPPORT_C32
+    MEM_REC_NB_SUPPORT_LN
+    MEM_REC_NB_SUPPORT_OR
+    MEM_REC_NB_SUPPORT_ON
+    {0, NULL, NULL, NULL, NULL, NULL,},
+  };
+
+  #define MEM_REC_TECH_CONSTRUCTOR_DDR2
+  #if (OPTION_DDR3 == TRUE)
+    extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
+    #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
+  #else
+    #define MEM_REC_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+  MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
+    MEM_REC_TECH_CONSTRUCTOR_DDR3
+    MEM_REC_TECH_CONSTRUCTOR_DDR2
+    NULL
+  };
+#else
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {    // Types of technology installed
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT NORTHBRIDGE SUPPORT LIST
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_NB_SUPPORT MemRecNBInstalled[] = {
+    {0, NULL, NULL, NULL, NULL, NULL,},
+  };
+#endif
+#endif  // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMsgBasedC1eInstall.h
new file mode 100755
index 0000000000..58b04efb47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMsgBasedC1eInstall.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * Install of build option: Message-Based C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
+#define _OPTION_MSG_BASED_C1E_INSTALL_H_
+
+#include "cpuMsgBasedC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_MSG_BASED_C1E_FEAT
+#define F10_MSG_BASED_C1E_SUPPORT
+#if OPTION_MSG_BASED_C1E == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_HY == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
+          #undef OPTION_MSG_BASED_C1E_FEAT
+          #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
+          extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
+          #undef F10_MSG_BASED_C1E_SUPPORT
+          #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
+        #endif
+      #endif
+    #endif
+    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
+    {
+      F10_MSG_BASED_C1E_SUPPORT
+      {0, NULL}
+    };
+    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
+    {
+      (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+      &MsgBasedC1eFamilyServiceArray[0]
+    };
+  #endif
+#endif
+
+#endif  // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/f10/Include/OptionMultiSocket.h
new file mode 100755
index 0000000000..82c3860b30
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMultiSocket.h
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * AMD Multi-socket option API.
+ *
+ * Contains structures and values used to control the multi-socket option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MULTISOCKET_H_
+#define _OPTION_MULTISOCKET_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * This function loops through all possible socket locations, gathering the number
+ * of power management steps each populated socket requires, and returns the
+ * highest number.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_PM_STEPS (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, starting core 0 of
+ * each populated socket to perform the passed in AP_TASK.  After starting all
+ * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by
+ * the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
+  IN       VOID *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+/**
+ * This function loops through all possible socket locations, comparing the
+ * maximum NB frequencies to determine the slowest.  This function also
+ * determines if all coherent NB frequencies are equivalent.
+ *
+ * @param[out] SystemNbCof       NB frequency for the system in MHz
+ * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef AGESA_STATUS OPTION_MULTISOCKET_PM_NB_COF (
+     OUT   UINT32 *SystemNbCof,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, checking whether
+ * any populated sockets require NB COF VID programming.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, collecting any
+ * power management initialization errors that may have occurred.  These errors
+ * are transferred from the core 0s of the socket in which the errors occurred
+ * to the BSC's heap.  The BSC's heap is then searched for the most severe error
+ * that occurred, and returns it.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#define MULTISOCKET_STRUCT_VERSION  0x01
+
+/**
+ * Provide build configuration of cpu multi-socket or single socket support.
+ *
+ */
+typedef struct  {
+  UINT16              OptMultiSocketVersion;                       ///< Table version
+  OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps;           ///< Method: Get number of power mgt tasks
+  OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s;   ///< Method: Perform tasks on Core 0 of each processor
+  OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbCof;                    ///< Method: Find the limiting Northbridge frequency in the system.
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate;    ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
+  OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors;  ///< Method: Gathers error information from all Core 0s.
+} OPTION_MULTISOCKET_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_MULTISOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionMultiSocketInstall.h
new file mode 100755
index 0000000000..a29f283728
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionMultiSocketInstall.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * Install of build option: Multiple Socket Support
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MULTISOCKET_INSTALL_H_
+#define _OPTION_MULTISOCKET_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#ifndef OPTION_MULTISOCKET
+  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+
+#if OPTION_MULTISOCKET == TRUE
+  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
+  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrMulti
+  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
+  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sMulti
+  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
+  #define GET_SYS_NB_COF      GetSystemNbCofMulti
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
+  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
+  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
+  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
+#else
+  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
+  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrSingle
+  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
+  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sSingle
+  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
+  #define GET_SYS_NB_COF      GetSystemNbCofSingle
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
+  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
+  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
+  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
+#endif
+
+/*  Declare the instance of the DMI option configuration structure  */
+OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
+  MULTISOCKET_STRUCT_VERSION,
+  GET_NUM_PM_STEPS,
+  CORE0_PM_TASK,
+  GET_SYS_NB_COF,
+  GET_SYS_NB_COF_UPDATE,
+  GET_EARLY_PM_ERRORS
+};
+
+#endif  // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionNileMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionNileMicrocodeInstall.h
new file mode 100755
index 0000000000..a50f8ae8e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionNileMicrocodeInstall.h
@@ -0,0 +1,63 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a Nile platform solution
+ *
+ * This file generates the defaults tables for the "Nile" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_NILE_MICROCODE_INSTALL_H_
+#define _OPTION_NILE_MICROCODE_INSTALL_H_
+
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6;
+
+// 'NULL' must be put at the end of MicroCodePatchArray[]
+CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000b6,
+  NULL
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionPreserveMailboxInstall.h
new file mode 100755
index 0000000000..4b7d16dd05
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionPreserveMailboxInstall.h
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * Install of build option: Preserve Mailbox
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
+#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
+
+#include "PreserveMailbox.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_PRESERVE_MAILBOX_FEAT
+#define F10_PRESERVE_MAILBOX_SUPPORT
+#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
+      #undef OPTION_PRESERVE_MAILBOX_FEAT
+      #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
+      CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = {
+        {MAKE_SBDFO (0, 0, 0, 3, 0x168)},
+        {MAKE_SBDFO (0, 0, 0, 3, 0x170)},
+        {ILLEGAL_SBDFO}
+      };
+      CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
+        0,
+        TRUE,
+        (PCI_ADDR *)&F10PreserveMailboxRegisters
+      };
+      #undef F10_PRESERVE_MAILBOX_SUPPORT
+      #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
+    #endif
+  #endif
+  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
+  {
+    F10_PRESERVE_MAILBOX_SUPPORT
+    {0, NULL}
+  };
+  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
+  {
+    (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+    &PreserveMailboxFamilyServiceArray[0]
+  };
+#endif
+
+#endif  // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f10/Include/OptionPstate.h
new file mode 100755
index 0000000000..1220701817
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionPstate.h
@@ -0,0 +1,103 @@
+/**
+ * @file
+ *
+ * AMD ACPI PState option API.
+ *
+ * Contains structures and values used to control the PStates option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_PSTATE_H_
+#define _OPTION_PSTATE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_PSTATE_FEATURE (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **AcpiPstatePtr
+  );
+
+typedef AGESA_STATUS OPTION_PSTATE_GATHER (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#define PSTATE_STRUCT_VERSION  0x01
+
+/// Indirection vectors for POST/PEI PState code
+typedef struct  {
+  UINT16                  OptPstateVersion;     ///< revision of this structure
+  OPTION_PSTATE_GATHER    *PstateGather;        ///< vector for data gathering routine
+  OPTION_PSTATE_LEVELING  *PstateLeveling;      ///< vector for leveling routine
+} OPTION_PSTATE_POST_CONFIGURATION;
+
+/// Indirection vectors for LATE/DXE PState code
+typedef struct  {
+  UINT16                  OptPstateVersion;     ///< revision of this structure
+  OPTION_PSTATE_FEATURE   *PstateFeature;       ///< vector for main routine
+  BOOLEAN                 CfgPstatePpc;         ///< boolean for creating _PPC method
+  BOOLEAN                 CfgPstatePct;         ///< boolean for creating _PCT method
+  BOOLEAN                 CfgPstatePsd;         ///< boolean for creating _PSD method
+  BOOLEAN                 CfgPstatePss;         ///< boolean for creating _PSS method
+  BOOLEAN                 CfgPstateXpss;        ///< boolean for creating _XPSS method
+} OPTION_PSTATE_LATE_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionPstateInstall.h
new file mode 100755
index 0000000000..51bc0db4d7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionPstateInstall.h
@@ -0,0 +1,209 @@
+/**
+ * @file
+ *
+ * Install of build option: PState
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PSTATE_INSTALL_H_
+#define _OPTION_PSTATE_INSTALL_H_
+
+#include "cpuPstateTables.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define F10_PSTATE_SERVICE_SUPPORT
+#define F12_PSTATE_SERVICE_SUPPORT
+#define F14_PSTATE_SERVICE_SUPPORT
+#define F15_PSTATE_SERVICE_SUPPORT
+
+#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
+  //
+  //Define Pstate CPU Family service
+  //
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
+      #undef F10_PSTATE_SERVICE_SUPPORT
+      #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY12H
+    #if OPTION_FAMILY12H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
+      #undef F12_PSTATE_SERVICE_SUPPORT
+      #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY14H
+    #if OPTION_FAMILY14H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
+      #undef F14_PSTATE_SERVICE_SUPPORT
+      #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY15H
+    #if OPTION_FAMILY15H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices;
+      #undef F15_PSTATE_SERVICE_SUPPORT
+      #define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices},
+    #endif
+  #endif
+  //
+  //Define ACPI Pstate objects.
+  //
+  #ifndef OPTION_ACPI_PSTATES
+    #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
+  #endif
+  #if OPTION_ACPI_PSTATES == TRUE
+    #ifndef OPTION_MULTISOCKET
+      #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+    #endif
+
+    OPTION_PSTATE_FEATURE             CreateAcpiTablesMain;
+    OPTION_PSTATE_GATHER              PStateGatherMain;
+    #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
+      OPTION_PSTATE_LEVELING          PStateLevelingMain;
+      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingMain
+    #else
+      OPTION_PSTATE_LEVELING            PStateLevelingStub;
+      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+    #endif
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesMain
+    #else
+      OPTION_PSTATE_FEATURE             CreateAcpiTablesStub;
+      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #endif
+    #if AGESA_ENTRY_INIT_POST == TRUE
+      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
+    #else
+      OPTION_PSTATE_GATHER              PStateGatherStub;
+      #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+    #endif
+    #if CFG_ACPI_PSTATES_PPC == TRUE
+      #define USER_PSTATE_CFG_PPC   TRUE
+    #else
+      #define USER_PSTATE_CFG_PPC   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PCT == TRUE
+      #define USER_PSTATE_CFG_PCT   TRUE
+    #else
+      #define USER_PSTATE_CFG_PCT   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PSD == TRUE
+      #define USER_PSTATE_CFG_PSD   TRUE
+    #else
+      #define USER_PSTATE_CFG_PSD   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PSS == TRUE
+      #define USER_PSTATE_CFG_PSS   TRUE
+    #else
+      #define USER_PSTATE_CFG_PSS   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_XPSS == TRUE
+      #define USER_PSTATE_CFG_XPSS   TRUE
+    #else
+      #define USER_PSTATE_CFG_XPSS   FALSE
+    #endif
+
+  #else
+    OPTION_PSTATE_FEATURE             CreateAcpiTablesStub;
+    OPTION_PSTATE_GATHER              PStateGatherStub;
+    OPTION_PSTATE_LEVELING            PStateLevelingStub;
+    #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+    #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+    #define USER_PSTATE_CFG_PPC    FALSE
+    #define USER_PSTATE_CFG_PCT    FALSE
+    #define USER_PSTATE_CFG_PSD    FALSE
+    #define USER_PSTATE_CFG_PSS    FALSE
+    #define USER_PSTATE_CFG_XPSS   FALSE
+  #endif
+#else
+  OPTION_PSTATE_FEATURE             CreateAcpiTablesStub;
+  OPTION_PSTATE_GATHER              PStateGatherStub;
+  OPTION_PSTATE_LEVELING            PStateLevelingStub;
+  #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+  #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+  #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+  #define USER_PSTATE_CFG_PPC    FALSE
+  #define USER_PSTATE_CFG_PCT    FALSE
+  #define USER_PSTATE_CFG_PSD    FALSE
+  #define USER_PSTATE_CFG_PSS    FALSE
+  #define USER_PSTATE_CFG_XPSS   FALSE
+#endif
+
+/*  Declare the instance of the PSTATE option configuration structure  */
+OPTION_PSTATE_POST_CONFIGURATION      OptionPstatePostConfiguration = {
+  PSTATE_STRUCT_VERSION,
+  USER_PSTATE_OPTION_GATHER,
+  USER_PSTATE_OPTION_LEVEL
+};
+
+OPTION_PSTATE_LATE_CONFIGURATION      OptionPstateLateConfiguration = {
+  PSTATE_STRUCT_VERSION,
+  USER_PSTATE_OPTION_MAIN,
+  USER_PSTATE_CFG_PPC,
+  USER_PSTATE_CFG_PCT,
+  USER_PSTATE_CFG_PSD,
+  USER_PSTATE_CFG_PSS,
+  USER_PSTATE_CFG_XPSS
+};
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
+{
+  F10_PSTATE_SERVICE_SUPPORT
+  F12_PSTATE_SERVICE_SUPPORT
+  F14_PSTATE_SERVICE_SUPPORT
+  F15_PSTATE_SERVICE_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
+{
+  (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &PstateCpuFamilyServiceArray[0]
+};
+#endif  // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionS3ScriptInstall.h
new file mode 100755
index 0000000000..ec47b98b2e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionS3ScriptInstall.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * Install of build option: S3SCRIPT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_S3SCRIPT_INSTALL_H_
+#define _OPTION_S3SCRIPT_INSTALL_H_
+
+#include "S3SaveState.h"
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#ifndef OPTION_S3SCRIPT
+  #define OPTION_S3SCRIPT  FALSE    //if not define assume PI not use script
+#endif
+
+#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  #if OPTION_S3SCRIPT == TRUE
+    #define P_S3_SCRIPT_INIT      S3ScriptInitState
+  #endif
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+  #if OPTION_S3SCRIPT == TRUE
+    #define P_S3_SCRIPT_RESTORE   S3ScriptRestoreState
+  #endif
+#endif
+
+#ifndef P_S3_SCRIPT_INIT
+  #define P_S3_SCRIPT_INIT        S3ScriptInitStateStub
+#endif
+
+#ifndef P_S3_SCRIPT_RESTORE
+  #define P_S3_SCRIPT_RESTORE     S3ScriptInitStateStub
+#endif
+
+/*  Declare the instance of the S3SCRIPT option configuration structure  */
+S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
+  P_S3_SCRIPT_INIT,
+  P_S3_SCRIPT_RESTORE
+};
+
+#endif  // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h
new file mode 100755
index 0000000000..3168fd62f8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionSanMarinoMicrocodeInstall.h
@@ -0,0 +1,60 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a SanMarino platform solution
+ *
+ * This file generates the defaults tables for the "SanMarino" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SANMARINO_MICROCODE_INSTALL_H_
+#define _OPTION_SANMARINO_MICROCODE_INSTALL_H_
+
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
+
+// 'NULL' must be put at the end of MicroCodePatchArray[]
+CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch010000c4,
+  &CpuF10MicrocodePatch010000c5,
+  NULL
+};
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionSlit.h b/src/vendorcode/amd/agesa/f10/Include/OptionSlit.h
new file mode 100755
index 0000000000..30953d8bfc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionSlit.h
@@ -0,0 +1,96 @@
+/**
+ * @file
+ *
+ * AMD SLIT option API.
+ *
+ * Contains structures and values used to control the SLIT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_SLIT_H_
+#define _OPTION_SLIT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Create the ACPI System Locality Distance Information Table.
+ *
+ */
+typedef AGESA_STATUS OPTION_SLIT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+
+/**
+ * Clean up DRAM used during SLIT creation.
+ *
+ */
+typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define SLIT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of SLIT
+typedef struct  {
+  UINT16              OptSlitVersion;       ///< The version number of SLIT
+  OPTION_SLIT_FEATURE  *SlitFeature;        ///< The Option Feature of SLIT
+  OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
+} OPTION_SLIT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_SLIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionSlitInstall.h
new file mode 100755
index 0000000000..319620d819
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionSlitInstall.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * Install of build option: SLIT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SLIT_INSTALL_H_
+#define _OPTION_SLIT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_SLIT
+    #error  BLDOPT: Option not defined: "OPTION_SLIT"
+  #endif
+  #if OPTION_SLIT == TRUE
+    OPTION_SLIT_FEATURE               GetAcpiSlitMain;
+    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBuffer;
+    #define USER_SLIT_OPTION     GetAcpiSlitMain
+    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
+  #else
+    OPTION_SLIT_FEATURE               GetAcpiSlitStub;
+    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
+    #define USER_SLIT_OPTION     GetAcpiSlitStub
+    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
+  #endif
+#else
+  OPTION_SLIT_FEATURE               GetAcpiSlitStub;
+  OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
+  #define USER_SLIT_OPTION     GetAcpiSlitStub
+  #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
+#endif
+/*  Declare the instance of the SLIT option configuration structure  */
+OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
+  SLIT_STRUCT_VERSION,
+  USER_SLIT_OPTION,
+  USER_SLIT_RELEASE_BUFFER
+};
+
+#endif  // _OPTION_SLIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionSrat.h b/src/vendorcode/amd/agesa/f10/Include/OptionSrat.h
new file mode 100755
index 0000000000..0a6d820687
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionSrat.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * AMD SRAT option API.
+ *
+ * Contains structures and values used to control the SRAT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_SRAT_H_
+#define _OPTION_SRAT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_SRAT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+
+#define SRAT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of SRAT
+typedef struct  {
+  UINT16              OptSratVersion;       ///< The version number of SRAT
+  OPTION_SRAT_FEATURE  *SratFeature;        ///< The Option Feature of SRAT
+} OPTION_SRAT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_SRAT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionSratInstall.h
new file mode 100755
index 0000000000..1c94b1594a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionSratInstall.h
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * Install of build option: SRAT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SRAT_INSTALL_H_
+#define _OPTION_SRAT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_SRAT
+    #error  BLDOPT: Option not defined: "OPTION_SRAT"
+  #endif
+  #if OPTION_SRAT == TRUE
+    OPTION_SRAT_FEATURE          GetAcpiSratMain;
+    #define USER_SRAT_OPTION     GetAcpiSratMain
+  #else
+    OPTION_SRAT_FEATURE          GetAcpiSratStub;
+    #define USER_SRAT_OPTION     GetAcpiSratStub
+  #endif
+#else
+  OPTION_SRAT_FEATURE            GetAcpiSratStub;
+  #define USER_SRAT_OPTION       GetAcpiSratStub
+#endif
+
+/*  Declare the instance of the WHEA option configuration structure  */
+OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
+  SRAT_STRUCT_VERSION,
+  USER_SRAT_OPTION
+};
+
+#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h
new file mode 100755
index 0000000000..1d69456127
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionTigrisMicrocodeInstall.h
@@ -0,0 +1,65 @@
+/**
+ * @file
+ *
+ * Install microcode build options for a Tigris platform solution
+ *
+ * This file generates the defaults tables for the "Tigris" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_TIGRIS_MICROCODE_INSTALL_H_
+#define _OPTION_TIGRIS_MICROCODE_INSTALL_H_
+
+extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000098;
+
+// 'NULL' must be put at the end of MicroCodePatchArray[]
+CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch01000098,
+  NULL
+};
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+{
+  &CpuF10MicrocodePatch01000098,
+  NULL
+};
+
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionWhea.h b/src/vendorcode/amd/agesa/f10/Include/OptionWhea.h
new file mode 100755
index 0000000000..b1a08bc6bb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionWhea.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * AMD WHEA option API.
+ *
+ * Contains structures and values used to control the WHEA option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2008-04-25 03:59:36 -0700 (Fri, 25 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_WHEA_H_
+#define _OPTION_WHEA_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_WHEA_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+#define WHEA_STRUCT_VERSION  0x01
+
+/// The Option Configuration of WHEA
+typedef struct  {
+  UINT16              OptWheaVersion;       ///< The version number of WHEA
+  OPTION_WHEA_FEATURE  *WheaFeature;        ///< The Option Feature of WHEA
+} OPTION_WHEA_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_WHEA_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionWheaInstall.h
new file mode 100755
index 0000000000..4cea069184
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionWheaInstall.h
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * Install of build option: WHEA
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_WHEA_INSTALL_H_
+#define _OPTION_WHEA_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_WHEA
+    #error  BLDOPT: Option not defined: "OPTION_WHEA"
+  #endif
+  #if OPTION_WHEA == TRUE
+    OPTION_WHEA_FEATURE          GetAcpiWheaMain;
+    #define USER_WHEA_OPTION     GetAcpiWheaMain
+  #else
+    OPTION_WHEA_FEATURE          GetAcpiWheaStub;
+    #define USER_WHEA_OPTION     GetAcpiWheaStub
+  #endif
+
+#else
+  OPTION_WHEA_FEATURE            GetAcpiWheaStub;
+  #define USER_WHEA_OPTION       GetAcpiWheaStub
+#endif
+
+/*  Declare the instance of the WHEA option configuration structure  */
+OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
+  WHEA_STRUCT_VERSION,
+  USER_WHEA_OPTION
+};
+
+#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/Options.h b/src/vendorcode/amd/agesa/f10/Include/Options.h
new file mode 100755
index 0000000000..ce899a5c39
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/Options.h
@@ -0,0 +1,203 @@
+/**
+ * @file
+ *
+ * AGESA options structures
+ *
+ * Contains options control structures for the AGESA build options
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6104 $   @e \$Date: 2008-05-19 06:54:08 -0500 (Mon, 19 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+
+#ifndef _OPTIONS_H_
+#define _OPTIONS_H_
+
+/**
+ * Provide topology limits for loops and runtime, based on supported families.
+ */
+typedef struct {
+  UINT32              PlatformNumberOfSockets;                  ///< The limit to the number of processors based on
+                                                                ///< supported families and other build options.
+  UINT32              PlatformNumberOfModules;                  ///< The limit to the number of modules in a processor, based
+                                                                ///< on supported families.
+} OPTIONS_CONFIG_TOPOLOGY;
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+  UINT32              FunctionId;                   ///< The function id specified.
+  IMAGE_ENTRY         EntryPoint;                   ///< The corresponding entry point to call.
+} DISPATCH_TABLE;
+
+/*
+ * Platform common build option and configuration processing.
+ *
+ * Defaults selection goes into the platform install .h file.  If the default is
+ * not platform specific, it goes here.
+ *
+ */
+
+  // HT Configuration
+
+#ifdef BLDCFG_STARTING_BUSNUM
+  #define CFG_STARTING_BUSNUM         (BLDCFG_STARTING_BUSNUM)
+#else
+  #define CFG_STARTING_BUSNUM         (0)
+#endif
+
+#ifdef BLDCFG_MAXIMUM_BUSNUM
+  #define CFG_MAXIMUM_BUSNUM          (BLDCFG_MAXIMUM_BUSNUM)
+#else
+  #define CFG_MAXIMUM_BUSNUM          (0xF8)
+#endif
+
+#ifdef BLDCFG_ALLOCATED_BUSNUM
+  #define CFG_ALLOCATED_BUSNUM        (BLDCFG_ALLOCATED_BUSNUM)
+#else
+  #define CFG_ALLOCATED_BUSNUM        (0x20)
+#endif
+
+#ifdef BLDCFG_BUID_SWAP_LIST
+  #define CFG_BUID_SWAP_LIST         (BLDCFG_BUID_SWAP_LIST)
+#else
+  #define CFG_BUID_SWAP_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
+  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
+#else
+  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
+  #define CFG_HTFABRIC_LIMITS_LIST         (BLDCFG_HTFABRIC_LIMITS_LIST)
+#else
+  #define CFG_HTFABRIC_LIMITS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
+  #define CFG_HTCHAIN_LIMITS_LIST         (BLDCFG_HTCHAIN_LIMITS_LIST)
+#else
+  #define CFG_HTCHAIN_LIMITS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_BUS_NUMBERS_LIST
+  #define CFG_BUS_NUMBERS_LIST         (BLDCFG_BUS_NUMBERS_LIST)
+#else
+  #define CFG_BUS_NUMBERS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_IGNORE_LINK_LIST
+  #define CFG_IGNORE_LINK_LIST         (BLDCFG_IGNORE_LINK_LIST)
+#else
+  #define CFG_IGNORE_LINK_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
+  #define CFG_LINK_SKIP_REGANG_LIST         (BLDCFG_LINK_SKIP_REGANG_LIST)
+#else
+  #define CFG_LINK_SKIP_REGANG_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
+  #define CFG_SET_HTCRC_SYNC_FLOOD         (BLDCFG_SET_HTCRC_SYNC_FLOOD)
+#else
+  #define CFG_SET_HTCRC_SYNC_FLOOD         (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
+  #define CFG_USE_UNIT_ID_CLUMPING         (BLDCFG_USE_UNIT_ID_CLUMPING)
+#else
+  #define CFG_USE_UNIT_ID_CLUMPING         (FALSE)
+#endif
+
+#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
+  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
+#else
+  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_USE_HT_ASSIST
+  #define CFG_USE_HT_ASSIST               (BLDCFG_USE_HT_ASSIST)
+#else
+  #define CFG_USE_HT_ASSIST               (TRUE)
+#endif
+
+#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
+  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
+#else
+  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (Nfcm)
+#endif
+
+#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
+  #define CFG_PLATFORM_DEEMPHASIS_LIST  (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
+#else
+  #define CFG_PLATFORM_DEEMPHASIS_LIST  (NULL)
+#endif
+
+#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
+  #define CFG_VRM_ADDITIONAL_DELAY      (BLDCFG_VRM_ADDITIONAL_DELAY)
+#else
+  #define CFG_VRM_ADDITIONAL_DELAY      (0)
+#endif
+
+#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
+  #define CFG_PLATFORM_POWER_POLICY_MODE  (BLDCFG_PLATFORM_POWER_POLICY_MODE)
+#else
+  #define CFG_PLATFORM_POWER_POLICY_MODE  (Performance)
+#endif
+
+#ifdef BLDCFG_PCI_MMIO_BASE
+  #define CFG_PCI_MMIO_BASE               (BLDCFG_PCI_MMIO_BASE)
+#else
+  #define CFG_PCI_MMIO_BASE               (0)
+#endif
+
+#ifdef BLDCFG_PCI_MMIO_SIZE
+  #define CFG_PCI_MMIO_SIZE               (BLDCFG_PCI_MMIO_SIZE)
+#else
+  #define CFG_PCI_MMIO_SIZE               (0)
+#endif
+
+#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
+  #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
+#else
+  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
+#endif
+
+#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionsHt.h b/src/vendorcode/amd/agesa/f10/Include/OptionsHt.h
new file mode 100755
index 0000000000..06fb4d2eef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionsHt.h
@@ -0,0 +1,100 @@
+/**
+ * @file
+ *
+ * AMD HyperTransport option API.
+ *
+ * Contains option pre-compile logic.  This file is used by the options
+ * installer and internally by the HT code initializers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_HT_H_
+#define _OPTION_HT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Provide HT build option results
+ */
+typedef struct {
+  CONST BOOLEAN IsUsingRecoveryHt;                   ///< Manual BUID Swap List processing should assume that HT Recovery was used.
+  CONST BOOLEAN IsSetHtCrcFlood;                     ///< Enable setting of HT CRC Flood.
+                                                     ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
+  CONST BOOLEAN IsUsingUnitIdClumping;               ///< Enable automatically HT Spec compliant Unit Id Clumping.
+                                                     ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
+  CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults;  ///< A set of build time options for HT constructor.
+  CONST VOID *HtOptionInternalInterface;             ///< Use this internal interface initializer.
+  CONST VOID *HtOptionInternalFeatures;              ///< Use this internal feature set initializer.
+  CONST VOID *HtOptionFamilyNorthbridgeList;         ///< Use this list of northbridge initializers.
+  CONST UINT8 *CONST *HtOptionBuiltinTopologies;     ///< Use this list of built-in topologies.
+} OPTION_HT_CONFIGURATION;
+
+typedef AGESA_STATUS
+F_OPTION_HT_INIT_RESET (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
+
+/**
+ * Provide HT reset initialization build option results
+ */
+typedef struct {
+  PF_OPTION_HT_INIT_RESET HtInitReset;  ///< Method: HT reset initialization.
+} OPTION_HT_INIT_RESET;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_HT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionsPage.h b/src/vendorcode/amd/agesa/f10/Include/OptionsPage.h
new file mode 100755
index 0000000000..f6fa0d6be9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/OptionsPage.h
@@ -0,0 +1,283 @@
+/**
+ * @file
+ *
+ * Create outline and references for Build Configuration and Options Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page optionmain Build Configuration and Options Documentation
+ *
+ * Additional documentation for the Build Configuration and Options component consists of
+ *
+ * - Introduction and Overview to Build Options
+ *   - @subpage platforminstall "Platform Build Options"
+ *   - @subpage bldcfg "Build Configuration Item Cross Reference"
+ *   - @subpage examplecustomizations "Customization Examples"
+ * - Maintenance Guides:
+ *   -  For debug of the Options system, use compiler options
+ *      @n <tt>      /P /EP /C /FAs      </tt> @n
+ *      PreProcessor output is produced in an .i file in the directory where the project
+ *      file is located.
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+/**
+ * @page platforminstall Platform Build Options.
+ *
+ * Build options are boolean constants. The purpose of build options is to remove code
+ * from the build to reduce the overall code size present in the ROM image. Unless
+ * otherwise specified, the default action is to include all options. If a build option is
+ * not specifically listed as disabled, then it is included into the build.
+ *
+ * The documented build options are imported from a user controlled file for
+ * processing. The build options for all platform solutions are listed below:
+ *
+ * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
+ * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
+ *        If unbuffered DIMMs are NOT expected to be required in the system, the code that
+ *        handles unbuffered DIMMs can be removed from the build.
+ *
+ * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
+ * @li @e  BLDOPT_REMOVE_RDIMMS_SUPPORT @n
+ *         If registered DIMMs are NOT expected to be required in the system, the code
+ *         that handles registered DIMMs can be removed from the build.
+ *
+ *     @note The above two options operate independently from each other; however, at
+ *     least one of the unbuffered or registered options must be present in the build.
+ *
+ * @anchor BLDOPT_REMOVE_ECC_SUPPORT
+ * @li @e  BLDOPT_REMOVE_ECC_SUPPORT @n
+ *         Use this option to remove the code for Error Checking & Correction.
+ *
+ * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
+ * @li @e  BLDOPT_REMOVE_BANK_INTERLEAVE @n
+ *         Interleaving is a mechanism to do performance fine tuning. This option
+ *         interleaves memory between banks on a DIMM.
+ *
+ * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
+ * @li @e  BLDOPT_REMOVE_DCT_INTERLEAVE @n
+ *         Interleaving is a mechanism to do performance fine tuning. This option
+ *         interleaves memory from two DRAM controllers.
+ *
+ * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
+ * @li @e  BLDOPT_REMOVE_NODE_INTERLEAVE @n
+ *         Interleaving is a mechanism to do performance fine tuning. This option
+ *         interleaves memory from two HyperTransport nodes.
+ *
+ * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
+ * @li @e  BLDOPT_REMOVE_PARALLEL_TRAINING @n
+ *         For multi-socket systems, training memory in parallel can reduce the time
+ *         needed to boot.
+ *
+ * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+ * @li @e  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
+ *         Online Spare support is removed by this option.
+ *
+ * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+ * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
+ *        Many systems use only a single socket and may benefit in code space to remove
+ *        this code. However, certain processors have multiple HyperTransport nodes
+ *        within a single socket. For these processors, the multi-node support is
+ *        required and this option has no effect.
+ *
+ * @anchor BLDOPT_REMOVE_ACPI_PSTATES
+ * @li @e  BLDOPT_REMOVE_ACPI_PSTATES @n
+ *         This option removes the code that generates the ACPI tables used in power
+ *         management.
+ *
+ * @anchor BLDOPT_REMOVE_SRAT
+ * @li @e  BLDOPT_REMOVE_SRAT @n
+ *         This option removes the code that generates the SRAT tables used in performance
+ *         tuning.
+ *
+ * @anchor BLDOPT_REMOVE_SLIT
+ * @li @e  BLDOPT_REMOVE_SLIT @n
+ *         This option removes the code that generates the SLIT tables used in performance
+ *         tuning.
+ *
+ * @anchor BLDOPT_REMOVE_WHEA
+ * @li @e  BLDOPT_REMOVE_WHEA @n
+ *         This option removes the code that generates the WHEA tables used in error
+ *         handling and reporting.
+ *
+ * @anchor BLDOPT_REMOVE_DMI
+ * @li @e  BLDOPT_REMOVE_DMI @n
+ *         This option removes the code that generates the DMI tables used in system
+ *         management.
+ *
+ * @anchor BLDOPT_REMOVE_DQS_TRAINING
+ * @li @e  BLDOPT_REMOVE_DQS_TRAINING @n
+ *         This option removes the code used in memory performance tuning.
+ *
+ * @anchor BLDOPT_REMOVE_EARLY_SAMPLES
+ * @li @e  BLDOPT_REMOVE_EARLY_SAMPLES @n
+ *         Special support for Early Samples is included. Default setting is FALSE.
+ *
+ * @anchor BLDOPT_REMOVE_HT_ASSIST
+ * @li @e  BLDOPT_REMOVE_HT_ASSIST @n
+ *         This option removes the code which implements the HT Assist feature.
+ *
+ * @anchor BLDOPT_REMOVE_MSG_BASED_C1E
+ * @li @e  BLDOPT_REMOVE_MSG_BASED_C1E @n
+ *         This option removes the code which implements the Message Based C1e feature.
+ *
+ * @anchor BLDOPT_REMOVE_C6_STATE
+ * @li @e  BLDOPT_REMOVE_C6_STATE @n
+ *         This option removes the code which implements the C6 C-state feature.
+ *
+ * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+ * @li @e  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
+ *         This option removes the memory context restore feature.
+ *
+ */
+
+/**
+ * @page examplecustomizations Customization Examples
+ *
+ * The Addendum \<plat\>Options.c file for each platform contains the minimum required
+ * customizations for that platform.  That is, it contains settings which would be needed
+ * to boot a SimNow! bsd for that platform.
+ * However, each individual product based on that platform will have customizations necessary for
+ * that hardware.  Since the actual customizations needed vary so much, they are not included in
+ * the \<plat\>Options.c.  This section provides examples of useful customizations that you can use or
+ * modify to suit your needs.
+ *
+ * @par
+ *
+ * Source for the examples shown can be found at Addendum\\Examples. @n
+ *
+ * - @ref DeemphasisExamples "Deemphasis List Examples"
+ * - @ref FrequencyLimitExamples "Frequency Limit Examples"
+ * - @ref PerfPerWattHt "A performance-per-watt optimization Example"
+ *
+ * @anchor DeemphasisExamples
+ * @par Deemphasis List Examples
+ *
+ * These examples customize ::PLATFORM_CONFIGURATION::PlatformDeemphasisList.
+ * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
+ * @dontinclude DeemphasisExamples.c
+ * <ul>
+ * <li>
+ *  The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
+ *  High Speed HT frequencies are supported.  There is only one non-coherent chain.  Note the technique of
+ *  putting specified link matches before all uses of match any.  It often works well to specify the non-coherent links
+ *  and use match any for the coherent links.
+ *  @skip DinarDeemphasisList
+ *  @until {
+ *  The non-coherent chain can run up to 2600 MHz.  The chain is located on Socket 0, package Link 2.
+ *  @until {
+ *  @line }
+ *  @line {
+ *  @line }
+ *  The coherent links can run up to 3200 MHz.
+ *  @until HT_FREQUENCY_MAX
+ *  @line }
+ *  end of list:
+ *  @until }
+ *  Make this list the build time customized deemphasis list.
+ *  @line define
+ *
+ * </li><li>
+ *
+ * The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
+ * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
+ * There can be one to four IO Chains, depending on the IO board.
+ * @skipline DoubloonDeemphasisList
+ * @until DoubloonDeemphasisList
+ *
+ * </ul>
+ *
+ * @anchor FrequencyLimitExamples
+ * @par Frequency Limit Examples
+ *
+ * These examples customize ::AMD_HT_INTERFACE::CpuToCpuPcbLimitsList and ::AMD_HT_INTERFACE::IoPcbLimitsList.
+ * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
+ * @dontinclude FrequencyLimitExamples.c
+ * <ul>
+ * <li>
+ *    The following list provides an example for limiting all coherent links to non-extended frequencies,
+ * that is, to 2600 MHz or less.
+ * @skipline NonExtendedCpuToCpuLimitList
+ * @until {
+ *   Provide the limit customization.  Match links from any socket, any package link, to any socket, any package link. Width is not limited.
+ * @until HT_FREQUENCY_LIMIT_2600M
+ * End of list:
+ * @until ;
+ * Customize the build to use this cpu to cpu frequency limit.
+ * @until NonExtendedCpuToCpuLimitList
+ * @n </li>
+ * <li>
+ *    The following list provides an example for limiting all coherent links to HT 1 frequencies,
+ * that is, to 1000 MHz or less.  This is sometimes useful for test and debug.
+ * @skipline Ht1CpuToCpuLimitList
+ * @until Ht1CpuToCpuLimitList
+ * @n </li>
+ * <li>
+ *    The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
+ *    The chain is matched by host processor Socket and package Link.  The depth can be used to select a particular device
+ *    to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
+ * @skipline No2600MhzIoLimitList
+ * @until No2600MhzIoLimitList
+ * @n </li>
+ * <li>
+ *    The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
+ * that is, to 1200 MHz or less.  This can be useful for test and debug.
+ * @skipline MinHt3IoLimitList
+ * @until MinHt3IoLimitList
+ * @n </li>
+ *
+ * </ul>
+ *
+ * @anchor PerfPerWattHt
+ * @par Performance-per-Watt Optimization Example
+ *
+ * This example customizes ::AMD_HT_INTERFACE::SkipRegangList.
+ * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
+ * @dontinclude PerfPerWatt.c
+ * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
+ * @skipline PerfPerWatt
+ * @until PerfPerWatt
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f10/Include/PlatformMemoryConfiguration.h
new file mode 100755
index 0000000000..702abda387
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/PlatformMemoryConfiguration.h
@@ -0,0 +1,303 @@
+/**
+ * @file
+ *
+ * AMD Platform Specific Memory Configuration
+ *
+ * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 5937 $   @e \$Date: 2009-12-02 03:59:36 -0700 (Wed, 02 Dec 2009) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
+#define _PLATFORM_MEMORY_CONFIGURATION_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+  #define PSO_ENTRY UINT8
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ *                 PLATFORM SPECIFIC MEMORY DEFINITIONS
+ *----------------------------------------------------------------------------------------
+ */
+///
+///  Memory Speed and DIMM Population Masks
+///
+///<  DDR Speed Masks
+///<    Specifies the DDR Speed on a memory channel
+///
+#define ANY_SPEED 0xFFFFFFFF
+#define DDR400  ((UINT32) 1 << (DDR400_FREQUENCY  / 66))
+#define DDR533  ((UINT32) 1 << (DDR533_FREQUENCY  / 66))
+#define DDR667  ((UINT32) 1 << (DDR667_FREQUENCY  / 66))
+#define DDR800  ((UINT32) 1 << (DDR800_FREQUENCY  / 66))
+#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
+#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
+#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
+#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
+///
+///<  DIMM POPULATION MASKS
+///<    Specifies the DIMM Population on a channel (can be added together to specify configuration).
+///<    ex. SR_DIMM0 + SR_DIMM1                       : Single Rank Dimm in slot 0 AND Slot 1
+///<        SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1  : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
+///
+#define ANY_       0xFF       ///< Any dimm configuration the current channel
+#define SR_DIMM0   0x0001     ///< Single rank dimm in slot 0 on the current channel
+#define SR_DIMM1   0x0010     ///< Single rank dimm in slot 1 on the current channel
+#define SR_DIMM2   0x0100     ///< Single rank dimm in slot 2 on the current channel
+#define SR_DIMM3   0x1000     ///< Single rank dimm in slot 3 on the current channel
+#define DR_DIMM0   0x0002     ///< Dual rank dimm in slot 0 on the current channel
+#define DR_DIMM1   0x0020     ///< Dual rank dimm in slot 1 on the current channel
+#define DR_DIMM2   0x0200     ///< Dual rank dimm in slot 2 on the current channel
+#define DR_DIMM3   0x2000     ///< Dual rank dimm in slot 3 on the current channel
+#define QR_DIMM0   0x0004     ///< Quad rank dimm in slot 0 on the current channel
+#define QR_DIMM1   0x0040     ///< Quad rank dimm in slot 1 on the current channel
+#define QR_DIMM2   0x0400     ///< Quad rank dimm in slot 2 on the current channel
+#define QR_DIMM3   0x4000     ///< Quad rank dimm in slot 3 on the current channel
+#define ANY_DIMM0   0x000F    ///< Any Dimm combination in slot 0 on the current channel
+#define ANY_DIMM1   0x00F0    ///< Any Dimm combination in slot 1 on the current channel
+#define ANY_DIMM2   0x0F00    ///< Any Dimm combination in slot 2 on the current channel
+#define ANY_DIMM3   0xF000    ///< Any Dimm combination in slot 3 on the current channel
+///
+///< Number of Dimms on the current channel
+///<   This is a mask used to indicate the number of dimms in a channel
+///<   They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
+///
+#define ANY_NUM     0xFF      ///< Any number of Dimms
+#define NO_DIMM     0x00      ///< No Dimms present
+#define ONE_DIMM    0x01      ///< One dimm Poulated on the current channel
+#define TWO_DIMM    0x02      ///< Two dimms Poulated on the current channel
+#define THREE_DIMM  0x04      ///< Three dimms Poulated on the current channel
+#define FOUR_DIMM   0x08      ///< Four dimms Poulated on the current channel
+
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Override Definitions for Socket, Channel and Dimm
+ * This indicates where a platform override will be applied.
+ *
+ *----------------------------------------------------------------------------------------
+ */
+///
+///< SOCKET MASKS
+///<   Indicates associated processor sockets to apply override settings
+///
+#define ANY_SOCKET     0xFF    ///<  Apply to all sockets
+#define SOCKET0        0x01    ///<  Apply to socket 0
+#define SOCKET1        0x02    ///<  Apply to socket 1
+#define SOCKET2        0x04    ///<  Apply to socket 2
+#define SOCKET3        0x08    ///<  Apply to socket 3
+#define SOCKET4        0x10    ///<  Apply to socket 4
+#define SOCKET5        0x20    ///<  Apply to socket 5
+#define SOCKET6        0x40    ///<  Apply to socket 6
+#define SOCKET7        0x80    ///<  Apply to socket 7
+///
+///< CHANNEL MASKS
+///<   Indicates Memory channels where override should be applied
+///
+#define ANY_CHANNEL    0xFF    ///<  Apply to all Memory channels
+#define CHANNEL_A      0x01    ///<  Apply to Channel A
+#define CHANNEL_B      0x02    ///<  Apply to Channel B
+#define CHANNEL_C      0x04    ///<  Apply to Channel C
+#define CHANNEL_D      0x08    ///<  Apply to Channel D
+///
+/// DIMM MASKS
+///   Indicates Dimm Slots where override should be applied
+///
+#define ALL_DIMMS      0xFF    ///<  Apply to all dimm slots
+#define DIMM0          0x01    ///<  Apply to Dimm Slot 0
+#define DIMM1          0x02    ///<  Apply to Dimm Slot 1
+#define DIMM2          0x04    ///<  Apply to Dimm Slot 2
+#define DIMM3          0x08    ///<  Apply to Dimm Slot 3
+///
+/// REGISTER ACCESS MASKS
+///   Not supported as an at this time
+///
+#define ACCESS_NB0     0x0
+#define ACCESS_NB1     0x1
+#define ACCESS_NB2     0x2
+#define ACCESS_NB3     0x3
+#define ACCESS_NB4     0x4
+#define ACCESS_PHY     0x5
+#define ACCESS_DCT_XT  0x6
+
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Overriding Table Definitions
+ *
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PSO_END           0     ///< Table End
+#define PSO_CKE_TRI       1     ///< CKE Tristate Map
+#define PSO_ODT_TRI       2     ///< ODT Tristate Map
+#define PSO_CS_TRI        3     ///< CS Tristate Map
+#define PSO_MAX_DIMMS     4     ///< Max Dimms per channel
+#define PSO_CLK_SPEED     5     ///< Clock Speed
+#define PSO_DIMM_TYPE     6     ///< Dimm Type
+#define PSO_MEMCLK_DIS    7     ///< MEMCLK Disable Map
+#define PSO_MAX_CHNLS     8     ///< Max Channels per Socket
+#define PSO_BUS_SPEED     9     ///< Max Memory Bus Speed
+#define PSO_MAX_CHIPSELS 10     ///< Max Chipsel per Channel
+#define PSO_MEM_TECH     11     ///< Channel Memory Type
+#define PSO_WL_SEED      12     ///< DDR3 Write Levelization Seed delay
+#define PSO_LVDIMM_VOLT1_5_SUPPORT 16     ///< Force LvDimm voltage to 1.5V
+
+/*----------------------------------
+ * CONDITIONAL PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition Types
+#define CONDITIONAL_PSO_MIN   100     ///< Start of Conditional Entry Types
+#define PSO_CONDITION_AND     100     ///< And Block - Start of Conditional block
+#define PSO_CONDITION_LOC     101     ///< Location - Specify Socket, Channel, Dimms to be affected
+#define PSO_CONDITION_SPD     102     ///< SPD - Specify a specific SPD value on a Dimm on the channel
+#define PSO_CONDITION_REG     103     //   Reserved
+#define PSO_CONDITION_MAX     103     ///< End Of Condition Entry Types
+// Action Types
+#define PSO_ACTION_MIN        120     ///< Start of Action Entry Types
+#define PSO_ACTION_ODT        120     ///< ODT values to override
+#define PSO_ACTION_ADDRTMG    121     ///< Address/Timing values to override
+#define PSO_ACTION_ODCCONTROL 122     ///< ODC Control values to override
+#define PSO_ACTION_SLEWRATE   123     ///< Slew Rate value to override
+#define PSO_ACTION_REG        124     //   Reserved
+#define PSO_ACTION_SPEEDLIMIT 125     ///< Memory Bus speed Limit based on configuration
+#define PSO_ACTION_MAX        125     ///< End of Action Entry Types
+#define CONDITIONAL_PSO_MAX   139     ///< End of Conditional Entry Types
+
+/*----------------------------------------------------------------------------------------
+ *                 CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+  PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
+
+#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
+  PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map
+
+#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+  PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+  PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
+
+#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
+  PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel
+
+#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
+  PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel
+
+#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
+  PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket
+
+#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
+  PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
+  BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
+
+#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
+  PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
+
+#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+  Byte6Seed, Byte7Seed, ByteEccSeed) \
+  PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+  Byte6Seed, Byte7Seed, ByteEccSeed
+
+#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
+  PSO_LVDIMM_VOLT1_5_SUPPORT, 3, ANY_SOCKET, ANY_CHANNEL, TRUE
+
+/*----------------------------------------------------------------------------------------
+ *                 CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CONDITION_AND \
+  PSO_CONDITION_AND, 0
+
+#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
+  PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
+
+#define COND_SPD(Byte, Mask, Value) \
+  PSO_CONDITION_SPD, 3, Byte, Mask, Value
+
+#define COND_REG(Access, Offset, Mask, Value) \
+ PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
+   ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
+   ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
+
+#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
+  PSO_ACTION_ODT, 9, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
+  Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
+
+#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
+  PSO_ACTION_ADDRTMG, 10, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
+
+#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
+  PSO_ACTION_ODCCONTROL, 10, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
+
+#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
+  PSO_ACTION_SLEWRATE, 10, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
+
+#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
+  PSO_ACTION_SPEEDLIMIT, 9, \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
+  (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
+  (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
+  (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
+
+/*----------------------------------------------------------------------------------------
+ *                 END OF CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _PLATFORM_MEMORY_CONFIGURATION_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/f10/Include/SanMarinoInstall.h
new file mode 100755
index 0000000000..55c69e6a77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/SanMarinoInstall.h
@@ -0,0 +1,1527 @@
+/**
+ * @file
+ *
+ * Install of build options for a SanMarino platform solution
+ *
+ * This file generates the defaults tables for the "SanMarino" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 15447 $   @e \$Date: 2009-06-20 06:22:00 +0800 (Sat, 20 Jun 2009) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#include  "AGESA.h"
+#include  "cpuRegisters.h"
+#include  "cpuFamRegisters.h"
+#include  "cpuFamilyTranslation.h"
+#include  "AdvancedApi.h"
+#include  "heapManager.h"
+#include  "CreateStruct.h"
+#include  "cpuFeatures.h"
+#include  "Table.h"
+#include  "CommonReturns.h"
+#include  "cpuEarlyInit.h"
+#include  "cpuLateInit.h"
+#include  "GnbInterfaceStub.h"
+
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "MarG34PI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'M', 'a', 'r', 'G', '3', '4', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '8', ' ', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  '0000',
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY10H                          TRUE
+#define OPTION_FAMILY10H_BL                       FALSE
+#define OPTION_FAMILY10H_DA                       FALSE
+#define OPTION_FAMILY10H_HY                       TRUE
+#define OPTION_FAMILY10H_RB                       FALSE
+
+#define OPTION_MEMCTLR_DR                         FALSE
+#define OPTION_MEMCTLR_HY                         FALSE
+#define OPTION_MEMCTLR_OR                         FALSE
+#define OPTION_MEMCTLR_C32                        TRUE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       TRUE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        TRUE
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     TRUE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              TRUE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   TRUE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      TRUE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          TRUE
+#define OPTION_PARALLEL_TRAINING        TRUE
+#define OPTION_ONLINE_SPARE             TRUE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     TRUE
+#define OPTION_SLIT                     TRUE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     FALSE
+#define OPTION_DDR3                     TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                TRUE
+#define OPTION_CPU_CORELEVLING          TRUE
+#define OPTION_CPU_CFOH                 TRUE
+#define OPTION_MSG_BASED_C1E            TRUE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                2500
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0xFF
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0x10
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0x10
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0x12
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G             BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G             FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   FALSE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE             FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily10h.h"
+#include  "OptionFamily10hBlInstall.h"
+#include  "OptionFamily10hDaInstall.h"
+#include  "OptionFamily10hHyInstall.h"
+#include  "OptionFamily10hRbInstall.h"
+#include  "OptionFamily10hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionSanMarinoMicrocodeInstall.h"
+#endif
+
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,         // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+  CPU_DMI_AP_GET_TYPE4_TYPE7
+  // Probe filter enable
+  HT_ASSIST_AP_DISABLE_CACHE
+  HT_ASSIST_AP_ENABLE_CACHE
+
+  { 0, NULL }
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+{
+  &F10BrandIdString1ArrayC32
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+{
+  &F10BrandIdString2ArrayC32
+};
+
+CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
diff --git a/src/vendorcode/amd/agesa/f10/Include/TigrisInstall.h b/src/vendorcode/amd/agesa/f10/Include/TigrisInstall.h
new file mode 100755
index 0000000000..eda118e0ba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/TigrisInstall.h
@@ -0,0 +1,1495 @@
+/**
+ * @file
+ *
+ * Install of build options for a Tigris platform solution
+ *
+ * This file generates the defaults tables for the "Tigris" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#include  "cpuRegisters.h"
+#include  "cpuFamRegisters.h"
+#include  "cpuFamilyTranslation.h"
+#include  "AdvancedApi.h"
+#include  "heapManager.h"
+#include  "CreateStruct.h"
+#include  "cpuFeatures.h"
+#include  "Table.h"
+#include  "CommonReturns.h"
+#include  "cpuEarlyInit.h"
+#include  "cpuLateInit.h"
+#include  "GnbInterfaceStub.h"
+
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
+extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "TigrisPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'T', 'i', 'g', 'r', 'i', 's', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
+
+//
+//Support multiple dll's per image for legacy BIOS only.
+//Platform BIOS may need to extern AmdAgesaDispatcher, if ModuleDispatcher is not NULL.
+//
+//extern AGESA_STATUS CALLCONV AmdAgesaDispatcher( VOID *);
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  '0000',
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+// Add logic for determining if the AP callout is required
+// by checking enabled entry points / enabled features that
+// may need them.  Leave the ifndef here in case the logic
+// does not define this equate.
+#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #define AGESA_ENTRY_LATE_RUN_AP_TASK               FALSE
+#endif
+
+#define OPTION_FAMILY10H                          TRUE
+#define OPTION_FAMILY10H_DA                       TRUE
+#define OPTION_FAMILY10H_BL                       TRUE
+#define OPTION_MEMCTLR_DA                         TRUE
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#define OPTION_HW_WRITE_LEV_TRAINING            TRUE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   TRUE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    TRUE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
+#define OPTION_MAX_RD_LAT_TRAINING              TRUE
+#define OPTION_HW_DRAM_INIT                     TRUE
+#define OPTION_SW_DRAM_INIT                     FALSE
+#define OPTION_S3_MEM_SUPPORT                   TRUE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_MULTISOCKET              TRUE
+#define OPTION_UDIMMS                   TRUE
+#define OPTION_RDIMMS                   TRUE
+#define OPTION_SODIMMS                  TRUE
+#define OPTION_ECC                      FALSE
+#define OPTION_BANK_INTERLEAVE          TRUE
+#define OPTION_DCT_INTERLEAVE           TRUE
+#define OPTION_NODE_INTERLEAVE          TRUE
+#define OPTION_PARALLEL_TRAINING        TRUE
+#define OPTION_ONLINE_SPARE             TRUE
+#define OPTION_MEM_RESTORE              TRUE
+#define OPTION_DIMM_EXCLUDE             TRUE
+#define OPTION_TABLE_SUPPORT            TRUE
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_SRAT                     TRUE
+#define OPTION_SLIT                     TRUE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_DDR2                     TRUE
+#define OPTION_DDR3                     FALSE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define OPTION_HT_ASSIST                FALSE
+#define OPTION_CPU_CORELEVLING          TRUE
+#define OPTION_CPU_CFOH                 TRUE
+#define OPTION_MSG_BASED_C1E            FALSE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                5000
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              QUADRANK_REGISTERED
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_BY_CHANNEL
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         0
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           0
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           0
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          0
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G             BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G             FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT must be FALSE.
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #error   BLDCFG: No dimm type is capable
+    #endif
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+              #error    BLDCFG: Unsupported memory bus frequency
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTables
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE             FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE   TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+// Initialize family mask for the PCI MMIO MSR to 0
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "OptionFamily10h.h"
+#include  "OptionFamily10hBlInstall.h"
+#include  "OptionFamily10hDaInstall.h"
+#include  "OptionFamily10hHyInstall.h"
+#include  "OptionFamily10hRbInstall.h"
+#include  "OptionFamily10hInstall.h"
+#include  "Options.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  #include  "OptionTigrisMicrocodeInstall.h"
+#endif
+
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+    CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+    CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+    CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+    CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+    CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,   // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+
+  0,                                    //reserved...
+};
+
+/// @todo, hmmm options.c override? multisocket == false?  Look broken.
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, NULL }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+#if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+  CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+  {
+    { 1, (IMAGE_ENTRY)AMDSetAPMsr },
+    // Get DMI info
+
+    // Probe filter enable
+
+    { 0, NULL }
+  };
+#endif
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+{
+  &F10BrandIdString1ArrayS1g3
+};
+
+CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+{
+  &F10BrandIdString2ArrayS1g3
+};
+
+CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
diff --git a/src/vendorcode/amd/agesa/f10/Include/Topology.h b/src/vendorcode/amd/agesa/f10/Include/Topology.h
new file mode 100755
index 0000000000..9b286a2d2e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/Topology.h
@@ -0,0 +1,160 @@
+/**
+ * @file
+ *
+ * Topology interface definitions.
+ *
+ * Contains AMD AGESA internal interface for topology related data which
+ * is consumed by code other than HyperTransport init (and produced by
+ * HyperTransport init.)
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _TOPOLOGY_H_
+#define _TOPOLOGY_H_
+
+// Defines for limiting data structure maximum allocation and limit checking.
+#define MAX_NODES 8
+#define MAX_SOCKETS MAX_NODES
+#define MAX_DIES 2
+
+// Defines useful with package link
+#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
+#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
+#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
+
+/**
+ * Hop Count Table.
+ * This is a heap data structure.  The Hops array is filled as a size x size matrix.
+ * The unused space, if any, is all at the end.
+ */
+typedef struct {
+  UINT8 Size;                         ///< The row and column size of actual hop count data */
+  UINT8 Hops[MAX_NODES * MAX_NODES];  ///< Room for a dynamic two dimensional array of [size][size] */
+} HOP_COUNT_TABLE;
+
+/**
+ * Socket and Module to Node Map Item.
+ * Provide the Node Id and core id range for each module in each processor.
+ */
+typedef struct {
+  UINT8 Node;                 ///< The module's Node id.
+  UINT8 LowCore;              ///< The lowest processor core id for this module.
+  UINT8 HighCore;             ///< The highest processor core id for this module.
+} SOCKET_DIE_TO_NODE_ITEM;
+
+/**
+ * Socket and Module to Node Map.
+ * This type is a pointer to the actual map, it can be used for a struct item or
+ * for typecasting a heap buffer pointer.
+ */
+typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
+
+/**
+ * Node id to Socket Die Map Item.
+ */
+typedef struct {
+  UINT8 Socket;             ///< socket of the processor containing the Node.
+  UINT8 Die;                ///< the module in the processor which is Node.
+} NODE_TO_SOCKET_DIE_ITEM;
+
+/**
+ * Node id to Socket Die Map.
+ */
+typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
+
+/**
+ * Provide AP core with socket and node context at start up.
+ * This information is posted to the AP cores using a register as a mailbox.
+ */
+typedef struct {
+  UINT32 Node:4;          ///< The node id of Core's node.
+  UINT32 Socket:4;        ///< The socket of this Core's node.
+  UINT32 Module:2;        ///< The internal module number for Core's node.
+  UINT32 ModuleType:2;    ///< Single Module = 0, Multi-module = 1.
+  UINT32 :20;             ///< Reserved
+} AP_MAIL_INFO_FIELDS;
+
+/**
+ * AP info fields can be written and read to a register.
+ */
+typedef union {
+  UINT32              Info;        ///< Just a number for register access, or opaque passing.
+  AP_MAIL_INFO_FIELDS Fields;      ///< access to the info fields.
+} AP_MAIL_INFO;
+
+/**
+ * Provide AP core with system degree and system core number at start up.
+ * This information is posted to the AP cores using a register as a mailbox.
+ */
+typedef struct {
+  UINT32 SystemDegree:3;  ///< The number of connected links
+  UINT32 :3;              ///< Reserved
+  UINT32 HeapIndex:6;     ///< The zero-based system core number
+  UINT32 :20;             ///< Reserved
+} AP_MAIL_EXT_INFO_FIELDS;
+
+/**
+ * AP info fields can be written and read to a register.
+ */
+typedef union {
+  UINT32              Info;        ///< Just a number for register access, or opaque passing.
+  AP_MAIL_EXT_INFO_FIELDS Fields;  ///< access to the info fields.
+} AP_MAIL_EXT_INFO;
+
+/**
+ * AP Info mailbox set.
+ */
+typedef struct {
+  AP_MAIL_INFO      ApMailInfo;    ///< The AP mail info
+  AP_MAIL_EXT_INFO  ApMailExtInfo; ///< The extended AP mail info
+} AP_MAILBOXES;
+
+/**
+ * Provide a northbridge to package mapping for link assignments.
+ *
+ */
+typedef struct {
+  UINT8  Link;             ///< The Node's link
+  UINT8  Module;           ///< The internal module position of Node
+  UINT8  PackageLink;      ///< The corresponding package link
+} PACKAGE_HTLINK_MAP_ITEM;
+
+/**
+ * A Processor's complete set of link assignments
+ */
+typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
+
+#endif  // _TOPOLOGY_H_
diff --git a/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h
new file mode 100755
index 0000000000..5a9fc6c815
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Include/gcc-intrin.h
@@ -0,0 +1,630 @@
+/*
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if defined (__GNUC__)
+
+/* I/O intrin functions.  */
+static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+{
+  unsigned char value;
+
+  __asm__ __volatile__ (
+    "in  %%dx, %%al"
+    : "=a" (value)
+    : "d" (Port)
+    );
+
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+{
+  unsigned short value;
+
+  __asm__ __volatile__ (
+    "in  %%dx, %%ax"
+    : "=a" (value)
+    : "d" (Port)
+    );
+
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+{
+  unsigned long value;
+    
+  __asm__ __volatile__ (
+    "in  %%dx, %%eax"
+    : "=a" (value)
+    : "d" (Port)
+    );
+  return value;
+
+}
+
+static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+{
+  __asm__ __volatile__ (
+    "out  %%al, %%dx"
+    :
+    : "a" (Data), "d" (Port)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+{
+  __asm__ __volatile__ (
+    "out  %%ax, %%dx"
+    :
+    : "a" (Data), "d" (Port)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "out  %%eax, %%dx"
+    :
+    : "a" (Data), "d" (Port)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; insb " 
+    : "=D" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; insw " 
+    : "=D" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; insl " 
+    : "=D" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; outsb " 
+    : "=S" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; outsw " 
+    : "=S" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+  );
+}
+
+static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+   "cld ; rep ; outsl " 
+   : "=S" (Buffer), "=c" (Count)
+   : "d"(Port), "0"(Buffer), "1" (Count)
+   );
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr0, %[value]" 
+    : [value] "=a" (value)
+    );
+  return value;
+}
+ 
+static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr1, %[value]" 
+    : [value] "=a" (value)
+    );
+  return value;
+}
+ 
+static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr2, %[value]" 
+    : [value] "=a" (value)
+    );
+  return value;
+}
+ 
+static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr3, %[value]" 
+    : [value] "=a" (value)
+    );
+  return value;
+}
+ 
+static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr7, %[value]" 
+    : [value] "=a" (value)
+    );
+  return value;
+}
+ 
+static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
+{
+  switch (reg){
+    case 0:
+      return __readdr0 ();
+      break;
+
+    case 1:
+      return __readdr1 ();
+      break;
+
+    case 2:
+      return __readdr2 ();
+      break;
+
+    case 3:
+      return __readdr3 ();
+      break;
+
+    case 7:
+      return __readdr7 ();
+      break;
+
+    default:
+      return -1;
+  }      
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr0"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr1"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr2"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr3"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr7"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
+{
+  switch (reg){
+    case 0:
+      __writedr0 (Data);
+      break;
+
+    case 1:
+      __writedr1 (Data);
+      break;
+
+    case 2:
+      __writedr2 (Data);
+      break;
+
+    case 3:
+      __writedr3 (Data);
+      break;
+
+    case 7:
+      __writedr7 (Data);
+      break;
+
+    default:
+      ;
+  } 
+}
+ 
+static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr0, %[value]" 
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr2, %[value]" 
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr3, %[value]" 
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr4, %[value]" 
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr8, %[value]" 
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
+{
+  switch (reg){
+    case 0:
+      return __readcr0 ();
+      break;
+
+    case 2:
+      return __readcr2 ();
+      break;
+
+    case 3:
+      return __readcr3 ();
+      break;
+
+    case 4:
+      return __readcr4 ();
+      break;
+
+    case 8:
+      return __readcr8 ();
+      break;
+
+    default:
+      return -1;
+  }      
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr0"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr2"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr3"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr4"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr8"
+    : 
+    : "a" (Data)
+    );
+}
+ 
+static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
+{
+  switch (reg){
+    case 0:
+      __writecr0 (Data);
+      break;
+
+    case 2:
+      __writecr2 (Data);
+      break;
+
+    case 3:
+      __writecr3 (Data);
+      break;
+
+    case 4:
+      __writecr4 (Data);
+      break;
+
+    case 8:
+      __writecr8 (Data);
+      break;
+
+    default:
+      ;
+  } 
+}
+
+static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
+{
+  UINT64 retval;
+  __asm__ __volatile__(
+       "rdmsr\n\t"
+       : "=A" (retval)
+       : "c" (msr)
+       );
+   return retval;
+}
+
+static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
+{
+  __asm__ __volatile__ (
+     "wrmsr\n\t"
+     :
+     : "c" (msr), "A" (Value)
+     );
+}
+ 
+static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
+{
+  UINT64 retval;
+  __asm__ __volatile__ (
+     "rdtsc" 
+     : "=A" (retval));
+  return retval;
+}
+
+static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
+{
+   __asm__ __volatile__(
+     "cpuid" 
+     :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3]) 
+     : "a" (InfoType)
+     );
+}
+
+
+static __inline__ __attribute__((always_inline)) void _disable(void)
+{
+  __asm__ __volatile__ ("cli");
+}
+
+
+static __inline__ __attribute__((always_inline)) void _enable(void)
+{
+  __asm__ __volatile__ ("sti");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __halt(void)
+{
+  __asm__ __volatile__ ("hlt");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __debugbreak(void)
+{
+  __asm__ __volatile__ ("int3");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __wbinvd(void)
+{
+  __asm__ __volatile__ ("wbinvd");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
+{
+  __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
+}
+
+static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data)
+{
+  __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data)
+{
+  __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data)
+{
+  __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset)
+{
+  unsigned char value;
+  __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset)
+{
+  unsigned short value;
+  __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset)
+{
+  unsigned long long value;
+  __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+  return value;
+}
+
+#ifdef __SSE3__
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
+{
+  __asm__(".byte 0x64"); // fs prefix
+  __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
+}
+
+static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
+{
+  __m128i data;
+  data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
+  _mm_stream_si128_fs2 (__A, data);
+}
+
+static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
+{
+  __asm__(".byte 0x64"); // fs prefix
+  __builtin_ia32_clflush (__A);
+}
+
+static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
+{
+  __builtin_ia32_mfence ();
+}
+
+static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
+{
+  __builtin_ia32_sfence ();
+}
+#endif
+
+static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
+{
+   __asm__ __volatile__ (
+    "cld ; rep ; stosb "
+    : "=D" (dest), "=c" (count)
+    : "a"(data), "0"(dest), "1" (count)
+  );
+}
+
+static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count)
+{
+   __asm__ __volatile__ (
+    "cld ; rep ; movsb "
+    : "=D" (dest), "=S"(data), "=c" (count)
+    : "S"(data), "0"(dest), "1" (count)
+  );
+}
+
+static __inline__ __attribute__((always_inline)) 
+void debug_point ( unsigned short Port,  unsigned long Data )
+{
+   __outdword (Port, Data);     
+   __asm__ __volatile__ (".word 0xfeeb");
+
+}
+
+static __inline__ __attribute__((always_inline)) 
+void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
+{
+  UINTN  Index;
+  Index = 0;
+  __outdword (Port, Data);
+  while (Index < delayTime * 600000) {
+    __outdword (0xE0, 0);
+    Index ++;
+  }
+}
+#endif // defined (__GNUC__)
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
new file mode 100755
index 0000000000..27e57c1b93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
@@ -0,0 +1,383 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * AMD Platform Specific Memory Configuration
+; *
+; * Contains AMD AGESA Memory Configuration Override Interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 22910 $   @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
+;
+; ****************************************************************************
+; *
+; * Copyright (c) 2011, Advanced Micro Devices, Inc.
+; * All rights reserved.
+; * 
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *     * Redistributions of source code must retain the above copyright
+; *       notice, this list of conditions and the following disclaimer.
+; *     * Redistributions in binary form must reproduce the above copyright
+; *       notice, this list of conditions and the following disclaimer in the
+; *       documentation and/or other materials provided with the distribution.
+; *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+; *       its contributors may be used to endorse or promote products derived 
+; *       from this software without specific prior written permission.
+; * 
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * 
+; *
+; **************************************************************************
+IFNDEF PSO_ENTRY
+  PSO_ENTRY           TEXTEQU    <UINT8>; < Platform Configuration Table Entry
+ENDIF
+; *****************************************************************************************
+; *
+; *                 PLATFORM SPECIFIC MEMORY DEFINITIONS
+; *
+; *****************************************************************************************
+; */
+;
+; < Memory Speed and DIMM Population Masks
+;
+; < DDR Speed Masks
+;
+ANY_SPEED     EQU     0FFFFFFFFh
+DDR400        EQU     ( 1 SHL (DDR400_FREQUENCY   / 66))
+DDR533        EQU     ( 1 SHL (DDR533_FREQUENCY   / 66))
+DDR667        EQU     ( 1 SHL (DDR667_FREQUENCY   / 66))
+DDR800        EQU     ( 1 SHL (DDR800_FREQUENCY   / 66))
+DDR1066       EQU     ( 1 SHL (DDR1066_FREQUENCY  / 66))
+DDR1333       EQU     ( 1 SHL (DDR1333_FREQUENCY  / 66))
+DDR1600       EQU     ( 1 SHL (DDR1600_FREQUENCY  / 66))
+DDR1866       EQU     ( 1 SHL (DDR1866_FREQUENCY  / 66))
+; <
+; <  DIMM POPULATION MASKS
+;
+ANY_        EQU      0FFh
+SR_DIMM0    EQU     0001h
+SR_DIMM1    EQU     0010h
+SR_DIMM2    EQU     0100h
+SR_DIMM3    EQU     1000h
+DR_DIMM0    EQU     0002h
+DR_DIMM1    EQU     0020h
+DR_DIMM2    EQU     0200h
+DR_DIMM3    EQU     2000h
+QR_DIMM0    EQU     0004h
+QR_DIMM1    EQU     0040h
+QR_DIMM2    EQU     0400h
+QR_DIMM3    EQU     4000h
+ANY_DIMM0   EQU     000Fh
+ANY_DIMM1   EQU     00F0h
+ANY_DIMM2   EQU     0F00h
+ANY_DIMM3   EQU    0F000h
+;
+;  Number of Dimms
+;
+ANY_NUM      EQU    0FFh
+NO_DIMM      EQU     00h
+ONE_DIMM     EQU     01h
+TWO_DIMM     EQU     02h
+THREE_DIMM   EQU     04h
+FOUR_DIMM    EQU     08h
+; *****************************************************************************************
+; *
+; * Platform Specific Override Definitions for Socket, Channel and Dimm
+; * This indicates where a platform override will be applied.
+; *
+; *****************************************************************************************
+;
+;  SOCKET MASKS
+;
+ANY_SOCKET      EQU    0FFh
+SOCKET0         EQU     01h
+SOCKET1         EQU     02h
+SOCKET2         EQU     04h
+SOCKET3         EQU     08h
+SOCKET4         EQU     10h
+SOCKET5         EQU     20h
+SOCKET6         EQU     40h
+SOCKET7         EQU     80h
+;
+;  CHANNEL MASKS
+;
+ANY_CHANNEL     EQU    0FFh
+CHANNEL_A       EQU     01h
+CHANNEL_B       EQU     02h
+CHANNEL_C       EQU     04h
+CHANNEL_D       EQU     08h
+;
+;  DIMM MASKS
+;
+ALL_DIMMS       EQU    0FFh
+DIMM0           EQU     01h
+DIMM1           EQU     02h
+DIMM2           EQU     04h
+DIMM3           EQU     08h
+;
+;  REGISTER ACCESS MASKS
+;
+ACCESS_NB0      EQU      0h
+ACCESS_NB1      EQU     01h
+ACCESS_NB2      EQU     02h
+ACCESS_NB3      EQU     03h
+ACCESS_NB4      EQU     04h
+ACCESS_PHY      EQU     05h
+ACCESS_DCT_XT   EQU     06h
+; *****************************************************************************************
+; *
+; * Platform Specific Overriding Table Definitions
+; *
+; *****************************************************************************************
+PSO_END                EQU      0     ; < Table End
+PSO_CKE_TRI            EQU      1     ; < CKE Tristate Map
+PSO_ODT_TRI            EQU      2     ; < ODT Tristate Map
+PSO_CS_TRI             EQU      3     ; < CS Tristate Map
+PSO_MAX_DIMMS          EQU      4     ; < Max Dimms per channel
+PSO_CLK_SPEED          EQU      5     ; < Clock Speed
+PSO_DIMM_TYPE          EQU      6     ; < Dimm Type
+PSO_MEMCLK_DIS         EQU      7     ; < MEMCLK Disable Map
+PSO_MAX_CHNLS          EQU      8     ; < Max Channels per Socket
+PSO_BUS_SPEED          EQU      9     ; < Max Memory Bus Speed
+PSO_MAX_CHIPSELS       EQU     10     ; < Max Chipsel per Channel
+PSO_MEM_TECH           EQU     11     ; < Channel Memory Type
+PSO_WL_SEED            EQU     12     ; < DDR3 Write Levelization Seed delay
+PSO_LVDIMM_VOLT1_5_SUPPORT          EQU    16     ; < Force LvDimm voltage to 1.5V
+; **********************************
+; * CONDITIONAL PSO SPECIFIC ENTRIES
+; **********************************
+;  Condition Types
+CONDITIONAL_PSO_MIN   EQU     100     ; < Start of Conditional Entry Types
+PSO_CONDITION_AND     EQU     100     ; < And Block - Start of Conditional block
+PSO_CONDITION_LOC     EQU     101     ; < Location - Specify Socket, Channel, Dimms to be affected
+PSO_CONDITION_SPD     EQU     102     ; < SPD - Specify a specific SPD value on a Dimm on the channel
+PSO_CONDITION_REG     EQU     103     ;    Reserved
+PSO_CONDITION_MAX     EQU     103     ; < End Of Condition Entry Types
+;  Action Types
+PSO_ACTION_MIN        EQU     120     ; < Start of Action Entry Types
+PSO_ACTION_ODT        EQU     120     ; < ODT values to override
+PSO_ACTION_ADDRTMG    EQU     121     ; < Address/Timing values to override
+PSO_ACTION_ODCCONTROL EQU     122     ; < ODC Control values to override
+PSO_ACTION_SLEWRATE   EQU     123     ; < Slew Rate value to override
+PSO_ACTION_REG        EQU     124     ;    Reserved
+PSO_ACTION_SPEEDLIMIT EQU     125     ; < Memory Bus speed Limit based on configuration
+PSO_ACTION_MAX        EQU     125     ; < End of Action Entry Types
+CONDITIONAL_PSO_MAX   EQU     139     ; < End of Conditional Entry Types
+; *****************************************************************************************
+; *
+; *                 CONDITIONAL OVERRIDE TABLE MACROS
+; *
+; *****************************************************************************************
+MEMCLK_DIS_MAP    MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
+ DB PSO_MEMCLK_DIS
+ DB 10
+ DB SocketID
+ DB ChannelID
+ DB Bit0Map
+ DB Bit1Map
+ DB Bit2Map
+ DB Bit3Map
+ DB Bit4Map
+ DB Bit5Map
+ DB Bit6Map
+ DB Bit7Map
+ENDM
+
+CKE_TRI_MAP     MACRO     SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
+ DB PSO_CKE_TRI
+ DB 4
+ DB SocketID
+ DB ChannelID
+ DB Bit0Map
+ DB Bit1Map
+ENDM
+
+ODT_TRI_MAP     MACRO     SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
+ DB PSO_ODT_TRI
+ DB 6
+ DB SocketID
+ DB ChannelID
+ DB Bit0Map
+ DB Bit1Map
+ DB Bit2Map
+ DB Bit3Map
+ENDM
+
+CS_TRI_MAP     MACRO     SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
+ DB PSO_CS_TRI
+ DB 10
+ DB SocketID
+ DB ChannelID
+ DB Bit0Map
+ DB Bit1Map
+ DB Bit2Map
+ DB Bit3Map
+ DB Bit4Map
+ DB Bit5Map
+ DB Bit6Map
+ DB Bit7Map
+ENDM
+
+NUMBER_OF_DIMMS_SUPPORTED     MACRO     SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
+ DB PSO_MAX_DIMMS
+ DB 3
+ DB SocketID
+ DB ChannelID
+ DB NumberOfDimmSlotsPerChannel
+ENDM
+
+NUMBER_OF_CHIP_SELECTS_SUPPORTED     MACRO     SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
+ DB PSO_MAX_CHIPSELS
+ DB 3
+ DB SocketID
+ DB ChannelID
+ DB NumberOfChipSelectsPerChannel
+ENDM
+
+NUMBER_OF_CHANNELS_SUPPORTED     MACRO     SocketID:REQ, NumberOfChannelsPerSocket:REQ
+ DB PSO_MAX_CHNLS
+ DB 3
+ DB SocketID
+ DB ANY_CHANNEL
+ DB NumberOfChannelsPerSocket
+ENDM
+
+OVERRIDE_DDR_BUS_SPEED     MACRO     SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
+ PSO_BUS_SPEED
+ DB 10
+ DB SocketID
+ DB ChannelID
+ DD TimingMode
+ DD BusSpeed
+ENDM
+
+DRAM_TECHNOLOGY           MACRO SocketID:REQ, MemTechType:REQ
+ DB PSO_MEM_TECH
+ DB 6
+ DB SocketID
+ DB ANY_CHANNEL
+ DD MemTechType
+ENDM
+
+WRITE_LEVELING_SEED     MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
+Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
+ DB PSO_WL_SEED
+ DB 11
+ DB SocketID
+ DB ChannelID
+ DB Byte0Seed
+ DB Byte1Seed
+ DB Byte2Seed
+ DB Byte3Seed
+ DB Byte4Seed
+ DB Byte5Seed
+ DB Byte6Seed
+ DB Byte7Seed
+ DB ByteEccSeed
+ENDM
+
+LVDIMM_FORCE_VOLT1_5_FOR_D0     MACRO
+ DB PSO_LVDIMM_VOLT1_5_SUPPORT
+ DB 3
+ DB ANY_SOCKET
+ DB ANY_CHANNEL
+ DB 1
+ENDM
+ 
+; *****************************************************************************************
+; *
+; *                 CONDITIONAL OVERRIDE TABLE MACROS
+; *
+; *****************************************************************************************
+CONDITION_AND      MACRO
+ DB PSO_CONDITION_AND
+ DB 0
+ENDM
+
+COND_LOC     MACRO     SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
+ DB PSO_CONDITION_LOC
+ DB 3
+ DB SocketMsk
+ DB ChannelMsk
+ DB DimmMsk
+ENDM
+
+COND_SPD     MACRO     Byte:REQ, Mask:REQ, Value:REQ
+ DB PSO_CONDITION_SPD
+ DB 3
+ DB Byte
+ DB Mask
+ DB Value
+ENDM
+
+COND_REG     MACRO     Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
+ DB PSO_CONDITION_REG
+ DB 11
+ DB Access
+ DW Offset
+ DD Mask
+ DD Value
+ENDM
+
+ACTION_ODT     MACRO     Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
+ DB PSO_ACTION_ODT
+ DB 9
+ DD Frequency
+ DB Dimms
+ DB QrDimms
+ DB DramOdt
+ DB QrDramOdt
+ DB DramDynOdt
+ENDM
+
+ACTION_ADDRTMG     MACRO     Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
+ DB PSO_ACTION_ADDRTMG
+ DB 10
+ DD Frequency
+ DW DimmConfig
+ DD AddrTmg
+ENDM
+
+ACTION_ODCCTRL     MACRO     Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
+ DB PSO_ACTION_ODCCONTROL
+ DB 10
+ DD Frequency
+ DW DimmConfig
+ DD OdcCtrl
+ENDM
+
+ACTION_SLEWRATE     MACRO     Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
+ DB PSO_ACTION_SLEWRATE
+ DB 10
+ DD Frequency
+ DW DimmConfig
+ DD SlewRate
+ENDM
+
+ACTION_SPEEDLIMIT     MACRO     DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
+ DB PSO_ACTION_SPEEDLIMIT
+ DB 9
+ DW DimmConfig
+ DB Dimms
+ DW SpeedLimit15
+ DW SpeedLimit135
+ DW SpeedLimit125
+ENDM
+
+; *****************************************************************************************
+; *
+; *                 END OF CONDITIONAL OVERRIDE TABLE MACROS
+; *
+; *****************************************************************************************
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c
new file mode 100755
index 0000000000..d1d62b96bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/Dispatcher.c
@@ -0,0 +1,155 @@
+/**
+ * @file
+ *
+ * AMD binary block interface
+ *
+ * Contains the block entry function dispatcher
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 7116 $   @e \$Date: 2008-08-01 10:39:07 -0500 (Fri, 01 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Dispatcher.h"
+#include "Options.h"
+#include "Filecode.h"
+#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST DISPATCH_TABLE DispatchTable[];
+extern AMD_MODULE_HEADER mCpuModuleID;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The Dispatcher is the entry point into the AGESA software. It takes a function
+ * number as entry parameter in order to invoke the published function
+ *
+ * @param[in,out]  ConfigPtr
+ *
+ * @return   AGESA Status.
+ *
+ */
+AGESA_STATUS
+CALLCONV
+AmdAgesaDispatcher (
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  IMAGE_ENTRY ImageEntry;
+  MODULE_ENTRY  ModuleEntry;
+  DISPATCH_TABLE *Entry;
+  UINT32 ImageStart;
+  UINT32 ImageEnd;
+  AMD_IMAGE_HEADER* AltImagePtr;
+
+  Status = AGESA_UNSUPPORTED;
+  ImageEntry = NULL;
+  ModuleEntry = NULL;
+  ImageStart = 0xFFF00000;
+  ImageEnd = 0xFFFFFFFF;
+  AltImagePtr = NULL;
+
+  Entry = (DISPATCH_TABLE *) DispatchTable;
+  while (Entry->FunctionId != 0) {
+    if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
+      Status = Entry->EntryPoint (ConfigPtr);
+      break;
+    }
+    Entry++;
+  }
+
+  // 2. Try next dispatcher if possible, and we have not already got status back
+  if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
+    ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
+    if (ModuleEntry != NULL) {
+      Status = (*ModuleEntry) (ConfigPtr);
+    }
+  }
+
+  // 3. If not this image specific function, see if we can find alternative image instead
+  if (Status == AGESA_UNSUPPORTED) {
+    if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF  ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) {
+      ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
+      ImageEnd = ImageStart + 4;
+      // Locate/test image base that matches this component
+      AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *)AGESA_ID);
+      if (AltImagePtr != NULL) {
+        //Invoke alternative Image
+        ImageEntry = (IMAGE_ENTRY) (AltImagePtr + AltImagePtr->EntryPointAddress);
+        Status = (*ImageEntry) (ConfigPtr);
+      }
+    }
+  }
+
+  return (Status);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The host environment interface of callout.
+ *
+ * @param[in]      Func
+ * @param[in]      Data
+ * @param[in,out]  ConfigPtr
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+CALLCONV
+AmdAgesaCallout (
+  IN       UINT32  Func,
+  IN       UINT32  Data,
+  IN OUT   VOID    *ConfigPtr
+  )
+{
+  UINT32 Result;
+  Result = AGESA_UNSUPPORTED;
+  if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
+    return Result;
+  }
+
+  Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
+  return (Result);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c
new file mode 100755
index 0000000000..a104df8580
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/agesaCallouts.c
@@ -0,0 +1,371 @@
+/**
+ * @file
+ *
+ * AMD CPU AGESA Callout Functions
+ *
+ * Contains code to set / get useful platform information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 5931 $   @e \$Date: 2008-04-24 18:01:47 -0700 (Thu, 24 Apr 2008) $
+ *
+ */
+/*****************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * Description: agesaCallouts.c - AGESA Call out functions
+ *
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Dispatcher.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S - (AGESA ONLY)
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  );
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Call the host environment interface to do the warm or cold reset.
+ *
+ *  @param[in]      ResetType       Warm or Cold Reset is requested
+ *  @param[in,out]  StdHeader       Config header
+ *
+ */
+VOID
+AgesaDoReset (
+  IN       UINTN             ResetType,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Call the host environment interface to allocate buffer in main system memory.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  AllocParams  Heap manager parameters
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN       UINTN               FcnData,
+  IN OUT   AGESA_BUFFER_PARAMS *AllocParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to deallocate buffer in main system memory.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  DeallocParams   Heap Manager parameters
+ *
+ * @return   The AGESA Status returned from the callout.
+ */
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_BUFFER_PARAMS  *DeallocParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Call the host environment interface to Locate buffer Pointer in main system memory
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  LocateParams   Heap manager parameters
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_BUFFER_PARAMS  *LocateParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to launch APs
+ *
+ * @param[in]      ApicIdOfCore
+ * @param[in,out]  LaunchApParams
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN         ApicIdOfCore,
+  IN        AP_EXE_PARAMS *LaunchApParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to read an SPD's content.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  ReadSpd
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaReadSpd (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_READ_SPD_PARAMS *ReadSpd
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to read an SPD's content.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  ReadSpd
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_READ_SPD_PARAMS *ReadSpd
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to provide a user hook opportunity.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)FcnData, MemData);
+
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Call the host environment interface to provide a user hook opportunity.
+ *
+ *  @param[in]      FcnData
+ *  @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)FcnData, MemData);
+
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Call the host environment interface to provide a user hook opportunity.
+ *
+ *  @param[in]      FcnData
+ *  @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
+
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to provide a user hook opportunity.
+ *
+ * @param[in]      Data
+ * @param[in,out]  IdsCalloutData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+
+
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
+
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIE slot reset control
+ *
+ *
+ *
+ * @param[in]  FcnData              Function data
+ * @param[in]  ResetInfo            Reset information
+ * @retval     Status               Agesa status
+ */
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+  )
+{
+  AGESA_STATUS Status;
+  Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
+  return  Status;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
new file mode 100755
index 0000000000..eb1f838ab5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
@@ -0,0 +1,2670 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+;  Workfile: arch2008.asm     $Revision: 44323 $    $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+;
+; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
+;
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    INCLUDE agesa.inc
+    INCLUDE acwrapg.inc       ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
+    INCLUDE acwrap.inc        ; IBVs may specify host BIOS-specific include files required when building.
+    INCLUDE cpcarmac.inc
+    INCLUDE bridge32.inc
+    .LIST
+    .586p
+
+
+;----------------------------------------------------------------------------
+; Local definitions
+;----------------------------------------------------------------------------
+
+sOemCallout STRUCT
+    FuncName   DD   ?         ; Call out function name
+    FuncPtr    DW   ?         ; Call out function pointer
+sOemCallout ENDS
+
+sOemEventHandler STRUCT
+    ClassCode  DD   ?         ; AGESA event log sub-class code
+    FuncPtr    DW   ?         ; Event handler function pointer
+sOemEventHandler ENDS
+
+;; A typical legacy BIOS implementation may require the E000 and F000 segments
+;; to be cached.
+EXE_CACHE_REGION_BASE_0  EQU  0E0000h
+EXE_CACHE_REGION_SIZE_0  EQU  20000h
+
+;; In this sample implementation, the B1 and B2 images are placed next to each
+;; other in the BIOS ROM to help with the maximization of cached code.
+EXE_CACHE_REGION_BASE_1  EQU  AGESA_B1_ADDRESS
+EXE_CACHE_REGION_SIZE_1  EQU  40000h
+
+;; The third region is not needed in our example.
+EXE_CACHE_REGION_BASE_2  EQU  0
+EXE_CACHE_REGION_SIZE_2  EQU  0
+
+
+;----------------------------------------------------------------------------
+;    PERSISTENT SEGMENT
+; This segment is required to be present throughout all BIOS execution.
+;----------------------------------------------------------------------------
+
+AMD_PERSISTENT_START
+
+
+;----------------------------------------------------------------------------
+; Instantiate the global descriptor table
+;----------------------------------------------------------------------------
+
+AMD_BRIDGE_32_GDT AMD_GDT         ; Instantiate the global descriptor table
+                                  ; required by the push-high mechanism.
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the persistent segment
+;----------------------------------------------------------------------------
+
+;+-------------------------------------------------------------------------
+;
+;   AmdDfltRet
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Near stub procedure.  Simply perform a retn instruction.
+;
+EXTERN AmdDfltRet:NEAR
+
+
+;+-------------------------------------------------------------------------
+;
+;   AmdDfltRetFar
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Far stub procedure.  Simply perform a retf instruction.
+;
+EXTERN AmdDfltRetFar:FAR
+
+
+;----------------------------------------------------------------------------
+; Declare the optional external routines in the persistent segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myModuleTypeMismatchHandler (Example)
+;
+;   Entry:
+;     ESI - Pointer to the EVENT_PARAMS structure of the failure.
+;     [ESI].DataParam1 - Socket
+;     [ESI].DataParam2 - DCT
+;     [ESI].DataParam3 - Channel
+;     [ESI].DataParam4 - 0x00000000
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure can be used to react to a memory module type
+;     mismatch error discovered by the AGESA code.  Actions taken
+;     may include, but are not limited to:
+;       Logging the event to NV for display later
+;       Reset, excluding the mismatch on subsequent reboot
+;       Do nothing
+;
+;   Dependencies:
+;     None
+;
+EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   oemPlatformConfigInit (Optional)
+;
+;   Entry:
+;     EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
+;           passed in to the next AGESA entry point.
+;
+;           typedef struct {
+;             IN PERFORMANCE_PROFILE PlatformProfile;
+;             IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
+;             IN UINT8               CoreLevelingMode;
+;             IN PLATFORM_C1E_MODES  C1eMode;
+;             IN UINT32              C1ePlatformData;
+;             IN BOOLEAN             UserOptionDmi;
+;             IN BOOLEAN             UserOptionPState;
+;             IN BOOLEAN             UserOptionSrat;
+;             IN BOOLEAN             UserOptionSlit;
+;             IN BOOLEAN             UserOptionWhea;
+;             IN UINT32              PowerCeiling;
+;             IN BOOLEAN             PstateIndependent;
+;           } PLATFORM_CONFIGURATION;
+;
+;           typedef struct {
+;             IN UINT8 Socket;
+;             IN UINT8 Link;
+;             IN UINT8 LoFreq;
+;             IN UINT8 HighFreq;
+;             IN PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;
+;             IN PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;
+;           } CPU_HT_DEEMPHASIS_LEVEL;
+;
+;           typedef struct {
+;             IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
+;             IN BOOLEAN               UseHtAssist;
+;             IN BOOLEAN               Use32ByteRefresh;
+;             IN BOOLEAN               UseVariableMctIsocPriority;
+;           } PERFORMANCE_PROFILE;
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Provide a single hook routine to modify the parameters of a
+;     PLATFORM_CONFIGURATION structure before any entry point that
+;     has such a structure as an input.
+;
+;   Dependencies:
+;     None
+;
+;   Example:
+;     If your platform is running in UMA mode, the following code
+;     may be added:
+;       mov  (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
+;
+EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
+
+;+---------------------------------------------------------------------------
+;
+;   oemCallout (Optional)
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The default call out router function which resides in the same
+;     segment as the push-high bridge code.
+;
+;   Dependencies:
+;     None
+;
+EXTERN oemCallout(AmdDfltRet):NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the persistent segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdBridge32
+;
+;   Entry:
+;     EDX - A Real Mode FAR pointer using seg16:Offset16 format that
+;           points to a local host environment call-out router. If
+;           this pointer is not equal to zero, then this pointer is
+;           used as the call-out router instead of the standard
+;           OemCallout. This may be useful when the call-out router
+;           is not located in the same segment as the AmdBridge32 and
+;           AmdCallout16 routines.
+;     ESI - A Flat Mode pointer (32-bit address) that points to the
+;           configuration block (AMD_CONFIG_PARAMS) for the AGESA
+;           software function.
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Execute an AGESA software function through the Push-High interface.
+;
+;   Dependencies:
+;     This procedure requires a stack. The host environment must use the
+;     provided service function to establish the stack environment prior
+;     to making the call to this procedure.
+;
+AmdBridge32 PROC FAR PUBLIC
+    AMD_BRIDGE_32 AMD_GDT             ; use the macro for the body
+    ret
+AmdBridge32 ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdEnableStack
+;
+;   Entry:
+;     BX - Return address
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;     SS:ESP - Points to the private stack location for this processor core.
+;     ECX - Upon success, contains this processor core's stack size in bytes.
+;
+;   Modified:
+;     EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
+;
+;   Purpose:
+;     This procedure is used to establish the stack within the host environment.
+;
+;   Dependencies:
+;     The host environment must use this procedure and not rely on any other
+;     sources to create the stack region.
+;
+AmdEnableStack PROC NEAR PUBLIC
+    AMD_ENABLE_STACK
+    ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
+    ;; EAX = AGESA_WARNING, The stack has already been set up.  SS:ESP is set
+    ;;       to stack top, and ECX is the stack size in bytes.
+    jmp   bx
+AmdEnableStack ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdDisableStack
+;
+;   Entry:
+;     BX - Return address
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     EAX, ECX, EDX, ESI, ESP
+;
+;   Purpose:
+;     This procedure is used to remove the pre-memory stack from within the
+;     host environment.
+;     The exit state for the BSP is described as follows:
+;       Memory region 00000-9FFFF MTRRS are set as WB memory.
+;       Processor Cache is enabled (CD bit is cleared).
+;       MTRRs used for execution cache are kept.
+;       Cache content is flushed (invalidated without write-back).
+;       Any family-specific clean-up done.
+;     The exit state for the APs is described as follows:
+;       Memory region 00000-9FFFF MTRRS are set as WB memory.
+;       Memory region A0000-DFFFF MTRRS are set as UC IO.
+;       Memory region E0000-FFFFF MTRRS are set as UC memory.
+;       MTRRs used for execution cache are cleared.
+;       Processor Cache is disabled (CD bit is set).
+;       Top-of-Memory (TOM) set to the system top of memory as determined
+;         by the memory initialization routines.
+;       System lock command is enabled.
+;       Any family-specific clean-up done.
+;
+;   Dependencies:
+;     The host environment must use this procedure and not rely on any other
+;     sources to break down the stack region.
+;     If executing in 16-bit code, the host environment must establish the
+;     "Big Real" mode of 32-bit addressing of data.
+;
+AmdDisableStack PROC NEAR PUBLIC
+    AMD_DISABLE_STACK
+    ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
+    jmp   bx
+AmdDisableStack ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCallout16
+;
+;   Entry:
+;     [esp+8] - Func
+;     [esp+12] - Data
+;     [esp+16] - Configuration Block
+;     [esp+4] - Return address to AGESA
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Execute callback from the push-high interface.
+;
+;   Dependencies:
+;     None
+;
+AmdCallout16 PROC FAR PUBLIC ; declare the procedure
+    AMD_CALLOUT_16 oemCallout ; use the macro for the body
+    ret
+AmdCallout16 ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdProcessAgesaErrors (Optional)
+;
+;   Entry:
+;     AL - Heap status of the AGESA entry point that was just invoked.
+;     EBX - AGESA image base address.
+;     EDX - Segment / Offset of the appropriate callout router function.
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure is used to handle any errors that may have occurred
+;     during an AGESA entry point.
+;
+;   Dependencies:
+;     None
+;
+AmdProcessAgesaErrors PROC FAR PUBLIC
+    LOCAL localCpuInterfaceBlock:EVENT_PARAMS
+
+    pushad
+    xor   edi, edi
+    mov   di, ss
+    shl   edi, 4
+    lea   esi, localCpuInterfaceBlock
+    add   esi, edi
+
+    ; Fill default config block
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
+    mov   edi, SEG AmdCallout16
+    shl   edi, 4
+    add   edi, OFFSET AmdCallout16
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
+
+    ; Flush the event log searching for, and handling all monitored events
+    xor   eax, eax
+    .while (eax == 0)
+        push  edx
+        call  AmdBridge32
+        pop   edx
+        .if (eax == AGESA_SUCCESS)
+            mov   eax, (EVENT_PARAMS PTR [esi]).EventInfo
+            .if (eax != 0)
+                lea   di, cs:AgesaEventTable
+
+loopThruTable:
+                cmp   di, OFFSET cs:AgesaEventTableEnd
+                jae   unhandledEvent
+
+                cmp   eax, cs:[di].sOemEventHandler.ClassCode
+                je    FoundMatch
+                add   di, SIZEOF sOemEventHandler
+                jmp   loopThruTable
+
+FoundMatch:
+                mov   bx, cs:[di].sOemEventHandler.FuncPtr
+                call  bx
+
+unhandledEvent:
+                xor   eax, eax
+            .else
+                mov   al, 1
+            .endif
+        .endif
+    .endw
+    popad
+    ret
+
+AmdProcessAgesaErrors ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the error handler table
+;----------------------------------------------------------------------------
+
+AgesaEventTable LABEL BYTE
+    ;; Add entries as desired
+    ;;---------
+    ;; EXAMPLE
+    ;;---------
+    sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
+AgesaEventTableEnd LABEL BYTE
+
+
+AMD_PERSISTENT_END
+
+
+
+
+;----------------------------------------------------------------------------
+;    RECOVERY SEGMENT
+; This segment resides in the classic 'boot-block,' and is used
+; for recovery.
+;----------------------------------------------------------------------------
+
+AMD_RECOVERY_START
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the recovery segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myReadSPDRecovery (Required for proper recovery mode operation)
+;
+;   Entry:
+;     ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
+;
+;     typedef struct {
+;       IN OUT AMD_CONFIG_PARAMS StdHeader;
+;       IN       UINT8 SocketId;
+;       IN       UINT8 MemChannelId;
+;       IN       UINT8 DimmId;
+;       IN OUT   UINT8 *Buffer;
+;       IN OUT   MEM_DATA_STRUCT *MemData;
+;     } AGESA_READ_SPD_PARAMS;
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS Indicates the SPD block for the indicated
+;                         DIMM was read successfully.
+;           AGESA_BOUNDS_CHK The specified DIMM is not present.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function and no memory initialized.
+;           AGESA_ERROR The DIMM SPD read process has generated
+;                       communication errors.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This call out reads a block of memory SPD data and places it
+;     into the provided buffer.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myReadSPDRecovery:NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the recovery segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitResetWrapper
+;
+;   Entry:
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     A minimal initialization of the processor core is performed. This
+;     procedure must be called by all processor cores. The code path
+;     separates the BSP from the APs and performs a separate and appropriate
+;     list of tasks for each class of core.
+;     For the BSP, the following actions are performed:
+;       Internal heap sub-system initialization
+;       Primary non-coherent HyperTransportT link initialization
+;       Return to the host environment to test for Recovery Mode.
+;     The AP processor cores do not participate in the recovery process.
+;     However, they execute this routine after being released to execute
+;     by the BSP during the main boot process. Their actions include the
+;     following:
+;       Internal heap sub-system initialization
+;       Proceed to a wait loop waiting for commands from the BSP
+;
+;     For the cache regions, up to three regions of execution cache can be
+;     allocated following the following rules:
+;     1. Once a region is allocated, it cannot be de-allocated. However, it
+;        can be expanded.
+;     2. At most, two of the three regions can be located above 1 MByte. A
+;        region failing this rule is ignored.
+;     3. All region addresses must be at or above the 0x000D0000 linear
+;        address. A region failing this rule is ignored.
+;     4. The address is aligned on a 32-KByte boundary. Starting addresses
+;        is rounded down to the nearest 32-Kbyte boundary.
+;     5. The execution cache size must be a multiple of 32 KByte. Size is
+;        rounded up to the next multiple of 32 KByte.
+;     6. A region must not span either the 1-MByte boundary or the 4-GByte
+;        boundary. Allocated size is truncated to not span the boundary.
+;     7. The granted cached execution regions, address, and size are calculated
+;        based on the available cache resources of the processor core.
+;        Allocations are made up to the limit of cache available on the
+;        installed processor.
+;     Warning: Enabling instruction cache outside of this interface can cause
+;              data corruption.
+;
+;   Dependencies:
+;     This procedure is expected to be executed soon after a system reset
+;     for the main boot path or resume path of execution.
+;
+;     This procedure requires a stack.
+;
+;     Because the heap system is not yet operational at the point of the
+;     interface call, the host environment must allocate the storage for
+;     the AMD_RESET_PARAMS structure before making the first call to
+;     AmdCreateStruct.  This is the ByHost method of allocation.
+;
+AmdInitResetWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+    local localResetParams:AMD_RESET_PARAMS
+
+    pushad
+
+    ; Prepare for the call to initialize the input parameters for AmdInitReset
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
+    lea   edx, localResetParams
+    add   edx, eax
+    push  edx
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
+    mov   dx, SEG AmdCalloutRouterRecovery
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterRecovery
+    push  edx
+    call  AmdBridge32
+    pop   edx
+    pop   esi
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
+    ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
+    ; is cached.
+    mov   (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
+    mov   (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
+    mov   (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
+    mov   (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
+    mov   (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
+    mov   (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
+
+    ; Call in to the AmdInitReset entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS Early initialization completed successfully.
+    ;;  AGESA_WARNING One or more of the execution cache allocation
+    ;;                rules were violated, but an adjustment was made
+    ;;                and space was allocated.
+    ;;  AGESA_ERROR One or more of the execution cache allocation rules
+    ;;              were violated, which resulted in a requested cache
+    ;;              region to not be allocated.
+    ;;              The storage space allocated for the AMD_RESET_PARAMS
+    ;;              structure is insufficient.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B1_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+
+    ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
+
+    ;; Fixed-Range MTRRs
+    ;; Name                 Address         Value
+    ;; ----------------     --------        ----------------
+    ;; MTRRfix4k_E0000      0000026C        0505050505050505
+    ;; MTRRfix4k_E8000      0000026D        0505050505050505
+    ;; MTRRfix4k_F0000      0000026E        0505050505050505
+    ;; MTRRfix4k_F8000      0000026F        0505050505050505
+    ;; MTRRdefType          000002FF        0000000000000C00
+    ;;
+    ;; Variable-Range MTRRs and IO Range
+    ;;       MTRRphysBase(n)             MTRRphysMask(n)
+    ;;       -----------------           -----------------
+    ;; n=0   0000000000000000            0000000000000000
+    ;; n=1   0000000000000000            0000000000000000
+    ;; n=2   0000000000000000            0000000000000000
+    ;; n=3   0000000000000000            0000000000000000
+    ;; n=4   0000000000000000            0000000000000000
+    ;; n=5   Heap Base (Varies by core)  0000FFFFFFFF0800
+    ;; n=6   AGESA_B1_ADDRESS | 6        0000FFFFFFFC0800
+    ;; n=7   0000000000000000            0000000000000000
+
+
+    ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
+    ;; not necessary.  Stack space reclamation is left up to the host BIOS.
+
+    popad
+    ret
+
+
+AmdInitResetWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitRecoveryWrapper
+;
+;   Entry:
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Perform a minimum initialization of the processor and memory to
+;     support a recovery mode flash ROM update.
+;     For the BSP, the following actions are performed:
+;       Configuration of CPU core for recovery process
+;       Minimal initialization of some memory
+;     The AP processor cores do not participate in the recovery process.
+;     No actions or tasks are performed by the AP cores for this time point.
+;
+;   Dependencies:
+;     This procedure requires a stack. The host environment must use one of
+;     the provided service functions to establish the stack environment prior
+;     to making the call to this procedure.
+;
+AmdInitRecoveryWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterRecovery
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterRecovery
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+
+    ; Call in to the AmdInitRecovery entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_WARNING One or more of the allocation rules were violated,
+    ;;                but an adjustment was made and space was allocated.
+    ;;  AGESA_ERROR One or more of the allocation rules were violated,
+    ;;              which resulted in a requested cache region to not be
+    ;;              allocated.
+    ;;  AGESA_FATAL No memory was found in the system.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B1_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitRecovery
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+AmdInitRecoveryWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCalloutRouterRecovery
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The call out router function for AmdInitReset and
+;     AmdInitRecovery.
+;
+;   Dependencies:
+;     None
+;
+AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
+    xor   ax, ax
+    mov   ds, ax
+    mov   es, ax
+    lea   di, cs:CalloutRouterTableRecovery
+    mov   eax, AGESA_UNSUPPORTED
+
+loopThruTable:
+    cmp   di, OFFSET cs:CalloutRouterTableRecoveryEnd
+    jae   amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
+    cmp   ecx, cs:[di].sOemCallout.FuncName
+    je    FoundMatch
+    add   di, SIZEOF sOemCallout
+    jmp   loopThruTable
+
+FoundMatch:
+    mov   bx, cs:[di].sOemCallout.FuncPtr
+    call  bx
+
+amdCpuCalloutExit:
+    ret
+AmdCalloutRouterRecovery ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the callout dispatch table for the recovery segment
+;----------------------------------------------------------------------------
+
+CalloutRouterTableRecovery LABEL BYTE
+    ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
+    sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
+CalloutRouterTableRecoveryEnd LABEL BYTE
+
+
+AMD_RECOVERY_END
+
+
+
+;----------------------------------------------------------------------------
+;    PRE-MEMORY SEGMENT
+; This segment must be uncompressed in the ROM image.
+;----------------------------------------------------------------------------
+
+AMD_PREMEM_START
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the recovery segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myReadSPDPremem (Required)
+;
+;   Entry:
+;     ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
+;
+;     typedef struct {
+;       IN OUT AMD_CONFIG_PARAMS StdHeader;
+;       IN       UINT8 SocketId;
+;       IN       UINT8 MemChannelId;
+;       IN       UINT8 DimmId;
+;       IN OUT   UINT8 *Buffer;
+;       IN OUT   MEM_DATA_STRUCT *MemData;
+;     } AGESA_READ_SPD_PARAMS;
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS Indicates the SPD block for the indicated
+;                         DIMM was read successfully.
+;           AGESA_BOUNDS_CHK The specified DIMM is not present.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function and no memory initialized.
+;           AGESA_ERROR The DIMM SPD read process has generated
+;                       communication errors.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This call out reads a block of memory SPD data and places it
+;     into the provided buffer.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myReadSPDPremem:NEAR
+
+;+-------------------------------------------------------------------------
+;
+;   AmdDfltRetPremem
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Near stub procedure in the prememory segment.  Simply perform a
+;     retn instruction.
+;
+EXTERN AmdDfltRetPremem:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myDoReset (Required)
+;
+;   Entry:
+;     EDX - Reset type
+;           1 - Warm reset whenever
+;           2 - Cold reset whenever
+;           3 - Warm reset immediately
+;           4 - Cold reset immediately
+;     ESI - Pointer to an AMD_CONFIG_PARAMS structure.
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This host environment function must initiate the specified type
+;     of system reset.
+;
+;     Implementation of this function by the host environment is
+;     REQUIRED. Some host environments may record this as a request
+;     allowing other elements in the system to perform some additional
+;     tasks before the actual reset is issued.
+;
+;   Dependencies:
+;     The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
+;     register (F0x6C Link Initialization Control Register) that
+;     indicate the reset status. These bits are reserved for use by
+;     the AGESA software and should not be modified by the host
+;     environment.
+;
+EXTERN myDoReset:NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myGetNonVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     EBX - Pointer to the non-volatile S3 context block
+;     ECX - Size in bytes of the non-volatile S3 context block
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must return the pointer to the data
+;     saved during the mySaveNonVolatileS3Context routine.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myGetNonVolatileS3Context:NEAR
+
+
+;----------------------------------------------------------------------------
+; Declare the optional external routines in the prememory segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myAgesaHookBeforeExitSelfRefresh (Optional)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
+;     ESI - Pointer to a data structure containing the memory information
+;
+;   Exit:
+;     After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
+;     EAX - Contains the AGESA_STATUS return code
+;           AGESA_SUCCESS The function has completed successfully
+;           AGESA_UNSUPPORTED This function is not implemented by the host environment
+;           AGESA_WARNING A non-critical issue has occued in the host environment
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     General purpose hook called before the exiting self refresh
+;     This procedure is called once per channel
+;
+;     Implementation of this function is optional for the host environment
+;     This call-out is an opportunity for the host environment to make dynamic
+;     modifications to the memory timing settings specific to the board or host
+;     environment before exiting self refresh on S3 resume
+;
+;   Dependencies:
+;     This procedure is called before the exit self refresh bit is set in the resume
+;     sequence. The host environment must initiate the OS restart process. This procedure
+;     requires a stack. The host environment must establish the stack environment prior
+;     to making the call to this procedure
+;
+EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myHookBeforeDramInit (Optional)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
+;     ESI - Pointer to a data structure containing the memory information
+;
+;   Exit:
+;     After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This function is not implemented by the host environment
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     General-purpose hook called before the DRAM_Init bit is set. Called
+;     once per MCT
+;
+;     Implementation of this function is optional for the host environment
+;     This call-out is an opportunity for the host environment to make
+;     dynamic modifications to the memory timing settings specific to the
+;     board or host environment
+;
+;   Dependencies:
+;     None
+;
+EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myHookBeforeDQSTraining (Optional)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
+;     ESI - Pointer to a data structure containing the memory information.
+;
+;   Exit:
+;     After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This function is not implemented by the
+;                             host environment.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     General-purpose hook called just before the memory training processes
+;     begin. Called once per MCT.
+;
+;     Implementation of this function is optional for the host environment.
+;     This call-out is an opportunity for the host environment to make
+;     dynamic modifications to the memory timing settings specific to the
+;     board or host environment.
+;
+;     The host environment may also use this call-out for some board-
+;     specific features that should be activated at this time point,
+;     such as:
+;       Low voltage DIMMs-the host environment should set the recommended
+;       voltages found in the memory data structure for each memory
+;       channel. This needs to occur before training begins.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the prememory segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitEarlyWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     A full initialization of the processor is performed. Action details
+;     differ for the BSP and AP processor cores.
+;     For the BSP, the following actions are performed:
+;       Full HyperTransportT link initialization, coherent and non-coherent
+;       Processor register loading
+;       Microcode patch load
+;       Errata workaround processing
+;       Launch all processor cores
+;       Configure the processor power management capabilities
+;       Request a warm reset if needed
+;     For the AP, the following actions are performed:
+;       Processor register loading
+;       Microcode patch load
+;       Errata workaround processing
+;       Configure the processor power management capabilities
+;
+;   Dependencies:
+;     This procedure is expected to be called before main memory initialization
+;     and before the system warm reset. Prior to this, the basic configuration
+;     done by the AmdInitReset routine must be completed.
+;
+;     This procedure requires a stack. The host environment must use one of the
+;     provided service functions to establish the stack environment prior to
+;     making the call to this procedure.
+;
+;     The processes performed at this time point require communication between
+;     processor cores.
+;
+;     The host environment must recognize that all processor cores are running
+;     in parallel and avoid activities that might interfere with the core-to-core
+;     communication, such as modifying the MTRR settings or writing to the APIC
+;     registers.
+;
+AmdInitEarlyWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPremem
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPremem
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitEarly entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ALERT An HyperTransportT link CRC error was observed.
+    ;;  AGESA_WARNING One of more of the allocation rules were violated,
+    ;;                but an adjustment was made and space was allocated.
+    ;;                Or a HyperTransport device does not have the expected
+    ;;                capabilities, or unusable redundant HyperTransport
+    ;;                links were found.
+    ;;  AGESA_ERROR One or more of the allocation rules were violated, which
+    ;;              resulted in a requested cache region to not be allocated.
+    ;;              Or, a HyperTransport device failed to initialize.
+    ;;  AGESA_CRITICAL An illegal or unsupported mixture of processor types was
+    ;;                 found, or the processors installed were found to have an
+    ;;                 insufficient MP capability rating for this platform.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitEarly
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitEarlyWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitPostWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The main system memory is located, initialized, and brought on-line.
+;     The processor(s) are prepared for full operation and control by the
+;     host environment. Action details differ for the BSP and AP processor
+;     cores.
+;     For the BSP, the following actions are performed:
+;       Full memory initialization and configuration. BSP is the master for
+;       this process and may delegate some tasks to APs.
+;       AP collection of data for use later.
+;       Transfer the HOBs including the artifact data out of the pre-memory
+;       cache storage into a temporary holding buffer in the main memory.
+;       Check the BIST status of the BSP
+;       Shut down the APs.
+;       Prepare for the host environment to begin main boot activity.
+;       Disable the pre-memory stack.
+;     For the APs, the following actions are performed:
+;       Report core identity information.
+;       Execute indicated memory initialization processes as directed.
+;       Check the BIST status of the AP
+;       Disable the pre-memory stack.
+;       Prepare to halt, giving control to host environment.
+;     The entire range of system memory is enabled for Write-Back cache.
+;     The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
+;     to leave in place any flash ROM region currently set for Write-Protect
+;     execution cache.
+;
+;   Dependencies:
+;     This procedure is called after the host environment has determined that
+;     a normal boot to operating system should be performed after any system
+;     warm reset is completed and after the configuration done by AmdInitEarly
+;     has completed.
+;
+;     This procedure requires a stack. The host environment must use one of the
+;     provided service functions to establish the stack environment prior to
+;     making the call to this procedure.
+;
+;     The processes performed at this time point require communication between
+;     processor cores.  The host environment must recognize that all processor
+;     cores are running in parallel and avoid activities that might interfere
+;     with the core-to-core communication, such as modifying the MTRR settings
+;     or writing to the APIC registers.
+;
+AmdInitPostWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitPost
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPremem
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPremem
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitPost entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ALERT   A BIST error was found on one of the cores.
+    ;;  AGESA_WARNING HT Assist feature is running sub-optimally.
+    ;;  AGESA_FATAL   Memory initialization failed.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitPost
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitPostWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitResumeWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure initializes or re-initializes the silicon components
+;     for the resume boot path.  For the processor, main memory is brought
+;     out of self-refresh mode. This procedure will use the context data
+;     in the NvStorage area of the input structure to re-start the main
+;     memory.  The host environment must fill the AMD_S3_PARAMS NvStorage
+;     and VolatileStorage pointers and related size elements to describe
+;     the location of the context data. Note that for this procedure, the
+;     two data areas do not need to be contained in one buffer zone, they
+;     can be anywhere in the accessible memory address space. If the host
+;     environment uses a non-volatile storage device accessed on the system
+;     address bus such as flashROM, then the context data does not need to
+;     be moved prior to this call. If the host environment uses a non-
+;     volatile storage device not located on the system address bus (e.g.
+;     CMOS or SSEPROM) then the host environment must transfer the context
+;     data to a buffer in main memory prior to calling this procedure.
+;
+;   Dependencies:
+;     The host environment must have determined that the system should take
+;     the resume path prior to calling this procedure. The configuration
+;     done by AmdInitEarly and any necessary warm reset must be complete.
+;     After this procedure, execution proceeds to general system restoration.
+;
+;     This procedure requires a stack. The host environment must use one of
+;     the provided service functions to establish the stack environment prior
+;     to making the call to this procedure.
+;
+AmdInitResumeWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitResume
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPremem
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPremem
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
+    call  oemPlatformConfigInit
+
+    call  myGetNonVolatileS3Context
+    mov   (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
+    mov   (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
+
+    ; Call in to the AmdInitResume entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS Re-initialization has been completed successfully.
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+
+    ; Allow AGESA to free the space used by AmdInitResume
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitResumeWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCalloutRouterPremem
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The call out router function for AmdInitEarly,
+;     AmdInitPost, and AmdInitResume.
+;
+;   Dependencies:
+;     None
+;
+AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
+    xor   ax, ax
+    mov   ds, ax
+    mov   es, ax
+    lea   di, cs:CalloutRouterTablePremem
+    mov   eax, AGESA_UNSUPPORTED
+
+loopThruTable:
+    cmp   di, OFFSET cs:CalloutRouterTablePrememEnd
+    jae   amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
+    cmp   ecx, cs:[di].sOemCallout.FuncName
+    je    FoundMatch
+    add   di, SIZEOF sOemCallout
+    jmp   loopThruTable
+
+FoundMatch:
+    mov   bx, cs:[di].sOemCallout.FuncPtr
+    call  bx
+
+amdCpuCalloutExit:
+    ret
+AmdCalloutRouterPremem ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the callout dispatch table for the prememory segment
+;----------------------------------------------------------------------------
+
+CalloutRouterTablePremem LABEL BYTE
+    ;; Add entries as desired.
+    sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
+    sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
+    sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
+    sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
+    sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
+CalloutRouterTablePrememEnd LABEL BYTE
+
+
+
+AMD_PREMEM_END
+
+
+;----------------------------------------------------------------------------
+;    POST SEGMENT
+; This segment may be decompressed and run from system RAM.
+;----------------------------------------------------------------------------
+
+AMD_POST_START
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the POST segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myAllocateBuffer (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
+;     ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 BufferLength;
+;             IN       UINT32 BufferHandle;
+;                OUT   VOID *BufferPointer;
+;           } AGESA_BUFFER_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E3h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The requested size of memory has been
+;                         successfully allocated.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function.
+;           AGESA_ERROR Less than the requested amount of memory
+;                       was allocated.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of memory allocation.
+;     This function must allocate a buffer of the requested size or
+;     larger. This function is required to be implemented by the host
+;     environment.
+;
+;   Dependencies:
+;     The following call-outs must work together in the host system.
+;     Parameters of the same name have the same function and must be
+;     treated the same in each function:
+;       AgesaAllocateBuffer
+;       AgesaDeallocateBuffer
+;       AgesaLocateBuffer
+;       AgesaRunFcnOnAp
+;     The host environment may need to reserve a location in the buffer
+;     to store any host environment specific value(s). The returned
+;     pointer must not include this reserved space. The host environment
+;     on the AgesaDeallocateBuffer call needs to account for the reserved
+;     space.  This reserved space may be an identifier or the "handle"
+;     used to identify the specific memory block.
+;
+EXTERN myAllocateBuffer:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myDeallocateBuffer (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
+;     ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 BufferLength;
+;             IN       UINT32 BufferHandle;
+;                OUT   VOID *BufferPointer;
+;           } AGESA_BUFFER_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E5h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
+;                            software continues with its function.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of memory allocation.
+;     This function releases a valid working buffer. This function is
+;     required for the host environment to implement.
+;
+;   Dependencies:
+;     The following call-outs must work together in the host system.
+;     Parameters of the same name have the same function and must be
+;     treated the same in each function:
+;       AgesaAllocateBuffer
+;       AgesaDeallocateBuffer
+;       AgesaLocateBuffer
+;       AgesaRunFcnOnAp
+;
+EXTERN myDeallocateBuffer:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myLocateBuffer (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
+;     ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 BufferLength;
+;             IN       UINT32 BufferHandle;
+;                OUT   VOID *BufferPointer;
+;           } AGESA_BUFFER_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E7h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_BOUNDS_CHK The presented handle is invalid or the
+;                            buffer could not be located.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of memory allocation.
+;     This function must locate the buffer related to the indicated
+;     handle and return the address of the buffer and its length.
+;     This function is required to be implemented in the host
+;     environment.
+;
+;   Dependencies:
+;     The following call-outs must work together in the host system.
+;     Parameters of the same name have the same function and must be
+;     treated the same in each function:
+;       AgesaAllocateBuffer
+;       AgesaDeallocateBuffer
+;       AgesaLocateBuffer
+;       AgesaRunFcnOnAp
+;
+EXTERN myLocateBuffer:NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myRunFuncOnAp (Required)
+;
+;   Entry:
+;     EDX - Local APIC ID of the target core.
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must route execution to the target AP and
+;     have that AP call the AmdLateRunApTaskWrapper routine defined
+;     above.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myRunFuncOnAp:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   mySaveNonVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     EBX - Pointer to the non-volatile S3 context block
+;     ECX - Size in bytes of the non-volatile S3 context block
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must save the non-volatile data to an area
+;     that will not lose context while in the ACPI S3 sleep state, but
+;     cannot be placed in system RAM.  This data will need to be
+;     available during the call to AmdInitResume.
+;
+;   Dependencies:
+;     None
+;
+EXTERN mySaveNonVolatileS3Context:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   mySaveVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     EBX - Pointer to the volatile S3 context block
+;     ECX - Size in bytes of the volatile S3 context block
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must save the volatile data to an area
+;     that will not lose context while in the ACPI S3 sleep state.
+;     This data will need to be available during the call to
+;     AmdS3LateRestore.
+;
+;   Dependencies:
+;     None
+;
+EXTERN mySaveVolatileS3Context:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myGetVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     EBX - Pointer to the volatile S3 context block
+;     ECX - Size in bytes of the volatile S3 context block
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must return the pointer to the data
+;     saved during the mySaveVolatileS3Context routine.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myGetVolatileS3Context:NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the POST segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitEnvWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure uses the AgesaAllocateBuffer call-out to acquire
+;     permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
+;     is also known as, or includes, artifact data being used by the
+;     AGESA software. Upon entry to this procedure, the data is being
+;     held in a temporary memory location and it must be moved to a
+;     location controlled and protected by the host environment.
+;
+;     These actions are performed by the BSP. The APs are not assigned
+;     any tasks at this time point.
+;
+;   Dependencies:
+;     This procedure must be called after full memory is initialized and
+;     the host environment has taken control of main memory allocation.
+;     This procedure should be called before the PCI enumeration takes
+;     place and as soon as possible after the host environment memory
+;     allocation sub-system has started.
+;
+;     This procedure requires a stack. The host environment must use one
+;     of the provided service functions to establish the stack environment
+;     prior to making the call to this procedure.
+;
+AmdInitEnvWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitEnv entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ERROR The artifact data could not be found or the host
+    ;;  environment failed to allocate sufficient buffer space.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitEnv
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitEnvWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitMidWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure call performs special configuration requirements for
+;     the graphics display hardware.
+;
+;     These actions are performed by the BSP. The APs are not assigned any
+;     tasks at this time point.
+;
+;   Dependencies:
+;     This procedure must be called after PCI enumeration has allocated
+;     resources, but before the video BIOS call is performed.
+;
+;     This procedure requires a stack. The host environment must use one
+;     of the provided service functions to establish the stack environment
+;     prior to making the call to this procedure.
+;
+AmdInitMidWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitMid
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitMid entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitMid
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+
+AmdInitMidWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitLateWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The main purpose of this function is to generate informational
+;     data tables used by the operating system. The individual tables
+;     can be selected for generation through the user selection entries
+;     on the input parameters.
+;
+;     This routine uses the Call-Out AgesaAllocateBuffer to allocate a
+;     buffer of the proper size to contain the data.
+;
+;     The code path separates the BSP from the APs and perform a separate
+;     and appropriate list of tasks for each class of core.
+;     For the BSP, the following actions are performed:
+;       Allocate buffer space for the tables.
+;       Generate the table contents.
+;       Make sure that the CPU is in a known good power state before
+;       proceeding to boot the OS.
+;     For the APs, the following actions are performed:
+;       Final register settings preparing for entry to OS.
+;       Establish the final PState for entry to OS.
+;
+;   Dependencies:
+;     This routine is expected to be executed late in the boot sequence
+;     after main memory has been initialized, after PCI enumeration has
+;     completed, after the host environment ACPI sub-system has started,
+;     after the host environment has taken control of the APs, but just
+;     before the start of OS boot.
+;
+;     The host environment must provide the required call-outs listed in
+;     the "Required Call-Out Procedures" section of the AGESA interface
+;     specification to provide the buffer space in main memory and execute
+;     code on the APs. The host environment must register the created ACPI
+;     table in the main ACPI pointer tables. This may require moving the
+;     generated tables to another location in memory.
+;
+;     This procedure requires a stack. The host environment must establish
+;     the stack environment prior to making the call to this procedure.
+;     Some functions depend upon the preservation of the heap data across
+;     the shift from pre-memory environment to a post-memory environment.
+;     If that data was not preserved, then those functions cannot complete
+;     and an error is returned.
+;
+AmdInitLateWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitLate
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitLate entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ALERT
+    ;;  AGESA_ERROR The system could not allocate the needed amount of
+    ;;  buffer space; or could not locate the artifact data block in
+    ;;  memory. Likely cause: the host environment may not have preserved
+    ;;  the data properly.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    push  es
+    mov   ax, SEG AmdAcpiSratPointer
+    mov   es, ax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
+    mov   es:AmdAcpiSratPointer, ebx
+    mov   eax, DWORD PTR [ebx + 4]
+    mov   es:AmdAcpiSratSize, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
+    mov   es:AmdAcpiSlitPointer, ebx
+    mov   eax, DWORD PTR [ebx + 4]
+    mov   es:AmdAcpiSlitSize, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
+    mov   es:AmdAcpiSsdtPointer, ebx
+    mov   eax, DWORD PTR [ebx + 4]
+    mov   es:AmdAcpiSsdtSize, eax
+
+    xor   eax, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
+    mov   es:AmdAcpiWheaMcePointer, ebx
+    mov   ax, WORD PTR [ebx]
+    mov   es:AmdAcpiWheaMceSize, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
+    mov   es:AmdAcpiWheaCmcPointer, ebx
+    mov   ax, WORD PTR [ebx]
+    mov   es:AmdAcpiWheaCmcSize, eax
+
+    mov   eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
+    mov   es:AmdDmiInfoPointer, eax
+    pop   es
+
+
+    ; Allow AGESA to free the space used by AmdInitLate
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+
+AmdInitLateWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdS3SaveWrapper
+;
+;   Entry:
+;     On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure saves critical registers and/or configuration
+;     information for preservation across a system suspend mode. All
+;     actions needed to prepare the processor for suspend mode is
+;     performed, however this procedure does NOT initiate the suspend
+;     process. The host environment is expected to perform that duty.
+;
+;     These actions are performed by the BSP. The APs are not assigned
+;     any tasks at this time point.
+;
+;     The initializer routine will NULL out the save area pointers and
+;     sizes. This procedure will determine the size of storage needed
+;     for all the processor context, and make a call out to the environment
+;     for allocation of one buffer to store all of the data. Upon exit, the
+;     pointers and sizes within the AMD_S3_PARAMS structure will be updated
+;     with the appropriate addresses within the buffer that was allocated.
+;     The host environment is expected to then transfer the data pointed to
+;     by NvStorage to a non-volatile storage area, and the data pointed to
+;     by VolatileStorage to either a non-volatile storage area or system
+;     RAM that retains its content across suspend.
+;
+;   Dependencies:
+;     The host environment must initiate the suspend process.
+;
+;     This procedure requires a stack. The host environment must establish
+;     the stack environment prior to making the call to this procedure.
+;
+AmdS3SaveWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdS3Save
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdS3Save entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS All suspend duties have been completed successfully.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    mov   ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
+    .if (ecx != 0)
+        mov   ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
+        call  mySaveNonVolatileS3Context
+    .endif
+
+    mov   ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
+    .if (ecx != 0)
+        mov   ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
+        call  mySaveVolatileS3Context
+    .endif
+
+    ; Allow AGESA to free the space used by AmdS3Save
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+
+AmdS3SaveWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdS3LateRestoreWrapper
+;
+;   Entry:
+;     On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure restores the processor state, reloads critical
+;     silicon component registers, and performs any re-initialization
+;     required by the silicon. This procedure will use the context data
+;     in the VolatileStorage area of the input structure to restore the
+;     processor registers.
+;
+;     The host environment must fill the AMD_S3_PARAMS NvStorage and
+;     VolatileStorage pointers and related size elements to describe
+;     the location of the context data. Note that for this procedure,
+;     the two data areas do not need to be contained in one buffer zone,
+;     they can be anywhere in the accessible memory address space. If
+;     the host environment uses a non-volatile storage device accessed
+;     on the system address bus such as flashROM, then the context data
+;     does not need to be moved prior to this call. If the host
+;     environment uses a non-volatile storage device not located on the
+;     system address bus (e.g. CMOS or SSEPROM) then the host environment
+;     must transfer the context data to a buffer in main memory prior to
+;     calling this procedure.
+;
+;     These actions are performed by the BSP. The APs are not assigned
+;     any tasks at this time point.
+;
+;   Dependencies:
+;     This procedure is called late in the resume sequence, after the
+;     PCI control space is restored and just before resuming operating
+;     system execution.
+;
+;     The host environment must initiate the OS restart process.
+;
+;     This procedure requires a stack. The host environment must establish
+;     the stack environment prior to making the call to this procedure.
+;
+AmdS3LateRestoreWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
+    call  oemPlatformConfigInit
+
+    call  myGetVolatileS3Context
+    mov   (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
+    mov   (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
+
+    ; Call in to the AmdS3LateRestore entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS All resume processes have been completed successfully.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdS3LateRestore
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+AmdS3LateRestoreWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdLateRunApTaskWrapper
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - D5h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This entry point is tightly connected with the "AgesaRunFcnOnAp"
+;     call out.  The AGESA software will call the call-out "AgesaRunFcnOnAp";
+;     the host environment will then call this entry point to have the AP
+;     execute the requested function. This is needed late in the Post and
+;     Resume branches for running an AP task since the AGESA software has
+;     relinquished control of the APs to the host environment.
+;
+;   Dependencies:
+;     The host environment must implement the"AgesaRunFcnOnAp" call-out
+;     and route execution to the target AP.
+;
+AmdLateRunApTaskWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    push  es
+    mov   ax, SEG AmdRunCodeOnApDataPointer
+    mov   es, ax
+    mov   eax, es:AmdRunCodeOnApDataPointer
+    mov   (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
+    mov   eax, es:AmdRunCodeOnApDataSize
+    mov   (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
+    mov   eax, es:AmdRunCodeOnApFunction
+    mov   (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
+    pop   es
+
+    ; Call in to the AmdLateRunApTask dispatcher
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    push  es
+    mov   bx, SEG AmdRunCodeOnApStatus
+    mov   es, bx
+    mov   es:AmdRunCodeOnApStatus, eax
+    pop   es
+
+    ; Allow AGESA to free the space used by AmdLateRunApTask
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+
+AmdLateRunApTaskWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdRunFuncOnAp (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
+;     EDX - Local APIC ID of the target core.
+;     ESI - Pointer to an AP_EXE_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 FunctionNumber;
+;             IN       VOID *RelatedDataBlock;
+;             IN       UINT32 RelatedDataBlockLength;
+;           } AP_EXE_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E9h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This is a required function, so this value
+;                             being returned causes a critical error
+;                             response value from the AGESAT software
+;                             function and no memory initialized.
+;           AGESA_WARNING The AP did not respond.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of AP task dispatching.
+;     This function must cause the indicated function code to be executed
+;     upon the specified Application Processor. This procedure must be
+;     executed in 32-bit mode. This function is required to be implemented
+;     in the host environment.
+;
+;   Dependencies:
+;     The host environment must route execution to the target AP and
+;     have that AP call the"AmdLateRunApTask" entry point.
+;
+AmdRunFuncOnAp PROC NEAR PUBLIC
+
+    push  es
+    mov   ax, SEG AmdRunCodeOnApDataPointer
+    mov   es, ax
+    mov   eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
+    mov   es:AmdRunCodeOnApDataPointer, eax
+    mov   eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
+    mov   es:AmdRunCodeOnApDataSize, eax
+    mov   eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
+    mov   es:AmdRunCodeOnApFunction, eax
+    mov   eax, AGESA_UNSUPPORTED
+    mov   es:AmdRunCodeOnApStatus, eax
+    pop   es
+
+    call  myRunFuncOnAp
+
+    push  es
+    mov   ax, SEG AmdRunCodeOnApStatus
+    mov   es, ax
+    mov   eax, es:AmdRunCodeOnApStatus
+    pop   es
+    ret
+AmdRunFuncOnAp ENDP
+
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCalloutRouterPost
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The call out router function for AmdInitEnv,
+;     AmdInitMid, AmdInitLate, AmdS3Save, and
+;     AmdS3LateRestore.
+;
+;   Dependencies:
+;     None
+;
+AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
+    xor   ax, ax
+    mov   ds, ax
+    mov   es, ax
+    lea   di, cs:CalloutRouterTablePost
+    mov   eax, AGESA_UNSUPPORTED
+
+loopThruTable:
+    cmp   di, OFFSET cs:CalloutRouterTablePostEnd
+    jae   amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
+    cmp   ecx, cs:[di].sOemCallout.FuncName
+    je    FoundMatch
+    add   di, SIZEOF sOemCallout
+    jmp   loopThruTable
+
+FoundMatch:
+    mov   bx, cs:[di].sOemCallout.FuncPtr
+    call  bx
+
+amdCpuCalloutExit:
+    ret
+AmdCalloutRouterPost ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the callout dispatch table for the POST segment
+;----------------------------------------------------------------------------
+
+CalloutRouterTablePost LABEL BYTE
+    ;; Add entries as desired.
+    sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
+    sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
+    sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
+    sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
+CalloutRouterTablePostEnd LABEL BYTE
+
+AMD_POST_END
+
+
+;----------------------------------------------------------------------------
+;    CPU DATA SEGMENT
+; This segment must be writable, and present at the time that
+; AmdInitLate is run.
+;----------------------------------------------------------------------------
+
+CPU_DATASEG_START
+
+  ;; Data used to store pointers for later use by the host environment.
+  PUBLIC AmdAcpiSratPointer
+  PUBLIC AmdAcpiSratSize
+  PUBLIC AmdAcpiSlitPointer
+  PUBLIC AmdAcpiSlitSize
+  PUBLIC AmdAcpiSsdtPointer
+  PUBLIC AmdAcpiSsdtSize
+  PUBLIC AmdAcpiWheaMcePointer
+  PUBLIC AmdAcpiWheaMceSize
+  PUBLIC AmdAcpiWheaCmcPointer
+  PUBLIC AmdAcpiWheaCmcSize
+  PUBLIC AmdDmiInfoPointer
+  AmdAcpiSratPointer     DWORD ?
+  AmdAcpiSratSize        DWORD ?
+  AmdAcpiSlitPointer     DWORD ?
+  AmdAcpiSlitSize        DWORD ?
+  AmdAcpiSsdtPointer     DWORD ?
+  AmdAcpiSsdtSize        DWORD ?
+  AmdAcpiWheaMcePointer  DWORD ?
+  AmdAcpiWheaMceSize     DWORD ?
+  AmdAcpiWheaCmcPointer  DWORD ?
+  AmdAcpiWheaCmcSize     DWORD ?
+  AmdDmiInfoPointer      DWORD ?
+
+  ;; Data used for communication between the AP and the BSP.
+  PUBLIC AmdRunCodeOnApDataPointer
+  PUBLIC AmdRunCodeOnApDataSize
+  PUBLIC AmdRunCodeOnApFunction
+  PUBLIC AmdRunCodeOnApStatus
+  AmdRunCodeOnApDataPointer  DWORD ?
+  AmdRunCodeOnApDataSize     DWORD ?
+  AmdRunCodeOnApFunction     DWORD ?
+  AmdRunCodeOnApStatus       DWORD ?
+
+CPU_DATASEG_END
+
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
new file mode 100755
index 0000000000..1dbe4406f8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
@@ -0,0 +1,243 @@
+/**
+ * @file
+ *
+ * AMD Hob Transfer functions.
+ *
+ * Contains code that copy Heap to temp memory or main memory.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 7532 $   @e \$Date: 2008-08-22 04:50:27 +0800 (Fri, 22 Aug 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "cpuPostInit.h"
+#include "cpuEnvInit.h"
+#include "Filecode.h"
+#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CopyHeapToTempRamAtPost
+ *
+ *     This function copies BSP heap content to RAM
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+CopyHeapToTempRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  i;
+  UINT32  *HeapBufferPtr;
+  UINT32  *HeapRamPtr;
+  UINT64  MsrData;
+  HEAP_MANAGER *HeapManagerPtr;
+  BUFFER_NODE *CurrentNodePtr;
+  AGESA_STATUS IgnoredSts;
+  UINT32  AmdHeapRamAddress;
+  UINT32  HeapRamFixMtrr;
+
+  AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
+
+  //
+  //If the user define address above 1M, Mem Init has already set
+  //whole available memory as WB cacheable.
+  //
+  if (AmdHeapRamAddress < 0x100000) {
+    // Region below 1MB
+    // Fixed MTTR region
+    // turn on modification bit
+    LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+    MsrData |= 0x80000;
+    LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+    if (AmdHeapRamAddress >= 0xC0000) {
+      //
+      // 0xC0000 ~ 0xFFFFF
+      //
+      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
+      MsrData = AMD_MTRR_FIX4K_WB_DRAM;
+      LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
+      LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
+    } else if (AmdHeapRamAddress >= 0x80000) {
+      //
+      // 0x80000~0xBFFFF
+      //
+      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
+      MsrData = AMD_MTRR_FIX16K_WB_DRAM;
+      LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
+    } else {
+      //
+      // 0x0 ~ 0x7FFFF
+      //
+      LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
+      MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
+      MsrData = MsrData | (AMD_MTRR_FIX64K_WB_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
+      LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
+    }
+
+    // Turn on MTTR enable bit and turn off modification bit
+    LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+    MsrData &= 0xFFFFFFFFFFF7FFFFull;
+    LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+  }
+
+  // Copying Heap content
+  if (IsBsp (StdHeader, &IgnoredSts)) {
+    HeapBufferPtr  = (UINT32 *)AMD_HEAP_START_ADDRESS;
+    HeapRamPtr  = (UINT32 *)AmdHeapRamAddress;
+    for (i = 0; i < AMD_HEAP_COPY_SIZE_DWORD; i++) {
+      *HeapRamPtr = *HeapBufferPtr;
+      HeapBufferPtr++;
+      HeapRamPtr++;
+    }
+    // re-calculate NextNodePtr of every Heap
+    HeapManagerPtr = (HEAP_MANAGER *) AmdHeapRamAddress;
+    if (HeapManagerPtr->AvailableSize != AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER)) {
+      CurrentNodePtr = (BUFFER_NODE *) (AmdHeapRamAddress + sizeof (HEAP_MANAGER));
+      while (CurrentNodePtr != NULL) {
+        if (CurrentNodePtr->NextNodePtr != NULL) {
+          CurrentNodePtr->NextNodePtr = (BUFFER_NODE *) ((UINT8 *) CurrentNodePtr->NextNodePtr - AMD_HEAP_START_ADDRESS + AmdHeapRamAddress);
+        }
+        CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CopyHeapToMainRamAtPost
+ *
+ *    This function copies Temp Ram heap content to Main Ram
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+CopyHeapToMainRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 * HeapTempRamPtr;
+  UINT8 * HeapMainRamPtr;
+  UINT32 i;
+  HEAP_MANAGER *HeapManagerPtr;
+  BUFFER_NODE  *CurrentNodePtr;
+  AGESA_BUFFER_PARAMS agesaAllocateBuffer;
+  AGESA_STATUS AgesaStatus;
+  UINT32  AmdHeapRamAddress;
+
+  AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
+  // initialize StdHeader
+  AgesaStatus = AGESA_SUCCESS;
+  agesaAllocateBuffer.StdHeader = *StdHeader;
+
+  HeapManagerPtr = (HEAP_MANAGER *) AmdHeapRamAddress;
+  CurrentNodePtr = (BUFFER_NODE *) (AmdHeapRamAddress + sizeof (HEAP_MANAGER));
+
+  if (HeapManagerPtr->AvailableSize != AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER)) {
+    while (CurrentNodePtr != NULL) {
+      // allocate buffer
+      agesaAllocateBuffer.BufferHandle = CurrentNodePtr->BufferHandle;
+      agesaAllocateBuffer.BufferLength = CurrentNodePtr->BufferSize;
+      AgesaStatus = AgesaAllocateBuffer (0, &agesaAllocateBuffer);
+
+      if (AgesaStatus == AGESA_SUCCESS) {
+        // copy heap from temp ram to real ram
+        HeapMainRamPtr = (UINT8 *) agesaAllocateBuffer.BufferPointer;
+        HeapTempRamPtr = (UINT8 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE));
+        for (i = 0; i < CurrentNodePtr->BufferSize; i++) {
+          *HeapMainRamPtr = *HeapTempRamPtr;
+          HeapMainRamPtr++;
+          HeapTempRamPtr++;
+        }
+      } else {
+        return AgesaStatus;
+      }
+      CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+    }
+  }
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
new file mode 100755
index 0000000000..c8985b0801
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
@@ -0,0 +1,2466 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * Agesa structures and definitions
+; *
+; * Contains AMD AGESA core interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 47176 $   @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $
+;
+; ****************************************************************************
+; *
+; * Copyright (c) 2011, Advanced Micro Devices, Inc.
+; * All rights reserved.
+; * 
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *     * Redistributions of source code must retain the above copyright
+; *       notice, this list of conditions and the following disclaimer.
+; *     * Redistributions in binary form must reproduce the above copyright
+; *       notice, this list of conditions and the following disclaimer in the
+; *       documentation and/or other materials provided with the distribution.
+; *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+; *       its contributors may be used to endorse or promote products derived 
+; *       from this software without specific prior written permission.
+; * 
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * 
+; *
+; **************************************************************************
+
+INCLUDE amd.inc
+UINT64    TEXTEQU     <QWORD>
+UINT32    TEXTEQU     <DWORD>
+UINT16    TEXTEQU     <WORD>
+UINT8     TEXTEQU     <BYTE>
+CHAR8     TEXTEQU     <BYTE>
+BOOLEAN   TEXTEQU     <BYTE>
+POINTER   TEXTEQU     <DWORD>
+
+ ; AGESA Types and Definitions
+
+
+
+ ; AGESA BASIC CALLOUTS
+    AGESA_MEM_RELEASE           EQU    00028000h
+
+ ; AGESA ADVANCED CALLOUTS, Processor
+    AGESA_CHECK_UMA             EQU    00028100h
+    AGESA_DO_RESET              EQU    00028101h
+    AGESA_ALLOCATE_BUFFER       EQU    00028102h
+    AGESA_DEALLOCATE_BUFFER     EQU    00028103h
+    AGESA_LOCATE_BUFFER         EQU    00028104h
+    AGESA_RUNFUNC_ONAP          EQU    00028105h
+
+ ; AGESA ADVANCED CALLOUTS, HyperTransport
+
+ ; AGESA ADVANCED CALLOUTS, Memory
+    AGESA_READ_SPD              EQU    00028140h
+    AGESA_HOOKBEFORE_DRAM_INIT  EQU    00028141h
+    AGESA_HOOKBEFORE_DQS_TRAINING       EQU    00028142h
+    AGESA_READ_SPD_RECOVERY     EQU    00028143h
+    AGESA_HOOKBEFORE_EXIT_SELF_REF      EQU    00028144h
+
+ ; AGESA IDS CALLOUTS
+    AGESA_GET_IDS_INIT_DATA     EQU    00028200h
+
+ ; AGESA GNB CALLOUTS
+    AGESA_GNB_PCIE_SLOT_RESET   EQU    00028301h
+; ------------------------------------------------------------------------
+
+ ; HyperTransport Interface
+
+
+
+; -----------------------------------------------------------------------------
+                         ; HT DEFINITIONS AND MACROS
+
+; -----------------------------------------------------------------------------
+
+
+ ; Width equates for call backs
+    HT_WIDTH_8_BITS             EQU    8
+    HT_WIDTH_16_BITS            EQU    16
+    HT_WIDTH_4_BITS             EQU    4
+    HT_WIDTH_2_BITS             EQU    2
+    HT_WIDTH_NO_LIMIT           EQU    HT_WIDTH_16_BITS
+
+ ; Frequency Limit equates for call backs which take a frequency supported mask.
+    HT_FREQUENCY_LIMIT_200M     EQU    1
+    HT_FREQUENCY_LIMIT_400M     EQU    7
+    HT_FREQUENCY_LIMIT_600M     EQU    1Fh
+    HT_FREQUENCY_LIMIT_800M     EQU    3Fh
+    HT_FREQUENCY_LIMIT_1000M    EQU    7Fh
+    HT_FREQUENCY_LIMIT_HT1_ONLY EQU    7Fh
+    HT_FREQUENCY_LIMIT_1200M    EQU    0FFh
+    HT_FREQUENCY_LIMIT_1400M    EQU    1FFh
+    HT_FREQUENCY_LIMIT_1600M    EQU    3FFh
+    HT_FREQUENCY_LIMIT_1800M    EQU    7FFh
+    HT_FREQUENCY_LIMIT_2000M    EQU    0FFFh
+    HT_FREQUENCY_LIMIT_2200M    EQU    1FFFh
+    HT_FREQUENCY_LIMIT_2400M    EQU    3FFFh
+    HT_FREQUENCY_LIMIT_2600M    EQU    7FFFh
+    HT_FREQUENCY_LIMIT_2800M    EQU    27FFFh
+    HT_FREQUENCY_LIMIT_3000M    EQU    67FFFh
+    HT_FREQUENCY_LIMIT_3200M    EQU    0E7FFFh
+    HT_FREQUENCY_LIMIT_3600M    EQU    1E7FFFh
+    HT_FREQUENCY_LIMIT_MAX      EQU    HT_FREQUENCY_LIMIT_3600M
+    HT_FREQUENCY_NO_LIMIT       EQU    0FFFFFFFFh
+
+ ; Unit ID Clumping special values
+    HT_CLUMPING_DISABLE         EQU    00000000h
+    HT_CLUMPING_NO_LIMIT        EQU    0FFFFFFFFh
+
+    HT_LIST_TERMINAL            EQU    0FFh
+    HT_LIST_MATCH_ANY           EQU    0FEh
+    HT_LIST_MATCH_INTERNAL_LINK EQU    0FDh
+
+ ; Event Notify definitions
+
+ ; Event definitions.
+
+ ; Coherent subfunction events
+    HT_EVENT_COH_EVENTS         EQU    10001000h
+    HT_EVENT_COH_NO_TOPOLOGY    EQU    10011000h
+    HT_EVENT_COH_OBSOLETE000    EQU    10021000h
+    HT_EVENT_COH_PROCESSOR_TYPE_MIX     EQU    10031000h
+    HT_EVENT_COH_NODE_DISCOVERED        EQU    10041000h
+    HT_EVENT_COH_MPCAP_MISMATCH EQU    10051000h
+
+ ; Non-coherent subfunction events
+    HT_EVENT_NCOH_EVENTS        EQU    10002000h
+    HT_EVENT_NCOH_BUID_EXCEED   EQU    10012000h
+    HT_EVENT_NCOH_OBSOLETE000   EQU    10022000h
+    HT_EVENT_NCOH_BUS_MAX_EXCEED        EQU    10032000h
+    HT_EVENT_NCOH_CFG_MAP_EXCEED        EQU    10042000h
+    HT_EVENT_NCOH_DEVICE_FAILED EQU    10052000h
+    HT_EVENT_NCOH_AUTO_DEPTH    EQU    10062000h
+
+ ; Optimization subfunction events
+    HT_EVENT_OPT_EVENTS         EQU    10003000h
+    HT_EVENT_OPT_REQUIRED_CAP_RETRY     EQU    10013000h
+    HT_EVENT_OPT_REQUIRED_CAP_GEN3      EQU    10023000h
+    HT_EVENT_OPT_UNUSED_LINKS   EQU    10033000h
+    HT_EVENT_OPT_LINK_PAIR_EXCEED       EQU    10043000h
+
+ ; HW Fault events
+    HT_EVENT_HW_EVENTS          EQU    10004000h
+    HT_EVENT_HW_SYNCFLOOD       EQU    10014000h
+    HT_EVENT_HW_HTCRC           EQU    10024000h
+
+ ; The Recovery HT component uses 0x10005000 for events.
+ ; For consistency, we avoid that range here.
+
+    HT_MAX_NC_BUIDS             EQU    32
+; ----------------------------------------------------------------------------
+                         ; HT TYPEDEFS, STRUCTURES, ENUMS
+
+; ----------------------------------------------------------------------------
+MATCHED                 EQU     0               ; < The link matches the requested customization.
+POWERED_OFF             EQU     1               ; < Power the link off.
+UNMATCHED               EQU     2               ; < The link should be processed according to normal defaults.
+MaxFinalLinkState       EQU     3               ; < Not a final link state, use for limit checking.
+FINAL_LINK_STATE        TEXTEQU <DWORD>
+
+ ; Swap a device from its current id to a new one.
+
+BUID_SWAP_ITEM    STRUCT
+  FromId                        UINT8 ?         ; < The device responding to FromId,
+  ToId                          UINT8 ?         ; < will be moved to ToId.
+BUID_SWAP_ITEM    ENDS
+
+
+ ; Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+ ; the final in order list of device ids is provided. (There can be more swaps than devices.)
+ ; The unused entries in both are filled with 0xFF.
+
+BUID_SWAP_LIST    STRUCT
+  Swaps                         BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({})       ; < The BUID Swaps to perform
+  FinalIds                      UINT8 (HT_MAX_NC_BUIDS) DUP (?)         ; < The ordered final BUIDs, resulting from the swaps
+BUID_SWAP_LIST    ENDS
+
+
+ ; Control Manual Initialization of Non-Coherent Chains
+
+ ; This interface is checked every time a non-coherent chain is
+ ; processed.  BUID assignment may be controlled explicitly on a
+ ; non-coherent chain. Provide a swap list.  Swaps controls the
+ ; BUID assignment and FinalIds provides the device to device
+ ; Linking.  Device orientation can be detected automatically, or
+ ; explicitly.  See interface documentation for more details.
+
+ ; If a manual swap list is not supplied,
+ ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ ; based on each device's unit count.
+
+MANUAL_BUID_SWAP_LIST    STRUCT
+   ; Match fields
+  Socket                        UINT8 ?         ; < The Socket on which this chain is located
+  Link                          UINT8 ?         ; < The Link on the host for this chain
+   ; Override fields
+  SwapList                      BUID_SWAP_LIST {}       ; < The swap list
+MANUAL_BUID_SWAP_LIST    ENDS
+
+
+ ; Override options for DEVICE_CAP_OVERRIDE.
+
+ ; Specify which override actions should be performed.  For Checks, 1 means to check the item
+ ; and 0 means to skip the check.  For the override options, 1 means to apply the override and
+ ; 0 means to ignore the override.
+
+DEVICE_CAP_OVERRIDE_OPTIONS    STRUCT
+  IsCheckDevVenId               UINT32 ?
+;   IN       UINT32  IsCheckDevVenId:1;        ; < Check Match on Device/Vendor id
+;   IN       UINT32  IsCheckRevision:1;         ; < Check Match on device Revision
+;   IN       UINT32  IsOverrideWidthIn:1;       ; < Override Width In
+;   IN       UINT32  IsOverrideWidthOut:1;      ; < Override Width Out
+;   IN       UINT32  IsOverrideFreq:1;          ; < Override Frequency
+;   IN       UINT32  IsOverrideClumping:1;      ; < Override Clumping
+;   IN       UINT32  IsDoCallout:1;             ; < Make the optional callout
+DEVICE_CAP_OVERRIDE_OPTIONS    ENDS
+
+ ; Override capabilities of a device.
+
+ ; This interface is checked once for every Link on every IO device.
+ ; Provide the width and frequency capability if needed for this device.
+ ; This is used along with device capabilities, the limit interfaces, and northbridge
+ ; limits to compute the default settings.  The components of the device's PCI config
+ ; address are provided, so its settings can be consulted if need be.
+ ; The optional callout is a catch all.
+
+DEVICE_CAP_OVERRIDE    STRUCT
+   ; Match fields
+  HostSocket                    UINT8 ?         ; < The Socket on which this chain is located.
+  HostLink                      UINT8 ?         ; < The Link on the host for this chain.
+  Depth                         UINT8 ?         ; < The Depth in the I/O chain from the Host.
+  DevVenId                      UINT32 ?        ; < The Device's PCI Vendor + Device ID (offset 0x00).
+  Revision                      UINT8 ?         ; < The Device's PCI Revision field (offset 0x08).
+  Link                          UINT8 ?         ; < The Device's Link number (0 or 1).
+  Options                       DEVICE_CAP_OVERRIDE_OPTIONS {}          ; < The options for this device override.
+   ; Override fields
+  LinkWidthIn                   UINT8 ?         ; < modify to change the Link Width In.
+  LinkWidthOut                  UINT8 ?         ; < modify to change the Link Width Out.
+  FreqCap                       UINT32 ?        ; < modify to change the Link's frequency capability.
+  Clumping                      UINT32 ?        ; < modify to change Unit ID clumping support.
+  Callout                       CALLOUT_ENTRY ?         ; < optional call for really complex cases, or NULL.
+DEVICE_CAP_OVERRIDE    ENDS
+
+ ; Callout param struct for override capabilities of a device.
+
+ ; If the optional callout is implemented this param struct is passed to it.
+
+DEVICE_CAP_CALLOUT_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < The header
+   ; Match fields
+  HostSocket                    UINT8 ?         ; < The Socket on which this chain is located.
+  HostLink                      UINT8 ?         ; < The Link on the host for this chain.
+  Depth                         UINT8 ?         ; < The Depth in the I/O chain from the Host.
+  DevVenId                      UINT32 ?        ; < The Device's PCI Vendor + Device ID (offset 0x00).
+  Revision                      UINT8 ?         ; < The Device's PCI Revision field (offset 0x08).
+  Link                          UINT8 ?         ; < The Device's Link number (0 or 1).
+  PciAddress                    PCI_ADDR {}      ; < The Device's PCI Address.
+   ; Override fields
+     LinkWidthIn                POINTER ?       ; < modify to change the Link Width In.
+     LinkWidthOut               POINTER ?       ; < modify to change the Link Width Out.
+     FreqCap                    POINTER ?       ; < modify to change the Link's frequency capability.
+     Clumping                   POINTER ?       ; < modify to change Unit ID clumping support.
+DEVICE_CAP_CALLOUT_PARAMS    ENDS
+
+  ; Limits for CPU to CPU Links.
+
+  ; For each coherent connection this interface is checked once.
+  ; Provide the frequency and width if needed for this Link (usually based on board
+  ; restriction).  This is used with CPU device capabilities and northbridge limits
+  ; to compute the default settings.
+
+CPU_TO_CPU_PCB_LIMITS    STRUCT
+   ; Match fields
+  SocketA                       UINT8 ?         ; < One Socket on which this Link is located
+  LinkA                         UINT8 ?         ; < The Link on this Node
+  SocketB                       UINT8 ?         ; < The other Socket on which this Link is located
+  LinkB                         UINT8 ?         ; < The Link on that Node
+   ; Limit fields
+  ABLinkWidthLimit              UINT8 ?         ; < modify to change the Link Width A->B
+  BALinkWidthLimit              UINT8 ?         ; < modify to change the Link Width B-<A
+  PcbFreqCap                    UINT32 ?        ; < modify to change the Link's frequency capability
+CPU_TO_CPU_PCB_LIMITS    ENDS
+
+  ; Get limits for non-coherent Links.
+
+ ; For each non-coherent connection this interface is checked once.
+ ; Provide the frequency and width if needed for this Link (usually based on board
+ ; restriction).  This is used with device capabilities, device overrides, and northbridge limits
+ ; to compute the default settings.
+
+IO_PCB_LIMITS    STRUCT
+   ; Match fields
+  HostSocket                    UINT8 ?         ; < The Socket on which this Link is located
+  HostLink                      UINT8 ?         ; < The Link about to be initialized
+  Depth                         UINT8 ?         ; < The Depth in the I/O chain from the Host
+   ; Limit fields
+  DownstreamLinkWidthLimit      UINT8 ?         ; < modify to change the Link Width going away from processor
+  UpstreamLinkWidthLimit        UINT8 ?         ; < modify to change the Link Width moving toward processor
+  PcbFreqCap                    UINT32 ?        ; < modify to change the Link's frequency capability
+IO_PCB_LIMITS    ENDS
+
+  ; Manually control bus number assignment.
+
+ ; This interface is checked every time a non-coherent chain is processed.
+ ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
+ ; assignments, this interface can provide explicit control.  For each chain, provide
+ ; the bus number range to use.
+
+OVERRIDE_BUS_NUMBERS    STRUCT
+   ; Match fields
+  Socket                        UINT8 ?         ; < The Socket on which this chain is located
+  Link                          UINT8 ?         ; < The Link on the host for this chain
+   ; Override fields
+  SecBus                        UINT8 ?         ; < Secondary Bus number for this non-coherent chain
+  SubBus                        UINT8 ?         ; < Subordinate Bus number
+OVERRIDE_BUS_NUMBERS    ENDS
+
+
+  ; Ignore a Link.
+
+  ; This interface is checked every time a coherent Link is found and then every
+  ; time a non-coherent Link from a CPU is found.
+  ; Any coherent or non-coherent Link from a CPU can be ignored and not used
+  ; for discovery or initialization.  Useful for connection based systems.
+  ; (Note: not checked for IO device to IO Device Links.)
+
+IGNORE_LINK    STRUCT
+   ; Match fields
+  Socket                        UINT8 ?         ; < The Socket on which this Link is located
+  Link                          UINT8 ?         ; < The Link about to be initialized
+   ; Customization fields
+  LinkState                     FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
+IGNORE_LINK    ENDS
+
+
+  ; Skip reganging of subLinks.
+
+  ; This interface is checked whenever two subLinks are both connected to the same CPUs.
+  ; Normally, unganged sublinks between the same two CPUs are reganged.
+  ; Provide a matching structure to leave the Links unganged.
+
+SKIP_REGANG    STRUCT
+   ; Match fields
+  SocketA                       UINT8 ?         ; < One Socket on which this Link is located
+  LinkA                         UINT8 ?         ; < The Link on this Node
+  SocketB                       UINT8 ?         ; < The other Socket on which this Link is located
+  LinkB                         UINT8 ?         ; < The Link on that Node
+   ; Customization fields
+  LinkState                     FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
+SKIP_REGANG    ENDS
+
+  ; The System Socket layout, which sockets are physically connected.
+
+  ; The hardware method for Socket naming is preferred.  Use this software method only
+  ; if required.
+
+SYSTEM_PHYSICAL_SOCKET_MAP    STRUCT
+  CurrentSocket                 UINT8 ?         ; < The socket from which this connection originates.
+  CurrentLink                   UINT8 ?         ; < The Link from the source socket connects to another socket.
+  TargetSocket                  UINT8 ?         ; < The target socket which is connected on that link.
+SYSTEM_PHYSICAL_SOCKET_MAP    ENDS
+
+; ----------------------------------------------------------------------------
+
+ ; This is the input structure for AmdHtInitialize.
+
+AMD_HT_INTERFACE    STRUCT
+   ; Basic level customization
+  AutoBusStart                  UINT8 ?         ; < For automatic bus number assignment, starting bus number usually zero.
+  AutoBusMax                    UINT8 ?         ; < For automatic bus number assignment, do not assign above max.
+  AutoBusIncrement              UINT8 ?         ; < For automatic bus number assignment, each chain gets this many busses.
+
+   ; Advanced Level Customization
+  ManualBuidSwapList            POINTER ?       ; < Provide Manual Swap List, if any.
+  DeviceCapOverrideList         POINTER ?       ; < Provide Device Overrides, if any.
+  CpuToCpuPcbLimitsList         POINTER ?       ; < Provide CPU PCB Limits, if any.
+  IoPcbLimitsList               POINTER ?       ; < Provide IO PCB Limits, if any.
+  OverrideBusNumbersList        POINTER ?       ; < Provide manual Bus Number assignment, if any.
+                                                 ; < Use either auto bus numbering or override bus
+                                                 ; < numbers, not both.
+
+  IgnoreLinkList                POINTER ?       ; < Provide links to ignore, if any.
+  SkipRegangList                POINTER ?       ; < Provide links to remain unganged, if any.
+
+   ; Expert Level Customization
+  Topolist                      POINTER ?       ; < Use this topology list in addition to the built in, if not NULL.
+  SystemPhysicalSocketMap       POINTER ?
+                                                     ; < The hardware socket naming method is preferred,
+                                                     ; <  If it can't be used, this provides a software method.
+AMD_HT_INTERFACE    ENDS
+
+; -----------------------------------------------------------------------------
+
+ ; HT Recovery Interface
+
+
+
+; -----------------------------------------------------------------------------
+; *              HT Recovery DEFINITIONS AND MACROS
+; *
+; *-----------------------------------------------------------------------------
+;
+
+ ; BBHT subfunction events
+    HT_EVENT_BB_EVENTS          EQU    10005000h
+    HT_EVENT_BB_BUID_EXCEED     EQU    10015000h
+    HT_EVENT_BB_DEVICE_FAILED   EQU    10055000h
+    HT_EVENT_BB_AUTO_DEPTH      EQU    10065000h
+
+; ----------------------------------------------------------------------------
+; *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+; *
+; *----------------------------------------------------------------------------
+;
+
+
+ ; The Interface structure to Recovery HT.
+
+AMD_HT_RESET_INTERFACE    STRUCT
+  ManualBuidSwapList            POINTER ?       ; < Option to manually control SB link init
+     Depth                      UINT32 ?        ; < If auto init was used this is set to the depth of the chain,
+                                   ; < else, for manual init unmodified.
+AMD_HT_RESET_INTERFACE    ENDS
+
+; ---------------------------------------------------------------------------
+;  CPU Feature related info
+; ---------------------------------------------------------------------------
+ ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+  C1eModeDisabled       EQU    0        ; < Disabled
+  C1eModeHardware       EQU    1        ; < Hardware method
+  C1eModeMsgBased       EQU    2        ; < Message-based method
+  MaxC1eMode            EQU    3        ; < Not a valid value, used for verifying input
+PLATFORM_C1E_MODES TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+  CStateModeDisabled    EQU    0        ; < Disabled
+  CStateModeC6          EQU    1        ; < C6 State
+  MaxCStateMode         EQU    2        ; < Not a valid value, used for verifying input
+PLATFORM_CSTATE_MODES TEXTEQU  <DWORD>
+
+
+;----------------------------------------------------------------------------
+;   GNB PCIe configuration info
+;----------------------------------------------------------------------------
+
+GNB_EVENT_INVALID_CONFIGURATION                 EQU  20010000h   ; User configuration invalid
+GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION   EQU  20010001h   ; Requested lane allocation for PCIe port can not be supported
+GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION       EQU  20010002h   ; Requested incorrect PCIe port device address
+GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION        EQU  20010003h   ; Incorrect parameter in DDI link configuration
+GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION      EQU  20010004h   ; Invalid with for PCIe port or DDI link
+GNB_EVENT_INVALID_DDI_LANES_CONFIGURATION       EQU  20010005h   ; DDI lane double subscribe lanes
+GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION    EQU  20010006h   ; Requested lane allocation for DDI link(s) can not be supported
+GNB_EVENT_LINK_TRAINING_FAIL                    EQU  20020000h   ; PCIe Link training fail
+GNB_EVENT_BROKEN_LANE_RECOVERY                  EQU  20030000h   ; Broken lane workaround applied to recover link training
+GNB_EVENT_GEN2_SUPPORT_RECOVERY                 EQU  20040000h   ; Scale back to GEN1 to recover link training
+
+DESCRIPTOR_TERMINATE_LIST                       EQU  80000000h
+
+PCIe_PORT_DATA                  STRUCT
+  PortPresent                   UINT8  ?                  ; < Enable PCIe port for initialization.
+  ChannelType                   UINT8  ?                  ; < Channel type.
+                                                          ;  0 - "lowLoss",
+                                                          ;  1 - "highLoss",
+                                                          ;  2 - "mob0db",
+                                                          ;  3 - "mob3db",
+                                                          ;  4 - "extnd6db"
+                                                          ;  5 - "extnd8db"
+                                                          ;
+  DeviceNumber                  UINT8  ?                  ; < Device number for port. Available device numbers may very on different CPUs.
+  FunctionNumber                UINT8  ?                  ; < Reserved for future use
+  LinkSpeedCapability           UINT8  ?                  ; < Advertised Gen Capability
+                                                          ;  0 - Maximum supported by silicon
+                                                          ;  1 - Gen1
+                                                          ;  2 - Gen2
+                                                          ;  3 - Gen3
+                                                          ;
+  LinkSpeed                     UINT8  ?                  ; < Default boot up speed
+                                                          ;  0 - Maximum supported by silicon
+                                                          ;  1 - Gen1
+                                                          ;  2 - Gen2
+                                                          ;  3 - Gen3
+                                                          ;
+  LinkAspm                      UINT8  ?                  ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
+                                                          ;  0 - Disabled
+                                                          ;  1 - L0s only
+                                                          ;  2 - L1 only
+                                                          ;  2 - L0s and L1
+                                                          ;
+  LinkHotplug                   UINT8  ?                  ; < Hotplug control.
+                                                          ;  0 - Disabled
+                                                          ;  1 - Basic
+                                                          ;  2 - Server
+                                                          ;  3 - Enhanced
+                                                          ;
+  ResetId                       UINT8  ?                  ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                          ; identification which control reset for given port.
+                                                          ; Each port with unique GPIO should have unique ResetId assigned.
+                                                          ; All ports use same GPIO to control reset should have same ResetId assigned.
+                                                          ; see AgesaPcieSlotResetControl
+                                                          ;
+  Compliance                    UINT8  ?                  ; < Force port into compliance mode (device will not be trained, port output compliance pattern)
+PCIe_PORT_DATA                  ENDS
+
+; DDI Configuration
+PCIe_DDI_DATA                   STRUCT
+  ConnectorType                 UINT8  ?                  ; < Display Connector Type
+                                                          ;  0 - DP
+                                                          ;  1 - eDP
+                                                          ;  2 - Single Link DVI
+                                                          ;  3 - Dual  Link DVI
+                                                          ;  4 - HDMI
+                                                          ;  5 - Travis DP-to-VGA
+                                                          ;  6 - Travis DP-to-LVDS
+                                                          ;  7 - SB900 NutMeg DP-to-VGA
+                                                          ;
+  AuxIndex                      UINT8  ?                  ; < Indicates which AUX or DDC Line is used
+                                                          ;  0 - AUX1
+                                                          ;  1 - AUX2
+                                                          ;  2 - AUX3
+                                                          ;  3 - AUX4
+                                                          ;  4 - AUX5
+                                                          ;  5 - AUX6
+                                                          ;
+  HdpIndex                      UINT8  ?                  ; < Indicates which HDP pin is used
+                                                          ;  0 - HDP1
+                                                          ;  1 - HDP2
+                                                          ;  2 - HDP3
+                                                          ;  3 - HDP4
+                                                          ;  4 - HDP5
+                                                          ;  5 - HDP6
+PCIe_DDI_DATA                   ENDS
+
+
+; Engine Configuration
+PCIe_ENGINE_DATA                STRUCT
+  EngineType                    UINT8   ?                 ; < Engine type
+                                                          ;  0 -  Ignore engine configuration
+                                                          ;  1 -  PCIe port
+                                                          ;  2 -  DDI
+  StartLane                     UINT16  ?                 ; < Start lane number (in reversed configuration StartLane > EndLane).
+  EndLane                       UINT16  ?                 ; < End lane number (in reversed configuration StartLane > EndLane).
+PCIe_ENGINE_DATA                ENDS
+
+; PCIe port descriptor
+PCIe_PORT_DESCRIPTOR            STRUCT
+  Flags                         UINT32  ?                 ; < Descriptor flags
+                                                          ;  Bit31 - last descriptor in complex
+  EngineData                    PCIe_ENGINE_DATA {}       ; < Engine data
+  Port                          PCIe_PORT_DATA {}         ; < PCIe port specific configuration info
+PCIe_PORT_DESCRIPTOR            ENDS
+
+; DDI descriptor
+PCIe_DDI_DESCRIPTOR             STRUCT
+  Flags                         UINT32  ?                 ; < Descriptor flags
+  EngineData                    PCIe_ENGINE_DATA {}       ; < Engine data
+  Ddi                           PCIe_DDI_DATA {}          ; < DDI port specific configuration info
+PCIe_DDI_DESCRIPTOR             ENDS
+
+; Slot Reset Info
+PCIe_SLOT_RESET_INFO            STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}      ; < AGESA Standard Header
+  ResetId                       UINT8  ?                  ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  ResetControl                  UINT8  ?                  ; < Reset control as defined by PCIE_RESET_CONTROL
+PCIe_SLOT_RESET_INFO            ENDS
+
+
+; PCIe Complex descriptor
+PCIe_COMPLEX_DESCRIPTOR         STRUCT
+  Flags                         UINT32  ?                 ; < Descriptor flags
+                                                          ; Bit31 - last descriptor in topology
+                                                          ;
+                                                          ;
+  SocketId                      UINT32  ?                 ; < Socket Id
+  PciePortList                  POINTER ?                 ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  DdiLinkList                   POINTER ?                 ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  Reserved                      POINTER ?         ;< Reserved for future use
+PCIe_COMPLEX_DESCRIPTOR         ENDS
+
+  AssertSlotReset               EQU  0
+  DeassertSlotReset             EQU  1
+PCIE_RESET_CONTROL TEXTEQU  <DWORD>
+
+  PcieUnusedEngine              EQU  0
+  PciePortEngine                EQU  1
+  PcieDdiEngine                 EQU  2
+  MaxPcieEngine                 EQU  3                    ; < Not a valid value, used for verifying input
+PCIE_ENGINE_TYPE   TEXTEQU  <DWORD>
+
+  PcieGenMaxSupported           EQU  0
+  PcieGen1                      EQU  1
+  PcieGen2                      EQU  2
+  MaxPcieGen                    EQU  3                    ; < Not a valid value, used for verifying input
+PCIE_LINK_SPEED_CAP      TEXTEQU  <DWORD>
+
+  PsppDisabled                  EQU  0
+  PsppPerformance               EQU  1
+  PsppBalanceHigh               EQU  2
+  PsppBalanceLow                EQU  3
+  PsppPowerSaving               EQU  4
+  MaxPspp                       EQU  5                     ; < Not a valid value, used for verifying input
+PCIE_PSPP_POLICY      TEXTEQU  <DWORD>
+
+  ConnectorTypeDP               EQU  0
+  ConnectorTypeEDP              EQU  1
+  ConnectorTypeSingleLinkDVI    EQU  2
+  ConnectorTypeDualLinkDVI      EQU  3
+  ConnectorTypeHDMI             EQU  4
+  ConnectorTypeTravisDpToVga    EQU  5
+  ConnectorTypeTravisDpToLvds   EQU  6
+  ConnectorTypeNutmegDpToVga    EQU  7
+  MaxConnectorType              EQU  8                    ; < Not a valid value, used for verifying input
+PCIE_CONNECTOR_TYPE      TEXTEQU  <DWORD>
+
+  ChannelTypeLowLoss            EQU  0
+  ChannelTypeHighLoss           EQU  1
+  ChannelTypeMob0db             EQU  2
+  ChannelTypeMob3db             EQU  3
+  ChannelTypeExt6db             EQU  4
+  ChannelTypeExt8db             EQU  5
+  MaxChannelType                EQU  6                    ; < Not a valid value, used for verifying input
+PCIE_CHANNEL_TYPE  TEXTEQU  <DWORD>
+
+  AspmDisabled                  EQU  0
+  AspmL0s                       EQU  1
+  AspmL1                        EQU  2
+  AspmL0sL1                     EQU  3
+  MaxAspm                       EQU  4                    ; < Not a valid value, used for verifying input
+PCIE_ASPM_TYPE  TEXTEQU  <DWORD>
+
+  HotplugDisabled               EQU  0
+  HotplugBasic                  EQU  1
+  HotplugServer                 EQU  2
+  HotplugEnhanced               EQU  3
+  MaxHotplug                    EQU  4                    ; < Not a valid value, used for verifying input
+PCIE_HOTPLUG_TYPE TEXTEQU  <DWORD>
+
+  PortDisabled                  EQU  0
+  PortEnabled                   EQU  1
+PCIE_PORT_ENABLE  TEXTEQU  <DWORD>
+
+  Aux1                          EQU  0
+  Aux2                          EQU  1
+  Aux3                          EQU  2
+  Aux4                          EQU  3
+  Aux5                          EQU  4
+  Aux6                          EQU  5
+  MaxAux                        EQU  6                    ; < Not a valid value, used for verifying input
+PCIE_AUX_TYPE TEXTEQU  <DWORD>
+
+  Hdp1                          EQU  0
+  Hdp2                          EQU  1
+  Hdp3                          EQU  2
+  Hdp4                          EQU  3
+  Hdp5                          EQU  4
+  Hdp6                          EQU  5
+  MaxHdp                        EQU  6                   ; < Not a valid value, used for verifying input
+PCIE_HDP_TYPE TEXTEQU  <DWORD>
+
+;----------------------------------------------------------------------------
+;   GNB configuration info
+;----------------------------------------------------------------------------
+;
+
+; GNB configuration info
+GNB_CONFIGURATION              STRUCT
+  PcieComplexList              POINTER ?      ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
+                                              ;  Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
+                                              ;
+                                              ;
+                                              ;
+                                              ;  Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
+                                              ;  PCIe_PORT_DESCRIPTOR and  PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
+                                              ;  defined in arbitrary sequence:
+                                              ;  Example of topology definition for single socket system:
+                                              ;    PlatfromTopology LABEL DWORD
+                                              ;
+                                              ;    Port0_2  PCIe_PORT_DESCRIPTOR <>;
+                                              ;    Port0_3  PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
+                                              ;    ...
+                                              ;    Ddi0_A   PCIe_DDI_DESCRIPTOR <>;
+                                              ;    Ddi0_B   PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
+                                              ;    ...
+                                              ;    Cpu0     PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
+                                              ;
+                                              ;
+  PsppPolicy                   UINT8  ?       ;< PSPP (PCIe Speed Power Policy)
+                                              ;  @li @b 0 - Disabled
+                                              ;  @li @b 1 - Performance
+                                              ;  @li @b 2 - Balance-High
+                                              ;  @li @b 3 - Balance-Low
+                                              ;  @li @b 4 - Power Saving
+                                              ;
+GNB_CONFIGURATION              ENDS
+
+
+; ---------------------------------------------------------------------------
+
+; MEMORY-SPECIFIC DATA STRUCTURES
+
+; ---------------------------------------------------------------------------
+
+
+ ; AGESA MAXIMIUM VALUES
+
+   ; These Max values are used to define array sizes and associated loop
+   ; counts in the code.  They reflect the maximum values that AGESA
+   ; currently supports and does not necessarily reflect the hardware
+   ; capabilities of configuration.
+
+
+    MAX_SOCKETS_SUPPORTED       EQU    8       ; < Max number of sockets in system
+    MAX_CHANNELS_PER_SOCKET     EQU    4       ; < Max Channels per sockets
+    MAX_DIMMS_PER_CHANNEL       EQU    4       ; < Max DIMMs on a memory channel (independent of platform)
+    NUMBER_OF_DELAY_TABLES      EQU    9       ; < Number of tables defined in CH_DEF_STRUCT.
+                                               ; < Eg: UINT16  *RcvEnDlys;
+                                               ; <     UINT8   *WrDqsDlys;
+                                               ; <     UINT8   *RdDqsDlys;
+                                               ; <     UINT8   *WrDatDlys;
+                                               ; <     UINT8   *RdDqsMinDlys;
+                                               ; <     UINT8   *RdDqsMaxDlys;
+                                               ; <     UINT8   *WrDatMinDlys;
+                                               ; <     UINT8   *WrDatMaxDlys;
+    NUMBER_OF_FAILURE_MASK_TABLES EQU 1        ; < Number of failure mask tables
+    MAX_PLATFORM_TYPES          EQU    16       ; < Platform types per system
+
+    MCT_TRNG_KEEPOUT_START      EQU    00004000h        ; < base [39:8]
+    MCT_TRNG_KEEPOUT_END        EQU    00007FFFh        ; < base [39:8]
+
+    UMA_ATTRIBUTE_INTERLEAVE    EQU    80000000h    ; < Uma Region is interleaved
+
+    PSO_TABLE           TEXTEQU    <UINT8>; < Platform Configuration Table
+
+        ; AGESA DEFINITIONS
+
+        ; Many of these are derived from the platform and hardware specific definitions
+
+ ; EccSymbolSize override value
+    ECCSYMBOLSIZE_USE_BKDG      EQU    0       ; < Use BKDG Recommended Value
+    ECCSYMBOLSIZE_FORCE_X4      EQU    4       ; < Force to x4
+    ECCSYMBOLSIZE_FORCE_X8      EQU    8       ; < Force to x8
+ ; CPU Package Type
+    PT_L1                       EQU    0                     ; < L1 Package type
+    PT_M2                       EQU    1                     ; < AM Package type
+    PT_S1                       EQU    2                     ; < S1 Package type
+
+ ; Structures use to pass system Logical CPU-ID
+CPU_LOGICAL_ID    STRUCT
+  Family                        UINT64 ?        ; < Indicates logical ID Family
+  Revision                      UINT64 ?        ; < Indicates logical ID Family
+CPU_LOGICAL_ID    ENDS
+
+ ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+
+  AMD_PLATFORM_SERVER   EQU    8000h    ; < Server
+  AMD_PLATFORM_DESKTOP  EQU    10000h   ; < Desktop
+  AMD_PLATFORM_MOBILE   EQU    20000h   ; < Mobile
+AMD_PLATFORM_TYPE  TEXTEQU  <DWORD>
+
+ ; Dram technology type
+
+  DDR2_TECHNOLOGY       EQU    0        ; < DDR2 technology
+  DDR3_TECHNOLOGY       EQU    1        ; < DDR3 technology
+TECHNOLOGY_TYPE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+
+  DDR400_FREQUENCY      EQU    200      ; < DDR 400
+  DDR533_FREQUENCY      EQU    266      ; < DDR 533
+  DDR667_FREQUENCY      EQU    333      ; < DDR 667
+  DDR800_FREQUENCY      EQU    400      ; < DDR 800
+  DDR1066_FREQUENCY     EQU    533      ; < DDR 1066
+  DDR1333_FREQUENCY     EQU    667      ; < DDR 1333
+  DDR1600_FREQUENCY     EQU    800      ; < DDR 1600
+  DDR1866_FREQUENCY     EQU    933      ; < DDR 1866
+  UNSUPPORTED_DDR_FREQUENCY     EQU    934      ; < Highest limit of DDR frequency
+MEMORY_BUS_SPEED  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+
+  QUADRANK_REGISTERED   EQU    0
+  QUADRANK_UNBUFFERED   EQU    1
+QUANDRANK_TYPE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+
+  TIMING_MODE_AUTO      EQU    0        ; < Use best rate possible
+  TIMING_MODE_LIMITED   EQU    1        ; < Set user top limit
+  TIMING_MODE_SPECIFIC  EQU    2        ; < Set user specified speed
+USER_MEMORY_TIMING_MODE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
+
+  POWER_DOWN_BY_CHANNEL EQU    0
+  POWER_DOWN_BY_CHIP_SELECT     EQU    1
+POWER_DOWN_MODE  TEXTEQU  <DWORD>
+
+ ; Low voltage support
+
+  VOLT1_5 EQU 0                  ; < 1.5 Volt
+  VOLT1_35 EQU 1                 ; < 1.35 Volt
+  VOLT1_25 EQU 2                 ; < 1.25 Volt
+  VOLT_UNSUPPORTED EQU 0xFF      ; < No common voltage found
+DIMM_VOLTAGE   TEXTEQU  <DWORD>
+
+ ; UMA Mode
+
+  UMA_NONE       EQU    0        ; < UMA None
+  UMA_SPECIFIED  EQU    1        ; < UMA Specified
+  UMA_AUTO       EQU    2        ; < UMA Auto
+UMA_MODE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
+
+  NO_UMA_ALIGNED    EQU    00FFFFFFh
+  UMA_128MB_ALIGNED EQU    00FFF800h
+  UMA_256MB_ALIGNED EQU    00FFF000h
+  UMA_512MB_ALIGNED EQU    00FFE000h
+UMA_ALIGNMENT  TEXTEQU  <DWORD>
+ ; ===============================================================================
+   ; Global MCT Configuration Status Word (GStatus)
+ ; ===============================================================================
+
+  GsbMTRRshort          EQU    0        ; < Ran out of MTRRs while mapping memory
+  GsbAllECCDimms        EQU    1        ; < All banks of all Nodes are ECC capable
+  GsbDramECCDis         EQU    2        ; < Dram ECC requested but not enabled.
+  GsbSoftHole           EQU    3        ; < A Node Base gap was created
+  GsbHWHole             EQU    4        ; < A HW dram remap was created
+  GsbNodeIntlv          EQU    5        ; < Node Memory interleaving was enabled
+  GsbSpIntRemapHole     EQU    6        ; < Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW      EQU    7        ; < Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                EQU    8        ; < End of list
+GLOBAL_STATUS_FIELD  TEXTEQU  <DWORD>
+
+; ===============================================================================
+   ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+; ===============================================================================
+
+  EsbNoDimms            EQU    0        ; < No DIMMs
+  EsbSpdChkSum          EQU    1        ; < SPD Checksum fail
+  EsbDimmMismatchM      EQU    2        ; < dimm module type(buffer) mismatch
+  EsbDimmMismatchT      EQU    3        ; < dimm CL/T mismatch
+  EsbDimmMismatchO      EQU    4        ; < dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc          EQU    5        ; < SPD missing Trc or Trfc info
+  EsbNoCycTime          EQU    6        ; < SPD missing byte 23 or 25
+  EsbBkIntDis           EQU    7        ; < Bank interleave requested but not enabled
+  EsbDramECCDis         EQU    8        ; < Dram ECC requested but not enabled
+  EsbSpareDis           EQU    9        ; < Online spare requested but not enabled
+  EsbMinimumMode        EQU    10       ; < Running in Minimum Mode
+  EsbNoRcvrEn           EQU    11       ; < No DQS Receiver Enable pass window found
+  EsbSmallRcvr          EQU    12       ; < DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos           EQU    13       ; < No DQS-DQ passing positions
+  EsbSmallDqs           EQU    14       ; < DQS-DQ passing window too small
+  EsbDCBKScrubDis       EQU    15       ; < DCache scrub requested but not enabled
+
+  EsbEMPNotSupported    EQU    16       ; < Processor is not capable for EMP.
+  EsbEMPConflict        EQU    17       ; < EMP requested but cannot be enabled since
+                               ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis             EQU    18       ; < EMP requested but cannot be enabled since
+                               ; < memory size of each DCT is not a power of two.
+
+  EsbEOL                EQU    19       ; < End of list
+ERROR_STATUS_FIELD  TEXTEQU  <DWORD>
+
+; ===============================================================================
+  ; Local Configuration Status (DIE_STRUCT.Status[31:0])
+; ===============================================================================
+
+  SbRegistered          EQU    0        ; < All DIMMs are Registered
+  SbEccDimms            EQU    1        ; < All banks ECC capable
+  SbParDimms            EQU    2        ; < All banks Addr/CMD Parity capable
+  SbDiagClks            EQU    3        ; < Jedec ALL slots clock enable diag mode
+  Sb128bitmode          EQU    4        ; < DCT in 128-bit mode operation
+  Sb64MuxedMode         EQU    5        ; < DCT in 64-bit mux'ed mode.
+  Sb2TMode              EQU    6        ; < 2T CMD timing mode is enabled.
+  SbSWNodeHole          EQU    7        ; < Remapping of Node Base on this Node to create a gap.
+  SbHWHole              EQU    8        ; < Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz          EQU    9        ; < DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2         EQU    10       ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit         EQU    11       ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig           EQU    12       ; < Indicate the default setting for extended PCI configuration support
+
+  SbEOL                 EQU    13       ; < End of list
+LOCAL_STATUS_FIELD  TEXTEQU  <DWORD>
+
+
+; < CPU MSR Register definitions ------------------------------------------
+    SYS_CFG                     EQU    0C0010010h
+    TOP_MEM                     EQU    0C001001Ah
+    TOP_MEM2                    EQU    0C001001Dh
+    HWCR                        EQU    0C0010015h
+    NB_CFG                      EQU    0C001001Fh
+
+    FS_BASE                     EQU    0C0000100h
+    IORR0_BASE                  EQU    0C0010016h
+    IORR0_MASK                  EQU    0C0010017h
+    BU_CFG                      EQU    0C0011023h
+    BU_CFG2                     EQU    0C001102Ah
+    COFVID_STAT                 EQU    0C0010071h
+    TSC                         EQU    10h
+
+; ===============================================================================
+ ; SPD Data for each DIMM
+; ===============================================================================
+SPD_DEF_STRUCT    STRUCT
+  DimmPresent                   BOOLEAN ?       ; < Indicates that the DIMM is present and Data is valid
+  Data                          UINT8 (256) DUP (?)     ; < Buffer for 256 Bytes of SPD data from DIMM
+SPD_DEF_STRUCT    ENDS
+
+; ===============================================================================
+ ; Channel Definition Structure
+ ; This data structure defines entries that are specific to the channel initialization
+; ===============================================================================
+CH_DEF_STRUCT    STRUCT
+  ChannelID                     UINT8 ?         ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  TechType                      TECHNOLOGY_TYPE ?       ; < Technology type of this channel
+  ChDimmPresent                 UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is present.
+                                 ; <  DIMM#  Select Signal
+                                 ; <  0      MA0_CS_L[0, 1]
+                                 ; <  1      MB0_CS_L[0, 1]
+                                 ; <  2      MA1_CS_L[0, 1]
+                                 ; <  3      MB1_CS_L[0, 1]
+                                 ; <  4      MA2_CS_L[0, 1]
+                                 ; <  5      MB2_CS_L[0, 1]
+                                 ; <  6      MA3_CS_L[0, 1]
+                                 ; <  7      MB3_CS_L[0, 1]
+
+  DCTPtr                        POINTER ?       ; < Pointer to the DCT data of this channel.
+  MCTPtr                        POINTER ?       ; < Pointer to the node data of this channel.
+  SpdPtr                        POINTER ?       ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  DimmSpdPtr                    POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?)         ; < Array of pointers to
+                                 ; <   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  ChDimmValid                   UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is valid and is/will be configured
+  RegDimmPresent                UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is a registered DIMM
+  SODimmPresent                 UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is a SO-DIMM
+  Loads                         UINT8 ?         ; < Number of devices loading bus
+  Dimms                         UINT8 ?         ; < Number of DIMMs loading Channel
+  Ranks                         UINT8 ?         ; < Number of ranks loading Channel DATA
+  SlowMode                      BOOLEAN ?       ; < 1T or 2T CMD mode (slow access mode)
+                                 ; < FALSE = 1T
+                                 ; < TRUE = 2T
+  ; < The following pointers will be pointed to dynamically allocated buffers.
+  ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ; < Example: If DIMM and Byte based training, then
+  ; < XX is a value in Hex
+  ; <                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ; <  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ; <  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  RcvEnDlys                     POINTER ?       ; < DQS Receiver Enable Delays
+  WrDqsDlys                     POINTER ?       ; < Write DQS delays (only valid for DDR3)
+  RdDqsDlys                     POINTER ?       ; < Read Dqs delays
+  WrDatDlys                     POINTER ?       ; < Write Data delays
+  RdDqsMinDlys                  POINTER ?       ; < Minimum Window for Read DQS
+  RdDqsMaxDlys                  POINTER ?       ; < Maximum Window for Read DQS
+  WrDatMinDlys                  POINTER ?       ; < Minimum Window for Write data
+  WrDatMaxDlys                  POINTER ?       ; < Maximum Window for Write data
+  RowCount                      UINT8 ?         ; < Number of rows of the allocated buffer.
+  ColumnCount                   UINT8 ?         ; < Number of columns of the allocated buffer.
+
+  FailingBitMask                POINTER ?       ; < Table of masks to Track Failing bits
+  DctOdcCtl                     UINT32 ?        ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  DctAddrTmg                    UINT32 ?        ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  PhyRODTCSLow                  UINT32 ?        ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+  PhyRODTCSHigh                 UINT32 ?        ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+  PhyWODTCSLow                  UINT32 ?        ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+  PhyWODTCSHigh                 UINT32 ?        ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+  PhyWLODT                      UINT8 (4) DUP (?)       ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  DctEccDqsLike                 UINT16 ?        ; < DCT DQS ECC UINT8 like...
+  DctEccDqsScale                UINT8 ?         ; < DCT DQS ECC UINT8 scale
+  PtrPatternBufA                UINT16 ?        ; < Ptr on stack to aligned DQS testing pattern
+  PtrPatternBufB                UINT16 ?        ; < Ptr on stack to aligned DQS testing pattern
+  ByteLane                      UINT8 ?         ; < Current UINT8 Lane (0..7)
+  Direction                     UINT8 ?         ; < Current DQS-DQ training write direction (0=read, 1=write)
+  Pattern                       UINT8 ?         ; < Current pattern
+  DqsDelay                      UINT8 ?         ; < Current DQS delay value
+  HostBiosSrvc1                 UINT16 ?        ; < UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  HostBiosSrvc2                 UINT32 ?        ; < UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  DctMaxRdLat                   UINT16 ?        ; < Max Read Latency (ns) for the DCT
+  DIMMValidCh                   UINT8 ?         ; < DIMM# in CH
+  MaxCh                         UINT8 ?         ; < Max number of CH in system
+  Dct                           UINT8 ?         ; < Dct pointer
+  WrDatGrossH                   UINT8 ?         ; < Write Data Gross delay high value
+  DqsRcvEnGrossL                UINT8 ?         ; < DQS Receive Enable Gross Delay low
+
+  TrwtWB                        UINT8 ?         ; <  Non-SPD timing value for TrwtWB
+  CurrRcvrDctADelay             UINT8 ?         ; < for keep current RcvrEnDly
+  T1000                         UINT16 ?        ; < get the T1000 figure (cycle time (ns) * 1K)
+  DqsRcvEnPass                  UINT8 ?         ; < for TrainRcvrEn UINT8 lane pass flag
+  DqsRcvEnSaved                 UINT8 ?         ; < for TrainRcvrEn UINT8 lane saved flag
+  SeedPass1Remainder            UINT8 ?         ; < for Phy assisted DQS receiver enable training
+
+  ClToNbFlag                    UINT8 ?         ; < is used to restore ClLinesToNbDis bit after memory
+  NodeSysBase                   UINT32 ?        ; < for channel interleave usage
+  RefRawCard                    UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Array of rawcards detected
+  CtrlWrd02                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 2 values per DIMM
+  CtrlWrd03                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 3 values per DIMM
+  CtrlWrd04                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 4 values per DIMM
+  CtrlWrd05                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 5 values per DIMM
+  CtrlWrd08                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 8 values per DIMM
+
+  CsPresentDCT                  UINT16 ?        ; < For each bit n 0..7, 1 = Chip-select n is present
+  DimmMirrorPresent             UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
+  DimmSpdCse                    UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
+  DimmExclude               UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n gets excluded
+  DimmYr06                      UINT8 ?         ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  DimmWk2406                    UINT8 ?         ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  DimmPlPresent                 UINT8 ?         ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  DimmQrPresent                 UINT8 ?         ; < QuadRank DIMM present?
+  DimmDrPresent                 UINT8 ?         ; < Bitmap indicating that Dual Rank Dimms are present
+  DimmSRPresent                 UINT8 ?         ; < Bitmap indicating that Single Rank Dimms are present
+  Dimmx4Present                 UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n contains x4 data devices.
+  Dimmx8Present                 UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n contains x8 data devices.
+  Dimmx16Present                UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n contains x16 data devices.
+
+  MemClkDisMap                  POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ; <  base on this array to disable unused MemClk to save power.
+                                  ; <
+                                  ; <  The array must have 8 entries. Each entry, which associates with
+                                  ; <  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+                                  ; <    Example:
+                                  ; <    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+                                  ; <    is like below:
+                                  ; <         Bit AM3/S1g3 pin name
+                                  ; <         0   M[B,A]_CLK_H/L[0]
+                                  ; <         1   M[B,A]_CLK_H/L[1]
+                                  ; <         2   M[B,A]_CLK_H/L[2]
+                                  ; <         3   M[B,A]_CLK_H/L[3]
+                                  ; <         4   M[B,A]_CLK_H/L[4]
+                                  ; <         5   M[B,A]_CLK_H/L[5]
+                                  ; <         6   M[B,A]_CLK_H/L[6]
+                                  ; <         7   M[B,A]_CLK_H/L[7]
+                                  ; <    And platform has the following routing:
+                                  ; <         CS0   M[B,A]_CLK_H/L[4]
+                                  ; <         CS1   M[B,A]_CLK_H/L[2]
+                                  ; <         CS2   M[B,A]_CLK_H/L[3]
+                                  ; <         CS3   M[B,A]_CLK_H/L[5]
+                                  ; <    Then MemClkDisMap should be pointed to the following array:
+                                  ; <               CLK_2 CLK_3 CLK_4 CLK_5
+                                  ; <    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+                                  ; <  Each entry of the array is the bitmask of 8 chip selects.
+
+  CKETriMap                     POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of CKE pins to the DIMMs' ranks.
+                                  ; <  The array must have 2 entries. Each entry, which associates with
+                                  ; <  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ; <  AGESA will base on this array to disable unused CKE pins to save power.
+
+  ODTTriMap                     POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of ODT pins to the DIMMs' ranks.
+                                  ; <  The array must have 4 entries. Each entry, which associates with
+                                  ; <  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ; <  AGESA will base on this array to disable unused ODT pins to save power.
+
+  ChipSelTriMap                 POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of chip select pins to the DIMMs' ranks.
+                                  ; <  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ; <  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  ExtendTmp                     BOOLEAN ?       ; <  If extended temperature is supported on all dimms on a channel.
+
+  Reserved                      UINT8 (100) DUP (?)     ; < Reserved
+CH_DEF_STRUCT    ENDS
+
+; ===============================================================================
+ ; DCT Channel Timing Parameters
+ ; This data structure sets timings that are specific to the channel
+; ===============================================================================
+CH_TIMING_STRUCT    STRUCT
+  DctDimmValid                  UINT16 ?        ; < For each bit n 0..7, 1=DIMM n is valid and is/will be configured
+  DimmMirrorPresent             UINT16 ?        ; < For each bit n 0..7, 1=DIMM n is OnDimmMirror capable
+  DimmSpdCse                    UINT16 ?        ; < For each bit n 0..7, 1=DIMM n SPD checksum error
+  DimmExclude               UINT16 ?        ; < For each bit n 0..7, 1 = DIMM n gets excluded because of no common voltage is found
+  CsPresent                     UINT16 ?        ; < For each bit n 0..7, 1=Chip-select n is present
+  CsEnabled                     UINT16 ?        ; < For each bit n 0..7, 1=Chip-select n is enabled
+  CsTestFail                    UINT16 ?        ; < For each bit n 0..7, 1=Chip-select n is present but disabled
+  CsTrainFail                   UINT16 ?        ; < Bitmap showing which chipselects failed training
+  DIMM1KPage                    UINT16 ?        ; < For each bit n 0..7, 1=DIMM n contains 1K page devices.
+  DimmQrPresent                 UINT16 ?        ; < QuadRank DIMM present?
+  DimmDrPresent                 UINT16 ?        ; < Bitmap indicating that Dual Rank Dimms are present
+  DimmSRPresent                 UINT8 ?         ; < Bitmap indicating that Single Rank Dimms are present
+  Dimmx4Present                 UINT16 ?        ; < For each bit n 0..7, 1=DIMM n contains x4 data devices.
+  Dimmx8Present                 UINT16 ?        ; < For each bit n 0..7, 1=DIMM n contains x8 data devices.
+  Dimmx16Present                UINT16 ?        ; < For each bit n 0..7, 1=DIMM n contains x16 data devices.
+
+  DIMMTrcd                      UINT16 ?        ; < Minimax Trcd*40 (ns) of DIMMs
+  DIMMTrp                       UINT16 ?        ; < Minimax Trp*40 (ns) of DIMMs
+  DIMMTrtp                      UINT16 ?        ; < Minimax Trtp*40 (ns) of DIMMs
+  DIMMTras                      UINT16 ?        ; < Minimax Tras*40 (ns) of DIMMs
+  DIMMTrc                       UINT16 ?        ; < Minimax Trc*40 (ns) of DIMMs
+  DIMMTwr                       UINT16 ?        ; < Minimax Twr*40 (ns) of DIMMs
+  DIMMTrrd                      UINT16 ?        ; < Minimax Trrd*40 (ns) of DIMMs
+  DIMMTwtr                      UINT16 ?        ; < Minimax Twtr*40 (ns) of DIMMs
+  DIMMTfaw                      UINT16 ?        ; < Minimax Tfaw*40 (ns) of DIMMs
+  TargetSpeed                   UINT16 ?        ; < Target DRAM bus speed in MHz
+  Speed                         UINT16 ?        ; < DRAM bus speed in MHz
+                                  ; <  400 (MHz)
+                                  ; <  533 (MHz)
+                                  ; <  667 (MHz)
+                                  ; <  800 (MHz)
+                                  ; <  and so on...
+  CasL                          UINT8 ?         ; < CAS latency DCT setting (busclocks)
+  Trcd                          UINT8 ?         ; < DCT Trcd (busclocks)
+  Trp                           UINT8 ?         ; < DCT Trp (busclocks)
+  Trtp                          UINT8 ?         ; < DCT Trtp (busclocks)
+  Tras                          UINT8 ?         ; < DCT Tras (busclocks)
+  Trc                           UINT8 ?         ; < DCT Trc (busclocks)
+  Twr                           UINT8 ?         ; < DCT Twr (busclocks)
+  Trrd                          UINT8 ?         ; < DCT Trrd (busclocks)
+  Twtr                          UINT8 ?         ; < DCT Twtr (busclocks)
+  Tfaw                          UINT8 ?         ; < DCT Tfaw (busclocks)
+  Trfc0                         UINT8 ?         ; < DCT Logical DIMM0 Trfc
+                                  ; <  0 = 75ns (for 256Mb devs)
+                                  ; <  1 = 105ns (for 512Mb devs)
+                                  ; <  2 = 127.5ns (for 1Gb devs)
+                                  ; < 3 = 195ns (for 2Gb devs)
+                                  ; <  4 = 327.5ns (for 4Gb devs)
+  Trfc1                         UINT8 ?         ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  Trfc2                         UINT8 ?         ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  Trfc3                         UINT8 ?         ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  DctMemSize                    UINT32 ?        ; < Base[47:16], total DRAM size controlled by this DCT.
+  SlowMode                      BOOLEAN ?       ; < 1T or 2T CMD mode (slow access mode)
+                                  ; < FALSE = 1T
+                                  ; < TRUE = 2T
+  TrwtTO                        UINT8 ?         ; < DCT TrwtTO (busclocks)
+  Twrrd                         UINT8 ?         ; < DCT Twrrd (busclocks)
+  Twrwr                         UINT8 ?         ; < DCT Twrwr (busclocks)
+  Trdrd                         UINT8 ?         ; < DCT Trdrd (busclocks)
+  TrwtWB                        UINT8 ?         ; < DCT TrwtWB (busclocks)
+  TrdrdSD                       UINT8 ?         ; < DCT TrdrdSD (busclocks)
+  TwrwrSD                       UINT8 ?         ; < DCT TwrwrSD (busclocks)
+  TwrrdSD                       UINT8 ?         ; < DCT TwrrdSD (busclocks)
+  MaxRdLat                      UINT16 ?        ; < Max Read Latency
+  WrDatGrossH                   UINT8 ?         ; < Temporary variables must be removed
+  DqsRcvEnGrossL                UINT8 ?         ; < Temporary variables must be removed
+CH_TIMING_STRUCT    ENDS
+
+; ===============================================================================
+ ; Data for each DCT
+ ; This data structure defines data used to configure each DRAM controller
+; ===============================================================================
+DCT_STRUCT    STRUCT
+  Dct                           UINT8 ?         ; < Current Dct
+  Timings                       CH_TIMING_STRUCT {}     ; < Channel Timing structure
+  ChData                        POINTER ?       ; < Pointed to a dynamically allocated array of Channel structures
+  ChannelCount                  UINT8 ?         ; < Number of channel per this DCT
+DCT_STRUCT    ENDS
+
+
+; ===============================================================================
+ ; Data Structure defining each Die
+ ; This data structure contains information that is used to configure each Die
+; ===============================================================================
+DIE_STRUCT    STRUCT
+
+   ; Advanced:
+
+  NodeId                        UINT8 ?         ; < Node ID of current controller
+  SocketId                      UINT8 ?         ; < Socket ID of this Die
+  DieId                         UINT8 ?         ; < ID of this die relative to the socket
+  PciAddr                       PCI_ADDR {}      ; < Pci bus and device number of this controller.
+  ErrCode                       AGESA_STATUS ?          ; < Current error condition of Node
+                                   ; <  0x0 = AGESA_SUCCESS
+                                   ; <  0x1 = AGESA_UNSUPPORTED
+                                   ; <  0x2 = AGESA_BOUNDS_CHK
+                                   ; <  0x3 = AGESA_ALERT
+                                   ; <  0x4 = AGESA_WARNING
+                                   ; <  0x5 = AGESA_ERROR
+                                   ; <  0x6 = AGESA_CRITICAL
+                                   ; <  0x7 = AGESA_FATAL
+                                   ; <
+  ErrStatus                     BOOLEAN (EsbEOL) DUP (?)        ; < Error Status bit Field
+  Status                        BOOLEAN (SbEOL) DUP (?)         ; < Status bit Field
+  NodeMemSize                   UINT32 ?        ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+  NodeSysBase                   UINT32 ?        ; < Base[47:16] (system address) DRAM base address of this Node.
+  NodeHoleBase                  UINT32 ?        ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+  NodeSysLimit                  UINT32 ?        ; < Base[47:16] (system address) DRAM limit address of this Node.
+  DimmPresent                   UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is present.
+                                   ; <   DIMM#  Select Signal
+                                   ; <   0      MA0_CS_L[0, 1]
+                                   ; <   1      MB0_CS_L[0, 1]
+                                   ; <   2      MA1_CS_L[0, 1]
+                                   ; <   3      MB1_CS_L[0, 1]
+                                   ; <   4      MA2_CS_L[0, 1]
+                                   ; <   5      MB2_CS_L[0, 1]
+                                   ; <   6      MA3_CS_L[0, 1]
+                                   ; <   7      MB3_CS_L[0, 1]
+  DimmValid                     UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  RegDimmPresent                UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
+  DimmEccPresent                UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
+  DimmParPresent                UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+  DimmTrainFail                 UINT16 ?        ; < Bitmap showing which dimms failed training
+  ChannelTrainFail              UINT16 ?        ; < Bitmap showing the channel information about failed Chip Selects
+                                   ; <  0 in any bit field indicates Channel 0
+                                   ; <  1 in any bit field indicates Channel 1
+  Dct                           UINT8 ?         ; <  Need to be removed
+                                   ; <  DCT pointer
+  GangedMode                    BOOLEAN ?       ; < Ganged mode
+                                   ; <  0 = disabled
+                                   ; <  1 = enabled
+  LogicalCpuid                  CPU_LOGICAL_ID {}       ; < The logical CPUID of the node
+  HostBiosSrvc1                 UINT16 ?        ; < UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  HostBiosSrvc2                 UINT32 ?        ; < UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  MLoad                         UINT8 ?         ; < Need to be removed
+                                   ; < Number of devices loading MAA bus
+  MaxAsyncLat                   UINT8 ?         ; < Legacy wrapper
+  ChbD3Rcvrdly                  UINT8 ?         ; < Legacy wrapper
+  ChaMaxRdLat                   UINT16 ?        ; < Max Read Latency (ns) for DCT 0
+  ChbD3BcRcvrdly                UINT8 ?         ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  DctData                       POINTER ?       ; < Pointed to a dynamically allocated array of DCT_STRUCTs
+  DctCount                      UINT8 ?         ; < Number of DCTs per this Die
+  Reserved                      UINT8 (16) DUP (?)      ; < Reserved
+DIE_STRUCT    ENDS
+
+; *********************************************************************
+; * S3 Support structure
+; *********************************************************************
+ ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+AMD_S3_PARAMS    STRUCT
+     Signature                  UINT32 ?        ; < "ASTR" for AMD Suspend-To-RAM
+     Version                    UINT16 ?        ; < S3 Params version number
+  Flags                         UINT32 ?        ; < Indicates operation
+  NvStorage                     POINTER ?       ; < Pointer to memory critical save state data
+  NvStorageSize                 UINT32 ?        ; < Size in bytes of the NvStorage region
+  VolatileStorage               POINTER ?       ; < Pointer to remaining AMD save state data
+  VolatileStorageSize           UINT32 ?        ; < Size in bytes of the VolatileStorage region
+AMD_S3_PARAMS    ENDS
+
+; ===============================================================================
+ ; MEM_PARAMETER_STRUCT
+ ; This data structure is used to pass wrapper parameters to the memory configuration code
+; ===============================================================================
+MEM_PARAMETER_STRUCT    STRUCT
+
+   ; Basic (Return parameters)
+   ; (This section contains the outbound parameters from the memory init code)
+
+  GStatus                       BOOLEAN (GsbEOL) DUP (?)        ; < Global Status bitfield
+  HoleBase                      UINT32 ?        ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+  Sub4GCacheTop                 UINT32 ?        ; < If not zero, the 32-bit top of cacheable memory.
+  Sub1THoleBase                 UINT32 ?        ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
+  SysLimit                      UINT32 ?        ; < Limit[47:16] (system address)
+  DDR3Voltage                   DIMM_VOLTAGE ?    ; < Find support voltage and send back to platform BIOS.
+                                  ; < 0 = 1.5v
+                                  ; < 1 = 1.35v
+                                  ; < 2 = 1.2v
+                                  ; < 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
+                                  ; <        from the system.
+                                  ; <
+
+  MemData                       POINTER ?       ; < Pointer to MEM_DATA_STRUCT
+    ; Advanced (Optional parameters)
+    ; Optional (all defaults values will be initialized by the
+    ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
+    ; to the IBV/OEM to change the defaults after initialization
+    ; but prior to the main entry to the memory code):
+
+   ; Memory Map/Mgt.
+
+  BottomIo                      UINT16 ?        ; < Bottom of 32-bit IO space (8-bits)
+                                   ; <   NV_BOTTOM_IO[7:0]=Addr[31:24]
+  MemHoleRemapping              BOOLEAN ?       ; < Memory Hole Remapping (1-bit)
+                                   ; <  FALSE = disable
+                                   ; <  TRUE  = enable
+  LimitMemoryToBelow1Tb         BOOLEAN ?       ; < Limit memory address space to below 1 TB
+                                                ; <  FALSE = disable
+                                                ; <  TRUE  = enable
+   ; Dram Timing
+
+  UserTimingMode                USER_MEMORY_TIMING_MODE ?       ; < User Memclock Mode
+
+  MemClockValue                 MEMORY_BUS_SPEED ?      ; < Memory Clock Value
+
+   ; Dram Configuration
+
+  EnableBankIntlv               BOOLEAN ?       ; < Dram Bank (chip-select) Interleaving (1-bit)
+                                   ; <   FALSE =disable (AMD default)
+                                   ; <   TRUE =enable
+  EnableNodeIntlv               BOOLEAN ?       ; < Node Memory Interleaving (1-bit)
+                                   ; <   FALSE = disable (AMD default)
+                                   ; <   TRUE = enable
+  EnableChannelIntlv            BOOLEAN ?       ; < Channel Interleaving (1-bit)
+                                   ; <   FALSE = disable (AMD default)
+                                   ; <   TRUE = enable
+   ; ECC
+
+  EnableEccFeature              BOOLEAN ?       ; < enable ECC error to go into MCE
+                                   ; <   FALSE = disable (AMD default)
+                                   ; <   TRUE = enable
+   ; Dram Power
+
+  EnablePowerDown               BOOLEAN ?       ; < CKE based power down mode (1-bit)
+                                   ; <   FALSE =disable (AMD default)
+                                   ; <   TRUE =enable
+   ; Online Spare
+
+  EnableOnLineSpareCtl          BOOLEAN ?       ; < Chip Select Spare Control bit 0:
+                                   ; <  FALSE = disable Spare (AMD default)
+                                   ; <  TRUE = enable Spare
+  TableBasedAlterations         POINTER ?       ; < Point to an array of data bytes describing desired modifications to register settings.
+
+  PlatformMemoryConfiguration           POINTER ?
+                                   ; < Points to a table that contains platform specific settings
+                                   ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
+                                   ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ; < contains default conservative settings. Platform BIOS can either tweak
+                                   ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ; <
+  EnableParity                  BOOLEAN ?       ; < Parity control
+                                   ; <  TRUE = enable
+                                   ; <  FALSE = disable (AMD default)
+  EnableBankSwizzle             BOOLEAN ?       ; < BankSwizzle control
+                                   ; <  FALSE = disable
+                                   ; <  TRUE = enable  (AMD default)
+  EnableMemClr                  BOOLEAN ?       ; < Memory Clear functionality control
+                                   ; <  FALSE = disable
+                                   ; <  TRUE = enable  (AMD default)
+  ; Uma Configuration
+
+  UmaMode                       UMA_MODE ?       ; < Uma Mode
+                                   ; <  0 = None
+                                   ; <  1 = Specified
+                                   ; <  2 = Auto
+  UmaSize                       UINT32 ?       ; < The size of shared graphics dram (16-bits)
+                                   ; <  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ; <
+  UmaBase                       UINT32 ?       ; < The allocated Uma base address (32-bits)
+                                   ; <  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ; <
+
+   ; Memory Restore Feature
+
+  MemRestoreCtl                 BOOLEAN ?       ; < Memory context restore control
+                                   ; <   FALSE = perform memory init as normal (AMD default)
+                                   ; <   TRUE = restore memory context and skip training. This requires
+                                   ; <          MemContext is valid before AmdInitPost
+  SaveMemContextCtl             BOOLEAN ?       ; < Control switch to save memory context at the end of MemAuto
+                                   ; <   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ; <   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ; <           expected to call S3Save later in POST if it wants to
+                                   ; <           use memory context restore feature.
+  MemContext                    AMD_S3_PARAMS {}        ; < Memory context block describes the data that platform needs to
+                                   ; < save and restore for memory context restore feature to work.
+                                   ; < It uses the subset of S3Save block to save/restore. Hence platform
+                                   ; < may save only S3 block and uses it for both S3 resume and
+                                   ; < memory context restore.
+                                   ; <  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ; <    before AmdInitPost.
+                                   ; <  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ; <    right after AmdInitPost.
+MEM_PARAMETER_STRUCT    ENDS
+
+
+; ===============================================================================
+ ; Function definition
+ ; This data structure passes function pointers to the memory configuration code.
+ ; The wrapper can use this structure with customized versions
+; ================================================================================
+MEM_FUNCTION_STRUCT    STRUCT
+
+   ; PUBLIC required Internal functions
+
+  amdMemGetPsCfgU       POINTER ?       ; < Proc for Unbuffered DIMMs, platform specific
+  amdMemGetPsCfgR       POINTER ?       ; < Proc for Registered DIMMs, platform specific
+
+   ; PUBLIC optional functions
+
+  amdMemEccInit         POINTER ?       ; < NB proc for ECC feature
+  amdMemChipSelectInterleaveInit        POINTER ?       ; < NB proc for CS interleave feature
+  amdMemDctInterleavingInit     POINTER ?       ; < NB proc for Channel interleave feature
+  amdMemMctInterleavingInit     POINTER ?       ; < NB proc for Node interleave feature
+  amdMemParallelTraining        POINTER ?       ; < NB proc for parallel training feature
+  amdMemEarlySampleSupport      POINTER ?       ; < NB code for early sample support feature
+  amdMemMultiPartInitSupport    POINTER ?       ; < NB code for 'multi-part'
+  amdMemOnlineSpareSupport      POINTER ?       ; < NB code for On-Line Spare feature
+  amdMemUDimmInit       POINTER ?       ; < NB code for UDIMMs
+  amdMemRDimmInit       POINTER ?       ; < NB code for RDIMMs
+
+  Reserved                      UINT32 (100) DUP (?)    ; < Reserved for later function definition
+MEM_FUNCTION_STRUCT    ENDS
+
+; ===============================================================================
+ ; Socket Structure
+
+; ===============================================================================
+MEM_SOCKET_STRUCT    STRUCT
+  ChannelPtr                    POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?)       ; < Pointers to each channels training data
+
+  TimingsPtr                    POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?)       ; < Pointers to each channels timing data
+
+MEM_SOCKET_STRUCT    ENDS
+
+; ===============================================================================
+ ; MEM_DATA_STRUCT
+; ===============================================================================
+MEM_DATA_STRUCT    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < AGESA Standard Header
+
+  ParameterListPtr              POINTER ?       ; < List of input Parameters
+
+  FunctionList                  MEM_FUNCTION_STRUCT {}          ; < List of function Pointers
+
+  GetPlatformCfg        POINTER (MAX_PLATFORM_TYPES) DUP (?)    ; < look-up platform info
+
+  ErrorHandling         POINTER ?     ; < Error Handling
+
+   ; SocketList is a shortcut for IBVs to retrieve training
+   ; and timing data for each channel indexed by socket/channel,
+   ; eliminating their need to parse die/dct/channel etc.
+   ; It contains pointers to the populated data structures for
+   ; each channel and skips the channel structures that are
+   ; unpopulated. In the case of channels sharing the same DCT,
+   ; the pTimings pointers will point to the same DCT Timing data.
+
+  SocketList                    MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({})      ; < Socket list for memory code
+
+  DiesPerSystem                 POINTER ?       ; < Pointed to an array of DIE_STRUCTs
+  DieCount                      UINT8 ?         ; < Number of MCTs in the system.
+
+  SpdDataStructure              POINTER ?       ; < Pointer to SPD Data structure
+
+  PlatFormConfig              POINTER ?       ; < Pointer to Platform profile/build option config structure
+MEM_DATA_STRUCT    ENDS
+
+; ===============================================================================
+; UMA_INFO_STRUCT
+; ===============================================================================
+UMA_INFO      STRUCT
+  UmaBase         UINT64 ?        ; < UmaBase[63:0] = Addr[63:0]
+  UmaSize         UINT32 ?        ; < UmaSize[31:0] = Addr[31:0]
+  UmaAttributes   UINT32 ?        ; < Indicate the attribute of Uma
+  UmaMode         UINT8 ?         ; < Indicate the mode of Uma
+  MemClock        UINT16 ?        ; < Indicate memory running speed in MHz
+  Reserved        UINT8 (3) DUP (?)         ; < Reserved for future usage
+UMA_INFO      ENDS
+
+  ; AGESA MEMORY ERRORS
+
+ ; AGESA_ALERT Memory Errors
+MEM_ALERT_USER_TMG_MODE_OVERRULED   EQU    04010000h     ; < TIMING_MODE_SPECIFIC is requested but
+                                                       ; < cannot be applied to current configurations.
+MEM_ALERT_ORG_MISMATCH_DIMM         EQU    04010100h     ; < DIMM organization miss-match
+MEM_ALERT_BK_INT_DIS                EQU    04010200h     ; < Bank interleaving disable for internal issue
+
+ ; AGESA_ERROR Memory Errors
+MEM_ERROR_NO_DQS_POS_RD_WINDOW            EQU   04010300h     ; < No DQS Position window for RD DQS
+MEM_ERROR_SMALL_DQS_POS_RD_WINDOW         EQU   04020300h     ; < Small DQS Position window for RD DQS
+MEM_ERROR_NO_DQS_POS_WR_WINDOW            EQU   04030300h     ; < No DQS Position window for WR DQS
+MEM_ERROR_SMALL_DQS_POS_WR_WINDOW         EQU   04040300h     ; < Small DQS Position window for WR DQS
+MEM_ERROR_ECC_DIS                         EQU   04010400h     ; < ECC has been disabled as a result of an internal issue
+MEM_ERROR_DIMM_SPARING_NOT_ENABLED        EQU   04010500h     ; < DIMM sparing has not been enabled for an internal issues
+MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE         EQU   04050300h     ; < Receive Enable value is too large
+MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW       EQU   04060300h     ; < There is no DQS receiver enable window
+MEM_ERROR_DRAM_ENABLED_TIME_OUT           EQU   04010600h     ; < Time out when polling DramEnabled bit
+MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT        EQU   04010700h     ; < Time out when polling DctAccessDone bit
+MEM_ERROR_SEND_CTRL_WORD_TIME_OUT         EQU   04010800h     ; < Time out when polling SendCtrlWord bit
+MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT   EQU   04010900h     ; < Time out when polling PrefDramTrainMode bit
+MEM_ERROR_ENTER_SELF_REF_TIME_OUT         EQU   04010A00h     ; < Time out when polling EnterSelfRef bit
+MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT       EQU   04010B00h     ; < Time out when polling FreqChgInProg bit
+MEM_ERROR_EXIT_SELF_REF_TIME_OUT          EQU   04020A00h     ; < Time out when polling ExitSelfRef bit
+MEM_ERROR_SEND_MRS_CMD_TIME_OUT           EQU   04010C00h     ; < Time out when polling SendMrsCmd bit
+MEM_ERROR_SEND_ZQ_CMD_TIME_OUT            EQU   04010D00h     ; < Time out when polling SendZQCmd bit
+MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT  EQU   04010E00h     ; < Time out when polling DctExtraAccessDone bit
+MEM_ERROR_MEM_CLR_BUSY_TIME_OUT           EQU   04010F00h     ; < Time out when polling MemClrBusy bit
+MEM_ERROR_MEM_CLEARED_TIME_OUT            EQU   04020F00h     ; < Time out when polling MemCleared bit
+MEM_ERROR_FLUSH_WR_TIME_OUT               EQU   04011000h     ; < Time out when polling FlushWr bit
+MEM_ERROR_MAX_LAT_NO_WINDOW               EQU   04070300h     ; < Fail to find pass during Max Rd Latency training
+MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL   EQU   04080300h     ; < Fail to launch training code on an AP
+MEM_ERROR_PARALLEL_TRAINING_TIME_OUT      EQU   04090300h     ; < Fail to finish parallel training
+MEM_ERROR_NO_ADDRESS_MAPPING              EQU   04011100h     ; < No address mapping found for a dimm
+MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  EQU   040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
+MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU   040B0300h ; < Receive Enable value is too large and is 1 less than limit
+MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR     EQU    04011200h    ; < SPD Checksum error for NV_SPDCHK_RESTRT
+MEM_ERROR_NO_CHIPSELECT     EQU    04011300h                  ; < No chipselects found
+MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM   EQU   04011500h          ; < Unbuffered dimm is not supported at 333MHz
+
+ ; AGESA_WARNING Memory Errors
+    MEM_WARNING_UNSUPPORTED_QRDIMM      EQU    04011600h     ; < QR DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_UDIMM       EQU    04021600h     ; < U DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_SODIMM      EQU    04031600h     ; < SO-DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_X4DIMM      EQU    04041600h     ; < x4 DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_RDIMM       EQU    04051600h     ; < R DIMMs detected but not supported
+    MEM_WARNING_EMP_NOT_SUPPORTED       EQU    04011700h     ; < Processor is not capable for EMP
+    MEM_WARNING_EMP_CONFLICT    EQU    04021700h      ; < EMP cannot be enabled if channel interleaving,
+                                                        ; < bank interleaving, or bank swizzle is enabled.
+    MEM_WARNING_EMP_NOT_ENABLED EQU    04031700h      ; < Memory size is not power of two.
+    MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h  ; < Performance has been enabled, but battery life is preferred.
+    MEM_WARNING_NO_SPDTRC_FOUND EQU    04011900h      ; < No Trc timing value found in SPD of a dimm.
+    MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED     EQU     04012000h    ; < Node Interleaveing Requested, but could not be enabled
+    MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED  EQU     04012100h    ; < Channel Interleaveing Requested, but could not be enabled
+    MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED     EQU     04012200h    ; < Bank Interleaveing Requested, but could not be enabled
+    MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED     EQU     04012300h    ; < Voltage 1.35 determined, but could not be supported
+
+ ; AGESA_FATAL Memory Errors
+    MEM_ERROR_MINIMUM_MODE      EQU    04011A00h                   ; < Running in minimum mode
+    MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU    04011B00h      ; < DIMM modules are miss-matched
+    MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM    EQU    04011C00h     ; < No DIMMs have been found on system
+    MEM_ERROR_MISMATCH_DIMM_CLOCKS      EQU    04011D00h          ; < DIMM clocks miss-matched
+    MEM_ERROR_NO_CYC_TIME       EQU    04011E00h                    ; < No cycle time found
+    MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   EQU    04011F00h ; < Heap allocation error with dynamic storing of trained timings
+    MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   EQU    04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+    MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   EQU    04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
+    MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     EQU    04041F00h    ; < Heap allocation error for SPD data
+    MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     EQU    04051F00h    ; < Heap allocation error for RECEIVED_DATA during parallel training
+    MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     EQU    04061F00h    ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+    MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     EQU    04071F00h    ; < Heap allocation error for Training Data
+    MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     EQU    04081F00h   ; < Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+    MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM    EQU    04022300h    ; < No Constructor for DIMM Identify
+    MEM_ERROR_VDDIO_UNSUPPORTED   EQU   04022500h     ; < VDDIO of the dimms on the board is not supported
+
+
+ ; AGESA_CRITICAL Memory Errors
+    MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     EQU    04091F00h    ; < Heap allocation error for DMI table for DDR3
+    MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     EQU    040A1F00h    ; < Heap allocation error for DMI table for DDR2
+    MEM_ERROR_UNSUPPORTED_DIMM_CONFIG    EQU   04011400h          ; < Dimm population is not supported
+
+
+; ----------------------------------------------------------------------------
+; *
+; *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+; *
+; *----------------------------------------------------------------------------
+;
+
+
+; ----------------------------------------------------------------------------
+; *
+; *                    CPU RELATED DEFINITIONS
+; *
+; *----------------------------------------------------------------------------
+;
+
+; CPU Event definitions.
+
+; Defines used to filter CPU events based on functional blocks
+CPU_EVENT_PM_EVENT_MASK                         EQU   0FF00FF00h
+CPU_EVENT_PM_EVENT_CLASS                        EQU   008000400h
+
+;================================================================
+; CPU General events
+;    Heap allocation                    (AppFunction =     01h)
+CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            EQU   008000100h
+CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           EQU   008010100h
+CPU_ERROR_HEAP_IS_FULL                          EQU   008020100h
+CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    EQU   008030100h
+CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     EQU   008040100h
+;    BrandId                            (AppFunction =     02h)
+CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            EQU   008000200h
+;    Micro code patch                   (AppFunction =     03h)
+CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        EQU   008000300h
+;    Power management                   (AppFunction =     04h)
+CPU_EVENT_PM_PSTATE_OVERCURRENT                 EQU   008000400h
+CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             EQU   008010400h
+CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             EQU   008020400h
+;   BIST                                (AppFunction =     05h)
+CPU_EVENT_BIST_ERROR                            EQU   008000500h
+;=================================================================
+; CPU Feature events
+;    Execution cache                    (AppFunction =     21h)
+;        AGESA_CACHE_SIZE_REDUCED                          2101
+;        AGESA_CACHE_REGIONS_ACROSS_1MB                    2102
+;        AGESA_CACHE_REGIONS_ACROSS_4GB                    2103
+;        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY              2104
+;        AGESA_CACHE_START_ADDRESS_LESS_D0000              2105
+;        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB               2106
+;        AGESA_DEALLOCATE_CACHE_REGIONS                    2107
+CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      EQU   008002100h
+;    Core Leveling                      (AppFunction =     22h)
+CPU_WARNING_ADJUSTED_LEVELING_MODE              EQU   008002200h
+;    HT Assist                          (AppFunction =     23h)
+CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            EQU   008002300h
+
+; CPU Build Configuration structures and definitions
+
+; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
+AP_MTRR_SETTINGS  STRUCT
+  MsrAddr       UINT32 ?  ; < Fixed-Sized MTRR address
+  MsrData       UINT64 ?  ; < MTRR Settings
+AP_MTRR_SETTINGS  ENDS
+
+AMD_AP_MTRR_FIX64k_00000    EQU 000000250h
+AMD_AP_MTRR_FIX16k_80000    EQU 000000258h
+AMD_AP_MTRR_FIX16k_A0000    EQU 000000259h
+AMD_AP_MTRR_FIX4k_C0000     EQU 000000268h
+AMD_AP_MTRR_FIX4k_C8000     EQU 000000269h
+AMD_AP_MTRR_FIX4k_D0000     EQU 00000026Ah
+AMD_AP_MTRR_FIX4k_D8000     EQU 00000026Bh
+AMD_AP_MTRR_FIX4k_E0000     EQU 00000026Ch
+AMD_AP_MTRR_FIX4k_E8000     EQU 00000026Dh
+AMD_AP_MTRR_FIX4k_F0000     EQU 00000026Eh
+AMD_AP_MTRR_FIX4k_F8000     EQU 00000026Fh
+CPU_LIST_TERMINAL           EQU 0FFFFFFFFh
+
+; ***********************************************************************
+; *
+; *  AGESA interface Call-Out function parameter structures
+; *
+; **********************************************************************
+
+ ; Parameters structure for interface call-out AgesaAllocateBuffer
+AGESA_BUFFER_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  BufferLength                  UINT32 ?        ; < Size of buffer to allocate
+  BufferHandle                  UINT32 ?        ; < Identifier or name for the buffer
+  BufferPointer                 POINTER ?       ; < location of the created buffer
+AGESA_BUFFER_PARAMS    ENDS
+
+ ; Parameters structure for interface call-out AgesaRunCodeOnAp
+AP_EXE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  FunctionNumber                UINT32 ?        ; < Index of the procedure to execute
+  RelatedDataBlock              POINTER ?       ; < Location of data structure the procedure will use
+  RelatedBlockLength            UINT32 ?        ; < Size of the related data block
+AP_EXE_PARAMS    ENDS
+
+ ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+AGESA_READ_SPD_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < standard header
+  SocketId                      UINT8 ?         ; < Address of SPD - socket ID
+  MemChannelId                  UINT8 ?         ; < Address of SPD - memory channel ID
+  DimmId                        UINT8 ?         ; < Address of SPD - DIMM ID
+  Buffer                        POINTER ?       ; < Location where to place the SPD content
+  MemData                       POINTER ?       ; < Location of the MemData structure, for reference
+AGESA_READ_SPD_PARAMS    ENDS
+
+ ; Buffer Handles
+  AMD_DMI_INFO_BUFFER_HANDLE    EQU    000D000h ; < Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE EQU    000D001h ; < Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE EQU    000D002h ; < Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE    EQU    000D003h ; < Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE   EQU    000D004h ; < Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE   EQU    000D005h ; < Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE        EQU    000D006h ; < Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE     EQU    000D007h ; < Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE  EQU    000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
+AMD_BUFFER_HANDLE  TEXTEQU  <DWORD>
+; ***********************************************************************
+; *
+; *  AGESA interface Call-Out function prototypes
+; *
+; **********************************************************************
+
+; ***********************************************************************
+; *
+; *  AGESA interface structure definition and function prototypes
+; *
+; **********************************************************************
+
+; *********************************************************************
+; * Platform Configuration:  The parameters in boot branch function
+; *********************************************************************
+
+;   The possible platform control flow settings.
+  Nfcm                          EQU  0            ; < Normal Flow Control Mode.
+  UmaDr                         EQU  1            ; < UMA using Display Refresh flow control.
+  UmaIfcm                       EQU  2            ; < UMA using Isochronous Flow Control.
+  Ifcm                          EQU  3            ; < Isochronous Flow Control Mode (other than for UMA).
+  Iommu                         EQU  4            ; < An IOMMU is in use in the system.
+  MaxControlFlow                EQU  5            ; < Not a control flow mode, use for limit checking.
+PLATFORM_CONTROL_FLOW  TEXTEQU  <DWORD>
+
+;   Platform Deemphasis Levels.
+  DeemphasisLevelNone            EQU  0           ; < No Deemphasis.
+  DeemphasisLevelMinus3          EQU  1           ; < Minus 3 db deemphasis.
+  DeemphasisLevelMinus6          EQU  2           ; < Minus 6 db deemphasis.
+  DeemphasisLevelMinus8          EQU  3           ; < Minus 8 db deemphasis.
+  DeemphasisLevelMinus11         EQU  4           ; < Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8     EQU  5           ; < Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone                   EQU  16          ; < No DCV Deemphasis.
+  DcvLevelMinus2                 EQU  17          ; < Minus 2 db DCV deemphasis.
+  DcvLevelMinus3                 EQU  18          ; < Minus 3 db DCV deemphasis.
+  DcvLevelMinus5                 EQU  19          ; < Minus 5 db DCV deemphasis.
+  DcvLevelMinus6                 EQU  20          ; < Minus 6 db DCV deemphasis.
+  DcvLevelMinus7                 EQU  21          ; < Minus 7 db DCV deemphasis.
+  DcvLevelMinus8                 EQU  22          ; < Minus 8 db DCV deemphasis.
+  DcvLevelMinus9                 EQU  23          ; < Minus 9 db DCV deemphasis.
+  DcvLevelMinus11                EQU  24          ; < Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel     EQU  25          ; < Not a deemphasis level, use for limit checking.
+PLATFORM_DEEMPHASIS_LEVEL  TEXTEQU  <DWORD>
+
+;   Provide Deemphasis Levels for HT Links.
+;
+;   For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+;   be checked for a match. The item matches for a Socket, Link if the link frequency is
+;   is in the inclusive range HighFreq:LoFreq.
+;   AGESA does not set deemphasis in IO devices, only in processors.
+
+CPU_HT_DEEMPHASIS_LEVEL STRUCT
+  ; Match fields
+  Socket                   UINT8  ?               ; < One Socket on which this Link is located
+  Link                     UINT8  ?               ; < The Link on this Processor.
+  LoFreq                   UINT8  ?               ; < If the link is set to this frequency or greater, apply these levels, and
+  HighFreq                 UINT8  ?               ; < If the link is set to this frequency or less, apply these levels.
+  ; Value fields
+  ReceiverDeemphasis       PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
+  DcvDeemphasis            PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
+CPU_HT_DEEMPHASIS_LEVEL ENDS
+
+;   The possible platform power policy settings.
+  Performance                    EQU  0           ; < Optimize for performance.
+  BatteryLife                    EQU  1           ; < Optimize for battery life.
+  MaxPowerPolicy                 EQU  2           ; < Not a power policy mode, use for limit checking.
+PLATFORM_POWER_POLICY  TEXTEQU  <DWORD>
+
+; Platform performance settings for optimized settings.
+; Several configuration settings for the processor depend upon other parts and
+; general designer choices for the system. The determination of these data points
+; is not standard for all platforms, so the host environment needs to provide these
+; to specify how the system is to be configured.
+PERFORMANCE_PROFILE    STRUCT
+  PlatformControlFlowMode       PLATFORM_CONTROL_FLOW ?  ; < The platform's control flow mode for optimum platform performance.
+  UseHtAssist                   BOOLEAN ?       ; < HyperTransport link traffic optimization.
+  Use32ByteRefresh              BOOLEAN ?       ; < Display Refresh traffic generates 32 byte requests.
+  UseVariableMctIsocPriority    BOOLEAN ?       ; < The Memory controller will be set to Variable Isoc Priority.
+  PlatformPowerPolicy           PLATFORM_POWER_POLICY ?  ; < The platform's desired power policy
+PERFORMANCE_PROFILE    ENDS
+
+; Platform settings that describe the voltage regulator modules of the system.
+; Many power management settings are dependent upon the characteristics of the
+; on-board voltage regulator module (VRM).  The host environment needs to provide
+; these to specify how the system is to be configured.
+PLATFORM_VRM_CONFIGURATION   STRUCT
+  CurrentLimit                  UINT32 ?         ; < Vrm Current Limit.
+  LowPowerThreshold             UINT32 ?         ; < Vrm Low Power Threshold.
+  SlewRate                      UINT32 ?         ; < Vrm Slew Rate.
+  AdditionalDelay               UINT32 ?         ; < Vrm Additional Delay.
+  HiSpeedEnable                 BOOLEAN ?        ; < Select high speed VRM.
+  InrushCurrentLimit            UINT32 ?         ; < Vrm Inrush Current Limit.
+PLATFORM_VRM_CONFIGURATION   ENDS
+
+; Build Option/Configuration Boolean Structure
+BUILD_OPT_CFG    STRUCT
+  ; Build Option Area
+  VersionString                 AMD_CODE_HEADER {} ; < AMD embedded code version string
+  OptionUDimms                  BOOLEAN ?       ; < UDIMMS
+  OptionRDimms                  BOOLEAN ?       ; < RDIMMS
+  OptionEcc                     BOOLEAN ?       ; < ECC
+  OptionBankInterleave          BOOLEAN ?       ; < BANK_INTERLEAVE
+  OptionDctInterleave           BOOLEAN ?       ; < DCT_INTERLEAVE
+  OptionNodeInterleave          BOOLEAN ?       ; < NODE_INTERLEAVE
+  OptionParallelTraining        BOOLEAN ?       ; < PARALLEL_TRAINING
+  OptionOnlineSpare             BOOLEAN ?       ; < ONLINE_SPARE
+  OptionMemRestore              BOOLEAN ?       ; < MEM CONTEXT RESTORE
+  OptionMultisocket             BOOLEAN ?       ; < MULTISOCKET
+  OptionAcpiPstates             BOOLEAN ?       ; < ACPI_PSTATES
+  OptionSrat                    BOOLEAN ?       ; < SRAT
+  OptionSlit                    BOOLEAN ?       ; < SLIT
+  OptionWhea                    BOOLEAN ?       ; < WHEA
+  OptionDmi                     BOOLEAN ?       ; < DMI
+  OptionEarlySamples            BOOLEAN ?       ; < EARLY_SAMPLES
+  OptionAddrToCsTranslator      BOOLEAN ?       ; < ADDR_TO_CS_TRANSLATOR
+
+  ; Build Configuration Area
+  CfgPciMmioAddress             UINT64 ?        ; < PciMmioBase
+  CfgPciMmioSize                UINT32 ?        ; < PciMmioSize
+  CfgPlatVrmCfg                 PLATFORM_VRM_CONFIGURATION {}  ; < Several configuration settings for the voltage regulator module.
+  CfgPlatNumIoApics             UINT32 ?        ; < PlatformApicIoNumber
+  CfgMemInitPstate              UINT32 ?        ; < MemoryInitPstate
+  CfgPlatformC1eMode            PLATFORM_C1E_MODES ?  ; < PlatformC1eMode
+  CfgPlatformC1eOpData          UINT32 ?        ; < PlatformC1eOpData
+  CfgPlatformCStateMode         PLATFORM_CSTATE_MODES ?  ; < PlatformCStateMode
+  CfgPlatformCStateOpData       UINT32 ?        ; < PlatformCStateOpData
+  CfgCoreLevelingMode           UINT32 ?        ; < CoreLevelingCofig
+  CfgPerformanceProfile         PERFORMANCE_PROFILE  {}  ; < The platform's control flow mode and platform performance settings.
+  CfgPlatformDeemphasisList     POINTER  ?      ; < HT Deemphasis
+  CfgAmdPlatformType            UINT32 ?        ; < AmdPlatformType
+  CfgAmdPstateCapValue          UINT32 ?        ; < Amd pstate ceiling enabling deck
+
+  CfgMemoryBusFrequencyLimit    MEMORY_BUS_SPEED ?      ; < Memory Bus Frequency Limit
+  CfgMemoryModeUnganged         BOOLEAN ?       ; < Memory Mode Unganged
+  CfgMemoryQuadRankCapable      BOOLEAN ?       ; < Memory Quad Rank Capable
+  CfgMemoryQuadrankType         QUANDRANK_TYPE ?        ; < Memory Quadrank Type
+  CfgMemoryRDimmCapable         BOOLEAN ?       ; < Memory RDIMM Capable
+  CfgMemoryUDimmCapable         BOOLEAN ?       ; < Memory UDIMM Capable
+  CfgMemorySODimmCapable        BOOLEAN ?       ; < Memory SODimm Capable
+  CfgLimitMemoryToBelow1Tb      BOOLEAN ?       ; < Limit memory address space to below 1TB
+  CfgMemoryEnableBankInterleaving       BOOLEAN ?       ; < Memory Enable Bank Interleaving
+  CfgMemoryEnableNodeInterleaving       BOOLEAN ?       ; < Memory Enable Node Interleaving
+  CfgMemoryChannelInterleaving  BOOLEAN ?       ; < Memory Channel Interleaving
+  CfgMemoryPowerDown            BOOLEAN ?       ; < Memory Power Down
+  CfgPowerDownMode              POWER_DOWN_MODE ?       ; < Power Down Mode
+  CfgOnlineSpare                BOOLEAN ?       ; < Online Spare
+  CfgMemoryParityEnable         BOOLEAN ?       ; < Memory Parity Enable
+  CfgBankSwizzle                BOOLEAN ?       ; < Bank Swizzle
+  CfgTimingModeSelect           USER_MEMORY_TIMING_MODE ?       ; < Timing Mode Select
+  CfgMemoryClockSelect          MEMORY_BUS_SPEED ?      ; < Memory Clock Select
+  CfgDqsTrainingControl         BOOLEAN ?       ; < Dqs Training Control
+  CfgIgnoreSpdChecksum          BOOLEAN ?       ; < Ignore Spd Checksum
+  CfgUseBurstMode               BOOLEAN ?       ; < Use Burst Mode
+  CfgMemoryAllClocksOn          BOOLEAN ?       ; < Memory All Clocks On
+  CfgEnableEccFeature           BOOLEAN ?       ; < Enable ECC Feature
+  CfgEccRedirection             BOOLEAN ?       ; < ECC Redirection
+  CfgScrubDramRate              UINT16 ?        ; < Scrub Dram Rate
+  CfgScrubL2Rate                UINT16 ?        ; < Scrub L2Rate
+  CfgScrubL3Rate                UINT16 ?        ; < Scrub L3Rate
+  CfgScrubIcRate                UINT16 ?        ; < Scrub Ic Rate
+  CfgScrubDcRate                UINT16 ?        ; < Scrub Dc Rate
+  CfgEccSyncFlood               BOOLEAN ?       ; < ECC Sync Flood
+  CfgEccSymbolSize              UINT16 ?        ; < ECC Symbol Size
+  CfgHeapDramAddress            UINT64 ?        ; < Heap contents will be temporarily stored in this address during the transition
+  CfgNodeMem1GBAlign            BOOLEAN ?       ; < Node Mem 1GB boundary Alignment
+  CfgS3LateRestore              BOOLEAN ?       ; < S3 Late Restore
+  CfgAcpiPstateIndependent      BOOLEAN ?       ; < PSD method dependent/Independent
+  CfgApMtrrSettingsList         POINTER ?       ; < The AP's MTRR settings before final halt
+  CfgUmaMode                    UMA_MODE ?      ; < Uma Mode
+  CfgUmaSize                    UINT32 ?        ; < Uma Size [31:0]=Addr[47:16]
+  CfgUmaAbove4G                 BOOLEAN ?       ; < Uma Above 4G Support
+  CfgUmaAlignment               UMA_ALIGNMENT ? ; < Uma alignment
+  CfgProcessorScopeInSb         BOOLEAN ?       ; < ACPI Processor Object in \_SB scope
+  CfgProcessorScopeName0        CHAR8 ?         ; < OEM specific 1st character of processor scope name.
+  CfgProcessorScopeName1        CHAR8 ?         ; < OEM specific 2nd character of processor scope name.
+  CfgGnbHdAudio                 UINT8 ?         ; < Gnb HD Audio Enable
+  CfgAbmSupport                 UINT8 ?         ; < ABM support
+  CfgDynamicRefreshRate         UINT8 ?         ; < Dynamic refresh rate
+  CfgLcdBackLightControl        UINT8 ?         ; < Lcd back light control
+  CfgTempPcieMmioBaseAddress    UINT32 ?        ; < Temp pcie MMIO base address
+
+  Reserved                      BOOLEAN ?       ; < reserved...
+BUILD_OPT_CFG    ENDS
+
+  ; A structure containing platform specific operational characteristics. This
+  ; structure is initially populated by the initializer with a copy of the same
+  ; structure that was created at build time using the build configuration controls.
+PLATFORM_CONFIGURATION    STRUCT
+  PlatformProfile               PERFORMANCE_PROFILE {}          ; < Several configuration settings for the processor.
+  PlatformDeemphasisList        POINTER ?       ; < Deemphasis levels for the platform's HT links.
+  CoreLevelingMode              UINT8 ?         ; < Indicates how to balance the number of cores per processor.
+  C1eMode                       PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
+  C1ePlatformData               UINT32 ?        ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+  CStateMode                    PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
+  CStatePlatformData            UINT32 ?        ; < If CStateMode is C6, specifies a block of 8 free I/O ports to be used for
+                                                ; < placing the CPU in C6.
+  UserOptionDmi                 BOOLEAN ?       ; < When set to TRUE, the DMI data table is generated.
+  UserOptionPState              BOOLEAN ?       ; < When set to TRUE, the PState data tables are generated.
+  UserOptionSrat                BOOLEAN ?       ; < When set to TRUE, the SRAT data table is generated.
+  UserOptionSlit                BOOLEAN ?       ; < When set to TRUE, the SLIT data table is generated.
+  UserOptionWhea                BOOLEAN ?       ; < When set to TRUE, the WHEA data table is generated.
+  PowerCeiling                  UINT32 ?        ; <  P-State Ceiling Enabling Deck - Max power milli-watts.
+  ForcePstateIndependent        BOOLEAN ?       ; < P-State _PSD independence or dependence.
+  NumberOfIoApics               UINT32 ?        ; < Number of I/O APICs in the system
+  VrmProperties                 PLATFORM_VRM_CONFIGURATION {}  ; < Several configuration settings for the voltage regulator module.
+  ProcessorScopeInSb            BOOLEAN ?       ; < ACPI Processor Object in \_SB scope
+  ProcessorScopeName0           CHAR8 ?         ; < OEM specific 1st character of processor scope name.
+  ProcessorScopeName1           CHAR8 ?         ; < OEM specific 2nd character of processor scope name.
+PLATFORM_CONFIGURATION    ENDS
+
+ ; P-state structure for each state
+S_PSTATE_VALUES    STRUCT
+  PStateEnable                  UINT32 ?        ; < Pstate enable
+  CoreFreq                      UINT32 ?        ; < MHz
+  Power                         UINT32 ?        ; < milliWatts
+  IddValue                      UINT32 ?     ; < Current value field
+  IddDiv                        UINT32 ?       ; < Current divisor field
+S_PSTATE_VALUES    ENDS
+
+ ; P-state structure for each core
+S_PSTATE    STRUCT
+  PStateMaxValue                UINT8 ?         ; < Max p-state number in this core
+  HtcPstateLimit                UINT8 ?         ; < Htc limit
+  HtcCapable                    UINT8 ?         ; < Htc capable
+  Reserved                      UINT8 ?         ; < Reserved
+  PStateStruct                  S_PSTATE_VALUES (1) DUP ({})    ; < P state struc
+S_PSTATE    ENDS
+
+ ; P-state structure for each node
+PSTATE_LEVELING    STRUCT
+  SetPState0                    UINT8 ?         ; < If value = 0x55 (Don't set PState0)
+  TotalCoresInNode              UINT8 ?         ; < core number per node
+  PStateLevelingSizeOfBytes     UINT16 ?        ; < Size
+  OnlyOneEnabledPState          BOOLEAN ?       ; < Only P0
+  InitStruct                    UINT8 ?         ; < Init struc
+  AllCpusHaveIdenticalPStates   BOOLEAN ?       ; < Have Identical p state
+  CreateAcpiTables              UINT8 ?         ; < Create table flag
+  SocketNumber                  UINT8 ?         ; < Physical socket number of this socket
+  Reserved                      UINT8 (3) DUP (?)       ; < Reserved.
+  PStateCoreStruct              S_PSTATE (1) DUP ({})           ; < P state core struc
+PSTATE_LEVELING    ENDS
+
+ ; P-state structure for whole system
+S_CPU_AMD_PSTATE    STRUCT
+  TotalSocketInSystem           UINT32 ?        ; < Total node number in system
+  SizeOfBytes                   UINT32 ?        ; < Structure size
+  PStateLevelingStruc           PSTATE_LEVELING (1) DUP ({})    ; < P state level structure
+S_CPU_AMD_PSTATE    ENDS
+
+; *********************************************************************
+; * Structures for: AmdInitLate
+; *********************************************************************
+    PROC_VERSION_LENGTH         EQU    3h
+    MAX_DIMMS_PER_SOCKET        EQU    16
+
+
+  ; Interface Parameter Structures
+ ; DMI Type4 - Processor ID
+TYPE4_PROC_ID    STRUCT
+  ProcIdLsd                     UINT32 ?        ; < Lower half of 64b ID
+  ProcIdMsd                     UINT32 ?        ; < Upper half of 64b ID
+TYPE4_PROC_ID    ENDS
+
+ ; DMI Type 4 - Processor information
+TYPE4_DMI_INFO    STRUCT
+  T4ProcType                    UINT8 ?         ; < CPU Type
+  T4ProcFamily                  UINT8 ?         ; < Family 1
+  T4ProcId                      TYPE4_PROC_ID {}        ; < Id
+  T4Voltage                     UINT8 ?         ; < Voltage
+  T4ExternalClock               UINT16 ?        ; < External clock
+  T4MaxSpeed                    UINT16 ?        ; < Max speed
+  T4CurrentSpeed                UINT16 ?        ; < Current speed
+  T4Status                      UINT8 ?         ; < Status
+  T4ProcUpgrade                 UINT8 ?         ; < Up grade
+  T4CoreCount                   UINT8 ?         ; < Core count
+  T4CoreEnabled                 UINT8 ?         ; < Core Enable
+  T4ThreadCount                 UINT8 ?         ; < Thread count
+  T4ProcCharacteristics         UINT16 ?        ; < Characteristics
+  T4ProcFamily2                 UINT16 ?        ; < Family 2
+  T4ProcVersion                 CHAR8 (PROC_VERSION_LENGTH) DUP (?)     ; < Cpu version
+TYPE4_DMI_INFO    ENDS
+
+ ; DMI Type 7 - Cache information
+TYPE7_DMI_INFO    STRUCT
+  T7CacheCfg                    UINT16 ?        ; < Cache cfg
+  T7MaxCacheSize                UINT16 ?        ; < Max size
+  T7InstallSize                 UINT16 ?        ; < Install size
+  T7SupportedSramType           UINT16 ?        ; < Supported Sram Type
+  T7CurrentSramType             UINT16 ?        ; < Current type
+  T7CacheSpeed                  UINT8 ?         ; < Speed
+  T7ErrorCorrectionType         UINT8 ?         ; < ECC type
+  T7SystemCacheType             UINT8 ?         ; < Cache type
+  T7Associativity               UINT8 ?         ; < Associativity
+TYPE7_DMI_INFO    ENDS
+
+ ; DMI Type 16 offset 04h - Location
+
+  OtherLocation         EQU    01h      ; < Assign 01 to Other
+  UnknownLocation       EQU    2        ; < Assign 02 to Unknown
+  SystemboardOrMotherboard      EQU    3        ; < Assign 03 to systemboard or motherboard
+  IsaAddonCard          EQU    4        ; < Assign 04 to ISA add-on card
+  EisaAddonCard         EQU    5        ; < Assign 05 to EISA add-on card
+  PciAddonCard          EQU    6        ; < Assign 06 to PCI add-on card
+  McaAddonCard          EQU    7        ; < Assign 07 to MCA add-on card
+  PcmciaAddonCard       EQU    8        ; < Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard  EQU    9        ; < Assign 09 to proprietary add-on card
+  NuBus                 EQU    10       ; < Assign 0A to NuBus
+  Pc98C20AddonCard      EQU    11       ; < Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard      EQU    12       ; < Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard        EQU    13       ; < Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard EQU    14       ; < Assign 0A3 to PC-98/Local bus add-on card
+DMI_T16_LOCATION  TEXTEQU  <DWORD> ;} DMI_T16_LOCATION;
+
+ ; DMI Type 16 offset 05h - Memory Error Correction
+
+  OtherUse              EQU    01h      ; < Assign 01 to Other
+  UnknownUse            EQU    2        ; < Assign 02 to Unknown
+  SystemMemory          EQU    3        ; < Assign 03 to system memory
+  VideoMemory           EQU    4        ; < Assign 04 to video memory
+  FlashMemory           EQU    5        ; < Assign 05 to flash memory
+  NonvolatileRam        EQU    6        ; < Assign 06 to non-volatile RAM
+  CacheMemory           EQU    7        ; < Assign 07 to cache memory
+DMI_T16_USE  TEXTEQU  <DWORD> ;} DMI_T16_USE;
+
+ ; DMI Type 16 offset 07h - Maximum Capacity
+
+  Dmi16OtherErrCorrection    EQU    01h ; < Assign 01 to Other
+  Dmi16UnknownErrCorrection  EQU    2   ; < Assign 02 to Unknown
+  Dmi16NoneErrCorrection     EQU    3   ; < Assign 03 to None
+  Dmi16Parity                EQU    4   ; < Assign 04 to parity
+  Dmi16SingleBitEcc          EQU    5   ; < Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc           EQU    6   ; < Assign 06 to Multi-bit ECC
+  Dmi16Crc                   EQU    7   ; < Assign 07 to CRC
+DMI_T16_ERROR_CORRECTION  TEXTEQU  <DWORD> ;} DMI_T16_ERROR_CORRECTION;
+
+ ; DMI Type 16 - Physical Memory Array
+TYPE16_DMI_INFO    STRUCT
+  Location                      DMI_T16_LOCATION ?      ; < The physical location of the Memory Array,
+                                                        ; < whether on the system board or an add-in board.
+  Use                           DMI_T16_USE ?           ; < Identifies the function for which the array
+                                                        ; < is used.
+  MemoryErrorCorrection         DMI_T16_ERROR_CORRECTION ?      ; < The primary hardware error correction or
+                                                        ; < detection method supported by this memory array.
+  MaximumCapacity               UINT32 ?        ; < The maximum memory capacity, in kilobytes,
+                                                        ; < for the array.
+  NumberOfMemoryDevices         UINT16 ?        ; < The number of slots or sockets available
+                                                        ; < for memory devices in this array.
+TYPE16_DMI_INFO    ENDS
+
+ ; DMI Type 17 offset 0Eh - Form Factor
+  OtherFormFactor       EQU    01h      ; < Assign 01 to Other
+  UnknowFormFactor      EQU    2        ; < Assign 02 to Unknown
+  SimmFormFactor        EQU    3        ; < Assign 03 to SIMM
+  SipFormFactor         EQU    4        ; < Assign 04 to SIP
+  ChipFormFactor        EQU    5        ; < Assign 05 to Chip
+  DipFormFactor         EQU    6        ; < Assign 06 to DIP
+  ZipFormFactor         EQU    7        ; < Assign 07 to ZIP
+  ProprietaryCardFormFactor     EQU    8        ; < Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor      EQU    9        ; < Assign 09 to DIMM
+  TsopFormFactor        EQU    10       ; < Assign 10 to TSOP
+  RowOfChipsFormFactor  EQU    11       ; < Assign 11 to Row of chips
+  RimmFormFactor        EQU    12       ; < Assign 12 to RIMM
+  SodimmFormFactor      EQU    13       ; < Assign 13 to SODIMM
+  SrimmFormFactor       EQU    14       ; < Assign 14 to SRIMM
+  FbDimmFormFactor      EQU    15       ; < Assign 15 to FB-DIMM
+DMI_T17_FORM_FACTOR  TEXTEQU  <DWORD>
+
+ ; DMI Type 17 offset 12h - Memory Type
+  OtherMemType          EQU    01h      ; < Assign 01 to Other
+  UnknownMemType        EQU    2        ; < Assign 02 to Unknown
+  DramMemType           EQU    3        ; < Assign 03 to DRAM
+  EdramMemType          EQU    4        ; < Assign 04 to EDRAM
+  VramMemType           EQU    5        ; < Assign 05 to VRAM
+  SramMemType           EQU    6        ; < Assign 06 to SRAM
+  RamMemType            EQU    7        ; < Assign 07 to RAM
+  RomMemType            EQU    8        ; < Assign 08 to ROM
+  FlashMemType          EQU    9        ; < Assign 09 to Flash
+  EepromMemType         EQU    10       ; < Assign 10 to EEPROM
+  FepromMemType         EQU    11       ; < Assign 11 to FEPROM
+  EpromMemType          EQU    12       ; < Assign 12 to EPROM
+  CdramMemType          EQU    13       ; < Assign 13 to CDRAM
+  ThreeDramMemType      EQU    14       ; < Assign 14 to 3DRAM
+  SdramMemType          EQU    15       ; < Assign 15 to SDRAM
+  SgramMemType          EQU    16       ; < Assign 16 to SGRAM
+  RdramMemType          EQU    17       ; < Assign 17 to RDRAM
+  DdrMemType            EQU    18       ; < Assign 18 to DDR
+  Ddr2MemType           EQU    19       ; < Assign 19 to DDR2
+  Ddr2FbdimmMemType     EQU    20       ; < Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType           EQU    24       ; < Assign 24 to DDR3
+  Fbd2MemType           EQU    25       ; < Assign 25 to FBD2
+DMI_T17_MEMORY_TYPE  TEXTEQU  <DWORD>
+
+ ; DMI Type 17 offset 13h - Type Detail
+DMI_T17_TYPE_DETAIL    STRUCT
+  Reserved1                     UINT16 ?
+;   OUT UINT16                    Reserved1:1;                  ; < Reserved
+;   OUT UINT16                    Other:1;                      ; < Other
+;   OUT UINT16                    Unknown:1;                    ; < Unknown
+;   OUT UINT16                    FastPaged:1;                  ; < Fast-Paged
+;   OUT UINT16                    StaticColumn:1;               ; < Static column
+;   OUT UINT16                    PseudoStatic:1;               ; < Pseudo-static
+;   OUT UINT16                    Rambus:1;                     ; < RAMBUS
+;   OUT UINT16                    Synchronous:1;                ; < Synchronous
+;   OUT UINT16                    Cmos:1;                       ; < CMOS
+;   OUT UINT16                    Edo:1;                        ; < EDO
+;   OUT UINT16                    WindowDram:1;                 ; < Window DRAM
+;   OUT UINT16                    CacheDram:1;                  ; < Cache Dram
+;   OUT UINT16                    NonVolatile:1;                ; < Non-volatile
+;   OUT UINT16                    Reserved2:3;                  ; < Reserved
+DMI_T17_TYPE_DETAIL    ENDS
+
+ ; DMI Type 17 - Memory Device
+TYPE17_DMI_INFO    STRUCT
+  TotalWidth                    UINT16 ?        ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
+  DataWidth                     UINT16 ?        ; < Data Width, in bits, of this memory device.
+  MemorySize                    UINT16 ?        ; < The size of the memory device.
+  FormFactor                    DMI_T17_FORM_FACTOR ?           ; < The implementation form factor for this memory device.
+  DeviceSet                     UINT8 ?         ; < Identifies when the Memory Device is one of a set of
+                                                        ; < Memory Devices that must be populated with all devices of
+                                                        ; < the same type and size, and the set to which this device belongs.
+  DeviceLocator                 CHAR8 (8) DUP (?)       ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  BankLocator                   CHAR8 (10) DUP (?)      ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
+  MemoryType                    DMI_T17_MEMORY_TYPE ?           ; < The type of memory used in this device.
+  TypeDetail                    DMI_T17_TYPE_DETAIL {}          ; < Additional detail on the memory device type
+  Speed                         UINT16 ?        ; < Identifies the speed of the device, in megahertz (MHz).
+  ManufacturerIdCode            UINT64 ?        ; < Manufacturer ID code.
+  SerialNumber                  CHAR8 (9) DUP (?)       ; < Serial Number.
+  PartNumber                    CHAR8 (19) DUP (?)      ; < Part Number.
+  Attributes                    UINT8 ?         ; < Bits 7-4: Reserved, Bits 3-0: rank.
+TYPE17_DMI_INFO    ENDS
+
+ ; Memory DMI Type 17 and 20 - for memory use
+MEM_DMI_INFO    STRUCT
+  TotalWidth                    UINT16 ?              ; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  DataWidth                     UINT16 ?              ; ///< Data Width, in bits, of this memory device.
+  MemorySize                    UINT16 ?              ; ///< The size of the memory device.
+  FormFactor                    DMI_T17_FORM_FACTOR ? ; ///< The implementation form factor for this memory device.
+  DeviceLocator                 UINT8 ?               ; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  BankLocator                   UINT8 ?               ; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  Speed                         UINT16 ?              ; ///< Identifies the speed of the device, in megahertz (MHz).
+  ManufacturerIdCode            UINT64 ?              ; ///< Manufacturer ID code.
+  SerialNumber                  UINT8 (4) DUP (?)     ; ///< Serial Number.
+  PartNumber                    UINT8 (18) DUP (?)    ; ///< Part Number.
+  Attributes                    UINT8 ?               ; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  Socket                        UINT8 ?
+; OUT UINT8                     Socket:3              ; ///< Socket ID
+; OUT UINT8                     Channel:2             ; ///< Channel ID
+; OUT UINT8                     Dimm:2                ; ///< DIMM ID
+; OUT UINT8                     DimmPresent:1         ; ///< Dimm Present
+  StartingAddr                  UINT32 ?              ; ///< The physical address, in kilobytes, of a range
+                                                      ; ///< of memory mapped to the referenced Memory Device.
+  EndingAddr                    UINT32 ?              ; ///< The handle, or instance number, associated with
+                                                      ; ///< the Memory Device structure to which this address
+                                                      ; ///< range is mapped.
+MEM_DMI_INFO    ENDS
+
+ ; DMI Type 19 - Memory Array Mapped Address
+TYPE19_DMI_INFO    STRUCT
+  StartingAddr                  UINT32 ?        ; < The physical address, in kilobytes,
+                                                        ; < of a range of memory mapped to the
+                                                        ; < specified physical memory array.
+  EndingAddr                    UINT32 ?        ; < The physical ending address of the
+                                                        ; < last kilobyte of a range of addresses
+                                                        ; < mapped to the specified physical memory array.
+  MemoryArrayHandle             UINT16 ?        ; < The handle, or instance number, associated
+                                                        ; < with the physical memory array to which this
+                                                        ; < address range is mapped.
+  PartitionWidth                UINT8 ?         ; < Identifies the number of memory devices that
+                                                        ; < form a single row of memory for the address
+                                                        ; < partition defined by this structure.
+TYPE19_DMI_INFO    ENDS
+
+; DMI Type 20 - Memory Device Mapped Address
+TYPE20_DMI_INFO    STRUCT
+  StartingAddr                  UINT32 ?        ; < The physical address, in kilobytes, of a range
+                                                        ; < of memory mapped to the referenced Memory Device.
+  EndingAddr                    UINT32 ?        ; < The handle, or instance number, associated with
+                                                        ; < the Memory Device structure to which this address
+                                                        ; < range is mapped.
+  MemoryDeviceHandle            UINT16 ?        ; < The handle, or instance number, associated with
+                                                        ; < the Memory Device structure to which this address
+                                                        ; < range is mapped.
+  MemoryArrayMappedAddressHandle        UINT16 ?        ; < The handle, or instance number, associated
+                                                        ; < with the Memory Array Mapped Address structure to
+                                                        ; < which this device address range is mapped.
+  PartitionRowPosition          UINT8 ?         ; < Identifies the position of the referenced Memory
+                                                        ; < Device in a row of the address partition.
+  InterleavePosition            UINT8 ?         ; < The position of the referenced Memory Device in
+                                                        ; < an interleave.
+  InterleavedDataDepth          UINT8 ?         ; < The maximum number of consecutive rows from the
+                                                        ; < referenced Memory Device that are accessed in a
+                                                        ; < single interleaved transfer.
+TYPE20_DMI_INFO    ENDS
+
+ ; Collection of pointers to the DMI records
+DMI_INFO    STRUCT
+  T4                            TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 4 struc
+  T7L1                          TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 7 struc 1
+  T7L2                          TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 7 struc 2
+  T7L3                          TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 7 struc 3
+  T16                           TYPE16_DMI_INFO {}      ; < Type 16 struc
+  T17                           TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({})          ; < Type 17 struc
+  T19                           TYPE19_DMI_INFO {}      ; < Type 19 struc
+  T20                           TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({})          ; < Type 20 struc
+DMI_INFO    ENDS
+
+
+
+; *********************************************************************
+; * Interface call:  AllocateExecutionCache
+; *********************************************************************
+    MAX_CACHE_REGIONS           EQU    3
+
+ ; AllocateExecutionCache sub param structure for cached memory region
+EXECUTION_CACHE_REGION    STRUCT
+  ExeCacheStartAddr             UINT32 ?        ; < Start address
+  ExeCacheSize                  UINT32 ?        ; < Size
+EXECUTION_CACHE_REGION    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdGetAvailableExeCacheSize
+; *********************************************************************
+ ; Get available Cache remain
+AMD_GET_EXE_SIZE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+     AvailableExeCacheSize      UINT32 ?        ; < Remain size
+AMD_GET_EXE_SIZE_PARAMS    ENDS
+
+
+
+
+
+
+ ; Selection type for core leveling
+  CORE_LEVEL_LOWEST     EQU    0        ; < Level to lowest common denominator
+  CORE_LEVEL_TWO        EQU    1        ; < Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO       EQU    2        ; < Level to 1,2,4 or 8
+  CORE_LEVEL_NONE       EQU    3        ; < Do no leveling
+  CORE_LEVEL_ONE        EQU    4        ; < Level to 1 core
+  CORE_LEVEL_THREE      EQU    5        ; < Level to 3 cores
+  CORE_LEVEL_FOUR       EQU    6        ; < Level to 4 cores
+  CORE_LEVEL_FIVE       EQU    7        ; < Level to 5 cores
+  CORE_LEVEL_SIX        EQU    8        ; < Level to 6 cores
+  CORE_LEVEL_SEVEN      EQU    9        ; < Level to 7 cores
+  CORE_LEVEL_EIGHT      EQU    10       ; < Level to 8 cores
+  CORE_LEVEL_NINE       EQU    11       ; < Level to 9 cores
+  CORE_LEVEL_TEN        EQU    12       ; < Level to 10 cores
+  CORE_LEVEL_ELEVEN     EQU    13       ; < Level to 11 cores
+  CORE_LEVEL_TWELVE     EQU    14       ; < Level to 12 cores
+  CORE_LEVEL_THIRTEEN   EQU    15       ; < Level to 13 cores
+  CORE_LEVEL_FOURTEEN   EQU    16       ; < Level to 14 cores
+  CORE_LEVEL_FIFTEEN    EQU    17       ; < Level to 15 cores
+  CoreLevelModeMax      EQU    18       ; < Used for bounds checking
+CORE_LEVELING_TYPE  TEXTEQU  <DWORD>
+
+
+; ***********************************************************************
+; *
+; *  AGESA Basic Level interface structure definition and function prototypes
+; *
+; **********************************************************************
+
+; *********************************************************************
+; * Interface call:  AmdCreateStruct
+; *********************************************************************
+
+; *********************************************************************
+; * Interface call:  AmdReleaseStruct
+; *********************************************************************
+
+; *********************************************************************
+; * Interface call:  AmdInitReset
+; *********************************************************************
+ ; AmdInitReset param structure
+AMD_RESET_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  CacheRegion                   EXECUTION_CACHE_REGION (3) DUP ({})     ; < The cached memory region
+  HtConfig                      AMD_HT_RESET_INTERFACE {}       ; < The interface for Ht Recovery
+AMD_RESET_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitEarly
+; *********************************************************************
+ ; InitEarly param structure
+
+ ; Provide defaults or customizations to each service performed in AmdInitEarly.
+
+AMD_EARLY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < The standard header
+  CacheRegion                   EXECUTION_CACHE_REGION (3) DUP ({})     ; < Execution Map Interface
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  HtConfig                      AMD_HT_INTERFACE {}     ; < HyperTransport Interface
+  GnbConfig                     GNB_CONFIGURATION {}    ; < GNB configuration
+AMD_EARLY_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitPost
+; *********************************************************************
+ ; AmdInitPost param structure
+AMD_POST_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  MemConfig                     MEM_PARAMETER_STRUCT {}         ; < Memory post param
+AMD_POST_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitEnv
+; *********************************************************************
+ ; AmdInitEnv param structure
+AMD_ENV_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+AMD_ENV_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitMid
+; *********************************************************************
+ ; AmdInitMid param structure
+AMD_MID_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+AMD_MID_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitLate
+; *********************************************************************
+ ; AmdInitLate param structure
+AMD_LATE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}    ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
+     DmiTable                   POINTER ?       ; < DMI Interface
+     AcpiPState                 POINTER ?       ; < Acpi Pstate SSDT Table
+     AcpiSrat                   POINTER ?       ; < SRAT Table
+     AcpiSlit                   POINTER ?       ; < SLIT Table
+     AcpiWheaMce                POINTER ?       ; < WHEA MCE Table
+     AcpiWheaCmc                POINTER ?       ; < WHEA CMC Table
+AMD_LATE_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitRecovery
+; *********************************************************************
+ ; CPU Recovery Parameters
+AMD_CPU_RECOVERY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard Header
+  PlatformConfig                PLATFORM_CONFIGURATION {} ; < platform operational characteristics
+AMD_CPU_RECOVERY_PARAMS    ENDS
+
+ ; AmdInitRecovery param structure
+AMD_RECOVERY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  MemConfig                     MEM_PARAMETER_STRUCT {}         ; < Memory post param
+  CacheRegion                   EXECUTION_CACHE_REGION (3) DUP ({})     ; < The cached memory region. And the max cache region is 3
+  CpuRecoveryParams             AMD_CPU_RECOVERY_PARAMS {}      ; < Params for CPU related recovery init.
+AMD_RECOVERY_PARAMS    ENDS
+
+
+; *********************************************************************
+; * Interface call:  AmdInitResume
+; *********************************************************************
+ ; AmdInitResume param structure
+AMD_RESUME_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}      ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
+  S3DataBlock                   AMD_S3_PARAMS {}          ; < Save state data
+AMD_RESUME_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdS3LateRestore
+; *********************************************************************
+ ; AmdS3LateRestore param structure
+AMD_S3LATE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  S3DataBlock                   AMD_S3_PARAMS {}        ; < Save state data
+AMD_S3LATE_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdS3Save
+; *********************************************************************
+ ; AmdS3Save param structure
+AMD_S3SAVE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  S3DataBlock                   AMD_S3_PARAMS {}        ; < Standard header
+AMD_S3SAVE_PARAMS    ENDS
+
+ ; General Services API
+
+
+; *********************************************************************
+; * Interface service call:  AmdGetApicId
+; *********************************************************************
+ ; Request the APIC ID of a particular core.
+
+AMD_APIC_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+  Socket                        UINT8 ?         ; < The Core's Socket.
+  Core                          UINT8 ?         ; < The Core id.
+     IsPresent                  BOOLEAN ?       ; < The Core is present, and  ApicAddress is valid.
+     ApicAddress                UINT8 ?         ; < The Core's APIC ID.
+AMD_APIC_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdGetPciAddress
+; *********************************************************************
+ ; Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+AMD_GET_PCI_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+  Socket                        UINT8 ?         ; < The Processor's socket
+  Module                        UINT8 ?         ; < The Module in that Processor
+     IsPresent                  BOOLEAN ?       ; < The Core is present, and  PciAddress is valid.
+     PciAddress                 PCI_ADDR {}      ; < The Processor's PCI Config Space address (Function 0, Register 0)
+AMD_GET_PCI_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdIdentifyCore
+; *********************************************************************
+ ; Request the identity (Socket, Module, Core) of the current Processor Core
+
+AMD_IDENTIFY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+     Socket                     UINT8 ?         ; < The current Core's Socket
+     Module                     UINT8 ?         ; < The current Core's Processor Module
+     Core                       UINT8 ?         ; < The current Core's core id.
+AMD_IDENTIFY_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdReadEventLog
+; *********************************************************************
+ ; An Event Log Entry.
+EVENT_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+     EventClass                 UINT32 ?        ; < The severity of this event, matches AGESA_STATUS.
+     EventInfo                  UINT32 ?        ; < The unique event identifier, zero means "no event".
+     DataParam1                 UINT32 ?        ; < Data specific to the Event.
+     DataParam2                 UINT32 ?        ; < Data specific to the Event.
+     DataParam3                 UINT32 ?        ; < Data specific to the Event.
+     DataParam4                 UINT32 ?        ; < Data specific to the Event.
+EVENT_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdIdentifyDimm
+; *********************************************************************
+ ; Request the identity of dimm from system address
+
+AMD_IDENTIFY_DIMM    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+  MemoryAddress                 UINT64 ?        ; < System Address that needs to be translated to dimm identification.
+  SocketId                      UINT8 ?         ; < The socket on which the targeted address locates.
+  MemChannelId                  UINT8 ?         ; < The channel on which the targeted address locates.
+  DimmId                        UINT8 ?         ; < The dimm on which the targeted address locates.
+AMD_IDENTIFY_DIMM    ENDS
+
+ ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
+ ; and the option value.
+
+IDS_NV_ITEM    STRUCT
+  IdsNvId                       UINT16 ?        ; < Unified ID for IDS Setup Option.
+  IdsNvValue                    UINT16 ?        ; < The value of IDS Setup Option.
+IDS_NV_ITEM    ENDS
+
+ ; Data Structure for IDS CallOut Function
+IDS_CALLOUT_STRUCT    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < The Standard Header for AGESA Service
+  IdsNvPtr                      POINTER ?       ; < Memory Pointer of IDS NV Table
+  Reserved                      UINT32 ?         ; < reserved
+IDS_CALLOUT_STRUCT    ENDS
+
+
+ ; AGESA IDS NV ID Definitions
+  AGESA_IDS_DFT_VAL                            EQU    0FFFFh; <  Default value of every uninitlized NV item, the action for it will be ignored
+  AGESA_IDS_NV_END                             EQU    0FFFFh; <  Flag specify end of option structure
+
+  AGESA_IDS_EXT_ID_START                            EQU    0000h; <                                   specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE                                EQU    0001h; <                                  Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE                        EQU    0002h; <                              Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE                           EQU    0003h; <                 Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE                   EQU    0004h; <                                  Enable or disable Channel Interleave
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION                    EQU    0005h; <                 Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB                           EQU    0006h; <                         Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB                         EQU    0007h; <                  Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB                             EQU    0008h; <                 Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB                             EQU    0009h; <                 Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR                    EQU    000Ah; <          Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE                      EQU    000Bh; <                                                   Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS                          EQU    000Ch; <                            Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE                     EQU    000Dh; <                                                   Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32                  EQU    000Eh; <                                          Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN                    EQU    000Fh; <                              Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE               EQU    0010h; <                                        Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN                        EQU    0011h; <                                         Enable or disable DLLShutdown
+
+  AGESA_IDS_NV_PROBEFILTER                          EQU    0012h; <                                         Enable or Disable ProbeFilter
+
+  AGESA_IDS_NV_HDTOUT                               EQU    0013h; <                                      Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET                         EQU    0014h; <                                                        HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT                           EQU    0015h; <                                                          HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ                           EQU    0016h; <                                                     HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN                        EQU    0017h; <                                                      HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT                       EQU    0018h; <                                                     HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN                         EQU    0019h; <                                        Enable or disable GNB HD Audio
+  AGESA_IDS_EXT_ID_END                              EQU    001Ah; <                                     specify the end of external NV ID
+
+  IDS_EX_NV_ID  TEXTEQU  <DWORD>
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/amd.inc b/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
new file mode 100755
index 0000000000..d84e44d868
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/amd.inc
@@ -0,0 +1,461 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * Agesa structures and definitions
+; *
+; * Contains AMD AGESA core interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+;
+; ****************************************************************************
+; *
+; * Copyright (c) 2011, Advanced Micro Devices, Inc.
+; * All rights reserved.
+; * 
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *     * Redistributions of source code must retain the above copyright
+; *       notice, this list of conditions and the following disclaimer.
+; *     * Redistributions in binary form must reproduce the above copyright
+; *       notice, this list of conditions and the following disclaimer in the
+; *       documentation and/or other materials provided with the distribution.
+; *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+; *       its contributors may be used to endorse or promote products derived 
+; *       from this software without specific prior written permission.
+; * 
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * 
+; *
+; **************************************************************************
+
+
+UINT64    TEXTEQU     <QWORD>
+UINT32    TEXTEQU     <DWORD>
+UINT16    TEXTEQU     <WORD>
+UINT8     TEXTEQU     <BYTE>
+CHAR8     TEXTEQU     <BYTE>
+BOOLEAN   TEXTEQU     <BYTE>
+POINTER   TEXTEQU     <DWORD>
+
+ ; AGESA Types and Definitions
+
+    AGESA_REVISION              EQU    "Arch2008"
+    AGESA_ID                    EQU    "AGESA"
+
+    LAST_ENTRY                  EQU    0FFFFFFFFh
+    IMAGE_SIGNATURE             EQU    'DMA$'
+    IOCF8                       EQU    0CF8h
+    IOCFC                       EQU    0CFCh
+
+ ; The return status for all AGESA public services.
+
+ ; Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+ ; will have log entries with more detail.
+
+  AGESA_SUCCESS               EQU    0        ; < The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED           EQU    1        ; < The dispatcher or create struct had an unimplemented function requested.
+                                              ; <  Not logged.
+  AGESA_BOUNDS_CHK            EQU    2        ; < A dynamic parameter was out of range and the service was not provided.
+                                              ; < Example, memory address not installed, heap buffer handle not found.
+                                              ; < Not Logged.
+ ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT                 EQU    3        ; < An observed condition, but no loss of function.
+                                              ; <  See log.  Example, HT CRC.
+  AGESA_WARNING               EQU    4        ; < Possible or minor loss of function.  See Log.
+  AGESA_ERROR                 EQU    5        ; < Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL              EQU    6        ; < Continue boot only to notify user.  See Log.
+  AGESA_FATAL                 EQU    7        ; < Halt booting.  See Log.
+  AgesaStatusMax              EQU    8        ; < Not a status, use for limit checking.
+AGESA_STATUS        TEXTEQU    <DWORD>
+
+; For checking whether a status is at or above the mandatory log level.
+AGESA_STATUS_LOG_LEVEL         EQU   AGESA_ALERT
+
+    CALLOUT_ENTRY       TEXTEQU    <POINTER>
+    IMAGE_ENTRY         TEXTEQU    <POINTER>
+    MODULE_ENTRY        TEXTEQU    <POINTER>
+
+; This allocation type is used by the AmdCreateStruct entry point
+  PreMemHeap            EQU    0        ; < Create heap in cache.
+  PostMemDram           EQU    1        ; < Create heap in memory.
+  ByHost                EQU    2        ; < Create heap by Host.
+ALLOCATION_METHOD  TEXTEQU  <DWORD>
+
+ ; These width descriptors are used by the library function, and others, to specify the data size
+  AccessWidth8          EQU    1        ; < Access width is 8 bits.
+  AccessWidth16         EQU    2        ; < Access width is 16 bits.
+  AccessWidth32         EQU    3        ; < Access width is 32 bits.
+  AccessWidth64         EQU    4        ; < Access width is 64 bits.
+
+  AccessS3SaveWidth8    EQU    81h      ; < Save 8 bits data.
+  AccessS3SaveWidth16   EQU    130      ; < Save 16 bits data.
+  AccessS3SaveWidth32   EQU    131      ; < Save 32 bits data.
+  AccessS3SaveWidth64   EQU    132      ; < Save 64 bits data.
+ACCESS_WIDTH  TEXTEQU  <DWORD>
+
+ ; AGESA struct name
+
+   ; AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY     EQU    00020000h
+  AMD_CREATE_STRUCT     EQU    00020001h
+  AMD_INIT_EARLY        EQU    00020002h
+  AMD_INIT_ENV          EQU    00020003h
+  AMD_INIT_LATE         EQU    00020004h
+  AMD_INIT_MID          EQU    00020005h
+  AMD_INIT_POST         EQU    00020006h
+  AMD_INIT_RESET        EQU    00020007h
+  AMD_INIT_RESUME       EQU    00020008h
+  AMD_RELEASE_STRUCT    EQU    00020009h
+  AMD_S3LATE_RESTORE    EQU    0002000Ah
+  AMD_S3_SAVE           EQU    0002000Bh
+  AMD_GET_APIC_ID       EQU    0002000Ch
+  AMD_GET_PCI_ADDRESS   EQU    0002000Dh
+  AMD_IDENTIFY_CORE     EQU    0002000Eh
+  AMD_READ_EVENT_LOG    EQU    0002000Fh
+  AMD_LATE_RUN_AP_TASK  EQU    00020010h
+  AMD_IDENTIFY_DIMMS    EQU    00020011h
+AGESA_STRUCT_NAME  TEXTEQU  <DWORD>
+
+
+  ; ResetType constant values
+    WARM_RESET_WHENEVER         EQU    1
+    COLD_RESET_WHENEVER         EQU    2
+    WARM_RESET_IMMEDIATELY      EQU    3
+    COLD_RESET_IMMEDIATELY      EQU    4
+
+
+ ; AGESA Structures
+
+ ; The standard header for all AGESA services.
+AMD_CONFIG_PARAMS    STRUCT
+  ImageBasePtr                  UINT32 ?        ; < The AGESA Image base address.
+  Func                          UINT32 ?        ; < The service desired, @sa dispatch.h.
+  AltImageBasePtr               UINT32 ?        ; < Alternate Image location
+  CalloutPtr                    CALLOUT_ENTRY ?         ; < For Callout from AGESA
+  HeapStatus                    UINT8 ?         ; < For heap status from boot time slide.
+  HeapBasePtr                   UINT64 ?        ; < Location of the heap
+  Reserved                      UINT8 (7) DUP (?)      ; < This space is reserved for future use.
+AMD_CONFIG_PARAMS    ENDS
+
+
+ ; Create Struct Interface.
+AMD_INTERFACE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}    ; < Config header
+  AgesaFunctionName             AGESA_STRUCT_NAME ?     ; < The service to init, @sa dispatch.h
+  AllocationMethod              ALLOCATION_METHOD ?     ; < How to handle buffer allocation
+  NewStructSize                 UINT32 ?        ; < The size of the allocated data, in for ByHost, else out only.
+  NewStructPtr                  POINTER ?       ; < The struct for the service.
+                                                   ; < The struct to init for ByHost allocation,
+                                                   ; < the initialized struct on return.
+AMD_INTERFACE_PARAMS    ENDS
+
+    FUNC_0                      EQU    0        ; bit-placed for PCI address creation
+    FUNC_1                      EQU    1
+    FUNC_2                      EQU    2
+    FUNC_3                      EQU    3
+    FUNC_4                      EQU    4
+    FUNC_5                      EQU    5
+    FUNC_6                      EQU    6
+    FUNC_7                      EQU    7
+
+ ; AGESA Binary module header structure
+AMD_IMAGE_HEADER    STRUCT
+  Signature                     UINT32 ?        ; < Binary Signature
+  CreatorID                     CHAR8 (8) DUP (?)       ; < 8 characters ID
+  Version                       CHAR8 (12) DUP (?)      ; < 12 characters version
+  ModuleInfoOffset              UINT32 ?        ; < Offset of module
+  EntryPointAddress             UINT32 ?        ; < Entry address
+  ImageBase                     UINT32 ?        ; < Image base
+  RelocTableOffset              UINT32 ?        ; < Relocate Table offset
+  ImageSize                     UINT32 ?        ; < Size
+  Checksum                      UINT16 ?        ; < Checksum
+  ImageType                     UINT8 ?         ; < Type
+  V_Reserved                    UINT8 ?         ; < Reserved
+AMD_IMAGE_HEADER    ENDS
+ ; AGESA Binary module header structure
+AMD_MODULE_HEADER    STRUCT
+  ModuleHeaderSignature         UINT32 ?        ; < Module signature
+  ModuleIdentifier              CHAR8 (8) DUP (?)       ; < 8 characters ID
+  ModuleVersion                 CHAR8 (12) DUP (?)      ; < 12 characters version
+  ModuleDispatcher              POINTER ?       ; < A pointer point to dispatcher
+  NextBlock                     POINTER ?       ; < Next module header link
+AMD_MODULE_HEADER    ENDS
+
+; AMD_CODE_HEADER Signatures.
+AGESA_CODE_SIGNATURE    TEXTEQU  <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
+CIMXNB_CODE_SIGNATURE   TEXTEQU  <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
+CIMXSB_CODE_SIGNATURE   TEXTEQU  <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
+
+; AGESA_CODE_SIGNATURE
+AMD_CODE_HEADER    STRUCT
+  Signature             CHAR8 (8) DUP (?)           ; < code header Signature
+  ComponentName         CHAR8 (8) DUP (?)           ; < 8 character name of the code module
+  Version               CHAR8 (12) DUP (?)          ; < 12 character version string
+  TerminatorNull        CHAR8 ?                     ; < null terminated string
+  VerReserved           CHAR8 (7) DUP (?)           ; < reserved space
+AMD_CODE_HEADER    ENDS
+
+ ; Extended PCI address format
+EXT_PCI_ADDR    STRUCT
+  Register                      UINT32 ?
+;   IN OUT  UINT32      Register:12;                           ; < Register offset
+;   IN OUT  UINT32      Function:3;                     ; < Function number
+;   IN OUT  UINT32      Device:5;                       ; < Device number
+;   IN OUT  UINT32      Bus:8;                          ; < Bus number
+;   IN OUT  UINT32      Segment:4;                      ; < Segment
+EXT_PCI_ADDR    ENDS
+
+ ; Union type for PCI address
+PCI_ADDR    UNION
+  AddressValue                  UINT32 ?        ; < Formal address
+  Address                       EXT_PCI_ADDR {}         ; < Extended address
+PCI_ADDR    ENDS
+
+   ; SBDFO - Segment Bus Device Function Offset
+   ; 31:28   Segment (4-bits)
+   ; 27:20   Bus     (8-bits)
+   ; 19:15   Device  (5-bits)
+   ; 14:12   Function(3-bits)
+   ; 11:00   Offset  (12-bits)
+
+
+
+    ILLEGAL_SBDFO               EQU    0FFFFFFFFh
+
+ ; CPUID data received registers format
+CPUID_DATA    STRUCT
+  EAX_Reg                       UINT32 ?        ; < CPUID instruction result in EAX
+  EBX_Reg                       UINT32 ?        ; < CPUID instruction result in EBX
+  ECX_Reg                       UINT32 ?        ; < CPUID instruction result in ECX
+  EDX_Reg                       UINT32 ?        ; < CPUID instruction result in EDX
+CPUID_DATA    ENDS
+
+ ; HT frequency for external callbacks
+;typedef enum {
+  HT_FREQUENCY_200M     EQU    0        ; < HT speed 200 for external callbacks
+  HT_FREQUENCY_400M     EQU    2        ; < HT speed 400 for external callbacks
+  HT_FREQUENCY_600M     EQU    4        ; < HT speed 600 for external callbacks
+  HT_FREQUENCY_800M     EQU    5        ; < HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M    EQU    6        ; < HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M    EQU    7        ; < HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M    EQU    8        ; < HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M    EQU    9        ; < HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M    EQU    10       ; < HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M    EQU    11       ; < HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M    EQU    12       ; < HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M    EQU    13       ; < HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M    EQU    14       ; < HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M    EQU    17       ; < HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M    EQU    18       ; < HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M    EQU    19       ; < HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX      EQU    20       ; < Limit Check.
+HT_FREQUENCIES  TEXTEQU  <DWORD> ;} HT_FREQUENCIES;
+
+HT3_FREQUENCY_MIN     EQU    HT_FREQUENCY_1200M
+
+IFNDEF   BIT0
+    BIT0                        EQU    0000000000000001h
+ENDIF
+IFNDEF   BIT1
+    BIT1                        EQU    0000000000000002h
+ENDIF
+IFNDEF   BIT2
+    BIT2                        EQU    0000000000000004h
+ENDIF
+IFNDEF   BIT3
+    BIT3                        EQU    0000000000000008h
+ENDIF
+IFNDEF   BIT4
+    BIT4                        EQU    0000000000000010h
+ENDIF
+IFNDEF   BIT5
+    BIT5                        EQU    0000000000000020h
+ENDIF
+IFNDEF   BIT6
+    BIT6                        EQU    0000000000000040h
+ENDIF
+IFNDEF   BIT7
+    BIT7                        EQU    0000000000000080h
+ENDIF
+IFNDEF   BIT8
+    BIT8                        EQU    0000000000000100h
+ENDIF
+IFNDEF   BIT9
+    BIT9                        EQU    0000000000000200h
+ENDIF
+IFNDEF   BIT10
+    BIT10                       EQU    0000000000000400h
+ENDIF
+IFNDEF   BIT11
+    BIT11                       EQU    0000000000000800h
+ENDIF
+IFNDEF   BIT12
+    BIT12                       EQU    0000000000001000h
+ENDIF
+IFNDEF   BIT13
+    BIT13                       EQU    0000000000002000h
+ENDIF
+IFNDEF   BIT14
+    BIT14                       EQU    0000000000004000h
+ENDIF
+IFNDEF   BIT15
+    BIT15                       EQU    0000000000008000h
+ENDIF
+IFNDEF   BIT16
+    BIT16                       EQU    0000000000010000h
+ENDIF
+IFNDEF   BIT17
+    BIT17                       EQU    0000000000020000h
+ENDIF
+IFNDEF   BIT18
+    BIT18                       EQU    0000000000040000h
+ENDIF
+IFNDEF   BIT19
+    BIT19                       EQU    0000000000080000h
+ENDIF
+IFNDEF   BIT20
+    BIT20                       EQU    0000000000100000h
+ENDIF
+IFNDEF   BIT21
+    BIT21                       EQU    0000000000200000h
+ENDIF
+IFNDEF   BIT22
+    BIT22                       EQU    0000000000400000h
+ENDIF
+IFNDEF   BIT23
+    BIT23                       EQU    0000000000800000h
+ENDIF
+IFNDEF   BIT24
+    BIT24                       EQU    0000000001000000h
+ENDIF
+IFNDEF   BIT25
+    BIT25                       EQU    0000000002000000h
+ENDIF
+IFNDEF   BIT26
+    BIT26                       EQU    0000000004000000h
+ENDIF
+IFNDEF   BIT27
+    BIT27                       EQU    0000000008000000h
+ENDIF
+IFNDEF   BIT28
+    BIT28                       EQU    0000000010000000h
+ENDIF
+IFNDEF   BIT29
+    BIT29                       EQU    0000000020000000h
+ENDIF
+IFNDEF   BIT30
+    BIT30                       EQU    0000000040000000h
+ENDIF
+IFNDEF   BIT31
+    BIT31                       EQU    0000000080000000h
+ENDIF
+IFNDEF   BIT32
+    BIT32                       EQU    0000000100000000h
+ENDIF
+IFNDEF   BIT33
+    BIT33                       EQU    0000000200000000h
+ENDIF
+IFNDEF   BIT34
+    BIT34                       EQU    0000000400000000h
+ENDIF
+IFNDEF   BIT35
+    BIT35                       EQU    0000000800000000h
+ENDIF
+IFNDEF   BIT36
+    BIT36                       EQU    0000001000000000h
+ENDIF
+IFNDEF   BIT37
+    BIT37                       EQU    0000002000000000h
+ENDIF
+IFNDEF   BIT38
+    BIT38                       EQU    0000004000000000h
+ENDIF
+IFNDEF   BIT39
+    BIT39                       EQU    0000008000000000h
+ENDIF
+IFNDEF   BIT40
+    BIT40                       EQU    0000010000000000h
+ENDIF
+IFNDEF   BIT41
+    BIT41                       EQU    0000020000000000h
+ENDIF
+IFNDEF   BIT42
+    BIT42                       EQU    0000040000000000h
+ENDIF
+IFNDEF   BIT43
+    BIT43                       EQU    0000080000000000h
+ENDIF
+IFNDEF   BIT44
+    BIT44                       EQU    0000100000000000h
+ENDIF
+IFNDEF   BIT45
+    BIT45                       EQU    0000200000000000h
+ENDIF
+IFNDEF   BIT46
+    BIT46                       EQU    0000400000000000h
+ENDIF
+IFNDEF   BIT47
+    BIT47                       EQU    0000800000000000h
+ENDIF
+IFNDEF   BIT48
+    BIT48                       EQU    0001000000000000h
+ENDIF
+IFNDEF   BIT49
+    BIT49                       EQU    0002000000000000h
+ENDIF
+IFNDEF   BIT50
+    BIT50                       EQU    0004000000000000h
+ENDIF
+IFNDEF   BIT51
+    BIT51                       EQU    0008000000000000h
+ENDIF
+IFNDEF   BIT52
+    BIT52                       EQU    0010000000000000h
+ENDIF
+IFNDEF   BIT53
+    BIT53                       EQU    0020000000000000h
+ENDIF
+IFNDEF   BIT54
+    BIT54                       EQU    0040000000000000h
+ENDIF
+IFNDEF   BIT55
+    BIT55                       EQU    0080000000000000h
+ENDIF
+IFNDEF   BIT56
+    BIT56                       EQU    0100000000000000h
+ENDIF
+IFNDEF   BIT57
+    BIT57                       EQU    0200000000000000h
+ENDIF
+IFNDEF   BIT58
+    BIT58                       EQU    0400000000000000h
+ENDIF
+IFNDEF   BIT59
+    BIT59                       EQU    0800000000000000h
+ENDIF
+IFNDEF   BIT60
+    BIT60                       EQU    1000000000000000h
+ENDIF
+IFNDEF   BIT61
+    BIT61                       EQU    2000000000000000h
+ENDIF
+IFNDEF   BIT62
+    BIT62                       EQU    4000000000000000h
+ENDIF
+IFNDEF   BIT63
+    BIT63                       EQU    8000000000000000h
+ENDIF
+
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
new file mode 100755
index 0000000000..5a26195316
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
@@ -0,0 +1,577 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * Agesa structures and definitions
+; *
+; * Contains AMD AGESA core interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+;
+; ****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+PARAM1          textequ <[bp+8]>
+PARAM2          textequ <[bp+12]>
+PARAM3          textequ <[bp+16]>
+RETAddress      textequ <[bp+4]>
+
+AMD_PRIVATE_PARAMS STRUCT
+    Gate16_CS   DW ?                ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
+    Gate16_SS   DW ?                ; RM stack segment
+    Router_Seg  DW ?                ; Segment of oem router
+    Router_Off  DW ?                ; Offset of oem router
+AMD_PRIVATE_PARAMS ENDS
+
+; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
+IFNDEF  AGESA_SELECTOR_GDT
+        AGESA_SELECTOR_GDT         EQU 00h
+ENDIF
+IFNDEF  AGESA_SELECTOR_CODE16
+        AGESA_SELECTOR_CODE16      EQU 08h
+ENDIF
+IFNDEF  AGESA_SELECTOR_DATA16
+        AGESA_SELECTOR_DATA16      EQU 10h
+ENDIF
+IFNDEF  AGESA_SELECTOR_CODE32
+        AGESA_SELECTOR_CODE32      EQU 18h
+ENDIF
+IFNDEF  AGESA_SELECTOR_DATA32
+        AGESA_SELECTOR_DATA32      EQU 20h
+ENDIF
+
+
+AMD_BRIDGE_32_GDT MACRO  GDT_Name:REQ
+
+        GDT_Name LABEL BYTE
+            DD 000000000h, 000000000h       ; NULL descriptor
+            DD 00000ffffh, 000009b00h       ; 16-bit code, fixed up
+            DD 00000ffffh, 000009300h       ; 16-bit data, fixed up
+            DD 00000ffffh, 000CF9B00h       ; 32-bit protected mode code
+            DD 00000ffffh, 000CF9300h       ; 32-bit protected mode data
+        GDT_Length EQU ($-GDT_Name)
+
+ENDM
+
+;+-------------------------------------------------------------------------
+;
+;       AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
+;
+;   Processing:
+;       The following steps are taken:
+;       1) Enter 32bit Protected Mode (PM32)
+;       2) Run AGESA code
+;       3) Restore Real Mode (RM)
+;
+; Entry:
+;       [big real mode] : ds, es set to base 0 limit 4G segment
+;       EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
+;       ESI - configuration block pointer
+;
+; Exit:
+;       EAX - return value
+;       ESI - configuration block pointer
+;       ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
+;
+; Modified:
+;      None
+;
+
+AMD_BRIDGE_32 MACRO GDT_Name
+
+        local   copyGDT
+        local   flushTo16PM
+        local   agesaReturnAddress
+        local   leave32bitPM
+        local   flush2RM
+
+        push    gs
+        push    fs
+        push    ebx
+        push    ecx
+        push    edi
+        mov     eax, esp
+        push    eax
+        movzx   esp, sp
+;
+; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
+;
+        pushf
+        cli                         ; Disable interrupts during AGESA
+        cld                         ; Need known direction flag during AGESA
+
+;
+; Save the FAR PTR input parameter
+;
+        mov     gs, dx                  ; Offset
+        shr     edx, 16
+        mov     fs, dx                  ; Segment
+;
+; Determine where our binary file is and get entry point
+;
+        mov     edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
+        add     edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
+;
+; Figure out the return address we will use after calling AGESA
+; and store it in ebx until we have our stack set up properly
+;
+        mov     ebx, cs
+        shl     ebx, 4
+        add     ebx, OFFSET agesaReturnAddress
+;
+; Save our current RM stack AND entry EBP
+;
+        push    ebp
+;       push    esp
+        push    ss
+
+;
+; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
+;
+; Copy the GDT onto the stack for modification
+;
+        mov     cx, GDT_Length
+        sub     sp, cx
+        mov     bp, sp
+        lea     di, GDT_Name
+copyGDT:
+        mov     al, cs:[di]
+        mov     [bp], al
+        inc     di
+        inc     bp
+        loop    copyGDT
+;
+; Patch 16-bit code and data descriptors on stack.  We will
+; fix up CS and SS for PM16 during the callout if applicable.
+;
+        mov     bp, sp
+
+        mov     eax, cs
+        shl     eax, 4
+        mov     [bp+AGESA_SELECTOR_CODE16+2], ax
+        shr     eax, 16
+        mov     [bp+AGESA_SELECTOR_CODE16+4], al
+
+        mov     eax, ss
+        shl     eax, 4
+        mov     [bp+AGESA_SELECTOR_DATA16+2], ax
+        shr     eax, 16
+        mov     [bp+AGESA_SELECTOR_DATA16+4], al
+;
+; Need to place Length and Address on GDT
+;
+        mov     eax, ss
+        shl     eax, 4
+        add     eax, esp
+        push    eax
+        push    WORD PTR (GDT_Length-1)
+;
+; Load the GDT
+;
+        mov     bp, sp
+        lgdt    FWORD PTR [bp]
+;
+; TABLE 1
+;
+; Place PRIVATE DATA on stack DIRECTLY following GDT
+; During this routine, stack data is critical.  If
+; order is changed or additional added, bad things
+; will happen!
+;
+; HIGHEST PHYSICAL ADDRESS
+;
+; | ...                  |
+; ------------------------
+; | old RM SP            |
+; | old RM SS            |
+; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
+; | GDT_DATA32           |
+; | ...                  |
+; | GDT_NULL             |
+; | GDT Addr, Length     |
+; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
+; | Priv.Gate16_SS       |
+; | Priv.Gate16_CS       |
+; ------------------------ sp
+; ------ THEN PUSH -------
+; | Return to 16-bit CS  |
+; | Return to 16-bit Off |
+; | ...                  |
+;
+; LOWEST  PHYSICAL ADDRESS
+;
+        mov     edi, esp
+        sub     edi, SIZEOF AMD_PRIVATE_PARAMS
+        mov     ax, cs
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
+        mov     ax, ss
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
+
+        mov     esp, edi
+;
+; Save an address for returning to 16 bit real mode on stack,
+; we'll use it in a far ret after turning off CR0.PE so that
+; we can take our address off and force a far jump.  Be sure
+; no unexpected data is on the stack after this!
+;
+        mov     ax, cs
+        push    cs
+        lea     ax, flush2RM
+        push    ax
+;
+; Convert ss:esp to "flat"
+;
+
+        mov     ax, sp
+        push    ax
+        mov     eax, ss
+        shl     eax, 4
+        add     eax, esp
+        mov     esp, eax                ; Load the zero based ESP
+
+;
+; Set CR0.PE
+;
+        mov     eax, CR0                ; Get CPU control word 0
+        or      al, 01                  ; Enable CPU protected mode
+        mov     CR0, eax                ; Write back to CPU control word 0
+        jmp     flushTo16PM
+
+flushTo16PM:
+;
+; 16-bit protected mode
+;
+        mov     ax, AGESA_SELECTOR_DATA32
+        mov     ds, ax
+        mov     es, ax
+        mov     fs, ax
+        mov     gs, ax
+        mov     ss, ax
+;
+; Push our parameters RIGHT TO LEFT, and then return address
+;
+        push    esi                     ; AGESA configuration block pointer (data)
+        push    ebx                     ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
+        pushd   AGESA_SELECTOR_CODE32   ; AGESA entry selector (32PM flat)
+        push    edx                     ; AGESA entry point (32PM flat)
+
+        DB      066h
+        retf                            ; <><><> Enter AGESA 32-bit code!!! <><><>
+
+agesaReturnAddress:
+;
+; Returns from the Agesa 32-bit code still PM32
+;
+        DB      0EAh
+        DD      OFFSET leave32bitPM
+        DW      AGESA_SELECTOR_CODE16
+
+leave32bitPM:
+;
+; Now in 16-bit PM
+;
+        add     esp, 4                  ; +4 to remove our config block pointer
+;
+; Eax reserve AGESA_STATUS return code, save it
+;
+        mov     ebx, eax
+;
+; Turn off CR0.PE, restore 64K stack limit
+;
+        pop     ax
+        mov     sp, ax
+        mov     ax, AGESA_SELECTOR_DATA16
+        mov     ss, ax
+
+        mov     eax, CR0
+        and     al, NOT 1               ; Disable protected mode
+        mov     CR0, eax                ; Write back CR0.PE
+;
+; Jump far to enter RM, we saved this address on the stack
+; already.  Hopefully stack is balanced through AGESA
+; nor were any params added by pushing them on the stack and
+; not removing them between BEGIN-END comments.
+;
+        retf
+
+flush2RM:
+;
+; Set segments registers for big real mode before returning
+;
+        xor     ax, ax
+        mov     ds, ax
+        mov     es, ax
+        mov     fs, ax
+        mov     gs, ax
+;
+; Discard GDT, +6 for GDT pointer/size, privates
+;
+        add     esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
+;
+; Restore real mode stack and entry EBP
+;
+        pop     cx
+;       mov     esp, [esp]
+        mov     ss, cx
+        pop     ebp
+;
+; Restore AGESA_STATUS return code to eax
+;
+        mov     eax, ebx
+;
+; END --- STACK MUST BE BALANCED TO THIS POINT --- END
+;
+
+        popf
+        pop     ebx
+        mov     esp, ebx
+        pop     edi
+        pop     ecx
+        pop     ebx
+        pop     fs
+        pop     gs
+                            ; EXIT AMD_BRIDGE_32
+ENDM
+;+-------------------------------------------------------------------------
+;
+; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
+;
+;   Processing:
+;       The following steps are taken:
+;       1) Enter PM16
+;       2) Setup stack, get private params
+;       3) Enter RM
+;       4) Get 3 params
+;       5) Call oemCallout OR oem router
+;       6) Enter PM32
+;       7) Return to Agesa PH
+;
+; Entry:
+;       [32-bit protected mode]
+;       [esp+8] Func
+;       [esp+12] Data
+;       [esp+16] Configuration Block
+;       [esp+4] return address to Agesa
+;
+; Exit:
+;       [32-bit protected mode]
+;
+; Modified:
+;     None
+;
+AMD_CALLOUT_16 MACRO  LocalOemCalloutRouter
+;
+; Note that we are still PM32, so MASM may work strangely
+;
+
+        push    bp                     ; Save our original SP to access params
+        mov     bp, sp
+        push    bx
+        push    si
+        push    di
+        push    cx
+        push    dx
+        push    di
+
+        DB      066h, 0EAh
+        DW      OFFSET PM16Entry
+        DW      AGESA_SELECTOR_CODE16
+
+PM16Entry:
+;
+; PM16 CS, but still PM32 SS, as we need to access our private params
+; before we enter RM.
+;
+; Note: we are working below the stack temporarily, and and it will
+; not affect our ability to get entry params
+;
+        xor     ecx, ecx
+        xor     edx, edx
+;
+; SGDT will give us the original location of the GDT on our CAS stack.
+; We need this value because our private parameters are located just
+; below the GDT.
+;
+        mov     edi, esp
+        sub     edi, GDT_Length + 6
+        sgdt    FWORD PTR [edi]        ; [edi] = word size, dword address
+        mov     edi, DWORD PTR [edi+2]  ; Get the PM32 address only
+        sub     edi, SIZEOF AMD_PRIVATE_PARAMS + 6
+;
+; cx = code segment of this code in RM
+; dx = stack segment of CAS in RM
+; fs = code segment of oem router (save for later)
+; gs = offset of oem router (save for later)
+; fs and gs are loaded after switch to real mode because we can't
+; use them as scratch pad registers in protected mode
+;
+        mov     cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
+        mov     dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
+
+        mov     eax, edi             ; Save edi in eax for after RM switch
+        mov     edi, esp             ; Save our current ESP for RM
+
+        movzx   ebx, dx
+        shl     ebx, 4
+        sub     esp, ebx
+
+;
+; We had been accessing the stack in PM32, we will now change to PM16 so we
+; will make the stack segment 64KB limit so SP needs to be fixed made PM16
+; compatible.
+;
+        mov     bx, AGESA_SELECTOR_DATA16
+        mov     ss, bx
+
+;
+; Save the RM segment and RM offset of the jump we will need to make in
+; order to enter RM so that code in this segment is relocatable.
+;
+; BEGIN --- Don't unbalance the stack --- BEGIN
+;
+        push    cx
+        pushw   OFFSET RMEntry
+
+        mov     ebx, CR0
+        and     bl, NOT 1
+        mov     CR0, ebx                ; CR0.PE cleared
+;
+; Far jump to clear segment descriptor cache and enter RM
+;
+        retf
+
+RMEntry:
+;
+; We are in RM, setup RM stack
+;
+        movzx   ebx, dx               ; Get RM SS in ebx
+        shl     ebx, 4                  ; Get our stack top on entry in EBP to
+        sub     ebp, ebx                ; access our entry parameters
+        sub     eax, ebx                ; save copy of parameters address
+        mov     ss, dx                  ; Set stack segment
+;
+; We are going to figure out the address to use when we return
+; and have to go back into PM32 while we have access to it
+;
+        movzx   ebx, cx               ; Get original CS in ebx
+        shl     ebx, 4
+        add     ebx, OFFSET PM32Entry
+;
+; Now we put our data, func, block params into calling convention
+; for our hook
+;
+; ECX = Func
+; EDX = Data
+; ESI = config pointer
+;
+        mov     ecx, PARAM1             ; Func
+        mov     edx, PARAM2             ; Data
+        mov     esi, PARAM3             ; pointer
+
+        push    ebx                    ; Save PM32 mode switch address
+        push    edi                    ; Save PM32 stack pointer
+        pushf
+;
+; Get Router Function Address
+;
+        mov     edi, eax
+        mov     ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
+        mov     fs, ax
+        mov     ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
+        mov     gs, ax
+
+        mov     eax, AGESA_UNSUPPORTED  ; Default return value
+;
+; If AMD_BRIDGE_32 EDX == 0 call oemCallout
+; otherwise call FAR PTR EDX
+;
+; Critical:
+;   sp+2 - EDI aka PM32 stack address
+;   sp+4 - address of PM32Entry in PM32
+;
+        mov     bx, fs
+        shl     ebx, 16
+        mov     bx, gs
+
+        .if (ebx == 0)
+            call        LocalOemCalloutRouter
+        .else
+;
+; Make far call to Router function
+;
+        push    cs
+        push    offset CalloutReturn
+        push    ebx
+        retf
+CalloutReturn:
+    .endif
+;
+; Restore PM32 esp from RM stack
+;
+        popf
+        pop     edi                     ; Our PM32 stack pointer
+        pop     edx                     ; Our PM32 mode switch address
+
+        mov     ebx, CR0
+        or      bl, 1                   ; CR0.PE set
+        mov     CR0, ebx
+
+        mov     ebx, AGESA_SELECTOR_DATA32
+        pushd   AGESA_SELECTOR_CODE32 ; PM32 selector
+        push    edx                    ; PM32 entry point
+
+        DB      066h
+        retf                        ; Far jump to enter PM32
+
+PM32Entry:
+;
+; END --- Don't unbalance the stack --- END
+; We are now PM32, so remember MASM is assembling in 16-bit again
+;
+        mov     ss, bx
+        mov     ds, bx
+        mov     es, bx
+        mov     fs, bx
+        mov     gs, bx
+
+        mov     sp, di
+        pop     di
+        pop     dx
+        pop     cx
+        pop     di
+        pop     si
+        pop     bx
+        pop     bp
+                            ; EXIT AMD_CALLOUT_16
+ENDM
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
new file mode 100755
index 0000000000..a35ecdf0af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
@@ -0,0 +1,624 @@
+;/**
+; * @file
+; *
+; * Agesa library 32bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 17071 $   @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO byte
+; *
+; *  @param[in]   Address IO port address
+; *  @param[in]   Data    IO port Value
+; */
+
+public  WriteIo8
+WriteIo8        PROC NEAR C USES DX AX Address:WORD, Data:Byte
+        mov     dx, Address
+        mov     al, Data
+        out     dx, al
+        ret
+WriteIo8        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO word
+; *
+; *  @param[in]   Address IO port address
+; *  @param[in]   Data    IO port Value
+; */
+public WriteIo16
+WriteIo16       PROC NEAR C USES DX AX Address:WORD, Data:WORD
+        mov     dx, Address
+        mov     ax, Data
+        out     dx, ax
+        ret
+WriteIo16       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO dword
+; *
+; *  @param[in]   Address IO port address
+; *  @param[in]   Data    IO port Value
+; */
+
+public WriteIo32
+WriteIo32       PROC NEAR C USES DX EAX Address:WORD, Data:DWORD
+        mov     dx, Address
+        mov     eax, Data
+        out     dx, eax
+        ret
+WriteIo32       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO byte
+; *
+; *  @param[in] - IO port address
+; *  @retval      IO port Value
+; */
+public ReadIo8
+ReadIo8 PROC NEAR C USES DX Address:WORD
+        mov     dx, Address
+        in      al, dx
+        ret
+ReadIo8 ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO word
+; *
+; *  @param[in]   Address IO port address
+; *  @retval      IO port Value
+; */
+public ReadIo16
+ReadIo16        PROC NEAR C USES DX Address:WORD
+        mov     dx, Address
+        in      ax, dx
+        ret
+ReadIo16        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO dword
+; *
+; *  @param[in]   Address  IO port address
+; *  @retval      IO port Value
+; */
+public ReadIo32
+ReadIo32        PROC NEAR C USES DX Address:WORD
+        mov     dx, Address
+        in      eax, dx
+        ret
+ReadIo32        ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read MSR
+; *
+; *  @param[in]  Address  MSR Address
+; *  @param[in]  Data     Pointer to data
+; *  @param[in]  ConfigPtr (Optional)
+; */
+public LibAmdMsrRead
+LibAmdMsrRead  PROC NEAR C USES ECX ESI EDX Address:DWORD, Value:PTR, ConfigPtr:PTR
+        mov     esi, ConfigPtr        ;Dummy read to avoid compilation warning
+        mov     ecx, Address
+        rdmsr
+        mov     esi, Value
+        mov     [esi],   eax
+        mov     [esi+4], edx
+        ret
+LibAmdMsrRead  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write MSR
+; *
+; *  @param[in]  Address    MSR Address
+; *  @param[in]  Data       Pointer to data
+; *  @param[in]  ConfigPtr  (Optional)
+; */
+public LibAmdMsrWrite
+LibAmdMsrWrite                PROC NEAR C USES ECX ESI EDX Address:DWORD, Data:PTR, ConfigPtr:PTR
+        mov     esi, ConfigPtr         ;Dummy read to avoid compilation warning
+        mov     ecx, Address
+        mov     esi, Data
+        mov     eax, [esi]
+        mov     edx, [esi+4]
+        wrmsr
+        ret
+LibAmdMsrWrite                ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read CPUID
+; *
+; *  @param[in]  Func   CPUID function
+; *  @param[in]  DATA   Pointer to CPUID_DATA to save cpuid data
+; *  @param[in]  ConfigPtr (Optional)
+; */
+public LibAmdCpuidRead
+LibAmdCpuidRead       PROC NEAR C  Func:DWORD, DATA:PTR, ConfigPtr:PTR
+        pushad
+        mov     esi, ConfigPtr           ;Dummy read to avoid compilation warning
+        mov     eax, Func
+        cpuid
+        mov     esi, DATA
+        mov     [esi],   eax
+        mov     [esi+4], ebx
+        mov     [esi+8], ecx
+        mov     [esi+12],edx
+        popad
+        ret
+LibAmdCpuidRead              ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read TSC
+; *
+; *
+; *
+; */
+
+public ReadTSC
+ReadTSC  PROC    NEAR C
+        rdtsc
+        ret
+ReadTSC  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Set FS_BASE
+; *
+; *
+; *
+; * @param[in]  esi - Low Dword of physical address
+; * @param[in]  edi - High Dword of physical address
+; */
+SetFsBase  PROC NEAR PUBLIC USES EAX EBX ECX EDX EDI
+
+        mov     eax, ecx
+        mov     ecx, 0C0010015h ; HWCR
+        rdmsr
+        mov     ebx, eax
+        bts     eax, 17         ; HWCR.Wrap32Dis
+        wrmsr
+        xchg    edx, edi
+        mov     eax, esi
+        mov     esi, ebx
+
+        mov     ecx, 0C0000100h ; FS_BASE
+        wrmsr
+        ret
+
+SetFsBase  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Restore MSR0C001_0015
+; *
+; * @param[in]  esi - Low Dword
+; * @param[in]  edi - High Dword
+; */
+RestoreHwcr PROC NEAR PUBLIC USES EAX ECX EDX
+
+        mov     ecx, 0C0010015h
+        mov     eax, esi
+        mov     edx, edi
+        wrmsr
+        ret
+
+RestoreHwcr ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO byte
+; *
+; * @param[in]  Address - Memory Address
+; * @retval     Memory byte at given address
+; */
+Read64Mem8  PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     al, fs:[ebx]
+        call    RestoreHwcr
+        jmp     Done
+AccesBelow4G:
+        mov     al, ds:[esi]
+Done:
+        ret
+
+Read64Mem8  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO word
+; *
+; * @param[in]  Address - Memory Address
+; * @retval     Memory word at given address
+; */
+Read64Mem16  PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     ax, fs:[ebx]
+        call    RestoreHwcr
+        jmp     Done
+AccesBelow4G:
+        mov     ax, ds:[esi]
+Done:
+
+        ret
+
+Read64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO dword
+; *
+; * @param[in]  Address - Memory Address
+; * @retval     Memory dword at given address
+; */
+Read64Mem32  PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     eax, fs:[ebx]
+        call    RestoreHwcr
+        jmp     Done
+AccesBelow4G:
+        mov     eax, ds:[esi]
+Done:
+        ret
+
+Read64Mem32  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO byte
+; *
+; * @param[in]  Address - Memory Address
+; * @param[in]  Value   - Value to write
+; */
+
+Write64Mem8  PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:BYTE
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     al, Data
+        mov     fs:[ebx], al
+        call    RestoreHwcr
+        jmp     Done
+AccesBelow4G:
+        mov     al, Data
+        mov     ds:[esi], al
+Done:
+
+        ret
+
+Write64Mem8  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO word
+; *
+; * @param[in]  Address - Memory Address
+; * @param[in]  Value   - Value to write
+; */
+Write64Mem16  PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:WORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     ax, Data
+        mov     fs:[ebx], ax
+        call    RestoreHwcr
+        jmp     Done
+AccesBelow4G:
+        mov     ax, Data
+        mov     ds:[esi], ax
+Done:
+        ret
+
+Write64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO dword
+; *
+; * @param[in]  Address - Memory Address
+; * @param[in]  Value   - Value to write
+; */
+Write64Mem32  PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:DWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     eax, Data
+        mov     fs:[ebx], eax
+        call    RestoreHwcr
+        jmp     Done
+AccesBelow4G:
+        mov     eax, Data
+        mov     ds:[esi], eax
+
+Done:
+
+        ret
+
+Write64Mem32  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read various CPU registers
+; *
+; * @param[in]  Reg     Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  Value   Value to write
+; */
+
+LibAmdReadCpuReg PROC NEAR C Reg:BYTE, Value:NEAR PTR DWORD
+    pushad
+    push ds
+
+    .if(Reg == 00h)
+        mov eax, cr0
+    .elseif(Reg == 04h)
+        mov eax, cr4
+    .elseif(Reg == 10h)
+        mov eax, dr0
+    .elseif(Reg == 11h)
+        mov eax, dr1
+    .elseif(Reg == 12h)
+        mov eax, dr2
+    .elseif(Reg == 13h)
+        mov eax, dr3
+    .elseif(Reg == 17h)
+        mov eax, dr7
+    .else
+        xor eax,eax
+    .endif
+
+    mov edi, Value
+    mov [edi], eax
+
+    pop ds
+    popad
+    ret
+LibAmdReadCpuReg ENDP
+
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write various CPU registers
+; *
+; * @param[in]  Reg     Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  Value   Value to write
+; */
+
+LibAmdWriteCpuReg PROC NEAR C Reg:BYTE, Value:DWORD
+    mov eax, Value
+
+    .if(Reg == 00h)
+        mov cr0, eax
+    .elseif(Reg == 4)
+        mov cr4, eax
+    .elseif(Reg == 10h)
+        mov dr0, eax
+    .elseif(Reg == 11h)
+        mov dr1, eax
+    .elseif(Reg == 12h)
+        mov dr2, eax
+    .elseif(Reg == 13h)
+        mov dr3, eax
+    .elseif(Reg == 17h)
+        mov dr7, eax
+    .endif
+    ret
+LibAmdWriteCpuReg ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write back invalidate caches using wbinvd.
+; *
+; *
+; *
+; */
+
+PUBLIC LibAmdWriteBackInvalidateCache
+LibAmdWriteBackInvalidateCache PROC NEAR C
+    wbinvd
+    ret
+LibAmdWriteBackInvalidateCache ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Stop CPU
+; *
+; *
+; *
+; */
+
+PUBLIC StopHere
+StopHere PROC NEAR C
+@@:
+    jmp short @b
+StopHere ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Enter debugger on SimNow
+; *
+; *
+; *
+; */
+PUBLIC LibAmdSimNowEnterDebugger
+LibAmdSimNowEnterDebugger PROC NEAR C
+    pushad
+    mov     eax, 0BACCD00Bh         ; Backdoor in SimNow
+    mov     ebx, 2                  ; Select breakpoint feature
+    cpuid
+@@:
+    jmp short @b
+    popad
+    ret
+LibAmdSimNowEnterDebugger ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  IDS IO port write
+; *
+; * @param[in]  Address     IO Port Address
+; * @param[in]  Value       Value to write
+; * @param[in]  Flag        IDS flags
+; *
+; */
+
+PUBLIC IdsOutPort
+IdsOutPort PROC NEAR C Address:DWORD, Value:DWORD ,Flag:DWORD
+    push edx
+    push eax
+    push ebx
+    mov edx, Address
+    mov eax, Value
+    mov ebx, Flag
+    out dx, eax
+    pop ebx
+    pop eax
+    pop edx
+    ret
+IdsOutPort  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Force breakpoint on HDT
+; *
+; *
+; */
+PUBLIC LibAmdHDTBreakPoint
+LibAmdHDTBreakPoint PROC NEAR C
+
+    pushad
+
+    mov ecx, 0C001100Ah             ;bit 0 = HDT redirect
+    mov edi, 09C5A203Ah             ;Password
+    RDMSR                           ;
+    or al, 1                        ;
+    WRMSR                           ;
+    mov al, 0B2h                    ;Marker = B2
+    db 0F1h                         ;ICEBP
+
+    popad
+    ret
+
+LibAmdHDTBreakPoint ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most right hand side non-zero bit with .
+; *
+; * @param[in]  Value       Value
+; */
+PUBLIC LibAmdBitScanForward
+LibAmdBitScanForward PROC NEAR C Value:DWORD
+    mov eax, Value
+    bsf eax, Value
+    .if (Zero?)
+      mov al,32
+    .endif
+    ret
+LibAmdBitScanForward  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most left hand side non-zero bit.
+; *
+; * @param[in]  Value       Value
+; */
+PUBLIC LibAmdBitScanReverse
+LibAmdBitScanReverse PROC NEAR C Value:DWORD
+    mov eax, Value
+    bsr eax, Value
+    .if (Zero?)
+      mov al,0FFh
+    .endif
+    ret
+LibAmdBitScanReverse  ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
new file mode 100755
index 0000000000..7fe47c0382
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
@@ -0,0 +1,110 @@
+;/**
+; * @file
+; *
+; * Agesa library 32bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 9201 $   @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+;/*++
+;
+;Routine Description:
+;
+;  Shifts a UINT64 to the right.
+;
+;Arguments:
+;
+;  EDX:EAX - UINT64 value to be shifted
+;  CL -      Shift count
+;
+;Returns:
+;
+;  EDX:EAX - shifted value
+;
+;--*/
+_aullshr  PROC NEAR C PUBLIC
+        .if (cl < 64)
+            .if (cl >= 32)
+                sub    cl, 32
+                mov    eax, edx
+                xor    edx, edx
+            .endif
+            shrd   eax, edx, cl
+            shr    edx, cl
+        .else
+            xor    eax, eax
+            xor    edx, edx
+        .endif
+        ret
+_aullshr ENDP
+
+;/*++
+;
+;Routine Description:
+;
+;  Shifts a UINT64 to the left.
+;
+;Arguments:
+;
+;  EDX:EAX - UINT64 value to be shifted
+;  CL -      Shift count
+;
+;Returns:
+;
+;  EDX:EAX - shifted value
+;
+;--*/
+_allshl  PROC NEAR C PUBLIC USES CX
+        .if (cl < 64)
+            .if (cl >= 32)
+                sub    cl, 32
+                mov    edx, eax
+                xor    eax, eax
+            .endif
+            shld   edx, eax, cl
+            shl    eax, cl
+        .else
+            xor    eax, eax
+            xor    edx, edx
+        .endif
+        ret
+_allshl ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
new file mode 100755
index 0000000000..bd8bc61100
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
@@ -0,0 +1,84 @@
+;/**
+; * @file
+; *
+; * Agesa library 32bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 9201 $   @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+; void *memcpy( void *dest, void *src, size_t count );
+;
+; Copy count bytes from src to dest, returning dest.
+; ("c" is not legal as an assembly parameter name, replaced with value.)
+; Assume ES is set appropriately, 32 bit flat.
+;
+public memcpy
+memcpy  PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
+        pushf
+        cld     ; We will increment through *dest
+        mov     edi, dest
+        mov     esi, src
+        mov     ecx, count
+        rep movsb
+        mov eax, dest
+        popf
+        ret
+memcpy ENDP
+
+; void *memset( void *dest, int c, size_t count );
+;
+; At dest, set count bytes to byte value, returning dest.
+; ("c" is not legal as an assembly parameter name, replaced with value.)
+; Assume ES is set appropriately, 32 bit flat.
+;
+public memset
+memset  PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
+        pushf
+        cld     ; We will increment through *dest
+        mov     edi, dest
+        mov     eax, value
+        mov     ecx, count
+        rep stosb
+        mov     eax, edi
+        popf
+        ret
+memset ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Lib/amdlib.c b/src/vendorcode/amd/agesa/f10/Lib/amdlib.c
new file mode 100755
index 0000000000..d88eee7a8e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Lib/amdlib.c
@@ -0,0 +1,1336 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Library
+ *
+ * Contains interface to the AMD AGESA library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Lib
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "amdlib.h"
+#include "Filecode.h"
+#define FILECODE LIB_AMDLIB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+BOOLEAN
+STATIC
+GetPciMmioAddress (
+     OUT   UINT64            *MmioAddress,
+     OUT   UINT32            *MmioSize,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+LibAmdGetDataFromPtr (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       VOID         *Data,
+  IN       VOID         *DataMask,
+     OUT   UINT32       *TemData,
+     OUT   UINT32       *TempDataMask
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8
+ReadIo8 (
+  IN       UINT16 Address
+  )
+{
+  return __inbyte (Address);
+}
+UINT16
+ReadIo16 (
+  IN       UINT16 Address
+  )
+{
+  return __inword (Address);
+}
+UINT32
+ReadIo32 (
+  IN       UINT16 Address
+  )
+{
+  return __indword (Address);
+}
+VOID
+WriteIo8 (
+  IN       UINT16 Address,
+  IN       UINT8 Data
+  )
+{
+  __outbyte (Address, Data);
+}
+VOID
+WriteIo16 (
+  IN       UINT16 Address,
+  IN       UINT16 Data
+  )
+{
+  __outword (Address, Data);
+}
+VOID
+WriteIo32 (
+  IN       UINT16 Address,
+  IN       UINT32 Data
+  )
+{
+   __outdword (Address, Data);
+}
+STATIC
+UINT64 SetFsBase (
+  UINT64 address
+  )
+{
+  UINT64 hwcr;
+  hwcr = __readmsr (0xC0010015);
+  __writemsr (0xC0010015, hwcr | 1 << 17);
+  __writemsr (0xC0000100, address);
+  return hwcr;
+}
+STATIC
+VOID
+RestoreHwcr (
+  UINT64
+  value
+  )
+{
+  __writemsr (0xC0010015, value);
+}
+UINT8
+Read64Mem8 (
+  IN       UINT64 Address
+  )
+{
+  UINT8 dataRead;
+  UINT64 hwcrSave;
+  if ((Address >> 32) == 0) {
+    return *(volatile UINT8 *) (UINTN) Address;
+  }
+  hwcrSave = SetFsBase (Address);
+  dataRead = __readfsbyte (0);
+  RestoreHwcr (hwcrSave);
+  return dataRead;
+}
+UINT16
+Read64Mem16 (
+  IN       UINT64 Address
+  )
+{
+  UINT16 dataRead;
+  UINT64 hwcrSave;
+  if ((Address >> 32) == 0) {
+    return *(volatile UINT16 *) (UINTN) Address;
+  }
+  hwcrSave = SetFsBase (Address);
+  dataRead = __readfsword (0);
+  RestoreHwcr (hwcrSave);
+  return dataRead;
+}
+UINT32
+Read64Mem32 (
+  IN       UINT64 Address
+  )
+{
+  UINT32 dataRead;
+  UINT64 hwcrSave;
+  if ((Address >> 32) == 0) {
+    return *(volatile UINT32 *) (UINTN) Address;
+  }
+  hwcrSave = SetFsBase (Address);
+  dataRead = __readfsdword (0);
+  RestoreHwcr (hwcrSave);
+  return dataRead;
+  }
+VOID
+Write64Mem8 (
+  IN       UINT64 Address,
+  IN       UINT8 Data
+  )
+{
+  if ((Address >> 32) == 0){
+    *(volatile UINT8 *) (UINTN) Address = Data;
+  }
+  else {
+    UINT64 hwcrSave;
+    hwcrSave = SetFsBase (Address);
+    __writefsbyte (0, Data);
+    RestoreHwcr (hwcrSave);
+  }
+}
+VOID
+Write64Mem16 (
+  IN       UINT64 Address,
+  IN       UINT16 Data
+  )
+{
+ if ((Address >> 32) == 0){
+   *(volatile UINT16 *) (UINTN) Address = Data;
+ }
+ else {
+   UINT64 hwcrSave;
+   hwcrSave = SetFsBase (Address);
+   __writefsword (0, Data);
+   RestoreHwcr (hwcrSave);
+ }
+}
+VOID
+Write64Mem32 (
+  IN       UINT64 Address,
+  IN       UINT32 Data
+  )
+{
+  if ((Address >> 32) == 0){
+    *(volatile UINT32 *) (UINTN) Address = Data;
+  }
+  else {
+    UINT64 hwcrSave;
+    hwcrSave = SetFsBase (Address);
+    __writefsdword (0, Data);
+    RestoreHwcr (hwcrSave);
+  }
+}
+VOID
+LibAmdReadCpuReg (
+  IN       UINT8 RegNum,
+     OUT   UINT32 *Value
+  )
+{
+    *Value = 0;
+    switch (RegNum){
+    case CR4_REG:
+      *Value = __readcr4 ();
+      break;
+    case DR0_REG:
+      *Value = __readdr (0);
+      break;
+    case DR1_REG:
+      *Value = __readdr (1);
+      break;
+    case DR2_REG:
+      *Value = __readdr (2);
+      break;
+    case DR3_REG:
+      *Value = __readdr (3);
+      break;
+    case DR7_REG:
+      *Value = __readdr (7);
+      break;
+    default:
+      *Value = -1;
+  }
+}
+VOID
+LibAmdWriteCpuReg (
+  IN       UINT8 RegNum,
+  IN       UINT32 Value
+  )
+{
+   switch (RegNum){
+    case CR4_REG:
+      __writecr4 (Value);
+      break;
+    case DR0_REG:
+      __writedr (0, Value);
+      break;
+    case DR1_REG:
+      __writedr (1, Value);
+      break;
+    case DR2_REG:
+      __writedr (2, Value);
+      break;
+    case DR3_REG:
+      __writedr (3, Value);
+      break;
+    case DR7_REG:
+      __writedr (7, Value);
+      break;
+    default:
+      ;
+  }
+}
+VOID
+LibAmdWriteBackInvalidateCache (
+  IN       VOID
+  )
+{
+  __wbinvd ();
+}
+VOID
+LibAmdHDTBreakPoint (
+  VOID
+  )
+{
+  __writemsr (0xC001100A, __readmsr (0xC001100A) | 1);
+  __debugbreak (); // do you really need icebp? If so, go back to asm code
+}
+UINT8
+LibAmdBitScanForward (
+  IN       UINT32 value
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < 32; Index++){
+    if (value & (1 << Index)) break;
+  }
+  return (UINT8) Index;
+}
+UINT8
+LibAmdBitScanReverse (
+  IN       UINT32 value
+)
+{
+  UINTN Index;
+  for (Index = 31; Index >= 0; Index--){
+      if (value & (1 << Index)) break;
+  }
+  return (UINT8) Index;
+}
+VOID
+LibAmdMsrRead (
+  IN       UINT32 MsrAddress,
+     OUT   UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *ConfigPtr
+  )
+{
+  *Value = __readmsr (MsrAddress);
+}
+VOID
+LibAmdMsrWrite (
+  IN       UINT32 MsrAddress,
+  IN       UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *ConfigPtr
+  )
+{
+  __writemsr (MsrAddress, *Value);
+}
+void LibAmdCpuidRead (
+  IN       UINT32 CpuidFcnAddress,
+     OUT   CPUID_DATA* Value,
+  IN OUT   AMD_CONFIG_PARAMS *ConfigPtr
+  )
+{
+  __cpuid ((int *)Value, CpuidFcnAddress);
+}
+UINT64
+ReadTSC (
+  VOID
+  )
+{
+  return __rdtsc ();
+}
+VOID
+LibAmdSimNowEnterDebugger (
+  VOID
+  )
+{
+  STATIC CONST UINT8 opcode [] = {0x60,                             // pushad
+                                   0xBB, 0x02, 0x00, 0x00, 0x00,     // mov ebx, 2
+                                   0xB8, 0x0B, 0xD0, 0xCC, 0xBA,     // mov eax, 0xBACCD00B
+                                   0x0F, 0xA2,                       // cpuid
+                                   0x61,                             // popad
+                                   0xC3                              // ret
+                                 };
+  ((VOID (*)(VOID)) (size_t) opcode) (); // call the function
+}
+
+#ifdef __SSE3__
+VOID F10RevDProbeFilterCritical (
+  IN       PCI_ADDR PciAddress,
+  IN       UINT32   PciRegister
+  )
+{
+  UINT64 msrsave;
+  msrsave = __readmsr (0xC001001F);
+  __writemsr (0xC001001F, msrsave | 1ULL << 46);  // EnableCf8ExtCfg
+  _mm_mfence ();
+  __outdword (0xCF8, PciAddress.AddressValue);
+  _mm_mfence ();
+  __outdword (0xCFC, PciRegister | 2);
+  _mm_mfence ();
+  __writemsr (0xC001001F, msrsave);
+}
+
+VOID
+LibAmdCLFlush (
+  IN       UINT64 Address,
+  IN       UINT8  Count
+  )
+{
+  UINT64 hwcrSave;
+  UINT8  *address32;
+  UINTN  Index;
+  address32 = 0;
+  hwcrSave = SetFsBase (Address);
+  for (Index = 0; Index < Count; Index++){
+    _mm_mfence ();
+    _mm_clflush_fs (&address32 [Index * 64]);
+  }
+  RestoreHwcr (hwcrSave);
+}
+#endif //__SSE3__
+
+VOID
+IdsOutPort (
+  IN       UINT32 Addr,
+  IN       UINT32 Value,
+  IN       UINT32 Flag
+  )
+{
+  __outdword ((UINT16) Addr, Value);
+}
+VOID
+StopHere (
+  VOID
+  )
+{
+  VOLATILE UINTN x = 1;
+  while (x);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read IO port
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO port address
+ * @param[in] Value         Pointer to save data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    *(UINT8 *) Value = ReadIo8 (IoAddress);
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    *(UINT16 *) Value = ReadIo16 (IoAddress);
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    *(UINT32 *) Value = ReadIo32 (IoAddress);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write IO port
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO port address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    WriteIo8 (IoAddress, *(UINT8 *) Value);
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    WriteIo16 (IoAddress, *(UINT16 *) Value);
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    WriteIo32 (IoAddress, *(UINT32 *) Value);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * IO read modify write
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO address
+ * @param[in] Data          OR data
+ * @param[in] DataMask      Mask to be used before data write back to register.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData = 0;
+  UINT32  TempMask = 0;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
+  Value = (Value & (~TempMask)) | TempData;
+  LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Poll IO register
+ *
+ *  Poll register until (RegisterValue & DataMask) ==  Data
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO address
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      And mask
+ * @param[in] Delay         Poll for time in 100ns (not supported)
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData = 0;
+  UINT32  TempMask = 0;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  do {
+    LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
+  } while (TempData != (Value & TempMask));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read memory/MMIO
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    *(UINT8 *) Value = Read64Mem8 (MemAddress);
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    *(UINT16 *) Value = Read64Mem16 (MemAddress);
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    *(UINT32 *) Value = Read64Mem32 (MemAddress);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write memory/MMIO
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    Write64Mem8 (MemAddress, *((UINT8 *) Value));
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    Write64Mem16 (MemAddress, *((UINT16 *) Value));
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    Write64Mem32 (MemAddress, *((UINT32 *) Value));
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Memory/MMIO read modify write
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Data          OR data
+ * @param[in] DataMask      Mask to be used before data write back to register.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData = 0;
+  UINT32  TempMask = 0;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
+  Value = (Value & (~TempMask)) | TempData;
+  LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Poll Mmio
+ *
+ *  Poll register until (RegisterValue & DataMask) ==  Data
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      AND mask
+ * @param[in] Delay         Poll for time in 100ns (not supported)
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData = 0;
+  UINT32  TempMask = 0;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  do {
+    LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
+  } while (TempData != (Value & TempMask));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read PCI config space
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 LegacyPciAccess;
+  UINT32 MMIOSize;
+  UINT64 RMWrite;
+  UINT64 RMWritePrevious;
+  UINT64 MMIOAddress;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
+  if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) {
+    // We need to convert our "portable" PCI address into a "real" PCI access
+    LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
+    if (PciAddress.Address.Register <= 0xFF) {
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+    } else {
+      LibAmdMsrRead  (NB_CFG, &RMWritePrevious, StdHeader);
+      RMWrite = RMWritePrevious | 0x0000400000000000ull;
+      LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+      LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
+    }
+  } else {
+    // Setup the MMIO address
+    ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
+    MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
+    LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write PCI config space
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 LegacyPciAccess;
+  UINT32 MMIOSize;
+  UINT64 RMWrite;
+  UINT64 RMWritePrevious;
+  UINT64 MMIOAddress;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
+  if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) {
+    // We need to convert our "portable" PCI address into a "real" PCI access
+    LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
+    if (PciAddress.Address.Register <= 0xFF) {
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+    } else {
+      LibAmdMsrRead  (NB_CFG, &RMWritePrevious, StdHeader);
+      RMWrite = RMWritePrevious | 0x0000400000000000ull;
+      LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+      LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
+    }
+  } else {
+    // Setup the MMIO address
+    ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
+    MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
+    LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * PCI read modify write
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Data          OR Data
+ * @param[in] DataMask      Mask to be used before data write back to register.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData = 0;
+  UINT32  TempMask = 0;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
+  Value = (Value & (~TempMask)) | TempData;
+  LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Poll PCI config space register
+ *
+ *  Poll register until (RegisterValue & DataMask) ==  Data
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      AND mask
+ * @param[in] Delay         Poll for time in 100ns (not supported)
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData = 0;
+  UINT32  TempMask = 0;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  do {
+    LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
+  } while (TempData != (Value & TempMask));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get MMIO base address for PCI accesses
+ *
+ * @param[out] MmioAddress   PCI MMIO base address
+ * @param[out] MmioSize      Size of region in bytes
+ * @param[in]  StdHeader     Standard configuration header
+ *
+ * @retval    TRUE          MmioAddress/MmioSize are valid
+ */
+BOOLEAN
+STATIC
+GetPciMmioAddress (
+     OUT   UINT64            *MmioAddress,
+     OUT   UINT32            *MmioSize,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN MmioIsEnabled;
+  UINT32  EncodedSize;
+  UINT64  MsrReg;
+
+  ASSERT (StdHeader != NULL);
+
+  MmioIsEnabled = FALSE;
+  LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
+  if ((MsrReg & BIT0) != 0) {
+    *MmioAddress = MsrReg & 0xFFFFFFFFFFF00000ull;
+    EncodedSize = (UINT32) ((MsrReg & 0x3C) >> 2);
+    *MmioSize = ((1 << EncodedSize) * 0x100000);
+    MmioIsEnabled = TRUE;
+  }
+  return MmioIsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read field of PCI config register.
+ *
+ *
+ *
+ * @param[in]   Address       Pci address  (register must be DWORD aligned)
+ * @param[in]   Highbit       High bit position of the field in DWORD
+ * @param[in]   Lowbit        Low bit position of the field in DWORD
+ * @param[out]  Value         Pointer to data
+ * @param[in]   StdHeader     Standard configuration header
+ */
+VOID
+LibAmdPciReadBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+     OUT   UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0);
+
+  LibAmdPciRead (AccessWidth32, Address, Value, StdHeader);
+  *Value >>= Lowbit;  // Shift
+
+  // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
+
+  if ((Highbit - Lowbit) != 31) {
+    *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write field of PCI config register.
+ *
+ *
+ *
+ * @param[in]   Address       Pci address  (register must be DWORD aligned)
+ * @param[in]   Highbit       High bit position of the field in DWORD
+ * @param[in]   Lowbit        Low bit position of the field in DWORD
+ * @param[in]   Value         Pointer to data
+ * @param[in]   StdHeader     Standard configuration header
+ */
+VOID
+LibAmdPciWriteBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Temp;
+  UINT32 Mask;
+
+  ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0);
+
+  // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+
+  if ((Highbit - Lowbit) != 31) {
+    Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
+  } else {
+    Mask = (UINT32) 0xFFFFFFFF;
+  }
+
+  LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader);
+  Temp &= ~(Mask << Lowbit);
+  Temp |= (*Value & Mask) << Lowbit;
+  LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locate next capability pointer
+ *
+ *  Given a SBDFO this routine will find the next PCI capabilities list entry.
+ *  if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is
+ *  returned.
+ *  To start a new search from the head of the list, specify a SBDFO with an offset of zero.
+ *
+ * @param[in,out] Address       Pci address
+ * @param[in]     StdHeader     Standard configuration header
+ */
+
+VOID
+LibAmdPciFindNextCap (
+  IN OUT   PCI_ADDR *Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR Base;
+  UINT32 Offset;
+  UINT32 Temp;
+  PCI_ADDR TempAddress;
+
+  ASSERT (Address != NULL);
+  ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO);
+
+  Base.AddressValue = Address->AddressValue;
+  Offset = Base.Address.Register;
+  Base.Address.Register = 0;
+
+  Address->AddressValue = (UINT32) ILLEGAL_SBDFO;
+
+  // Verify that the SBDFO points to a valid PCI device SANITY CHECK
+  LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader);
+  if (Temp == 0xFFFFFFFF) {
+    ASSERT (FALSE);
+    return; // There is no device at this address
+  }
+
+  // Verify that the device supports a capability list
+  TempAddress.AddressValue = Base.AddressValue + 0x04;
+  LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader);
+  if (Temp == 0) {
+    return; // This PCI device does not support capability lists
+  }
+
+  if (Offset != 0) {
+    // If we are continuing on an existing list
+    TempAddress.AddressValue = Base.AddressValue + Offset;
+    LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader);
+  } else {
+    // We are starting on a new list
+    TempAddress.AddressValue = Base.AddressValue + 0x34;
+    LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader);
+  }
+
+  if (Temp == 0) {
+    return; // We have reached the end of the capabilities list
+  }
+
+  // Error detection and recovery- The statement below protects against
+  //   PCI devices with broken PCI capabilities lists.  Detect a pointer
+  //   that is not uint32 aligned, points into the first 64 reserved DWORDs
+  //   or points back to itself.
+  if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) {
+    ASSERT (FALSE);
+    return;
+  }
+
+  Address->AddressValue = Base.AddressValue + Temp;
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set memory with value
+ *
+ *
+ * @param[in,out] Destination   Pointer to memory range
+ * @param[in]     Value         Value to set memory with
+ * @param[in]     FillLength    Size of the memory range
+ * @param[in]     StdHeader     Standard configuration header (Optional)
+ */
+VOID
+LibAmdMemFill (
+  IN       VOID *Destination,
+  IN       UINT8 Value,
+  IN       UINTN FillLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *Dest;
+  ASSERT (StdHeader != NULL);
+  Dest = Destination;
+  while ((FillLength--) != 0) {
+    *Dest++ = Value;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copy memory
+ *
+ *
+ * @param[in,out] Destination   Pointer to destination buffer
+ * @param[in]     Source        Pointer to source buffer
+ * @param[in]     CopyLength    buffer length
+ * @param[in]     StdHeader     Standard configuration header (Optional)
+ */
+VOID
+LibAmdMemCopy (
+  IN       VOID *Destination,
+  IN       VOID *Source,
+  IN       UINTN CopyLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *Dest;
+  UINT8 *SourcePtr;
+  ASSERT (StdHeader != NULL);
+  Dest = Destination;
+  SourcePtr = Source;
+  while ((CopyLength--) != 0) {
+    *Dest++ = *SourcePtr++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Verify checksum of binary image (B1/B2/B3)
+ *
+ *
+ * @param[in]   ImagePtr      Pointer to image  start
+ * @retval      TRUE          Checksum valid
+ * @retval      FALSE         Checksum invalid
+ */
+BOOLEAN
+LibAmdVerifyImageChecksum (
+  IN       VOID *ImagePtr
+  )
+{
+  // Assume ImagePtr points to the binary start ($AMD)
+  // Checksum is on an even boundary in AMD_IMAGE_HEADER
+
+  UINT16 Sum;
+  UINT32 i;
+
+  Sum = 0;
+
+  i = ((AMD_IMAGE_HEADER*) ImagePtr)->ImageSize;
+
+  while (i > 1) {
+    Sum = Sum + *((UINT16 *)ImagePtr);
+    ImagePtr = (VOID *) ((UINT8 *)ImagePtr + 2);
+    i = i - 2;
+  }
+  if (i > 0) {
+    Sum = Sum + *((UINT8 *) ImagePtr);
+  }
+
+  return (Sum == 0)?TRUE:FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locate AMD binary image that contain specific module
+ *
+ *
+ * @param[in]   StartAddress    Pointer to start range
+ * @param[in]   EndAddress      Pointer to end range
+ * @param[in]   Alignment       Image address alignment
+ * @param[in]   ModuleSignature Module signature.
+ * @retval     NULL  if image not found
+ * @retval     pointer to image header
+ */
+VOID *
+LibAmdLocateImage (
+  IN       VOID *StartAddress,
+  IN       VOID *EndAddress,
+  IN       UINT32 Alignment,
+  IN       CHAR8 ModuleSignature[8]
+  )
+
+{
+  UINT8 *CurrentPtr;
+  AMD_MODULE_HEADER *ModuleHeaderPtr;
+  UINT64 *SearchStr;
+  UINT64 *InputStr;
+
+  CurrentPtr = StartAddress;
+  InputStr = (UINT64 *)ModuleSignature;
+
+  // Search from start to end incrementing by alignment
+  while ((CurrentPtr >= (UINT8 *) StartAddress) && (CurrentPtr < (UINT8 *) EndAddress)) {
+    // First find a binary image
+    if (*((UINT32 *) CurrentPtr) == IMAGE_SIGNATURE) {
+      if (LibAmdVerifyImageChecksum (CurrentPtr)) {
+        // If we have a valid image, search module linked list for a match
+        ModuleHeaderPtr = (AMD_MODULE_HEADER*) ((UINT8 *)CurrentPtr + ((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset);
+        while (ModuleHeaderPtr != NULL) {
+          SearchStr = (UINT64 *)&ModuleHeaderPtr->ModuleIdentifier;
+          if (*InputStr == *SearchStr) {
+            return  CurrentPtr;
+          }
+          ModuleHeaderPtr = (AMD_MODULE_HEADER *)ModuleHeaderPtr->NextBlock;
+        }
+      }
+    }
+    CurrentPtr += Alignment;
+  }
+  return NULL;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the package type mask for the processor
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header (Optional)
+ */
+
+//  Returns the package type mask for the processor
+UINT32
+LibAmdGetPackageType (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32      ProcessorPackageType;
+  CPUID_DATA  CpuId;
+
+  LibAmdCpuidRead (0x80000001, &CpuId, StdHeader);
+  ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+  return (UINT32) (1 << ProcessorPackageType);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the package type mask for the processor
+ *
+ *
+ * @param[in]     AccessWidth     Access width
+ * @param[in]     Data            data
+ * @param[in]     DataMask        data
+ * @param[out]    TemData         typecast data
+ * @param[out]    TempDataMask    typecast data
+ */
+
+
+VOID
+STATIC
+LibAmdGetDataFromPtr (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       VOID         *Data,
+  IN       VOID         *DataMask,
+     OUT   UINT32       *TemData,
+     OUT   UINT32       *TempDataMask
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    *TemData = (UINT32)*(UINT8 *) Data;
+    *TempDataMask = (UINT32)*(UINT8 *) DataMask;
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    *TemData = (UINT32)*(UINT16 *) Data;
+    *TempDataMask = (UINT32)*(UINT16 *) DataMask;
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    *TemData = *(UINT32 *) Data;
+    *TempDataMask = *(UINT32 *) DataMask;
+    break;
+  default:
+    IDS_ERROR_TRAP;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the package type mask for the processor
+ *
+ *
+ * @param[in]     AccessWidth     Access width
+ * @retval        Width in number of bytes
+ */
+
+
+UINT8
+LibAmdAccessWidth (
+  IN       ACCESS_WIDTH AccessWidth
+  )
+{
+  UINT8 Width;
+
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    Width = 1;
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    Width = 2;
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    Width = 4;
+    break;
+  case AccessWidth64:
+  case AccessS3SaveWidth64:
+    Width = 8;
+    break;
+  default:
+    Width = 0;
+    IDS_ERROR_TRAP;
+  }
+  return Width;
+}
+
+VOID
+CpuidRead (
+  IN        UINT32      CpuidFcnAddress,
+  OUT       CPUID_DATA  *Value
+  )
+{
+  __cpuid ((int *)Value, CpuidFcnAddress);
+}
+
+UINT8
+ReadNumberOfCpuCores(
+  VOID
+  )
+{
+  CPUID_DATA  Value;
+  CpuidRead (0x80000008, &Value);
+  return   Value.ECX_Reg & 0xff;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Lib/amdlib.h b/src/vendorcode/amd/agesa/f10/Lib/amdlib.h
new file mode 100755
index 0000000000..a76b01febb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Lib/amdlib.h
@@ -0,0 +1,387 @@
+/**
+ * @file
+ *
+ * AMD Library
+ *
+ * Contains interface to the AMD AGESA library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Lib
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ **/
+
+#ifndef _AMD_LIB_H_
+#define _AMD_LIB_H_
+
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+// Reg Values for ReadCpuReg and WriteCpuReg
+#define    CR4_REG  0x04
+#define    DR0_REG  0x10
+#define    DR1_REG  0x11
+#define    DR2_REG  0x12
+#define    DR3_REG  0x13
+#define    DR7_REG  0x17
+
+// PROTOTYPES FOR amdlib32.asm
+UINT8
+ReadIo8 (
+  IN       UINT16 Address
+  );
+
+UINT16
+ReadIo16 (
+  IN       UINT16 Address
+  );
+
+UINT32
+ReadIo32 (
+  IN       UINT16 Address
+  );
+
+VOID
+WriteIo8 (
+  IN       UINT16 Address,
+  IN       UINT8 Data
+  );
+
+VOID
+WriteIo16 (
+  IN       UINT16 Address,
+  IN       UINT16 Data
+  );
+
+VOID
+WriteIo32 (
+  IN       UINT16 Address,
+  IN       UINT32 Data
+  );
+
+UINT8
+Read64Mem8 (
+  IN       UINT64 Address
+  );
+
+UINT16
+Read64Mem16 (
+  IN       UINT64 Address
+  );
+
+UINT32
+Read64Mem32 (
+  IN       UINT64 Address
+  );
+
+VOID
+Write64Mem8 (
+  IN       UINT64 Address,
+  IN       UINT8 Data
+  );
+
+VOID
+Write64Mem16 (
+  IN       UINT64 Address,
+  IN       UINT16 Data
+  );
+
+VOID
+Write64Mem32 (
+  IN       UINT64 Address,
+  IN       UINT32 Data
+  );
+
+UINT64
+ReadTSC (VOID);
+
+// MSR
+VOID
+LibAmdMsrRead (
+  IN       UINT32 MsrAddress,
+     OUT   UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMsrWrite (
+  IN       UINT32 MsrAddress,
+  IN       UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// IO
+VOID
+LibAmdIoRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// Memory or MMIO
+VOID
+LibAmdMemRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// PCI
+VOID
+LibAmdPciRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciReadBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+     OUT   UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciWriteBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciFindNextCap (
+  IN OUT   PCI_ADDR *Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// CPUID
+VOID
+LibAmdCpuidRead (
+  IN       UINT32 CpuidFcnAddress,
+     OUT   CPUID_DATA *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// Utility Functions
+VOID
+LibAmdMemFill (
+  IN       VOID *Destination,
+  IN       UINT8 Value,
+  IN       UINTN FillLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemCopy (
+  IN       VOID *Destination,
+  IN       VOID *Source,
+  IN       UINTN CopyLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID *
+LibAmdLocateImage (
+  IN       VOID *StartAddress,
+  IN       VOID *EndAddress,
+  IN       UINT32 Alignment,
+  IN       CHAR8 ModuleSignature[8]
+  );
+
+UINT32
+LibAmdGetPackageType (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+LibAmdVerifyImageChecksum (
+  IN       VOID *ImagePtr
+  );
+
+UINT8
+LibAmdBitScanReverse (
+  IN       UINT32 value
+  );
+UINT8
+LibAmdBitScanForward (
+  IN       UINT32 value
+  );
+
+VOID
+LibAmdReadCpuReg (
+  IN       UINT8 RegNum,
+     OUT   UINT32 *Value
+  );
+VOID
+LibAmdWriteCpuReg (
+  IN       UINT8 RegNum,
+  IN       UINT32 Value
+  );
+
+VOID
+LibAmdWriteBackInvalidateCache (
+  IN       VOID
+  );
+
+VOID
+LibAmdSimNowEnterDebugger (VOID);
+
+VOID
+LibAmdHDTBreakPoint (VOID);
+
+UINT8
+LibAmdAccessWidth (
+  IN       ACCESS_WIDTH AccessWidth
+  );
+
+#ifdef __SSE3__
+VOID F10RevDProbeFilterCritical (
+  IN       PCI_ADDR PciAddress,
+  IN       UINT32   PciRegister
+  );
+
+VOID LibAmdCLFlush (
+  IN       UINT64 Address,
+  IN       UINT8  Count
+  );
+#endif
+
+VOID
+IdsOutPort (
+  IN       UINT32 Addr,
+  IN       UINT32 Value,
+  IN       UINT32 Flag
+  );
+
+VOID StopHere(VOID);
+
+VOID
+CpuidRead (
+  IN        UINT32      CpuidFcnAddress,
+  OUT       CPUID_DATA  *Value
+  );
+
+UINT8
+ReadNumberOfCpuCores(
+  VOID
+  );
+
+#endif // _AMD_LIB_H_
diff --git a/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
new file mode 100755
index 0000000000..7ed3d1005a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
@@ -0,0 +1,569 @@
+;/**
+; * @file
+; *
+; * Agesa library 64bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 17071 $   @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+.code
+;/*++
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO byte
+; *
+; *  @param[in]   CX    IO port address
+; *  @param[in]   DL    IO port Value
+; */
+
+PUBLIC  WriteIo8
+WriteIo8        PROC
+        mov     al, dl
+        mov     dx, cx
+        out     dx, al
+        ret
+WriteIo8        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO word
+; *
+; *  @param[in]   CX      IO port address
+; *  @param[in]   DX      IO port Value
+; */
+PUBLIC  WriteIo16
+WriteIo16       PROC
+        mov     ax, dx
+        mov     dx, cx
+        out     dx, ax
+        ret
+WriteIo16       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO dword
+; *
+; *  @param[in]   CX      IO port address
+; *  @param[in]   EDX     IO port Value
+; */
+
+PUBLIC WriteIo32
+WriteIo32       PROC
+        mov     eax, edx
+        mov     dx, cx
+        out     dx, eax
+        ret
+WriteIo32       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO byte
+; *
+; *  @param[in] CX  IO port address
+; *  @retval    AL  IO port Value
+; */
+PUBLIC ReadIo8
+ReadIo8 PROC
+        mov     dx, cx
+        in      al, dx
+        ret
+ReadIo8 ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO word
+; *
+; *  @param[in]   CX  IO port address
+; *  @retval      AX  IO port Value
+; */
+PUBLIC ReadIo16
+ReadIo16        PROC
+        mov     dx, cx
+        in      ax, dx
+        ret
+ReadIo16        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO dword
+; *
+; *  @param[in]   CX  IO port address
+; *  @retval      EAX IO port Value
+; */
+PUBLIC ReadIo32
+ReadIo32        PROC
+        mov     dx, cx
+        in      eax, dx
+        ret
+ReadIo32        ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read MSR
+; *
+; *  @param[in]  RCX      MSR Address
+; *  @param[in]  RDX      Pointer to data
+; *  @param[in]  R8D      ConfigPtr (Optional)
+; */
+PUBLIC LibAmdMsrRead
+LibAmdMsrRead  PROC
+    push rsi
+    mov     rsi, rdx
+    rdmsr
+    mov     [rsi], eax
+    mov     [rsi+4], edx
+    pop rsi
+    ret
+LibAmdMsrRead  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write MSR
+; *
+; *  @param[in]  RCX        MSR Address
+; *  @param[in]  RDX        Pointer to data
+; *  @param[in]  R8D        ConfigPtr  (Optional)
+; */
+PUBLIC LibAmdMsrWrite
+LibAmdMsrWrite                PROC
+    push rsi
+    mov rsi, rdx
+    mov eax, [rsi]
+    and rax, 0ffffffffh
+    mov edx, [rsi+4]
+    and rdx, 0ffffffffh
+    wrmsr
+    pop rsi
+    ret
+LibAmdMsrWrite                ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read CPUID
+; *
+; *  @param[in]  RCX    CPUID function
+; *  @param[in]  RDX    Pointer to CPUID_DATA to save cpuid data
+; *  @param[in]  R8D    ConfigPtr (Optional)
+; */
+PUBLIC LibAmdCpuidRead
+LibAmdCpuidRead       PROC
+
+    push rbx
+    push rsi
+    mov  rsi, rdx
+    mov  rax, rcx
+    cpuid
+    mov [rsi],   eax
+    mov [rsi+4], ebx
+    mov [rsi+8], ecx
+    mov [rsi+12],edx
+    pop rsi
+    pop rbx
+    ret
+
+LibAmdCpuidRead              ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read TSC
+; *
+; *
+; * @retval     RAX Time stamp counter value
+; */
+
+PUBLIC ReadTSC
+ReadTSC  PROC
+    rdtsc
+    and  rax, 0ffffffffh
+    shl  rdx, 32
+    or   rax, rdx
+    ret
+ReadTSC  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO byte
+; *
+; * @param[in]  RCX - Memory Address
+; * @retval     Memory byte at given address
+; */
+PUBLIC  Read64Mem8
+Read64Mem8  PROC
+
+     xor  rax, rax
+     mov  al, [rcx]
+     ret
+
+Read64Mem8  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO word
+; *
+; * @param[in]  RCX - Memory Address
+; * @retval     Memory word at given address
+; */
+PUBLIC  Read64Mem16
+Read64Mem16  PROC
+
+        xor     rax, rax
+        mov     ax, [rcx]
+        ret
+
+Read64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO dword
+; *
+; * @param[in]  RCX - Memory Address
+; * @retval     Memory dword at given address
+; */
+PUBLIC  Read64Mem32
+Read64Mem32  PROC
+
+        xor     rax, rax
+        mov     eax, [rcx]
+        ret
+
+Read64Mem32  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO byte
+; *
+; * @param[in]  RCX   Memory Address
+; * @param[in]  DL    Value to write
+; */
+
+PUBLIC  Write64Mem8
+Write64Mem8  PROC
+
+        xor     rax, rax
+        mov     rax, rdx
+        mov     [rcx], al
+        ret
+
+Write64Mem8  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO word
+; *
+; * @param[in]  RCX   Memory Address
+; * @param[in]  DX    Value to write
+; */
+PUBLIC  Write64Mem16
+Write64Mem16  PROC
+
+        xor     rax, rax
+        mov     rax, rdx
+        mov     [rcx], ax
+        ret
+
+Write64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO dword
+; *
+; * @param[in]  RCX   Memory Address
+; * @param[in]  EDX   Value to write
+; */
+PUBLIC  Write64Mem32
+Write64Mem32  PROC
+
+        xor     rax, rax
+        mov     rax, rdx
+        mov     [rcx], eax
+        ret
+
+Write64Mem32  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read various CPU registers
+; *
+; * @param[in]  CL     Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  RDX    Pointer to value
+; */
+
+PUBLIC  LibAmdReadCpuReg
+LibAmdReadCpuReg PROC
+
+        push    rax
+        xor     rax, rax
+Reg00h:
+        cmp     cl, 00h
+        jne     Reg04h
+        mov     rax, cr0
+        jmp     RegRead
+Reg04h:
+        cmp     cl, 04h
+        jne     Reg10h
+        mov     rax, cr4
+        jmp     RegRead
+Reg10h:
+        cmp     cl, 10h
+        jne     Reg11h
+        mov     rax, dr0
+        jmp     RegRead
+Reg11h:
+        cmp     cl, 11h
+        jne     Reg12h
+        mov     rax, dr1
+        jmp     RegRead
+Reg12h:
+        cmp     cl, 12h
+        jne     Reg13h
+        mov     rax, dr2
+        jmp     RegRead
+Reg13h:
+        cmp     cl, 13h
+        jne     Reg17h
+        mov     rax, dr3
+        jmp     RegRead
+Reg17h:
+        cmp     cl, 17h
+        jne     RegRead
+        mov     rax, dr7
+RegRead:
+        mov     [rdx], eax
+        pop     rax
+        ret
+LibAmdReadCpuReg ENDP
+
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write various CPU registers
+; *
+; * @param[in]  CL    Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  RDX   Value to write
+; */
+
+PUBLIC  LibAmdWriteCpuReg
+LibAmdWriteCpuReg PROC
+
+        push    rax
+Reg00h:
+        cmp     cl, 00h
+        jne     Reg04h
+        mov     rax, cr0
+        mov     eax, edx
+        mov     cr0, rax
+        jmp     Done
+Reg04h:
+        cmp     cl, 04h
+        jne     Reg10h
+        mov     rax, cr4
+        mov     eax, edx
+        mov     cr4, rax
+        jmp     Done
+Reg10h:
+        cmp     cl, 10h
+        jne     Reg11h
+        mov     rax, dr0
+        mov     eax, edx
+        mov     dr0, rax
+        jmp     Done
+Reg11h:
+        cmp     cl, 11h
+        jne     Reg12h
+        mov     rax, dr1
+        mov     eax, edx
+        mov     dr1, rax
+        jmp     Done
+Reg12h:
+        cmp     cl, 12h
+        jne     Reg13h
+        mov     rax, dr2
+        mov     eax, edx
+        mov     dr2, rax
+        jmp     Done
+Reg13h:
+        cmp     cl, 13h
+        jne     Reg17h
+        mov     rax, dr3
+        mov     eax, edx
+        mov     dr3, rax
+        jmp     Done
+Reg17h:
+        cmp     cl, 17h
+        jne     Done
+        mov     rax, dr7
+        mov     eax, edx
+        mov     dr7, rax
+Done:
+        pop     rax
+        ret
+LibAmdWriteCpuReg ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write back invalidate caches using wbinvd.
+; *
+; *
+; *
+; */
+
+PUBLIC LibAmdWriteBackInvalidateCache
+LibAmdWriteBackInvalidateCache PROC
+    wbinvd
+    ret
+LibAmdWriteBackInvalidateCache ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Stop CPU
+; *
+; *
+; *
+; */
+
+PUBLIC StopHere
+StopHere PROC
+@@:
+    jmp short @b
+StopHere ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Enter debugger on SimNow
+; *
+; *
+; *
+; */
+PUBLIC LibAmdSimNowEnterDebugger
+LibAmdSimNowEnterDebugger PROC
+    pushfq
+    mov     rax, 0BACCD00Bh         ; Backdoor in SimNow
+    mov     rbx, 2                  ; Select breakpoint feature
+    cpuid
+@@:
+    jmp short @b
+    popfq
+    ret
+LibAmdSimNowEnterDebugger ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  IDS IO port write
+; *
+; * @param[in]  ECX     IO Port Address
+; * @param[in]  EDX     Value to write
+; * @param[in]  R8D     IDS flags
+; *
+; */
+
+PUBLIC IdsOutPort
+IdsOutPort PROC
+    push rbx
+    push rax
+
+    mov ebx, r8d
+    mov eax, edx
+    mov edx, ecx
+    out dx, eax
+
+    pop rax
+    pop rbx
+    ret
+IdsOutPort  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Force breakpoint on HDT
+; *
+; *
+; */
+PUBLIC LibAmdHDTBreakPoint
+LibAmdHDTBreakPoint PROC
+
+    push rbx
+
+    mov rcx, 0C001100Ah             ;bit 0 = HDT redirect
+    mov rdi, 09C5A203Ah             ;Password
+    rdmsr
+    and rax, 0ffffffffh
+    or rax, 1
+
+    wrmsr
+
+    mov rax, 0B2h                  ;Marker = B2
+    db 0F1h                        ;ICEBP
+
+    pop rbx
+    ret
+
+LibAmdHDTBreakPoint ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most right hand side non-zero bit with
+; *
+; * @param[in]  ECX       Value
+; */
+PUBLIC LibAmdBitScanForward
+LibAmdBitScanForward PROC
+    bsf eax, ecx
+    jnz nonZeroSource
+    mov al,32
+nonZeroSource:
+    ret
+LibAmdBitScanForward  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most left hand side non-zero bit.
+; *
+; * @param[in]  ECX       Value
+; */
+PUBLIC LibAmdBitScanReverse
+LibAmdBitScanReverse PROC
+    bsr eax, ecx
+    jnz nonZeroSource
+    mov al,0FFh
+nonZeroSource:
+    ret
+LibAmdBitScanReverse  ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/MainPage.h b/src/vendorcode/amd/agesa/f10/MainPage.h
new file mode 100755
index 0000000000..fc0c269ce3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/MainPage.h
@@ -0,0 +1,119 @@
+/**
+ * @file
+ *
+ * Create outline and references for mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @mainpage
+ *
+ * The design and maintenance documentation for AGESA Sample Code is organized as
+ * follows.  On this page, you can reference design guides, maintenance guides, and
+ * general documentation.  Detailed Data Structure, Function, and Interface documentation
+ * may be found using the Data Structures or Files tabs.  See Related Pages for a
+ * Release content summary, and, if this is not a production release, lists of To Do's,
+ * Deprecated items, etc.
+ *
+ * @subpage starthere "Start Here - Initial Porting and Integration."
+ *
+ * @subpage optionmain "Build Configuration and Options Guides and Documentation."
+ *
+ * @subpage commonmain "Processor Common Component Guides and Documentation."
+ *
+ * @subpage cpumain "CPU Component Guides and Documentation."
+ *
+ * @subpage htmain "HT Component Guides and Documentation."
+ *
+ * @subpage memmain "MEM Component Guides and Documentation."
+ *
+ * @subpage gnbmain "GNB Component Documentation."
+ *
+ * @subpage idsmain "IDS Component Guides and Documentation."
+ *
+ * @subpage recoverymain "Recovery Component Guides and Documentation."
+ *
+ */
+
+/**
+ * @page starthere Initial Porting and Integration
+ *
+ * @par Basic Check List
+ *
+ * <ul>
+ * <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
+ * AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
+ * <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
+ * and make changes to enable the IDS support desired. It is highly recommended to set the following for
+ * initial integration and development:@n
+ * @code
+ * #define IDSOPT_IDS_ENABLED TRUE
+ * #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+ * #define IDSOPT_ASSERT_ENABLED TRUE
+ * @endcode
+ * <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
+ * <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
+ * <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
+ * <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
+ * </ul>
+ *
+ * @par Debugging Using ASSERT and IDS_ERROR_TRAP
+ *
+ * While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
+ * catch and assist debug of wrapper and platform BIOS issues.
+ *
+ * When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
+ * Stop Code.  A Stop Code is eight hex digits.  The first (most significant) four are the FILECODE.
+ * FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro.  Each file has a
+ * unique code value.
+ * The least significant digits are the line number in that file.
+ * For example, 0210 means the macro is on line two hundred ten.
+ * (see ::IdsErrorStop for more details on stop code display.)
+ *
+ * Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
+ * Comments near each macro use will describe the nature of the error and typical wrapper errors or other
+ * root causes.
+ *
+ * After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
+ * OptionsIds.h, except for regression testing.  IDS is not expected to be enabled in production BIOS builds.
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc
new file mode 100755
index 0000000000..b2125151b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Makefile.inc
@@ -0,0 +1,52 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+## ABSOLUTE AGESA V5 ROOT PATH ##
+AGESA_ROOT ?= $(PWD)
+
+AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR)
+AGESA_INC += -I$(AGESA_ROOT)
+AGESA_INC += -I$(AGESA_ROOT)/Include
+AGESA_INC += -I$(AGESA_ROOT)/Lib
+AGESA_INC += -I$(AGESA_ROOT)/Legacy
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/NbCommon
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x10
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/HY
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x10
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
+
+## AGESA need sse feature ##
+AGESA_CFLAGS = -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+
+export AGESA_ROOT
+export AGESA_INC
+export AGESA_CFLAGS
+CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
+
diff --git a/src/vendorcode/amd/agesa/f10/Porting.h b/src/vendorcode/amd/agesa/f10/Porting.h
new file mode 100755
index 0000000000..c34d9b1cc2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Porting.h
@@ -0,0 +1,277 @@
+/**
+ * @file
+ *
+ * Describes compiler dependencies - to support several compile time environments
+ *
+ * Contains compiler environment porting descriptions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Includes
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ */
+
+#ifndef _PORTING_H_
+#define _PORTING_H_
+
+#if defined (_MSC_VER)
+  #pragma warning(disable: 4103 4001)
+  #pragma warning(push)
+  #if _MSC_VER < 900
+    // -----------------------------------------------------------------------
+    //    Assume MSVC 1.52C (16-bit)
+    //
+    //    NOTE: When using MSVC 1.52C use the following command line:
+    //
+    //       CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
+    //
+    //    This will produce 32-bit code in USE16 segment that is optimized for code
+    //    size.
+    typedef void          VOID;
+
+    // Create the universal 32, 16, and 8-bit data types
+    typedef unsigned long   UINTN;
+    typedef          long   INT32;
+    typedef unsigned long   UINT32;
+    typedef          int    INT16;
+    typedef unsigned int    UINT16;
+    typedef          char   INT8;
+    typedef unsigned char   UINT8;
+    typedef          char   CHAR8;
+    typedef unsigned short  CHAR16;
+
+    /// struct for 16-bit environment handling of 64-bit value
+    typedef struct _UINT64 {
+      IN OUT  UINT32 lo;      ///< lower 32-bits of 64-bit value
+      IN OUT  UINT32 hi;      ///< highest 32-bits of 64-bit value
+    } UINT64;
+
+    // Create the Boolean type
+    #define TRUE  1
+    #define FALSE 0
+    typedef unsigned char BOOLEAN;
+
+    #define CONST const
+    #define STATIC static
+    #define VOLATILE volatile
+    #define CALLCONV __pascal
+    #define ROMDATA __based( __segname( "_CODE" ) )
+    #define _16BYTE_ALIGN   __declspec(align(16))
+
+    // Force tight packing of structures
+    // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+    #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
+    #pragma pack(1)
+
+    //   Disable WORD->BYTE automatic conversion warnings.  Example:
+    //   BYTE LocalByte;
+    //   void MyFunc(BYTE val);
+    //
+    //   MyFunc(LocalByte*2+1); // Warning, automatic conversion
+    //
+    //   The problem is any time math is performed on a BYTE, it is converted to a
+    //   WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
+    //   is generated.  Disable warning C4761
+    #pragma warning( disable : 4761 )
+
+  #else
+    // -----------------------------------------------------------------------
+    //   Assume a 32-bit MSVC++
+    //
+    // Disable the following warnings:
+    // 4100 - 'identifier' : unreferenced formal parameter
+    // 4276 - 'function' : no prototype provided; assumed no parameters
+    // 4214 - non standard extension used : bit field types other than int
+    // 4001 - nonstandard extension 'single line comment' was used
+    // 4142 - benign redefinition of type for following declaration
+    //      - typedef char    INT8
+    #if defined (_M_IX86)
+      #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
+
+      #ifndef VOID
+        typedef void VOID;
+      #endif
+    // Create the universal 32, 16, and 8-bit data types
+      #ifndef UINTN
+        typedef unsigned __w64 UINTN;
+      #endif
+      typedef          __int64 INT64;
+      typedef unsigned __int64 UINT64;
+      typedef          int   INT32;
+      typedef unsigned int   UINT32;
+      typedef          short INT16;
+      typedef unsigned short UINT16;
+      typedef          char  INT8;
+      typedef unsigned char  UINT8;
+      typedef          char  CHAR8;
+      typedef unsigned short CHAR16;
+
+    // Create the Boolean type
+      #ifndef TRUE
+        #define TRUE  1
+      #endif
+      #ifndef FALSE
+        #define FALSE 0
+      #endif
+      typedef unsigned char BOOLEAN;
+
+      // Force tight packing of structures
+      // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+      #pragma pack(1)
+
+      #define CONST const
+      #define STATIC static
+      #define VOLATILE volatile
+      #define CALLCONV
+      #define ROMDATA
+      #define _16BYTE_ALIGN __declspec(align(64))
+      // 64 bit of compiler
+    #else
+      #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
+
+      #ifndef VOID
+        typedef void VOID;
+      #endif
+      // Create the universal 32, 16, and 8-bit data types
+      #ifndef UINTN
+        typedef unsigned __int64 UINTN;
+      #endif
+      typedef          __int64 INT64;
+      typedef unsigned __int64 UINT64;
+      typedef          int   INT32;
+      typedef unsigned int   UINT32;
+      typedef          short INT16;
+      typedef unsigned short UINT16;
+      typedef          char  INT8;
+      typedef unsigned char  UINT8;
+      typedef          char  CHAR8;
+      typedef unsigned short CHAR16;
+
+      // Create the Boolean type
+      #ifndef TRUE
+        #define TRUE  1
+      #endif
+      #ifndef FALSE
+        #define FALSE 0
+      #endif
+      typedef unsigned char BOOLEAN;
+
+      // Force tight packing of structures
+      // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+      #pragma pack(1)
+
+      #define CONST const
+      #define STATIC static
+      #define VOLATILE volatile
+      #define CALLCONV
+      #define ROMDATA
+    #endif
+  #endif
+  // -----------------------------------------------------------------------
+  // End of Microsoft compiler versions
+
+#elif defined __GNUC__
+
+  #define IN
+  #define OUT
+  #define STATIC static
+  #define VOLATILE volatile
+  #define TRUE 1
+  #define FALSE 0
+  #define CONST const
+  #define ROMDATA
+  #define CALLCONV
+  #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
+
+  typedef unsigned char  BOOLEAN;
+  typedef   signed char  INT8;
+  typedef   signed short INT16;
+  typedef   signed long  INT32;
+  typedef unsigned char  CHAR8;
+  typedef unsigned char  UINT8;
+  typedef unsigned short UINT16;
+  typedef unsigned long  UINT32;
+  typedef unsigned long  UINTN;
+  typedef unsigned long  long UINT64;
+  typedef void VOID;
+  //typedef unsigned long  size_t;
+//typedef unsigned int   uintptr_t; 
+// Force tight packing of structures
+// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+#pragma pack(1)
+      
+#define CODE_GROUP(arg)
+#define RDATA_GROUP(arg)
+
+#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) 
+#define MAKE_AS_A_STRING(arg) #arg
+                                 
+// -----------------------------------------------------------------------
+// Common definitions for all compilers
+//
+#include <stddef.h>
+#include "gcc-intrin.h"
+
+#include <assert.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+
+#ifndef NULL
+  #define NULL              (void *)0
+#endif
+#ifdef ROMDATA
+//#undef ROMDATA
+#endif
+//#define ROMDATA __attribute__ ((section("rom.data"))
+
+#else
+  // -----------------------------------------------------------------------
+  // Unknown or unsupported compiler
+  //
+  #error "Unknown compiler in use"
+#endif
+
+
+
+  // -----------------------------------------------------------------------
+  // Common definitions for all compilers
+  //
+
+//Support forward reference construct
+#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
+
+
+// The following are use in conformance to the UEFI style guide
+#define IN
+#define OUT
+
+#endif // _PORTING_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
new file mode 100755
index 0000000000..4313e08695
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
@@ -0,0 +1,1442 @@
+/**
+ * @file
+ *
+ * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] =
+{
+  // Function 0
+
+// F0x68 - Link Transaction Control
+// bit[14:13], BufPriRel = 02h
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      (AMD_F10_ALL & ~AMD_F10_Dx),          // CpuRevision  rev C or less.
+    },
+    {AMD_PF_MULTI_LINK},                     // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 2
+  // 17:16 NpReqData: 2
+  // 15:12 ProbeCmd: 9
+  // 11:8 RspCmd: 9
+  // 7:5 PReq: 2
+  // 4:0 NpReqCmd: 4
+{
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x10,                               // address
+      0x048A9944,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 4
+  // 4:0 NpReqCmd: 18
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x04850292,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 16
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x008502D0,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 3
+  // 17:16 NpReqData: 2
+  // 15:12 ProbeCmd: 8
+  // 11:8 RspCmd: 9
+  // 7:5 PReq: 2
+  // 4:0 NpReqCmd: 4
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x10,                               // address
+      0x008E8944,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x008502CF,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+{
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x14,                               // address
+      0x00000000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x14,                               // address
+      0x00000000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 1
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x14,                               // address
+      0x02010000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x14,                               // address
+      0x00010000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+
+// Function 3 - Misc. Control
+
+// F3x6C - Data Buffer Control
+// XBAR buffer settings
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
+      0x00018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// XBAR buffer settings
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 2
+// bits[30:28] IsocRspDBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
+      0x00028052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00041153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00051153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x10151153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00081111,                           // regData
+      0x00FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00181111,                           // regData
+      0x00FF7777,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 24
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090A18,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 22
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090A16,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 23
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090917,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 23
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090917,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 21
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090915,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = A
+  {
+    ProcCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),  // anything but two.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A00755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    ProcCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),   // exactly two.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 10
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A11755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 9
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00911755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 5
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00511755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 7
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00711555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = ]
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE),     // 4 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00811755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 2
+// bits[23:20] FreeTok = 2
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00211755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 6
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00611555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00811756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// All non probe filter configs
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 4
+// bits[7:4] ProbeTok = 1
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)),     // 2 Socket, half populated, or 4 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000014,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)),     // 2 Socket, fully populated, or 4 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_GANGED,
+      0x000000AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      0x00550055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 1
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      0x00554055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      0x0000012A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x000001A6,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROBEFILTER,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x0000016A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      0x01550155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 2
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      0x0000022A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 1
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      0x01554155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x000001A6,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 =1
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROBEFILTER,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x00000196,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEATURES_ALL,
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      0x0000812A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_COHERENT,
+      0x000081AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10MultiLinkPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h
new file mode 100755
index 0000000000..7573da9c8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Package Type Definitions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _F10_PACKAGE_TYPE_H_
+#define _F10_PACKAGE_TYPE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+// Below equates are defined to cooperate with LibAmdGetPackageType.
+#define PACKAGE_TYPE_FR2_FR5_FR6            (1 << 0)
+#define PACKAGE_TYPE_AM2R2_AM3              (1 << 1)
+#define PACKAGE_TYPE_S1G3_S1G4              (1 << 2)
+#define PACKAGE_TYPE_G34                    (1 << 3)
+#define PACKAGE_TYPE_ASB2                   (1 << 4)
+#define PACKAGE_TYPE_C32                    (1 << 5)
+
+#define PACKAGE_TYPE_FR2                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_FR5                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_FR6                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_S1G3                   PACKAGE_TYPE_S1G3_S1G4
+#define PACKAGE_TYPE_S1G4                   PACKAGE_TYPE_S1G3_S1G4
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif  // _F10_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
new file mode 100755
index 0000000000..1e87ce596b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -0,0 +1,287 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB COF VID Initialization
+ *
+ * Performs the "BIOS Northbridge COF and VID Configuration" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "cpuCommonF10Utilities.h"
+#include "F10PmNbCofVidInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Structure used for performing the steps outlined in
+/// the NB COFVID configuration sequence
+typedef struct {
+  UINT8   NewNbVid;           ///< Destination NB VID code
+  BOOLEAN NbVidUpdateAll;     ///< Status of NbVidUpdateAll
+} NB_COF_VID_INIT_WARM;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PmNbCofVidInitP0P1Core (
+  IN       VOID *NewNbVid,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+PmNbCofVidInitWarmCore (
+  IN       VOID *FunctionData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the "Northbridge COF and
+ * VID Configuration" algorithm.
+ *
+ * The steps are as follows:
+ *    1. Determine if the algorithm is necessary by checking if all NB FIDs
+ *       match in the coherent fabric.  If so, check to see if NbCofVidUpdate
+ *       is zero for all CPUs.  If that is also true, no further steps are
+ *       necessary.  If not + cold reset, proceed to step 2.  If not + warm
+ *       reset, proceed to step 8.
+ *    2. Determine NewNbVid & NewNbFid.
+ *    3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
+ *    4. Copy NewNbVid to P0 NbVid on all local cores.
+ *    5. Transition to P1 on all local cores.
+ *    6. Transition to P0 on local core 0 only.
+ *    7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
+ *    8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
+ *       on all local cores.
+ *    9. Transition to Startup Pstate on all local cores.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmNbCofVidInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  BOOLEAN   PerformNbCofVidCfg;
+  BOOLEAN   SystemNbCofsMatch;
+  UINT8     NewNbFid;
+  UINT8     NewNbVid;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Core;
+  UINT32    SystemNbCof;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT32    Ignored;
+  UINT32    NewNbVoltage;
+  WARM_RESET_REQUEST Request;
+  AP_TASK   TaskPtr;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+  NB_COF_VID_INIT_WARM FunctionData;
+
+  PerformNbCofVidCfg = TRUE;
+  OptionMultiSocketConfiguration.GetSystemNbCof (&SystemNbCof, &SystemNbCofsMatch, StdHeader);
+  if (SystemNbCofsMatch) {
+    if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
+      PerformNbCofVidCfg = FALSE;
+    }
+  }
+  if (PerformNbCofVidCfg) {
+    // get the local node ID
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+    ASSERT (Core == 0);
+
+    // get NewNbVid
+    FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, &Ignored, &NewNbVoltage, StdHeader);
+    ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
+    NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
+    ASSERT (NewNbVid < 0x80);
+
+    if (!(IsWarmReset (StdHeader))) {
+
+      // determine NewNbFid
+      NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
+
+      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
+      TaskPtr.DataTransfer.DataSizeInDwords = 1;
+      TaskPtr.DataTransfer.DataPtr = &NewNbVid;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = 0;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+      // Transition core 0 to P0 and wait for change to complete
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+
+      PciAddress.Address.Register = CPTC0_REG;
+      AndMask = 0xFFFFFFFF;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
+      OrMask = 0x00000000;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
+      ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+      // warm reset request
+      FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
+      Request.RequestBit = TRUE;
+      FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
+    } else {
+      // warm reset path
+
+      FunctionData.NewNbVid = NewNbVid;
+      FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
+
+      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
+      TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
+      TaskPtr.DataTransfer.DataPtr = &FunctionData;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = WAIT_FOR_CORE;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+    }
+  } // skip whole algorithm
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Cold reset support routine for F10PmNbCofVidInit.
+ *
+ * This function implements steps 3, 4, & 5 on each core.
+ *
+ * @param[in]  NewNbVid           NewNbVid determined by core 0 in step 2.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbCofVidInitP0P1Core (
+  IN       VOID *NewNbVid,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 MsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
+  LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
+  ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
+  LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Warm reset support routine for F10PmNbCofVidInit.
+ *
+ * This function implements steps 8 & 9 on each core.
+ *
+ * @param[in]  FunctionData       Contains NewNbVid determined by core 0 in step
+ *                                2, and NbVidUpdateAll.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbCofVidInitWarmCore (
+  IN       VOID *FunctionData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 MsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
+    LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
+        ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
+        LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+      }
+    }
+  }
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (((COFVID_STS_MSR *) &MsrRegister)->StartupPstate), (BOOLEAN) FALSE, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
new file mode 100755
index 0000000000..4e6f3e4e10
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB COF VID Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
+#define _CPU_F10_PM_NB_COF_VID_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmNbCofVidInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_PM_NB_COF_VID_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
new file mode 100755
index 0000000000..455f312090
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -0,0 +1,186 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB Pstate Initialization
+ *
+ * Performs the action described in F3x1F0[NbPstate] as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "F10PmNbPstateInit.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Structure used for modifying the P-state
+/// MSRs on fuse enable CPUs.
+typedef struct {
+  UINT8   NbVid1;             ///< Destination NB VID code
+  UINT8   NbPstate;           ///< Status of NbVidUpdateAll
+} NB_PSTATE_INIT;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PmNbPstateInitCore (
+  IN       VOID *NbPstateParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the actions described in the
+ * description of F3x1F0[NbPstate].
+ *
+ * If F3x1F0[NbPstate] is non zero, it specifies the highest performance
+ * P-state in which to enable NbDid.  Each core must loop through their
+ * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmNbPstateInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32         Core;
+  UINT32         Module;
+  UINT32         PciRegister;
+  UINT32         ProcessorPackageType;
+  UINT32         Socket;
+  AP_TASK        TaskPtr;
+  PCI_ADDR       PciAddress;
+  AGESA_STATUS   IgnoredSts;
+  NB_PSTATE_INIT ApParams;
+
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, StdHeader)) {
+    ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+    if ((CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) ||
+        (ProcessorPackageType != PACKAGE_TYPE_S1G3_S1G4)) {
+      IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+      ASSERT (Core == 0);
+      GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = 0x1F0;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if ((PciRegister & 0x00070000) != 0) {
+        ApParams.NbPstate = (UINT8) ((PciRegister & 0x00070000) >> 16);
+        ASSERT (ApParams.NbPstate < NM_PS_REG);
+
+        PciAddress.Address.Function = FUNC_4;
+        PciAddress.Address.Register = 0x1F4;
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+        ApParams.NbVid1 = (UINT8) ((PciRegister & 0x00003F80) >> 7);
+
+        TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
+        TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
+        TaskPtr.DataTransfer.DataPtr = &ApParams;
+        TaskPtr.DataTransfer.DataTransferFlags = 0;
+        TaskPtr.ExeFlags = WAIT_FOR_CORE;
+        ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmNbPstateInit.
+ *
+ * This function modifies NbVid and NbDid on each core.
+ *
+ * @param[in]  NbPstateParams     Appropriate NbVid1 and NbPstate as determined by core 0.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbPstateInitCore (
+  IN       VOID *NbPstateParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 MsrRegister;
+
+  for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
+    LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      ((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
+      ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
+      LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
new file mode 100755
index 0000000000..d4c868cd02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB P-State Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
+#define _CPU_F10_PM_NB_PSTATE_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmNbPstateInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_PM_NB_PSTATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
new file mode 100755
index 0000000000..a97214ad1a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
@@ -0,0 +1,1267 @@
+/**
+ * @file
+ *
+ * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] =
+{
+// F0x68 - Link Transaction Control
+// bit[14:13], BufPriRel = 01b
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                     // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00002000,                           // regData
+      0x00006000,                           // regMask
+    }
+  },
+// F0x68 - Link Transaction Control
+// bit[24], DispRefModeEn = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_ALL,                             // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00000000,                           // regData
+      0x01000000,                           // regMask
+    }
+  },
+// F0x68 - Link Transaction Control
+// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_UMA,                     // platform Features
+    {
+      PERFORMANCE_IS_WARM_RESET,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x01000000,                           // regData
+      0x01000000,                           // regMask
+    }
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 3
+  // 4:0 NpReqCmd: 11
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x0885026B,                           // Data
+      0x0FFFFFFF                            // Mask
+    },
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x008502CF,                           // Data
+      0x0FFFFFFF                            // Mask
+    },
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 1
+  // 18:16 IsocNpReqCmd: 7
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x000F0000,                           // Data
+      0x1FFF0000                            // Mask
+    },
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x00010000,                           // Data
+      0x1FFF0000                            // Mask
+    },
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// bit[8] LS2En = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                     // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 10b
+// bits[31:28] MctVarPriCntLmt = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x00002000,                           // regData
+      0xF0003000,                           // regMask
+    }
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 11b
+// bits[31:28] MctVarPriCntLmt = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),       // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x10003000,                           // regData
+      0xF0003000,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32  0
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
+      0x00000000,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 0
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
+      0x00000000,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 1
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
+      0x00000400,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 1
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
+      0x00000400,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x00018052,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x60018051,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x60018051,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00041153,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 2
+// bits[22:20] IsocReqCBC = 2
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x61221151,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 2
+// bits[22:20] IsocReqCBC = 2
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x61221151,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x11141153,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00081111,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = 9
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x91180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = 9
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x91180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = C
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xC1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = C
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xC1181111,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = F
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xF1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = F
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xF1181111,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 8
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x01880101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x007FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080C,                           // regData
+      0x007FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080C,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 9
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070809,                           // regData
+      0x007FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 9
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070809,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 17
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070811,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000016,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20, 2-core is 20
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000014,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000012,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000010,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x0000000E,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x0000000C,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 2
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37656,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 1
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x8000152A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 1
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x8000152A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+  // F3x158 - Link to XCS Token Count Registers
+  // bits [3:0]LnkToXcsDRToken = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU),
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000000,
+      0x0000000F
+    }
+  },
+  // F3x158 - Link to XCS Token Count Registers
+  // bits [3:0]LnkToXcsDRToken = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA_IFCM | AMD_PF_UMA),
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,
+      0x0000000F
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10SingleLinkPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
new file mode 100755
index 0000000000..c4f819a062
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -0,0 +1,146 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/BL
+ * @e \$Revision: 10071 $   @e \$Date: 2008-12-17 08:03:04 +0800 (Wed, 17 Dec 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable BL-C Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in,out]   PciAddress               Pointer to Pci address struct.
+ *    @param[in,out]   AndMask                  Pointer to AND mask bits.
+ *    @param[in,out]   OrMask                   Pointer to Or mask bits.
+ *    @param[in]       StdHeader                Handle of Header for calling lib functions and services.
+ */
+VOID
+GetF10BlCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN OUT   PCI_ADDR                     *PciAddress,
+  IN OUT   UINT32                       *AndMask,
+  IN OUT   UINT32                       *OrMask,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32     CoreCount;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
+    //
+    // F3xDC[25:19] = 04h
+    // F3xDC[18:16] = 111b
+    //
+    *AndMask = 0xFC00FFFF;
+    *OrMask = 0x00270000;
+  } else {
+    //
+    // F3xDC[25:19] = 28h
+    // F3xDC[18:16] = 111b
+    //
+    *AndMask = 0xFC00FFFF;
+    *OrMask = 0x01470000;
+
+    //
+    //For BL_C2 single Core, F3xDC[18:16] = 0
+    //
+    GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+    if (CoreCount == 1) {
+      if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
+        *OrMask = 0x01400000;
+      }
+    }
+  }
+
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
+{
+  0,
+  GetF10BlCacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
new file mode 100755
index 0000000000..b81e267c3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
+{
+  0x1052, 0x1041,
+  0x1053, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
new file mode 100755
index 0000000000..a3d744ccf9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT  Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
+{
+
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+//
+// Deemphasis Settings
+//
+
+// For BL-C3, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_BL_C3                         // CpuRevision
+    },
+    AMD_PF_ALL,                             // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10BlHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
new file mode 100755
index 0000000000..32a9fcb802
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] =
+{
+  {
+    0x1052,
+    AMD_F10_BL_C2
+  },
+  {
+    0x1053,
+    AMD_F10_BL_C3
+  }
+};
+
+VOID
+GetF10BlLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **BlIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *BlIdPtr = CpuF10BlLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_BL;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
+//};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
new file mode 100755
index 0000000000..2a1bfa9a56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10BlMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
new file mode 100755
index 0000000000..fb7a30ddc3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
new file mode 100755
index 0000000000..c3bbb55e23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
@@ -0,0 +1,174 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
+{
+  // Function 0
+
+// F0x16C - Link Global Extended Control Register, Errata 351
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C2                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// Errata 351 (only need to override single link case.)
+// bit[8] LS2En = 0,
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C2                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000000,                           // regData
+      0x00000100,                           // regMask
+    }
+  },
+
+
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_Cx                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEATURES_ALL,                 // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000000,                           // regData
+      0x10000000,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10BlPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
new file mode 100755
index 0000000000..c1c9db0f33
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/DA
+ * @e \$Revision: 10071 $   @e \$Date: 2008-12-17 08:03:04 +0800 (Wed, 17 Dec 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable DA-C Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in,out]   PciAddress               Pointer to Pci address struct.
+ *    @param[in,out]   AndMask                  Pointer to AND mask bits.
+ *    @param[in,out]   OrMask                   Pointer to Or mask bits.
+ *    @param[in]       StdHeader                Handle of Header for calling lib functions and services.
+ */
+VOID
+GetF10DaCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN OUT   PCI_ADDR                     *PciAddress,
+  IN OUT   UINT32                       *AndMask,
+  IN OUT   UINT32                       *OrMask,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32     CoreCount;
+  CPU_LOGICAL_ID LogicalId;
+
+  //
+  // F3xDC[25:19] = 04h
+  // F3xDC[18:16] = 111b
+  //
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  *AndMask = 0xFC00FFFF;
+  *OrMask = 0x00270000;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if (LogicalId.Revision == AMD_F10_DA_C2) {
+    //
+    //For DA_C2 single Core, F3xDC[18:16] = 0
+    //
+    GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+    if (CoreCount == 1) {
+      *OrMask = 0x00200000;
+    }
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt =
+{
+  0,
+  GetF10DaCacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
new file mode 100755
index 0000000000..afedd8890d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
+{
+  0x1062, 0x1062,
+  0x1063, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  DaEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10DaMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **DaEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
new file mode 100755
index 0000000000..91ac42329e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
@@ -0,0 +1,278 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] =
+{
+
+//
+// Deemphasis Settings
+//
+
+// For DA, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10DaHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
new file mode 100755
index 0000000000..0917fb3173
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] =
+{
+  {
+    0x1062,
+    AMD_F10_DA_C2
+  },
+  {
+    0x1063,
+    AMD_F10_DA_C3
+  }
+};
+
+VOID
+GetF10DaLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **DaIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *DaIdPtr = CpuF10DaLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_DA;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
+//};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
new file mode 100755
index 0000000000..48a8cd0bb1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  DaUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10DaMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **DaUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10DaMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
new file mode 100755
index 0000000000..836760aacc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
new file mode 100755
index 0000000000..77305cb549
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
@@ -0,0 +1,172 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] =
+{
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }
+  },
+
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_Cx                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEATURES_ALL,                 // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 1
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000800,                           // regData
+      0x10003800,                           // regMask
+    }
+  },
+// F3xD4 - Clock Power/Timing Control 0 Register
+// bits[30:28] NbClkDiv = 5
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_C2                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEAT_HT3,                     // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0x50000000,                           // regData
+      0x70000000,                           // regMask
+    }
+  },
+// F3x188 - NB Extended Configuration Low Register
+// bits[4] EnStpGntOnFlushMaskWakeup = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_Cx                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00000010,                           // regData
+      0x00000010,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10DaPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
new file mode 100755
index 0000000000..949b846463
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 5832 $   @e \$Date: 2008-04-15 16:30:24 -0700 (Tue, 15 Apr 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000085 for 1040 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 =
+{
+0x08,
+0x20,
+0x01,
+0x05,
+0x85,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xc1,
+0xb9,
+0x5d,
+0x3d,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x40,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x2f,
+0x02,
+0x00,
+0x00,
+0xa0,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xcf,
+0xf8,
+0xff,
+0x2a,
+0xc3,
+0x3f,
+0xd5,
+0xfd,
+0xbc,
+0xff,
+0xff,
+0xb3,
+0x0f,
+0xff,
+0x58,
+0xd5,
+0xf0,
+0x35,
+0x95,
+0x03,
+0x1d,
+0xf8,
+0x63,
+0x7b,
+0x40,
+0x03,
+0xd4,
+0x00,
+0x80,
+0x77,
+0xff,
+0x7f,
+0xfe,
+0xe1,
+0x98,
+0x8a,
+0x54,
+0xfe,
+0xaf,
+0xff,
+0xff,
+0x87,
+0x7f,
+0xa9,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x1f,
+0xc0,
+0x65,
+0xf4,
+0x0d,
+0xf0,
+0xe0,
+0x8f,
+0xfe,
+0x04,
+0xde,
+0x04,
+0x03,
+0xad,
+0xc3,
+0x2f,
+0xfe,
+0xa9,
+0xfc,
+0x07,
+0x00,
+0x3f,
+0x0f,
+0xff,
+0x15,
+0x00,
+0xb0,
+0x00,
+0xf8,
+0xaf,
+0xe4,
+0x3f,
+0x07,
+0xf8,
+0x79,
+0xf8,
+0xfe,
+0xff,
+0x97,
+0xa7,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0xbf,
+0xf1,
+0x00,
+0xfe,
+0x7f,
+0x6f,
+0x80,
+0x03,
+0x4a,
+0x1a,
+0x00,
+0xc8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xfb,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfd,
+0x6b,
+0x00,
+0xa0,
+0xcf,
+0x56,
+0x0e,
+0x80,
+0xe0,
+0x0f,
+0xe8,
+0x75,
+0xf6,
+0xff,
+0xff,
+0x00,
+0xc3,
+0xbb,
+0x16,
+0xf2,
+0x04,
+0x37,
+0xf8,
+0x13,
+0x0e,
+0x7f,
+0x0c,
+0xb8,
+0xe0,
+0xdc,
+0x35,
+0x00,
+0x60,
+0xff,
+0xff,
+0x1f,
+0x7f,
+0x78,
+0xc7,
+0xa2,
+0x95,
+0xff,
+0xe9,
+0x3f,
+0xdf,
+0xe0,
+0xcf,
+0x2a,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0xff,
+0xf2,
+0xbf,
+0xff,
+0xfd,
+0x1f,
+0xfc,
+0x7b,
+0x0f,
+0xc0,
+0x23,
+0xd0,
+0xed,
+0xf5,
+0xe0,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfe,
+0x03,
+0xf9,
+0x5f,
+0x01,
+0x7e,
+0x1e,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x4c,
+0x06,
+0x00,
+0xbc,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c
new file mode 100755
index 0000000000..e25ca890f1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000086 for 1041 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 5832 $   @e \$Date: 2008-04-15 16:30:24 -0700 (Tue, 15 Apr 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000086 for 1041 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000086 =
+{
+0x08,
+0x20,
+0x01,
+0x05,
+0x86,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0x04,
+0xde,
+0x30,
+0x03,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x41,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0xa0,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x97,
+0xd1,
+0x7f,
+0x00,
+0x83,
+0x3f,
+0x36,
+0xc0,
+0xa0,
+0x1b,
+0xf8,
+0x13,
+0x0e,
+0xbf,
+0x0c,
+0xb4,
+0xf2,
+0x1f,
+0xf8,
+0xa7,
+0x3c,
+0xfc,
+0x03,
+0xfc,
+0x40,
+0x03,
+0x54,
+0x00,
+0x92,
+0xff,
+0xe0,
+0xbf,
+0xe7,
+0xe1,
+0x1f,
+0xe0,
+0x5f,
+0x9e,
+0xfa,
+0xff,
+0x9f,
+0x87,
+0x7f,
+0x80,
+0x03,
+0xf8,
+0xff,
+0xc6,
+0x01,
+0x0e,
+0xfc,
+0xbd,
+0x00,
+0xa0,
+0x2a,
+0x69,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0xff,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xfb,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfd,
+0x6b,
+0x00,
+0xa0,
+0xff,
+0xfe,
+0xff,
+0xcb,
+0xf0,
+0xef,
+0xf5,
+0x7f,
+0x8f,
+0x40,
+0x3f,
+0x00,
+0x83,
+0xbf,
+0xb7,
+0xd7,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe4,
+0x7f,
+0xf9,
+0x0f,
+0x79,
+0xf8,
+0x07,
+0xf8,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf0,
+0x32,
+0x19,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c
new file mode 100755
index 0000000000..090cd918da
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000098 for 1062 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000098 for 1062 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000098 =
+{
+0x08,
+0x20,
+0x11,
+0x11,
+0x98,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xf8,
+0x53,
+0xca,
+0x9a,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x62,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x9a,
+0x0b,
+0x00,
+0x00,
+0x16,
+0x0c,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x6f,
+0x58,
+0x39,
+0x00,
+0x81,
+0x3f,
+0xa0,
+0xd7,
+0x04,
+0x00,
+0xfc,
+0xb7,
+0x0f,
+0xff,
+0x58,
+0xf7,
+0x72,
+0xc0,
+0xff,
+0x6f,
+0x3c,
+0xfc,
+0x03,
+0xfc,
+0xc0,
+0x18,
+0xd5,
+0x00,
+0x80,
+0xff,
+0x66,
+0x3c,
+0xeb,
+0xc0,
+0x9f,
+0xd9,
+0x4d,
+0xee,
+0xf8,
+0xff,
+0xff,
+0x83,
+0x7f,
+0xa6,
+0x07,
+0xe8,
+0xff,
+0xff,
+0xe8,
+0x1f,
+0xbe,
+0xb5,
+0x00,
+0x60,
+0x2f,
+0x6a,
+0x0e,
+0xc0,
+0xd3,
+0x37,
+0x08,
+0x70,
+0xe0,
+0x0f,
+0xff,
+0xaf,
+0x13,
+0xfc,
+0xd7,
+0xcf,
+0xc3,
+0xbf,
+0xeb,
+0x01,
+0xfc,
+0x67,
+0xde,
+0x00,
+0x0f,
+0xfe,
+0x35,
+0x00,
+0xd0,
+0x00,
+0xff,
+0x1f,
+0x40,
+0xfc,
+0xc7,
+0x42,
+0x7e,
+0x78,
+0xef,
+0xff,
+0x16,
+0xfe,
+0x0f,
+0x60,
+0xcb,
+0xe1,
+0xb7,
+0x72,
+0x00,
+0xee,
+0x7e,
+0x00,
+0x9f,
+0x83,
+0x9f,
+0x1a,
+0x00,
+0x58,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x00,
+0xfa,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0xe0,
+0xf8,
+0xff,
+0x7f,
+0x8b,
+0xf0,
+0x0f,
+0x70,
+0xd6,
+0xff,
+0xdb,
+0x7f,
+0x2c,
+0xc3,
+0x3f,
+0xd6,
+0xe2,
+0xfc,
+0x67,
+0xeb,
+0x01,
+0x0f,
+0xfd,
+0x5e,
+0x3e,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c
new file mode 100755
index 0000000000..ae26d0f563
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000B6 for 1043 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000b6 for 1043 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6 =
+{
+0x09,
+0x20,
+0x31,
+0x07,
+0xb6,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xe9,
+0x98,
+0xda,
+0x6b,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x43,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x10,
+0x0c,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x18,
+0x80,
+0x38,
+0xc0,
+0x83,
+0x37,
+0x80,
+0xff,
+0xb8,
+0xff,
+0xff,
+0x13,
+0x0e,
+0xbf,
+0x0c,
+0xb6,
+0x7a,
+0xc4,
+0xff,
+0x2f,
+0x3c,
+0xfc,
+0x6b,
+0xfd,
+0x40,
+0x03,
+0xd4,
+0x00,
+0x97,
+0xff,
+0xff,
+0xff,
+0xe7,
+0xe1,
+0x1f,
+0xe0,
+0x00,
+0xfe,
+0xbf,
+0xf5,
+0x9f,
+0x87,
+0x7e,
+0x22,
+0x01,
+0xc6,
+0x00,
+0xc4,
+0x7c,
+0x1e,
+0xfa,
+0x01,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0xff,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0x20,
+0x04,
+0xff,
+0xbf,
+0xe8,
+0xf0,
+0xaf,
+0xf5,
+0xf3,
+0xff,
+0xd9,
+0x7a,
+0x00,
+0x83,
+0x3f,
+0x31,
+0xc0,
+0x0c,
+0x7d,
+0xe3,
+0x00,
+0x0f,
+0xfe,
+0x80,
+0x5e,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0x65,
+0xfe,
+0xff,
+0x9f,
+0x7f,
+0xf8,
+0xc7,
+0xba,
+0x96,
+0xf2,
+0xff,
+0x7f,
+0xfa,
+0xe1,
+0x1f,
+0xeb,
+0x45,
+0x0e,
+0xf8,
+0xff,
+0x9f,
+0x87,
+0x7f,
+0x80,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x5f,
+0x8c,
+0x7b,
+0x1d,
+0xf8,
+0x13,
+0xbf,
+0xe8,
+0x1a,
+0xff,
+0xf4,
+0xf3,
+0xf0,
+0x4f,
+0xff,
+0x2f,
+0xe3,
+0xff,
+0xd7,
+0xf5,
+0xc3,
+0xbf,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xd6,
+0x03,
+0xf8,
+0xdf,
+0x89,
+0x01,
+0x1e,
+0xfc,
+0xfb,
+0x0f,
+0xe0,
+0x3f,
+0xd6,
+0xa2,
+0x7f,
+0xf8,
+0xff,
+0x7f,
+0x82,
+0xff,
+0x97,
+0xc1,
+0xd6,
+0xe1,
+0x40,
+0x02,
+0x00,
+0x14,
+0x7f,
+0xff,
+0x01,
+0xfc,
+0xdf,
+0x5a,
+0xf4,
+0x0f,
+0xfe,
+0xff,
+0xef,
+0x32,
+0xfc,
+0x03,
+0x9c,
+0x35,
+0x7f,
+0xf7,
+0x5f,
+0xcb,
+0xf0,
+0xaf,
+0xf5,
+0xff,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x5a,
+0x87,
+0x5f,
+0xad,
+0x2b,
+0xf8,
+0xdf,
+0xd6,
+0x03,
+0x1e,
+0xfa,
+0x89,
+0x7c,
+0x20,
+0x7d,
+0xc0,
+0x9f,
+0x75,
+0xf8,
+0x65,
+0xb0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0xdb,
+0x7a,
+0xc0,
+0x83,
+0x3f,
+0x31,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xf4,
+0x0f,
+0xdf,
+0x5a,
+0x4f,
+0xa0,
+0x3e,
+0xe0,
+0xd8,
+0x3a,
+0xfc,
+0x32,
+0x00,
+0xc0,
+0x01,
+0x48,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
new file mode 100755
index 0000000000..a15cad701f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
@@ -0,0 +1,436 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
+{
+// 0x60:0x68
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0x60, 0x68,                           // Address range
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0x70:0x78
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0x70, 0x78,                           // Address range
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// Erratum 354
+// 0x40:48
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_C2 | AMD_F10_C3)           // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0x40, 0x48,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0x50:0x58
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_C2 | AMD_F10_C3)          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0x50, 0x58,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0xC0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0xC0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }
+  },
+// 0xD0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0xD0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }
+  },
+// 0xCF
+// FIFO_PTR_OPT_VALUE
+  {
+    HtPhyProfileRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      PERFORMANCE_NB_PSTATES_ENABLE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// 0xDF
+// FIFO_PTR_OPT_VALUE
+  {
+    HtPhyProfileRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      PERFORMANCE_NB_PSTATES_ENABLE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// 0x520A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                           // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_ALL,                   //
+      0x520A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }
+  },
+// 0x530A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                           // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_ALL,                   //
+      0x530A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }
+  },
+
+
+
+
+//
+// Deemphasis Settings
+//
+
+// For C3, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RevCHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
new file mode 100755
index 0000000000..93b9216251
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -0,0 +1,178 @@
+/**
+ * @file
+ *
+ * AMD Family_10 HW C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the hardware C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuHwC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeHwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should hardware C1e be enabled
+ *
+ * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsHwC1eSupported (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e on a family 10h CPU.
+ *
+ * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeHwC1e (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+  AP_TASK TaskPtr;
+
+  MsrRegister = 0;
+  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
+  ((INTPEND_MSR *) &MsrRegister)->IoMsgData = 0xC1;
+  ((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
+  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
+  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
+
+  TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e on a family 10h core.
+ *
+ * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeHwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  MsrRegister;
+
+  // Enable C1e
+  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
+
+  // Set OS Visible Workaround Status BIT1 to indicate that C1e
+  // is enabled.
+  LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
+  MsrRegister |= BIT1;
+  LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
+}
+
+
+CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
+{
+  0,
+  F10IsHwC1eSupported,
+  F10InitializeHwC1e
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
new file mode 100755
index 0000000000..bd1f788ca6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
@@ -0,0 +1,130 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// bit[21] = 1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_BU_CFG,                           // MSR Address
+      (1 << 21),                            // OR Mask
+      (1 << 21),                            // NAND Mask
+    }
+  },
+
+// MSR_BU_CFG2 (0xC001102A)
+// bit[50] = 1
+// For GH rev C1 and later [RdMmExtCfgQwEn]=1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_BU_CFG2,                          // MSR Address
+      0x0004000000000000,                   // OR Mask
+      0x0004000000000000,                   // NAND Mask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
new file mode 100755
index 0000000000..6abe3895e6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
@@ -0,0 +1,261 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/RevC
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
+{
+// Function 2 - DRAM Controller
+
+// F2x1B0 - Extended Memory Controller Configuration Low Register
+//
+// bit[5:4], AdapPrefNegativeStep = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
+      0x00000000,                           // regData
+      0x00000030,                           // regMask
+    }
+  },
+// Function 3 - Misc. Control
+
+// F3x158 - Link to XCS Token Count
+// bits[3:0] LnkToXcsDRToken = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    AMD_PF_UMA,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,                           // regData
+      0x0000000F,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C2
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 1
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000E681,                           // regData
+      0x0000FFFF,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEAT_HT1,                     // link feats
+      PACKAGE_TYPE_ASB2,                    // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x00008700,                           // regData
+      0x0000FF00,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 1
+// bits[7:5] ClkDivisor = 7
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                           // CpuRevision
+    },
+    AMD_PF_ALL,                             // platformFeatures
+    {
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000F600,                           // regData
+      0x0000FF00,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEAT_HT1,                     // link feats
+      PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2),  // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x00008700,                           // regData
+      0x0000FF00,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }
+  },
+// F3x180 - NB Extended Configuration
+// bits[23] SyncFloodOnDramTempErr = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x00800000,                           // regData
+      0x00800000,                           // regMask
+    }
+  },
+// F3x188 - NB Extended Configuration Low Register
+// Must be set by BIOS
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00400000,                           // regData
+      0x00400000,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RevCPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
new file mode 100755
index 0000000000..06a4fa7632
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -0,0 +1,401 @@
+/**
+ * @file
+ *
+ * AMD Family_10 revision Cx specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h rev C.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "GeneralServices.h"
+#include "cpuEarlyInit.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on a revision C processor.
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+F10CommonRevCSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    TempVar32_a;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS AgesaStatus;
+
+  switch (*LeveledCores) {
+  case 1:
+    CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    break;
+  case 2:
+    CoreDisableBits = DOWNCORE_MASK_DUAL;
+    break;
+  case 3:
+    CoreDisableBits = DOWNCORE_MASK_TRI;
+    break;
+  default:
+    CoreDisableBits = 0;
+    break;
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a = (TempVar32_a >> 12) & 0x3;
+      if (TempVar32_a == 0) {
+        CoreDisableBits &= 0x1;
+      } else if (TempVar32_a == 1) {
+        CoreDisableBits &= 0x3;
+      } else if (TempVar32_a == 2) {
+        CoreDisableBits &= 0x7;
+      } else if (TempVar32_a == 3) {
+        CoreDisableBits &= 0x0F;
+      }
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a |= CoreDisableBits;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+    }
+  }
+
+  return;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
+{
+  0,
+  F10CommonRevCSetDownCoreRegister
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current on a revision C processor.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F10CommonRevCGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       IddDiv;
+  UINT32       CmpCap;
+  UINT32       PciRegister;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Ignored;
+  UINT32       MsrAddress;
+  UINT32       SinglePlaneNbIdd;
+  UINT64       PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
+  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
+    CmpCap++;
+
+    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
+    case 0:
+      IddDiv = 1000;
+      break;
+    case 1:
+      IddDiv = 100;
+      break;
+    case 2:
+      IddDiv = 10;
+      break;
+    default:  // IddDiv = 3 is reserved. Use 10
+      ASSERT (FALSE);
+      IddDiv = 10;
+      break;
+    }
+
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
+    if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
+      *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
+    } else {
+      PciAddress.Address.Register = PRCT_INFO_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
+      SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &PciRegister)->SinglePlaneNbIdd;
+      SinglePlaneNbIdd <<= 1;
+      *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
+    }
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F10CommonRevCGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProductInfoRegister;
+
+  PciAddress->Address.Register = PRCT_INFO_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+  *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
+  return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[out]  VoltageInuV              Northbridge voltage in uV.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS     Always succeeds.
+ */
+AGESA_STATUS
+F10CommonRevCGetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProductInfoRegister;
+  UINT32 PciRegister;
+  UINT32 NbFid;
+  UINT32 NbVid;
+  UINT64 MsrRegister;
+
+  PciAddress->Address.Register = PRCT_INFO_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+  if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
+    PciAddress->Address.Register = CPTC0_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
+    NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+    NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
+  } else {
+    NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
+    NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
+    PciAddress->Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
+    if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 0) {
+      NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
+      NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
+    }
+  }
+  *FrequencyInMHz = ((NbFid + 4) * 200);
+  *VoltageInuV = (1550000 - (12500 * NbVid));
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F10CommonRevCIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32         Core;
+  UINT32         Module;
+  UINT32         NbPstate;
+  UINT32         Socket;
+  PCI_ADDR       PciAddress;
+  AGESA_STATUS   IgnoredSts;
+  CPU_LOGICAL_ID LogicalId;
+  BOOLEAN        Result;
+
+  Result = FALSE;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F10_C3) != 0) {
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = 0x1F0;
+    LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
+    if (NbPstate != 0) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get number of processor cores to be used in determining the brand string.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of cores to be used in brand string calculation.
+ */
+UINT8
+F10CommonRevCGetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Core;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = NB_CAPS_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
new file mode 100755
index 0000000000..79858d24a9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -0,0 +1,105 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
+{
+  0x1040, 0x1040,
+  0x1041, 0x1041,
+  0x1042, 0x1041,
+  0x1043, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  RbEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10RbMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **RbEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
new file mode 100755
index 0000000000..424f5ca31a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -0,0 +1,115 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] =
+{
+// Erratum 354
+// 0x40:0x48
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C1)                     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0x40, 0x48,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0x50:0x58
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C1)                     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0x50, 0x58,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RbHtPhyRegisters
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
new file mode 100755
index 0000000000..c9d5aed20f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
@@ -0,0 +1,109 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] =
+{
+  {
+    0x1040,
+    AMD_F10_RB_C0
+  },
+  {
+    0x1041,
+    AMD_F10_RB_C1
+  },
+  {
+    0x1042,
+    AMD_F10_RB_C2
+  },
+  {
+    0x1043,
+    AMD_F10_RB_C3
+  }
+};
+
+VOID
+GetF10RbLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **RbIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *RbIdPtr = CpuF10RbLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_RB;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray
+//};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
new file mode 100755
index 0000000000..7362ebdbd6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB microcode patches
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  RbUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10RbMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **RbUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10RbMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
new file mode 100755
index 0000000000..a4c0a91129
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
@@ -0,0 +1,115 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_DC_CFG (0xC0011022)
+// bits[43:42] = 0
+// Errata #326
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                       // CpuFamily
+      AMD_F10_RB_C0                        // CpuRevision
+    },
+    AMD_PF_MULTI_LINK,                     // platformFeatures
+    {
+      MSR_DC_CFG,                            // MSR Address
+      0x0000000000000000,                    // OR Mask
+      0x00000C0000000000,                    // NAND Mask
+    }
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// Erratum #309 BU_CFG[23]=1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                            // platformFeatures
+    {
+      MSR_BU_CFG,                            // MSR Address
+      (1 << 23),                             // OR Mask
+      (1 << 23),                             // NAND Mask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
new file mode 100755
index 0000000000..6bfe0b6303
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -0,0 +1,212 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] =
+{
+  // Function 0
+
+// F0x16C - Link Global Extended Control Register, Errata 351
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// Errata 351 (only need to override single link case.)
+// bit[8] LS2En = 0,
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+     (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000000,                           // regData
+      0x00000100,                           // regMask
+    }
+  },
+
+
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00002800,                           // regData
+      0x00003800,                           // regMask
+    }
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000000,                           // regData
+      0x10000000,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_ALL                      // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00006000,                           // regData
+      0x00007000,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C0                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                            // CpuRevision
+    },
+    AMD_PF_ALL,                             // platformFeatures
+    {
+      PERFORMANCE_NB_PSTATES_ENABLE,        // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RbPciRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
new file mode 100755
index 0000000000..a86f326b8d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
@@ -0,0 +1,1037 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c4 for 1081 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVD
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c4 for 1081 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4 =
+{
+{
+0x10,
+0x20,
+0x03,
+0x03,
+0xc4,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x01,
+0x4a,
+0xe0,
+0x9c,
+0x93,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x81,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0xa7,
+0x0b,
+0x00,
+0x00,
+0x14,
+0x0c,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0x51,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x4f,
+0xdf,
+0x38,
+0x00,
+0x81,
+0x3f,
+0x20,
+0xc0,
+0x4e,
+0xf0,
+0xff,
+0xbf,
+0x0f,
+0xff,
+0x5e,
+0x3f,
+0xf0,
+0xdf,
+0xad,
+0x07,
+0x3d,
+0xf8,
+0x7b,
+0x7b,
+0xc0,
+0x00,
+0xd4,
+0x00,
+0x13,
+0xf1,
+0xff,
+0xff,
+0xac,
+0xe1,
+0x1f,
+0xe0,
+0x4e,
+0xfe,
+0xbb,
+0xff,
+0xfe,
+0x87,
+0x7f,
+0xa7,
+0x03,
+0xf8,
+0x7f,
+0xd6,
+0x7c,
+0x1e,
+0xfa,
+0xbd,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x0e,
+0x00,
+0x3d,
+0x57,
+0xe0,
+0x73,
+0xd0,
+0x0f,
+0xff,
+0x2e,
+0xfe,
+0xff,
+0xc0,
+0xcf,
+0xc3,
+0x3f,
+0xeb,
+0x01,
+0xfc,
+0x77,
+0x5a,
+0x3e,
+0x0f,
+0xfd,
+0x35,
+0x00,
+0x90,
+0x3e,
+0xff,
+0x9f,
+0xe0,
+0xfd,
+0x65,
+0x60,
+0x75,
+0xf8,
+0x9f,
+0xff,
+0x97,
+0xff,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0x03,
+0xf5,
+0xde,
+0xff,
+0x7e,
+0x2c,
+0x9f,
+0x87,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x6f,
+0x95,
+0x03,
+0x50,
+0xf4,
+0x03,
+0xf8,
+0x1c,
+0xf8,
+0xff,
+0x3f,
+0x00,
+0xf0,
+0xee,
+0x84,
+0xfc,
+0xfe,
+0xff,
+0xff,
+0x22,
+0xc3,
+0x1f,
+0x51,
+0x96,
+0x38,
+0x16,
+0x0d,
+0x00,
+0xf8,
+0xfe,
+0xfe,
+0x01,
+0x0e,
+0xfc,
+0xb1,
+0x01,
+0xe5,
+0xa6,
+0xff,
+0x1f,
+0x79,
+0xf8,
+0x07,
+0xf8,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfa,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x3f,
+0xe3,
+0x3e,
+0x0f,
+0xfd,
+0x50,
+0x03,
+0xb0,
+0xdf,
+0x8c,
+0xf9,
+0x3c,
+0xf4,
+0x43,
+0x0e,
+0xc0,
+0xfd,
+0x32,
+0xe5,
+0xf3,
+0xd0,
+0x0f,
+0x03,
+0x00,
+0x03,
+0x25,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0xff,
+0xff,
+0x00,
+0xfd,
+0xbb,
+0x14,
+0xf2,
+0xc3,
+0x2f,
+0xf8,
+0x13,
+0xcc,
+0x7f,
+0x0c,
+0xb8,
+0x0e,
+0x74,
+0xf5,
+0x03,
+0xf0,
+0xf8,
+0x33,
+0x03,
+0x1c,
+0x2b,
+0xd7,
+0x00,
+0x00,
+0xeb,
+0xe5,
+0x1f,
+0x80,
+0xc0,
+0x1f,
+0x1b,
+0xe0,
+0x9e,
+0x9b,
+0x7f,
+0x00,
+0x03,
+0x7f,
+0x6c,
+0x80,
+0xf8,
+0x7d,
+0xfe,
+0x01,
+0x0e,
+0xfc,
+0xb1,
+0x01,
+0x80,
+0xd7,
+0x62,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x38,
+0x00,
+0x43,
+0xdf,
+0xa0,
+0xd7,
+0x83,
+0x3f,
+0xe3,
+0x00,
+0x3c,
+0x75,
+0x80,
+0x5e,
+0x07,
+0xfe,
+0xff,
+0xef,
+0x7a,
+0xc1,
+0x73,
+0xfd,
+0x3c,
+0xfc,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xff,
+0xff,
+0x17,
+0xff,
+0xdf,
+0xeb,
+0xff,
+0xe1,
+0xb7,
+0xf5,
+0x00,
+0xfe,
+0x7f,
+0x6e,
+0x80,
+0x07,
+0xff,
+0xff,
+0x6f,
+0x11,
+0xfe,
+0xb5,
+0xaa,
+0x1f,
+0xff,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xff,
+0x7f,
+0x8b,
+0xf0,
+0xaf,
+0x75,
+0xff,
+0xff,
+0xdb,
+0x7f,
+0x2f,
+0xc3,
+0xbf,
+0x57,
+0xf5,
+0x0c,
+0xf1,
+0xff,
+0xb7,
+0x0f,
+0xff,
+0x00,
+0x3f,
+0x70,
+0xa2,
+0x35,
+0x00,
+0xe0,
+0xff,
+0x1b,
+0x0f,
+0x79,
+0xe8,
+0xd7,
+0xf2,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x2f,
+0x3a,
+0xc1,
+0xff,
+0xfd,
+0x3c,
+0xfc,
+0x6b,
+0x1e,
+0xc0,
+0x7f,
+0xb6,
+0x0c,
+0xf0,
+0xe0,
+0x4f,
+0xff,
+0x2f,
+0x43,
+0xfc,
+0xc0,
+0xcf,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xff,
+0x67,
+0x81,
+0xff,
+0xb1,
+0xee,
+0x1f,
+0xfe,
+0x1b,
+0x0f,
+0xe0,
+0xff,
+0xf7,
+0xf6,
+0x7a,
+0xf0,
+0xef,
+0xbf,
+0x96,
+0xff,
+0x1d,
+0xab,
+0xfe,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x6f,
+0xff,
+0xb1,
+0xfc,
+0x7f,
+0x58,
+0x59,
+0x0e,
+0xc0,
+0xff,
+0x2f,
+0x72,
+0xfc,
+0x03,
+0xfc,
+0x3c,
+0x7f,
+0x31,
+0x1e,
+0xc0,
+0xe0,
+0x4f,
+0xec,
+0x75,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xd7,
+0xf8,
+0xff,
+0x45,
+0x87,
+0x7f,
+0xa2,
+0x9f,
+0x19,
+0xff,
+0xff,
+0x67,
+0x1f,
+0xfe,
+0xb1,
+0xae,
+0x65,
+0xfc,
+0xff,
+0xff,
+0x7e,
+0xf8,
+0xf7,
+0xba,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0xdb,
+0x7a,
+0xc0,
+0x83,
+0x3f,
+0x31,
+0x01,
+0xfc,
+0x67,
+0xff,
+0xf4,
+0x0f,
+0xdf,
+0x5a,
+0x4f,
+0xf0,
+0xff,
+0xff,
+0xd8,
+0x3a,
+0xfc,
+0x32,
+0x00,
+0xc0,
+0x01,
+0x48,
+0x7f,
+0x97,
+0xf1,
+0xff,
+0xe0,
+0xac,
+0xe1,
+0x1f,
+0xff,
+0x5a,
+0xfe,
+0xbb,
+0xad,
+0xff,
+0x87,
+0x7f,
+0xfe,
+0x03,
+0xf8,
+0xff,
+0xb5,
+0xe8,
+0x1f,
+0xbe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x5f,
+0xcb,
+0x7f,
+0xab,
+0x75,
+0xe5,
+0xf0,
+0xdb,
+0x7a,
+0x00,
+0xff,
+0x3f,
+0x91,
+0xcf,
+0x43,
+0x0f,
+0xf8,
+0x13,
+0x90,
+0xbf,
+0x0c,
+0xb6,
+0x0e,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x7f,
+0x5b,
+0x0f,
+0xe0,
+0xf0,
+0x27,
+0x06,
+0x78,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x5b,
+0x8b,
+0xfe,
+0xca,
+0x07,
+0xfc,
+0x09,
+0x87,
+0x5f,
+0x06,
+0x5b,
+0x20,
+0x00,
+0x09,
+0x00,
+0xb0,
+0xc0,
+0x8d,
+0x03,
+0x3c,
+0xf8,
+0x03,
+0x02,
+0x80,
+0xf8,
+0xff,
+0x3f,
+0xfc,
+0xf0,
+0xce,
+0x85,
+0x04,
+0x3a,
+0x0e,
+0xfe,
+0xae,
+0xc3,
+0x1f,
+0x03,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x77,
+0x01,
+0x00,
+0xf8,
+0xee,
+0x1f,
+0xfe,
+0xb9,
+0x3f,
+0x65,
+0x40,
+0xe0,
+0xf8,
+0x79,
+0xf8,
+0x07,
+0xff,
+0x94,
+0xf3,
+0xff,
+0xea,
+0xfa,
+0xe0,
+0x5f,
+0x06,
+0x00,
+0x7a,
+0xbc,
+0xff,
+0xa5,
+0xfe,
+0x77,
+0x52,
+0x3f,
+0x0f,
+0xff,
+0xff,
+0xef,
+0xf2,
+0xfe,
+0x03,
+0xfc,
+0x3c,
+0xfc,
+0x77,
+0x1f,
+0xe0,
+0x7f,
+0x2f,
+0xe5,
+0xf3,
+0xd0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
new file mode 100755
index 0000000000..ce01eabdc9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c5 for 1080 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVD
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c5 for 1080 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5 =
+{{
+0x10,
+0x20,
+0x05,
+0x03,
+0xc5,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0x83,
+0xc5,
+0x93,
+0xcd,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x80,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x89,
+0x0b,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0x51,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xf8,
+0xff,
+0x2e,
+0xc3,
+0x3f,
+0xd7,
+0xfd,
+0xac,
+0xff,
+0xff,
+0xbb,
+0x0f,
+0xff,
+0x5c,
+0xd7,
+0xf3,
+0xdf,
+0xfd,
+0xc7,
+0x3f,
+0xfc,
+0xe3,
+0xf5,
+0x00,
+0x1d,
+0xd5,
+0x00,
+0x00,
+0xfd,
+0xff,
+0x7f,
+0xfa,
+0xe1,
+0xd9,
+0xca,
+0x00,
+0x66,
+0xfa,
+0x71,
+0x80,
+0x07,
+0x7f,
+0x40,
+0x67,
+0xd9,
+0xff,
+0xff,
+0xde,
+0x1d,
+0x7e,
+0xb1,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x0e,
+0x40,
+0xbd,
+0x55,
+0xe0,
+0x73,
+0xd0,
+0x0f,
+0xff,
+0x00,
+0xe0,
+0xff,
+0x13,
+0xf2,
+0xc3,
+0xbb,
+0xff,
+0x8b,
+0xf8,
+0xff,
+0x44,
+0x59,
+0x0e,
+0x7f,
+0x34,
+0x00,
+0x10,
+0x59,
+0xfb,
+0x07,
+0xe0,
+0xfb,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0xfe,
+0x7f,
+0x94,
+0x9b,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xe8,
+0xff,
+0x8c,
+0x07,
+0xf0,
+0xf4,
+0x43,
+0xf9,
+0x3c,
+0x7e,
+0x33,
+0x0e,
+0xc0,
+0xd0,
+0x0f,
+0xe5,
+0xf3,
+0xf7,
+0xcb,
+0x38,
+0x00,
+0x43,
+0x3f,
+0x94,
+0xcf,
+0x0c,
+0x94,
+0x0c,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x03,
+0xf4,
+0xff,
+0xff,
+0xc8,
+0x0f,
+0xef,
+0x52,
+0x4f,
+0x30,
+0xbf,
+0xe0,
+0xe0,
+0x3a,
+0xfc,
+0x31,
+0x0f,
+0xc0,
+0xd3,
+0xd5,
+0x0c,
+0x70,
+0xe0,
+0xcf,
+0x03,
+0x00,
+0xac,
+0x5c,
+0x7f,
+0x00,
+0xae,
+0x97,
+0x6c,
+0x80,
+0x03,
+0x7f,
+0xfe,
+0x01,
+0x78,
+0x6e,
+0xb1,
+0x01,
+0x0e,
+0xfc,
+0xf9,
+0x07,
+0xe0,
+0xf7,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0x8b,
+0x01,
+0x80,
+0x5f,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x40,
+0xf9,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0x80,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
new file mode 100755
index 0000000000..ddd937ab66
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
@@ -0,0 +1,113 @@
+;/**
+; * @file
+; *
+; * AGESA Family 10h Revision D support routines.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU/F10
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    .LIST
+
+    .586P
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   P R E S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .MODEL flat
+    .CODE
+
+;======================================================================
+; F10RevDProbeFilterCritical:  Performs critical sequence for probe
+;                              filter initialization.
+;
+;   In:
+;       PciAddress      Full PCI address of the node to init
+;       PciRegister     Current value of F3x1D4
+;
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
+
+  mov    ecx, 0C001001Fh
+  rdmsr
+  push   eax
+  push   ecx
+  push   edx
+  or     dh, 40h
+  wrmsr
+
+  mov    eax, 810003D4h
+
+  mov    ecx, PciRegister
+  mov    edx, PciAddress
+  shr    edx, 4
+  and    dh, 0F8h
+  or     ah, dh
+
+  or     cl, 2
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  mov    dx, 0CF8h        ; Set Reg Config Space
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  out    dx, eax
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  mov    dl, 0FCh         ; Set DX to Pci Config Data
+  mov    eax, ecx         ;Set config Reg data
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  out    dx, eax          ; move data to return position
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  pop    edx
+  pop    ecx
+  pop    eax
+  wrmsr
+  ret
+
+F10RevDProbeFilterCritical ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
new file mode 100755
index 0000000000..2804d29153
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
@@ -0,0 +1,127 @@
+;/**
+; * @file
+; *
+; * AGESA Family 10h Revision D support routines.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU/F10
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    .LIST
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   P R E S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .CODE
+
+;======================================================================
+; F10RevDProbeFilterCritical:  Performs critical sequence for probe
+;                              filter initialization.
+;
+;   In:
+;       PciAddress      Full PCI address of the node to init
+;       PciRegister     Current value of F3x1D4
+;
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC F10RevDProbeFilterCritical
+F10RevDProbeFilterCritical PROC
+
+  push   rax
+  push   rcx
+  push   rdx
+  push   rsi
+  push   rdi
+
+  mov    esi, ecx
+  mov    edi, edx
+
+  mov    ecx, 0C001001Fh
+  rdmsr
+  push   rax
+  push   rcx
+  push   rdx
+  or     dh, 40h
+  wrmsr
+
+  mov    eax, 810003D4h
+
+  mov    ecx, edi
+  mov    edx, esi
+
+  shr    edx, 4
+  and    dh, 0F8h
+  or     ah, dh
+
+  or     cl, 2
+  mfence
+
+  mov    dx, 0CF8h        ; Set Reg Config Space
+  mfence
+
+  out    dx, eax
+  mfence
+
+  mov    dl, 0FCh         ; Set DX to Pci Config Data
+  mov    eax, ecx         ;Set config Reg data
+  mfence
+
+  out    dx, eax          ; move data to return position
+  mfence
+
+  pop    rdx
+  pop    rcx
+  pop    rax
+  wrmsr
+
+  pop    rdi
+  pop    rsi
+  pop    rdx
+  pop    rcx
+  pop    rax
+  ret
+
+F10RevDProbeFilterCritical ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
new file mode 100755
index 0000000000..538ebdaa29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
@@ -0,0 +1,454 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RevD HT Assist feature support functions.
+ *
+ * Provides the functions necessary to initialize the HT Assist feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "CommonReturns.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuLateInit.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuHtAssist.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * The family 10h background scrubber context structure.
+ *
+ * These fields need to be saved, modified, then restored
+ * per die as part of HT Assist initialization.
+ */
+typedef struct {
+  UINT32  DramScrub:5;               ///< DRAM scrub rate
+  UINT32  :3;                        ///< Reserved
+  UINT32  L3Scrub:5;                 ///< L3 scrub rate
+  UINT32  :3;                        ///< Reserved
+  UINT32  Redirect:1;                ///< DRAM scrubber redirect enable
+  UINT32  :15;                       ///< Reserved
+} F10_SCRUB_CONTEXT;
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU supports HT Assist.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsHtAssistSupported (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       PciRegister;
+  BOOLEAN      IsSupported;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  IsSupported = FALSE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NB_CAPS_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if (((NB_CAPS_REGISTER *) &PciRegister)->L3Capable == 1) {
+        IsSupported = TRUE;
+      }
+      break;
+    }
+  }
+  return IsSupported;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the Probe filter feature.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HtAssistInit (
+  IN       HT_ASSIST_FAMILY_SERVICES  *HtAssistServices,
+  IN       UINT32  Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                     Module;
+  UINT32                     PciRegister;
+  PCI_ADDR                   PciAddress;
+  AGESA_STATUS               IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = L3_CACHE_PARAM_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      } while (((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit != 0);
+
+      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFMode = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+      F10RevDProbeFilterCritical (PciAddress, PciRegister);
+
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      } while (((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFInitDone != 1);
+      IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Save the current settings of the scrubbers, and disabled them.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10GetL3ScrubCtrl (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       ScrubCtrl;
+  UINT32       ScrubAddr;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+
+      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
+
+      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
+
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
+        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
+        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
+        ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
+
+      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
+      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
+      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Restore the initial settings for the scrubbers.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10SetL3ScrubCtrl (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+
+      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((SCRUB_RATE_CTRL_REGISTER *) &PciRegister)->DramScrub =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
+      ((SCRUB_RATE_CTRL_REGISTER *) &PciRegister)->L3Scrub =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &PciRegister)->ScrubReDirEn =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set MSR bits required for HT Assist on each core.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HookDisableCache (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  MsrRegister;
+
+  LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader);
+  MsrRegister |= BIT42;
+  LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Hook before the probe filter initialization sequence.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HookBeforeInit (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32          Module;
+  UINT32          PciRegister;
+  UINT32          PfCtrlRegister;
+  PCI_ADDR        PciAddress;
+  CPU_LOGICAL_ID  LogicalId;
+  AGESA_STATUS    IgnoredStatus;
+  UINT32          PackageType;
+
+  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
+  PackageType = LibAmdGetPackageType (StdHeader);
+
+  PciRegister = 0;
+  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFWayNum = 2;
+  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFSubCacheEn = 15;
+  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFLoIndexHashEn = 1;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
+      ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFPreferredSORepl =
+        ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+      // Assumption: all socket use the same CPU package.
+      if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
+        // Apply erratum #384
+        // Set F2x11C[13:12] = 11b
+        PciAddress.Address.Function = FUNC_2;
+        PciAddress.Address.Register = 0x11C;
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+        PciRegister |= 0x3000;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU is running in the optimal configuration.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is running sub-optimally.
+ * @retval       FALSE              HT Assist is running optimally.
+ *
+ */
+STATIC BOOLEAN
+F10IsNonOptimalConfig (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN      IsNonOptimal;
+  BOOLEAN      IsMemoryPresent;
+  UINT32       Module;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  IsNonOptimal = FALSE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      IsMemoryPresent = FALSE;
+      PciAddress.Address.Function = FUNC_2;
+      PciAddress.Address.Register = DRAM_CFG_HI_REG0;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
+        IsMemoryPresent = TRUE;
+        if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
+          IsNonOptimal = TRUE;
+          break;
+        }
+      }
+
+      PciAddress.Address.Register = DRAM_CFG_HI_REG1;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
+        IsMemoryPresent = TRUE;
+        if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
+          IsNonOptimal = TRUE;
+          break;
+        }
+      }
+      if (!IsMemoryPresent) {
+        IsNonOptimal = TRUE;
+        break;
+      }
+    }
+  }
+  return IsNonOptimal;
+}
+
+
+CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist =
+{
+  0,
+  F10IsHtAssistSupported,
+  F10HtAssistInit,
+  F10GetL3ScrubCtrl,
+  F10SetL3ScrubCtrl,
+  F10HookBeforeInit,
+  (PF_HT_ASSIST_AFTER_INIT) CommonVoid,
+  F10HookDisableCache,
+  (PF_HT_ASSIST_ENABLE_CACHE) CommonVoid,
+  F10IsNonOptimalConfig
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
new file mode 100755
index 0000000000..aa2c738ea1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -0,0 +1,277 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RevD Message-Based C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the message-based C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 46667 $   @e \$Date: 2011-02-08 14:06:57 -0700 (Tue, 08 Feb 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuMsgBasedC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeMsgBasedC1eOnCore (
+  IN       VOID              *BmStsAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+STATIC
+IsDramScrubberEnabled (
+  IN       PCI_ADDR PciAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should message-based C1e be enabled
+ *
+ * @param[in]    MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsMsgBasedC1eSupported (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
+  return ((BOOLEAN) ((LogicalId.Revision & AMD_F10_GT_D0) != 0));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Core 0 task to enable message-based C1e on a family 10h CPU.
+ *
+ * @param[in]    MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
+ * @param[in]    EntryPoint          Timepoint designator.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeMsgBasedC1e (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       AndMask;
+  UINT32       Core;
+  UINT32       Module;
+  UINT32       OrMask;
+  UINT32       PciRegister;
+  UINT32       Socket;
+  AP_TASK      TaskPtr;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    // Note that this core 0 does NOT have the ability to launch
+    // any of its cores.  Attempting to do so could lead to a system
+    // hang.
+
+    // Set F3xA0[IdleExitEn] = 1
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    AndMask = 0xFFFFFFFF;
+    OrMask = 0;
+    ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
+
+    // BIOS should set F3x1B8[5]
+    PciAddress.Address.Register = 0x1B8;
+    OrMask = 0x00000020;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x1B8
+
+    // Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
+    PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
+    OrMask = 0;
+    ((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
+
+    // Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
+    // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
+    OrMask = 0;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
+
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+
+    for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
+        PciAddress.Address.Function = FUNC_3;
+        PciAddress.Address.Register = CPTC0_REG;
+        if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
+          ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
+        } else {
+          ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
+        }
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+        PciRegister &= AndMask;
+        PciRegister |= OrMask;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      }
+    }
+
+  } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
+    // At early, this core 0 can launch its subordinate cores.
+    TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 1;
+    TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable message-based C1e on a family 10h core.
+ *
+ * @param[in]    BmStsAddress       System I/O address of the bus master status bit.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeMsgBasedC1eOnCore (
+  IN       VOID              *BmStsAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
+  LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader);
+  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1;
+  ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0;
+  ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0;
+  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
+  LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader);
+
+  // Set MSRC001_0015[HltXSpCycEn] = 1
+  LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader);
+  MsrRegister |= BIT12;
+  LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the DRAM background scrubbers are enabled or not.
+ *
+ * @param[in]    PciAddress         Address of F10 socket/module to check.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Memory scrubbers are enabled on the current node.
+ * @retval       FALSE              Memory scrubbers are disabled on the current node.
+ */
+BOOLEAN
+STATIC
+IsDramScrubberEnabled (
+  IN       PCI_ADDR PciAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PciRegister;
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = 0x58;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  return ((BOOLEAN) ((PciRegister & 0x1F) != 0));
+}
+
+
+CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e =
+{
+  0,
+  F10IsMsgBasedC1eSupported,
+  F10InitializeMsgBasedC1e
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
new file mode 100755
index 0000000000..fe1b2d6ad5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -0,0 +1,372 @@
+/**
+ * @file
+ *
+ * AMD Family_10 revision Dx specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h rev D.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "GeneralServices.h"
+#include "cpuEarlyInit.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+F10CommonRevDGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+  OUT      BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+BOOLEAN
+F10CommonRevDGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+  OUT      UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+AGESA_STATUS
+F10CommonRevDGetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+  OUT      UINT32 *FrequencyInMHz,
+  OUT      UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+UINT8
+F10CommonRevDGetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on a revision D processor.
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ */
+STATIC VOID
+F10CommonRevDSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    TempVar32_a;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS AgesaStatus;
+
+  switch (*LeveledCores) {
+  case 1:
+    CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    break;
+  case 2:
+    CoreDisableBits = DOWNCORE_MASK_DUAL;
+    break;
+  case 3:
+    CoreDisableBits = DOWNCORE_MASK_TRI;
+    break;
+  case 4:
+    CoreDisableBits = DOWNCORE_MASK_FOUR;
+    break;
+  case 5:
+    CoreDisableBits = DOWNCORE_MASK_FIVE;
+    break;
+  default:
+    CoreDisableBits = 0;
+    break;
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
+      if (TempVar32_a == 0) {
+        CoreDisableBits &= 0x1;
+      } else if (TempVar32_a == 1) {
+        CoreDisableBits &= 0x3;
+      } else if (TempVar32_a == 2) {
+        CoreDisableBits &= 0x7;
+      } else if (TempVar32_a == 3) {
+        CoreDisableBits &= 0x0F;
+      } else if (TempVar32_a == 4) {
+        CoreDisableBits &= 0x1F;
+      } else if (TempVar32_a == 5) {
+        CoreDisableBits &= 0x3F;
+      }
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a |= CoreDisableBits;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+    }
+  }
+
+  return;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
+{
+  0,
+  F10CommonRevDSetDownCoreRegister
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current on a revision D processor.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F10CommonRevDGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       IddDiv;
+  UINT32       CmpCap;
+  UINT32       MultiNodeCpu;
+  UINT32       NbCaps;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Ignored;
+  UINT32       MsrAddress;
+  UINT64       PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
+  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // F3xE8
+
+    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
+    case 0:
+      IddDiv = 1000;
+      break;
+    case 1:
+      IddDiv = 100;
+      break;
+    case 2:
+      IddDiv = 10;
+      break;
+    default:  // IddDiv = 3 is reserved. Use 10
+      IddDiv = 10;
+      break;
+    }
+    MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->MultiNodeCpu + 1);
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapHi << 2);
+    CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapLo);
+    CmpCap++;
+    *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F10CommonRevDGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NbVidUpdateAll = FALSE;
+  return FALSE;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[out]  VoltageInuV              Northbridge voltage in uV.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS     Always succeeds.
+ */
+AGESA_STATUS
+F10CommonRevDGetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PciRegister;
+  UINT32 NbFid;
+  UINT64 MsrRegister;
+
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CPTC0_REG;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
+  NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
+  *FrequencyInMHz = ((NbFid + 4) * 200);
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get number of processor cores to be used in determining the brand string.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of cores to be used in brand string calculation.
+ */
+UINT8
+F10CommonRevDGetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       CmpCap;
+  UINT32       CmpCapOnNode;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Core;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  CmpCap = 0;
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NB_CAPS_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      CmpCapOnNode = (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2);
+      CmpCapOnNode |= (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
+      CmpCapOnNode++;
+      CmpCap += CmpCapOnNode;
+    }
+  }
+  return ((UINT8) CmpCap);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
new file mode 100755
index 0000000000..6a2f04f5ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10HyMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
+{
+  0x1080, 0x1080,
+  0x1081, 0x1081,
+  0x1091, 0x1081
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  HyEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10HyMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
new file mode 100755
index 0000000000..4b50153636
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
@@ -0,0 +1,1290 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Ht Phy tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyHtPhyRegisters[] =
+{
+// 0x60:0x68
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL0_ALL,               //
+      0x60, 0x68,                           // Address
+      0x00000040,                           // regData
+      0x00000040},                           // regMask
+    }
+  },
+// 0x70:0x78
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL1_ALL,               //
+      0x70, 0x78,                           // Address
+      0x00000040,                           // regData
+      0x00000040},                           // regMask
+    }
+  },
+// 0xC0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL0_ALL,               //
+      0xC0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000},                           // regMask
+    }
+  },
+// 0xD0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL1_ALL,               //
+      0xD0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000},                           // regMask
+    }
+  },
+// 0xCF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF},                           // regMask
+    }
+  },
+// 0xDF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF},                           // regMask
+    }
+  },
+
+//
+// All the entries for XmtRdPtr 6
+//
+
+// 0xCF
+// For HT frequencies 1200-1600 and NB Freq 1600, 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1200-1600 and NB Freq 1600, 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3200 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3200 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Entries for XmtRdPtr 5
+//
+
+// 0xCF
+// For HT frequencies 1800-2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800-2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2000 - 2800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2000 - 2800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Entries for XmtRdPtr 4
+//
+
+// 0xCF
+// For HT frequencies 2800-3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2800-3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3000 - 3200 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3000 - 3200 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Entries for XmtRdPtr 3
+//
+
+// 0xCF
+// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Rev D0 fixups for Erratum 398.
+//
+
+// 0xCF
+// For HT frequencies 1800, 2200 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800, 2200 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2600, 3000 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600, 3000 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2200, 2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2200, 2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2200, 2600 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2200, 2600 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3000 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3000 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1800 and NB Freq 1600 for all links
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800 and NB Freq 1600 for all links
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000001A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000001A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Deemphasis Settings for D1 processors.
+//
+
+// For D1, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+
+// 0x520A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,                   //
+      0x520A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+// 0x530A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,                   //
+      0x530A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10HyHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10HyHtPhyRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
new file mode 100755
index 0000000000..ec31f2bf84
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
@@ -0,0 +1,138 @@
+/**
+ * @file
+ *
+ * Implements the workaround for erratum 419.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/RevD/HY
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
+extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
+
+CONST PF_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
+{
+  McaInitializationAtEarly,
+  SetRegistersFromTablesAtEarly,
+  LocalApicInitializationAtEarly,
+  LoadMicrocodePatchAtEarly,
+  SetBrandIdRegistersAtEarly,
+  NULL
+};
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly to return the steps
+ * appropriate for the executing Rev D core.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetF10HyEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+VOID
+GetF10HyEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  UINT32         ProcessorPackageType;
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+
+  // Check if this CPU is affected by erratum 419.
+  if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) {
+    // Return initialization steps such that the microcode patch is applied before
+    // brand string determination is performed.
+    *Table = F10HyC32D0EarlyInitOnCoreTable;
+  } else {
+    // No workaround is necessary.  Return the standard table.
+    GetCommonEarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
new file mode 100755
index 0000000000..4ff9ea5d0f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
@@ -0,0 +1,112 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10HyLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10HyLogicalIdAndRevArray[] =
+{
+  {
+    0x1080,
+    AMD_F10_HY_SCM_D0
+  },
+  {
+    0x1090,
+    AMD_F10_HY_MCM_D0
+  },
+  {
+    0x1081,
+    AMD_F10_HY_SCM_D1
+  },
+  {
+    0x1091,
+    AMD_F10_HY_MCM_D1
+  }
+};
+
+VOID
+GetF10HyLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10HyLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_HY;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
new file mode 100755
index 0000000000..9715ebc9e3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -0,0 +1,112 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+extern  CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[];
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10HyMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  OUT      CONST VOID **HyUcodePtr,
+  OUT      UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  HyUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10HyMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10HyMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
new file mode 100755
index 0000000000..2c441ca1f2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -0,0 +1,139 @@
+/**
+ * @file
+ *
+ * AMD Family_10 HY MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    { AMD_PF_ALL },                       // platformFeatures
+    {
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1)                              // NAND Mask
+    }
+    }
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// bit[21] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    { AMD_PF_ALL },                       // platformFeatures
+    {
+    {
+      MSR_BU_CFG,                           // MSR Address
+      (1 << 21),                            // OR Mask
+      (1 << 21),                            // NAND Mask
+    }
+    }
+  },
+
+// MSR_BU_CFG2 (0xC001102A)
+// bit[50] = 1
+// For GH rev C1 and later [RdMmExtCfgQwEn]=1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    { AMD_PF_ALL },                       // platformFeatures
+    {
+    {
+      MSR_BU_CFG2,                          // MSR Address
+      0x0004000000000000ull,                   // OR Mask
+      0x0004000000000000ull,                   // NAND Mask
+    }
+  }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
new file mode 100755
index 0000000000..c8fc912cdc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
@@ -0,0 +1,362 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 46786 $   @e \$Date: 2011-02-09 18:32:59 -0700 (Wed, 09 Feb 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyPciRegisters[] =
+{
+// F0x68 -
+  // BufRelPri for rev D
+  // bits[14:13]  BufRelPri = 1
+  // bit [25] CHtExtAddrEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68),   // Address
+      0x02002000,                           // regData
+      0x02006000,                           // regMask
+    }}
+  },
+  // F0x[E4,A4,C4,84] Link Control Register
+  // bit [15] Addr64bitEn = 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},
+    {{
+      HT_HOST_FEAT_NONCOHERENT,
+      0x4,
+      0x00008000,
+      0x00008000,
+    }}
+  },
+// F0x150 - Link Global Retry Control Register
+// bit[18:16] TotalRetryAttempts = 7
+// bit[13] HtRetryCrcDatInsDynEn = 1
+// bit[12]HtRetryCrcCmdPackDynEn = 1
+// bit[11:9] HtRetryCrcDatIns = 0
+// bit[8] HtRetryCrcCmdPack = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
+      0x00073100,                           // regData
+      0x00073F00,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[5:0] T0Time = 0x26
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10_HY,                   // CpuFamily
+      AMD_F10_D1                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C026,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[9] RXCalEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10_HY,                   // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000200,                           // regData
+      0x00000200,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 01b (PHY_OFF)
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_Dx                            // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }}
+  },
+// F0x[18C:170] - Link Extended Control Register - All connected links.
+// bit[8] LS2En = 1
+  {
+    HtLinkPciRegister,
+    {
+      AMD_FAMILY_10_HY,                     // CpuFamily
+      AMD_F10_D1                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platform Features
+    {{
+      HT_HOST_FEATURES_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F2x1B0 - Extended Memory Controller Configuration Low
+// bits[10:8], CohPrefPrbLmt = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_Dx                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
+      0x00000000,                           // regData
+      0x00000700,                           // regMask
+    }}
+  },
+// Function 3 - Misc. Control
+// F3x158 - Link to XCS Token Count
+// bits[3:0] LnkToXcsDRToken = 3
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    {AMD_PF_UMA},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,                           // regData
+      0x0000000F,                           // regMask
+    }}
+  },
+
+// F3x80 - ACPI Power State Control
+// ACPI State C2
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 1
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 5
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_Ax                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000A681,                           // regData
+      0x0000FFFF,                           // regMask
+    }}
+  },
+
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_D0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000E600,                           // regData
+      0x0000FF00,                           // regMask
+    }}
+  },
+
+// F3xA0 - Power Control Miscellaneous
+// bit[14] BpPinsTriEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_D0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00004000,                           // regData
+      0x00004000,                           // regMask
+    }}
+  },
+
+// F3x188 - NB Extended Configuration Low Register
+// Must be set by BIOS
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x08000000,                           // regData
+      0x08000000,                           // regMask
+    }}
+  },
+
+// F3x1B8 - L3 Control
+// Must be set by BIOS
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
+      0x00040000,                           // regData
+      0x00040000,                           // regMask
+    }}
+  },
+
+// F3x1B8 - L3 Control
+// Must be set by BIOS
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
+      0x00800000,                           // regData
+      0x00800000,                           // regMask
+    }}
+  },
+
+// F3x1D4 - Probe Filter Control Register
+// bits[21:20] PFPreferedSORepl = 2
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1D4), // Address
+      0x00200000,                           // regData
+      0x00300000,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10HyPciRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
new file mode 100755
index 0000000000..0c21de5420
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
@@ -0,0 +1,343 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 5893 $   @e \$Date: 2008-04-23 08:37:29 -0700 (Wed, 23 Apr 2008) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCommonF10Utilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/**
+ * Node ID MSR register fields.
+ * Provide the layout of fields in the Node ID MSR.
+ */
+typedef struct {
+  UINT64    NodeId:3;                 ///< The core is on the node with this node id.
+  UINT64    NodesPerProcessor:3;      ///< The number of Nodes in this processor.
+  UINT64    HeapIndex:6;              ///< The AP core heap index.
+  UINT64    :(63 - 11);               ///< Reserved.
+} NODE_ID_MSR_FIELDS;
+
+/// Node ID MSR.
+typedef union {
+  NODE_ID_MSR_FIELDS   Fields;        ///< Access the register as individual fields
+  UINT64               Value;         ///< Access the register value.
+} NODE_ID_MSR;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+F10SetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32                 Socket,
+  IN       UINT32                 Module,
+  IN       UINT32                 ApCoreNumber,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+UINT32
+F10GetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+VOID
+F10TransferApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
+ *
+ *  This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Handle of Header for calling lib functions and services.
+ *  @param[in]  Request                  Indicate warm reset status
+ *
+ */
+VOID
+F10SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  PciData &= ~(HT_INIT_BIOS_RST_DET_0);
+  PciData = PciData | (Request->RequestBit << 5);
+
+  // bit[10,9] - indicate warm reset status and count
+  PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
+  PciData |= Request->StateBits << 9;
+
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
+ *
+ *  This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Config handle for library and services
+ *  @param[in]  Request                  Indicate warm reset status
+ *
+ */
+VOID
+F10GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
+  // bit[10,9] - indicate warm reset status and count
+  Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Use the Mailbox Register to get the Ap Mailbox info for the current core.
+ *
+ *  @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
+ *
+ *  Access the mailbox register used with this NB family.  This is valid until the
+ *  point that some init code initializes the mailbox register for its normal use.
+ *  The Machine Check Misc (Thresholding) register is available as both a PCI config
+ *  register and a MSR, so it can be used as a mailbox from HT to other functions.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    ApMailboxInfo           The AP Mailbox info
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F10GetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64 MailboxInfo;
+
+  LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader);
+  // Mailbox info is in bits 32 thru 43, 12 bits.
+  ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
+  LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader);
+  // Mailbox info is in bits 32 thru 43, 12 bits.
+  ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set the system AP core number in the AP's Mailbox.
+ *
+ *  @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}.
+ *
+ *  Access the mailbox register used with this NB family.  This is only intended to
+ *  run on the BSC at the time of initial AP launch.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     Socket                  The AP's socket
+ *  @param[in]     Module                  The AP's module
+ *  @param[in]     ApCoreNumber            The AP's unique core number
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F10SetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32                 Socket,
+  IN       UINT32                 Module,
+  IN       UINT32                 ApCoreNumber,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   PciRegister;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = 0x170;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  ((AP_MAIL_EXT_INFO *) &PciRegister)->Fields.HeapIndex = ApCoreNumber;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get this AP's system core number from hardware.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
+ *
+ *  Returns the system core number from the scratch MSR, where
+ *  it was saved at heap initialization.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+UINT32
+F10GetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  NODE_ID_MSR NodeIdMsr;
+
+  LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader);
+  return (UINT32) NodeIdMsr.Fields.HeapIndex;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Move the AP's core number from the mailbox to hardware.
+ *
+ *  @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}.
+ *
+ *  Transfers this AP's system core number from the mailbox to
+ *  the NodeId MSR and initializes the other NodeId fields.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F10TransferApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_MAILBOXES Mailboxes;
+  NODE_ID_MSR NodeIdMsr;
+  UINT64 ExtFeatures;
+
+  NodeIdMsr.Value = 0;
+  FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader);
+  NodeIdMsr.Fields.HeapIndex = Mailboxes.ApMailExtInfo.Fields.HeapIndex;
+  NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node;
+  NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType;
+  LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader);
+
+  // Indicate that the NodeId MSR is supported.
+  LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
+  ExtFeatures = (ExtFeatures | BIT51);
+  LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Return a number zero or one, based on the Core ID position in the initial APIC Id.
+ *
+ * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @retval        CoreIdPositionZero      Core Id is not low
+ * @retval        CoreIdPositionOne       Core Id is low
+ */
+CORE_ID_POSITION
+F10CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64 InitApicIdCpuIdLo;
+
+  //  Check bit_54 [InitApicIdCpuIdLo] to find core id position.
+  LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
+  InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
+  return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
new file mode 100755
index 0000000000..b135429ca9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
@@ -0,0 +1,98 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_COMMON_F10_UTILITES_H_
+#define _CPU_COMMON_F10_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10GetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+CORE_ID_POSITION
+F10CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F10SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+VOID
+F10GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+#endif  // _CPU_COMMON_F10_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
new file mode 100755
index 0000000000..7dbdf14c4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -0,0 +1,155 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10BrandIdString1 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString1Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+VOID
+GetF10BrandIdString2 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString2Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern CPU_BRAND_TABLE *F10BrandIdString1Tables[];
+extern CPU_BRAND_TABLE *F10BrandIdString2Tables[];
+extern CONST UINT8 F10BrandIdString1TableCount;
+extern CONST UINT8 F10BrandIdString2TableCount;
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate beginnings of the CPU brandstring.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BrandString1Ptr          Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BrandIdString1 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString1Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_BRAND_TABLE **TableEntryPtr;
+
+  TableEntryPtr = &F10BrandIdString1Tables[0];
+  *BrandString1Ptr = TableEntryPtr;
+  *NumberOfElements = F10BrandIdString1TableCount;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate endings of the CPU brandstring.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BrandString2Ptr          Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BrandIdString2 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString2Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_BRAND_TABLE **TableEntryPtr;
+
+  TableEntryPtr = &F10BrandIdString2Tables[0];
+  *BrandString2Ptr = TableEntryPtr;
+  *NumberOfElements = F10BrandIdString2TableCount;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
new file mode 100755
index 0000000000..73e9bb3263
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
@@ -0,0 +1,315 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket Am3.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+/*CHAR8 strEngSample[] = "AMD Engineering Sample";
+CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
+CHAR8 strUnknown[] = "AMD Processor model unknown";
+*/
+//AM3 NC 0
+CONST CHAR8 ROMDATA str_SC_AthlonLE[] =  "AMD Athlon(tm) Processor LE-";
+CONST CHAR8 ROMDATA str_SC_SempronLE[] = "AMD Sempron(tm) Processor LE-";
+CONST CHAR8 ROMDATA str_SC_Sempron_1[] = "AMD Sempron(tm) 1";
+CONST CHAR8 ROMDATA str_SC_Athlon_1[] = "AMD Athlon(tm) II 1";
+
+//AM3 NC 1
+CONST CHAR8 ROMDATA str_Athlon[] = "AMD Athlon(tm) ";
+CONST CHAR8 ROMDATA str_Athlon_II_XL_V[] = "AMD Athlon(tm) II XL V";
+CONST CHAR8 ROMDATA str_Athlon_II_XLT_V[] = "AMD Athlon(tm) II XLT V";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_4[] = "AMD Athlon(tm) II X2 4";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_B[] = "AMD Athlon(tm) II X2 B";
+CONST CHAR8 ROMDATA str_Athlon_II_X2[] = "AMD Athlon(tm) II X2 ";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_X2[] = "AMD Athlon(tm) II Neo X2 ";
+CONST CHAR8 ROMDATA str_Phenom_II_X2_5[] = "AMD Phenom(tm) II X2 5";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_5[] = "AMD Athlon(tm) II X2 5";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_3[] = "AMD Athlon(tm) II X2 3";
+CONST CHAR8 ROMDATA str_Phenom_II_X2[] = "AMD Phenom(tm) II X2 ";
+CONST CHAR8 ROMDATA str_Phenom_II_X2_B[] = "AMD Phenom(tm) II X2 B";
+CONST CHAR8 ROMDATA str_DC_Opteron13[] = "Dual-Core AMD Opteron(tm) Processor 13";
+
+//AM3 NC2
+CONST CHAR8 ROMDATA str_Phenom[] = "AMD Phenom(tm) ";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_5[] = "AMD Phenom(tm) II X3 5";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_4[] = "AMD Phenom(tm) II X3 4";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_B[] = "AMD Phenom(tm) II X3 B";
+CONST CHAR8 ROMDATA str_Phenom_II_X3[] = "AMD Phenom(tm) II X3 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_X3[] = "AMD Athlon(tm) II Neo X3 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_7[] = "AMD Phenom(tm) II X3 7";
+CONST CHAR8 ROMDATA str_Athlon_II_X3_B[] = "AMD Athlon(tm) II X3 B";
+CONST CHAR8 ROMDATA str_Athlon_II_X3[] = "AMD Athlon(tm) II X3 ";
+
+//AM3 NC 3
+CONST CHAR8 ROMDATA str_Phenom_FX[] =  "AMD Phenom(tm) FX-";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_9[] = "AMD Phenom(tm) II X4 9";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_8[] = "AMD Phenom(tm) II X4 8";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_7[] = "AMD Phenom(tm) II X4 7";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_6[] = "AMD Phenom(tm) II X4 6";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_B[] = "AMD Phenom(tm) II X4 B";
+CONST CHAR8 ROMDATA str_Phenom_II_X4[] = "AMD Phenom(tm) II X4 ";
+CONST CHAR8 ROMDATA str_Phenom_II_Neo_X4[] = "AMD Phenom(tm) II Neo X4 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6";
+CONST CHAR8 ROMDATA str_Athlon_II_X4_5[] = "AMD Athlon(tm) II X4 5";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_X4[] = "AMD Athlon(tm) II Neo X4 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X4_B[] = "AMD Athlon(tm) II X4 B";
+CONST CHAR8 ROMDATA str_Phenom_II__FX[] = "AMD Phenom(tm) II FX-";
+CONST CHAR8 ROMDATA str_Athlon_II_X4[] = "AMD Athlon(tm) II X4 ";
+CONST CHAR8 ROMDATA str_Phenom_II[] = "AMD Phenom(tm) II ";
+CONST CHAR8 ROMDATA str_Phenom_II_XLT_Q[] = "AMD Phenom(tm) II XLT Q";
+CONST CHAR8 ROMDATA str_QC_Opteron13[] = "Quad-Core AMD Opteron(tm) Processor 13";
+
+// String2
+CONST CHAR8 ROMDATA str2_SE_AM3[] = " SE";
+CONST CHAR8 ROMDATA str2_HE_AM3[] = " HE";
+CONST CHAR8 ROMDATA str2_EE_AM3[] = " EE";
+
+CONST CHAR8 ROMDATA str2_QCP_AM3[] = " Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_00[] = "00";
+CONST CHAR8 ROMDATA str2_10[] = "10";
+CONST CHAR8 ROMDATA str2_20[] = "20";
+CONST CHAR8 ROMDATA str2_30[] = "30";
+CONST CHAR8 ROMDATA str2_40[] = "40";
+CONST CHAR8 ROMDATA str2_50[] = "50";
+CONST CHAR8 ROMDATA str2_60[] = "60";
+CONST CHAR8 ROMDATA str2_70[] = "70";
+CONST CHAR8 ROMDATA str2_80[] = "80";
+CONST CHAR8 ROMDATA str2_90[] = "90";
+CONST CHAR8 ROMDATA str2_DC_00[] = "00 Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_00e[] = "00e Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_00B[] = "00B Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_50[] = "50 Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_50e[] = "50e Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_50B[] = "50B Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_Processor[] = " Processor";
+CONST CHAR8 ROMDATA str2_e_Processor[] = "e Processor";
+CONST CHAR8 ROMDATA str2_B_Processor[] = "B Processor";
+CONST CHAR8 ROMDATA str2_0e_Processor[] = "0e Processor";
+CONST CHAR8 ROMDATA str2_u_Processor[] = "u Processor";
+CONST CHAR8 ROMDATA str2_0_Processor[] = "0 Processor";
+CONST CHAR8 ROMDATA str2_L_Processor[] = "L Processor";
+CONST CHAR8 ROMDATA str2_C_Processor[] = "C Processor";
+CONST CHAR8 ROMDATA str2_TWKR_Black_Edition[] = " TWKR Black Edition";
+
+CONST CHAR8 ROMDATA str2_TC_00[] = "00 Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_00e[] = "00e Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_00B[] = "00B Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_50[] = "50 Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_50e[] = "50e Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_50B[] = "50B Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_00[] = "00 Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_00e[] = "00e Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_00B[] = "00B Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_50[] = "50 Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_50e[] = "50e Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_50B[] = "50B Quad-Core Processor";
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAm3[] =
+{
+  // AM3
+  {1, 0, 0, DR_SOCKET_AM3, str_SC_AthlonLE, sizeof (str_SC_AthlonLE)},
+  {1, 0, 1, DR_SOCKET_AM3, str_SC_SempronLE, sizeof (str_SC_SempronLE)},
+  {1, 0, 2, DR_SOCKET_AM3, str_SC_Sempron_1, sizeof (str_SC_Sempron_1)},
+  {1, 0, 3, DR_SOCKET_AM3, str_SC_Athlon_1, sizeof (str_SC_Athlon_1)},
+  {2, 0, 0, DR_SOCKET_AM3, str_DC_Opteron13, sizeof (str_DC_Opteron13)},
+  {2, 0, 1, DR_SOCKET_AM3, str_Athlon, sizeof (str_Athlon)},
+  {2, 0, 2, DR_SOCKET_AM3, str_Athlon_II_X2_4, sizeof (str_Athlon_II_X2_4)},
+  {2, 0, 3, DR_SOCKET_AM3, str_Athlon_II_X2_2, sizeof (str_Athlon_II_X2_2)},
+  {2, 0, 4, DR_SOCKET_AM3, str_Athlon_II_X2_B, sizeof (str_Athlon_II_X2_B)},
+  {2, 0, 5, DR_SOCKET_AM3, str_Athlon_II_X2, sizeof (str_Athlon_II_X2)},
+  {2, 0, 6, DR_SOCKET_AM3, str_Athlon_II_Neo_X2, sizeof (str_Athlon_II_Neo_X2)},
+  {2, 0, 7, DR_SOCKET_AM3, str_Phenom_II_X2_5, sizeof (str_Phenom_II_X2_5)},
+  {2, 0, 8, DR_SOCKET_AM3, str_Athlon_II_X2_5, sizeof (str_Athlon_II_X2_5)},
+  {2, 0, 9, DR_SOCKET_AM3, str_Athlon_II_X2_3, sizeof (str_Athlon_II_X2_3)},
+  {2, 0, 10, DR_SOCKET_AM3, str_Phenom_II_X2, sizeof (str_Phenom_II_X2)},
+  {2, 0, 11, DR_SOCKET_AM3, str_Phenom_II_X2_B, sizeof (str_Phenom_II_X2_B)},
+
+  {3, 0, 0, DR_SOCKET_AM3, str_Phenom, sizeof (str_Phenom)},
+  {3, 0, 1, DR_SOCKET_AM3, str_Phenom_II_X3_5, sizeof (str_Phenom_II_X3_5)},
+  {3, 0, 2, DR_SOCKET_AM3, str_Phenom_II_X3_4, sizeof (str_Phenom_II_X3_4)},
+  {3, 0, 3, DR_SOCKET_AM3, str_Phenom_II_X3_B, sizeof (str_Phenom_II_X3_B)},
+  {3, 0, 4, DR_SOCKET_AM3, str_Phenom_II_X3, sizeof (str_Phenom_II_X3)},
+  {3, 0, 5, DR_SOCKET_AM3, str_Athlon_II_X3_3, sizeof (str_Athlon_II_X3_3)},
+  {3, 0, 6, DR_SOCKET_AM3, str_Athlon_II_Neo_X3, sizeof (str_Athlon_II_Neo_X3)},
+  {3, 0, 7, DR_SOCKET_AM3, str_Athlon_II_X3_4, sizeof (str_Athlon_II_X3_4)},
+  {3, 0, 8, DR_SOCKET_AM3, str_Phenom_II_X3_7, sizeof (str_Phenom_II_X3_7)},
+  {3, 0, 9, DR_SOCKET_AM3, str_Athlon_II_X3_B, sizeof (str_Athlon_II_X3_B)},
+  {3, 0, 10, DR_SOCKET_AM3, str_Athlon_II_X3, sizeof (str_Athlon_II_X3)},
+
+  {4, 0, 0, DR_SOCKET_AM3, str_QC_Opteron13, sizeof (str_QC_Opteron13)},
+  {4, 0, 1, DR_SOCKET_AM3, str_Phenom_FX, sizeof (str_Phenom_FX)},
+  {4, 0, 2, DR_SOCKET_AM3, str_Phenom, sizeof (str_Phenom)},
+  {4, 0, 3, DR_SOCKET_AM3, str_Phenom_II_X4_9, sizeof (str_Phenom_II_X4_9)},
+  {4, 0, 4, DR_SOCKET_AM3, str_Phenom_II_X4_8, sizeof (str_Phenom_II_X4_8)},
+  {4, 0, 5, DR_SOCKET_AM3, str_Phenom_II_X4_7, sizeof (str_Phenom_II_X4_7)},
+  {4, 0, 6, DR_SOCKET_AM3, str_Phenom_II_X4_6, sizeof (str_Phenom_II_X4_6)},
+  {4, 0, 7, DR_SOCKET_AM3, str_Phenom_II_X4_B, sizeof (str_Phenom_II_X4_B)},
+  {4, 0, 8, DR_SOCKET_AM3, str_Phenom_II_X4, sizeof (str_Phenom_II_X4)},
+  {4, 0, 9, DR_SOCKET_AM3, str_Phenom_II_Neo_X4, sizeof (str_Phenom_II_Neo_X4)},
+  {4, 0, 10, DR_SOCKET_AM3, str_Athlon_II_X4_6, sizeof (str_Athlon_II_X4_6)},
+  {4, 0, 11, DR_SOCKET_AM3, str_Athlon_II_X4_5, sizeof (str_Athlon_II_X4_5)},
+  {4, 0, 12, DR_SOCKET_AM3, str_Athlon_II_Neo_X4, sizeof (str_Athlon_II_Neo_X4)},
+  {4, 0, 13, DR_SOCKET_AM3, str_Athlon_II_X4_B, sizeof (str_Athlon_II_X4_B)},
+  {4, 0, 14, DR_SOCKET_AM3, str_Phenom_II__FX, sizeof (str_Phenom_II__FX)},
+  {4, 0, 15, DR_SOCKET_AM3, str_Athlon_II_X4, sizeof (str_Athlon_II_X4)},
+  {2, 1, 1, DR_SOCKET_AM3, str_Athlon_II_XLT_V, sizeof (str_Athlon_II_XLT_V)},
+  {2, 1, 2, DR_SOCKET_AM3, str_Athlon_II_XL_V, sizeof (str_Athlon_II_XL_V)},
+  {4, 1, 0, DR_SOCKET_AM3, str_Phenom_II, sizeof (str_Phenom_II)},
+  {4, 1, 1, DR_SOCKET_AM3, str_Phenom_II_XLT_Q, sizeof (str_Phenom_II_XLT_Q)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAm3[] =
+{
+  // AM3
+  {1, 0, 0x00, DR_SOCKET_AM3, str2_00, sizeof (str2_00)},
+  {1, 0, 0x01, DR_SOCKET_AM3, str2_10, sizeof (str2_10)},
+  {1, 0, 0x02, DR_SOCKET_AM3, str2_20, sizeof (str2_20)},
+  {1, 0, 0x03, DR_SOCKET_AM3, str2_30, sizeof (str2_30)},
+  {1, 0, 0x04, DR_SOCKET_AM3, str2_40, sizeof (str2_40)},
+  {1, 0, 0x05, DR_SOCKET_AM3, str2_50, sizeof (str2_50)},
+  {1, 0, 0x06, DR_SOCKET_AM3, str2_60, sizeof (str2_60)},
+  {1, 0, 0x07, DR_SOCKET_AM3, str2_70, sizeof (str2_70)},
+  {1, 0, 0x08, DR_SOCKET_AM3, str2_80, sizeof (str2_80)},
+  {1, 0, 0x09, DR_SOCKET_AM3, str2_90, sizeof (str2_90)},
+  {1, 0, 0x0A, DR_SOCKET_AM3, str2_Processor, sizeof (str2_Processor)},
+  {1, 0, 0x0B, DR_SOCKET_AM3, str2_u_Processor, sizeof (str2_u_Processor)},
+  {1, 0, 0x0F, DR_SOCKET_AM3, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x00, DR_SOCKET_AM3, str2_DC_00, sizeof (str2_DC_00)},
+  {2, 0, 0x01, DR_SOCKET_AM3, str2_DC_00e,sizeof (str2_DC_00e)},
+  {2, 0, 0x02, DR_SOCKET_AM3, str2_DC_00B,sizeof (str2_DC_00B)},
+  {2, 0, 0x03, DR_SOCKET_AM3, str2_DC_50, sizeof (str2_DC_50)},
+  {2, 0, 0x04, DR_SOCKET_AM3, str2_DC_50e,sizeof (str2_DC_50e)},
+  {2, 0, 0x05, DR_SOCKET_AM3, str2_DC_50B,sizeof (str2_DC_50B)},
+  {2, 0, 0x06, DR_SOCKET_AM3, str2_Processor,sizeof (str2_Processor)},
+  {2, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor,sizeof (str2_e_Processor)},
+  {2, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor,sizeof (str2_B_Processor)},
+  {2, 0, 0x09, DR_SOCKET_AM3, str2_0_Processor,sizeof (str2_0_Processor)},
+  {2, 0, 0x0A, DR_SOCKET_AM3, str2_0e_Processor,sizeof (str2_0e_Processor)},
+  {2, 0, 0x0B, DR_SOCKET_AM3, str2_u_Processor,sizeof (str2_u_Processor)},
+  {2, 0, 0x0F, DR_SOCKET_AM3, 0, 0},    // Size 0 for no suffix
+  {3, 0, 0x00, DR_SOCKET_AM3, str2_TC_00, sizeof (str2_TC_00)},
+  {3, 0, 0x01, DR_SOCKET_AM3, str2_TC_00e,sizeof (str2_TC_00e)},
+  {3, 0, 0x02, DR_SOCKET_AM3, str2_TC_00B,sizeof (str2_TC_00B)},
+  {3, 0, 0x03, DR_SOCKET_AM3, str2_TC_50, sizeof (str2_TC_50)},
+  {3, 0, 0x04, DR_SOCKET_AM3, str2_TC_50e,sizeof (str2_TC_50e)},
+  {3, 0, 0x05, DR_SOCKET_AM3, str2_TC_50B,sizeof (str2_TC_50B)},
+  {3, 0, 0x06, DR_SOCKET_AM3, str2_Processor,sizeof (str2_Processor)},
+  {3, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor,sizeof (str2_e_Processor)},
+  {3, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor,sizeof (str2_B_Processor)},
+  {3, 0, 0x09, DR_SOCKET_AM3, str2_0e_Processor,sizeof (str2_0e_Processor)},
+  {3, 0, 0x0A, DR_SOCKET_AM3, str2_0_Processor,sizeof (str2_0_Processor)},
+  {3, 0, 0x0F, DR_SOCKET_AM3, 0, 0},    //Size 0 for no suffix
+  {4, 0, 0x00, DR_SOCKET_AM3, str2_QC_00, sizeof (str2_QC_00)},
+  {4, 0, 0x01, DR_SOCKET_AM3, str2_QC_00e,sizeof (str2_QC_00e)},
+  {4, 0, 0x02, DR_SOCKET_AM3, str2_QC_00B,sizeof (str2_QC_00B)},
+  {4, 0, 0x03, DR_SOCKET_AM3, str2_QC_50, sizeof (str2_QC_50)},
+  {4, 0, 0x04, DR_SOCKET_AM3, str2_QC_50e,sizeof (str2_QC_50e)},
+  {4, 0, 0x05, DR_SOCKET_AM3, str2_QC_50B,sizeof (str2_QC_50B)},
+  {4, 0, 0x06, DR_SOCKET_AM3, str2_Processor, sizeof (str2_Processor)},
+  {4, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor, sizeof (str2_e_Processor)},
+  {4, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor, sizeof (str2_B_Processor)},
+  {4, 0, 0x09, DR_SOCKET_AM3, str2_0e_Processor, sizeof (str2_0e_Processor)},
+  {4, 0, 0x0A, DR_SOCKET_AM3, str2_SE_AM3, sizeof (str2_SE_AM3)},
+  {4, 0, 0x0B, DR_SOCKET_AM3, str2_HE_AM3, sizeof (str2_HE_AM3)},
+  {4, 0, 0x0C, DR_SOCKET_AM3, str2_EE_AM3, sizeof (str2_EE_AM3)},
+  {4, 0, 0x0D, DR_SOCKET_AM3, str2_QCP_AM3, sizeof (str2_QCP_AM3)},
+  {4, 0, 0x0E, DR_SOCKET_AM3, str2_0_Processor, sizeof (str2_0_Processor)},
+  {2, 1, 0x01, DR_SOCKET_AM3, str2_L_Processor, sizeof (str2_L_Processor)},
+  {2, 1, 0x02, DR_SOCKET_AM3, str2_C_Processor, sizeof (str2_C_Processor)},
+  {4, 1, 0x00, DR_SOCKET_AM3, str2_TWKR_Black_Edition, sizeof (str2_TWKR_Black_Edition)},
+  {4, 1, 0x01, DR_SOCKET_AM3, str2_L_Processor, sizeof (str2_L_Processor)},
+  {4, 0, 0x0F, DR_SOCKET_AM3, 0, 0}
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3 = {
+  (sizeof (CpuF10BrandIdString1ArrayAm3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayAm3
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
+  (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayAm3
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
new file mode 100755
index 0000000000..1db5664235
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for package ASB2.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "F10PackageType.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+// String1
+CONST CHAR8 ROMDATA str_AMD_V[] = "AMD V";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_K[] = "AMD Athlon(tm) II Neo K";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_N[] = "AMD Athlon(tm) II Neo N";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_R[] = "AMD Athlon(tm) II Neo R";
+CONST CHAR8 ROMDATA str_Turion_II_Neo_K[] = "AMD Turion(tm) II Neo K";
+CONST CHAR8 ROMDATA str_Turion_II_Neo_N[] = "AMD Turion(tm) II Neo N";
+
+// String2
+CONST CHAR8 ROMDATA str_Asb2_5_Processor[] = "5 Processor";
+CONST CHAR8 ROMDATA str_Asb2_5_Dual_Core_Processor[] = "5 Dual-Core Processor";
+CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
+CONST CHAR8 ROMDATA str_L_Dual_Core_Processor[] = "L Dual-Core Processor";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAsb2[] =
+{
+  // ASB2
+  {1, 0, 1, DR_SOCKET_ASB2, str_Athlon_II_Neo_K, sizeof (str_Athlon_II_Neo_K)},
+  {1, 0, 2, DR_SOCKET_ASB2, str_AMD_V, sizeof (str_AMD_V)},
+  {1, 0, 3, DR_SOCKET_ASB2, str_Athlon_II_Neo_R, sizeof (str_Athlon_II_Neo_R)},
+  {2, 0, 1, DR_SOCKET_ASB2, str_Turion_II_Neo_K, sizeof (str_Turion_II_Neo_K)},
+  {2, 0, 2, DR_SOCKET_ASB2, str_Athlon_II_Neo_K, sizeof (str_Athlon_II_Neo_K)},
+  {2, 0, 3, DR_SOCKET_ASB2, str_AMD_V, sizeof (str_AMD_V)},
+  {2, 0, 4, DR_SOCKET_ASB2, str_Turion_II_Neo_N, sizeof (str_Turion_II_Neo_N)},
+  {2, 0, 5, DR_SOCKET_ASB2, str_Athlon_II_Neo_N, sizeof (str_Athlon_II_Neo_N)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAsb2[] =
+{
+  // ASB2
+  {1, 0, 0x01, DR_SOCKET_ASB2, str_Asb2_5_Processor, sizeof (str_Asb2_5_Processor)},
+  {1, 0, 0x02, DR_SOCKET_ASB2, str_L_Processor, sizeof (str_L_Processor)},
+  {2, 0, 0x01, DR_SOCKET_ASB2, str_Asb2_5_Dual_Core_Processor, sizeof (str_Asb2_5_Dual_Core_Processor)},
+  {2, 0, 0x02, DR_SOCKET_ASB2, str_L_Dual_Core_Processor, sizeof (str_L_Dual_Core_Processor)},
+  {1, 0, 0x0F, DR_SOCKET_ASB2, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x0F, DR_SOCKET_ASB2, 0, 0},    //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2 = {
+  (sizeof (CpuF10BrandIdString1ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayAsb2
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
+  (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayAsb2
+};
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
new file mode 100755
index 0000000000..6cd250e6c2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket C32.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+CONST CHAR8 ROMDATA str_Opteron_41[] = "AMD Opteron(tm) Processor 41";
+CONST CHAR8 ROMDATA str_Embedded_Opteron_C32[] = "Embedded AMD Opteron(tm) Processor ";
+
+// String2
+CONST CHAR8 ROMDATA str2_HE_C32[] = " HE";
+CONST CHAR8 ROMDATA str2_EE_C32[] = " EE";
+CONST CHAR8 ROMDATA str2_QS_HE_C32[] = "QS HE";
+CONST CHAR8 ROMDATA str2_LE_HE_C32[] = "LE HE";
+CONST CHAR8 ROMDATA str2_KX_HE_C32[] = "KX HE";
+CONST CHAR8 ROMDATA str2_GL_EE_C32[] = "GL EE";
+CONST CHAR8 ROMDATA str2_CL_EE[] = "CL EE";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayC32[] =
+{
+  // C32r1 string1:
+  {4, 0, 0x00, DR_SOCKET_C32, str_Opteron_41, sizeof (str_Opteron_41)},
+  {4, 1, 0x01, DR_SOCKET_C32, str_Embedded_Opteron_C32, sizeof (str_Embedded_Opteron_C32)},
+  {6, 0, 0x00, DR_SOCKET_C32, str_Opteron_41, sizeof (str_Opteron_41)},
+  {6, 1, 0x01, DR_SOCKET_C32, str_Embedded_Opteron_C32, sizeof (str_Embedded_Opteron_C32)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayC32[] =
+{
+  // C32r1 string2:
+  {4, 0, 0x00, DR_SOCKET_C32, str2_HE_C32, sizeof (str2_HE_C32)},
+  {4, 0, 0x01, DR_SOCKET_C32, str2_EE_C32, sizeof (str2_EE_C32)},
+  {4, 0, 0x0F, DR_SOCKET_C32, 0, 0},  //Size 0 for no suffix
+  {4, 1, 0x01, DR_SOCKET_C32, str2_QS_HE_C32, sizeof (str2_QS_HE_C32)},
+  {4, 1, 0x02, DR_SOCKET_C32, str2_LE_HE_C32, sizeof (str2_LE_HE_C32)},
+  {4, 1, 0x03, DR_SOCKET_C32, str2_CL_EE, sizeof (str2_CL_EE)},
+  {6, 0, 0x00, DR_SOCKET_C32, str2_HE_C32, sizeof (str2_HE_C32)},
+  {6, 0, 0x01, DR_SOCKET_C32, str2_EE_C32, sizeof (str2_EE_C32)},
+  {6, 0, 0x0F, DR_SOCKET_C32, 0, 0},  //Size 0 for no suffix
+  {6, 1, 0x01, DR_SOCKET_C32, str2_KX_HE_C32, sizeof (str2_KX_HE_C32)},
+  {6, 1, 0x02, DR_SOCKET_C32, str2_GL_EE_C32, sizeof (str2_GL_EE_C32)}
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32 = {
+  (sizeof (CpuF10BrandIdString1ArrayC32) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayC32
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
+  (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayC32
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
new file mode 100755
index 0000000000..a647bfd662
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
@@ -0,0 +1,176 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket Fr1207.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+/*CHAR8 strEngSample[] = "AMD Engineering Sample";
+CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
+CHAR8 strUnknown[] = "AMD Processor model unknown";
+*/
+CONST CHAR8 ROMDATA str_DC_Opteron83[] = "Dual-Core AMD Opteron(tm) Processor 83";
+CONST CHAR8 ROMDATA str_DC_Opteron23[] = "Dual-Core AMD Opteron(tm) Processor 23";
+CONST CHAR8 ROMDATA str_QC_Opteron83[] = "Quad-Core AMD Opteron(tm) Processor 83";
+CONST CHAR8 ROMDATA str_QC_Opteron23[] = "Quad-Core AMD Opteron(tm) Processor 23";
+CONST CHAR8 ROMDATA str_eQC_Opteron83[] = "Embedded AMD Opteron(tm) Processor 83";
+CONST CHAR8 ROMDATA str_eQC_Opteron23[] = "Embedded AMD Opteron(tm) Processor 23";
+CONST CHAR8 ROMDATA str_eQC_Opteron13[] = "Embedded AMD Opteron(tm) Processor 13";
+CONST CHAR8 ROMDATA str_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor ";
+CONST CHAR8 ROMDATA str_SC_Opteron84[] = "Six-Core AMD Opteron(tm) Processor 84";
+CONST CHAR8 ROMDATA str_SC_Opteron24[] = "Six-Core AMD Opteron(tm) Processor 24";
+
+CONST CHAR8 ROMDATA str_PhenomFX[] =  "AMD Phenom(tm) FX-";
+
+
+// String2
+CONST CHAR8 ROMDATA str2_SE[] = " SE";
+CONST CHAR8 ROMDATA str2_HE[] = " HE";
+CONST CHAR8 ROMDATA str2_EE[] = " EE";
+CONST CHAR8 ROMDATA str2_VS[] = "VS";
+CONST CHAR8 ROMDATA str2_QS[] = "QS";
+
+CONST CHAR8 ROMDATA str2_NP_HE[] = "NP HE";
+CONST CHAR8 ROMDATA str2_GF_HE[] = "GF HE";
+CONST CHAR8 ROMDATA str2_HF_HE[] = "HF HE";
+CONST CHAR8 ROMDATA str2_QS_HE[] = "QS HE";
+CONST CHAR8 ROMDATA str2_KH_HE[] = "KH HE";
+CONST CHAR8 ROMDATA str2_KS_EE[] = "KS EE";
+CONST CHAR8 ROMDATA str2_KS_HE[] = "KS HE";
+
+CONST CHAR8 ROMDATA str2_QCP[] = " Quad-Core Processor";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayFr1207[] =
+{
+  // FR2/FR4 1207
+  {2, 0, 0, DR_SOCKET_1207, str_DC_Opteron83, sizeof (str_DC_Opteron83)},
+  {2, 0, 1, DR_SOCKET_1207, str_DC_Opteron23, sizeof (str_DC_Opteron23)},
+  {3, 0, 0, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
+  {4, 0, 0, DR_SOCKET_1207, str_QC_Opteron83, sizeof (str_QC_Opteron83)},
+  {4, 0, 1, DR_SOCKET_1207, str_QC_Opteron23, sizeof (str_QC_Opteron23)},
+  {4, 0, 2, DR_SOCKET_1207, str_eQC_Opteron83, sizeof (str_eQC_Opteron83)},
+  {4, 0, 3, DR_SOCKET_1207, str_eQC_Opteron23, sizeof (str_eQC_Opteron23)},
+  {4, 0, 4, DR_SOCKET_1207, str_eQC_Opteron13, sizeof (str_eQC_Opteron13)},
+  {4, 0, 5, DR_SOCKET_1207, str_PhenomFX, sizeof (str_PhenomFX)},
+  {4, 1, 1, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
+  {6, 0, 0, DR_SOCKET_1207, str_SC_Opteron84, sizeof (str_SC_Opteron84)},
+  {6, 0, 1, DR_SOCKET_1207, str_SC_Opteron24, sizeof (str_SC_Opteron24)},
+  {6, 1, 1, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayFr1207[] =
+{
+  // FR2/FR4 1207
+  {2, 0, 0x0A, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
+  {2, 0, 0x0B, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
+  {2, 0, 0x0C, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
+  {2, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {3, 0, 0x00, DR_SOCKET_1207, str2_NP_HE, sizeof (str2_NP_HE)},
+  {3, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {4, 0, 0x0A, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
+  {4, 0, 0x0B, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
+  {4, 0, 0x0C, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
+  {4, 0, 0x0D, DR_SOCKET_1207, str2_QCP, sizeof (str2_QCP)},
+  {4, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {4, 1, 0x01, DR_SOCKET_1207, str2_GF_HE, sizeof (str2_GF_HE)},
+  {4, 1, 0x02, DR_SOCKET_1207, str2_HF_HE, sizeof (str2_HF_HE)},
+  {4, 1, 0x03, DR_SOCKET_1207, str2_VS, sizeof (str2_VS)},
+  {4, 1, 0x04, DR_SOCKET_1207, str2_QS_HE, sizeof (str2_QS_HE)},
+  {4, 1, 0x05, DR_SOCKET_1207, str2_NP_HE, sizeof (str2_NP_HE)},
+  {4, 1, 0x06, DR_SOCKET_1207, str2_KH_HE, sizeof (str2_KH_HE)},
+  {4, 1, 0x07, DR_SOCKET_1207, str2_KS_EE, sizeof (str2_KS_EE)},
+  {6, 0, 0x00, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
+  {6, 0, 0x01, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
+  {6, 0, 0x02, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
+  {6, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {6, 1, 0x01, DR_SOCKET_1207, str2_QS, sizeof (str2_QS)},
+  {6, 1, 0x02, DR_SOCKET_1207, str2_KS_HE, sizeof (str2_KS_HE)},
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayFr1207 = {
+  (sizeof (CpuF10BrandIdString1ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayFr1207
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
+  (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayFr1207
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
new file mode 100755
index 0000000000..ed312a7461
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket G34.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+CONST CHAR8 ROMDATA str_Opteron_61[] = "AMD Opteron(tm) Processor 61";
+CONST CHAR8 ROMDATA str_Embedded_Opteron_G34[] = "Embedded AMD Opteron(tm) Processor ";
+
+// String2
+CONST CHAR8 ROMDATA str2_SE_G34[] = " SE";
+CONST CHAR8 ROMDATA str2_HE_G34[] = " HE";
+CONST CHAR8 ROMDATA str2_QS_G34[] = "QS";
+CONST CHAR8 ROMDATA str2_KS_G34[] = "KS";
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayG34[] =
+{
+  // G34r1 string1:
+  {8, 0, 0x00, DR_SOCKET_G34, str_Opteron_61, sizeof (str_Opteron_61)},
+  {8, 1, 0x01, DR_SOCKET_G34, str_Embedded_Opteron_G34, sizeof (str_Embedded_Opteron_G34)},
+  {12, 0, 0x00, DR_SOCKET_G34, str_Opteron_61, sizeof (str_Opteron_61)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayG34[] =
+{
+  // G34r1 string2:
+  {8, 0, 0x00, DR_SOCKET_G34, str2_HE_G34, sizeof (str2_HE_G34)},
+  {8, 0, 0x01, DR_SOCKET_G34, str2_SE_G34, sizeof (str2_SE_G34)},
+  {8, 1, 0x01, DR_SOCKET_G34, str2_QS_G34, sizeof (str2_QS_G34)},
+  {8, 1, 0x02, DR_SOCKET_G34, str2_KS_G34, sizeof (str2_KS_G34)},
+  {8, 0, 0x0F, DR_SOCKET_G34, 0, 0},  //Size 0 for no suffix
+  {12, 0, 0x00, DR_SOCKET_G34, str2_HE_G34, sizeof (str2_HE_G34)},
+  {12, 0, 0x01, DR_SOCKET_G34, str2_SE_G34, sizeof (str2_SE_G34)},
+  {12, 0, 0x0F, DR_SOCKET_G34, 0, 0}  //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34 = {
+  (sizeof (CpuF10BrandIdString1ArrayG34) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayG34
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
+  (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayG34
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
new file mode 100755
index 0000000000..c98d369f2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket S1g3.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+/*CHAR8 strEngSample[] = "AMD Engineering Sample";
+CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
+CHAR8 strUnknown[] = "AMD Processor model unknown";
+*/
+// S1g3 NC 0
+CONST CHAR8 ROMDATA str_Sempron_M1[] = "AMD Sempron(tm) M1";
+
+// S1g3 NC 1
+CONST CHAR8 ROMDATA str_Turion_II_U_DC_M_M6[] = "AMD Turion(tm) II Ultra Dual-Core Mobile M6";
+CONST CHAR8 ROMDATA str_Turion_II_DC_M_M5[] = "AMD Turion(tm) II Dual-Core Mobile M5";
+CONST CHAR8 ROMDATA str_Athlon_II_DC_M3[] = "AMD Athlon(tm) II Dual-Core M3";
+
+// String2
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g3[] =
+{
+  // S1g3
+  {1, 0, 0, DR_SOCKET_S1G3, str_Sempron_M1, sizeof (str_Sempron_M1)},
+  {2, 0, 0, DR_SOCKET_S1G3, str_Turion_II_U_DC_M_M6, sizeof (str_Turion_II_U_DC_M_M6)},
+  {2, 0, 1, DR_SOCKET_S1G3, str_Turion_II_DC_M_M5, sizeof (str_Turion_II_DC_M_M5)},
+  {2, 0, 2, DR_SOCKET_S1G3, str_Athlon_II_DC_M3, sizeof (str_Athlon_II_DC_M3)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g3[] =
+{
+  // S1g3
+  {1, 0, 0x0F, DR_SOCKET_S1G3, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x0F, DR_SOCKET_S1G3, 0, 0}     //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3 = {
+  (sizeof (CpuF10BrandIdString1ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayS1g3
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
+  (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayS1g3
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
new file mode 100755
index 0000000000..343cda9a55
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
@@ -0,0 +1,138 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for package S1g4.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "F10PackageType.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+// String1
+CONST CHAR8 ROMDATA str_AMD_V_S1g4[] = "AMD V";
+CONST CHAR8 ROMDATA str_Turion_II_P[] = "AMD Turion(tm) II P";
+CONST CHAR8 ROMDATA str_Athlon_II_P[] = "AMD Athlon(tm) II P";
+CONST CHAR8 ROMDATA str_Phenom_II_X[] = "AMD Phenom(tm) II X";
+CONST CHAR8 ROMDATA str_Turion_II_N[] = "AMD Turion(tm) II N";
+CONST CHAR8 ROMDATA str_Athlon_II_N[] = "AMD Athlon(tm) II N";
+CONST CHAR8 ROMDATA str_Phenom_II_P[] = "AMD Phenom(tm) II P";
+CONST CHAR8 ROMDATA str_Phenom_II_N[] = "AMD Phenom(tm) II N";
+
+// String2
+CONST CHAR8 ROMDATA str_0_Processor[] = "0 Processor";
+CONST CHAR8 ROMDATA str_0_Dual_Core_Processor[] = "0 Dual-Core Processor";
+CONST CHAR8 ROMDATA str_0_Triple_Core_Processor[] = "0 Triple-Core Processor";
+CONST CHAR8 ROMDATA str_0_Quad_Core_Processor[] = "0 Quad-Core Processor";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g4[] =
+{
+  // S1g4
+  {1, 0, 1, DR_SOCKET_S1G4, str_AMD_V_S1g4, sizeof (str_AMD_V_S1g4)},
+  {2, 0, 3, DR_SOCKET_S1G4, str_Turion_II_P, sizeof (str_Turion_II_P)},
+  {2, 0, 4, DR_SOCKET_S1G4, str_Athlon_II_P, sizeof (str_Athlon_II_P)},
+  {2, 0, 5, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
+  {2, 0, 6, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)},
+  {2, 0, 7, DR_SOCKET_S1G4, str_Turion_II_N, sizeof (str_Turion_II_N)},
+  {2, 0, 8, DR_SOCKET_S1G4, str_Athlon_II_N, sizeof (str_Athlon_II_N)},
+  {3, 0, 2, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
+  {3, 0, 3, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)},
+  {4, 0, 1, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
+  {4, 0, 2, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
+  {4, 0, 3, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g4[] =
+{
+  // S1g4
+  {1, 0, 0x01, DR_SOCKET_S1G4, str_0_Processor, sizeof (str_0_Processor)},
+  {2, 0, 0x02, DR_SOCKET_S1G4, str_0_Dual_Core_Processor, sizeof (str_0_Dual_Core_Processor)},
+  {3, 0, 0x02, DR_SOCKET_S1G4, str_0_Triple_Core_Processor, sizeof (str_0_Triple_Core_Processor)},
+  {4, 0, 0x01, DR_SOCKET_S1G4, str_0_Quad_Core_Processor, sizeof (str_0_Quad_Core_Processor)},
+  {1, 0, 0x0F, DR_SOCKET_S1G4, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x0F, DR_SOCKET_S1G4, 0, 0},    //Size 0 for no suffix
+  {3, 0, 0x0F, DR_SOCKET_S1G4, 0, 0},    //Size 0 for no suffix
+  {4, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}     //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4 = {
+  (sizeof (CpuF10BrandIdString1ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayS1g4
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
+  (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayS1g4
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
new file mode 100755
index 0000000000..4f2296ce8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AMD Family_10 ROM Execution Cache Defaults
+ *
+ * Contains default values for ROM execution cache setup
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6163 $   @e \$Date: 2008-05-28 15:41:06 -0500 (Wed, 28 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#define BSP_STACK_SIZE            16384
+#define CORE0_STACK_SIZE          16384
+#define CORE1_STACK_SIZE          4096
+#define MEM_TRAINING_BUFFER_SIZE  16384
+#define VAR_MTRR_MASK             0x0000FFFFFFFFFFFFull
+
+#define SHARED_MEM_SIZE       0
+
+CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
+{
+  BSP_STACK_SIZE,
+  CORE0_STACK_SIZE,
+  CORE1_STACK_SIZE,
+  MEM_TRAINING_BUFFER_SIZE,
+  SHARED_MEM_SIZE,
+  VAR_MTRR_MASK
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific properties of the cache, and its usage.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  CacheInfoPtr             Points to the cache info properties on exit.
+ *  @param[out]  NumberOfElements         Will be one to indicate one entry.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *CacheInfoPtr = &CpuF10CacheInfo;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
new file mode 100755
index 0000000000..1c638c7a8a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in,out]   PciAddress               Pointer to Pci address struct.
+ *    @param[in,out]   AndMask                  Pointer to AND mask bits.
+ *    @param[in,out]   OrMask                   Pointer to Or mask bits.
+ *    @param[in]       StdHeader                Handle of Header for calling lib functions and services.
+ */
+STATIC VOID
+GetF10CacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN OUT   PCI_ADDR                     *PciAddress,
+  IN OUT   UINT32                       *AndMask,
+  IN OUT   UINT32                       *OrMask,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32     CoreCount;
+  CPU_LOGICAL_ID LogicalId;
+
+  //
+  // F3xDC[25:19] = 28h
+  // F3xDC[18:16] = 111b
+  //
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  *AndMask = 0xFC00FFFF;
+  *OrMask = 0x01470000;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F10_C2) != 0) {
+    //
+    //For F10_C2 single Core, F3xDC[18:16] = 0
+    //
+    GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+    if (CoreCount == 1) {
+      *OrMask = 0x01400000;
+    }
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt =
+{
+  0,
+  GetF10CacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
new file mode 100755
index 0000000000..f72cb0fd1b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -0,0 +1,411 @@
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuLateInit.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10Translate7BitVidTo6Bit (
+  IN OUT   UINT8 * MaxVidPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF10GetInfo
+ *
+ *    Get CPU type information
+ *
+ *    @param[in,out]  CpuInfoPtr     Pointer to CPU_TYPE_INFO struct.
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *
+ */
+STATIC VOID
+DmiF10GetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CPUID_DATA CpuId;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+  CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
+  CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
+  CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
+  CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4)  & 0xF; // bit 7:4
+  CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
+
+  CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+  CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15
+  CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11
+  CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
+  CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber--;
+
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
+  CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
+
+  switch (CpuInfoPtr->PackageType) {
+  case DR_SOCKET_1207:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_F1207;
+    break;
+  case DR_SOCKET_AM3:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_AM3;
+    break;
+  case DR_SOCKET_S1G3:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_S1GX;
+    break;
+  case DR_SOCKET_G34:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_G34;
+    break;
+  case DR_SOCKET_ASB2:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
+    break;
+  case DR_SOCKET_C32:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_C32;
+    break;
+  default:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
+    break;
+  }
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF10GetVoltage
+ *
+ *    Get the voltage value according to SMBIOS SPEC's requirement.
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *
+ *    @retval  Voltage   - CPU Voltage.
+ *
+ */
+STATIC UINT8
+DmiF10GetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8     MaxVid;
+  UINT8     Voltage;
+  UINT32    Pvimode;
+  UINT32    CurrentNodeNum;
+  UINT64    MsrData;
+  PCI_ADDR  TempAddr;
+
+  // Voltage = 0x80 + (voltage at boot time * 10)
+  GetCurrentNodeNum (&CurrentNodeNum, StdHeader);
+  TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_3, PW_CTL_MISC_REG);
+  LibAmdPciReadBits (TempAddr, 8, 8, &Pvimode, (VOID *)StdHeader);
+  //Pvimode is a 1-bit register field:  1-PVI 0-SVI
+
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
+  MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
+  if (MaxVid == 0) {
+    LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
+    MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+  }
+
+  if (Pvimode) {
+    // PVI mode
+    F10Translate7BitVidTo6Bit (&MaxVid);
+    if (MaxVid >= 0x20) {
+      Voltage = (UINT8) ((7625 - (125 * (MaxVid - 0x20)) + 500) / 1000);
+    } else {
+      Voltage = (UINT8) ((1550 - (25 * MaxVid) + 50) / 100);
+    }
+  } else {
+    // is SVI mode
+    if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
+      Voltage = 0;
+    } else {
+      Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000);
+    }
+  }
+
+  Voltage += 0x80;
+  return (Voltage);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF10GetMaxSpeed
+ *
+ *    Get the Max Speed
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *
+ *    @retval  MaxSpeed   - CPU Max Speed.
+ *
+ */
+STATIC UINT16
+DmiF10GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 TempVar8_a;
+  UINT64 MsrData;
+  UINT16  MaxSpeed;
+
+  // CPU COF = 100MHz * (CpuFid + 0x10) / (2 ^ CpuDid)
+  LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
+  TempVar8_a = (UINT8) ((PSTATE_MSR *) &MsrData)->CpuDid;
+  switch (TempVar8_a) {
+  case 0:
+    TempVar8_a = 1;
+    break;
+  case 1:
+    TempVar8_a = 2;
+    break;
+  case 2:
+    TempVar8_a = 4;
+    break;
+  case 3:
+    TempVar8_a = 8;
+    break;
+  case 4:
+    TempVar8_a = 16;
+    break;
+  default:
+    TempVar8_a = 1;
+    break;
+  }
+
+  MaxSpeed = (UINT16) (MsrData & 0x3F); // get CpuFid
+  MaxSpeed = (100 * (MaxSpeed + 0x10)) / TempVar8_a;
+  return (MaxSpeed);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ * Processor Family Table
+ *
+ * Note: 'x' means we don't care this field
+ *       002h = "Unknown"
+ *       038h = "AMD Turion(TM) II Ultra Dual-Core Mobile M Processor Family"
+ *       039h = "AMD Turion(TM) II Dual-Core Mobile M Processor Family"
+ *       03Ah = "AMD Athlon(TM) II Dual-Core M Processor Family"
+ *       083h = "AMD Athlon(tm) 64 Processor Family"
+ *       084h = "AMD Opteron(TM) Processor Family"
+ *       085h = "AMD Sempron(tm) Processor Family"
+ *       087h = "Dual-Core AMD Opteron Processor Family"
+ *       08Ah = "Quad-Core AMD Opteron Processor Family"
+ *       08Ch = "AMD Phenom FX Quad-Core Processor Family"
+ *       08Dh = "AMD Phenom X4 Quad-Core Processor Family"
+ *       08Eh = "AMD Phenom X2 Dual-Core Processor Family"
+ *       08Fh = "AMD Athlon X2 Dual-Core Processor Family"
+ *       0E6h = "Embedded AMD Opteron Processor Family"
+ *       0E7h = "AMD Phenom Triple-Core Processor Family"
+ *       0ECh = "AMD Phenom(TM) II Processor Family"
+ *       0EDh = "AMD Athlon(TM) II Processor Family"
+ *       0EEh = "Six-Core AMD Opteron(TM) Processor Family"
+ *       0EFh = "AMD Sempron(TM) M Processor Family"
+ *-------------------------------------------------------------------------------------*/
+CONST DMI_BRAND_ENTRY ROMDATA Family10BrandList[] =
+{
+  // Brand --> DMI ID translation table
+  // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
+  // {'x', 'x', 'x', 'x', 0x02} MUST be the last one.
+    {0, 0, 1, 0, 0x87},
+    {0, 0, 1, 1, 0x87},
+    {0, 0, 2, 0, 0xE6},
+    {0, 0, 3, 0, 0x8A},
+    {0, 0, 3, 1, 0x8A},
+    {0, 0, 3, 2, 0xE6},
+    {0, 0, 3, 3, 0xE6},
+    {0, 0, 3, 4, 0xE6},
+    {0, 0, 3, 5, 0x8C},
+    {0, 0, 5, 0, 0xEE},
+    {0, 0, 5, 1, 0xEE},
+    {0, 1, 3, 1, 0xE6},
+    {1, 0, 0, 0, 0x83},
+    {1, 0, 0, 1, 0x85},
+    {1, 0, 0, 2, 0x85},
+    {1, 0, 0, 3, 0xED},
+    {1, 0, 1, 0, 0x87},
+    {1, 0, 1, 1, 0x8F},
+    {1, 0, 1, 2, 0xED},
+    {1, 0, 1, 3, 0xED},
+    {1, 0, 1, 4, 0xED},
+    {1, 0, 1, 5, 0xED},
+    {1, 0, 1, 6, 0xED},
+    {1, 0, 1, 7, 0xEC},
+    {1, 0, 1, 8, 0xED},
+    {1, 0, 1, 9, 0xED},
+    {1, 0, 1, 0xA, 0xEC},
+    {1, 0, 1, 0xB, 0xEC},
+    {1, 0, 2, 0, 0xE7},
+    {1, 0, 2, 1, 0xEC},
+    {1, 0, 2, 2, 0xEC},
+    {1, 0, 2, 3, 0xEC},
+    {1, 0, 2, 4, 0xEC},
+    {1, 0, 2, 5, 0xED},
+    {1, 0, 2, 6, 0xED},
+    {1, 0, 2, 7, 0xED},
+    {1, 0, 2, 8, 0xEC},
+    {1, 0, 2, 9, 0xED},
+    {1, 0, 2, 0xA, 0xED},
+    {1, 0, 3, 0, 0x8A},
+    {1, 0, 3, 1, 0x8C},
+    {1, 0, 3, 2, 0x8D},
+    {1, 0, 3, 3, 0xEC},
+    {1, 0, 3, 4, 0xEC},
+    {1, 0, 3, 5, 0xEC},
+    {1, 0, 3, 6, 0xEC},
+    {1, 0, 3, 7, 0xEC},
+    {1, 0, 3, 8, 0xEC},
+    {1, 0, 3, 9, 0xEC},
+    {1, 0, 3, 0xA, 0xED},
+    {1, 0, 3, 0xB, 0xED},
+    {1, 0, 3, 0xC, 0xED},
+    {1, 0, 3, 0xD, 0xED},
+    {1, 0, 3, 0xE, 0xEC},
+    {1, 0, 3, 0xF, 0xED},
+    {1, 1, 1, 1, 0xED},
+    {1, 1, 1, 2, 0xED},
+    {1, 1, 3, 0, 0xEC},
+    {1, 1, 3, 1, 0xEC},
+    {2, 0, 0, 0, 0xEF},
+    {2, 0, 0, 1, 0xEF},
+    {2, 0, 1, 0, 0x38},
+    {2, 0, 1, 1, 0x39},
+    {2, 0, 1, 2, 0x3A},
+    {2, 0, 1, 3, 0x39},
+    {2, 0, 1, 4, 0xED},
+    {2, 0, 1, 5, 0xEC},
+    {2, 0, 1, 6, 0xEC},
+    {2, 0, 1, 7, 0x39},
+    {2, 0, 1, 8, 0xED},
+    {2, 0, 2, 2, 0xEC},
+    {2, 0, 2, 3, 0xEC},
+    {2, 0, 3, 1, 0xEC},
+    {2, 0, 3, 2, 0xEC},
+    {2, 0, 3, 3, 0xEC},
+    {3, 0, 7, 0, 0x84},
+    {3, 0, 0xB, 0, 0x84},
+    {4, 0, 0, 1, 0xED},
+    {4, 0, 1, 1, 0x39},
+    {4, 0, 1, 2, 0xED},
+    {5, 'x', 'x', 'x', 0x84},
+    {'x', 'x', 'x', 'x', 0x02}
+  };
+
+CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
+{
+// This table is for Processor family 10h
+  AMD_FAMILY_10,                      // ID for Family 10h
+  DmiF10GetInfo,                  // Transfer vectors for family
+  DmiF10GetVoltage,                  //   specific routines (above)
+  DmiF10GetMaxSpeed,
+  (sizeof (Family10BrandList) / sizeof (Family10BrandList[0])), // Number of entries in following table
+  &Family10BrandList[0]
+};
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  F10Translate7BitVidTo6Bit
+ *
+ *    translate 7 bit VID to 6 bit VID
+ *
+ *    @param[in]  MaxVidPtr   - Pointer to MaxVid.
+ */
+VOID
+STATIC
+F10Translate7BitVidTo6Bit (
+  IN OUT   UINT8 * MaxVidPtr
+  )
+{
+  if ((*MaxVidPtr >= 0x5E) && (*MaxVidPtr <= 0x7F)) {
+    *MaxVidPtr = 0x3F;
+  } else if ((*MaxVidPtr >= 0x3F) && (*MaxVidPtr <= 0x5D)) {
+    *MaxVidPtr = *MaxVidPtr - 0x1F;
+  } else if (*MaxVidPtr <= 0x3E) {
+    *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
new file mode 100755
index 0000000000..d5c98aa59d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -0,0 +1,403 @@
+/**
+ * @file
+ *
+ * AMD Family_10 after warm reset sequence
+ *
+ * Performs the "CPU Core Minimum P-State Transition Sequence After Warm Reset"
+ * as described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "cpuF10EarlyInit.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Enum for handling code branching while transitioning to the
+/// minimum P-state after a warm reset
+typedef enum {
+  EXIT_SEQUENCE,        ///< Exit the sequence
+  STEP7,                ///< Go to step 7
+  STEP17,               ///< Go to step 17
+  STEP20                ///< Go to step 20
+} GO_TO_STEP;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10PmAfterResetCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+WaitForCpuFidAndDidToMatch (
+  IN       UINT32             PstateNumber,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the necessary steps after
+ * a warm reset has occurred.
+ *
+ * The steps are as follows:
+ *    1. Modify F3xDC[PstateMaxVal] to reflect the lowest performance P-state
+ *       supported, as indicated in MSRC001_00[68:64][PstateEn]
+ *    2. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
+ *    3. If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
+ *    4. If F3xDC[PstateMaxVal] = 0 or F3xDC[PstateMaxVal] != 4, go to step 7
+ *    5. If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
+ *    6. Exit the sequence
+ *    7. Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
+ *       register pointed to by F3xDC[PstateMaxVal]+1
+ *    8. Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
+ *    9. Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+ *   10. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by (the new) F3xDC[PstateMaxVal]
+ *   11. Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+ *   12. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by (the new) F3xDC[PstateMaxVal]-1
+ *   13. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
+ *   14. If required, transition the NB COF and VID to the NbDid and NbVid from the
+ *       P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
+ *       and VID transition sequence after a warm reset
+ *   15. Write MSRC001_00[68:64][PstateEn]=0 for the P-state pointed to by F3xDC[PstateMaxVal]
+ *   16. Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] and exit the sequence
+ *   17. Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+ *   18. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by F3xDC[PstateMaxVal]-1
+ *   19. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
+ *   20. Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+ *   21. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by F3xDC[PstateMaxVal]
+ *   22. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
+ *   23. Issue an LDTSTOP assertion in the IO hub and exit sequence
+ *   24. If required, transition the NB COF and VID to the NbDid and NbVid from the
+ *       P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
+ *       transition sequence after a warm reset
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    PsMaxVal;
+  UINT32    CoreNum;
+  UINT32    MsrAddr;
+  UINT32    Core;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT64    MsrRegister;
+  PCI_ADDR  PciAddress;
+  AP_TASK   TaskPtr;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+
+  ASSERT (Core == 0);
+
+  // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
+  //        P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
+  for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
+    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+  PsMaxVal = MsrAddr - PS_REG_BASE;
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = CPTC2_REG;
+  AndMask = 0xFFFFFFFF;
+  OrMask = 0x00000000;
+  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
+  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PsMaxVal;
+  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+  // Launch each local core to perform the remaining steps.
+  TaskPtr.FuncAddress.PfApTask = F10PmAfterResetCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmAfterReset to perform MSR initialization on all
+ * cores of a family 10h socket.
+ *
+ * This function implements steps 2 - 24 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmAfterResetCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Ignored;
+  UINT32 PsMaxVal;
+  UINT32 PciRegister;
+  UINT64 MsrRegister;
+  UINT64 CurrentLimitMsr;
+  PCI_ADDR PciAddress;
+  GO_TO_STEP GoToStep;
+  AGESA_STATUS IgnoredSts;
+  CPU_LOGICAL_ID LogicalId;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
+  if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+    if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
+      LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+      MsrRegister |= BIT62;
+      LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+    }
+  }
+
+  GoToStep = EXIT_SEQUENCE;
+
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &CurrentLimitMsr, StdHeader);
+  PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
+
+  // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate !=
+      ((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
+    GoToStep = STEP20;
+  } else {
+    // Step 4 If F3xDC[PstateMaxVal] = 0 || F3xDC[PstateMaxVal] != 4, go to step 7
+    if ((PsMaxVal == 0) || (PsMaxVal != 4)) {
+      GoToStep = STEP7;
+    } else {
+      // Step 5 If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
+      if (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->CurPstateLimit <=
+          (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal - 1)) {
+        GoToStep = STEP17;
+      }
+    }
+  }
+  switch (GoToStep) {
+  default:
+  case EXIT_SEQUENCE:
+    // Step 6 Exit the sequence
+    break;
+  case STEP7:
+    // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
+    //        register pointed to by F3xDC[PstateMaxVal]+1
+    LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader);
+    LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+
+    // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = CPTC2_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PsMaxVal + 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+    // Step 9 Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal + 1), (BOOLEAN) FALSE, StdHeader);
+
+    // Step 10 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by (the new) F3xDC[PstateMaxVal]
+    WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal + 1), StdHeader);
+
+    // Step 11 Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
+
+    // Step 12 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by (the new) F3xDC[PstateMaxVal]-1
+    WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
+
+    // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
+    if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
+        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+        MsrRegister |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      }
+    }
+
+    // Step 14 If required, transition the NB COF and VID to the NbDid and NbVid from the
+    //         P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
+    //         and VID transition sequence after a warm reset
+
+    // Step 15 Write 0 to PstateEn of the P-state register pointed to by (the new) F3xDC[PstateMaxVal]
+    LibAmdMsrRead ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+    ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
+    LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+
+    // Step 16 Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal]
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PsMaxVal;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    break;
+  case STEP17:
+    // Step 17 Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal - 1), (BOOLEAN) FALSE, StdHeader);
+
+    // Step 18 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by F3xDC[PstateMaxVal]-1
+    WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal - 1), StdHeader);
+
+    // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
+    if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
+        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+        MsrRegister |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      }
+    }
+
+    // Fall through from step 19 to step 20
+  case STEP20:
+    // Step 20 Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
+
+    // Step 21 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by F3xDC[PstateMaxVal]
+    WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
+
+    // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
+    //         the sequence
+    if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
+        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+        MsrRegister |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+        break;
+      }
+    }
+
+    // Step 23 Issue an LDTSTOP and exit the sequence
+
+    // Step 24 If required, transition the NB COF and VID to the NbDid and NbVid from the
+    //         P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
+    //         transition sequence after a warm reset
+    break;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
+ * match a specific P-state.
+ *
+ * This function implements steps 11, 13, 18, and 20 on each core as needed.
+ *
+ * @param[in]  PstateNumber       P-state settings to match
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+WaitForCpuFidAndDidToMatch (
+  IN       UINT32             PstateNumber,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT64  TargetPsMsr;
+  UINT64  CurrentStatus;
+
+  // Get target P-state settings
+  LibAmdMsrRead ((MSR_PSTATE_0 + PstateNumber), &TargetPsMsr, StdHeader);
+
+  // Wait for current CPU FID/DID to match target FID/DID
+  do {
+    LibAmdMsrRead (MSR_COFVID_STS, &CurrentStatus, StdHeader);
+  } while ((((COFVID_STS_MSR *) &CurrentStatus)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
+           (((COFVID_STS_MSR *) &CurrentStatus)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h
new file mode 100755
index 0000000000..a55a4832b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Early Init related functions Prototypes.
+ *
+ * Contains code that provide power management functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_EARLY_INIT_H_
+#define _CPU_F10_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_EARLY_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
new file mode 100755
index 0000000000..12a2e88977
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -0,0 +1,389 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific feature leveling functions.
+ *
+ * Provides feature leveling functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuPostInit.h"
+#include "cpuF10FeatureLeveling.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+cpuFeatureListNeedUpdate (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  );
+
+VOID
+STATIC
+updateCpuFeatureList (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function get features which CPU supports.
+ *
+ *  @CpuServiceMethod{::F_CPU_SAVE_FEATURES}.
+ *
+ *  Read features from MSR_C0011004 and MSR_C0011005.
+ *
+ *    @param[in]      FamilySpecificServices   - Pointer to CPU_SPECIFIC_SERVICES struct.
+ *    @param[in,out]  cpuFeatureList           - Pointer to CPU_FEATURES_LIST struct.
+ *    @param[in]      StdHeader                - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+F10SaveFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 CpuMsrData;
+  BOOLEAN *FirstTime;
+  BOOLEAN *NeedLeveling;
+  CPU_F10_FEATURES *CpuF10Features;
+  CPU_F10_EXT_FEATURES *CpuF10ExtFeatures;
+  CPU_FEATURES_LIST thisCoreCpuFeatureList;
+
+  FirstTime = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST));
+  NeedLeveling = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
+
+  LibAmdMemFill (&thisCoreCpuFeatureList, 0x0, sizeof (CPU_FEATURES_LIST), StdHeader);
+  LibAmdMsrRead (MSR_CPUID_FEATS, &CpuMsrData, StdHeader);
+  CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData;
+
+  thisCoreCpuFeatureList.APIC = (UINT8) CpuF10Features->CpuF10FeaturesLo.APIC;
+  thisCoreCpuFeatureList.CLFSH = (UINT8) CpuF10Features->CpuF10FeaturesLo.CLFSH;
+  thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMOV;
+  thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B;
+  thisCoreCpuFeatureList.DE = (UINT8) CpuF10Features->CpuF10FeaturesLo.DE;
+  thisCoreCpuFeatureList.FPU = (UINT8) CpuF10Features->CpuF10FeaturesLo.FPU;
+  thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.FXSR;
+  thisCoreCpuFeatureList.HTT = (UINT8) CpuF10Features->CpuF10FeaturesLo.HTT;
+  thisCoreCpuFeatureList.MCA = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCA;
+  thisCoreCpuFeatureList.MCE = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCE;
+  thisCoreCpuFeatureList.MMX = (UINT8) CpuF10Features->CpuF10FeaturesLo.MMX;
+  thisCoreCpuFeatureList.MSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MSR;
+  thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MTRR;
+  thisCoreCpuFeatureList.PAE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAE;
+  thisCoreCpuFeatureList.PAT = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAT;
+  thisCoreCpuFeatureList.PGE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PGE;
+  thisCoreCpuFeatureList.PSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE;
+  thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE36;
+  thisCoreCpuFeatureList.SSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE;
+  thisCoreCpuFeatureList.SSE2 = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE2;
+  thisCoreCpuFeatureList.SysEnterSysExit = (UINT8) CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit;
+  thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10Features->CpuF10FeaturesLo.TimeStampCounter;
+  thisCoreCpuFeatureList.VME = (UINT8) CpuF10Features->CpuF10FeaturesLo.VME;
+
+  thisCoreCpuFeatureList.CMPXCHG16B = (UINT8) CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B;
+  thisCoreCpuFeatureList.Monitor = (UINT8) CpuF10Features->CpuF10FeaturesHi.Monitor;
+  thisCoreCpuFeatureList.POPCNT = (UINT8) CpuF10Features->CpuF10FeaturesHi.POPCNT;
+  thisCoreCpuFeatureList.SSE3 = (UINT8) CpuF10Features->CpuF10FeaturesHi.SSE3;
+
+  LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
+  CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData;
+
+  thisCoreCpuFeatureList.ThreeDNow = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow;
+  thisCoreCpuFeatureList.ThreeDNowExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt;
+  thisCoreCpuFeatureList.APIC = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC;
+  thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV;
+  thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B;
+  thisCoreCpuFeatureList.DE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE;
+  thisCoreCpuFeatureList.FFXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR;
+  thisCoreCpuFeatureList.FPU = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU;
+  thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR;
+  thisCoreCpuFeatureList.LM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM;
+  thisCoreCpuFeatureList.MCA = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA;
+  thisCoreCpuFeatureList.MCE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE;
+  thisCoreCpuFeatureList.MMX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX;
+  thisCoreCpuFeatureList.MmxExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt;
+  thisCoreCpuFeatureList.MSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR;
+  thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR;
+  thisCoreCpuFeatureList.NX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX;
+  thisCoreCpuFeatureList.PAE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE;
+  thisCoreCpuFeatureList.Page1GB = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB;
+  thisCoreCpuFeatureList.PAT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT;
+  thisCoreCpuFeatureList.PGE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE;
+  thisCoreCpuFeatureList.PSE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE;
+  thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36;
+  thisCoreCpuFeatureList.RDTSCP = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP;
+  thisCoreCpuFeatureList.SysCallSysRet = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet;
+  thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter;
+  thisCoreCpuFeatureList.VME = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME;
+
+  thisCoreCpuFeatureList.ThreeDNowPrefetch = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch;
+  thisCoreCpuFeatureList.ABM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM;
+  thisCoreCpuFeatureList.AltMovCr8 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8;
+  thisCoreCpuFeatureList.CmpLegacy = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy;
+  thisCoreCpuFeatureList.ExtApicSpace = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace;
+  thisCoreCpuFeatureList.IBS = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS;
+  thisCoreCpuFeatureList.LahfSahf = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf;
+  thisCoreCpuFeatureList.MisAlignSse = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse;
+  thisCoreCpuFeatureList.OSVW = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM;
+  thisCoreCpuFeatureList.SKINIT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT;
+  thisCoreCpuFeatureList.SSE4A = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A;
+  thisCoreCpuFeatureList.SVM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM;
+  thisCoreCpuFeatureList.WDT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT;
+  thisCoreCpuFeatureList.NodeId = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId;
+
+  if (*FirstTime) {
+    updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList);
+    *FirstTime = FALSE;
+  } else if (cpuFeatureListNeedUpdate (cpuFeatureList, &thisCoreCpuFeatureList)) {
+    updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList);
+    *NeedLeveling = TRUE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function set features which All CPUs support.
+ *
+ *  @CpuServiceMethod{::F_CPU_WRITE_FEATURES}.
+ *
+ *  Write least common features to MSR_C0011004 and MSR_C0011005.
+ *
+ *    @param[in]      FamilySpecificServices   - Pointer to CPU_SPECIFIC_SERVICES struct.
+ *    @param[in,out]  cpuFeatureList           - Pointer to CPU_FEATURES_LIST struct.
+ *    @param[in]      StdHeader                - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+F10WriteFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 CpuMsrData;
+  CPU_F10_FEATURES *CpuF10Features;
+  CPU_F10_EXT_FEATURES *CpuF10ExtFeatures;
+
+  CpuMsrData = 0;
+  CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData;
+
+  CpuF10Features->CpuF10FeaturesLo.APIC = cpuFeatureList->APIC;
+  CpuF10Features->CpuF10FeaturesLo.CLFSH = cpuFeatureList->CLFSH;
+  CpuF10Features->CpuF10FeaturesLo.CMOV = cpuFeatureList->CMOV;
+  CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B;
+  CpuF10Features->CpuF10FeaturesLo.DE = cpuFeatureList->DE;
+  CpuF10Features->CpuF10FeaturesLo.FPU = cpuFeatureList->FPU;
+  CpuF10Features->CpuF10FeaturesLo.FXSR = cpuFeatureList->FXSR;
+  CpuF10Features->CpuF10FeaturesLo.HTT = cpuFeatureList->HTT;
+  CpuF10Features->CpuF10FeaturesLo.MCA = cpuFeatureList->MCA;
+  CpuF10Features->CpuF10FeaturesLo.MCE = cpuFeatureList->MCE;
+  CpuF10Features->CpuF10FeaturesLo.MMX = cpuFeatureList->MMX;
+  CpuF10Features->CpuF10FeaturesLo.MSR = cpuFeatureList->MSR;
+  CpuF10Features->CpuF10FeaturesLo.MTRR = cpuFeatureList->MTRR;
+  CpuF10Features->CpuF10FeaturesLo.PAE = cpuFeatureList->PAE;
+  CpuF10Features->CpuF10FeaturesLo.PAT = cpuFeatureList->PAT;
+  CpuF10Features->CpuF10FeaturesLo.PGE = cpuFeatureList->PGE;
+  CpuF10Features->CpuF10FeaturesLo.PSE = cpuFeatureList->PSE;
+  CpuF10Features->CpuF10FeaturesLo.PSE36 = cpuFeatureList->PSE36;
+  CpuF10Features->CpuF10FeaturesLo.SSE = cpuFeatureList->SSE;
+  CpuF10Features->CpuF10FeaturesLo.SSE2 = cpuFeatureList->SSE2;
+  CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit = cpuFeatureList->SysEnterSysExit;
+  CpuF10Features->CpuF10FeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter;
+  CpuF10Features->CpuF10FeaturesLo.VME = cpuFeatureList->VME;
+
+  CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B = cpuFeatureList->CMPXCHG16B;
+  CpuF10Features->CpuF10FeaturesHi.Monitor = cpuFeatureList->Monitor;
+  CpuF10Features->CpuF10FeaturesHi.POPCNT = cpuFeatureList->POPCNT;
+  CpuF10Features->CpuF10FeaturesHi.SSE3 = cpuFeatureList->SSE3;
+
+  LibAmdMsrWrite (MSR_CPUID_FEATS, &CpuMsrData, StdHeader);
+
+  CpuMsrData = 0;
+  CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData;
+
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow = cpuFeatureList->ThreeDNow;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt = cpuFeatureList->ThreeDNowExt;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC = cpuFeatureList->APIC;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV = cpuFeatureList->CMOV;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE = cpuFeatureList->DE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR = cpuFeatureList->FFXSR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU = cpuFeatureList->FPU;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR = cpuFeatureList->FXSR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM = cpuFeatureList->LM;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA = cpuFeatureList->MCA;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE = cpuFeatureList->MCE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX = cpuFeatureList->MMX;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt = cpuFeatureList->MmxExt;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR = cpuFeatureList->MSR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR = cpuFeatureList->MTRR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX = cpuFeatureList->NX;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE = cpuFeatureList->PAE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB = cpuFeatureList->Page1GB;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT = cpuFeatureList->PAT;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE = cpuFeatureList->PGE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE = cpuFeatureList->PSE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36 = cpuFeatureList->PSE36;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP = cpuFeatureList->RDTSCP;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet = cpuFeatureList->SysCallSysRet;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME = cpuFeatureList->VME;
+
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch = cpuFeatureList->ThreeDNowPrefetch;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM = cpuFeatureList->ABM;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8 = cpuFeatureList->AltMovCr8;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy = cpuFeatureList->CmpLegacy;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace = cpuFeatureList->ExtApicSpace;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS = cpuFeatureList->IBS;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf = cpuFeatureList->LahfSahf;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse = cpuFeatureList->MisAlignSse;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM = cpuFeatureList->OSVW;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT = cpuFeatureList->SKINIT;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A = cpuFeatureList->SSE4A;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM = cpuFeatureList->SVM;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT = cpuFeatureList->WDT;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId = cpuFeatureList->NodeId;
+  LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  cpuFeatureListNeedUpdate
+ *
+ *    Compare global CPU feature list with this core feature list to see if global CPU feature list
+ *    needs updated.
+ *
+ *    @param[in]  globalCpuFeatureList  - Pointer to global CPU Feature List.
+ *    @param[in]  thisCoreCpuFeatureList  - Pointer to this core CPU Feature List.
+ *
+ *    @retval FALSE  globalCpuFeatureList is equal to thisCoreCpuFeatureList
+ *    @retval True  globalCpuFeatureList is NOT equal to thisCoreCpuFeatureList
+ */
+BOOLEAN
+STATIC
+cpuFeatureListNeedUpdate (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  )
+{
+  BOOLEAN flag;
+  UINT8 *global;
+  UINT8 *thisCore;
+  UINT8 i;
+
+  flag = FALSE;
+  global = (UINT8 *) globalCpuFeatureList;
+  thisCore = (UINT8 *) thisCoreCpuFeatureList;
+
+  for (i = 0; i < sizeof (CPU_FEATURES_LIST); i++) {
+    if ((*global) != (*thisCore)) {
+      flag = TRUE;
+      break;
+    }
+    global++;
+    thisCore++;
+  }
+  return flag;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  updateCpuFeatureList
+ *
+ *    Update global CPU feature list
+ *
+ *    @param[in]  globalCpuFeatureList  - Pointer to global CPU Feature List.
+ *    @param[in]  thisCoreCpuFeatureList  - Pointer to this core CPU Feature List.
+ *
+ */
+VOID
+STATIC
+updateCpuFeatureList (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  )
+{
+  UINT8 *globalFeatureList;
+  UINT8 *thisCoreFeatureList;
+  UINT32 sizeInByte;
+
+  globalFeatureList = (UINT8 *) globalCpuFeatureList;
+  thisCoreFeatureList = (UINT8 *) thisCoreCpuFeatureList;
+
+  for (sizeInByte = 0; sizeInByte < sizeof (CPU_FEATURES_LIST); sizeInByte++) {
+    *globalFeatureList &= *thisCoreFeatureList;
+    globalFeatureList++;
+    thisCoreFeatureList++;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h
new file mode 100755
index 0000000000..6d27821b8d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific feature leveling functions.
+ *
+ * Provides feature leveling functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_FEATURE_LEVELING_H_
+#define _CPU_F10_FEATURE_LEVELING_H_
+
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// F10 CPU Feature Low
+typedef struct {
+  UINT32 FPU:1;               ///< Bit0
+  UINT32 VME:1;               ///< Bit1
+  UINT32 DE:1;                ///< Bit2
+  UINT32 PSE:1;               ///< Bit3
+  UINT32 TimeStampCounter:1;  ///< Bit4
+  UINT32 MSR:1;               ///< Bit5
+  UINT32 PAE:1;               ///< Bit6
+  UINT32 MCE:1;               ///< Bit7
+  UINT32 CMPXCHG8B:1;         ///< Bit8
+  UINT32 APIC:1;              ///< Bit9
+  UINT32 Reserved1:1;         ///< Bit10
+  UINT32 SysEnterSysExit:1;   ///< Bit11
+  UINT32 MTRR:1;              ///< Bit12
+  UINT32 PGE:1;               ///< Bit13
+  UINT32 MCA:1;               ///< Bit14
+  UINT32 CMOV:1;              ///< Bit15
+  UINT32 PAT:1;               ///< Bit16
+  UINT32 PSE36:1;             ///< Bit17
+  UINT32 Reserved2:1;         ///< Bit18
+  UINT32 CLFSH:1;             ///< Bit19
+  UINT32 Reserved3:3;         ///< Bit20~22
+  UINT32 MMX:1;               ///< Bit23
+  UINT32 FXSR:1;              ///< Bit24
+  UINT32 SSE:1;               ///< Bit25
+  UINT32 SSE2:1;              ///< Bit26
+  UINT32 Reserved4:1;         ///< Bit27
+  UINT32 HTT:1;               ///< Bit28
+  UINT32 Reserved5:3;         ///< Bit29~31
+} CPU_F10_FEATURES_LO;
+
+/// F10 CPU Feature High
+typedef struct {
+  UINT32 SSE3:1;            ///< Bit0
+  UINT32 Reserved1:2;       ///< Bit1~2
+  UINT32 Monitor:1;         ///< Bit3
+  UINT32 Reserved2:9;       ///< Bit4~12
+  UINT32 CMPXCHG16B:1;      ///< Bit13
+  UINT32 Reserved3:9;       ///< Bit14~22
+  UINT32 POPCNT:1;          ///< Bit23
+  UINT32 Reserved4:8;       ///< Bit24~31
+} CPU_F10_FEATURES_HI;
+
+/// F10 CPU Feature
+typedef struct {
+  CPU_F10_FEATURES_LO CpuF10FeaturesLo; ///< Low
+  CPU_F10_FEATURES_HI CpuF10FeaturesHi; ///< High
+} CPU_F10_FEATURES;
+
+/// F10 CPU Extended Feature Low
+typedef struct {
+  UINT32 FPU:1;               ///< Bit0
+  UINT32 VME:1;               ///< Bit1
+  UINT32 DE:1;                ///< Bit2
+  UINT32 PSE:1;               ///< Bit3
+  UINT32 TimeStampCounter:1;  ///< Bit4
+  UINT32 MSR:1;               ///< Bit5
+  UINT32 PAE:1;               ///< Bit6
+  UINT32 MCE:1;               ///< Bit7
+  UINT32 CMPXCHG8B:1;         ///< Bit8
+  UINT32 APIC:1;              ///< Bit9
+  UINT32 Reserved1:1;         ///< Bit10
+  UINT32 SysCallSysRet:1;     ///< Bit11
+  UINT32 MTRR:1;              ///< Bit12
+  UINT32 PGE:1;               ///< Bit13
+  UINT32 MCA:1;               ///< Bit14
+  UINT32 CMOV:1;              ///< Bit15
+  UINT32 PAT:1;               ///< Bit16
+  UINT32 PSE36:1;             ///< Bit17
+  UINT32 Reserved2:2;         ///< Bit18~19
+  UINT32 NX:1;                ///< Bit20
+  UINT32 Reserved3:1;         ///< Bit21
+  UINT32 MmxExt:1;            ///< Bit22
+  UINT32 MMX:1;               ///< Bit23
+  UINT32 FXSR:1;              ///< Bit24
+  UINT32 FFXSR:1;             ///< Bit25
+  UINT32 Page1GB:1;           ///< Bit26
+  UINT32 RDTSCP:1;            ///< Bit27
+  UINT32 Reserved4:1;         ///< Bit28
+  UINT32 LM:1;                ///< Bit29
+  UINT32 ThreeDNowExt:1;      ///< Bit30
+  UINT32 ThreeDNow:1;         ///< Bit31
+} CPU_F10_EXT_FEATURES_LO;
+
+/// F10 CPU Extended Feature High
+typedef struct {
+  UINT32 LahfSahf:1;        ///< Bit0
+  UINT32 CmpLegacy:1;       ///< Bit1
+  UINT32 SVM:1;             ///< Bit2
+  UINT32 ExtApicSpace:1;    ///< Bit3
+  UINT32 AltMovCr8:1;       ///< Bit4
+  UINT32 ABM:1;             ///< Bit5
+  UINT32 SSE4A:1;           ///< Bit6
+  UINT32 MisAlignSse:1;     ///< Bit7
+  UINT32 ThreeDNowPrefetch:1; ///< Bit8
+  UINT32 OSVM:1;            ///< Bit9
+  UINT32 IBS:1;             ///< Bit10
+  UINT32 Reserved1:1;       ///< Bit11
+  UINT32 SKINIT:1;          ///< Bit12
+  UINT32 WDT:1;             ///< Bit13
+  UINT32 Reserved2:5;       ///< Bit14~18
+  UINT32 NodeId:1;          ///< Bit19
+  UINT32 Reserved3:12;      ///< Bit20~31
+} CPU_F10_EXT_FEATURES_HI;
+
+/// F10 CPU Extended Feature
+typedef struct {
+  CPU_F10_EXT_FEATURES_LO CpuF10ExtFeaturesLo;  ///< Low
+  CPU_F10_EXT_FEATURES_HI CpuF10ExtFeaturesHi;  ///< High
+} CPU_F10_EXT_FEATURES;
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10SaveFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10WriteFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _CPU_F10_FEATURE_LEVELING_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
new file mode 100755
index 0000000000..ecf85c12e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
@@ -0,0 +1,747 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DR PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   P C I   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HtPhyRegisters[] =
+{
+// 0xCF
+// HT_PHY_HT1_FIFO_PTR_OPT_VALUE
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xCF,                                 // Address
+      0x0000006D,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// HT_PHY_HT1_FIFO_PTR_OPT_VALUE
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xDF,                                 // Address
+      0x0000006D,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xD1
+// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD1,                                 // Address
+      0x08040000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+// 0xC1
+// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC1,                                 // Address
+      0x08040000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+// 0xD1
+// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xD1,                                 // Address
+      0x04020000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+// 0xC1
+// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xC1,                                 // Address
+      0x04020000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+//
+// Deemphasis Settings
+//
+
+// HT1: clear any warm reset deemphasis settings.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xC5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xD5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xC4,                                 // Address
+      0x00000000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xD4,                                 // Address
+      0x00000000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0640,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0640,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0D40,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0D40,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F0647,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F0647,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+
+// Far-device deemphasis setting DCV[15:10]
+// No deemphasis                 20h
+// -2dB postcursor               19h
+// -3dB postcursor               17h
+// -5dB postcursor               11h
+// -6dB postcursor               10h
+// -7dB postcursor               0Eh
+// -8dB postcursor               0Dh
+// -9dB postcursor               0Bh
+// -11dB postcursor              09h
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00008000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00008000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__2,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00006400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__2,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00006400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00005C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00005C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__5,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00004400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__5,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00004400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00004000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00004000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__7,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00003800,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__7,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00003800,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00003400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00003400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__9,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00002C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__9,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00002C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00002400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00002400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+
+};
+
+CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10HtPhyRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
new file mode 100755
index 0000000000..29840c8185
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
@@ -0,0 +1,270 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DR, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10MsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_TOM2 (0xC001001D)
+// bits[63:0] - TOP_MEM2 = 0
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_TOM2,                              // MSR Address
+      0x0000000000000000ull,                    // OR Mask
+      0xFFFFFFFFFFFFFFFFull,                    // NAND Mask
+    }}
+  },
+// MSR_SYS_CFG (0xC0010010)
+// bit[21] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_SYS_CFG,                           // MSR Address
+      (1 << 21),                             // OR Mask
+      (1 << 21),                             // NAND Mask
+    }}
+  },
+// MSR_HWCR (0xC0010015)
+// Do not set bit[24] = 1, it will be set in AmdInitPost.
+// bit[4] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_HWCR,                              // MSR Address
+      0x0000000000000010ull,                    // OR Mask
+      0x0000000000000010ull,                    // NAND Mask
+    }}
+  },
+// MSR_MC4_CTL_MASK (0xC0010048)
+// bit[10] = 1
+// bits[22:19] = 1111b
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_MC4_CTL_MASK,                      // MSR Address
+      0x0000000000780400ull,                    // OR Mask
+      0x0000000000780400ull,                    // NAND Mask
+    }}
+  },
+// MSR_DC_CFG (0xC0011022)
+// bits[35:34] = 01
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_MULTI_LINK},                     // platformFeatures
+    {{
+      MSR_DC_CFG,                            // MSR Address
+      0x0000000400000000ull,                    // OR Mask
+      0x0000000C00000000ull,                    // NAND Mask
+    }}
+  },
+// MSR_NB_CFG (0xC001001F)
+// bit[54] = 1
+// bit[52:51] = 11b for Erratum #372
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},   // platformFeatures
+    {{
+      MSR_NB_CFG,                            // MSR Address
+      0x0058000000000000ull,                    // OR Mask
+      0x0058000000000000ull,                    // NAND Mask
+    }}
+  },
+// MSR_DC_CFG (0xC0011022)
+// bit[24] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_DC_CFG,                            // MSR Address
+      (1 << 24),                             // OR Mask
+      (1 << 24),                             // NAND Mask
+    }}
+  },
+// MSR_CPUID_FEATS (0xC0011004)
+// bit[28] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_MULTI_CORE | AMD_PF_DUAL_CORE)},  // platformFeatures
+    {{
+      MSR_CPUID_FEATS,                       // MSR Address
+      (1 << 28),                             // OR Mask
+      (1 << 28),                             // NAND Mask
+    }}
+  },
+// MSR_CPUID_EXT_FEATS (0xC0011005)
+// bit[33] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_DUAL_CORE},                     // platformFeatures
+    {{
+      MSR_CPUID_EXT_FEATS,                   // MSR Address
+      0x0000000200000000ull,                    // OR Mask
+      0x0000000200000000ull,                    // NAND Mask
+    }}
+  },
+// MSR_OSVW_ID_Length (0xC0010140)
+// bit[15:0] = 4
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_OSVW_ID_Length,                    // MSR Address
+      0x0000000000000004ull,                    // OR Mask
+      0x000000000000FFFFull,                    // NAND Mask
+    }}
+  },
+// MSR_OSVW_Status (0xC0010141)
+// bit[3] = 1 for Erratum #383
+// bit[2] = 1 for Erratum #415
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_OSVW_Status,                       // MSR Address
+      0x000000000000000Cull,                    // OR Mask
+      0x000000000000000Cull,                    // NAND Mask
+    }}
+  },
+// This MSR should be set after the code that most errata would be applied in
+// MSR_MC0_CTL (0x00000400)
+// bits[63:0]  = 0xFFFFFFFFFFFFFFFF
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_MC0_CTL,                           // MSR Address
+      0xFFFFFFFFFFFFFFFFull,                    // OR Mask
+      0xFFFFFFFFFFFFFFFFull,                    // NAND Mask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
+  AllCores,
+  (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PciTables.c
new file mode 100755
index 0000000000..a977be06d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PciTables.c
@@ -0,0 +1,768 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DR PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PciRegisters[] =
+{
+// Function 0 - HT Config
+
+// F0x68 - Link Transaction Control
+// bit[11]   , RespPassPW = 1
+// bit[19:17], for 8bit APIC config
+// bit[22:21], DsNpReqLmt = 10h
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x004E0800,                           // regData
+      0x006E0800,                           // regMask
+    }}
+  },
+// F0x68 - Link Transaction Control
+// For uni-processor systems (that is, single link package processors), single core, and no L3:
+// [10, DisFillP] = 1b
+// [3, DisWrDwP] = 1b
+// [2, DisWrBP] = 1b
+// [1, DisRdDwP] = 1b
+// [0, DisRdBP] = 1b
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_SINGLE_CORE | AMD_PF_SINGLE_LINK)},   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x0000040F,                           // regData
+      0x0000040F,                           // regMask
+    }}
+  },
+// F0x[E4,C4,A4,84] - Link 0 Control Register
+// bit[13] LdtStopTriEn = 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x04,                                 // Address
+      0x00002000,                           // regData
+      0x00002000,                           // regMask
+    }}
+  },
+// F0x[E4,C4,A4,84] - Link 0 Control Register
+// bit [12] IsocEn = 0 default
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_NFCM | AMD_PF_UMA)},         // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x04,                                 // Address
+      0x00000000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+// F0x[E4,C4,A4,84] - Link 0 Control Register
+// bit [12] IsocEn = 1 for Isochronous control flow modes.
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU)}, // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x04,                                 // Address
+      0x00001000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+// F0x[F0,D0,B0,90] - Link Base Channel Buffer Count
+// bit[31] LockBc = 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x10,                                 // Address
+      0x80000000,                           // regData
+      0x80000000,                           // regMask
+    }}
+  },
+// F0x150 - Link Global Retry Control Register
+// bit[18:16] TotalRetryAttempts = 7
+// bit[13] HtRetryCrcDatInsDynEn = 1
+// bit[12]HtRetryCrcCmdPackDynEn = 1
+// bit[11:9] HtRetryCrcDatIns = 4
+// bit[8] HtRetryCrcCmdPack = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
+      0x00073900,                           // regData
+      0x00073F00,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[5:0] T0Time = 0x26
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C026,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[22:17] FullT0Time = 0x33
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                          // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00660000,                           // regData
+      0x007E0000,                           // regMask
+    }}
+  },
+
+// Function 1 - Map Init
+
+// Before reading F1x114_x2 or F1x114_x3 software must initialize
+// the registers or NB Array MCA errors may occur.  BIOS should
+// initialize index 0h of F1x114_x2 and F1x114_x3 to prevent reads
+// from F1x114 from generating NB Array MCA errors.
+// BKDG Doc #3116 Rev 1.07
+
+// F1x110 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
+      0x20000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F1x114 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
+      0x00000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F1x110 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
+      0x30000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F1x114 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
+      0x00000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+
+// F2x1B0 - Extended Memory Controller Configuration Low
+// bits[10:8], CohPrefPrbLmt = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0),  // Address
+      0x00000100,                           // regData
+      0x00000700,                           // regMask
+    }}
+  },
+
+// Function 3 - Misc. Control
+// F3x40 - MCA NB Control
+//
+// bit[8], MstrAbrtEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40),  // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F3x44 - MCA NB Configuration
+// bit[30]  SyncOnDramAdrParErrEn = 1
+// bit[27]  NB MCA to CPU0 Enable = 1
+// bit[25]  DisPciCfgCpuErrRsp = 1
+// bit[21]  SyncOnErr = 1
+// bit[20]  SyncOnWDTEn = 1
+// bit[6]   CpuErrDis = 1
+// bit[4]   SyncPktPropDis = 1
+// bit[3]   SyncPktGenDis = 1
+// bit[2]   SyncOnUcEccEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
+      0x4A30005C,                           // regData
+      0x4A30005C,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+// ACPI State S1
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0xE6000000,                           // regData
+      0xFFFF0000,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }}
+  },
+// F3x84 - ACPI Power State Control
+// ACPI State S3
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+// ACPI State Throttling
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 2
+// ACPI State S4/S5
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+// ACPI State C1
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 5
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
+      0x01E641E6,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F3x84 - ACPI Power State Control
+// ACPI State C1
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_SINGLE_CORE},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
+      0x80000000,                           // regData
+      0xFF000000,                           // regMask
+    }}
+  },
+// F3x8C - NB Configuration High
+// Errata 373, bits[25] DisFastTprWr = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
+      0x02000000,                           // regData
+      0x02000000,                           // regMask
+    }}
+  },
+// F3x8C - NB Configuration High
+// Must be cleared by BIOS
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platform Features
+    {{
+      PERFORMANCE_L3_CACHE,                 // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
+      0x00000000,                           // regData
+      0x02000000,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00000800,                           // regData
+      0x00003800,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00000200,                           // regData
+      0x00000200,                           // regMask
+    }}
+  },
+// F3xA4 - Reported Temperature Control
+// bits[12:8] PerStepTimeDn = 15
+// bits[7] TmpSlewDnEn = 1
+// bits[6:5] TmpMaxDiffUp = 3
+// bits[4:0] PerStepTimeUp = 15
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),  // Address
+      0x00000FEF,                           // regData
+      0x00001FFF,                           // regMask
+    }}
+  },
+// F3xD4 - Clock Power Timing Control 0
+// bits[11:8] ClkRampHystSel = 1
+// bits[30:28] NbClkDiv = 1
+// bits[31] NbClkDivApplyAll = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0xC0010F00,                           // regData
+      0xF0030F00,                           // regMask
+    }}
+  },
+// F3xD8 - Clock Power Timing Control 1
+// bits[2:0] VSSlamTime = 6
+// bits[6:4] VSRampTime = 1
+// bits[26:24] ReConDel = 3
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8),  // Address
+      0x03000016,                           // regData
+      0x0F000077,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 6
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00006000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[18:16] CacheFlushOnHaltCtl = 0 to ensure AP cache stability at Early
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_Bx                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00000000,                           // regData
+      0x00070000,                           // regMask
+    }}
+  },
+// F3x180 - NB Extended Configuration
+// bits[1] SyncFloodOnUsPwDataErr = 1
+// bits[5] DisPciCfgCpuMstAbtRsp = 1
+// bits[6] SyncFloodOnDatErr = 1
+// bits[7] SyncFloodOnTgtAbtErr = 1
+// bits[8] SyncOnProtEn = 1
+// bits[9] SyncOnUncNbAryEn = 1
+// bits[20] SyncFloodOnL3LeakErr = 1
+// bits[21] SyncFloodOnCpuLeakErr = 1
+// bits[22] SyncFloodOnTblWalkErr = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x007003E2,                           // regData
+      0x007003E2,                           // regMask
+    }}
+  },
+// F3x188 - NB Extended Configuration Low Register
+// bits[4] EnStpGntOnFlushMaskWakeup = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00000010,                           // regData
+      0x00000010,                           // regMask
+    }}
+  },
+// F3x1A0 - L3 Buffer Count Register
+// bits[14:12]  L3ToSriReqCBC = 4, 4 or fewer cores with L3 cache is 4.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
+      0x00004000,                               // regData
+      0x00007000,                               // regMask
+    }}
+  },
+// F3x1A0 - L3 Buffer Count Register
+// bits[14:12]  L3ToSriReqCBC = 5, 5-core with L3 cache is 5.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
+      0x00005000,                               // regData
+      0x00007000,                               // regMask
+    }}
+  },
+// F3x1A0 - L3 Buffer Count Register
+// bits[14:12]  L3ToSriReqCBC = 6, 6-core with L3 cache is 6.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
+      0x00006000,                               // regData
+      0x00007000,                               // regMask
+    }}
+  },
+// F3x1B8 - L3 Control
+// bits[12] Must be set by BIOS.
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
+      0x00001000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+  // F4x1C4 - L3 Power Control Register
+  // bits[8] L3PwrSavEn = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,                 // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F3x1CC - IBS Control
+// bits[8] LvtOffsetVal = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10PciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10PciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
new file mode 100755
index 0000000000..67ef653d23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -0,0 +1,376 @@
+/**
+ * @file
+ *
+ * AMD Family_10 P-State power check
+ *
+ * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerCheck.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuF10Utilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10PmPwrCheckCore (
+  IN     VOID *ErrorData,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F10PmPwrChkCopyPstate (
+  IN     UINT8 Dest,
+  IN     UINT8 Src,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the family 10h Processor-
+ * Systemboard Power Delivery Check.
+ *
+ * The steps are as follows:
+ *    1. Starting with P0, loop through all P-states until a passing state is
+ *       found.  A passing state is one in which the current required by the
+ *       CPU is less than the maximum amount of current that the system can
+ *       provide to the CPU.  If P0 is under the limit, no further action is
+ *       necessary.
+ *    2. If at least one P-State is under the limit & at least one P-State is
+ *       over the limit, the BIOS must:
+ *       a. If the processor's current P-State is disabled by the power check,
+ *          then the BIOS must request a transition to an enabled P-state
+ *          using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
+ *          to reflect the new value.
+ *       b. Copy the contents of the enabled P-state MSRs to the highest
+ *          performance P-state locations.
+ *       c. Request a P-state transition to the P-state MSR containing the
+ *          COF/VID values currently applied.
+ *       d. Adjust the following P-state parameters affected by the P-state
+ *          MSR copy by subtracting the number of P-states that are disabled
+ *          by the power check.
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[StcPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *    3. If all P-States are over the limit, the BIOS must:
+ *       a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
+ *          write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
+ *          MSRC001_0063[CurPstate] to reflect the new value.
+ *       b. If F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
+ *          MSR pointed to by F3xDC[PstateMaxVal] to MSRC001_0064 and set
+ *          MSRC001_0064[PstateEn]
+ *       c. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
+ *          [CurPstate] to reflect the new value.
+ *       d. Adjust the following P-state parameters to zero:
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[StcPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8       DisPsNum;
+  UINT8       PsMaxVal;
+  UINT8       Pstate;
+  UINT32      ProcIddMax;
+  UINT32      PciRegister;
+  UINT32      Socket;
+  UINT32      Module;
+  UINT32      Core;
+  UINT32      AndMask;
+  UINT32      OrMask;
+  UINT32      PstateLimit;
+  PCI_ADDR    PciAddress;
+  UINT64      MsrRegister;
+  AP_TASK     TaskPtr;
+  AGESA_STATUS IgnoredSts;
+  PWRCHK_ERROR_DATA ErrorData;
+
+  // get the socket number
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  ErrorData.SocketNumber = (UINT8)Socket;
+
+  ASSERT (Core == 0);
+
+  // get the Max P-state value
+  for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+
+  ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
+
+  DisPsNum = 0;
+  for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
+    if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
+      if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties.CurrentLimit) {
+        // Add to event log the Pstate that exceeded the current limit
+        PutEventLog (AGESA_WARNING,
+                     CPU_EVENT_PM_PSTATE_OVERCURRENT,
+                     Socket, Pstate, 0, 0, StdHeader);
+        DisPsNum++;
+      } else {
+        break;
+      }
+    }
+  }
+
+  // If all P-state registers are disabled, move P[PsMaxVal] to P0
+  // and transition to P0, then wait for CurPstate = 0
+
+  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+
+  // We only need to log this event on the BSC
+  if (ErrorData.AllowablePstateNumber == 0) {
+    PutEventLog (AGESA_FATAL,
+                 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
+                 Socket, 0, 0, 0, StdHeader);
+  }
+
+  if (DisPsNum != 0) {
+    TaskPtr.FuncAddress.PfApTaskI = F10PmPwrCheckCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
+    TaskPtr.DataTransfer.DataPtr = &ErrorData;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
+
+    // Final Step
+    //    F3x64[HtPstatelimit] -= disPsNum
+    //    F3x68[StcPstateLimit]-= disPsNum
+    //    F3xDC[PstateMaxVal]-= disPsNum
+
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+
+    PciAddress.Address.Register = HTC_REG;
+    AndMask = 0xFFFFFFFF;
+    ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3x64
+    PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
+    if (PstateLimit > DisPsNum) {
+      PstateLimit -= DisPsNum;
+      ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
+
+    PciAddress.Address.Register = STC_REG;
+    AndMask = 0xFFFFFFFF;
+    ((STC_REGISTER *) &AndMask)->StcPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3x68
+    PstateLimit = ((STC_REGISTER *) &PciRegister)->StcPstateLimit;
+    if (PstateLimit > DisPsNum) {
+      PstateLimit -= DisPsNum;
+      ((STC_REGISTER *) &OrMask)->StcPstateLimit = PstateLimit;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
+
+    PciAddress.Address.Register = CPTC2_REG;
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xDC
+    PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
+    if (PstateLimit > DisPsNum) {
+      PstateLimit -= DisPsNum;
+      ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
+
+    // Now that P0 has changed, recalculate VSSlamTime
+    F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Core-level error handler called if any p-states were determined to be out
+ * of range for the mother board.
+ *
+ * This function implements steps 2a-c and 3a-c on each core.
+ *
+ * @param[in]  ErrorData            Details about the error condition.
+ * @param[in]  StdHeader            Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmPwrCheckCore (
+  IN       VOID *ErrorData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  i;
+  UINT8  PsMaxVal;
+  UINT8  DisPsNum;
+  UINT8  CurrentPs;
+  UINT64 MsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+  DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+             ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
+
+  LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
+  CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
+
+  if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+
+    // Step 1
+    // Transition to Pstate Max if not there already
+
+    if (CurrentPs != PsMaxVal) {
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
+    }
+
+
+    // Step 2
+    // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+    // to P0.
+
+    if (PsMaxVal != 0) {
+      F10PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+    }
+  } else {
+
+    // move remaining P-state register(s) up
+    // Step 1
+    // Transition to a valid Pstate if current Pstate has been disabled
+
+    if (CurrentPs < DisPsNum) {
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
+      CurrentPs = DisPsNum;
+    }
+
+    // Step 2
+    // Move enabled Pstates up and disable the remainder
+
+    for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
+      F10PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
+    }
+
+    // Step 3
+    // Transition to current COF/VID at shifted location
+
+    CurrentPs = (CurrentPs - DisPsNum);
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
+  }
+  i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
+  if (i == 0) {
+    ++i;
+  }
+  while (i <= PsMaxVal) {
+    FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
+    ++i;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copies the contents of one P-State MSR to another.
+ *
+ * @param[in]  Dest              Destination p-state number
+ * @param[in]  Src               Source p-state number
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+F10PmPwrChkCopyPstate (
+  IN       UINT8 Dest,
+  IN       UINT8 Src,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h
new file mode 100755
index 0000000000..a02e05a056
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_POWER_CHECK_H_
+#define _CPU_F10_POWER_CHECK_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Power Check Error Data
+typedef struct {
+  UINT8 SocketNumber;                 ///< Socket Number
+  UINT8 HwPstateNumber;               ///< Hardware P-state Number
+  UINT8 AllowablePstateNumber;        ///< Allowable P-state Number
+} PWRCHK_ERROR_DATA;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
new file mode 100755
index 0000000000..a3ce49a1cf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
@@ -0,0 +1,516 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Management related stuff
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPUF10POWERMGMT_H_
+#define _CPUF10POWERMGMT_H_
+
+/*
+ * Family 10h CPU Power Management MSR definitions
+ *
+ */
+
+/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */
+#define MSR_INTPEND 0xC0010055
+
+/// Interrupt Pending and CMP-Halt MSR Register
+typedef struct {
+  UINT64 IoMsgAddr:16;               ///< IO message address
+  UINT64 IoMsgData:8;                ///< IO message data
+  UINT64 IntrPndMsgDis:1;            ///< Interrupt pending message disable
+  UINT64 IntrPndMsg:1;               ///< Interrupt pending message
+  UINT64 IoRd:1;                     ///< IO read
+  UINT64 SmiOnCmpHalt:1;             ///< SMI on chip multi-processing halt
+  UINT64 C1eOnCmpHalt:1;             ///< C1E on chip multi-processing halt
+  UINT64 BmStsClrOnHltEn:1;          ///< Clear BM status bit on server C1e entry
+  UINT64 :34;                        ///< Reserved
+} INTPEND_MSR;
+
+
+/* P-state Current Limit Register 0xC0010061 */
+#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
+
+/// Pstate Current Limit MSR Register
+typedef struct {
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 :1;                         ///< Reserved
+  UINT64 PstateMaxVal:3;             ///< Pstate Max Value
+  UINT64 :57;                        ///< Reserved
+} PSTATE_CURLIM_MSR;
+
+
+/* P-state Control Register 0xC0010062 */
+#define MSR_PSTATE_CTL 0xC0010062
+
+/// Pstate Control MSR Register
+typedef struct {
+  UINT64 PstateCmd:3;                ///< Pstate change command
+  UINT64 :61;                        ///< Reserved
+} PSTATE_CTRL_MSR;
+
+
+/* P-state Status Register 0xC0010063 */
+#define MSR_PSTATE_STS 0xC0010063
+
+/// Pstate Status MSR Register
+typedef struct {
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :61;                        ///< Reserved
+} PSTATE_STS_MSR;
+
+
+/* P-state Registers 0xC001006[8:4] */
+#define MSR_PSTATE_0 0xC0010064
+#define MSR_PSTATE_1 0xC0010065
+#define MSR_PSTATE_2 0xC0010066
+#define MSR_PSTATE_3 0xC0010067
+#define MSR_PSTATE_4 0xC0010068
+
+#define PS_REG_BASE MSR_PSTATE_0     /* P-state Register base */
+#define PS_MAX_REG  MSR_PSTATE_4     /* Maximum P-State Register */
+#define PS_MIN_REG  MSR_PSTATE_0     /* Minimum P-State Register */
+#define NM_PS_REG 5                  /* number of P-state MSR registers */
+
+/// Pstate MSR
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid:7;                   ///< CpuVid
+  UINT64 :6;                         ///< Reserved
+  UINT64 NbDid:1;                    ///< NbDid
+  UINT64 :2;                         ///< Reserved
+  UINT64 NbVid:7;                    ///< NbVid
+  UINT64 IddValue:8;                 ///< IddValue
+  UINT64 IddDiv:2;                   ///< IddDiv
+  UINT64 :21;                        ///< Reserved
+  UINT64 PsEnable:1;                 ///< Pstate Enable
+} PSTATE_MSR;
+
+
+/* COFVID Control Register 0xC0010070 */
+#define MSR_COFVID_CTL 0xC0010070
+
+/// COFVID Control MSR Register
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid:7;                   ///< CpuVid
+  UINT64 PstateId:3;                 ///< Pstate ID
+  UINT64 :3;                         ///< Reserved
+  UINT64 NbDid:1;                    ///< NbDid
+  UINT64 :2;                         ///< Reserved
+  UINT64 NbVid:7;                    ///< NbVid
+  UINT64 :32;                        ///< Reserved
+} COFVID_CTRL_MSR;
+
+
+/* COFVID Status Register 0xC0010071 */
+#define MSR_COFVID_STS 0xC0010071
+
+/// COFVID Status MSR Register
+typedef struct {
+  UINT64 CurCpuFid:6;                ///< Current CpuFid
+  UINT64 CurCpuDid:3;                ///< Current CpuDid
+  UINT64 CurCpuVid:7;                ///< Current CpuVid
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :3;                         ///< Reserved
+  UINT64 CurNbDid:1;                 ///< Current NbDid
+  UINT64 :2;                         ///< Reserved
+  UINT64 CurNbVid:7;                 ///< Current NbVid
+  UINT64 StartupPstate:3;            ///< Startup Pstate
+  UINT64 MaxVid:7;                   ///< MaxVid
+  UINT64 MinVid:7;                   ///< MinVid
+  UINT64 MaxCpuCof:6;                ///< MaxCpuCof
+  UINT64 :1;                         ///< Reserved
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 MaxNbFid:5;                 ///< MaxNbFid
+} COFVID_STS_MSR;
+
+
+/*
+ * Family 10h CPU Power Management PCI definitions
+ *
+ */
+
+/* DRAM Configuration High Register F2x[1,0]94 */
+#define DRAM_CFG_HI_REG0 0x94
+#define DRAM_CFG_HI_REG1 0x194
+
+/// DRAM Configuration High PCI Register
+typedef struct {
+  UINT32 MemClkFreq:3;               ///< Memory clock frequency
+  UINT32 MemClkFreqVal:1;            ///< Memory clock frequency valid
+  UINT32 :4;                         ///< Reserved
+  UINT32 Ddr3Mode:1;                 ///< DDR3 mode
+  UINT32 LegacyBiosMode:1;           ///< Legacy BIOS mode
+  UINT32 ZqcsInterval:2;             ///< ZQ calibration short interval
+  UINT32 RDqsEn:1;                   ///< Read DQS enable
+  UINT32 DisSimulRdWr:1;             ///< Disable simultaneous read and write
+  UINT32 DisDramInterface:1;         ///< Disable the DRAM interface
+  UINT32 PowerDownEn:1;              ///< Power down mode enable
+  UINT32 PowerDownMode:1;            ///< Power down mode
+  UINT32 :1;                         ///< Reserved
+  UINT32 FourRankRDimm:1;            ///< Four rank registered DIMM connected
+  UINT32 DcqArbBypassEn:1;           ///< DRAM controller arbiter bypass enable
+  UINT32 SlowAccessMode:1;           ///< Slow access mode
+  UINT32 FreqChgInProg:1;            ///< Frequency change in progress
+  UINT32 BankSwizzleMode:1;          ///< Bank swizzle mode
+  UINT32 ProcOdtDis:1;               ///< Processor on-die termination disable
+  UINT32 DcqBypassMax:4;             ///< DRAM controller queue bypass maximum
+  UINT32 FourActWindow:4;            ///< Four bank activate window
+} DRAM_CFG_HI_REGISTER;
+
+
+/* Extended Memory Controller Configuration Low Register F2x1B0 */
+#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0
+
+/// Extended Memory Controller Configuration Low PCI Register
+typedef struct {
+  UINT32 AdapPrefMissRatio:2;        ///< Adaptive prefetch miss ratio
+  UINT32 AdapPrefPositiveStep:2;     ///< Adaptive prefetch positive step
+  UINT32 AdapPrefNegativeStep:2;     ///< Adaptive prefetch negative step
+  UINT32 :2;                         ///< Reserved
+  UINT32 CohPrefPrbLmt:3;            ///< Coherent prefetch probe limit
+  UINT32 DisIoCohPref:1;             ///< Disable coherent prefetched for IO
+  UINT32 EnSplitDctLimits:1;         ///< Split DCT write limits enable
+  UINT32 SpecPrefDis:1;              ///< Speculative prefetch disable
+  UINT32 SpecPrefMis:1;              ///< Speculative prefetch predict miss
+  UINT32 SpecPrefThreshold:3;        ///< Speculative prefetch threshold
+  UINT32 :4;                         ///< Reserved
+  UINT32 PrefFourConf:3;             ///< Prefetch four-ahead confidence
+  UINT32 PrefFiveConf:3;             ///< Prefetch five-ahead confidence
+  UINT32 DcqBwThrotWm:4;             ///< Dcq bandwidth throttle watermark
+} EXT_MEMCTRL_CFG_LOW_REGISTER;
+
+
+/* Scrub Rate Control Register F3x58 */
+#define SCRUB_RATE_CTRL_REG 0x58
+
+/// Scrub Rate Control PCI Register
+typedef struct {
+  UINT32 DramScrub:5;                ///< DRAM scrub rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 L2Scrub:5;                  ///< L2 cache scrub rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 DcacheScrub:5;              ///< Data cache scrub rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 L3Scrub:5;                  ///< L3 cache scrub rate
+  UINT32 :3;                         ///< Reserved
+} SCRUB_RATE_CTRL_REGISTER;
+
+/* DRAM Scrub Address Low Register F3x5C */
+#define DRAM_SCRUB_ADDR_LOW_REG 0x5C
+
+/// DRAM Scrub Address Low PCI Register
+typedef struct {
+  UINT32 ScrubReDirEn:1;             ///< DRAM scrubber redirect enable
+  UINT32 :5;                         ///< Reserved
+  UINT32 ScrubAddrLo:26;             ///< DRAM scrubber address bits[31:6]
+} DRAM_SCRUB_ADDR_LOW_REGISTER;
+
+
+/* Hardware thermal control register F3x64 */
+#define HTC_REG 0x64
+
+/// Hardware Thermal Control PCI Register
+typedef struct {
+  UINT32 HtcEn:1;                    ///< HTC Enable
+  UINT32 :3;                         ///< Reserved
+  UINT32 HtcAct:1;                   ///< HTC Active State
+  UINT32 HtcActSts:1;                ///< HTC Active Status
+  UINT32 PslApicHiEn:1;              ///< P-state limit higher APIC int enable
+  UINT32 PslApicLoEn:1;              ///< P-state limit lower APIC int enable
+  UINT32 :8;                         ///< Reserved
+  UINT32 HtcTmpLmt:7;                ///< HTC temperature limit
+  UINT32 HtcSlewSel:1;               ///< HTC slew-controlled temp select
+  UINT32 HtcHystLmt:4;               ///< HTC hysteresis
+  UINT32 HtcPstateLimit:3;           ///< HTC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} HTC_REGISTER;
+
+
+/* Software thermal control register F3x68 */
+#define STC_REG 0x68
+
+/// Software Thermal Control PCI Register
+typedef struct {
+  UINT32 StcSbcTmpHiEn:1;            ///< STC SBC temperature high enable
+  UINT32 StcSbcTmpLoEn:1;            ///< STC SBC temperature low enable
+  UINT32 StcApcTmpHiEn:1;            ///< STC APIC temperature high enable
+  UINT32 StcApcTmpLoEn:1;            ///< STC APIC temperature low enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 StcPstateEn:1;              ///< STC P-state enable
+  UINT32 StcTmpHiSts:1;              ///< STC temperature high status
+  UINT32 StcTmpLoSts:1;              ///< STC temperature low status
+  UINT32 :8;                         ///< Reserved
+  UINT32 StcTmpLmt:7;                ///< STC temperature limit
+  UINT32 StcSlewSel:1;               ///< STC slew-controlled temp select
+  UINT32 StcHystLmt:4;               ///< STC hysteresis
+  UINT32 StcPstateLimit:3;           ///< STC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} STC_REGISTER;
+
+/* ACPI Power State Control Registers F3x84:80 */
+
+/// System Management Action Field (SMAF) Register
+typedef struct {
+  UINT8 CpuPrbEn:1;                  ///< CPU direct probe enable
+  UINT8 NbLowPwrEn:1;                ///< Northbridge low-power enable
+  UINT8 NbGateEn:1;                  ///< Northbridge gate enable
+  UINT8 :1;                          ///< Reserved
+  UINT8 AltVidEn:1;                  ///< alternate VID enable
+  UINT8 ClkDivisor:3;                ///< Clock divisor
+} SMAF_REGISTER;
+
+/// union type for ACPI State SMAF setting
+typedef union {
+  UINT8 SMAFValue;                   ///< SMAF raw value
+  SMAF_REGISTER SMAF;                ///< SMAF structure
+} ACPI_STATE_SMAF;
+
+/// ACPI Power State Control Register F3x80
+typedef struct {
+  ACPI_STATE_SMAF C2;                ///< [7:0]   SMAF Code 000b - C2
+  ACPI_STATE_SMAF C3C1eLinkInit;     ///< [15:8]  SMAF Code 001b - C3, C1e or Link init
+  ACPI_STATE_SMAF FidVidChg;         ///< [23:16] SMAF Code 010b - FIDVID Change
+  ACPI_STATE_SMAF S1;                ///< [31:24] SMAF Code 011b - S1
+} ACPI_PSC_0_REGISTER;
+
+/// ACPI Power State Control Register F3x84
+typedef struct {
+  ACPI_STATE_SMAF S3;                 ///< [7:0]   SMAF Code 100b - S3
+  ACPI_STATE_SMAF Throttling;         ///< [15:8]  SMAF Code 101b - Throttling
+  ACPI_STATE_SMAF S4S5;               ///< [23:16] SMAF Code 110b - S4/S5
+  ACPI_STATE_SMAF C1;                 ///< [31:24] SMAF Code 111b - C1
+} ACPI_PSC_4_REGISTER;
+
+
+/* Power Control Miscellaneous Register F3xA0 */
+#define PW_CTL_MISC_REG 0xA0
+
+/// Power Control Miscellaneous PCI Register
+typedef struct {
+  UINT32 PsiVid:7;                   ///< PSI_L VID threshold
+  UINT32 PsiVidEn:1;                 ///< PSI_L VID enable
+  UINT32 PviMode:1;                  ///< Parallel VID interface mode
+  UINT32 SviHighFreqSel:1;           ///< SVI high frequency select
+  UINT32 IdleExitEn:1;               ///< IDLEEXIT_L Enable
+  UINT32 PllLockTime:3;              ///< PLL synchronization lock time
+  UINT32 BpPinsTriEn:1;              ///< Breakpoint pins tristate enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 PstateId:12;                ///< Pstate ID
+  UINT32 :1;                         ///< Reserved
+  UINT32 SlamVidMode:1;              ///< Slam voltage ID mode
+  UINT32 :1;                         ///< Reserved
+  UINT32 CofVidProg:1;               ///< COF and VID of Pstate programmed
+} POWER_CTRL_MISC_REGISTER;
+
+/* Popup P-state Register F3xA8 */
+#define POPUP_PSTATE_REG 0xA8
+
+/// Popup P-state Register
+typedef struct {
+  UINT32 PopupEn:1;                  ///< Popup enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 PopupPstate:3;              ///< Popup P-state
+  UINT32 PopupCpuVid:7;              ///< Popup core VID
+  UINT32 PopupCpuFid:6;              ///< Popup core FID
+  UINT32 PopupCpuDid:3;              ///< Popup core DID
+  UINT32 :11;                        ///< Reserved
+} POPUP_PSTATE_REGISTER;
+
+/* Clock Power/Timing Control 0 Register F3xD4 */
+#define CPTC0_REG 0xD4
+
+/// Clock Power Timing Control PCI Register
+typedef struct {
+  UINT32 NbFid:5;                    ///< NbFid
+  UINT32 NbFidEn:1;                  ///< NbFidEn
+  UINT32 :2;                         ///< Reserved
+  UINT32 ClkRampHystSel:4;           ///< Clock Ramp Hysteresis Select
+  UINT32 ClkRampHystCtl:1;           ///< Clock Ramp Hysteresis Control
+  UINT32 MTC1eEn:1;                  ///< Message Triggered C1e Enable
+  UINT32 CacheFlushImmOnAllHalt:1;   ///< Cache Flush Immediate on All Halt
+  UINT32 StutterScrubEn:1;           ///< Stutter Mode Scrub Enable
+  UINT32 LnkPllLock:2;               ///< Link PLL Lock
+  UINT32 :2;                         ///< Reserved
+  UINT32 PowerStepDown:4;            ///< Power Step Down
+  UINT32 PowerStepUp:4;              ///< Power Step Up
+  UINT32 NbClkDiv:3;                 ///< NbClkDiv
+  UINT32 NbClkDivApplyAll:1;         ///< NbClkDivApplyAll
+} CLK_PWR_TIMING_CTRL_REGISTER;
+
+
+/* Clock Power/Timing Control 1 Register F3xD8 */
+#define CPTC1_REG 0xD8
+
+/// Clock Power Timing Control 1 PCI Register
+typedef struct {
+  UINT32 VSSlamTime:3;               ///< Voltage stabilization slam time
+  UINT32 :1;                         ///< Reserved
+  UINT32 VSRampTime:3;               ///< Voltage stabilization ramp time
+  UINT32 :1;                         ///< Reserved
+  UINT32 TdpVid:7;                   ///< Thermal design power VID
+  UINT32 :1;                         ///< Reserved
+  UINT32 AltVidStart:7;              ///< Alternate VID start limit
+  UINT32 :1;                         ///< Reserved
+  UINT32 ReConDel:4;                 ///< Link reconnect delay
+  UINT32 PwrPlanes:1;                ///< Power planes
+  UINT32 :3;                         ///< Reserved
+} CLK_PWR_TIMING_CTRL1_REGISTER;
+
+
+/* Clock Power/Timing Control 2 Register F3xDC */
+#define CPTC2_REG 0xDC
+
+/// Clock Power Timing Control 2 PCI Register
+typedef struct {
+  UINT32 AltVid:7;                   ///< Alternate VID
+  UINT32 :1;                         ///< Reserved
+  UINT32 PstateMaxVal:3;             ///< P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbsynPtrAdj:3;              ///< NB/Core sync FIFO ptr adjust
+  UINT32 :1;                         ///< Reserved
+  UINT32 CacheFlushOnHaltCtl:3;      ///< Cache flush on halt control
+  UINT32 CacheFlushOnHaltTmr:7;      ///< Cache flush on halt timer
+  UINT32 :1;                         ///< Reserved
+  UINT32 SlamTimeMode:2;             ///< Slam time mode
+  UINT32 AltvidVSSlamTime:3;         ///< Altvid voltage stabilization slam time
+} CLK_PWR_TIMING_CTRL2_REGISTER;
+
+
+/* Northbridge Capabilities Register F3xE8 */
+#define NB_CAPS_REG 0xE8
+
+/// Northbridge Capabilities PCI Register
+typedef struct {
+  UINT32 DctDualCap:1;               ///< Two-channel DRAM capable
+  UINT32 DualNodeCap:1;              ///< Dual-node multi-processor capable
+  UINT32 EightNodeCap:1;             ///< Eight-node multi-processor capable
+  UINT32 EccCapable:1;               ///< ECC capable
+  UINT32 ChipkillCapable:1;          ///< Chipkill ECC capable
+  UINT32 DdrMaxRate:3;               ///< Maximum DRAM data rate
+  UINT32 MctCap:1;                   ///< Memory controller capable
+  UINT32 SvmCapable:1;               ///< SVM capable
+  UINT32 HtcCapable:1;               ///< HTC capable
+  UINT32 LnkRtryCap:1;               ///< Link error-retry capable
+  UINT32 CmpCapLo:2;                 ///< CMP capable[1:0]
+  UINT32 MultiVidPlaneCap:1;         ///< Multiple VID plane capable
+  UINT32 CmpCapHi:1;                 ///< CMP capable[2]
+  UINT32 MpCap:3;                    ///< MP capability
+  UINT32 :1;                         ///< Reserved
+  UINT32 UnGangEn:4;                 ///< Link unganging enabled
+  UINT32 :1;                         ///< Reserved
+  UINT32 L3Capable:1;                ///< L3 capable
+  UINT32 HtAcCapable:1;              ///< HT AC capable
+  UINT32 :2;                         ///< Reserved
+  UINT32 MultiNodeCpu:1;             ///< Multinode processor
+  UINT32 IntNodeNum:2;               ///< Internal node number
+} NB_CAPS_REGISTER;
+
+
+/* NB Extended Configuration Low Register F3x188 */
+#define NB_EXT_CFG_LO_REG 0x188
+
+/// Northbridge Extended Configuration Low PCI Register
+typedef struct {
+  UINT32 :4;                         ///< Reserved
+  UINT32 EnStpGntOnFlushMaskWakeup:1; ///< Enable stop grant on flush mask wakeup
+  UINT32 :27;                        ///< Reserved
+} NB_EXT_CFG_LO_REGISTER;
+
+
+/* L3 Cache Parameter Register F3x1C4 */
+#define L3_CACHE_PARAM_REG 0x1C4
+
+/// L3 Cache Parameter PCI Register
+typedef struct {
+  UINT32 L3SubcacheSize0:1;          ///< L3 subcache size 0
+  UINT32 :3;                         ///< Reserved
+  UINT32 L3SubcacheSize1:1;          ///< L3 subcache size 1
+  UINT32 :3;                         ///< Reserved
+  UINT32 L3SubcacheSize2:2;          ///< L3 subcache size 2
+  UINT32 :2;                         ///< Reserved
+  UINT32 L3SubcacheSize3:2;          ///< L3 subcache size 3
+  UINT32 :17;                        ///< Reserved
+  UINT32 L3TagInit:1;                ///< L3 tag initialization
+} L3_CACHE_PARAM_REGISTER;
+
+
+/* Probe Filter Control Register F3x1D4 */
+#define PROBE_FILTER_CTRL_REG 0x1D4
+
+/// Probe Filter Control PCI Register
+typedef struct {
+  UINT32 PFMode:2;                   ///< Probe Filter Mode
+  UINT32 PFWayNum:2;                 ///< Probe Filter way number
+  UINT32 PFSubCacheSize0:2;          ///< Probe filter subcache 0 size
+  UINT32 PFSubCacheSize1:2;          ///< Probe filter subcache 1 size
+  UINT32 PFSubCacheSize2:2;          ///< Probe filter subcache 2 size
+  UINT32 PFSubCacheSize3:2;          ///< Probe filter subcache 3 size
+  UINT32 PFSubCacheEn:4;             ///< Probe filter subcache enable
+  UINT32 :3;                         ///< Reserved
+  UINT32 PFInitDone:1;               ///< Probe filter initialization done
+  UINT32 PFPreferredSORepl:2;        ///< PF preferredSO replacement mode
+  UINT32 PFErrInt:2;                 ///< Probe filter error interrupt type
+  UINT32 PFErrIntLvtOff:4;           ///< Probe filter error interrupt LVT offset
+  UINT32 PFEccError:1;               ///< Probe filter ECC error
+  UINT32 PFLoIndexHashEn:1;          ///< Probe filter low index hash enable
+  UINT32 :2;                         ///< Reserved
+} PROBE_FILTER_CTRL_REGISTER;
+
+
+/* Product Info Register F3x1FC */
+#define PRCT_INFO_REG 0x1FC
+
+/// Product Information PCI Register
+typedef struct {
+  UINT32 NbCofVidUpdate:1;           ///< NbCofVidUpdate
+  UINT32 NbVidUpdateAll:1;           ///< NbVidUpdateAll
+  UINT32 SinglePlaneNbFid:5;         ///< SinglePlaneNbFid
+  UINT32 SinglePlaneNbVid:7;         ///< SinglePlaneNbVid
+  UINT32 DualPlaneNbFidOff:3;        ///< DualPlaneNbFidOff
+  UINT32 DualPlaneNbVidOff:5;        ///< DualPlaneNbVidOff
+  UINT32 SinglePlaneNbIdd:4;         ///< SinglePlaneNbIdd
+} PRODUCT_INFO_REGISTER;
+
+
+#endif /* _CPUF10POWERMGMT_H */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
new file mode 100755
index 0000000000..b697720f4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
@@ -0,0 +1,164 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Management related stuff
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6410 $   @e \$Date: 2008-06-17 06:08:25 -0500 (Tue, 17 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "IdsF10AllService.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuF10EarlyInit.h"
+#include "cpuF10SoftwareThermal.h"
+#include "cpuF10PowerPlane.h"
+#include "cpuF10PowerCheck.h"
+#include "F10PmNbCofVidInit.h"
+#include "F10PmNbPstateInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10SysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*  Family 10h Only Table */
+/* ---------------------- */
+CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
+{
+  IDS_INITIAL_F10_PM_STEP
+
+  // Step 1 - Configure F3x[84:80].  Handled by PCI register table.
+  // Step 2 - Configure Northbridge COF and VID.
+  //   Execute both cold & warm
+  {
+    0,
+    F10PmNbCofVidInit
+  },
+
+  // Step 3 - Dual-plane Only Support.  Not required by any Arch2008 supported CPU.
+  // Step 4 - Configure Nb-Pstates.
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmNbPstateInit
+  },
+  // Step 5 - Power Plane Initialization
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F10CpuAmdPmPwrPlaneInit                           // Function Pointer
+  },
+
+  // Step 6 - Pmin Transition After Reset
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmAfterReset                             // Function Pointer
+  },
+
+  // Step 7 - Current Delivery Check
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmPwrCheck                               // Function Pointer
+  },
+
+  // Step x - Software Thermal Control Init
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmThermalInit                            // Function Pointer
+  },
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate table of steps to perform to initialize the power management
+ *  subsystem.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  SysPmTblPtr              Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10SysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10SysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
+  *SysPmTblPtr = CpuF10SysPmTableArray;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
new file mode 100755
index 0000000000..3ce6d5f4e1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -0,0 +1,469 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Plane Initialization
+ *
+ * Performs the "BIOS Requirements for Power Plane Initialization" as described
+ * in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "Table.h"
+#include "cpuF10PowerPlane.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Register encodings for F3xD4[PowerStepUp/PowerStepDown]
+CONST UINT16 ROMDATA PowerStepEncodings[16] =
+{
+  400,    // 0000b: 400ns
+  300,    // 0001b: 300ns
+  200,    // 0010b: 200ns
+  100,    // 0011b: 100ns
+  90,     // 0100b: 90ns
+  80,     // 0101b: 80ns
+  70,     // 0110b: 70ns
+  60,     // 0111b: 60ns
+  50,     // 1000b: 50ns
+  45,     // 1001b: 45ns
+  40,     // 1010b: 40ns
+  35,     // 1011b: 35ns
+  30,     // 1100b: 30ns
+  25,     // 1101b: 25ns
+  20,     // 1110b: 20ns
+  15      // 1111b: 15ns
+};
+
+// Register encodings for F3xDC[AltvidVSSlamTime]
+CONST UINT32 ROMDATA AltvidSlamTime[8] =
+{
+  0,    // 000b: <1us
+  10,   // 001b: 10us
+  20,   // 010b: 20us
+  40,   // 011b: 40us
+  50,   // 100b: 50us
+  70,   // 101b: 70us
+  80,   // 110b: 80us
+  90    // 111b: 90us
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10PmPwrPlaneInitPviCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+STATIC
+F10CalculateAltvidVSSlamTimeOnCore (
+  IN       BOOLEAN PviModeFlag,
+  IN       PCI_ADDR *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F10PmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing power plane initialization.
+ *
+ * The steps are as follows:
+ *    1. If single plane, program lower VID code of CpuVid & NbVid for all
+ *       enabled P-States.
+ *    2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on
+ *       platform requirements.
+ *    3. Configure F3xD4[PowerStepUp & PowerStepDown]
+ *    4. Optionally configure F3xA0[PsiVidEn & PsiVid]
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10CpuAmdPmPwrPlaneInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  BOOLEAN   PviModeFlag;
+  PCI_ADDR  PciAddress;
+  UINT16    PowerStepTime;
+  UINT32    PowerStepEncoded;
+  UINT32    PciRegister;
+  UINT32    VsSlamTime;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Core;
+  UINT32    NumOfCores;
+  UINT32    LowCore;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT64    MsrRegister;
+  AP_TASK   TaskPtr;
+  AGESA_STATUS  IgnoredSts;
+  PLATFORM_FEATS Features;
+  CPU_LOGICAL_ID LogicalId;
+
+  // Initialize the union
+  Features.PlatformValue = 0;
+  GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  ASSERT (Core == 0);
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+
+  // Set SlamVidMode
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = PW_CTL_MISC_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  AndMask = 0xFFFFFFFF;
+  OrMask = 0x00000000;
+  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
+    PviModeFlag = TRUE;
+    ((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;
+
+    // Have all single plane cores adjust their NB and CPU VID fields
+    TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
+
+  } else {
+    PviModeFlag = FALSE;
+    ((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;
+  }
+  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+  F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
+
+  // Configure PowerStepUp/PowerStepDown
+  PciAddress.Address.Register = CPTC0_REG;
+  if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||
+      (Features.PlatformFeatures.PlatformUma == 1) ||
+      (Features.PlatformFeatures.PlatformUmaIfcm == 1) ||
+      (Features.PlatformFeatures.PlatformIfcm == 1) ||
+      (Features.PlatformFeatures.PlatformIommu == 1)) {
+    PowerStepEncoded = 0x8;
+  } else {
+    GetGivenModuleCoreRange ((UINT32) Socket,
+                             (UINT32) Module,
+                             &LowCore,
+                             &NumOfCores,
+                             StdHeader);
+    NumOfCores = ((NumOfCores - LowCore) + 1);
+    PowerStepTime = (UINT16) (400 / NumOfCores);
+    for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {
+      if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {
+        break;
+      }
+    }
+  }
+  AndMask = 0xFFFFFFFF;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
+  OrMask = 0x00000000;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded;
+  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+  if ((LogicalId.Revision & AMD_F10_C3) != 0) {
+    // Set up Pop up P-state register
+    PciAddress.Address.Register = CPTC2_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    AndMask = 0xFFFFFFFF;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0;
+    OrMask = 0x00000000;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
+    LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
+    PciAddress.Address.Register = POPUP_PSTATE_REG;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+    // Set AltVidStart
+    PciAddress.Address.Register = CPTC1_REG;
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
+    OrMask = 0x00000000;
+    ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+    // Set up Altvid slam time
+    PciAddress.Address.Register = CPTC2_REG;
+    VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader);
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0;
+    OrMask = 0x00000000;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+  }
+
+  if (IsWarmReset (StdHeader) && !PviModeFlag) {
+    // Configure PsiVid
+    F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10CpuAmdPmPwrPlaneInit.
+ *
+ * This function implements step 1 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmPwrPlaneInitPviCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddr;
+  UINT32 NbVid;
+  UINT32 CpuVid;
+  UINT64 MsrRegister;
+
+  for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
+    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
+      NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+      CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+      if (NbVid != CpuVid) {
+        if (NbVid > CpuVid) {
+          NbVid = CpuVid;
+        }
+        ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
+        ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
+        LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the encoded altvid voltage stabilization slam time for the executing
+ * family 10h core.
+ *
+ * This function calculates how much time it will take for the voltage to
+ * stabilize when transitioning from altvid to Pmin, and returns the necessary
+ * encoded value for the amount of time discovered.
+ *
+ * @param[in]  PviModeFlag        Whether or not the platform uses VRMs that
+ *                                employ the parallel VID interface.
+ * @param[in]  PciAddress         Full PCI address of the executing core's config space.
+ * @param[in]  CpuEarlyParams     Service parameters
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ * @retval     Encoded register value.
+ *
+ */
+UINT32
+STATIC
+F10CalculateAltvidVSSlamTimeOnCore (
+  IN       BOOLEAN PviModeFlag,
+  IN       PCI_ADDR *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     NbVid;
+  UINT8     AltVidCode;
+  UINT8     PminVidCode;
+  UINT32    MsrAddr;
+  UINT32    PciRegister;
+  UINT64    MsrRegister;
+  PCI_ADDR  LocalPciAddress;
+
+  // Calculate Slam Time
+  //   VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vpmin - Altvid
+  //   In our case, we will scale the values by 100 to avoid
+  //   decimals.
+
+  // Get Pmin's index
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
+  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+
+  // Get Pmin's VID
+  LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+
+  // If SVI, we only care about CPU VID.
+  // If PVI, determine the higher voltage b/t NB and CPU
+  if (PviModeFlag) {
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    if (PminVidCode > NbVid) {
+      PminVidCode = NbVid;
+    }
+  }
+
+  // Get Alt VID
+  LocalPciAddress.AddressValue = PciAddress->AddressValue;
+  LocalPciAddress.Address.Function = FUNC_3;
+  LocalPciAddress.Address.Register = CPTC2_REG;
+  LibAmdPciRead (AccessWidth32, LocalPciAddress, &PciRegister, StdHeader);
+  AltVidCode = (UINT8) (((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->AltVid);
+
+  return (F10GetSlamTimeEncoding (PminVidCode, AltVidCode, CpuEarlyParams, AltvidSlamTime, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Sets up PSI_L operation.
+ *
+ * This function implements the LowPowerThreshold parameter.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Contains VrmLowPowerThreshold parameter.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Pstate;
+  UINT32    PstateCurrent;
+  UINT32    NextPstateCurrent;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT32    PreviousVID;
+  UINT32    PstateVID;
+  UINT64    PstateMsr;
+  UINT64    PstateLimitMsr;
+  BOOLEAN   EnablePsi;
+  PCI_ADDR  PciAddress;
+
+  if (CpuEarlyParams->PlatformConfig.VrmProperties.LowPowerThreshold != 0) {
+    EnablePsi = FALSE;
+    PreviousVID = 0x7F;           // Initialize to invalid zero volt VID code
+    PstateVID = 0x7F;
+    LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &PstateLimitMsr, StdHeader);
+
+    for (Pstate = 0; Pstate <= (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal; Pstate++) {
+      if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) {
+        LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
+        PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid);
+        if ((Pstate + 1) > (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal) {
+          NextPstateCurrent = 0;
+        } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) {
+          NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties.InrushCurrentLimit + NextPstateCurrent;
+        }
+        if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties.LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties.LowPowerThreshold) && (PstateVID != PreviousVID)) {
+          EnablePsi = TRUE;
+          break;
+        }
+        PreviousVID = PstateVID;
+      }
+    }
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    AndMask = 0xFFFFFFFF;
+    OrMask = 0x00000000;
+    ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0;
+    if (EnablePsi) {
+      ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID;
+      ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1;
+    } else {
+      ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h
new file mode 100755
index 0000000000..17c9777742
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Plane related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_POWER_PLANE_H_
+#define _CPU_F10_POWER_PLANE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10CpuAmdPmPwrPlaneInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_POWER_PLANE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
new file mode 100755
index 0000000000..ef52322d12
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -0,0 +1,154 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Pstate feature support functions.
+ *
+ * Provides the functions necessary to initialize the Pstate feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 18309 $   @e \$Date: 2009-08-27 15:48:22 +0800 (Thu, 27 Aug 2009) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuPstateTables.h"
+#include "Table.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsPstatePsdDependent (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID         CpuLogicalId;
+  PLATFORM_FEATS         Features;
+
+  // Initialize the union
+  Features.PlatformValue = 0;
+  GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+  GetPlatformFeatures (&Features, PlatformConfig, StdHeader);
+
+  //
+  // RevC Single link has PSD option, default is dependent.
+  // If multi-link, always return independent.
+  //
+  if ((Features.PlatformFeatures.PlatformSingleLink) && ((CpuLogicalId.Revision & AMD_F10_Cx) != 0)) {
+    if (PlatformConfig->ForcePstateIndependent) {
+      return FALSE;
+    }
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/**
+ *  Family specific call to set core TscFreqSel.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10SetTscFreqSel (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64             MsrValue;
+
+  LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader);
+  if (UserOptions.OptionMultisocket) {
+    //
+    // If Agesa need to do p-state leveling on multi-socket, changing the P0
+    // frequency after setting this bit has no effect on the TSC rate.
+    //
+    ASSERT ((MsrValue & BIT24) == 0);
+  }
+  MsrValue = MsrValue | BIT24;
+  LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
+}
+
+CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices =
+{
+  0,
+  F10IsPstatePsdDependent,
+  F10SetTscFreqSel
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
new file mode 100755
index 0000000000..d7e03d4b79
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * AMD Family_10 thermal initialization
+ *
+ * Performs processor thermal initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuF10SoftwareThermal.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *    Main entry point for initializing the Thermal Control
+ *    safety net feature.
+ *
+ *    This must be run by all Family 10h core 0s in the system.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters.
+ * @param[in]  StdHeader               Config handle for library and services.
+ */
+VOID
+F10PmThermalInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Core;
+  UINT32    Module;
+  UINT32    PciRegister;
+  UINT32    Socket;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS  IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  ASSERT (Core == 0);
+
+  if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
+      // Enable HTC
+      PciAddress.Address.Register = HTC_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((HTC_REGISTER *) &PciRegister)->HtcSlewSel = 0;
+      ((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h
new file mode 100755
index 0000000000..4715f3b95d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * AMD Family_10 thermal initialization related functions and structures
+ *
+ * Performs processor thermal initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_SOFTWARE_THERMAL_H_
+#define _CPU_F10_SOFTWARE_THERMAL_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmThermalInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_SOFTWARE_THERMAL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
new file mode 100755
index 0000000000..549c59e134
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -0,0 +1,1768 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuF10Utilities.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+// Register encodings for F3xD8[VSRampTime/VSSlamTime]
+CONST UINT32 ROMDATA VSSlamTime[8] =
+{
+  10,   // 000b: 10us
+  20,   // 001b: 20us
+  30,   // 010b: 30us
+  40,   // 011b: 40us
+  60,   // 100b: 60us
+  100,  // 101b: 100us
+  200,  // 110b: 200us
+  500   // 111b: 500us
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+F10GetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+VOID
+F10GetHtLinkFeatures (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  OUT      UINTN                  *Link,
+  IN       PCI_ADDR               *LinkBase,
+  OUT      HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+BOOLEAN
+F10DoesLinkHaveHtPhyFeats (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR           CapabilitySet,
+  IN       UINT32             Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+  OUT      BOOLEAN            *MatchedSublink1,
+  OUT      HT_FREQUENCIES     *Frequency0,
+  OUT      HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+VOID
+F10SetHtPhyRegister (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+VOID
+F10SetRegisterForHtLinkTokenEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Performs the necessary steps for the 'Software Initiated CPU
+ *  Voltage Transitions.'
+ *
+ *  @param[in]   VidCode       VID code to transition to
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10PmSwVoltageTransition (
+  IN       UINT32 VidCode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    PciRegister;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Ignored;
+  UINT64    MsrRegister;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = PW_CTL_MISC_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) {
+    LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+    ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode;
+    LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+    F10WaitOutVoltageTransition  (TRUE, StdHeader);
+  } else
+    return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Performs the necessary steps for the 'Software Initiated NB
+ *  Voltage Transitions.'
+ *
+ *  This can only be run by a local core 0.
+ *
+ *  @param[in]   VidCode       VID code to transition to
+ *  @param[in]   SlamMode      Whether voltage is to be slammed, or stepped
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10PmSwVoltageTransitionServerNb (
+  IN       UINT32 VidCode,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Core;
+  UINT32 NbVidStatus;
+  UINT32 Socket;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  UINT32 CoreNum;
+  AP_TASK TaskPtr;
+  AGESA_STATUS IgnoredSts;
+  SW_VOLT_TRANS_NB RemoteInput;
+
+  RemoteInput.VidCode = VidCode;
+  RemoteInput.SlamMode = SlamMode;
+  TaskPtr.FuncAddress.PfApTaskIO = F10SwVoltageTransitionServerNbCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (SW_VOLT_TRANS_NB);
+  TaskPtr.DataTransfer.DataPtr = &RemoteInput;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+  IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+
+  do {
+    NbVidStatus = TaskPtr.FuncAddress.PfApTaskIO (&RemoteInput, StdHeader);
+    for (Core = 1; Core < (UINT8) CoreNum; Core++) {
+      NbVidStatus |= ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+    }
+    F10WaitOutVoltageTransition (SlamMode, StdHeader);
+  } while (NbVidStatus != 0);
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns current VsSlamTime in microseconds.
+ *
+ *  @param[out]  VsTimeUsecs   Provides the wait time needed for a Slam Voltage transition.
+ *  @param[in]   SlamMode      Whether voltage is to be slammed, or stepped
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10GetCurrentVsTimeInUsecs (
+     OUT   UINT32  *VsTimeUsecs,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     RegisterEncoding;
+  UINT32    PciRegister;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Ignored;
+  CONST UINT16    SlamTimes[8] = {10, 20, 30, 40, 60, 100, 200, 500};
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = CPTC1_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+  if (SlamMode) {
+    RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSSlamTime;
+  } else {
+    RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampTime;
+  }
+
+  *VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Spins until VsSlamTime microseconds have expired.
+ *
+ *  @param[in]   SlamMode      Whether voltage is to be slammed, or stepped
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10WaitOutVoltageTransition (
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 VsTimeUsecs;
+
+  F10GetCurrentVsTimeInUsecs (&VsTimeUsecs, SlamMode, StdHeader);
+  WaitMicroseconds (VsTimeUsecs, StdHeader);
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Code required to be run on every local core in order to perform
+ *  the steps necessary for 'Software Initiated NB Voltage
+ *  Transitions.'
+ *
+ *  @param[out]  InputData     Family specific data needed to perform a Voltage transition.
+ *  @param[in]   StdHeader     Header for library and services.
+ *
+ *  @retval     zero           All Voltage Transitions are completed.
+ *  @retval     one            There are Voltage transitions remaining to reach target.
+ *
+ */
+UINT32
+F10SwVoltageTransitionServerNbCore (
+  IN       VOID  *InputData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 VidCode;
+  UINT64 MsrRegister;
+
+  if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) {
+    VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode;
+  } else {
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+    VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid);
+    if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
+      --VidCode;
+    } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
+      ++VidCode;
+    }
+  }
+  LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+  ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode;
+  LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+
+  if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
+    return 0;
+  } else {
+    return 1;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
+ *
+ * This function determines the largest voltage step that the core will have
+ * to make, calculates how much time it will take for the voltage to stabilize,
+ * and programs the necessary encoded value for the amount of time discovered.
+ *
+ * @param[in]  PciAddress         Segment/bus/device of a module on the socket
+ *                                to program.
+ * @param[in]  CpuEarlyParams     Service parameters
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+F10ProgramVSSlamTimeOnSocket (
+  IN       PCI_ADDR             *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8    NbVid;
+  UINT8    P0VidCode;
+  UINT8    PminVidCode;
+  UINT32   AndMask;
+  UINT32   MsrAddr;
+  UINT32   OrMask;
+  UINT32   PciRegister;
+  UINT64   MsrRegister;
+  BOOLEAN  IsPviMode;
+  PCI_ADDR LocalPciAddress;
+
+  // Get F3xA0[PviMode]
+  LocalPciAddress.AddressValue = PciAddress->AddressValue;
+  LocalPciAddress.Address.Function = FUNC_3;
+  LocalPciAddress.Address.Register = PW_CTL_MISC_REG;
+  LibAmdPciRead (AccessWidth32, LocalPciAddress, &PciRegister, StdHeader);
+  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
+    IsPviMode = TRUE;
+  } else {
+    IsPviMode = FALSE;
+  }
+
+  // Get P0's voltage
+  LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader);
+  P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+
+  // If SVI, we only care about CPU VID.
+  // If PVI, determine the higher voltage between NB and CPU
+  if (IsPviMode) {
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    if (P0VidCode > NbVid) {
+      P0VidCode = NbVid;
+    }
+  }
+
+  // Get Pmin's index
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
+  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+
+  // Get Pmin's VID
+  LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+
+  // If SVI, we only care about CPU VID.
+  // If PVI, determine the higher voltage b/t NB and CPU
+  if (IsPviMode) {
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    if (PminVidCode > NbVid) {
+      PminVidCode = NbVid;
+    }
+  }
+
+  // Program F3xD8[VSSlamTime]
+  LocalPciAddress.Address.Register = CPTC1_REG;
+  AndMask = 0xFFFFFFFF;
+  ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->VSSlamTime = 0;
+  OrMask = 0x00000000;
+  ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSSlamTime =
+    F10GetSlamTimeEncoding (P0VidCode, PminVidCode, CpuEarlyParams, VSSlamTime, StdHeader);
+  ModifyCurrentSocketPci (&LocalPciAddress, AndMask, OrMask, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the encoded voltage stabilization slam time for the executing
+ * family 10h core.
+ *
+ * This function looks up the appropriate encoded value for the desired
+ * VID codes.
+ *
+ * @param[in]  HighVoltageVid     VID code of the higher voltage.
+ * @param[in]  LowVoltageVid      VID code of the lower voltage.
+ * @param[in]  CpuEarlyParams     Service parameters
+ * @param[in]  SlamTimeTable      Look-up table of slam times.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ * @retval     Encoded register value.
+ *
+ */
+UINT32
+F10GetSlamTimeEncoding (
+  IN       UINT8  HighVoltageVid,
+  IN       UINT8  LowVoltageVid,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       CONST UINT32 *SlamTimeTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 SlamTime;
+  UINT32 EncodedSlamTime;
+  UINT32 VoltageDifference;
+
+  ASSERT (LowVoltageVid >= HighVoltageVid);
+  ASSERT (CpuEarlyParams->PlatformConfig.VrmProperties.SlewRate != 0);
+
+  // Calculate Slam Time
+  //   VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vhigh - Vlow
+  //   In our case, we will scale the values by 100 to avoid
+  //   decimals.
+
+  VoltageDifference = (UINT32) ((LowVoltageVid - HighVoltageVid) * 12500);
+  SlamTime = (VoltageDifference / CpuEarlyParams->PlatformConfig.VrmProperties.SlewRate) + CpuEarlyParams->PlatformConfig.VrmProperties.AdditionalDelay;
+  if (VoltageDifference % CpuEarlyParams->PlatformConfig.VrmProperties.SlewRate) {
+    SlamTime++;
+  }
+
+  // Now round up to nearest register setting
+  for (EncodedSlamTime = 0; EncodedSlamTime < 8; EncodedSlamTime++) {
+    if (SlamTime <= SlamTimeTable[EncodedSlamTime]) {
+      break;
+    }
+  }
+
+  if (EncodedSlamTime > 7) {
+    // The VRMs are too slow for this CPU.  Set to max, and fire an error trap.
+    IDS_ERROR_TRAP;
+    EncodedSlamTime = 7;
+  }
+
+  return (EncodedSlamTime);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Calculates the power in milliWatts of the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_POWER}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              Which P-state to analyze
+ *  @param[out]  PowerInMw                The Power in milliWatts of that P-State
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstatePower (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  CpuVid;
+  UINT32  IddValue;
+  UINT32  IddDiv;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  Ignored;
+  BOOLEAN PviFlag;
+  UINT32  V_x10000;
+  UINT32  Power;
+  PCI_ADDR PciAddress;
+  UINT32  TempVar_a;
+  UINT64  MsrRegister;
+  AGESA_STATUS IgnoredSts;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+  IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
+  IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = POWER_CTRL_MISCELLANEOUS_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_a, StdHeader);
+  if ((TempVar_a & 0x00000100) != 0) {
+    PviFlag = TRUE;
+  } else {
+    PviFlag = FALSE;
+  }
+  if (PviFlag) {
+    // Set CpuVid value in case CPU is in PVI mode
+    if (CpuVid > 0x5D) {
+      CpuVid = 0x3F;
+    } else if (CpuVid > 0x3E) {
+      CpuVid = CpuVid - 0x1F;
+    } else {
+      CpuVid = (CpuVid >> 1);
+    }
+
+    // PVI Encoding
+    if (CpuVid >= 0x20) {
+      V_x10000 = 7625L - (125L * (CpuVid - 0x20));
+    } else {
+      V_x10000 = 15500L - (250L * CpuVid);
+    }
+  } else {
+    if (CpuVid >= 0x7C) {
+      V_x10000 = 0;
+    } else {
+      V_x10000 = 15500L - (125L * CpuVid);
+    }
+  }
+
+  Power = V_x10000 * IddValue;
+
+  switch (IddDiv) {
+  case 0:
+    *PowerInMw = Power / 10L;
+    break;
+  case 1:
+    *PowerInMw = Power / 100L;
+    break;
+  case 2:
+    *PowerInMw = Power / 1000L;
+    break;
+  default:
+    // IddDiv is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    *PowerInMw = 0;
+    break;
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Calculates the frequency in megahertz of the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The P-State to analyze.
+ *  @param[out]  FrequencyInMHz           The P-State's frequency in MegaHertz
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS   Always Succeeds.
+ */
+AGESA_STATUS
+F10GetPstateFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempValue;
+  UINT32 CpuDid;
+  UINT32 CpuFid;
+  UINT64 MsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid);
+  CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid);
+
+  switch (CpuDid) {
+  case 0:
+    TempValue = 1;
+    break;
+  case 1:
+    TempValue = 2;
+    break;
+  case 2:
+    TempValue = 4;
+    break;
+  case 3:
+    TempValue = 8;
+    break;
+  case 4:
+    TempValue  =  16;
+    break;
+  default:
+    // CpuDid is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    TempValue = 1;
+    break;
+  }
+  *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Disables the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The P-State to disable.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
+  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Transitions the executing core to the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The new P-State to make effective.
+ *  @param[in]   WaitForTransition        True if the caller wants the transition completed upon return.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS       Always Succeeds
+ */
+AGESA_STATUS
+F10TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+  ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+  if (WaitForTransition) {
+    do {
+      LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
+    } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the rate at which the executing core's time stamp counter is
+ *  incrementing.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  FrequencyInMHz           TSC actual frequency.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ *  @return      The most severe status of all called services
+ */
+AGESA_STATUS
+F10GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Ignored;
+  UINT64 MsrRegister;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
+  if ((MsrRegister & 0x01000000) != 0) {
+    return (FamilySpecificServices->GetPstateFrequency (FamilySpecificServices, 0, FrequencyInMHz, StdHeader));
+  } else {
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    return (FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, FrequencyInMHz, &Ignored, StdHeader));
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[out]  VoltageInuV              Northbridge voltage in uV.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_UNSUPPORTED   Unknown revs of F10 will return unsupported.
+ */
+AGESA_STATUS
+F10GetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // This was called by an unknown rev of F10 CPU.
+  return (AGESA_UNSUPPORTED);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initially launches the desired core to run from the reset vector.
+ *
+ * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   SocketNum                The Processor on which the core is to be launched
+ * @param[in]   ModuleNum                The Module in that processor containing that core
+ * @param[in]   CoreNum                  The Core to launch
+ * @param[in]   PrimaryCoreNum           The id of the module's primary core.
+ * @param[in]   StdHeader                Header for library and services
+ *
+ * @retval      TRUE          The core was launched
+ * @retval      FALSE         The core was previously launched
+ */
+BOOLEAN
+F10LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    NodeRelativeCoreNum;
+  UINT32    PciRegister;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   LaunchFlag;
+  AGESA_STATUS Ignored;
+
+  // Code Start
+  LaunchFlag = FALSE;
+  NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
+  GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored);
+  PciAddress.Address.Function = FUNC_0;
+
+  switch (NodeRelativeCoreNum) {
+  case 0:
+    PciAddress.Address.Register = HT_INIT_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & HT_INIT_CTRL_REQ_DIS) != 0) {
+      PciRegister &= ~HT_INIT_CTRL_REQ_DIS;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 1:
+    PciAddress.Address.Register = HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
+      PciRegister |= HT_TRANS_CTRL_CPU1_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 2:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister,
+                      StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 3:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 4:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU4_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU4_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 5:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU5_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU5_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+
+  default:
+    break;
+  }
+
+  return (LaunchFlag);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will return the CpuFid and CpuDid in MHz, using the formula
+ *    described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in]       PStateNumber             P-state number to check.
+ *    @param[in]       Frequency                Leveled target frequency for PStateNumber.
+ *    @param[out]      *CpuFidPtr               New leveled FID.
+ *    @param[out]      *CpuDidPtr1              New leveled DID info 1.
+ *    @param[out]      *CpuDidPtr2              New leveled DID info 2.
+ *    @param[in]       *StdHeader               Header for library and services.
+ *
+ *    @retval       AGESA_WARNING           This P-State does not need to be modified.
+ *    @retval       AGESA_SUCCESS           This P-State must be modified to be level.
+ */
+AGESA_STATUS
+F10GetFrequencyXlatRegInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  PStateNumber,
+  IN       UINT32                 Frequency,
+     OUT   UINT32                 *CpuFidPtr,
+     OUT   UINT32                 *CpuDidPtr1,
+     OUT   UINT32                 *CpuDidPtr2,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 i;
+  UINT32 j;
+  AGESA_STATUS Status;
+  UINT32 FrequencyInMHz;
+
+  FrequencyInMHz = 0;
+  *CpuDidPtr2 = 0xFFFF;
+
+  Status = AGESA_SUCCESS;
+
+  FamilySpecificServices->GetPstateFrequency (FamilySpecificServices, PStateNumber, &FrequencyInMHz, StdHeader);
+  if (FrequencyInMHz == Frequency) {
+    Status |= AGESA_WARNING;
+  }
+
+  // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid)
+  // In this for loop i = 2^CpuDid
+
+
+  for (i = 1; i < 17; (i += i)) {
+    for (j = 0; j < 64; j++) {
+      if (Frequency == ((100 * (j + 0x10)) / i )) {
+        *CpuFidPtr = j;
+        if (i == 1) {
+          *CpuDidPtr1 = 0;
+        } else if (i == 2) {
+          *CpuDidPtr1 = 1;
+        } else if (i == 4) {
+          *CpuDidPtr1 = 2;
+        } else if (i == 8) {
+          *CpuDidPtr1 = 3;
+        } else if (i == 16) {
+          *CpuDidPtr1 = 4;
+        } else {
+          *CpuFidPtr = 0xFFFF;
+          *CpuDidPtr1 = 0xFFFF;
+        }
+        // Success
+        return Status;
+      }
+    }
+  }
+
+  // Error Condition
+  *CpuFidPtr = 0x00FF;
+  *CpuDidPtr1 = 0x00FF;
+  *CpuDidPtr2 = 0x00FF;
+
+  return AGESA_ERROR;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function sets the Pstate MSR to each APs base on Pstate Buffer.
+ *
+ * @CpuServiceMethod{::F_CPU_SET_PSTATE_LEVELING_REG}.
+ *
+ * This function should be called for every core in the system.
+ *
+ * @param[in]       FamilySpecificServices   The current Family Specific Services.
+ * @param[in]       CpuAmdPState             Gathered P-state data structure for whole system.
+ * @param[in]       StdHeader                Config for library and services.
+ *
+ * @retval          AGESA_STATUS    @todo document return *values*.
+ *
+ */
+AGESA_STATUS
+F10PstateLevelingCoreMsrModify (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       S_CPU_AMD_PSTATE   *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32             i;
+  UINT32             Ignored;
+  UINT32             k;
+  UINT32             TempVar_d;
+  UINT32             TempVar_e;
+  UINT32             TempVar_f;
+  UINT64             MsrValue;
+  AGESA_STATUS       Status;
+  UINT32             Socket;
+  UINT32             Module;
+  UINT32             Core;
+  PSTATE_LEVELING    *PStateBufferPtr;
+  PSTATE_LEVELING    *PStateBufferPtrTmp;
+  S_CPU_AMD_PSTATE   *CpuAmdPstatePtr;
+  UINT32             LogicalSocketCount;
+  PCI_ADDR           PciAddress;
+  UINT32             PciRegister;
+
+  Ignored = 0;
+  CpuAmdPstatePtr = (S_CPU_AMD_PSTATE *) CpuAmdPState;
+  PStateBufferPtrTmp = CpuAmdPstatePtr->PStateLevelingStruc;
+  PStateBufferPtr = CpuAmdPstatePtr->PStateLevelingStruc;
+  LogicalSocketCount = CpuAmdPstatePtr->TotalSocketInSystem;
+  PciAddress.AddressValue = 0;
+
+  //
+  //Try to find the Pstate buffer specific to this core(socket).
+  //
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &Status);
+  for (i = 0; i < LogicalSocketCount; i++) {
+    CpuGetPStateLevelStructure (&PStateBufferPtrTmp, CpuAmdPstatePtr, i, StdHeader);
+    if (PStateBufferPtrTmp->SocketNumber == Socket) {
+      break;
+    }
+  }
+
+  if (PStateBufferPtr[0].OnlyOneEnabledPState) {
+    //
+    //If all processors have only 1 enabled P-state, the following sequence should be performed on all cores:
+    //
+
+    //1. Write the appropriate CpuFid value resulting from the matched CPU COF to MSRC001_0064[CpuFid].
+    LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
+    Status = F10GetFrequencyXlatRegInfo (FamilySpecificServices, 0, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader);
+    // Bits 5:0
+    ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d;
+    // Bits 8:6
+    ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e;
+    // Bits 39:32
+    ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue;
+    // Bits 41:40
+    ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv;
+    // Enable the P-State
+    ((PSTATE_MSR *) &MsrValue)->PsEnable = 1;
+    LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
+
+    //2. Copy MSRC001_0064 to MSRC001_0065.
+    LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
+
+    //3. Write 001b to F3xDC[PstatemaxVal].
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Status);
+    PciAddress.Address.Register = CPTC2_REG;
+    PciAddress.Address.Function = FUNC_3;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+    //4. Write 001b to MSRC001_0062[PstateCmd].
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
+
+    //5. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0065[CpuFid].
+    do {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader);
+    } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d);
+
+    //6. Write 000b to MSRC001_0062[PstateCmd].
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
+
+    //7. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0064[CpuFid].
+    do {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader);
+    } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d);
+
+    //8. Write 0b to MSRC001_0065[PstateEn].
+    LibAmdMsrRead (MSR_PSTATE_1, &MsrValue, StdHeader);
+    ((PSTATE_MSR *) &MsrValue)->PsEnable = 0;
+    LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
+
+    //9. Write 000b to F3xDC[PstateMaxVal] and exit the sequence (no further steps are required).
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+  } else {
+    TempVar_f = MSR_PSTATE_0;
+
+    for (k = 0; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++, TempVar_f++) {
+      // If pState is not disabled then do update
+      LibAmdMsrRead (TempVar_f, &MsrValue, StdHeader);
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable == 1) {
+        Status = F10GetFrequencyXlatRegInfo (FamilySpecificServices, (UINT8) k, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader);
+        if (Status != AGESA_ERROR) {
+          // Bits 5:0
+          ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d;
+          // Bits 8:6
+          ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e;
+        }
+
+        // Bits 39:32
+        ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddValue;
+        // Bits 41:40
+        ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddDiv;
+        // Enable the P-State
+        ((PSTATE_MSR *) &MsrValue)->PsEnable = 1;
+        LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader);
+      } else {
+        // Disable the P-State
+        ((PSTATE_MSR *) &MsrValue)->PsEnable = 0;
+        LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader);
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F10GetPowerStepValueInTime
+ *
+ *  Description:
+ *    Convert power step value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PowerStepPtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+STATIC VOID
+F10GetPowerStepValueInTime (
+  IN OUT   UINT32  *PowerStepPtr
+  )
+{
+  UINT32 TempVar_a;
+
+  TempVar_a = *PowerStepPtr;
+
+  if (TempVar_a < 0x4) {
+    *PowerStepPtr = 400 - (TempVar_a * 100);
+  } else if (TempVar_a <  0x9) {
+    *PowerStepPtr = 130 - (TempVar_a * 10);
+  } else {
+    *PowerStepPtr = 90 - (TempVar_a * 5);
+  }
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F10GetPllValueInTime
+ *
+ *  Description:
+ *    Convert PLL Value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PllLockTimePtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+STATIC VOID
+F10GetPllValueInTime (
+  IN OUT   UINT32  *PllLockTimePtr
+  )
+{
+  if (*PllLockTimePtr < 4) {
+    *PllLockTimePtr = *PllLockTimePtr + 1;
+  } else if (*PllLockTimePtr == 4) {
+    *PllLockTimePtr = 8;
+  } else if (*PllLockTimePtr == 5) {
+    *PllLockTimePtr = 16;
+  } else
+    *PllLockTimePtr = 0;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get Pstate Transition Latency.
+ *
+ *  @CpuServiceMethod{::F_CPU_PSTATE_TRANSITION_LATENCY}.
+ *
+ *  Calculate TransitionLatency by power step value and pll value.
+ *
+ *  @param[in]     FamilySpecificServices            The current Family Specific Services.
+ *  @param[in]     PStateLevelingBufferStructPtr     Pstate row data buffer pointer
+ *  @param[in]     PciAddress                        Pci address
+ *  @param[out]    TransitionLatency                 The transition latency.
+ *  @param[in]     StdHeader                         Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstateTransLatency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32               TempVar_b;
+  UINT32               TempVar_c;
+  UINT32               TempVar_d;
+  UINT32               TempVar8_a;
+  UINT32               TempVar8_b;
+  UINT32               Ignored;
+  UINT32               k;
+  UINT32               CpuFidSameFlag;
+  UINT8                PStateMaxValueOnCurrentCore;
+  UINT32               TransAndBusMastLatency;
+
+  CpuFidSameFlag = 1;
+
+  F10GetFrequencyXlatRegInfo (
+    FamilySpecificServices,
+    0,
+    PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq,
+    &TempVar_b,
+    &TempVar_c,
+    &Ignored,
+    StdHeader
+    );
+
+  TempVar_d = TempVar_b;
+  PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue;
+
+  //
+  //Check if MSRC001_00[68:64][CpuFid] is the same value for all P-states where
+  //MSRC001_00[68:64][PstateEn]=1
+  //
+  for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) {
+    if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+      F10GetFrequencyXlatRegInfo (
+        FamilySpecificServices,
+        (UINT8) k,
+        PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq,
+        &TempVar_b,
+        &TempVar_c,
+        &Ignored,
+        StdHeader
+        );
+    }
+
+    if (TempVar_d != TempVar_b) {
+      CpuFidSameFlag = 0;
+      break;
+    }
+  }
+
+  PciAddress->Address.Register = 0xD4;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
+
+  // PowerStepDown - Bits 20:23
+  TempVar8_a = (TempVar_d & 0x00F00000) >> 20;
+
+  // PowerStepUp   - Bits 24:27
+  TempVar8_b = (TempVar_d & 0x0F000000) >> 24;
+
+  // Convert the raw numbers in TempVar8_a and TempVar8_b into time
+  F10GetPowerStepValueInTime (&TempVar8_a);
+  F10GetPowerStepValueInTime (&TempVar8_b);
+
+  //
+  //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us
+  //
+  TransAndBusMastLatency =
+  (12 * (TempVar8_a + TempVar8_b) + 999) / 1000;
+
+  if (CpuFidSameFlag == 0) {
+    //
+    //+ F3xA0[PllLockTime]
+    //
+    PciAddress->Address.Register = 0xA0;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
+
+    TempVar8_a = (0x00003800 & TempVar_d) >> 11;
+    F10GetPllValueInTime (&TempVar8_a);
+    TransAndBusMastLatency += TempVar8_a;
+  }
+
+  *TransitionLatency = TransAndBusMastLatency;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate register Informations.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_REGISTER_INFO}.
+ *
+ *    This function will check if PState is Enabled by reading MSR.
+ *    This function also returns the MSR Value, that contains IddValue, IddDiv.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     PState                    Input Pstate number for query.
+ *  @param[out]    PStateEnabled             Boolean flag return pstate enable.
+ *  @param[in,out] IddVal                    Pstate current value.
+ *  @param[in,out] IddDiv                    Pstate current divisor.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstateRegisterInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  ASSERT (PState < NM_PS_REG);
+
+  // Read PSTATE MSRs
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
+
+  if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+    // PState enable = bit 63
+    *PStateEnabled = TRUE;
+  } else {
+    *PStateEnabled = FALSE;
+  }
+
+  // Bits 39:32 (high 32 bits [7:0])
+  *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
+  // Bits 41:40 (high 32 bits [9:8])
+  *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate max state.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_MAX_STATE}.
+ *
+ *    This function returns the MaxPStateNumber.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[out]    MaxPStateNumber             Boolean flag return pstate enable.
+ *  @param[in]     StdHeader              Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstateMaxState (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32              *MaxPStateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT64              MsrValue;
+
+  //
+  // Read PstateMaxVal [6:4] from MSR C001_0061
+  // So, we will know the max pstate state in this socket.
+  //
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
+  *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) & MsrValue)->PstateMaxVal);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU Specific Platform Type Info.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}.
+ *
+ *    This function returns Returns the platform features.
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[in,out] Features                       The Features supported by this platform.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPlatformTypeSpecificInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PLATFORM_FEATS         *Features,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the features of the given HT link.
+ *
+ *  @CpuServiceMethod{::F_GET_HT_LINK_FEATURES}.
+ *
+ * This method is different than the HT Phy Features method, because for the phy registers
+ * sublink 1 matches and should be programmed if the link is ganged but for PCI config
+ * registers sublink 1 is reserved if the link is ganged.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[out]    Link                      The link number, for accessing non-capability set registers.
+ * @param[in]     LinkBase                  The base HT Host capability PCI address for the link.
+ * @param[out]    HtHostFeats               The link's features.
+ * @param[in]     StdHeader                 Standard Head Pointer
+ */
+VOID
+F10GetHtLinkFeatures (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINTN                  *Link,
+  IN       PCI_ADDR               *LinkBase,
+     OUT   HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    RegValue;
+  UINT32    ExtendedFreq;
+  UINTN     LinkOffset;
+
+  ASSERT (FamilySpecificServices != NULL);
+
+  // No features present unless link is good and connected.
+  HtHostFeats->HtHostValue = 0;
+
+  // Compute link number
+  *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5));
+
+  // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+  PciAddress = *LinkBase;
+  PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+  LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader);
+  if (RegValue  == 3) {
+    HtHostFeats->HtHostFeatures.Coherent = 1;
+  } else if (RegValue == 7) {
+    HtHostFeats->HtHostFeatures.NonCoherent = 1;
+  }
+
+  // If link was not connected, don't check other attributes, make sure
+  // to return zero, no match.
+  if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) {
+    // Check gen3
+    PciAddress = *LinkBase;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+    PciAddress = *LinkBase;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+    RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+    if (RegValue > 6) {
+      HtHostFeats->HtHostFeatures.Ht3 = 1;
+    } else {
+      HtHostFeats->HtHostFeatures.Ht1 = 1;
+    }
+    // Check ganged.
+    LinkOffset = (*Link) * 4;
+    PciAddress = *LinkBase;
+    PciAddress.Address.Function = 0;
+    PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170);
+    LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader);
+    if (RegValue == 0) {
+      HtHostFeats->HtHostFeatures.UnGanged = 1;
+    } else {
+      HtHostFeats->HtHostFeatures.Ganged = 1;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks to see if the HT phy register table entry should be applied
+ *
+ * @CpuServiceMethod{::F_DOES_LINK_HAVE_HTFPY_FEATS}.
+ *
+ * This function determines if the link type field matches the HT link
+ * passed in.
+ *
+ * This method will match for sublink 1 if the link is ganged and sublink 0 matches.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[in]     CapabilitySet    Address of the HT capability block
+ * @param[in]     Link             Zero based HT link to check
+ * @param[in]     HtPhyLinkType    Link type field from a register table entry to compare against
+ * @param[out]    MatchedSublink1  TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
+ * @param[out]    Frequency0       The frequency of sublink0 (200 MHz if not connected).
+ * @param[out]    Frequency1       The frequency of sublink1 (200 MHz if not connected).
+ * @param[in]     StdHeader        Standard Head Pointer
+ *
+ * @retval        TRUE             Link matches
+ * @retval        FALSE            Link does not match
+ *
+ */
+BOOLEAN
+F10DoesLinkHaveHtPhyFeats (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR           CapabilitySet,
+  IN       UINT32             Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+     OUT   BOOLEAN            *MatchedSublink1,
+     OUT   HT_FREQUENCIES     *Frequency0,
+     OUT   HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32    RegValue;
+  UINT32    ExtendedFreq;
+  PCI_ADDR  PciAddress;
+  PCI_ADDR  SubLink1Address;
+  HT_PHY_LINK_FEATS LinkType;
+  BOOLEAN   IsReallyCheckingBoth;
+
+  ASSERT (Link < 4);
+  ASSERT (HtPhyLinkType != NULL);
+  // error checks: No unknown link type bits set and not a "match none"
+  ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0);
+  ASSERT (HtPhyLinkType->HtPhyLinkValue != 0);
+
+  *Frequency0 = 0;
+  *Frequency1 = 0;
+  IsReallyCheckingBoth = FALSE;
+  *MatchedSublink1 = FALSE;
+  LinkType.HtPhyLinkValue = 0;
+
+  // Set the link indicators.  This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4.
+  LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << Link);
+  LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << Link);
+
+  // if ganged, don't read sublink 1, but use sublink 0 to check.
+  SubLink1Address = CapabilitySet;
+
+  // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also,
+  // but only access it if it is also unganged.
+  Link *= 4;
+  PciAddress = CapabilitySet;
+  PciAddress.Address.Function = 0;
+  PciAddress.Address.Register = (Link + 0x170);
+  LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+  RegValue = (RegValue & 0x01);
+  if (RegValue == 0) {
+    // Then really read sublink1, rather than using sublink0
+    SubLink1Address.Address.Function = 4;
+    IsReallyCheckingBoth = TRUE;
+  }
+
+  // Checks for Sublink 0
+
+  // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+  PciAddress = CapabilitySet;
+  PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+  LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+  if ((RegValue & 0x1F) == 3) {
+    LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1;
+  } else if ((RegValue & 0x1F) == 7) {
+    LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1;
+  }
+
+  // If link was not connected, don't check other attributes, make sure
+  // to return zero, no match. (Phy may be powered off.)
+  if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) {
+    // Check gen3
+    PciAddress = CapabilitySet;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+    PciAddress = CapabilitySet;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+    RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+    *Frequency0 = RegValue;
+    if (RegValue > 6) {
+      LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1;
+    } else {
+      LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1;
+    }
+  } else {
+    LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL);
+  }
+
+  // Checks for Sublink 1
+  // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+  PciAddress = SubLink1Address;
+  PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+  LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+  if ((RegValue & 0x1F) == 3) {
+    LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1;
+  } else if ((RegValue & 0x1F) == 7) {
+    LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1;
+  }
+
+  if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) {
+    // Check gen3
+    PciAddress = SubLink1Address;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+    PciAddress = SubLink1Address;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+    RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+    *Frequency1 = RegValue;
+    if (RegValue > 6) {
+      LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1;
+    } else {
+      LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1;
+    }
+  } else {
+    LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL);
+  }
+
+  // For Deemphasis checking, indicate whether it was actually sublink 1 that matched.
+  // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false.
+  if ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0) {
+    if (IsReallyCheckingBoth &&
+        (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) {
+      *MatchedSublink1 = TRUE;
+    }
+    return TRUE;  // Link matches at least one of the desired characteristics
+  } else {
+    return FALSE; // Link does not match any criteria
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
+ *
+ * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}.
+ *
+ * This function performs the necessary sequence of PCI reads, writes, and waits
+ * necessary to program an HT Phy register.
+ *
+ * @param[in]  FamilySpecificServices    The current Family Specific Services.
+ * @param[in]  HtPhyEntry    HT Phy register table entry to apply
+ * @param[in]  CapabilitySet The link's HT Host base address.
+ * @param[in]  Link          Zero based, node, link number (not package link).
+ * @param[in]  StdHeader     Config handle for library and services
+ *
+ */
+VOID
+F10SetHtPhyRegister (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  UINT32    Temp;
+  UINT32    PhyReg;
+  PCI_ADDR  PhyBase;
+
+  // Determine the PCI config address of the HT Phy portal
+  PhyBase = CapabilitySet;
+  PhyBase.Address.Function = FUNC_4;
+  PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180);
+
+  LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+
+  // Handle direct map registers if needed
+  PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK);
+  if (HtPhyEntry->Address > 0x1FF) {
+    PhyReg |= HTPHY_DIRECT_MAP;
+  }
+
+  PhyReg |= (HtPhyEntry->Address);
+  // Ask the portal to read the HT Phy Register contents
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+
+  // Get the current register contents and do the update requested by the table
+  PhyBase.AddressValue += 4;
+  LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  Temp &= ~(HtPhyEntry->Mask);
+  Temp |= (HtPhyEntry->Data);
+  LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader);
+
+  PhyBase.AddressValue -= 4;
+  // Ask the portal to write our updated value to the HT Phy
+  PhyReg |= HTPHY_WRITE_CMD;
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the HT Link Token Count registers (F3X1[54,50,4C,48]).
+ *
+ * @TableEntryTypeMethod{::HtTokenPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * For all HT links, check the link's feature set for a match to the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The Link Token register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+F10SetRegisterForHtLinkTokenEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINTN                 LinkCount;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN                 ProcessorCount;
+  UINT32                RegisterData;
+  PCI_ADDR              PciAddress;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
+          ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->HtTokenEntry.Mask != 0));
+
+  HtHostFeats.HtHostValue = 0;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  // Check if the actual processor count is in either range.
+  ProcessorCount = GetNumberOfProcessors (StdHeader);
+  if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->HtTokenEntry.ProcessorCounts.ProcessorCountRanges)) {
+    // Check for any performance profile features.
+    GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+    if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                        Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) {
+      // Check the link features.
+      LinkCount = 0;
+      while (LinkCount < 4) {
+        if (FindHtHostCapability (LinkCount, &CapabilitySet, StdHeader)) {
+          FamilySpecificServices->GetHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader);
+          if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) {
+            // Do the HT Host PCI register update.
+            PciAddress = CapabilitySet;
+            PciAddress.Address.Function = 3;
+            PciAddress.Address.Register = LINK_TO_XCS_TOKEN_COUNT_REG_3X148 + ((UINT32)Link * 4);
+            LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+            RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask));
+            RegisterData = RegisterData | Entry->HtTokenEntry.Data;
+            LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+          }
+        } else {
+          // No more Capabilities.
+          break;
+        }
+        LinkCount ++;
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.h
new file mode 100755
index 0000000000..4b4a440d59
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.h
@@ -0,0 +1,223 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_UTILITES_H_
+#define _CPU_F10_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// The structure for Software Initiated NB Voltage Transitions
+typedef struct {
+  UINT32  VidCode;          ///< VID code to transition to
+  BOOLEAN SlamMode;         ///< Whether voltage is to be slammed, or stepped
+} SW_VOLT_TRANS_NB;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmSwVoltageTransition (
+  IN       UINT32 VidCode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10PmSwVoltageTransitionServerNb (
+  IN       UINT32 VidCode,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+F10SwVoltageTransitionServerNbCore (
+  IN       VOID  *InputData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10WaitOutVoltageTransition (
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10GetCurrentVsTimeInUsecs (
+     OUT   UINT32 *VsTimeUsecs,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10ProgramVSSlamTimeOnSocket (
+  IN       PCI_ADDR             *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+UINT32
+F10GetSlamTimeEncoding (
+  IN       UINT8                HighVoltageVid,
+  IN       UINT8                LowVoltageVid,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       CONST UINT32         *SlamTimeTable,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstatePower (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F10LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10GetFrequencyXlatRegInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8  PStateNumber,
+  IN       UINT32 Frequency,
+     OUT   UINT32               *CpuFidPtr,
+     OUT   UINT32               *CpuDidPtr1,
+     OUT   UINT32               *CpuDidPtr2,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10PstateLevelingCoreMsrModify (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       S_CPU_AMD_PSTATE   *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateTransLatency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateRegisterInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateMaxState (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32              *MaxPStateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPlatformTypeSpecificInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PLATFORM_FEATS         *Features,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif  // _CPU_F10_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
new file mode 100755
index 0000000000..387038152e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AMD Family_10 WHEA initial Data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6436 $   @e \$Date: 2008-06-18 05:49:23 -0500 (Wed, 18 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F10WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AMD_HEST_BANK_INIT_DATA F10HestBankInitData[] = {
+  {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
+  {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
+  {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
+  {0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F},
+  {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
+  {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
+};
+
+AMD_WHEA_INIT_DATA F10WheaInitData = {
+  0x000000000,              // AmdGlobCapInitDataLsd
+  0x000000000,              // AmdGlobCapInitDataMsd
+  0x00000003F,              // AmdGlobCtrlInitDataLsd
+  0x000000000,              // AmdGlobCtrlInitDataMsd
+  0x00,                     // AmdMcbClrStatusOnInit
+  0x02,                     // AmdMcbStatusDataFormat
+  0x00,                     // AmdMcbConfWriteEn
+  (sizeof (F10HestBankInitData) / sizeof (F10HestBankInitData[0])), // HestBankNum
+  &F10HestBankInitData[0]   // Pointer to Initial data of HEST Bank
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific WHEA table properties.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  F10WheaInitDataPtr       Points to the family 10h WHEA properties.
+ *  @param[out]  NumberOfElements         Will be one to indicate one structure.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F10WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *F10WheaInitDataPtr = &F10WheaInitData;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h
new file mode 100755
index 0000000000..4a027a8254
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/cpuFamRegisters.h
@@ -0,0 +1,180 @@
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6459 $   @e \$Date: 2008-06-19 17:56:21 -0700 (Thu, 19 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FAM_REGISTERS_H_
+#define _CPU_FAM_REGISTERS_H_
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      M O D U L E S    U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      D E F I N I T I O N S  /  M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+// This define should be equal to the total number of families
+// in the cpuFamily enum.
+#define MAX_CPU_FAMILIES    64
+#define MAX_CPU_REVISIONS   63    // Max Cpu Revisions Per Family
+
+// CPU_LOGICAL_ID.Family equates
+// Family 10h equates
+#define AMD_FAMILY_10_RB  0x0000000000000001ull
+#define AMD_FAMILY_10_BL  0x0000000000000002ull
+#define AMD_FAMILY_10_DA  0x0000000000000004ull
+#define AMD_FAMILY_10_HY  0x0000000000000008ull
+#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
+
+#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY)
+#define AMD_FAMILY_GH    (AMD_FAMILY_10)
+
+// Family 12h equates
+#define AMD_FAMILY_12_LN  0x0000000000000010ull
+#define AMD_FAMILY_12   (AMD_FAMILY_12_LN)
+#define AMD_FAMILY_LN   (AMD_FAMILY_12_LN)
+
+// Family 14h equates
+#define AMD_FAMILY_14_ON  0x0000000000000020ull
+#define AMD_FAMILY_14   (AMD_FAMILY_14_ON)
+#define AMD_FAMILY_ON   (AMD_FAMILY_14_ON)
+
+// Family 15h equates
+#define AMD_FAMILY_15   0x0000000000000040ull
+#define AMD_FAMILY_OR   (AMD_FAMILY_15)
+
+// Family 16h equates
+#define AMD_FAMILY_16   0x0000000000000080ull
+#define AMD_FAMILY_WF   (AMD_FAMILY_16)
+
+// Family Unknown
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
+
+// Family Group equates
+#define AMD_FAMILY_GE_12   (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16)
+
+// Family 10h CPU_LOGICAL_ID.Revision equates
+  // Family 10h RB steppings
+#define AMD_F10_RB_C0      0x0000000000000001ull
+#define AMD_F10_RB_C1      0x0000000000000002ull
+#define AMD_F10_RB_C2      0x0000000000000004ull
+#define AMD_F10_RB_C3      0x0000000000000008ull
+  // Family 10h BL steppings
+#define AMD_F10_BL_C2      0x0000000000000010ull
+#define AMD_F10_BL_C3      0x0000000000000020ull
+  // Family 10h DA steppings
+#define AMD_F10_DA_C2      0x0000000000000040ull
+#define AMD_F10_DA_C3      0x0000000000000080ull
+  // Family 10h HY SCM steppings
+#define AMD_F10_HY_SCM_D0  0x0000000000000100ull
+#define AMD_F10_HY_SCM_D1  0x0000000000000400ull
+  // Family 10h HY MCM steppings
+#define AMD_F10_HY_MCM_D0  0x0000000000000200ull
+#define AMD_F10_HY_MCM_D1  0x0000000000000800ull
+
+  // Family 10h Unknown stepping
+#define AMD_F10_UNKNOWN    0x8000000000000000ull
+
+  // Family 10h Miscellaneous equates
+#define AMD_F10_C0 (AMD_F10_RB_C0)
+#define AMD_F10_C1 (AMD_F10_RB_C1)
+#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2)
+#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3)
+#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3)
+
+#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3)
+
+#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3)
+#define AMD_F10_BL_Cx  (AMD_F10_BL_C2 | AMD_F10_BL_C3)
+
+#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3)
+#define AMD_F10_DA_Cx  (AMD_F10_DA_C2 | AMD_F10_DA_C3)
+
+#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0)
+#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1)
+#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1)
+
+#define AMD_F10_HY_ALL (AMD_F10_Dx)
+#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1)
+
+#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx)
+#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx)
+#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx)
+#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx)
+#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx)
+#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0)
+
+#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_UNKNOWN)
+
+// Family 12h CPU_LOGICAL_ID.Revision equates
+  // Family 12h LN steppings
+#define AMD_F12_LN_A0    0x0000000000000001ull
+  // Family 12h Unknown stepping
+#define AMD_F12_UNKNOWN  0x8000000000000000ull
+
+#define AMD_F12_ALL (AMD_F12_LN_A0 | AMD_F12_UNKNOWN)
+
+// Family 14h CPU_LOGICAL_ID.Revision equates
+  // Family 14h ON steppings
+#define AMD_F14_ON_A0    0x0000000000000001ull
+  // Family 14h Unknown stepping
+#define AMD_F14_UNKNOWN  0x8000000000000000ull
+
+#define AMD_F14_ALL (AMD_F14_ON_A0 | AMD_F14_UNKNOWN)
+
+// Family 15h CPU_LOGICAL_ID.Revision equates
+// TBD
+
+// Family 16h CPU_LOGICAL_ID.Revision equates
+// TBD
+
+#endif      // _CPU_FAM_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
new file mode 100755
index 0000000000..995f48357c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
@@ -0,0 +1,210 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Preserve Registers used for AP Mailbox.
+ *
+ * Save and Restore the normal feature content of the registers being used for
+ * the AP Mailbox.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "PreserveMailbox.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  The contents of the mailbox registers should always be preserved.
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Always TRUE
+ *
+ */
+BOOLEAN
+STATIC
+IsPreserveAroundMailboxEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Save and Restore or Initialize the content of the mailbox registers.
+ *
+ * The registers used for AP mailbox should have the content related to their function
+ * preserved.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+PreserveMailboxes (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;
+  UINT32 Socket;
+  UINT32 Module;
+  PCI_ADDR BaseAddress;
+  PCI_ADDR MailboxRegister;
+  PCI_ADDR *NextRegister;
+  AGESA_STATUS IgnoredStatus;
+  AGESA_STATUS HeapStatus;
+  UINT32 Value;
+  ALLOCATE_HEAP_PARAMS AllocateParams;
+  LOCATE_HEAP_PTR LocateParams;
+  UINT32 RegisterEntryIndex;
+
+  BaseAddress.AddressValue = ILLEGAL_SBDFO;
+
+  if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {
+    AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
+    AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));
+    AllocateParams.Persist = HEAP_SYSTEM_MEM;
+    HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);
+    ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));
+    LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);
+    RegisterEntryIndex = 0;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
+          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+          NextRegister = FamilySpecificServices->RegisterList;
+          while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
+            ASSERT (RegisterEntryIndex <
+                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
+            MailboxRegister = BaseAddress;
+            MailboxRegister.Address.Function = NextRegister->Address.Function;
+            MailboxRegister.Address.Register = NextRegister->Address.Register;
+            LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
+            (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;
+            RegisterEntryIndex++;
+            NextRegister++;
+          }
+        }
+      }
+    }
+  } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {
+    LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
+    HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);
+    ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));
+    RegisterEntryIndex = 0;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
+          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+          NextRegister = FamilySpecificServices->RegisterList;
+          while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
+            ASSERT (RegisterEntryIndex <
+                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
+            MailboxRegister = BaseAddress;
+            MailboxRegister.Address.Function = NextRegister->Address.Function;
+            MailboxRegister.Address.Register = NextRegister->Address.Register;
+            if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {
+              Value = 0;
+            } else {
+              Value = (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex];
+            }
+            LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);
+            RegisterEntryIndex++;
+            NextRegister++;
+          }
+        }
+      }
+    }
+    HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox =
+{
+  PreserveAroundMailbox,
+  (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsPreserveAroundMailboxEnabled,
+  PreserveMailboxes
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.h
new file mode 100755
index 0000000000..f23a12da78
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.h
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Preserve Registers used for AP Mailbox.
+ *
+ * Save and Restore the normal feature content of the registers being used for
+ * the AP Mailbox.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _PRESERVE_MAILBOX_H_
+#define _PRESERVE_MAILBOX_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#define MAX_PRESERVE_REGISTER_ENTRIES 2      ///< There is room on the heap for up to this per node. 
+
+/// Reference to a save buffer.
+typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES];
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Descriptor for family specific save-restore.
+ *
+ * Provide a list of the register offsets to save-restore on each node.  Optionally, zero the
+ * register instead of restoring it.
+ */
+typedef struct  {
+  UINT16          Revision;                        ///< Interface version
+  // Public Data.
+  BOOLEAN   IsZeroOnCold;                          ///< On a cold boot, zero the register instead of restore.
+  PCI_ADDR *RegisterList;                          ///< The list of registers, terminated by ILLEGAL_SBDFO.
+} PRESERVE_MAILBOX_FAMILY_SERVICES;
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _PRESERVE_MAILBOX_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
new file mode 100755
index 0000000000..12c6944f81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
@@ -0,0 +1,200 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU C6 feature support code.
+ *
+ * Contains code that declares the AGESA CPU C6 related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMultiSocket.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableC6OnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should C6 be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 is supported.
+ * @retval       FALSE              C6 cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsC6FeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32             Socket;
+  BOOLEAN            IsEnabled;
+  C6_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->CStateMode == CStateModeC6) {
+    ASSERT (PlatformConfig->CStatePlatformData < 0x10000);
+    ASSERT (PlatformConfig->CStatePlatformData != 0);
+    if ((PlatformConfig->CStatePlatformData != 0) && (PlatformConfig->CStatePlatformData <= 0xFFF8)) {
+      IsEnabled = TRUE;
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (IsProcessorPresent (Socket, StdHeader)) {
+          GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+          if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, StdHeader)) {
+            IsEnabled = FALSE;
+            break;
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the C6 C-state
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeC6Feature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK      TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable C6 on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableC6OnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  C6_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeC6 (FamilyServices,
+                                *((UINT64 *) EntryPoint),
+                                &CpuEarlyParams->PlatformConfig,
+                                StdHeader);
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State =
+{
+  C6Cstate,
+  (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsC6FeatureEnabled,
+  InitializeC6Feature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
new file mode 100755
index 0000000000..cbaf3ad8dc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
@@ -0,0 +1,198 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU C6 Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C6 related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_C6_STATE_H_
+#define _CPU_C6_STATE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _C6_FAMILY_SERVICES C6_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// Defines for CST ACPI Objects
+#define   CST_NAME__            '_'
+#define   CST_NAME_C            'C'
+#define   CST_NAME_S            'S'
+#define   CST_NAME_T            'T'
+#define   CST_LENGTH            (CST_BODY_SIZE - 1)
+#define   CST_NUM_OF_ELEMENTS   0x02
+#define   CST_COUNT             0x01
+#define   CST_PKG_LENGTH        (CST_BODY_SIZE - 5) // CST_BODY_SIZE - PkgHeader - Count Buffer
+#define   CST_PKG_ELEMENTS      0x04
+#define   CST_SUBPKG_LENGTH     0x14
+#define   CST_SUBPKG_ELEMENTS   0x0A
+#define   CST_GDR_LENGTH        0x000C
+#define   CST_C2_TYPE           0x02
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* AML code definition */
+
+/// CST Header
+typedef struct _CST_HEADER_STRUCT {
+  UINT8   NameOpcode;      ///< Name Opcode
+  UINT8   CstName_a__;     ///< String "_"
+  UINT8   CstName_a_C;     ///< String "C"
+  UINT8   CstName_a_S;     ///< String "S"
+  UINT8   CstName_a_T;     ///< String "T"
+} CST_HEADER_STRUCT;
+#define CST_HEADER_SIZE 5
+
+/// CST Body
+typedef struct _CST_BODY_STRUCT {
+  UINT8   PkgOpcode;       ///< Package Opcode
+  UINT8   PkgLength;       ///< Package Length
+  UINT8   PkgElements;     ///< Number of Elements
+  UINT8   Count;           ///< Number of Cstate info packages
+  UINT8   PkgOpcode2;      ///< Package Opcode
+  UINT8   PkgLength2;      ///< Package Length
+  UINT8   PkgElements2;    ///< Number of Elements
+  UINT8   BufferOpcode;    ///< Buffer Opcode
+  UINT8   BufferLength;    ///< Buffer Length
+  UINT8   BufferElements;  ///< Number of Elements
+  UINT8   BufferOpcode2;   ///< Buffer Opcode
+  UINT8   GdrOpcode;       ///< Generic Register Descriptor Opcode
+  UINT16  GdrLength;       ///< Descriptor Length
+  UINT8   AddrSpaceId;     ///< Address Space ID
+  UINT8   RegBitWidth;     ///< Register Bit Width
+  UINT8   RegBitOffset;    ///< Register Bit Offset
+  UINT8   AddressSize;     ///< Address Size
+  UINT64  RegisterAddr;    ///< Register Address
+  UINT16  EndTag;          ///< End Tag Descriptor
+  UINT8   BytePrefix;      ///< Byte Prefix Opcode
+  UINT8   Type;            ///< Type
+  UINT8   BytePrefix2;     ///< Byte Prefix Opcode
+  UINT8   Latency;         ///< Latency
+  UINT8   Power;           ///< Power
+} CST_BODY_STRUCT;
+#define CST_BODY_SIZE 33
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if C6 is supported.
+ *
+ * @param[in]    C6Services         C6 C-state services.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 is supported.
+ * @retval       FALSE              C6 is not supported.
+ *
+ */
+typedef BOOLEAN F_C6_IS_SUPPORTED (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT32             Socket,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable C6.
+ *
+ * @param[in]    C6Services         C6 services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_C6_INIT (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+typedef UINT32 F_C6_GET_CST_SIZE (
+  IN      VOID
+  );
+
+typedef VOID F_C6_CREATE_CST (
+  IN OUT   VOID              **PstateAcpiBufferPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_INIT *PF_C6_INIT;
+typedef F_C6_GET_CST_SIZE *PF_C6_GET_CST_SIZE;
+typedef F_C6_CREATE_CST   *PF_C6_CREATE_CST;
+
+/**
+ * Provide the interface to the C6 Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _C6_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_C6_IS_SUPPORTED IsC6Supported;                                     ///< Method: Family specific call to check if C6 is supported.
+  PF_C6_INIT InitializeC6;                                              ///< Method: Family specific call to enable C6.
+  PF_C6_GET_CST_SIZE  GetAcpiCstObj;                                    ///< Method: Family specific call to return the size of ACPI CST objects.
+  PF_C6_CREATE_CST    CreateAcpiCstObj;                                 ///< Method: Family specific call to create ACPI CST object
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_C6_STATE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
new file mode 100755
index 0000000000..48e5a93568
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -0,0 +1,185 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should cache flush on halt be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               core leveling is supported.
+ * @retval       FALSE              core leveling cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCFOHEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return (TRUE);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  InitializeCacheFlushOnHaltFeature
+ *
+ *    CPU feature leveling. Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       EntryPoint       Timepoint designator.
+ *    @param[in]       PlatformConfig   Contains the runtime modifiable feature input data.
+ *    @param[in,out]   StdHeader        Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @return          The most severe status of any family specific service.
+ */
+STATIC AGESA_STATUS
+InitializeCacheFlushOnHaltFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 AndMask;
+  UINT32 OrMask;
+  UINT32 PciRegister;
+  PCI_ADDR PciAddress;
+  PCI_ADDR CfohPciAddress;
+  AGESA_STATUS AgesaStatus;
+  CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices;
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  FamilySpecificServices = NULL;
+  AndMask = 0xFFFFFFFF;
+  OrMask = 0x00000000;
+  PciRegister = 0;
+  AgesaStatus = AGESA_SUCCESS;
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+
+      // Get services for the socket
+      GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+      if (FamilySpecificServices != NULL) {
+        FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader);
+
+        // Get the Or Mask value from IDS
+        IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
+
+        // Set Cache Flush On Halt register
+        for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+          if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+            PciAddress.Address.Function = CfohPciAddress.Address.Function;
+            PciAddress.Address.Register = CfohPciAddress.Address.Register;
+            LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+            PciRegister &= AndMask;
+            PciRegister |= OrMask;
+            LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt =
+{
+  CacheFlushOnHalt,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsCFOHEnabled,
+  InitializeCacheFlushOnHaltFeature
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
new file mode 100755
index 0000000000..10f4f5c4f1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
@@ -0,0 +1,541 @@
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Topology.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCacheInit.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *             L2 cache Association to Way translation table
+ *----------------------------------------------------------------------------
+ */
+CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] =
+{
+  0,
+  1,
+  2,
+  0xFF,
+  4,
+  0xFF,
+  8,
+  0xFF,
+  16,
+  0xFF,
+  32,
+  48,
+  64,
+  96,
+  128,
+  0xFF,
+};
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT8
+STATIC
+Ceiling (
+  IN UINT32 Divisor,
+  IN UINT32 Dividend
+  );
+
+UINT32
+STATIC
+CalculateOccupyExeCache (
+  IN AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will setup ROM execution cache.
+ *
+ * This function should only be called once.  The execution cache regions are passed
+ * in, the max number of execution cache regions are three.  If the start address of
+ * all three regions are zero, then no execution cache is allocated.
+ *
+ *   -1  available cache size is less than requested, the ROM execution cache
+ *       region is reduced or eliminated.
+ *   -2  at least one execution cache regions across the 1MB line, the ROM execution
+ *       cache size is reduced.
+ *   -3  at least one execution cache regions across the 4GB line, the ROM execution
+ *       cache size is reduced.
+ *   -4  the start address of a region is not at the boundary of cache size
+ *   -5  execution cache start address less than D0000
+ *   -6  more than 2 execution cache regions are above 1MB
+ *
+ * @param[in]   StdHeader          Handle to config for library and services
+ * @param[in]   AmdExeAddrMapPtr   Pointer to the start of EXECUTION_CACHE_REGION array
+ *
+ * @retval      AGESA_SUCCESS      No error
+ * @retval      AGESA_WARNING      AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB;
+ *                                 AGESA_CACHE_REGIONS_ACROSS_4GB;
+ * @retval      AGESA_ERROR        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY;
+ *                                 AGESA_CACHE_START_ADDRESS_LESS_D0000;
+ *                                 AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
+ *
+ * @todo on Tilapia, this routine returns AGESA_ERROR.
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+  IN AMD_CONFIG_PARAMS *StdHeader,
+  IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  AGESA_STATUS               AgesaStatus;
+  AMD_GET_EXE_SIZE_PARAMS    AmdGetExeSize;
+  UINT64                     MsrData;
+  UINT32                     RemainingExecutionCacheSize;
+  UINT32                     VariableMttrBase;
+  UINT32                     AgesaInfo;
+  UINT32                     StartAddr;
+  UINT32                     ExeCacheSize;
+  UINT32                     StartFixMtrr;
+  UINT32                     CurrentMtrr;
+  UINT32                     EndFixMtrr;
+  UINT32                     CurrentAllocatedExeCacheSize;
+  UINT8                      i;
+  UINT8                      Ignored;
+  UINT64                     OccupyExeCacheStartAddr;
+  UINT64                     OccupExeCacheSize;
+  CACHE_INFO                 *CacheInfoPtr;
+  CPU_SPECIFIC_SERVICES      *FamilySpecificServices;
+
+  //
+  // if start address of all three regions are zero, then the default values are used
+  //
+  if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) {
+    if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) {
+      if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) {
+        // No regions defined by the caller
+        return AGESA_SUCCESS;
+      }
+    }
+  }
+
+  // turn on modification bit
+  LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+  MsrData |= 0x80000;
+  LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+  // get available L2 cache size for ROM execution
+  AmdGetExeSize.StdHeader = *StdHeader;
+  AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize);
+  RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize;
+  CurrentAllocatedExeCacheSize = CalculateOccupyExeCache (StdHeader);
+  if (CurrentAllocatedExeCacheSize >= RemainingExecutionCacheSize) {
+    RemainingExecutionCacheSize = 0;
+  } else {
+    RemainingExecutionCacheSize = RemainingExecutionCacheSize - CurrentAllocatedExeCacheSize;
+  }
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader);
+
+  // Setup MTTRs for region 0 to region 2
+  VariableMttrBase = AMD_MTRR_VARIABLE_BASE6;
+  for (i = 0; i < 3; i++) {
+    // Exit if no more cache available
+    if (RemainingExecutionCacheSize == 0) {
+      break;
+    }
+
+    // Skip the region if ExeCacheSize = 0
+    if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) {
+      continue;
+    }
+
+    // Calculate available execution cache size for region 0 to 2
+    if (RemainingExecutionCacheSize >= AmdExeAddrMapPtr[i].ExeCacheSize) {
+      RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize;
+    } else {
+      AgesaStatus = AGESA_WARNING;
+      AgesaInfo = AGESA_CACHE_SIZE_REDUCED;
+      AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize;
+      RemainingExecutionCacheSize = 0;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+    }
+
+    // Align starting addresses on 32K boundary
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr =
+      AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000;
+
+    // Boundary alignment check mechanism
+    if ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) {
+      AgesaStatus = AGESA_ERROR;
+      AgesaInfo = AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      break;
+    }
+
+    // Check start address
+    if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) {
+      AgesaStatus = AGESA_ERROR;
+      AgesaInfo = AGESA_CACHE_START_ADDRESS_LESS_D0000;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      break;
+    }
+
+    StartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
+    ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize;
+
+    ExeCacheSize --;
+
+    if (StartAddr < 0x100000) {
+      // Region below 1MB
+      // Fixed MTTR region
+      if ((StartAddr + ExeCacheSize) > 0xFFFFF) {
+        ExeCacheSize = 0xFFFFF - StartAddr;
+        AgesaStatus = AGESA_WARNING;
+        AgesaInfo = AGESA_CACHE_REGIONS_ACROSS_1MB;
+        AmdExeAddrMapPtr[i].ExeCacheSize = ExeCacheSize + 1;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                     i, StartAddr, ExeCacheSize, 0, StdHeader);
+      }
+
+      // Find start and end of MTTR
+      StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7);
+      EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7);
+
+      //
+      //Check Mtrr before we use it, if Mtrr has been used, we need to add RemainingExecutionCacheSize back.
+      //
+      for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
+        LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader);
+        if (MsrData != 0) {
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000;
+        }
+      }
+
+      // Setup MTTRs
+      MsrData = WP_IO;
+      for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
+        LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader);
+      }
+    } else {
+      // Region above 1MB
+      // Variable MTTR region
+      if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) {
+        AgesaStatus = AGESA_ERROR;
+        AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                     i, StartAddr, ExeCacheSize, 0, StdHeader);
+        continue;
+      }
+      if ((0xFFFFFFFF - StartAddr) < ExeCacheSize) {
+        ExeCacheSize = 0xFFFFFFFF - StartAddr;
+        AgesaStatus = AGESA_WARNING;
+        AgesaInfo = AGESA_CACHE_REGIONS_ACROSS_4GB;
+        AmdExeAddrMapPtr[i].ExeCacheSize = ExeCacheSize + 1;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                     i, StartAddr, ExeCacheSize, 0, StdHeader);
+      }
+
+      //
+      //Check Mtrr before we use it.
+      //
+      LibAmdMsrRead (VariableMttrBase, &MsrData, StdHeader);
+      if (MsrData != 0) {
+
+        //
+        //Check expanded
+        //
+        OccupyExeCacheStartAddr = MsrData & (0xFFFF8000);
+        LibAmdMsrRead ((VariableMttrBase + 1), &MsrData, StdHeader);
+        OccupExeCacheSize = (~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000;
+
+        //
+        //Region below || Region above
+        //
+        if ( ((StartAddr + ExeCacheSize + 1) <= OccupyExeCacheStartAddr) ||
+             (StartAddr >= (OccupyExeCacheStartAddr + OccupExeCacheSize)) ) {
+          //
+          //Not overlap the original one, but it need to re-process and set an pair of empty Mtrr
+          //
+          VariableMttrBase += 2;
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + AmdExeAddrMapPtr[i].ExeCacheSize;
+          //
+          //Resume loop count
+          //
+          i--;
+          continue;
+        } else if (OccupyExeCacheStartAddr == StartAddr) {
+
+          //
+          //Overlap with same start address
+          //
+          if (OccupExeCacheSize > (ExeCacheSize + 1)) {
+            //AgesaInfo = AGESA_DEALLOCATE_CACHE_REGIONS;
+            break;
+          }
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + (UINT32)OccupExeCacheSize;
+        } else {
+          //
+          //Overlap with different start address
+          //
+          //AgesaInfo = AGESA_DEALLOCATE_CACHE_REGIONS;
+          break;
+        }
+      }
+
+      MsrData = (UINT64) (StartAddr | (WP_IO & 0xFull));
+
+      LibAmdMsrWrite (VariableMttrBase, &MsrData, StdHeader);
+      MsrData = (UINT64) ( 0xFFFFFFFF00000000ull | ((0xFFFFFFFFull - ExeCacheSize) | 0x800ull));
+      MsrData &= CacheInfoPtr->VariableMtrrMask;
+      LibAmdMsrWrite ((VariableMttrBase + 1), &MsrData, StdHeader);
+      VariableMttrBase += 2;
+    }
+  }
+
+  // Turn on MTTR enable bit and turn off modification bit
+  LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+  MsrData &= 0xFFFFFFFFFFF7FFFFull;
+  LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function calculates available L2 cache space for ROM execution.
+ *
+ * @param[in]   AmdGetExeSizeParams  Pointer to the start of AmdGetExeSizeParamsPtr structure
+ *
+ * @retval      AGESA_SUCCESS      No error
+ * @retval      AGESA_ALERT        No cache available for execution cache.
+ *
+ */
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  )
+{
+  UINT8     WayUsedForCar;
+  UINT8     L2Assoc;
+  UINT32    L2Size;
+  UINT32    L2WaySize;
+  UINT32    CurrentCoreNum;
+  UINT8     L2Ways;
+  UINT8     Ignored;
+  UINT32    DieNumber;
+  UINT32    TotalCores;
+  CPUID_DATA  CpuIdDataStruct;
+  CACHE_INFO  *CacheInfoPtr;
+  AP_MAIL_INFO ApMailboxInfo;
+  AGESA_STATUS IgnoredStatus;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
+
+  // Check for L2 cache size and way size
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader);
+  L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F);
+
+  // get L2Ways from L2 Association to Way translation table
+  L2Ways = L2AssocToL2WayTranslationTable[L2Assoc];
+  ASSERT (L2Ways != 0xFF);
+
+  // get L2Size
+  L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF);
+
+  // get each L2WaySize
+  L2WaySize = L2Size / L2Ways;
+
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
+
+  // Determine the size for execution cache
+  if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) {
+    // BSC (Boot Strap Core)
+    WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) +
+                    Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
+                    Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                    Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+  } else {
+    // AP (Application Processor)
+    GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader);
+
+    GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader);
+    DieNumber = (1 << ApMailboxInfo.Fields.ModuleType);
+    GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader);
+    ASSERT ((TotalCores % DieNumber) == 0);
+    if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) {
+      WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) +
+                      Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
+                      Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                      Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+    } else {
+      WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) +
+                      Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                      Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+    }
+  }
+
+  ASSERT (WayUsedForCar < L2Ways);
+
+  if (WayUsedForCar < L2Ways) {
+    AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar);
+    return AGESA_SUCCESS;
+  } else {
+    AmdGetExeSizeParams->AvailableExeCacheSize = 0;
+    return AGESA_ALERT;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function rounds a quotient up if the remainder is not zero.
+ *
+ * @param[in]   Divisor            The divisor
+ * @param[in]   Dividend           The dividend
+ *
+ * @retval      Value              Rounded quotient
+ *
+ */
+UINT8
+STATIC
+Ceiling (
+  IN UINT32 Divisor,
+  IN UINT32 Dividend
+  )
+{
+  if ((Divisor % Dividend) == 0) {
+    return (UINT8) (Divisor / Dividend);
+  } else {
+    return (UINT8) ((Divisor / Dividend) + 1);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function calculates the amount of cache that has already been allocated on the
+ * executing core.
+ *
+ * @param[in]   StdHeader       Handle to config for library and services
+ *
+ * @retval      Value              Allocated size in bytes
+ *
+ */
+UINT32
+STATIC
+CalculateOccupyExeCache (
+  IN AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64                     OccupExeCacheSize;
+  UINT64                     MsrData;
+  UINT8                      i;
+
+  MsrData = 0;
+  OccupExeCacheSize = 0;
+
+  //
+  //Calculate Variable MTRR base 6~7
+  //
+  for (i = 0; i < 2; i++) {
+    LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader);
+    if (MsrData != 0) {
+      LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader);
+      OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000);
+    }
+  }
+
+  //
+  //Calculate Fixed MTRR base D0000~F8000
+  //
+  for (i = 0; i < 6; i++) {
+    LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader);
+    if (MsrData!= 0) {
+      OccupExeCacheSize = OccupExeCacheSize + 0x8000;
+    }
+  }
+
+  return (UINT32)OccupExeCacheSize;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
new file mode 100755
index 0000000000..c4f51b7db7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_CACHE_INIT_H_
+#define _CPU_CACHE_INIT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define AMD_MTRR_FIX4K_BASE     0x268
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_VARIABLE_BASE7 0x20E
+
+#define WP_IO 0x0505050505050505ull
+
+#define AGESA_CACHE_SIZE_REDUCED              1
+#define AGESA_CACHE_REGIONS_ACROSS_1MB        2
+#define AGESA_CACHE_REGIONS_ACROSS_4GB        3
+#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY  4
+#define AGESA_CACHE_START_ADDRESS_LESS_D0000  5
+#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB   6
+#define AGESA_DEALLOCATE_CACHE_REGIONS        7
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Cache Information
+typedef struct {
+  IN       UINT32  BspStackSize;              ///< Stack size of BSP
+  IN       UINT32  Core0StackSize;            ///< Stack size of primary cores
+  IN       UINT32  Core1StackSize;            ///< Stack size of all non primary cores
+  IN       UINT32  MemTrainingBufferSize;     ///< Memory training buffer size
+  IN       UINT32  SharedMemSize;             ///< Shared memory size
+  IN       UINT64  VariableMtrrMask;          ///< Mask to apply before variable MTRR writes
+} CACHE_INFO;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+  IN AMD_CONFIG_PARAMS *StdHeader,
+  IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  );
+
+#endif  // _CPU_CACHE_INIT_H_
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
new file mode 100755
index 0000000000..bdb26abce7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -0,0 +1,283 @@
+/**
+ * @file
+ *
+ * AMD CPU Core Leveling Function.
+ *
+ * Contains code to Level the number of core in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "AMD.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuEarlyInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should core leveling be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               core leveling is supported.
+ * @retval       FALSE              core leveling cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCoreLevelingEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CORE_LEVELING_TYPE  CoreLevelMode;
+
+  CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
+  if (CoreLevelMode != CORE_LEVEL_NONE) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs core leveling for the system.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter.
+ * The possible modes are:
+ *    -1    CORE_LEVEL_LOWEST            Level to lowest common denominator
+ *    -2    CORE_LEVEL_TWO               Level to 2 cores
+ *    -3    CORE_LEVEL_POWER_OF_TWO      Level to 1,2,4 or 8
+ *    -4    CORE_LEVEL_NONE              Do no leveling
+ *
+ * @param[in]  EntryPoint        Timepoint designator.
+ * @param[in]  PlatformConfig    Contains the leveling mode parameter
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+STATIC AGESA_STATUS
+CoreLevelingAtEarly (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    NumberOfSockets;
+  UINT32    NumberOfModules;
+  UINT32    MinCoreCountOnNode;
+  UINT32    MaxCoreCountOnNode;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    LeveledCores;
+  UINT32    RequestedCores;
+  UINT32    TotalEnabledCoresOnNode;
+  AP_MAIL_INFO ApMailboxInfo;
+  CORE_LEVELING_TYPE  CoreLevelMode;
+  CPU_CORE_LEVELING_FAMILY_SERVICES  *FamilySpecificServices;
+
+  MaxCoreCountOnNode = 0;
+  MinCoreCountOnNode = 0xFFFFFFFF;
+  LeveledCores = 0;
+
+  ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax);
+
+  // Get OEM IO core level mode
+  CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
+
+  // Get socket count
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1;
+
+  // Collect cpu core info
+  // Get the highest and lowest core count in all nodes
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      for (Module = 0; Module < NumberOfModules; Module++) {
+        if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+          TotalEnabledCoresOnNode = HighCore - LowCore + 1;
+          if (TotalEnabledCoresOnNode < MinCoreCountOnNode) {
+            MinCoreCountOnNode = TotalEnabledCoresOnNode;
+          }
+          if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) {
+            MaxCoreCountOnNode = TotalEnabledCoresOnNode;
+          }
+        }
+      }
+    }
+  }
+
+  // Get LeveledCores
+  switch (CoreLevelMode) {
+  case CORE_LEVEL_LOWEST:
+    if (MinCoreCountOnNode == MaxCoreCountOnNode) {
+      return (AGESA_SUCCESS);
+    }
+    LeveledCores = MinCoreCountOnNode;
+    break;
+  case CORE_LEVEL_TWO:
+    LeveledCores = 2 / NumberOfModules;
+    if (LeveledCores != 0) {
+      LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
+    } else {
+      return (AGESA_WARNING);
+    }
+    if ((LeveledCores * NumberOfModules) != 2) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      2, (LeveledCores * NumberOfModules), 0, 0, StdHeader
+      );
+    }
+    break;
+  case CORE_LEVEL_POWER_OF_TWO:
+    // Level to power of 2 (1, 2, 4, 8...)
+    LeveledCores = 1;
+    while (MinCoreCountOnNode >= (LeveledCores * 2)) {
+      LeveledCores = LeveledCores * 2;
+    }
+    break;
+  case CORE_LEVEL_ONE:
+    LeveledCores = 1;
+    break;
+  case CORE_LEVEL_THREE:
+  case CORE_LEVEL_FOUR:
+  case CORE_LEVEL_FIVE:
+  case CORE_LEVEL_SIX:
+  case CORE_LEVEL_SEVEN:
+  case CORE_LEVEL_EIGHT:
+  case CORE_LEVEL_NINE:
+  case CORE_LEVEL_TEN:
+  case CORE_LEVEL_ELEVEN:
+  case CORE_LEVEL_TWELVE:
+  case CORE_LEVEL_THIRTEEN:
+  case CORE_LEVEL_FOURTEEN:
+  case CORE_LEVEL_FIFTEEN:
+    RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3;
+    LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules;
+    LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
+    if ((LeveledCores * NumberOfModules) != RequestedCores) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      RequestedCores, (LeveledCores * NumberOfModules), 0, 0, StdHeader
+      );
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+
+  // Set down core register
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+      if (FamilySpecificServices != NULL) {
+        for (Module = 0; Module < NumberOfModules; Module++) {
+          FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, StdHeader);
+        }
+      }
+    }
+  }
+
+  return (AGESA_SUCCESS);
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
+{
+  CoreLeveling,
+  (CPU_FEAT_AFTER_PM_INIT),
+  IsCoreLevelingEnabled,
+  CoreLevelingAtEarly
+};
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L      F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
new file mode 100755
index 0000000000..9e7ea86ec0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
@@ -0,0 +1,694 @@
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionDmi.h"
+#include "cpuLateInit.h"
+#include "cpuServices.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_DMI_CONFIGURATION    OptionDmiConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+AdjustGranularity (
+  IN UINT32 *CacheSizePtr
+  );
+
+VOID
+STATIC
+IntToString (
+  IN OUT   CHAR8 *String,
+  IN       UINT8 *Integer,
+  IN       UINT8 SizeInByte
+);
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetDmiInfoStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  );
+AGESA_STATUS
+GetDmiInfoMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  );
+AGESA_STATUS
+ReleaseDmiBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+AGESA_STATUS
+ReleaseDmiBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CreateDmiRecords
+ *
+ *  Description:
+ *     This function creates DMI/SMBios records pertinent to the processor
+ *     SMBIOS type 4, type 7, and type 40.
+ *
+ *  Parameters:
+ *    @param[in, out]  *StdHeader
+ *    @param[in, out]  **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+CreateDmiRecords (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader);
+  return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  GetDmiInfoStub
+ *
+ *  Description:
+ *     This is the default routine for use when the DMI option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *    @param[in, out]    **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+GetDmiInfoStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  GetDmiInfoMain
+ *
+ *  Description:
+ *     This is the common routine for getting Dmi type4 and type7 CPU related information.
+ *
+ *  Parameters:
+ *    @param[in, out]  *StdHeader
+ *    @param[in, out]  **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+GetDmiInfoMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  UINT8  Socket;
+  UINT8  Channel;
+  UINT8  Dimm;
+  UINT16 DimmIndex;
+  UINT16 NumberOfDimm;
+  UINT32 PciData;
+  UINT64 MsrData;
+  UINT64 MsrRegister;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS Flag;
+  AGESA_STATUS CalledStatus;
+  AP_EXE_PARAMS ApParams;
+  MEM_DMI_INFO *MemInfo;
+  DMI_T17_MEMORY_TYPE MemType;
+  DMI_INFO *DmiBufferPtr;
+  ALLOCATE_HEAP_PARAMS AllocateHeapParams;
+  LOCATE_HEAP_PTR LocateHeapParams;
+
+  MsrData = 0;
+  Flag = TRUE;
+  DmiBufferPtr = *DmiTable;
+  if (DmiBufferPtr == NULL) {
+    //
+    // Allocate a buffer by heap function
+    //
+    AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE;
+    AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO);
+    AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
+
+    if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+
+    DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr;
+    *DmiTable = DmiBufferPtr;
+  }
+  // Fill with 0x00
+  LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader);
+
+  //
+  // Get CPU information
+  //
+
+  // Run GetType4Type7Info on all core0s.
+  ApParams.StdHeader = *StdHeader;
+  ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7;
+  ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr;
+  ApParams.RelatedBlockLength = sizeof (DMI_INFO);
+  CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader);
+  if (CalledStatus > Flag) {
+    Flag = CalledStatus;
+  }
+  CalledStatus = GetType4Type7Info (&ApParams);
+  if (CalledStatus > Flag) {
+    Flag = CalledStatus;
+  }
+
+  //------------------------------
+  // T Y P E 16 17 19 20
+  //------------------------------
+
+  LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    if (Flag < AGESA_ERROR) {
+      Flag = AGESA_ERROR;
+    }
+  } else {
+    NumberOfDimm = *((UINT16 *) (LocateHeapParams.BufferPtr));
+    MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2));
+    MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+    // TYPE 16
+    DmiBufferPtr->T16.Location = 0x03;
+    DmiBufferPtr->T16.Use = 0x03;
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90);
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    if (PciData == 0) {
+      PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x190);
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    }
+    if ((PciData & 0x00080000) != 0) {
+      DmiBufferPtr->T16.MemoryErrorCorrection = 0x04;
+    } else {
+      DmiBufferPtr->T16.MemoryErrorCorrection = 0x03;
+    }
+
+    LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader);
+    if (MsrData == 0) {
+      LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader);
+      DmiBufferPtr->T16.MaximumCapacity = (UINT32) (MsrData >> 10);
+    } else {
+      DmiBufferPtr->T16.MaximumCapacity = (UINT32) (MsrData >> 10);
+    }
+
+    DmiBufferPtr->T16.NumberOfMemoryDevices = NumberOfDimm;
+
+    // TYPE 17
+    for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) {
+      Socket = (MemInfo + DimmIndex)->Socket;
+      Channel = (MemInfo + DimmIndex)->Channel;
+      Dimm = (MemInfo + DimmIndex)->Dimm;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' ';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0';
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' ';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0';
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode;
+
+      IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2);
+
+      LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader);
+      DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes;
+
+      //TYPE 20
+      DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = 0;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF;
+    }
+
+    // TYPE 19
+    DmiBufferPtr->T19.StartingAddr = 0;
+
+    LibAmdMsrRead (TOP_MEM2, &MsrRegister, StdHeader);
+    if (MsrRegister == 0) {
+      LibAmdMsrRead (TOP_MEM, &MsrRegister, StdHeader);
+      DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
+    } else if (MsrRegister != 0) {
+      DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
+    }
+
+    DmiBufferPtr->T19.PartitionWidth = 0xFF;
+  }
+  return (Flag);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  GetType4Type7Info
+ *
+ *  Description:
+ *    This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables.
+ *
+ *  Parameters:
+ *    @param[in] ApExeParams   Handle to config for library and services.
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *  Processing:
+ *
+ */
+AGESA_STATUS
+GetType4Type7Info (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT8  CpuStepping;
+  UINT16 Index;
+  UINT32 SocketNum;
+  UINT32 CacheSize;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  DMI_INFO *DmiBufferPtr;
+  AGESA_STATUS IgnoredSts;
+  AGESA_STATUS Flag;
+  BOOLEAN FamilyNotFound;
+  CPUID_DATA CpuId;
+  CPU_TYPE_INFO CpuInfo;
+  PROC_FAMILY_TABLE   *ProcData;
+  CPU_LOGICAL_ID LogicalID;
+
+  Flag = TRUE;
+  DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock;
+  GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);
+
+  ProcData = NULL;
+  FamilyNotFound = TRUE;
+  for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) {
+    ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]);
+    if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) {
+      FamilyNotFound = FALSE;
+      break;
+    }
+  }
+
+  if (FamilyNotFound) {
+    return AGESA_ERROR;
+  }
+
+  ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader);
+
+  // ------------------------------
+  // T Y P E 4
+  // ------------------------------
+
+  IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+
+  // Type 4 Offset 0x05, Processor Type
+  DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR;
+
+  // Type 4 Offset 0x06, Processor Family
+  for (Index = 0; Index < ProcData->LenBrandList; Index++) {
+    if ((ProcData->DmiBrandList[Index].PackageType == 'x' || ProcData->DmiBrandList[Index].PackageType == CpuInfo.PackageType) &&
+        (ProcData->DmiBrandList[Index].PgOfBrandId == 'x' || ProcData->DmiBrandList[Index].PgOfBrandId == CpuInfo.BrandId.Pg) &&
+        (ProcData->DmiBrandList[Index].NumberOfCores == 'x' || ProcData->DmiBrandList[Index].NumberOfCores == CpuInfo.TotalCoreNumber) &&
+        (ProcData->DmiBrandList[Index].String1ofBrandId == 'x' || ProcData->DmiBrandList[Index].String1ofBrandId == CpuInfo.BrandId.String1)) {
+      DmiBufferPtr->T4[SocketNum].T4ProcFamily = ProcData->DmiBrandList[Index].ValueSetToDmiTable;
+      break;
+    }
+  }
+
+  if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) {
+    Flag = AGESA_ERROR;
+  }
+
+  // Type4 Offset 0x08, Processor ID
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader);
+  DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg;
+  DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg;
+
+  // Type4 Offset 0x11, Voltage
+  DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader);
+
+  // Tyep4 Offset 0x12, External Clock
+  DmiBufferPtr->T4[SocketNum].T4ExternalClock = EXTERNAL_CLOCK;
+
+  // Type4 Offset 0x14, Max Speed
+  DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader);
+
+  // Type4 Offset 0x16, Current Speed
+  DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed;
+
+  // Type4 Offset 0x18, Status
+
+  // Type4 Offset 0x19, Processor Upgrade
+  DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade;
+
+  // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count
+  DmiBufferPtr->T4[SocketNum].T4CoreCount   = CpuInfo.TotalCoreNumber + 1;
+  DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1;
+  DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1;
+
+  // Type4 Offset 0x26, Processor Characteristics
+  DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS;
+
+  // Type4 Offset 0x28, Processor Family 2
+  DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily;
+
+  // Type4 ProcVersion
+  // BaseModel    ProcVersion
+  //    0~1         A
+  //    2~3         B
+  //    4~7         C
+  //    8~9         D
+  //    A~          E
+  switch (CpuInfo.BaseModel) {
+  case 0:
+  case 1:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x41;
+    break;
+  case 2:
+  case 3:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x42;
+    break;
+  case 4:
+  case 5:
+  case 6:
+  case 7:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x43;
+    break;
+  case 8:
+  case 9:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x44;
+    break;
+  case 0xA:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x45;
+    break;
+  default:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x41;
+  }
+
+  if (CpuInfo.Stepping >= 0xA) {
+    CpuStepping = CpuInfo.Stepping + 0x37;
+  } else {
+    CpuStepping = CpuInfo.Stepping + 0x30;
+  }
+
+  DmiBufferPtr->T4[SocketNum].T4ProcVersion[1] = (CHAR8) CpuStepping;
+  DmiBufferPtr->T4[SocketNum].T4ProcVersion[2] = '\0';
+
+  //------------------------------
+  // T Y P E 7
+  //------------------------------
+
+  // Type7 Offset 0x05, Cache Configuration
+  DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1;
+  DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2;
+  DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3;
+
+  // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size
+  LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, &ApExeParams->StdHeader);
+
+  // Maximum L1 cache size
+  CacheSize = (UINT32) (((UINT8) (CpuId.ECX_Reg >> 24) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfo.EnabledCoreNumber + 1));
+  DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
+
+  // Installed L1 cache size
+  DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize;
+
+  // Maximum L2 cache size
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, &ApExeParams->StdHeader);
+  CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfo.EnabledCoreNumber + 1));
+  DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
+
+  // Installed L2 cache size
+  DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize;
+
+  // Maximum L3 cache size
+  CacheSize = ((CpuId.EDX_Reg >> 18) & 0x3FFF) * 512;
+  DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
+
+  // Installed L3 cache size
+  DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize;
+
+  // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type
+  DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE;
+
+  // Type7 Offset 0x0F, Cache Speed
+  DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1;
+  DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1;
+  DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1;
+
+  // Type7 Offset 0x10, Error Correction Type
+  DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+
+  // Type7 Offset 0x11, System Cache Type
+  DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE;
+
+  // Type7 Offset 0x12, Associativity
+  DmiBufferPtr->T7L1[SocketNum].T7Associativity = ASSOCIATIVE_2_WAY;
+  DmiBufferPtr->T7L2[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY;
+  if (((CpuId.EDX_Reg >> 12) & 0x0F) == ASSOCIATIVE_16_WAY) {
+    DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY;
+  } else {
+    DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_OTHER;
+  }
+  return (Flag);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  AdjustGranularity
+ *
+ *  Description:
+ *    If cache size is greater than or equal to 32M, then set granularity
+ *    to 64K. otherwise, set granularity to 1K
+ *
+ *  Parameters:
+ *    @param[in]    *CacheSizePtr
+ *
+ *    @retval       CacheSize
+ *
+ *  Processing:
+ *
+ */
+UINT16
+STATIC
+AdjustGranularity (
+  IN UINT32 *CacheSizePtr
+  )
+{
+  UINT16 CacheSize;
+
+  if (*CacheSizePtr >= 0x8000) {
+    CacheSize = (UINT16) (*CacheSizePtr / 64);
+    CacheSize |= 0x8000;
+  } else {
+    CacheSize = (UINT16) *CacheSizePtr;
+  }
+
+  return (CacheSize);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseDmiBufferStub
+ *
+ *  Description:
+ *     This is the default routine for use when the DMI option is NOT requested.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseDmiBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseDmiBuffer
+ *
+ *  Description:
+ *     Deallocate DMI buffer
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseDmiBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader);
+
+  return  AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  IntToString
+ *
+ *  Description:
+ *    Translate UINT array to CHAR array.
+ *
+ *  Parameters:
+ *    @param[in, out]    *String       Pointer to CHAR array
+ *    @param[in]         *Integer      Pointer to UINT array
+ *    @param[in]         SizeInByte    The size of UINT array
+ *
+ *  Processing:
+ *
+ */
+VOID
+STATIC
+IntToString (
+  IN OUT   CHAR8 *String,
+  IN       UINT8 *Integer,
+  IN       UINT8 SizeInByte
+  )
+{
+  UINT8 Index;
+
+  for (Index = 0; Index < SizeInByte; Index++) {
+    *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F;
+    *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F;
+  }
+  for (Index = 0; Index < (SizeInByte * 2); Index++) {
+    if (*(String + Index) >= 0x0A) {
+      *(String + Index) += 0x37;
+    } else {
+      *(String + Index) += 0x30;
+    }
+  }
+  *(String + SizeInByte * 2) = 0x0;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
new file mode 100755
index 0000000000..03780ed500
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -0,0 +1,262 @@
+/**
+ * @file
+ *
+ * AMD CPU Feature Leveling Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuPostInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SaveFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+WriteFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+GetGlobalCpuFeatureListAddress (
+     OUT   UINT64            **Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  FeatureLeveling
+ *
+ *    CPU feature leveling. Set least common features set of all CPUs
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+FeatureLeveling (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 BscSocket;
+  UINT32 Ignored;
+  UINT32 BscCore;
+  UINT32 Socket;
+  UINT32 Core;
+  UINT32 NumberOfSockets;
+  UINT32 NumberOfCores;
+  BOOLEAN *FirstTime;
+  BOOLEAN *NeedLeveling;
+  AGESA_STATUS IgnoredSts;
+  CPU_FEATURES_LIST *globalCpuFeatureList;
+  AP_TASK  TaskPtr;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);
+  FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));
+  NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
+
+  *FirstTime = TRUE;
+  *NeedLeveling = FALSE;
+
+  LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      if (Socket !=  BscSocket) {
+        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
+      }
+    }
+  }
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+
+  if (*NeedLeveling) {
+    TaskPtr.FuncAddress.PfApTaskI  = WriteFeatures;
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+        for (Core = 0; Core < NumberOfCores; Core++) {
+          if ((Socket != BscSocket) || (Core != BscCore)) {
+            ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+          }
+        }
+      }
+    }
+    ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+  }
+}
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L      F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  SaveFeatures
+ *
+ *    save least common features set of all CPUs
+ *
+ *    @param[in,out]  cpuFeatureListPtr  - Pointer to CPU Feature List.
+ *    @param[in,out]  StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+SaveFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  WriteFeatures
+ *
+ *    Write out least common features set of all CPUs
+ *
+ *    @param[in,out]  cpuFeatureListPtr  - Pointer to CPU Feature List.
+ *    @param[in,out]  StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+WriteFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  GetGlobalCpuFeatureListAddress
+ *
+ *   Determines the address in system DRAM that should be used for CPU feature leveling.
+ *
+ * @param[out] Address           Address to utilize
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *
+ */
+VOID
+STATIC
+GetGlobalCpuFeatureListAddress (
+     OUT   UINT64            **Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 AddressValue;
+
+  AddressValue = (UINT32)GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
+
+  *Address = (UINT64 *)(AddressValue);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c
new file mode 100755
index 0000000000..e3a0ef99b5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c
@@ -0,0 +1,149 @@
+/**
+ * @file
+ *
+ * Implement general feature dispatcher.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - External General Services API
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[];
+
+/**
+ * Determines if a specific feature is or will be enabled.
+ *
+ * This code traverses the feature list until a match is
+ * found, then invokes the 'IsEnabled' function of the
+ * feature.
+ *
+ * @param[in]       Feature        Indicates the desired feature.
+ * @param[in]       PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in]       StdHeader      Standard AMD configuration parameters.
+ *
+ * @retval         TRUE      Feature is or will be enabled
+ * @retval         FALSE     Feature is not enabled
+ */
+BOOLEAN
+IsFeatureEnabled (
+  IN       DISPATCHABLE_CPU_FEATURES Feature,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINTN i;
+
+  ASSERT (Feature < MaxCpuFeature);
+
+  for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
+    if (SupportedCpuFeatureList[i]->Feature == Feature) {
+      return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader));
+    }
+  }
+  return FALSE;
+}
+
+/**
+ * Dispatches all features needing to perform some initialization at
+ * this time point.
+ *
+ * This routine searches the feature table for features needing to
+ * run at this time point, and invokes them.
+ *
+ * @param[in]      EntryPoint     Timepoint designator
+ * @param[in]      PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in]      StdHeader      Standard AMD configuration parameters.
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+DispatchCpuFeatures (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN i;
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledStatus;
+  AGESA_STATUS IgnoredStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);
+
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
+      if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) {
+        if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) {
+          CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader);
+          if (CalledStatus > AgesaStatus) {
+            AgesaStatus = CalledStatus;
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
new file mode 100755
index 0000000000..698eafdbc8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
@@ -0,0 +1,255 @@
+/**
+ * @file
+ *
+ * Generic CPU feature dispatcher and related services.
+ *
+ * Provides a feature processing engine to handle feature in a
+ * more generic way.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FEATURES_H_
+#define _CPU_FEATURES_H_
+
+/**
+ * @page cpufeatimpl CPU Generic Feature Implementation Guide
+ *
+ * The CPU generic feature dispatcher provides services which can be used to implement a
+ * wide range of features in a manner that isolates calling code from knowledge about which
+ * families or features are supported in the current build.
+ *
+ * @par Determine if a New Feature is a Suitable Candidate
+ *
+ * A feature must meet the following requirements:
+ * <ul>
+ * <li> Any core in the system must be able to determine if the feature should be enabled or not.
+ *
+ *   <ul>
+ *   <li> MSRs cannot be read in multisocket systems in the 'IsEnabled' function.
+ *
+ *   <li> Cores cannot be launched in the 'IsEnabled' function.
+ *   </ul>
+ * </ul>
+ *
+ * @par Determine the Time Point at which the Feature Should be Enabled
+ *
+ * Factors to consider in making this determination:
+ *
+ * <ul>
+ * <li> Determine if there are any dependencies on other settings that require strict ordering.
+ *
+ * <li> Consider the state of the APs that you will need.
+ *
+ * <li> Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume.
+ * </ul>
+ *
+ * @par Implementing a new feature
+ *
+ * Perform the following steps to implement a new feature:
+ *
+ * <ul>
+ * <li> Create a unique equate for your time point, @b if you cannot use an existing time point.
+ *
+ * <li> Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature.
+ *
+ * <li> Add a new 'C' file to the Features folder for your feature.
+ *
+ *   <ul>
+ *   <li> The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize'
+ *
+ *   <li> The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure.
+ *   </ul>
+ *
+ * <li> Add a new 'H' file to the Features folder for your feature.
+ *
+ *   <ul>
+ *   <li> The 'H' file declares whatever family specific functions required by the feature.
+ *
+ *   <li> The 'H' file declares a structure containing all family specific functions.  For a reference
+ *        example, your feature API should have a set of conventions similar to cpu specific services,
+ *        @ref cpuimplfss.
+ *   </ul>
+ *
+ * <li> Create 'C' files in all applicable family folders.
+ *
+ *   <ul>
+ *   <li> Implement the required family specific functions.
+ *
+ *   <li> Instantiate a family specific services structure.
+ *   </ul>
+ *
+ * <li> Create \<feature name\>Install.h in the include folder.
+ *
+ *   <ul>
+ *   <li> Add logic to determine when your feature should be included in the build.
+ *
+ *   <li> If the feature should be included, define OPTION_\<feature name\> to the address of your
+ *        CPU_FEATURE_DESCRIPTOR instantiation.  If not, define OPTION_\<feature name\> to be blank.
+ *
+ *   <li> Create a family translation table pointing to all applicable instantiations of
+ *        family specific function structures.
+ *   </ul>
+ *
+ * <li> Modify OptionCpuFeaturesInstall.h in the include folder.
+ *
+ *   <ul>
+ *   <li> Include \<feature name\>Install.h.
+ *
+ *   <li> Add OPTION_\<feature name\> to the SupportedCpuFeatureList array.
+ *   </ul>
+ *
+ * <li> If a new time point was created, add a call to DispatchCpuFeatures at the desired location,
+ *      passing your new time point equate.
+ * </ul>
+ *
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FEAT_AFTER_PM_INIT          (0x0000000000000001ull)
+#define CPU_FEAT_AFTER_POST_MTRR_SYNC   (0x0000000000000002ull)
+#define CPU_FEAT_INIT_MID_END           (0x0000000000000004ull)
+#define CPU_FEAT_INIT_LATE_END          (0x0000000000000008ull)
+#define CPU_FEAT_S3_LATE_RESTORE_END    (0x0000000000000010ull)
+#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC (0x0000000000000020ull)
+#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000040ull)
+/**
+ * Enumerated list of supported features.
+ */
+typedef enum {
+  HardwareC1e,               ///< Hardware C1e
+  HtAssist,                  ///< Probe filter
+  MsgBasedC1e,               ///< Message-based C1e
+  CoreLeveling,              ///< Core Leveling
+  C6Cstate,                  ///< C6 C-state
+  CacheFlushOnHalt,          ///< Cache Flush On Halt
+  PreserveAroundMailbox,     ///< Save-Restore the registers used for AP mailbox, to preserve their normal function.
+  MaxCpuFeature              ///< Not a valid value, used for verifying input
+} DISPATCHABLE_CPU_FEATURES;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Feature specific call to check if it is supported by the system.
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Feature is supported.
+ * @retval       FALSE              Feature is not supported.
+ *
+ */
+typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  The feature's main entry point for enablement.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE;
+
+
+/**
+ * Generic feature descriptor
+ */
+typedef struct {
+  DISPATCHABLE_CPU_FEATURES Feature;     ///< Enumerated feature ID
+  UINT64                    EntryPoint;  ///< Timepoint designator
+  PF_CPU_FEATURE_IS_ENABLED IsEnabled;   ///< Pointer to the function that checks if the feature is supported
+  PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature
+} CPU_FEATURE_DESCRIPTOR;
+
+/**
+ * Table descriptor for the installed features.
+ */
+typedef struct {
+  UINT8       NumberOfFeats;      ///< Number of valid entries in the table.
+  CPU_FEATURE_DESCRIPTOR *FeatureList;       ///< Pointer to the first element in the array.
+} CPU_FEATURE_TABLE;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+BOOLEAN
+IsFeatureEnabled (
+  IN       DISPATCHABLE_CPU_FEATURES Feature,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+DispatchCpuFeatures (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif // _CPU_FEATURES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
new file mode 100755
index 0000000000..1dead2cabb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
@@ -0,0 +1,344 @@
+/**
+ * @file
+ *
+ * AMD CPU HT Assist Initialization functions.
+ *
+ * Contains code for doing probe filter initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 7284 $   @e \$Date: 2008-08-08 23:29:33 +0800 (Fri, 08 Aug 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Topology.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "cpuHtAssist.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUHTASSIST_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE HtAssistFamilyServiceTable;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should HT Assist be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsHtAssistEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  UINT32           CpuCount;
+  UINT32           Socket;
+  AP_MAILBOXES     ApMailboxes;
+  HT_ASSIST_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->PlatformProfile.UseHtAssist) {
+    CpuCount = GetNumberOfProcessors (StdHeader);
+    ASSERT (CpuCount != 0);
+
+    if (CpuCount == 1) {
+      GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+      if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
+        IsEnabled = TRUE;
+      }
+    } else if (CpuCount > 1) {
+      IsEnabled = TRUE;
+    }
+    if (IsEnabled) {
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (IsProcessorPresent (Socket, StdHeader)) {
+          GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+          if ((FamilyServices == NULL) || !FamilyServices->IsHtAssistSupported (FamilyServices, Socket, StdHeader)) {
+            IsEnabled = FALSE;
+            break;
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the HT Assist feature.
+ *
+ * HT Assist initialization requires the following series of steps.
+ * -# Disable Cache on @b all cores.
+ * -# Initialize Probe Filter PCI regs
+ *    -# Save L3 Scrub Rate
+ *    -# On each node:
+ *       -# Turn off L3Scrubber and Disable L3 cache
+ *    -# On each node:
+ *       -# Enable probe filter
+ *    -# On each node:
+ *       -# Enable L3 cache and turn on Scrubber.
+ *    -# Restore L3 Scrub Rate
+ * -# Enable Cache on @b all cores.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      HT Assist feature is running optimally.
+ * @retval       AGESA_WARNING      HT Assist feature is not running optimally.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeHtAssistFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                     CpuCount;
+  UINT32                     Socket;
+  AGESA_STATUS               AgesaStatus;
+  AP_MAILBOXES               ApMailboxes;
+  AP_EXE_PARAMS              ApParams;
+  UINT32                     Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE];
+  HT_ASSIST_FAMILY_SERVICES  *FamilyServices[MAX_SOCKETS_SUPPORTED];
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // There are many family service call outs.  Initialize the family service array while
+  // cache is still enabled.
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices[Socket], StdHeader);
+    } else {
+      FamilyServices[Socket] = NULL;
+    }
+  }
+
+  if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) {
+    // Check for optimal settings
+    GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+    CpuCount = GetNumberOfProcessors (StdHeader);
+    if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) ||
+        ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) {
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (FamilyServices[Socket] != NULL) {
+          if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) {
+            // Non-optimal settings.  Log an event.
+            AgesaStatus = AGESA_WARNING;
+            PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader);
+            break;
+          }
+        }
+      }
+    }
+  } else {
+    // Disable the scrubbers.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
+      }
+    }
+
+    // Wait for 40us
+    WaitMicroseconds ((UINT32) 40, StdHeader);
+
+    // Run DisableAllCaches on AP cores.
+    ApParams.StdHeader = *StdHeader;
+    ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE;
+    ApParams.RelatedDataBlock = NULL;
+    ApParams.RelatedBlockLength = 0;
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+
+    // Run DisableAllCaches on core 0.
+    DisableAllCaches (&ApParams);
+
+    // Family hook before initialization.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Activate probe filter.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Family hook after initialization.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Run EnableAllCaches on core 0.
+    EnableAllCaches (&ApParams);
+
+    // Run EnableAllCaches on every core.
+    ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE;
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+
+    // Restore the scrubbers.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
+      }
+    }
+  }
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Disable all the caches on current core.
+ *
+ * @param[in] ApExeParams   Handle to config for library and services.
+ *
+ * @retval    AGESA_SUCCESS  Always succeeds.
+ *
+ */
+AGESA_STATUS
+DisableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT32   CR0Data;
+  HT_ASSIST_FAMILY_SERVICES  *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader);
+
+  FamilyServices->HookDisableCache (FamilyServices, &ApExeParams->StdHeader);
+
+  // Disable cache through CR0.
+  LibAmdReadCpuReg (0, &CR0Data);
+  CR0Data |= (0x60000000);
+  LibAmdWriteCpuReg (0, CR0Data);
+
+  // Execute wbinvd
+  LibAmdWriteBackInvalidateCache ();
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Enable all the caches on current core.
+ *
+ * @param[in] ApExeParams    Handle to config for library and services.
+ *
+ * @retval    AGESA_SUCCESS  Always succeeds.
+ *
+ */
+AGESA_STATUS
+EnableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT32   CR0Data;
+  HT_ASSIST_FAMILY_SERVICES  *FamilyServices;
+
+  // Enable cache through CR0.
+  LibAmdReadCpuReg (0, &CR0Data);
+  CR0Data &= ~(0x60000000);
+  LibAmdWriteCpuReg (0, CR0Data);
+
+  GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader);
+
+  FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist =
+{
+  HtAssist,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END),
+  IsHtAssistEnabled,
+  InitializeHtAssistFeature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
new file mode 100755
index 0000000000..0ce6b17574
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
@@ -0,0 +1,278 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU HT Assist Function declarations.
+ *
+ * Contains code that declares the AGESA CPU Probe filter related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_HT_ASSIST_H_
+#define _CPU_HT_ASSIST_H_
+
+#include "Filecode.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _HT_ASSIST_FAMILY_SERVICES HT_ASSIST_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define AP_LATE_TASK_DISABLE_CACHE (0x00000000 | PROC_CPU_FEATURE_CPUHTASSIST_FILECODE)
+#define AP_LATE_TASK_ENABLE_CACHE  (0x00010000 | PROC_CPU_FEATURE_CPUHTASSIST_FILECODE)
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if HT Assist is supported.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist is not supported.
+ *
+ */
+typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific hook before HT Assist is initialized.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_BEFORE_INIT (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_BEFORE_INIT *PF_HT_ASSIST_BEFORE_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_DISABLE_CACHE (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_DISABLE_CACHE *PF_HT_ASSIST_DISABLE_CACHE;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef VOID F_HT_ASSIST_ENABLE_CACHE (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_ENABLE_CACHE *PF_HT_ASSIST_ENABLE_CACHE;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to enable.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_INIT (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_AFTER_INIT (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_AFTER_INIT *PF_HT_ASSIST_AFTER_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to save the L3 scrubber.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_GET_L3_SCRUB_CTRL (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_GET_L3_SCRUB_CTRL *PF_HT_ASSIST_GET_L3_SCRUB_CTRL;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to restore the L3 scrubber.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Contains L3 scrubber settings to restore.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_SET_L3_SCRUB_CTRL (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_SET_L3_SCRUB_CTRL *PF_HT_ASSIST_SET_L3_SCRUB_CTRL;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to restore the L3 scrubber.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       TRUE                The system may be running with non-optimal settings.
+ * @return       FALSE               The system may is running optimally.
+ *
+ */
+typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
+
+
+/**
+ * Provide the interface to the HT Assist Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _HT_ASSIST_FAMILY_SERVICES {
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported;        ///< Method: Check if HT Assist is supported.
+  PF_HT_ASSIST_INIT HtAssistInit;                       ///< Method: Enable HT Assist.
+  PF_HT_ASSIST_GET_L3_SCRUB_CTRL GetL3ScrubCtrl;        ///< Method: Save/disable the L3 scrubber.
+  PF_HT_ASSIST_SET_L3_SCRUB_CTRL SetL3ScrubCtrl;        ///< Method: Restore the L3 scrubber.
+  PF_HT_ASSIST_BEFORE_INIT HookBeforeInit;              ///< Method: Hook before enabling HT Assist.
+  PF_HT_ASSIST_AFTER_INIT HookAfterInit;                ///< Method: Hook after enabling HT Assist.
+  PF_HT_ASSIST_DISABLE_CACHE HookDisableCache;          ///< Method: Core hook just before disabling cache.
+  PF_HT_ASSIST_ENABLE_CACHE HookEnableCache;            ///< Method: Core hook just after enabling cache.
+  PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig;        ///< Method: Check if HT Assist is running optimally.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+DisableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+AGESA_STATUS
+EnableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+#endif  // _CPU_HT_ASSIST_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
new file mode 100755
index 0000000000..49fb9b00a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
@@ -0,0 +1,166 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU HW C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Topology.h"
+#include "cpuFeatures.h"
+#include "cpuHwC1e.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should hardware C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ * @retval       FALSE              HW C1e cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsHwC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  AP_MAILBOXES     ApMailboxes;
+  HW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+  IsEnabled = FALSE;
+  if (PlatformConfig->C1eMode == C1eModeHardware) {
+    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
+    ASSERT (PlatformConfig->C1ePlatformData != 0);
+    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
+      if (GetNumberOfProcessors (StdHeader) == 1) {
+        GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+        if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
+          GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+          if (FamilyServices != NULL) {
+            IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader);
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeHwC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_STATUS CalledStatus;
+  AGESA_STATUS AgesaStatus;
+  HW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  if (IsWarmReset (StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
+    if (CalledStatus > AgesaStatus) {
+      AgesaStatus = CalledStatus;
+    }
+  }
+  return AgesaStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e =
+{
+  HardwareC1e,
+  CPU_FEAT_AFTER_PM_INIT,
+  IsHwC1eFeatureEnabled,
+  InitializeHwC1eFeature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
new file mode 100755
index 0000000000..53226f7ff1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU HW C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_HW_C1E_H_
+#define _CPU_HW_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _HW_C1E_FAMILY_SERVICES HW_C1E_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if hardware C1e is supported.
+ *
+ * @param[in]    HwC1eServices      Hardware C1e services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ * @retval       FALSE              HW C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable hardware C1e.
+ *
+ * @param[in]    HwC1eServices      Hardware C1e services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_HW_C1E_INIT (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HW_C1E_INIT *PF_HW_C1E_INIT;
+
+/**
+ * Provide the interface to the hardware C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _HW_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported;                              ///< Method: Family specific call to check if hardware C1e is supported.
+  PF_HW_C1E_INIT InitializeHwC1e;                                       ///< Method: Family specific call to enable hardware C1e.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_HW_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
new file mode 100755
index 0000000000..1be14e2db8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -0,0 +1,236 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Message-based C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuMsgBasedC1e.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableMsgC1eOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should message-based C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Message-based C1e is supported.
+ * @retval       FALSE              Message-based C1e cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsMsgBasedC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                         Link;
+  UINTN                         LinkCount;
+  UINT32                        Socket;
+  UINT32                        Module;
+  BOOLEAN                       IsEnabled;
+  PCI_ADDR                      PciAddress;
+  AGESA_STATUS                  AgesaStatus;
+  HT_HOST_FEATS                 HtHostFeats;
+  CPU_SPECIFIC_SERVICES         *CpuServices;
+  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->C1eMode == C1eModeMsgBased) {
+    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
+    ASSERT (PlatformConfig->C1ePlatformData != 0);
+    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
+      IsEnabled = TRUE;
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (IsProcessorPresent (Socket, StdHeader)) {
+          GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+          if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {
+            IsEnabled = FALSE;
+            break;
+          } else {
+            // If the CPU revision supports message-based C1e, check whether the feature should
+            // be disabled based on the speed of ncHT links (HT1).
+            GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);
+            for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+              if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+                HtHostFeats.HtHostValue = 0;
+                for (LinkCount = 0; LinkCount < 8; LinkCount++) {
+                  if (FindHtHostCapability (LinkCount, &PciAddress, StdHeader)) {
+                    CpuServices->GetHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader);
+                    if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {
+                      IsEnabled = FALSE;
+                      break;
+                    }
+                  }
+                }
+              }
+              // Exit for (Module = 0; Module < GetPlatformNumberOfModules; Module++)
+              if (!IsEnabled) {
+                break;
+              }
+            }
+          }
+        }
+        // Exit for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++)
+        if (!IsEnabled) {
+          break;
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Message-based C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeMsgBasedC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK      TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) {
+    CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+    TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable message-based C1e on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableMsgC1eOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeMsgBasedC1e (FamilyServices,
+                                         *((UINT64 *) EntryPoint),
+                                         &CpuEarlyParams->PlatformConfig,
+                                         StdHeader);
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e =
+{
+  MsgBasedC1e,
+  (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsMsgBasedC1eFeatureEnabled,
+  InitializeMsgBasedC1eFeature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
new file mode 100755
index 0000000000..4896622986
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -0,0 +1,127 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Message-based C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_MSG_BASED_C1E_H_
+#define _CPU_MSG_BASED_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _MSG_BASED_C1E_FAMILY_SERVICES MSG_BASED_C1E_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if message-based C1e is supported.
+ *
+ * @param[in]    MsgBasedC1eServices Contains the runtime modifiable feature input data.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               Message-based C1e is supported.
+ * @retval       FALSE              Message-based C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable hardware C1e.
+ *
+ * @param[in]    MsgBasedC1eServices Hardware C1e services.
+ * @param[in]    EntryPoint          Timepoint designator.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_MSG_BASED_C1E_INIT (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT;
+
+/**
+ * Provide the interface to the hardware C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _MSG_BASED_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported;                 ///< Method: Family specific call to check if hardware C1e is supported.
+  PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e;                          ///< Method: Family specific call to enable hardware C1e.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_MSG_BASED_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
new file mode 100755
index 0000000000..766a623102
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
@@ -0,0 +1,382 @@
+/**
+ * @file
+ *
+ * AMD CPU Pstate Data Gather Function.
+ *
+ * Contains code to collect all the Pstate related information from MSRs, and PCI registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuPostInit.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_POST_CONFIGURATION    OptionPstatePostConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+PStateGather (
+  IN OUT   VOID *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+AGESA_STATUS
+PStateGatherStub (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+AGESA_STATUS
+PStateGatherMain (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PStateGatherData
+ *
+ *  Description:
+ *    This function will gather PState information from the MSRs and fill up the
+ *    pStateBuf. This buffer will be used by the PState Leveling, and PState Table
+ *    generation code later.
+ *
+ *    Note:  This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval      AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherData (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader);
+  return (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr);
+  // Note: Split config struct into PEI/DXE halves. This one is PEI.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGatherStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherStub (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGatherMain
+ *
+ *  Description:
+ *     This is the common routine for BSP gathering the Pstate data.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherMain (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  PopulatedSockets;
+  UINT32                  NumberOfSockets;
+  UINT32                  Socket;
+  AGESA_STATUS            IgnoredSts;
+  PSTATE_LEVELING         *PStateBufferPtr;
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  UINT32                  MaxState;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+
+  PopulatedSockets = 1;
+  PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);
+
+  PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE);
+
+  MaxState = 0;
+  FamilySpecificServices->GetPstateMaxState (FamilySpecificServices, &MaxState, StdHeader);
+
+  TaskPtr.FuncAddress.PfApTaskI = PStateGather;
+  //
+  // Calculate max buffer size in dwords that need to pass to ap task.
+  //
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES)));
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  //
+  //Get P-States and fill the PStateBufferPtr for BSP
+  //
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+
+  //
+  //Calculate next node buffer address
+  //
+  PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
+  PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
+  PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
+  //
+  //Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
+  //
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        PopulatedSockets++;
+        LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader);
+        TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
+        PStateBufferPtr->SocketNumber = (UINT8) Socket;
+        //
+        //Calculate next node buffer address
+        //
+        PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+        PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
+        PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+      }
+    }
+  }
+  PStateStrucPtr->TotalSocketInSystem = PopulatedSockets;
+
+  return AGESA_SUCCESS;
+}
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGather
+ *
+ *  Description:
+ *     This is the common routine run on each BSC for gathering Pstate data.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateBuffer
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+PStateGather (
+  IN OUT   VOID                *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                 k;
+  UINT32                 IddVal;
+  UINT32                 IddDiv;
+  UINT32                 NodeNum;
+  UINT32                 CoreNum;
+  UINT32                 TempVar_c;
+  UINT32                 TotalEnabledPStates;
+  PCI_ADDR               PciAddress;
+  PSTATE_LEVELING        *PStateBufferPtr;
+  BOOLEAN                PStateEnabled;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  UINT32                 Socket;
+  AGESA_STATUS           IgnoredSts;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+
+  PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
+  TotalEnabledPStates = 0;
+  PStateEnabled = FALSE;
+
+  //
+  /// Sockets number:  code looking at PStateBufferPtr->TotalCoresInNode
+  ///        needs to know it is Processor (or socket) core count and NOT a Node Core count.
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+  PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum;
+
+  //
+  // Assume current CoreNum always zero.(BSC)
+  //
+  GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader);
+
+  PStateBufferPtr->CreateAcpiTables = 1; /// @todo need remove
+
+  //
+  // We need to know the max pstate state in this socket.
+  //
+  FamilySpecificServices->GetPstateMaxState (FamilySpecificServices, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c;
+
+  for (k = 0; k <= TempVar_c; k++) {
+    // Check if PState is enabled
+    FamilySpecificServices->GetPstateRegisterInfo (FamilySpecificServices,
+                                                   k,
+                                                   &PStateEnabled,
+                                                   &IddVal,
+                                                   &IddDiv,
+                                                   StdHeader);
+
+    LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader);
+
+    if (PStateEnabled) {
+
+      FamilySpecificServices->GetPstateFrequency (
+        FamilySpecificServices,
+        (UINT8) k,
+        &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq),
+        StdHeader);
+
+      FamilySpecificServices->GetPstatePower (
+        FamilySpecificServices,
+        (UINT8) k,
+        &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power),
+        StdHeader);
+
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal;
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv;
+
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable  = 1;
+      TotalEnabledPStates++;
+    }
+  } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+  // Don't create ACPI Tables if there is one or less than one PState is enabled
+  if (TotalEnabledPStates <= 1) {
+    PStateBufferPtr[0].CreateAcpiTables = 0;
+  }
+
+  //--------------------Check Again--------------------------------
+
+  IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, NodeNum, &PciAddress, &IgnoredSts);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+  TempVar_c = 0;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].HtcCapable =
+    (UINT8) ((TempVar_c & 0x00000400) >> 10);    // Bit  10
+
+  TempVar_c = 0;
+  PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit =
+    (UINT8) ((TempVar_c & 0x70000000) >> 28);   // Bits 30:28
+
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
new file mode 100755
index 0000000000..169a94f170
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -0,0 +1,1088 @@
+/**
+ * @file
+ *
+ * AMD CPU Pstate Leveling Function.
+ *
+ * Contains code to level the Pstates in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuPostInit.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_POST_CONFIGURATION    OptionPstatePostConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PStateLevelingStub (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+VOID
+CorePstateRegModify (
+  IN       VOID               *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PutAllCoreInPState0 (
+  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+StartPstateMsrModify (
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+STATIC
+PutCoreInPState0 (
+  IN       VOID   *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PStateLeveling
+ *
+ *  Description:
+ *    This function will populate the PStateBuffer, after doing the PState Leveling
+ *    Note: This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLeveling (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader);
+  return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader));
+  // Note: Split config struct into PEI/DXE halves. This one is PEI.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateLevelingStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLevelingStub (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateLevelingMain
+ *
+ *  Description:
+ *     This is the common routine for creating the ACPI information tables.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32                   i;
+  UINT32                   k;
+  UINT32                   m;
+  UINT32                   TotalIterations;
+  UINT32                   LogicalSocketCount;
+  UINT32                   TempVar_a;
+  UINT32                   TempVar_b;
+  UINT32                   TempVar_c;
+  UINT32                   TempVar_d;
+  UINT32                   TempVar_e;
+  UINT32                   TempVar_f;
+  PCI_ADDR                 PciAddress;
+
+  UINT32                   TempFreqArray[20];
+  UINT32                   TempPowerArray[20];
+  UINT32                   TempIddValueArray[20];
+  UINT32                   TempIddDivArray[20];
+  UINT32                   TempSocketPiArray[20];
+
+  BOOLEAN                  TempFlag1;
+  BOOLEAN                  TempFlag2;
+  BOOLEAN                  TempFlag3;
+  BOOLEAN                  TempFlag4;
+  BOOLEAN                  AllCoresHaveHtcCapEquToZeroFlag;
+  BOOLEAN                  AllCoreHaveMaxOnePStateFlag;
+  BOOLEAN                  PstateMaxValEquToPstateHtcLimitFlag;
+  BOOLEAN                  AtLeastOneCoreHasPstateHtcLimitEquToOneFlag;
+  BOOLEAN                  PstateMaxValMinusHtcPstateLimitLessThan2Flag;
+  PSTATE_LEVELING          *PStateBufferPtr;
+  PSTATE_LEVELING          *PStateBufferPtrTmp = NULL;
+  UINT32                   MaxPstateInNode;
+  AGESA_STATUS             Status;
+
+  TempFlag1 = FALSE;
+  TempFlag2 = FALSE;
+  TempFlag3 = FALSE;
+  TempFlag4 = FALSE;
+  AllCoresHaveHtcCapEquToZeroFlag = FALSE;
+  AllCoreHaveMaxOnePStateFlag = FALSE;
+  PstateMaxValEquToPstateHtcLimitFlag = FALSE;
+  AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE;
+  PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE;
+  PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
+  Status = AGESA_SUCCESS;
+
+  if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) {
+    PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
+    PStateBufferPtr[0].InitStruct = 1;
+    return AGESA_UNSUPPORTED;
+  }
+
+  LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem;
+
+  // This section of code will execute only for "core 0" i.e. BSP
+  // Read P-States of all the cores.
+  if (PStateBufferPtr[0].InitStruct == 0) {
+    // Check if core frequency and power are same across all sockets.
+    TempFlag1 = FALSE;
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) {
+        TempFlag1 = TRUE;
+        break;
+      }
+      MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+      for (k = 0; k <= MaxPstateInNode; k++) {
+        if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq !=
+             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) ||
+            (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power !=
+             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) {
+          TempFlag1 = TRUE;
+          break; // Come out of the inner FOR loop
+        }
+      }
+      if (TempFlag1) {
+        break; // Come out of the outer FOR loop
+      }
+    }
+
+    if (!TempFlag1) {
+      // No need to do pStateLeveling, or writing to pState MSR registers
+      // if all CPUs have Identical PStates
+      PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
+      PStateBufferPtr[0].InitStruct = 1;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    } else {
+      PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE;
+    }
+
+    // 1_b) & 1_c)
+    TempFlag1 = FALSE;
+    TempFlag2 = FALSE;
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 0) {
+        TempFlag1 = TRUE;
+      } else {
+        TempFlag2 = TRUE;
+      }
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) {
+        TempFlag3 = TRUE;
+      } else {
+        TempFlag4 = TRUE;
+      }
+
+      if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
+           PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) {
+        PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
+      }
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue ==
+          PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+        PstateMaxValEquToPstateHtcLimitFlag = TRUE;
+      }
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
+        AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
+      }
+    }
+
+    // Do general setup of flags, that we may use later
+    // Implementation of (1_b)
+    if (TempFlag1 && TempFlag2) {
+      //
+      //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with
+      //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b).
+      //
+      PStateBufferPtr[0].InitStruct = 1;
+      PStateBufferPtr[0].CreateAcpiTables = 0;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    } else if (TempFlag1 && !TempFlag2) {
+      //
+      //all processors have only 1 enabled P-state
+      //
+      AllCoreHaveMaxOnePStateFlag = TRUE;
+      PStateBufferPtr[0].OnlyOneEnabledPState = TRUE;
+    }
+
+    // Processors with F3xE8[HTC_CAPABLE] = 1 can not be
+    // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0.
+    if (TempFlag3 && TempFlag4) {
+      PStateBufferPtr[0].InitStruct = 1;
+      PStateBufferPtr[0].CreateAcpiTables = 0;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    }
+
+    if (TempFlag3) {
+      //
+      //If code run to here means that all processors do not have HTC_CAPABLE.
+      //
+      AllCoresHaveHtcCapEquToZeroFlag = TRUE;
+    }
+
+    //--------------------------------------------------------------------------------
+    // S T E P - 2
+    //--------------------------------------------------------------------------------
+    // Now run the PState Leveling Algorithm which will create mixed CPU P-State
+    // Tables.
+    // Follow the algorithm in the latest BKDG
+    // -------------------------------------------------------------------------------
+    // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the
+    // coherent fabric, and match P0 power for all CPU cores to the highest P0 power
+    // value in the coherent fabric.
+    // 2_a) If all processors have only 1 enabled P-State BIOS must write the
+    //      appropriate CpuFid value resulting from the matched CPU COF to all
+    //      copies of MSRC001_0070[CpuFid], and exit the sequence (No further
+    //      steps are executed)
+    //--------------------------------------------------------------------------------
+    // Identify the lowest P0 Frequency and maximum P0 Power
+    TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].CoreFreq;
+    TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].Power;
+    TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].IddValue;
+    TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].IddDiv;
+
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq) {
+        TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq;
+      }
+
+      if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power) {
+        TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power;
+        TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue;
+        TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv;
+      }
+    }
+
+    // Set P0 Frequency and Power for all CPUs
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq = TempVar_d;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power = TempVar_e;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue = TempVar_a;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv = TempVar_b;
+    }
+
+    // 2_a)
+    if (!AllCoreHaveMaxOnePStateFlag) {
+      //--------------------------------------------------------------------------
+      // STEP - 3
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for P-states used by HTC. Skip to step 4
+      // is any processor reports F3xE8[HTC_Capable] = 0;
+      // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for
+      //      processors with F3x64[HtcPstateLimit] = 000b.
+      // 3_b) Identify the lowest CPU COF for all processors in the P-state
+      //      pointed to by [The Hardware Thermal Control (HTC) Register]
+      //      F3x64[HtcPstateLimit]
+      // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control
+      //      (HTC) Register] F3x64[HtcPstateLimit] for all processors to the
+      //      previously identified lowest CPU COF value.
+      // 3_d) Identify the highest power for all processors in the P-state
+      //      pointed to by [The Hardware Thermal Control (HTC) Register]
+      //      F3x64[HtcPstateLimit].
+      // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC)
+      //      Register] F3x64[HtcPstateLimit] to the previously identified
+      //      highest power value.
+      if (!AllCoresHaveHtcCapEquToZeroFlag) {
+        // 3_a)
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) {
+            // To Be Done (Set Htc and Stc PstateLimit values)
+            // for this CPU (using PCI address space)
+            for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) {
+              if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) {
+                // Set F3x64[HtcPstateLimit] = 001b
+                PciAddress.Address.Function = FUNC_3;
+                PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+                // Bits 30:28
+                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
+                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+
+                // Set F3x68[StcPstateLimit] = 001b
+                PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG;
+                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+                // Bits 28:30
+                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
+                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+              }
+            }
+            // Set LocalBuffer
+            PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1;
+            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) {
+              PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
+            }
+
+            if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) {
+              PstateMaxValEquToPstateHtcLimitFlag = TRUE;
+            }
+          }
+
+          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
+            AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
+          }
+        }
+
+        // 3_b) and 3_d)
+        TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit;
+        TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
+        TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
+        TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
+        TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          for (k = 0; k < 1; k++) {
+            TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+            if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
+              TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
+            }
+
+            if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
+              TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
+              TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
+              TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
+            }
+          }
+        }
+
+        // 3_c) and 3_e)
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
+        }
+      } // if(AllCoresHaveHtcCapEquToZeroFlag)
+
+
+      //--------------------------------------------------------------------------
+      // STEP - 4
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for the lowest performance P-state:
+      // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor,
+      //      set PstateEn = 0 for all the P-states greater than
+      //      F3x64[HtcPstateLimit] for all processors.
+      // 4_b) Identify the lowest CPU COF for all processors in the P-state
+      //      pointed to by F3xDC[PstateMaxVal].
+      // 4_c) Modify the CPU COF for all processors in the P-state pointed to by
+      //      F3xDC[PstateMaxVal] to the previously identified lowest CPU COF
+      //      value.
+      // 4_d) Identify the highest power for all processors in the P-state
+      //      pointed to by F3xDC[PstateMaxVal].
+      // 4_e) Modify the power for all processors in the P-state pointed to by
+      //      F3xDC[PstateMaxVal] to the previously identified highest power
+      //      value.
+
+      // 4_a)
+      if (PstateMaxValEquToPstateHtcLimitFlag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1;
+          for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) {
+            PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+          }
+          //--------------------------------------------------------------------------
+          // STEP - 5
+          //--------------------------------------------------------------------------
+          // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance
+          //      P-state with PstateEn set for each processor (Step 4 can disable
+          //      P-states pointed to by F3xDC[PstateMaxVal])
+
+          // Use this value of HtcPstateLimit to program the
+          // F3xDC[pStateMaxValue]
+          TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+          TempVar_e <<= 8;
+          // Bits 10:8
+
+          for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) {
+            if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) {
+              PciAddress.Address.Function = FUNC_3;
+              PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+              LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+              TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e;
+              LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+            }
+          }//End of step 5
+        }
+      }// End of 4_a)
+
+      // 4_b) and 4_d)
+      TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue;
+      TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
+      TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
+      TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
+      TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
+
+      for (i = 0; i < LogicalSocketCount; i++) {
+        CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+        TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+        if (TempVar_d >
+            PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
+          TempVar_d =
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
+        }
+
+        if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
+          TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
+          TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
+          TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
+        }
+      }
+
+      // 4_c) and 4_e)
+      for (i = 0; i < LogicalSocketCount; i++) {
+        CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+        TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
+      }
+
+
+      //--------------------------------------------------------------------------
+      // STEP - 6
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for upper intermediate performance
+      // P-state(s):
+      // Upper intermediate PStates = PStates between (Not including) P0 and
+      // F3x64[HtcPstateLimit]
+      // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0
+      //      for enabled upper intermediate P-states for all processors with
+      //      F3x64[HtcPstateLimit] > 001b and skip the remaining actions for
+      //      this numbered step.
+      // 6_b) Define each of the available upper intermediate P-states; for each
+      //      processor concurrently evaluate the following loop; when any
+      //      processor falls out of the loop (runs out of available upper
+      //      intermediate Pstates) all other processors have their remaining
+      //      upper intermediate P-states invalidated (PstateEn = 0);
+      //      for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--)
+      //         - Identify the lowest CPU COF for P(i).
+      //         - Identify the highest power for P(i).
+      //         - Modify P(i) CPU COF for all processors to the previously
+      //           identified lowest CPU COF value.
+      //         - Modify P(i) power for all processors to the previously
+      //           identified highest power value.
+
+      // 6_a)
+      if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          for (k = 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) {
+            if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) {
+              // Make a function call to clear the
+              // structure values
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+            }
+          }
+        }
+      }
+      // 6_b)
+      else {
+        // Identify Lowest Frequency and Highest Power
+        TotalIterations = 0;
+        TempFlag1 = TRUE;
+
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1;
+        }
+
+        do {
+          //For first socket, try to find a candidate
+          if (TempSocketPiArray[0] != 0) {
+            while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
+              TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
+              if (TempSocketPiArray[0] == 0) {
+                TempFlag1 = FALSE;
+                break;
+              }
+            }
+          } else {
+            TempFlag1 = FALSE;
+          }
+          if (TempFlag1) {
+            TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
+            TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
+            TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
+            TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
+
+            //Try to find next candidate
+            for (i = 1; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempSocketPiArray[i] != 0) {
+                while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
+                  TempSocketPiArray[i]--;
+                  if (TempSocketPiArray[i] == 0) {
+                    TempFlag1 = FALSE;
+                    break;
+                  }
+                }//end while
+              } else {
+                TempFlag1 = FALSE;
+              }
+
+            } //end for LogicalSocketCount
+          }
+
+          if (TempFlag1) {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              //
+              //Compare
+              //
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
+                TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
+              }
+
+              if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
+                TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
+                TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
+                TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
+              }
+            }
+            // Modify (Pi) CPU COF and Power for all the CPUs
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power    = TempPowerArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv   = TempIddDivArray[TotalIterations];
+              TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
+            }
+          } else {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              for (m = TempSocketPiArray[i]; m > 0; m--) {
+                PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
+              }
+            }
+          }
+
+          TotalIterations++;
+        } while (TempFlag1);
+
+      } // else
+
+      //--------------------------------------------------------------------------
+      // STEP - 7
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for lower intermediate performance P - state(s)
+      // Lower Intermediate Pstates = Pstates between (not including)
+      // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal]
+      // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any
+      //      processor, set PstateEn = 0 for enabled lower intermediate P - states
+      //      for all processors with (F3xDC[PstateMaxVal] -
+      //      F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this
+      //      numbered step.
+      // 7_b) Define each of the available lower intermediate P-states; for each
+      //      processor concurrently evaluate the following loop; when any
+      //      processor falls out of the loop (runs out of available lower
+      //      intermediate Pstates) all other processors have their remaining
+      //      lower intermediate P-states invalidated (PstateEn = 0);
+      //      for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--)
+      //         - Identify the lowest CPU COF for P-states between
+      //           (not including) F3x64[HtcPstateLimit] and P(i).
+      //         - Identify the highest power for P-states between
+      //           (not including) F3x64[HtcPstateLimit] and P(i).
+      //         - Modify P(i) CPU COF for all processors to the previously
+      //           identified lowest CPU COF value.
+      //         - Modify P(i) power for all processors to the previously
+      //           identified highest power value.
+
+
+      // 7_a)
+      if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+
+          for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
+              k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+              k--) {
+            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
+                 PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) {
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+            }
+          }
+        }
+      }
+
+      // 7_b)
+      else {
+        // Identify Lowest Frequency and Highest Power
+
+        TotalIterations = 0;
+        TempFlag1 = TRUE;
+
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
+        }
+
+        do {
+          //For first socket, try to find a candidate
+          if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
+            while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
+              TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
+              if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
+                TempFlag1 = FALSE;
+                break;
+              }
+            }
+          } else {
+            TempFlag1 = FALSE;
+          }
+          if (TempFlag1) {
+            TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
+            TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
+            TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
+            TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
+
+            //Try to find next candidate
+            for (i = 1; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+                while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
+                  TempSocketPiArray[i]--;
+                  if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+                    TempFlag1 = FALSE;
+                    break;
+                  }
+                }//end while
+              } else {
+                TempFlag1 = FALSE;
+              }
+            } //end for LogicalSocketCount
+          }
+
+          if (TempFlag1) {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              //
+              //Compare
+              //
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
+                TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
+              }
+              if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
+                TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
+                TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
+                TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
+              }
+            }
+            // Modify (Pi) CPU COF and Power for all the CPUs
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power    = TempPowerArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv   = TempIddDivArray[TotalIterations];
+              TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
+            }
+          } else {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) {
+                PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
+              }
+            }
+          }
+          TotalIterations++;
+        } while (TempFlag1);
+      } // else
+    } // if(!AllCoreHaveMaxOnePStateFlag)
+
+    PStateBufferPtr[0].InitStruct = 1;
+  } // CurrentCore
+
+
+  // Update the pState MSRs
+  // This can be done only by individual core
+  StartPstateMsrModify (PStateStrucPtr, StdHeader);
+
+  //----------------------------------------------------------------------------------
+  // STEP - 8
+  //----------------------------------------------------------------------------------
+  // Place all cores into a valid COF and VID configuration corresponding to an
+  // enabled P-state:
+  // 8_a) Select an enabled P-state != to the P-state pointed to by
+  //      MSRC001_0063[CurPstate] for each core.
+  // 8_b) Transition all cores to the selected P-states by writing the Control value
+  //      from the_PSS object corresponding to the selected P-state to
+  //      MSRC001_0062[PstateCmd].
+  // 8_c) Wait for all cores to report the Status value from the _PSS object
+  //      corresponding to the selected P-state in MSRC001_0063[CurPstate].
+  //
+  PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PutAllCoreInPState0
+ *
+ *  Description:
+ *    This function will put core pstate to p0.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateBufferPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PutAllCoreInPState0 (
+  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  PutCoreInPState0 (PStateBufferPtr, StdHeader);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CorePstateRegModify
+ *
+ *  Description:
+ *    This function will setting the Pstate MSR to each APs base on Pstate Buffer.
+ *    Note: This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in,out]    *CpuAmdPState
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+CorePstateRegModify (
+  IN       VOID               *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->SetPStateLevelReg  (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader);
+
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will set msr on all cores of all nodes.
+ *
+ * @param[in]     CpuAmdPState  @todo describe
+ * @param[in]     StdHeader     Header for library and services.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds
+ *
+ */
+AGESA_STATUS
+StartPstateMsrModify (
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify;
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  CorePstateRegModify (CpuAmdPState, StdHeader);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CpuGetPStateLevelStructure
+ *
+ *  Description:
+ *    Based on the LogicalSocketNumber, this function will return a pointer
+ *      point to the accurate offset of the PSTATE_LEVELING structure.
+ *
+ *  Parameters:
+ *    @param[in,out]          *PStateBufferPtr
+ *    @param[in]              *CpuAmdPState
+ *    @param[in]              LogicalSocketNumber
+ *    @param[in]              *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CpuGetPStateLevelStructure (
+     OUT   PSTATE_LEVELING     **PStateBufferPtr,
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       UINT32              LogicalSocketNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PSTATE_LEVELING         *PStateBufferPtrTmp;
+  UINT32                  i;
+
+  if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc;
+
+  for (i = 1; i <= LogicalSocketNumber; i++) {
+    PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes));
+  }
+
+  *PStateBufferPtr = PStateBufferPtrTmp;
+
+  return AGESA_SUCCESS;
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PutCoreInPState0
+ *
+ *  Description:
+ *    This function will take the CPU core into P0
+ *
+ *  Parameters:
+ *    @param[in]         *PStateBuffer
+ *    @param[in]         *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+PutCoreInPState0 (
+  IN       VOID   *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  PSTATE_LEVELING         *PStateBufferPtr;
+
+  PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
+
+  if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) ||
+     (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) {
+    return;
+  }
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->TransitionPstate  (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
new file mode 100755
index 0000000000..ed4eb02144
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
@@ -0,0 +1,821 @@
+/**
+ * @file
+ *
+ * AMD PSTATE, ACPI table related API functions.
+ *
+ * Contains code that generates the _PSS, _PCT, and other ACPI tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#include "cpuPstateTables.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_LATE_CONFIGURATION    OptionPstateLateConfiguration;  // global user config record
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+extern CPU_FAMILY_SUPPORT_TABLE            C6FamilyServiceTable;
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuSsdtHdrStruct =
+{
+  {'S','S','D','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'P','O','W','E','R','N','O','W'},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+AGESA_STATUS
+CreateAcpiTablesMain (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+AGESA_STATUS
+CreateAcpiTablesStub (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CalAcpiTablesSize
+ *
+ *  Description:
+ *    This function will calculate the size of ACPI PState tables
+ *
+ *  Parameters:
+ *    @param[in]     *AmdPstatePtr
+ *    @param[in]     *PlatformConfig
+ *    @param[in]     *StdHeader
+ *
+ *    @retval      UINT32
+ *
+ *---------------------------------------------------------------------------------------
+ */
+STATIC UINT32
+CalAcpiTablesSize (
+  IN       S_CPU_AMD_PSTATE       *AmdPstatePtr,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32               ScopeSize;
+  UINT32               CoreCount;
+  UINT32               SocketCount;
+  UINT32               MaxCoreNumberInCurrentSocket;
+  UINT32               MaxSocketNumberInSystem;
+  UINT32               MaxPstateNumberInCurrentCore;
+  UINT32               CstObjSize;
+  PSTATE_LEVELING      *PStateLevelingBufferStructPtr;
+  C6_FAMILY_SERVICES   *C6FamilyServices;
+
+  ScopeSize = sizeof (ACPI_TABLE_HEADER);
+  CstObjSize = 0;
+  C6FamilyServices = NULL;
+
+  PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
+  MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem;
+
+  if (IsFeatureEnabled (C6Cstate, PlatformConfig, StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&C6FamilyServices, StdHeader);
+    CstObjSize = C6FamilyServices->GetAcpiCstObj ();
+  }
+
+  for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) {
+    MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode;
+    for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) {
+      MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1;
+      ScopeSize += (PCT_STRUCT_SIZE +
+                    PSS_HEADER_STRUCT_SIZE +
+                    (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) +
+                    XPSS_HEADER_STRUCT_SIZE +
+                    (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) +
+                    PSD_HEADER_STRUCT_SIZE +
+                    PSD_BODY_STRUCT_SIZE +
+                    PPC_HEADER_BODY_STRUCT_SIZE) + (SCOPE_STRUCT_SIZE - 1) +
+                    CstObjSize;
+
+    }
+    ScopeSize += MaxCoreNumberInCurrentSocket;
+    PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  }
+
+  AmdPstatePtr->SizeOfBytes = ScopeSize;
+
+  return ScopeSize;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTables
+ *
+ *  Description:
+ *    This function will populate the ACPI PState tables
+ *    This function should be called only from BSP
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval      AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+CreateAcpiTables (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader);
+  return ((*(OptionPstateLateConfiguration.PstateFeature)) (StdHeader, PlatformConfig, SsdtPtr));
+  // Note: Split config struct into PEI/DXE halves. This one is DXE.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTablesStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CreateAcpiTablesStub (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTablesMain
+ *
+ *  Description:
+ *     This is the common routine for creating the ACPI information tables.
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CreateAcpiTablesMain (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  UINT32                 i;
+  UINT32                 j;
+  UINT32                 k;
+  UINT32                 TempVar8_a;
+  UINT32                 PStateCount;
+  UINT32                 CoreCount;
+  UINT32                 CoreCount1;
+  UINT32                 SocketCount;
+  UINT32                 ScopeSize;
+  UINT32                 TempVar_a;
+  UINT32                 TempVar_b;
+  UINT32                 TempVar_c;
+  UINT32                 TempVar_d;
+  PCI_ADDR               PciAddress;
+  UINT32                 TransAndBusMastLatency;
+  UINT32                 MaxCorePerNode;
+  UINT8                  PStateMaxValueOnCurrentCore;
+  UINT8                  *IntermediatePtr;
+  PSTATE_LEVELING        *PStateLevelingBufferStructPtr;
+  AMD_CONFIG_PARAMS      *AmdConfigParamsStructPtr;
+  SCOPE                  *ScopeAcpiTablesStructPtr;
+  SCOPE                  *ScopeAcpiTablesStructPtrTemp;
+  PCT_HEADER_BODY        *pPctAcpiTables;
+  PSS_HEADER             *pPssHeaderAcpiTables;
+  PSS_BODY               *pPssBodyAcpiTables;
+  XPSS_HEADER            *pXpssHeaderAcpiTables;
+  XPSS_BODY              *pXpssBodyAcpiTables;
+  PSD_HEADER             *pPsdHeaderAcpiTables;
+  PSD_BODY               *pPsdBodyAcpiTables;
+  PPC_HEADER_BODY        *pPpcHeaderBodyAcpiTables;
+  AGESA_BUFFER_PARAMS    AgesaBuffer;
+  LOCATE_HEAP_PTR        LocateHeapParams;
+  S_CPU_AMD_PSTATE       *AmdPstatePtr;
+  BOOLEAN                PstateCapEnable;
+  UINT32                 PstateCapInputMilliWatts;
+  UINT8                  PstateCapLevelSupport;
+  BOOLEAN                PstateCapLevelSupportDetermined;
+  UINT8                  LocalApicId;
+  AGESA_STATUS           AgesaStatus;
+  AGESA_STATUS           IgnoredStatus;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
+  BOOLEAN                IsPsdDependent;
+  C6_FAMILY_SERVICES     *C6FamilyServices;
+  //
+  //Initialize local variables
+  //
+  AmdConfigParamsStructPtr = StdHeader;
+  PstateCapEnable = FALSE;
+  PstateCapInputMilliWatts = PlatformConfig->PowerCeiling;
+  PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP;
+  PstateCapLevelSupportDetermined = TRUE;
+  LocalApicId = 0;
+  AgesaStatus = AGESA_SUCCESS;
+  TempVar_c = 0;
+  ScopeAcpiTablesStructPtrTemp = NULL;
+  TransAndBusMastLatency = 0;
+  PStateCount = 0;
+  IsPsdDependent = !(PlatformConfig->ForcePstateIndependent);
+  FamilyServices = NULL;
+  C6FamilyServices = NULL;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredStatus));
+
+  //
+  //Locate P-state gathered data heap.
+  //
+  LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
+
+  AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    return AGESA_ERROR;
+  }
+  AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader);
+
+  AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr;
+  PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
+
+  //
+  // Check if we need to create ACPI tables
+  //
+  if (PStateLevelingBufferStructPtr[0].CreateAcpiTables == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  //
+  //Allocate rough buffer for AcpiTable, if AcpiPstateBufferPtr is NULL
+  //
+  if (*SsdtPtr == NULL) {
+    AgesaBuffer.StdHeader = *StdHeader;
+    //
+    //Do not know the actual size.. pre-calculate it.
+    //
+    AgesaBuffer.BufferLength = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader);
+    AgesaBuffer.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader);
+    *SsdtPtr = AgesaBuffer.BufferPointer;
+  }
+
+  //SSDT header
+  LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+
+  IntermediatePtr = (UINT8 *) *SsdtPtr;
+  ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)];
+
+  SocketCount = AmdPstatePtr->TotalSocketInSystem;
+
+  // Initialize data variables
+  ScopeSize = 0;
+  CoreCount = 0;
+  for (i = 0; i < SocketCount; i++) {
+
+    MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode;
+
+    for (j = 0; j < MaxCorePerNode; j++) {
+
+      //
+      //Check Pstate Capability enable
+      //
+      if (PstateCapInputMilliWatts != 0) {
+        PstateCapEnable = TRUE;
+        PstateCapLevelSupportDetermined = FALSE;
+      }
+
+      PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue;
+
+      CoreCount++;
+      // Set Name Scope for CPU0, 1, 2, ..... n
+      // CPU0 to CPUn will name  as  C000 to Cnnn
+      // -----------------------------------------
+      ScopeAcpiTablesStructPtr->ScopeOpcode      = SCOPE_OPCODE;
+      // This value will be filled at the end of this function
+      // Since at this time, we don't know how many  Pstates we
+      // would have
+      ScopeAcpiTablesStructPtr->ScopeLength      = 0;
+      ScopeAcpiTablesStructPtr->ScopeValue1      = SCOPE_VALUE1;
+      ScopeAcpiTablesStructPtr->ScopeValue2      = SCOPE_VALUE2;
+      ScopeAcpiTablesStructPtr->ScopeNamePt1a__  = SCOPE_NAME__;
+      if (PlatformConfig->ProcessorScopeInSb) {
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_P  = SCOPE_NAME_S;
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_R  = SCOPE_NAME_B;
+      } else {
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_P  = SCOPE_NAME_P;
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_R  = SCOPE_NAME_R;
+      }
+      ScopeAcpiTablesStructPtr->ScopeNamePt1b__  = SCOPE_NAME__;
+
+      ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z'))
+      ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \
+              ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \
+              (PlatformConfig->ProcessorScopeName1 == '_'))
+
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_C  = PlatformConfig->ProcessorScopeName0;
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_P  = PlatformConfig->ProcessorScopeName1;
+
+      TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F;
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_U  = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
+
+      TempVar8_a = (CoreCount - 1) & 0x0F;
+      if (TempVar8_a < 0xA) {
+        ScopeAcpiTablesStructPtr->ScopeNamePt2a_0  = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
+      } else {
+        ScopeAcpiTablesStructPtr->ScopeNamePt2a_0  = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA);
+      }
+
+      //
+      // Increment and typecast the pointer
+      //
+      ScopeAcpiTablesStructPtr++;
+      pPctAcpiTables = (PCT_HEADER_BODY *) ScopeAcpiTablesStructPtr;
+      ScopeAcpiTablesStructPtr--;
+      ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr;
+      ScopeAcpiTablesStructPtrTemp++;
+
+      if (OptionPstateLateConfiguration.CfgPstatePct) {
+        //
+        // Set _PCT Table
+        // --------------
+        pPctAcpiTables->NameOpcode              = NAME_OPCODE;
+        pPctAcpiTables->PctName_a__             = PCT_NAME__;
+        pPctAcpiTables->PctName_a_P             = PCT_NAME_P;
+        pPctAcpiTables->PctName_a_C             = PCT_NAME_C;
+        pPctAcpiTables->PctName_a_T             = PCT_NAME_T;
+        pPctAcpiTables->Value1                  = PCT_VALUE1;
+        pPctAcpiTables->Value2                  = PCT_VALUE2;
+        pPctAcpiTables->Value3                  = PCT_VALUE3;
+        pPctAcpiTables->GenericRegDescription1  = GENERIC_REG_DESCRIPTION;
+        pPctAcpiTables->Length1                 = PCT_LENGTH;
+        pPctAcpiTables->AddressSpaceId1         = PCT_ADDRESS_SPACE_ID;
+        pPctAcpiTables->RegisterBitWidth1       = PCT_REGISTER_BIT_WIDTH;
+        pPctAcpiTables->RegisterBitOffset1      = PCT_REGISTER_BIT_OFFSET;
+        pPctAcpiTables->Reserved1               = PCT_RESERVED;
+        pPctAcpiTables->ControlRegAddressLo     = PCT_CONTROL_REG_LO;
+        pPctAcpiTables->ControlRegAddressHi     = PCT_CONTROL_REG_HI;
+        pPctAcpiTables->Value4                  = PCT_VALUE4;
+        pPctAcpiTables->Value5                  = PCT_VALUE5;
+        pPctAcpiTables->GenericRegDescription2  = GENERIC_REG_DESCRIPTION;
+        pPctAcpiTables->Length2                 = PCT_LENGTH;
+        pPctAcpiTables->AddressSpaceId2         = PCT_ADDRESS_SPACE_ID;
+        pPctAcpiTables->RegisterBitWidth2       = PCT_REGISTER_BIT_WIDTH;
+        pPctAcpiTables->RegisterBitOffset2      = PCT_REGISTER_BIT_OFFSET;
+        pPctAcpiTables->Reserved2               = PCT_RESERVED;
+        pPctAcpiTables->StatusRegAddressLo      = PCT_STATUS_REG_LO;
+        pPctAcpiTables->StatusRegAddressHi      = PCT_STATUS_REG_HI;
+        pPctAcpiTables->Value6                  = PCT_VALUE6;
+
+        // Set _PSS Table - START
+        //------------------------
+
+        // Increment and then typecast the pointer
+        pPctAcpiTables++;
+        TempVar_c += PCT_STRUCT_SIZE;
+
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPctAcpiTables;
+      } // end of OptionPstateLateConfiguration.CfgPstatePct
+
+      pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstatePss) {
+        //
+        // Set _PSS Header
+        // Note: Set the pssLength and numOfItemsInPss later
+        //---------------------------------------------------
+        pPssHeaderAcpiTables->NameOpcode      = NAME_OPCODE;
+        pPssHeaderAcpiTables->PssName_a__     = PSS_NAME__;
+        pPssHeaderAcpiTables->PssName_a_P     = PSS_NAME_P;
+        pPssHeaderAcpiTables->PssName_a_S     = PSS_NAME_S;
+        pPssHeaderAcpiTables->PssName_b_S     = PSS_NAME_S;
+        pPssHeaderAcpiTables->PkgOpcode       = PACKAGE_OPCODE;
+
+        pPssHeaderAcpiTables++;
+      }// end of PSS Header if OptionPstateLateConfiguration.CfgPstatePss
+
+      pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstatePss) {
+        // Restore the pPssHeaderAcpiTables
+        pPssHeaderAcpiTables--;
+
+        // Set _PSS Body
+        //---------------
+        PStateCount = 0;
+
+        //
+        //Calculate pci address for socket only
+        //
+        GetPciAddress (StdHeader, (UINT32) PStateLevelingBufferStructPtr->SocketNumber, 0, &PciAddress, &IgnoredStatus);
+        TransAndBusMastLatency = 0;
+        GetCpuServicesOfSocket ((UINT32) PStateLevelingBufferStructPtr->SocketNumber, &FamilySpecificServices, StdHeader);
+        ASSERT (FamilySpecificServices != NULL);
+        FamilySpecificServices->GetPstateLatency (FamilySpecificServices,
+                                                  PStateLevelingBufferStructPtr,
+                                                  &PciAddress,
+                                                  &TransAndBusMastLatency,
+                                                  StdHeader);
+
+        for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+          if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+            pPssBodyAcpiTables->PkgOpcode           = PACKAGE_OPCODE;
+            pPssBodyAcpiTables->PkgLength           = PSS_PKG_LENGTH;
+            pPssBodyAcpiTables->NumOfElements       = PSS_NUM_OF_ELEMENTS;
+            pPssBodyAcpiTables->DwordPrefixOpcode1  = DWORD_PREFIX_OPCODE;
+
+            pPssBodyAcpiTables->Frequency           =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
+
+            pPssBodyAcpiTables->DwordPrefixOpcode2  = DWORD_PREFIX_OPCODE;
+
+            pPssBodyAcpiTables->Power               =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].Power;
+
+            if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) {
+              PstateCapLevelSupport = (UINT8) k;
+              PstateCapLevelSupportDetermined = TRUE;
+            }
+
+            pPssBodyAcpiTables->DwordPrefixOpcode3  = DWORD_PREFIX_OPCODE;
+
+            pPssBodyAcpiTables->TransitionLatency   = TransAndBusMastLatency;
+            pPssBodyAcpiTables->DwordPrefixOpcode4  = DWORD_PREFIX_OPCODE;
+            pPssBodyAcpiTables->BusMasterLatency    = TransAndBusMastLatency;
+            pPssBodyAcpiTables->DwordPrefixOpcode5  = DWORD_PREFIX_OPCODE;
+            pPssBodyAcpiTables->Control             = k;
+            pPssBodyAcpiTables->DwordPrefixOpcode6  = DWORD_PREFIX_OPCODE;
+            pPssBodyAcpiTables->Status              = k;
+
+            pPssBodyAcpiTables++;
+            PStateCount++;
+          }
+
+        } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+        if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) {
+          PstateCapLevelSupport = PStateMaxValueOnCurrentCore;
+        }
+
+        // Set _PSS Header again
+        // Now Set pssLength and numOfItemsInPss
+        //---------------------------------------
+        TempVar_a = (PStateCount * PSS_BODY_STRUCT_SIZE) + 3;
+        if (TempVar_a > 63) {
+          TempVar_b = TempVar_a;
+          TempVar_d = ((TempVar_b << 4) & 0x0000FF00);
+          TempVar_d = TempVar_d | ((TempVar_b & 0x0000000F) | 0x00000040);
+          TempVar_a = (UINT16) TempVar_d;
+        }
+
+        pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a;
+        pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PStateCount;
+        TempVar_c += (PSS_HEADER_STRUCT_SIZE + (PStateCount * PSS_BODY_STRUCT_SIZE));
+
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPssBodyAcpiTables;
+      } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss
+
+      //
+      // Set XPSS Table - START
+      //------------------------
+      // Typecast the pointer
+      pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstateXpss) {
+        // Set XPSS Header
+        // Note: Set the pssLength and numOfItemsInPss later
+        //---------------------------------------------------
+        pXpssHeaderAcpiTables->NameOpcode       = NAME_OPCODE;
+        pXpssHeaderAcpiTables->XpssName_a_X     = PSS_NAME_X;
+        pXpssHeaderAcpiTables->XpssName_a_P     = PSS_NAME_P;
+        pXpssHeaderAcpiTables->XpssName_a_S     = PSS_NAME_S;
+        pXpssHeaderAcpiTables->XpssName_b_S     = PSS_NAME_S;
+        pXpssHeaderAcpiTables->PkgOpcode        = PACKAGE_OPCODE;
+
+        // Increment and then typecast the pointer
+        pXpssHeaderAcpiTables++;
+      }//end of XPSS header if OptionPstateLateConfiguration.CfgPstateXpss
+
+      pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstateXpss) {
+        // Restore the pXpssHeaderAcpiTables
+        pXpssHeaderAcpiTables--;
+
+        // Set XPSS Body
+        //---------------
+        for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+          if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+            pXpssBodyAcpiTables->PkgOpcode          = PACKAGE_OPCODE;
+            pXpssBodyAcpiTables->PkgLength          = XPSS_PKG_LENGTH;
+            pXpssBodyAcpiTables->NumOfElements      = XPSS_NUM_OF_ELEMENTS;
+            pXpssBodyAcpiTables->XpssValueTbd       = 04;
+            pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE;
+
+            pXpssBodyAcpiTables->Frequency          =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
+
+            pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE;
+
+            pXpssBodyAcpiTables->Power              =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].Power;
+
+            pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE;
+
+            pXpssBodyAcpiTables->TransitionLatency  = TransAndBusMastLatency;
+            pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE;
+            pXpssBodyAcpiTables->BusMasterLatency   = TransAndBusMastLatency;
+            pXpssBodyAcpiTables->ControlBuffer      = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->ControlLo          = k;
+            pXpssBodyAcpiTables->ControlHi          = 0;
+            pXpssBodyAcpiTables->StatusBuffer       = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->StatusLo           = k;
+            pXpssBodyAcpiTables->StatusHi           = 0;
+            pXpssBodyAcpiTables->ControlMaskBuffer  = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->ControlMaskLo      = 0;
+            pXpssBodyAcpiTables->ControlMaskHi      = 0;
+            pXpssBodyAcpiTables->StatusMaskBuffer   = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->StatusMaskLo       = 0;
+            pXpssBodyAcpiTables->StatusMaskHi       = 0;
+
+            pXpssBodyAcpiTables++;
+          }
+        } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+        // Set XPSS Header again
+        // Now Set pssLength and numOfItemsInPss
+        //---------------------------------------
+        TempVar_a = (PStateCount * XPSS_BODY_STRUCT_SIZE) + 3;
+        if (TempVar_a > 63) {
+          TempVar_b = TempVar_a;
+          TempVar_d = ((TempVar_b << 4) & 0x0000FF00);
+          TempVar_d = TempVar_d | ((TempVar_b & 0x0000000F) | 0x00000040);
+          TempVar_a = (UINT16) TempVar_d;
+        }
+
+        pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a;
+        pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PStateCount;
+        TempVar_c += (XPSS_HEADER_STRUCT_SIZE + (PStateCount * XPSS_BODY_STRUCT_SIZE));
+
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pXpssBodyAcpiTables;
+      } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss
+
+      //
+      // Set _PSD Table - START
+      //------------------------
+      // Typecast the pointer
+      pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables;
+
+      //
+      // Get Total Cores Per Node
+      /// @todo Maybe this should ask for single core Sockets not single core nodes?
+      if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBufferStructPtr->SocketNumber, &CoreCount1, AmdConfigParamsStructPtr)) {
+        if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd)) {
+          //
+          // Set _PSD Header
+          //-----------------
+          pPsdHeaderAcpiTables->NameOpcode    = NAME_OPCODE;
+          pPsdHeaderAcpiTables->PkgOpcode     = PACKAGE_OPCODE;
+          pPsdHeaderAcpiTables->PsdLength     = PSD_HEADER_LENGTH;
+          pPsdHeaderAcpiTables->Value1        = PSD_VALUE1;
+
+          // Set _PSD Header
+          pPsdHeaderAcpiTables->PsdName_a__   = PSD_NAME__;
+          pPsdHeaderAcpiTables->PsdName_a_P   = PSD_NAME_P;
+          pPsdHeaderAcpiTables->PsdName_a_S   = PSD_NAME_S;
+          pPsdHeaderAcpiTables->PsdName_a_D   = PSD_NAME_D;
+
+          // Typecast the pointer
+          pPsdHeaderAcpiTables++;
+          TempVar_c += PSD_HEADER_STRUCT_SIZE;
+        }  // end of PSD Header if (CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd)
+     }
+      pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables;
+
+      if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd)) {
+        pPsdHeaderAcpiTables--;
+        //
+        // Set _PSD Body
+        //----------------
+        pPsdBodyAcpiTables->PkgOpcode           = PACKAGE_OPCODE;
+        pPsdBodyAcpiTables->PkgLength           = PSD_PKG_LENGTH;
+        pPsdBodyAcpiTables->NumOfEntries        = NUM_OF_ENTRIES;
+        pPsdBodyAcpiTables->BytePrefixOpcode1   = BYTE_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->PsdNumOfEntries     = PSD_NUM_OF_ENTRIES;
+        pPsdBodyAcpiTables->BytePrefixOpcode2   = BYTE_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->PsdRevision         = PSD_REVISION;
+        pPsdBodyAcpiTables->DwordPrefixOpcode1  = DWORD_PREFIX_OPCODE;
+        //
+        //Get ApicId from AMD CPU general service.
+        //Basically, DependencyDomain should be LocalApicId for each core PSD independent.
+        //
+        GetApicId (StdHeader, (UINT32) PStateLevelingBufferStructPtr->SocketNumber, j, &LocalApicId, &AgesaStatus);
+
+        GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+        if (FamilyServices != NULL) {
+          IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader);
+        }
+
+        if (IsPsdDependent) {
+          pPsdBodyAcpiTables->DependencyDomain    = PSD_DEPENDENCY_DOMAIN;
+          pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_SW_ALL;
+          pPsdBodyAcpiTables->NumOfProcessors     = CoreCount1;
+        } else {
+          pPsdBodyAcpiTables->DependencyDomain    = LocalApicId;
+          pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_SW_ANY;
+          pPsdBodyAcpiTables->NumOfProcessors     = PSD_NUM_OF_PROCESSORS;
+        }
+
+        pPsdBodyAcpiTables->DwordPrefixOpcode2  = DWORD_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->DwordPrefixOpcode3  = DWORD_PREFIX_OPCODE;
+
+        pPsdBodyAcpiTables++;
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPsdBodyAcpiTables;
+        TempVar_c += PSD_BODY_STRUCT_SIZE;
+      }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd)
+
+      //
+      // Set _PPC Table - START
+      //------------------------
+
+      // Typecast the pointer
+
+      pPpcHeaderBodyAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables;
+
+      // Set _PPC Header and Body
+      //--------------------------
+      if (OptionPstateLateConfiguration.CfgPstatePpc) {
+        pPpcHeaderBodyAcpiTables->NameOpcode            = NAME_OPCODE;
+        pPpcHeaderBodyAcpiTables->PpcName_a__           = PPC_NAME__;
+        pPpcHeaderBodyAcpiTables->PpcName_a_P           = PPC_NAME_P;
+        pPpcHeaderBodyAcpiTables->PpcName_b_P           = PPC_NAME_P;
+        pPpcHeaderBodyAcpiTables->PpcName_a_C           = PPC_NAME_C;
+        pPpcHeaderBodyAcpiTables->Value1                = PPC_VALUE1;
+
+        pPpcHeaderBodyAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport;
+        TempVar_c += PPC_HEADER_BODY_STRUCT_SIZE;
+        // Increment and typecast the pointer
+        pPpcHeaderBodyAcpiTables++;
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPpcHeaderBodyAcpiTables;
+      }// end of OptionPstateLateConfiguration.CfgPstatePpc
+
+      // If C6 is enabled, generate the corresponding ACPI object for it
+      if (IsFeatureEnabled (C6Cstate, PlatformConfig, StdHeader)) {
+        GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&C6FamilyServices, StdHeader);
+        C6FamilyServices->CreateAcpiCstObj ((VOID *) &ScopeAcpiTablesStructPtrTemp, StdHeader);
+        TempVar_c += C6FamilyServices->GetAcpiCstObj ();
+      }
+
+      //
+      // Now update the SCOPE Length field
+      //
+      {
+        TempVar_c += (SCOPE_STRUCT_SIZE - 1);
+        ScopeSize += TempVar_c;
+
+        TempVar_d = ((TempVar_c << 4) & 0x0000FF00);
+        TempVar_d |= ((TempVar_c & 0x0000000F) | 0x00000040);
+        TempVar_a = TempVar_d;
+        ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a;
+        TempVar_c = 0;
+      }
+
+      // Increment and typecast the pointer
+      ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp;
+
+    } // for (j = 0; j < MPPSTATE_MAX_CORES_PER_NODE; j++)
+
+    //
+    //Calculate next node buffer address
+    //
+    PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+
+  } // for (i = 0; i < NodeCount; i++)
+
+  //Update SSDT header Checksum
+  ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER));
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
new file mode 100755
index 0000000000..af55edfd67
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Pstate Table Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU _PSS related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 13766 $   @e \$Date: 2009-05-14 07:22:59 +0800 (Thu, 14 May 2009) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_PSTATE_TABLES_H_
+#define _CPU_PSTATE_TABLES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _PSTATE_CPU_FAMILY_SERVICES PSTATE_CPU_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT;
+
+/**
+ *  Family specific call to set core TscFreqSel.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ */
+typedef VOID F_PSTATE_SET_TSC_FREQ_SEL (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL;
+
+/**
+ * Provide the interface to the PSD dependent Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _PSTATE_CPU_FAMILY_SERVICES {
+  UINT16          Revision;                                         ///< Interface version
+  // Public Methods.
+  PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent;                  ///< Method: Family specific call to check if PSD is dependent.
+  PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel;                      ///< Method: Family specific call to set core TscFreqSel.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_PSTATE_TABLES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
new file mode 100755
index 0000000000..1447c450e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
@@ -0,0 +1,370 @@
+/**
+ * @file
+ *
+ * AMD SLIT, ACPI table related API functions.
+ *
+ * Contains code that generates the SLIT table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SLIT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionSlit.h"
+#include "heapManager.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "Topology.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration;  // global user config record
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuSlitHdrStruct =
+{
+  {'S','L','I','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'F','1','0',' ',' ',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+AcpiSlitHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     E X P O R T E D     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiSlitStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+AGESA_STATUS
+GetAcpiSlitMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+   );
+AGESA_STATUS
+ReleaseSlitBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+AGESA_STATUS
+ReleaseSlitBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete SLIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiSlit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader);
+  return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the SLIT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiSlitStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete SLIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiSlitMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+   )
+{
+  UINT8 MaxHops;
+  UINT8 SocketNum;
+  UINT8 i;
+  UINT8 j;
+  UINT8 *BufferPtr;
+  UINT8 *SocketTopologyDataPtr;
+  UINT8 *SocketTopologyPtr;
+  ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr;
+  AGESA_STATUS Flag;
+  ALLOCATE_HEAP_PARAMS AllocStruct;
+
+  MaxHops = 0;
+  SocketTopologyPtr = NULL;
+  Flag = AGESA_ERROR;
+
+  // find out the pointer to the BufferHandle which contains
+  // Node Topology information
+  AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr);
+  if (SocketTopologyPtr == 0) {
+    return (Flag);
+  }
+
+  SocketNum = *SocketTopologyPtr;
+
+  // create a buffer by calling IBV callout routine
+  AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER);
+  AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE;
+  AllocStruct.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) {
+    return (Flag);
+  }
+  *SlitPtr = AllocStruct.BufferPtr;
+
+  //SLIT header
+  LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+  CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr;
+  CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize;
+  BufferPtr = *SlitPtr;
+
+  Flag = AGESA_SUCCESS;
+  // SLIT body
+  // check if is PfMode (Prober Filer Mode)
+  if (!IsFeatureEnabled (HtAssist, PlatformConfig, StdHeader)) {
+    // probe filter is disabled
+
+    // get MaxHops
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        if (*SocketTopologyDataPtr > MaxHops) {
+          MaxHops = *SocketTopologyDataPtr;
+        }
+        SocketTopologyDataPtr++;
+      }
+    }
+
+    // the Max hop entries have a value of 13
+    // and all other entries have 10.
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        if (*SocketTopologyDataPtr++ == MaxHops) {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13;
+        } else {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10;
+        }
+      }
+    }
+  } else {
+    // probe filter is enabled
+
+    // formula : num_hops * 6 + 10
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+          AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) =
+          ((*SocketTopologyDataPtr++) * 6) + 10;
+      }
+    }
+  }
+
+  BufferPtr += sizeof (ACPI_TABLE_HEADER);
+  *((UINT64 *) BufferPtr) = (UINT64) SocketNum;
+
+  //Update SLIT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader);
+
+  return (Flag);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Find out the pointer to the BufferHandle which contains
+ * Node Topology information
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in] SocketTopologyPtr      Point to the address of Socket Topology
+ *
+ */
+VOID
+STATIC
+AcpiSlitHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBuffer;
+
+  LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) {
+    *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr;
+  }
+
+  return;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseSlitBufferStub
+ *
+ *  Description:
+ *      This is the default routine for use when the SLIT option is NOT requested.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseSlitBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseSlitBuffer
+ *
+ *  Description:
+ *     Deallocate SLIT buffer
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseSlitBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader);
+
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
new file mode 100755
index 0000000000..bf136043d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
@@ -0,0 +1,614 @@
+/**
+ * @file
+ *
+ * AMD SRAT, ACPI table related API functions.
+ *
+ * Contains code that Create the APCI SRAT Table after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ***************************************************************************/
+
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SRAT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "OptionSrat.h"
+#include "cpuRegisters.h"
+#include "cpuLateInit.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                          EXPORTED FUNCTIONS
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiSratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+AGESA_STATUS
+GetAcpiSratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration;  // global user config record
+
+#define NodeID 0x60
+#define FOURGB 0x010000
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *  All of the DATA should be defined in _CODE segment.
+ *  Use ROMDATA to specify that it belongs to _CODE.
+ *----------------------------------------------------------------------------
+ */
+STATIC CPU_SRAT_HEADER  ROMDATA CpuSratHdrStruct =
+{
+  {'S','R','A','T'},
+  0,
+  2,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'F','1','0',' ',' ',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1,
+  1,
+  {0, 0, 0, 0, 0, 0, 0, 0}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8
+STATIC
+*MakeApicEntry (
+  IN UINT8 ApicId,
+  IN UINT8 Domain,
+  IN UINT8 *BufferLocPtr
+  );
+
+UINT8
+STATIC
+*FillMemoryForCurrentNode (
+  IN      UINT8 *PDomain,
+  IN OUT  UINT8 *PDomainForBase640K,
+  IN      UINT8 Node,
+  IN OUT  UINT8 *BufferLocPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+STATIC
+*MakeMemEntry (
+  IN UINT8  PDomain,
+  IN UINT8  Node,
+  IN UINT32 Base,
+  IN UINT32 Size,
+  IN UINT8  *BufferLocPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Static Resource Affinity Table
+ * i.e. SRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+CreateAcpiSrat (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader);
+  return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the SRAT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiSratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Static Resource Affinity Table
+ * i.e. SRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiSratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  UINT8     *BufferPtr;
+  UINT8     NodeNum;
+  UINT8     NodeCount;
+  UINT8     PDomain;
+  UINT8     PDomainForBase640K;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    CoreNum;
+  UINT32    RegVal;
+  UINT32    tempVar_32;
+  AMD_APIC_PARAMS ApicParams;
+  PCI_ADDR  PciAddress;
+  CPU_SRAT_HEADER  *CpuSratHeaderStructPtr;
+  AGESA_BUFFER_PARAMS AllocParams;
+
+  // Get Node count
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID);
+  LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader);
+  NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1);
+
+  // The worst-case buffer size to request is for the SRAT table header, one
+  // entree for special region (base 640k block), two memory
+  // regions per node, and APIC entries for each core in the system.
+  tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY))
+               + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY))
+               + (MAX_NUMBER_CORES * sizeof (CPU_SRAT_APIC_ENTRY))));
+
+  if (*SratPtr == NULL) {
+    //
+    // Allocate a buffer by callback function
+    //
+    AllocParams.StdHeader = *StdHeader;
+    AllocParams.BufferLength = tempVar_32;
+    AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AllocParams) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader);
+
+    *SratPtr = AllocParams.BufferPointer;
+  }
+
+  CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr;
+  BufferPtr = (UINT8 *) *SratPtr;
+
+  // Copy acpiSRATHeader -> data buffer
+  LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader);
+
+  BufferPtr += sizeof (CPU_SRAT_HEADER);
+
+  // Place all memory and IO affinity entries
+  NodeNum = 0;
+  PDomain = 0;
+  PDomainForBase640K = 0xFF;
+  ApicParams.StdHeader = *StdHeader;
+  while (NodeNum < NodeCount) {
+    GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader);
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader);
+    for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) {
+      ApicParams.Socket = (UINT8) Socket;
+      ApicParams.Core = (UINT8) CoreNum;
+      AmdGetApicId (&ApicParams);
+      if (ApicParams.IsPresent) {
+        BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr);
+      }
+    }
+
+    NodeNum++;
+    PDomain = NodeNum;
+  }
+
+  // Store size in table (current buffer offset - buffer start offset)
+  CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr);
+
+  //Update SSDT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *                            L O C A L    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will build Memory entry for current node.
+ * Note that we only create a memory affinity entry if we find one
+ * that matches the current node.  This makes an easier to read table
+ * though it is not necessary.
+ *
+ *    @param[in]      PDomain            Proximity Domain
+ *    @param[in, out] PDomainForBase640K The PDomain for Base 640K
+ *    @param[in]      Node               The number of Node
+ *    @param[in, out] BufferLocPtr       Point to the address of buffer
+ *    @param[in, out] StdHeader          Standard Head Pointer
+ *
+ *    @retval         UINT8 *(New buffer location ptr)
+ */
+UINT8
+STATIC
+*FillMemoryForCurrentNode (
+  IN      UINT8 *PDomain,
+  IN OUT  UINT8 *PDomainForBase640K,
+  IN      UINT8 Node,
+  IN OUT  UINT8 *BufferLocPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    ValueLimit;
+  UINT32    ValueTOM;
+  BOOLEAN   isModified;
+  UINT8     Domain;
+  UINT32    RegVal;
+  UINT32    DramLeng;
+  UINT32    DramBase;
+  UINT32    DramLimit;
+  UINT32    OffsetRegs;
+  PCI_ADDR  PciAddress;
+  UINT64    MsrValue;
+  UINT32    TopOfMemoryAbove4Gb;
+
+  Domain = *PDomain;
+
+  PciAddress.Address.Segment = 0;
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = LOW_NODE_DEVICEID;
+  PciAddress.Address.Function = FUNC_1;
+
+  for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) {
+    isModified = FALSE;        // FALSE means normal update procedure
+    // Get DRAM Base Address
+    PciAddress.Address.Register = OffsetRegs;
+    LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader);
+    if ((DramBase & 3) != 3) {
+      // 0:1 set if memory range enabled
+      // Not set, so we don't have an enabled range
+      continue;   // Proceed to next Base register
+    }
+
+    // Get DRAM Limit
+    PciAddress.Address.Register = OffsetRegs + 4;
+    LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader);
+    if (DramLimit == 0xFFFFFFFF) {
+      // Node not installed(all FF's)?
+      continue;   // Proceed to next Base register
+    }
+
+    if ((DramLimit & 0xFF) != Node) {
+      // Check if Destination Node ID is current node
+      continue;   // Proceed to next Base register
+    }
+
+    //    We only add an entry now if detected range belongs to current node/PDomain
+    PciAddress.Address.Register = OffsetRegs + 0x104;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
+
+    DramLimit = (((RegVal & 0xFF) << 16) | (DramLimit >> 16));  // Get DRAM Limit addr [47:24]
+    DramLimit++;                     // Add 1 for potential length
+    DramLimit <<= 8;
+
+    // Get DRAM Base Address
+    PciAddress.Address.Register = OffsetRegs + 0x100;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
+    DramBase = ((((RegVal & 0xFF) << 24) | (DramBase >> 8)) & 0xFFFFFF00);   // Get DRAM Base Base value [47:24]
+    DramLeng = DramLimit - DramBase;    // Subtract base from limit to get length
+
+    //    Leave hole for conventional memory (Less than 640K).  It must be on CPU 0.
+    if (DramBase == 0) {
+      if (*PDomainForBase640K == 0xFF) {
+        // It is the first time that the range start at 0.
+        // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K
+        BufferLocPtr = MakeMemEntry (
+                         Domain,
+                         Node,
+                         0,              // Base = 0
+                         0xA0000 >> 16,  // Put it into format used in DRAM regs..
+                         BufferLocPtr
+                         );
+        DramBase += 0x10;       // Add 1MB, so range = 1MB to Top of Region
+        DramLeng -= 0x10;       // Also subtract 1MB from the length
+        *PDomainForBase640K = Domain;        // Save Domain number for memory Less than 640K
+      } else {
+        // If No, there are more than one memory range less than 640K, it should that
+        // node interleaving is enabled. All nodes have the same memory ranges
+        // and all cores in these nodes belong to the same domain.
+        *PDomain = *PDomainForBase640K;
+        return (BufferLocPtr);
+      }
+    }
+    LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader);
+    ValueTOM   = (UINT32) MsrValue >> 16;    // Save it in 39:24 format
+    ValueLimit = DramBase + DramLeng;        // We need to know how large region is
+
+    LibAmdMsrRead (SYS_CFG, &MsrValue, StdHeader);
+    if ((MsrValue & BIT21) != 0) {
+      LibAmdMsrRead (TOP_MEM2, &MsrValue, StdHeader);
+      TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16);    // Save it in 47:16 format
+    } else {
+      TopOfMemoryAbove4Gb = 0xFFFFFFFF;
+    }
+
+    //  SPECIAL CASES:
+    //
+    //  Several conditions require that we process the values of the memory range differently.
+    //  Here are descriptions of the corner cases.
+    //
+    //  1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole).  For this case,
+    //     the range must be truncated to end at TOM.
+    //  *******************************            *******************************
+    //  *                    *        *      ->    *                             *
+    //  *******************************            *******************************
+    //  2                    TOM      4            2                             TOM
+    //
+    //  2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB.  This is handled by changing the
+    //     start base to 4GB.
+    //          ****************                        **********
+    //          *     *        *      ->                *        *
+    //          ****************                        **********
+    //  TOM     3.8   4        6            TOM   3.8   4        6
+    //
+    //  3. Memory range starts below TOM, ends above 4GB.  For this case, the range must be truncated
+    //     to end at TOM.  Note that this scenario creates two ranges, as the second comparison below
+    //     will find that it ends above 4GB since base and limit have been restored after first truncation,
+    //     and a second range will be written based at 4GB ending at original end address.
+    //  *******************************            ****************          **********
+    //  *              *     *        *      ->    *              *          *        *
+    //  *******************************            ****************          **********
+    //  2              TOM   4        6            2              TOM        4        6
+    //
+    //  4. Memory range starts above TOM, ends below or equal to 4GB.  This invalid range should simply
+    //     be ignored.
+    //          *******
+    //          *     *      ->    < NULL >
+    //          *******
+    //  TOM     3.8   4
+    //
+    //  5. Memory range starts below TOM2, and ends beyond TOM2.  This range must be truncated to TOM2.
+    //  ************************         *******************************
+    //  *              *       *   ->    *                             *
+    //  ************************         *******************************
+    //  768          TOM2   1024         768                        TOM2
+    //
+    //  6. Memory range starts above TOM2.  This invalid range should simply be ignored.
+    //          ********************
+    //          *                  *    ->    < NULL >
+    //          ********************
+    //  TOM2    1024            1280
+
+    if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM))
+        || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) {
+      //   TRUNCATE LOW!!! Shrink entry below TOM...
+      //   Base = DramBase, Size = TOM - DramBase
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) {
+      //   TRUNCATE HIGH!!! Shrink entry above 4GB...
+      //   Size = Base + Size - 4GB, Base = 4GB
+      BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) {
+      //   IGNORE!!!  Entry located entirely within memory hole
+      isModified = TRUE;
+    }
+
+    if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) {
+      //   Truncate to TOM2
+      //   Base = DramBase, Size = TOM2 - DramBase
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (TopOfMemoryAbove4Gb - DramBase), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if (DramBase >= TopOfMemoryAbove4Gb) {
+      //   IGNORE!!!  Entry located entirely above TOM2
+      isModified = TRUE;
+    }
+
+    //    If special range(isModified), we are done.
+    //    If not, finally write the memory entry.
+    if (isModified == FALSE) {
+      // Finally write the memory entry.
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr);
+    }
+
+  } // for ( OffsetRegs = DRAMBase0; ... )
+
+  return (BufferLocPtr);
+} // FillMemoryForCurrentNode()
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add APIC entry.
+ *
+ *    @param[in]      ApicId            APIC ID number
+ *    @param[in]      Domain            Domain number
+ *    @param[in]      BufferLocPtr      Point to the address of buffer
+ *
+ *    @retval         UINT8 *(New buffer location ptr)
+ */
+UINT8
+STATIC
+*MakeApicEntry (
+  IN      UINT8 ApicId,
+  IN      UINT8 Domain,
+  IN      UINT8 *BufferLocPtr
+  )
+{
+  CPU_SRAT_APIC_ENTRY *psSratApicEntry;
+  UINT8 ReservedBytes;
+
+  psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr;
+
+  psSratApicEntry->Type = AE_APIC;
+  psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY);
+  psSratApicEntry->Domain = Domain;
+  psSratApicEntry->ApicId = ApicId;
+  psSratApicEntry->Flags = ENABLED;
+  psSratApicEntry->LSApicEid = 0;
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) {
+    psSratApicEntry->Reserved[ReservedBytes] = 0;
+  }
+  return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY));
+} // MakeApicEntry
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will add Memory entry.
+ *
+ *  Parameters:
+ *    @param[in]  PDomain               Proximity Domain
+ *    @param[in]  Node                  The number of Node
+ *    @param[in]  Base                  Memory Base
+ *    @param[in]  Size                  Memory Size
+ *    @param[in]  BufferLocPtr          Point to the address of buffer
+ *
+ *    @retval       UINT8 * (new buffer location ptr)
+ */
+UINT8
+STATIC
+*MakeMemEntry (
+  IN  UINT8   PDomain,
+  IN  UINT8   Node,
+  IN  UINT32  Base,
+  IN  UINT32  Size,
+  IN  UINT8   *BufferLocPtr
+  )
+{
+  CPU_SRAT_MEMORY_ENTRY *psSratMemEntry;
+  UINT8 ReservedBytes;
+
+  psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr;
+
+  psSratMemEntry->Type = AE_MEMORY;                       // [0] = Memory Entry
+  psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40
+  psSratMemEntry->Domain = PDomain;                            // [2] = Proximity Domain
+
+  // [6-7] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) {
+    psSratMemEntry->Reserved1[ReservedBytes] = 0;
+  }
+
+  // [8-11] = Keep 31:0 of address only -> Base Addr Low
+  psSratMemEntry->BaseAddrLow  = Base << 16;
+
+  // [12-15] = Keep 39:32 of address only -> Base Addr High
+  psSratMemEntry->BaseAddrHigh = Base >> 16;
+
+  // [16-19] = Keep 31:0 of address only -> Length Low
+  psSratMemEntry->LengthAddrLow  = Size << 16;
+
+  // [20-23] = Keep 39:32 of address only -> Length High
+  psSratMemEntry->LengthAddrHigh = Size >> 16;
+
+  // [24-27] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) {
+    psSratMemEntry->Reserved2[ReservedBytes] = 0;
+  }
+
+  // [28-31] = Flags
+  psSratMemEntry->Flags = ENABLED;
+
+  // [32-40] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) {
+    psSratMemEntry->Reserved3[ReservedBytes] = 0;
+  }
+  return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
+} // MakeMemEntry()
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
new file mode 100755
index 0000000000..fb8930269e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
@@ -0,0 +1,276 @@
+/**
+ * @file
+ *
+ * AMD WHEA Table Creation API, and related functions.
+ *
+ * Contains code that produce the ACPI WHEA related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionWhea.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+CreateHestBank (
+  IN       AMD_HEST_BANK *HestBankPtr,
+  IN       UINT8 BankNum,
+  IN       AMD_WHEA_INIT_DATA *WheaInitDataPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiWheaStub (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+AGESA_STATUS
+GetAcpiWheaMain (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create the ACPI table of WHEA and return the pointer to the table.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiWhea (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader);
+  return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the WHEA option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiWheaStub (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create the ACPI tale of WHEA and return the pointer to the table.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiWheaMain (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  UINT8  BankNum;
+  UINT8  Entries;
+  UINT16 HestMceTableSize;
+  UINT16 HestCmcTableSize;
+  UINT64 MsrData;
+  AMD_HEST_MCE_TABLE *HestMceTablePtr;
+  AMD_HEST_CMC_TABLE *HestCmcTablePtr;
+  AMD_HEST_BANK *HestBankPtr;
+  AMD_WHEA_INIT_DATA *WheaInitDataPtr;
+  AGESA_BUFFER_PARAMS AllocParams;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  FamilySpecificServices = NULL;
+
+  // step 1: calculate Hest table size
+  LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
+  BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count);
+  if (BankNum == 0) {
+    return AGESA_ERROR;
+  }
+
+  HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + BankNum * sizeof (AMD_HEST_BANK);
+  HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + BankNum * sizeof (AMD_HEST_BANK);
+
+  HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr;
+  HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr;
+
+  // step 2: allocate a buffer by callback function
+  if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) {
+    AllocParams.StdHeader = *StdHeader;
+    AllocParams.BufferLength = (UINT32) (HestMceTableSize + HestCmcTableSize);
+    AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AllocParams) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader);
+
+    HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPointer;
+    HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (BankNum * sizeof (AMD_HEST_BANK)));
+  }
+
+  // step 3: fill in Hest MCE table
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (CONST VOID **)&WheaInitDataPtr, &Entries, StdHeader);
+
+  ASSERT (BankNum <= WheaInitDataPtr->HestBankNum);
+
+  HestMceTablePtr->TblLength = HestMceTableSize;
+  HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD;
+  HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD;
+  HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD;
+  HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD;
+  HestMceTablePtr->NumHWBanks = BankNum;
+
+  HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1);
+  CreateHestBank (HestBankPtr, BankNum, WheaInitDataPtr);
+
+  // step 4: fill in Hest CMC table
+  HestCmcTablePtr->NumHWBanks = BankNum;
+  HestCmcTablePtr->TblLength = HestCmcTableSize;
+
+  HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1);
+  CreateHestBank (HestBankPtr, BankNum, WheaInitDataPtr);
+
+  // step 5: fill in the incoming structure
+  *WheaMcePtr = HestMceTablePtr;
+  *WheaCmcPtr = HestCmcTablePtr;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create Bank structure for Hest table
+ *
+ *    @param[in]  HestBankPtr           Pointer to the Hest Back structure
+ *    @param[in]  BankNum               The number of Bank
+ *    @param[in]  WheaInitDataPtr     Pointer to the AMD_WHEA_INIT_DATA structure
+ *
+ */
+VOID
+STATIC
+CreateHestBank (
+  IN       AMD_HEST_BANK *HestBankPtr,
+  IN       UINT8 BankNum,
+  IN       AMD_WHEA_INIT_DATA *WheaInitDataPtr
+  )
+{
+  UINT8 BankIndex;
+  for (BankIndex = 0; BankIndex < BankNum; BankIndex++) {
+    HestBankPtr->BankNum = BankIndex;
+    HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit;
+    HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat;
+    HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn;
+    HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr;
+    HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD;
+    HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD;
+    HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr;
+    HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr;
+    HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr;
+    HestBankPtr++;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c
new file mode 100755
index 0000000000..05a4827b21
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.c
@@ -0,0 +1,1166 @@
+/**
+ * @file
+ *
+ * ACPI S3 Support routines
+ *
+ * Contains routines needed for supporting resume from the ACPI S3 sleep state.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_S3_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+SaveDeviceContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+SavePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  );
+
+VOID
+SaveConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  );
+
+VOID
+SaveMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  );
+
+VOID
+SaveConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  );
+
+VOID
+RestorePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  );
+
+VOID
+RestoreConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  );
+
+VOID
+RestoreMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  );
+
+VOID
+RestoreConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves all devices in the given device list.
+ *
+ * This traverses the entire device list twice.  In the first pass, we save
+ * all devices identified as Pre ESR.  In the second pass, we save devices
+ * marked as post ESR.
+ *
+ * @param[in]     DeviceList        Beginning of the device list to save.
+ * @param[in]     Storage           Beginning of the context buffer.
+ * @param[in]     CallPoint         Indicates whether this is AMD_INIT_RESUME or
+ *                                  AMD_S3LATE_RESTORE.
+ * @param[out]    ActualBufferSize  Actual size used in saving the device list.
+ * @param[in]     StdHeader         AMD standard header config param.
+ *
+ */
+VOID
+SaveDeviceListContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       VOID                *Storage,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // Copy device list over
+  LibAmdMemCopy (Storage,
+                 DeviceList,
+                 (UINTN) DeviceList->RelativeOrMaskOffset,
+                 StdHeader);
+  SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves all devices in the given device list.
+ *
+ * This traverses the entire device list twice.  In the first pass, we save
+ * all devices identified as Pre ESR.  In the second pass, we save devices
+ * marked as post ESR.
+ *
+ * @param[in,out] DeviceList        Beginning of the device list to save.
+ * @param[in]     CallPoint         Indicates whether this is AMD_INIT_RESUME or
+ *                                  AMD_S3LATE_RESTORE.
+ * @param[out]    ActualBufferSize  Actual size used in saving the device list.
+ * @param[in]     StdHeader         AMD standard header config param.
+ *
+ */
+VOID
+SaveDeviceContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  UINT64 StartAddress;
+  UINT64 EndAddress;
+  VOID *OrMask;
+
+  StartAddress = (UINT32) DeviceList;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
+
+  // Process Pre ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_PCI:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CPCI:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_MSR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CMSR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  // Process Post ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI:
+      SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_PCI_PRE_ESR:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI:
+      SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CPCI_PRE_ESR:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR:
+      SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_MSR_PRE_ESR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR:
+      SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask);
+      // Fall through to advance the pointer after saving context
+    case DEV_TYPE_CMSR_PRE_ESR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+  EndAddress = (UINT32) OrMask;
+  *ActualBufferSize = (UINT32) (EndAddress - StartAddress);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of a PCI device.
+ *
+ * This traverses the provided register list saving PCI registers.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SavePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  AndMask;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  PCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+    PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+    RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+    switch (RegSizeInBytes) {
+    case 1:
+      AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+      AccessWidth = AccessS3SaveWidth8;
+      break;
+    case 2:
+      AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+      AccessWidth = AccessS3SaveWidth16;
+      break;
+    default:
+      AndMask = RegisterHdr->RegisterList[i].AndMask;
+      RegSizeInBytes = 4;
+      AccessWidth = AccessS3SaveWidth32;
+      break;
+    }
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);
+    }
+    **((UINT32 **) OrMask) &= AndMask;
+    IntermediatePtr = (UINT8 *) *OrMask;
+    *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of a 'conditional' PCI device.
+ *
+ * This traverses the provided register list saving PCI registers when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SaveConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  AndMask;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+      PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+      RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+      switch (RegSizeInBytes) {
+      case 1:
+        AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+        AccessWidth = AccessS3SaveWidth8;
+        break;
+      case 2:
+        AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+        AccessWidth = AccessS3SaveWidth16;
+        break;
+      default:
+        AndMask = RegisterHdr->RegisterList[i].AndMask;
+        RegSizeInBytes = 4;
+        AccessWidth = AccessS3SaveWidth32;
+        break;
+      }
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);
+      }
+      **((UINT32 **) OrMask) &= AndMask;
+      IntermediatePtr = (UINT8 *) *OrMask;
+      *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of an MSR device.
+ *
+ * This traverses the provided register list saving MSRs.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SaveMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  MSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader);
+    }
+    **OrMask &= RegisterHdr->RegisterList[i].AndMask;
+    (*OrMask)++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Saves the context of a 'conditional' MSR device.
+ *
+ * This traverses the provided register list saving MSRs when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+SaveConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  CMSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader);
+      }
+      **OrMask &= RegisterHdr->RegisterList[i].AndMask;
+      (*OrMask)++;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the maximum amount of space required to store all raw register
+ * values for the given device list.
+ *
+ * This traverses the entire device list, and calculates the worst case size
+ * of each device in the device list.
+ *
+ * @param[in]     DeviceList     Beginning of the device list.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        Size in bytes required for storing all registers.
+ */
+UINT32
+GetWorstCaseContextSize (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 WorstCaseSize;
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  REGISTER_BLOCK_HEADERS RegisterHdr;
+
+  WorstCaseSize = DeviceList->RelativeOrMaskOffset;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+
+  // Process Device List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_PCI:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader);
+      } else {
+        S3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.PciRegisters->NumRegisters * 4);
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_CPCI:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader);
+      } else {
+        S3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.CPciRegisters->NumRegisters * 4);
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_MSR:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader);
+      } else {
+        S3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.MsrRegisters->NumRegisters * 8);
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      // PRE_ESR and post ESR take the same amount of space
+    case DEV_TYPE_CMSR:
+      if (CallPoint == INIT_RESUME) {
+        MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader);
+      } else {
+        S3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader);
+      }
+      WorstCaseSize += (RegisterHdr.CMsrRegisters->NumRegisters * 8);
+      Device.CMsrDevice++;
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+  }
+  return (WorstCaseSize);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores all devices marked as 'before exiting self-refresh.'
+ *
+ * This traverses the entire device list, restoring all devices identified
+ * as Pre ESR.
+ *
+ * @param[in,out] OrMaskPtr      Current buffer pointer of raw register values.
+ * @param[in]     Storage        Beginning of the device list.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ */
+VOID
+RestorePreESRContext (
+     OUT   VOID              **OrMaskPtr,
+  IN       VOID              *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  DEVICE_BLOCK_HEADER *DeviceList;
+
+  DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  *OrMaskPtr = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
+
+  // Process Pre ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_PCI:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CPCI:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_MSR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CMSR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores all devices marked as 'after exiting self-refresh.'
+ *
+ * This traverses the entire device list, restoring all devices identified
+ * as Post ESR.
+ *
+ * @param[in]     OrMaskPtr      Current buffer pointer of raw register values.
+ * @param[in]     Storage        Beginning of the device list.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ */
+VOID
+RestorePostESRContext (
+  IN       VOID              *OrMaskPtr,
+  IN       VOID              *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  DEVICE_DESCRIPTORS Device;
+  UINT16 i;
+  DEVICE_BLOCK_HEADER *DeviceList;
+
+  DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+
+  // Process Pre ESR List
+  for (i = 0; i < DeviceList->NumDevices; i++) {
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI:
+      RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_PCI_PRE_ESR:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI:
+      RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CPCI_PRE_ESR:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR:
+      RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_MSR_PRE_ESR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR:
+      RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr);
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CMSR_PRE_ESR:
+      Device.CMsrDevice++;
+      break;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of a PCI device.
+ *
+ * This traverses the provided register list restoring PCI registers.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestorePciDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   VOID                  **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  AndMask;
+  UINT32  RegValueRead;
+  UINT32  RegValueWrite;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  PCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+    PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+    RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+    switch (RegSizeInBytes) {
+    case 1:
+      AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+      RegValueWrite = **(UINT8 **)OrMask;
+      AccessWidth = AccessS3SaveWidth8;
+      break;
+    case 2:
+      AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+      RegValueWrite = **(UINT16 **)OrMask;
+      AccessWidth = AccessS3SaveWidth16;
+      break;
+    default:
+      AndMask = RegisterHdr->RegisterList[i].AndMask;
+      RegSizeInBytes = 4;
+      RegValueWrite = **(UINT32 **)OrMask;
+      AccessWidth = AccessS3SaveWidth32;
+      break;
+    }
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);
+      RegValueWrite |= RegValueRead & (~AndMask);
+      LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,
+                                             PciAddress,
+                                             &RegValueRead,
+                                             StdHeader);
+      RegValueWrite |= RegValueRead & (~AndMask);
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,
+                                             PciAddress,
+                                             &RegValueWrite,
+                                             StdHeader);
+    }
+    IntermediatePtr = (UINT8 *) *OrMask;
+    *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of a 'conditional' PCI device.
+ *
+ * This traverses the provided register list restoring PCI registers when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' PCI device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestoreConditionalPciDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   VOID                              **OrMask
+  )
+{
+  UINT8   RegSizeInBytes;
+  UINT8   SpecialCaseIndex;
+  UINT8   *IntermediatePtr;
+  UINT16  i;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  RegValueRead;
+  UINT32  RegValueWrite;
+  UINT32  AndMask;
+  ACCESS_WIDTH AccessWidth;
+  AGESA_STATUS IgnoredSts;
+  PCI_ADDR PciAddress;
+  CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  GetSocketModuleOfNode ((UINT32) Device->Node,
+                               &Socket,
+                               &Module,
+                               StdHeader);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
+      PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
+      RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
+      switch (RegSizeInBytes) {
+      case 1:
+        AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
+        RegValueWrite = **(UINT8 **)OrMask;
+        AccessWidth = AccessS3SaveWidth8;
+        break;
+      case 2:
+        AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
+        RegValueWrite = **(UINT16 **)OrMask;
+        AccessWidth = AccessS3SaveWidth16;
+        break;
+      default:
+        AndMask = RegisterHdr->RegisterList[i].AndMask;
+        RegSizeInBytes = 4;
+        RegValueWrite = **(UINT32 **)OrMask;
+        AccessWidth = AccessS3SaveWidth32;
+        break;
+      }
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);
+        RegValueWrite |= RegValueRead & (~AndMask);
+        LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,
+                                             PciAddress,
+                                             &RegValueRead,
+                                             StdHeader);
+        RegValueWrite |= RegValueRead & (~AndMask);
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,
+                                               PciAddress,
+                                               &RegValueWrite,
+                                               StdHeader);
+      }
+      IntermediatePtr = (UINT8 *) *OrMask;
+      *OrMask = &IntermediatePtr[RegSizeInBytes];
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of an MSR device.
+ *
+ * This traverses the provided register list restoring MSRs.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestoreMsrDevice (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN       MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS           CallPoint,
+  IN OUT   UINT64                **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  UINT64  RegValueRead;
+  UINT64  RegValueWrite;
+  MSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    RegValueWrite = **OrMask;
+    if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+      LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader);
+      RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+      LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader);
+    } else {
+      SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address,
+                                                           &RegValueRead,
+                                                           StdHeader);
+      RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+      RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address,
+                                                           &RegValueWrite,
+                                                           StdHeader);
+    }
+    (*OrMask)++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores the context of a 'conditional' MSR device.
+ *
+ * This traverses the provided register list restoring MSRs when appropriate.
+ *
+ * @param[in]     StdHeader      AMD standard header config param.
+ * @param[in]     Device         'conditional' MSR device to restore.
+ * @param[in]     CallPoint      Indicates whether this is AMD_INIT_RESUME or
+ *                               AMD_S3LATE_RESTORE.
+ * @param[in,out] OrMask         Current buffer pointer of raw register values.
+ *
+ */
+VOID
+RestoreConditionalMsrDevice (
+  IN       AMD_CONFIG_PARAMS                 *StdHeader,
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+  IN       CALL_POINTS                       CallPoint,
+  IN OUT   UINT64                            **OrMask
+  )
+{
+  UINT8   SpecialCaseIndex;
+  UINT16  i;
+  UINT64  RegValueRead;
+  UINT64  RegValueWrite;
+  CMSR_REGISTER_BLOCK_HEADER *RegisterHdr;
+
+  if (CallPoint == INIT_RESUME) {
+    MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  } else {
+    S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
+  }
+
+  for (i = 0; i < RegisterHdr->NumRegisters; i++) {
+    if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
+        ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
+      RegValueWrite = **OrMask;
+      if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
+        LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader);
+        RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+        LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader);
+      } else {
+        SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address,
+                                                           &RegValueRead,
+                                                           StdHeader);
+        RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
+        RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address,
+                                                             &RegValueWrite,
+                                                             StdHeader);
+      }
+      (*OrMask)++;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to PCI register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[out]   NonMemoryRelatedDeviceList  List of devices to save and restore
+ *                                           during S3LateRestore.
+ * @param[in]    StdHeader                   AMD standard header config param.
+ *
+ */
+VOID
+GetNonMemoryRelatedDeviceList (
+     OUT   DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  *NonMemoryRelatedDeviceList = NULL;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to PCI register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output PCI register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to 'conditional' PCI register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output 'conditional' PCI register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to MSR register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output MSR register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Unique device ID to 'conditional' MSR register list translator.
+ *
+ * This translates the given device header in storage to the appropriate list
+ * of registers in the AGESA image.
+ *
+ * @param[in]     Device         Device header containing the unique ID.
+ * @param[out]    RegisterHdr    Output 'conditional' MSR register list pointer.
+ * @param[in]     StdHeader      AMD standard header config param.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+S3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  *RegisterHdr = NULL;
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3_PARAMS structure.
+ *
+ * This routine initializes failsafe values for the AMD_S3_PARAMS structure
+ * to be used by the AMD_INIT_RESUME, AMD_S3_SAVE, and AMD_S3LATE_RESTORE
+ * entry points.
+ *
+ * @param[in,out] S3Params       Required input parameter for the AMD_S3_SAVE,
+ *                               AMD_INIT_RESUME, and AMD_S3_SAVE entry points.
+ *
+ */
+VOID
+AmdS3ParamsInitializer (
+  OUT   AMD_S3_PARAMS *S3Params
+  )
+{
+  S3Params->Signature = 0x52545341;
+  S3Params->Version = 0x0000;
+  S3Params->VolatileStorage = NULL;
+  S3Params->VolatileStorageSize = 0x00000000;
+  S3Params->Flags = 0x00000000;
+  S3Params->NvStorage = NULL;
+  S3Params->NvStorageSize = 0x00000000;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.h
new file mode 100755
index 0000000000..3e72774213
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/S3.h
@@ -0,0 +1,394 @@
+/**
+ * @file
+ *
+ *  ACPI S3 support definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 7672 $   @e \$Date: 2008-08-25 21:30:52 -0500 (Mon, 25 Aug 2008) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _S3_H_
+#define _S3_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* Device related definitions */
+
+/// Header at the beginning of a context save buffer.
+typedef struct {
+  UINT16     Version;                 ///< Version of header
+  UINT16     NumDevices;              ///< Number of devices in the list
+  UINT16     RelativeOrMaskOffset;    ///< Size of device list + header
+} DEVICE_BLOCK_HEADER;
+
+/// S3 device types
+typedef enum {
+  DEV_TYPE_PCI_PRE_ESR,               ///< PCI device before exiting self-refresh
+  DEV_TYPE_PCI,                       ///< PCI device after exiting self-refresh
+  DEV_TYPE_CPCI_PRE_ESR,              ///< 'conditional' PCI device before exiting self-refresh
+  DEV_TYPE_CPCI,                      ///< 'conditional' PCI device after exiting self-refresh
+  DEV_TYPE_MSR_PRE_ESR,               ///< MSR device before exiting self-refresh
+  DEV_TYPE_MSR,                       ///< MSR device after exiting self-refresh
+  DEV_TYPE_CMSR_PRE_ESR,              ///< 'conditional' MSR device before exiting self-refresh
+  DEV_TYPE_CMSR                       ///< 'conditional' MSR device after exiting self-refresh
+} S3_DEVICE_TYPES;
+
+/// S3 restoration call points
+typedef enum {
+  INIT_RESUME,                        ///< AMD_INIT_RESUME
+  S3_LATE_RESTORE                     ///< AMD_S3LATE_RESTORE
+} CALL_POINTS;
+
+/// S3 device common header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< Appropriate S3_DEVICE_TYPES type
+} DEVICE_DESCRIPTOR;
+
+/// S3 PCI device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR
+  UINT8      Node;                    ///< Zero-based node number
+} PCI_DEVICE_DESCRIPTOR;
+
+/// S3 'conditional' PCI device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR
+  UINT8      Node;                    ///< Zero-based node number
+  UINT8      Mask1;                   ///< Conditional mask 1
+  UINT8      Mask2;                   ///< Conditional mask 2
+} CONDITIONAL_PCI_DEVICE_DESCRIPTOR;
+
+/// S3 MSR device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR
+} MSR_DEVICE_DESCRIPTOR;
+
+/// S3 'conditional' MSR device header
+typedef struct {
+  UINT32     RegisterListID;          ///< Unique ID of this device
+  UINT8      Type;                    ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR
+  UINT8      Mask1;                   ///< Conditional mask 1
+  UINT8      Mask2;                   ///< Conditional mask 2
+} CONDITIONAL_MSR_DEVICE_DESCRIPTOR;
+
+/* Special case related definitions */
+
+/**
+ * PCI special case save handler
+ *
+ * @param[in]     AccessWidth   8, 16, or 32 bit wide access
+ * @param[in]     Address       full PCI address of the register to save
+ * @param[out]    Value         Value read from the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR     Address,
+     OUT   VOID         *Value,
+  IN       VOID         *ConfigPtr
+  );
+
+/**
+ * PCI special case restore handler
+ *
+ * @param[in]     AccessWidth   8, 16, or 32 bit wide access
+ * @param[in]     Address       full PCI address of the register to save
+ * @param[in]     Value         Value to write to the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) (
+  IN       ACCESS_WIDTH       AccessWidth,
+  IN       PCI_ADDR           PciAddress,
+  IN       VOID               *Value,
+  IN       VOID               *StdHeader
+  );
+
+/**
+ * MSR special case save handler
+ *
+ * @param[in]     MsrAddress    Address of model specific register to save
+ * @param[out]    Value         Value read from the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) (
+  IN       UINT32             MsrAddress,
+     OUT   UINT64             *Value,
+  IN       VOID               *StdHeader
+  );
+
+/**
+ * MSR special case restore handler
+ *
+ * @param[in]     MsrAddress    Address of model specific register to restore
+ * @param[in]     Value         Value to write to the register
+ * @param[in]     ConfigPtr     AMD standard header config parameter
+ *
+ */
+typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) (
+  IN       UINT32             MsrAddress,
+  IN       UINT64             *Value,
+  IN       VOID               *StdHeader
+  );
+
+/// PCI special case save/restore structure.
+typedef struct {
+  PF_S3_SPECIAL_PCI_SAVE     Save;    ///< Save routine
+  PF_S3_SPECIAL_PCI_RESTORE  Restore; ///< Restore routine
+} PCI_SPECIAL_CASE;
+
+/// MSR special case save/restore structure.
+typedef struct {
+  PF_S3_SPECIAL_MSR_SAVE     Save;    ///< Save routine
+  PF_S3_SPECIAL_MSR_RESTORE  Restore; ///< Restore routine
+} MSR_SPECIAL_CASE;
+
+/* Register related definitions */
+/// S3 register type bit fields
+typedef struct {
+  UINT8      SpecialCaseIndex:4;      ///< Special Case array index
+  UINT8      RegisterSize:3;          ///< For PCI, 1 = byte, 2 = word, else = dword.
+                                      ///< For MSR, don't care
+  UINT8      SpecialCaseFlag:1;       ///< Indicates special case
+} S3_REGISTER_TYPE;
+
+/// S3 PCI register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = register size in bytes,
+                                      ///< Type[2:0] = special case index
+  UINT8             Function;         ///< PCI function of the register
+  UINT16            Offset;           ///< PCI offset of the register
+  UINT32            AndMask;          ///< AND mask to be applied to the value before saving
+} PCI_REG_DESCRIPTOR;
+
+/// S3 'conditional' PCI register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = register size in bytes,
+                                      ///< Type[2:0] = special case index
+  UINT8             Function;         ///< PCI function of the register
+  UINT16            Offset;           ///< PCI offset of the register
+  UINT32            AndMask;          ///< AND mask to be applied to the value before saving
+  UINT8             Mask1;            ///< conditional mask 1
+  UINT8             Mask2;            ///< conditional mask 2
+} CONDITIONAL_PCI_REG_DESCRIPTOR;
+
+/// S3 MSR register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = reserved,
+                                      ///< Type[2:0] = special case index
+  UINT32            Address;          ///< MSR address
+  UINT64            AndMask;          ///< AND mask to be applied to the value before saving
+} MSR_REG_DESCRIPTOR;
+
+/// S3 'conditional' MSR register descriptor.
+typedef struct {
+  S3_REGISTER_TYPE  Type;             ///< Type[7] = special case flag,
+                                      ///< Type[6:3] = reserved,
+                                      ///< Type[2:0] = special case index
+  UINT32            Address;          ///< MSR address
+  UINT64            AndMask;          ///< AND mask to be applied to the value before saving
+  UINT8             Mask1;            ///< conditional mask 1
+  UINT8             Mask2;            ///< conditional mask 2
+} CONDITIONAL_MSR_REG_DESCRIPTOR;
+
+/// Common header at the beginning of an S3 register list.
+typedef struct {
+  UINT16     Version;                 ///< Version of header
+  UINT16     NumRegisters;            ///< Number of registers in the list
+} REGISTER_BLOCK_HEADER;
+
+/// S3 PCI register list header.
+typedef struct {
+  UINT16                  Version;       ///< Version of header
+  UINT16                  NumRegisters;  ///< Number of registers in the list
+  PCI_REG_DESCRIPTOR      *RegisterList; ///< Pointer to the first register descriptor
+  PCI_SPECIAL_CASE        *SpecialCases; ///< Pointer to array of special case handlers
+} PCI_REGISTER_BLOCK_HEADER;
+
+/// S3 'conditional' PCI register list header.
+typedef struct {
+  UINT16                          Version;       ///< Version of header
+  UINT16                          NumRegisters;  ///< Number of registers in the list
+  CONDITIONAL_PCI_REG_DESCRIPTOR  *RegisterList; ///< Pointer to the first register descriptor
+  PCI_SPECIAL_CASE                *SpecialCases; ///< Pointer to array of special case handlers
+} CPCI_REGISTER_BLOCK_HEADER;
+
+/// S3 MSR register list header.
+typedef struct {
+  UINT16                 Version;       ///< Version of header
+  UINT16                 NumRegisters;  ///< Number of registers in the list
+  MSR_REG_DESCRIPTOR     *RegisterList; ///< Pointer to the first register descriptor
+  MSR_SPECIAL_CASE       *SpecialCases; ///< Pointer to array of special case handlers
+} MSR_REGISTER_BLOCK_HEADER;
+
+/// S3 'conditional' MSR register list header.
+typedef struct {
+  UINT16                          Version;       ///< Version of header
+  UINT16                          NumRegisters;  ///< Number of registers in the list
+  CONDITIONAL_MSR_REG_DESCRIPTOR  *RegisterList; ///< Pointer to the first register descriptor
+  MSR_SPECIAL_CASE                *SpecialCases; ///< Pointer to array of special case handlers
+} CMSR_REGISTER_BLOCK_HEADER;
+
+/// S3 device descriptor pointers for ease of proper pointer advancement.
+typedef union {
+  DEVICE_DESCRIPTOR *CommonDeviceHeader;         ///< Common header
+  PCI_DEVICE_DESCRIPTOR *PciDevice;              ///< PCI header
+  CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header
+  MSR_DEVICE_DESCRIPTOR *MsrDevice;              ///< MSR header
+  CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header
+} DEVICE_DESCRIPTORS;
+
+/// S3 register list header pointers for ease of proper pointer advancement.
+typedef union {
+  DEVICE_DESCRIPTOR          *CommonDeviceHeader; ///< Common header
+  PCI_REGISTER_BLOCK_HEADER  *PciRegisters;       ///< PCI header
+  CPCI_REGISTER_BLOCK_HEADER *CPciRegisters;      ///< 'conditional' PCI header
+  MSR_REGISTER_BLOCK_HEADER  *MsrRegisters;       ///< MSR header
+  CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters;      ///< 'conditional' MSR header
+} REGISTER_BLOCK_HEADERS;
+
+/// S3 Volatile Storage Header
+typedef struct {
+  UINT32  HeapOffset;                             ///< Offset to beginning of heap data
+  UINT32  HeapSize;                               ///< Size of the heap data
+  UINT32  RegisterDataOffset;                     ///< Offset to beginning of raw save data
+  UINT32  RegisterDataSize;                       ///< Size of raw save data
+} S3_VOLATILE_STORAGE_HEADER;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+GetWorstCaseContextSize (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       CALL_POINTS         CallPoint,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+SaveDeviceListContext (
+  IN       DEVICE_BLOCK_HEADER *DeviceList,
+  IN       VOID                *Storage,
+  IN       CALL_POINTS         CallPoint,
+     OUT   UINT32              *ActualBufferSize,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+RestorePreESRContext (
+     OUT   VOID **OrMaskPtr,
+  IN       VOID *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+RestorePostESRContext (
+  IN       VOID *OrMaskPtr,
+  IN       VOID *Storage,
+  IN       CALL_POINTS       CallPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdS3ParamsInitializer (
+     OUT   AMD_S3_PARAMS *S3Params
+  );
+
+VOID
+GetNonMemoryRelatedDeviceList (
+     OUT   DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+S3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+AGESA_STATUS
+S3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+S3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+
+#endif  // _S3_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c
new file mode 100755
index 0000000000..4f767b8f27
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.c
@@ -0,0 +1,1576 @@
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Set registers according to a set of register tables
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Table.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_TABLE_FILECODE
+
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+VOID
+SetRegistersFromTablesAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * An iterator for all the Family and Model Register Tables.
+ *
+ * RegisterTableHandle should be set to NULL to begin iteration, the first time the method is
+ * invoked.  Register tables can be processed, until this method returns NULL.  RegisterTableHandle
+ * should simply be passed back to the method without modification or use by the caller.
+ * The table selector allows the relevant tables for different cores to be iterated, if the family separates
+ * tables.  For example, MSRs can be in a table processed by all cores and PCI registers in a table processed by
+ * primary cores.
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     Selector                Select whether to iterate over tables for either all cores, primary cores, bsp, ....
+ * @param[in,out] RegisterTableHandle     IN: The handle of the current register table, or NULL if Begin.
+ *                                        OUT: The handle of the next register table, if not End.
+ * @param[out]    NumberOfEntries         The number of entries in the table returned, if not End.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @return        The pointer to the next Register Table, or NULL if End.
+ */
+TABLE_ENTRY_FIELDS
+STATIC
+*GetNextRegisterTable (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       TABLE_CORE_SELECTOR     Selector,
+  IN OUT   REGISTER_TABLE       ***RegisterTableHandle,
+     OUT   UINTN                  *NumberOfEntries,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  REGISTER_TABLE **NextTable;
+  TABLE_ENTRY_FIELDS *Entries;
+
+  ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL));
+  ASSERT (Selector < (TABLE_CORE_SELECTOR)TableEntryTypeMax);
+
+  NextTable = *RegisterTableHandle;
+  if (NextTable == NULL) {
+    // Begin
+    NextTable = FamilySpecificServices->RegisterTableList;
+  } else {
+    NextTable++;
+  }
+  // skip if not selected
+  while ((*NextTable != NULL) && (*NextTable)->Selector != Selector) {
+    NextTable++;
+  }
+  if (*NextTable == NULL) {
+    // End
+    *RegisterTableHandle = NULL;
+    Entries = NULL;
+  } else {
+    // Iterate next table
+    *RegisterTableHandle = NextTable;
+    *NumberOfEntries = (*NextTable)->NumberOfEntries;
+    Entries = (TABLE_ENTRY_FIELDS *) (*NextTable)->Table;
+  }
+  return Entries;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Compare counts to a pair of ranges.
+ *
+ * @param[in]       FirstCount       The actual count to be compared to the first range.
+ * @param[in]       SecondCount      The actual count to be compared to the second range.
+ * @param[in]       Ranges           The ranges which the counts are compared to.
+ *
+ * @retval          TRUE             Either one, or both, of the counts is in the range given.
+ * @retval          FALSE            Neither count is in the range given.
+ */
+BOOLEAN
+IsEitherCountInRange (
+  IN       UINTN                FirstCount,
+  IN       UINTN                SecondCount,
+  IN       COUNT_RANGE_FEATURE  Ranges
+  )
+{
+  // Errors: Entire Range value is zero, Min and Max reversed or not <=, ranges overlap (OK if first range is all),
+  // the real counts are too big.
+  ASSERT ((Ranges.Range0Min <= Ranges.Range0Max) &&
+          (Ranges.Range1Min <= Ranges.Range1Max) &&
+          (Ranges.Range0Max != 0) &&
+          (Ranges.Range1Max != 0) &&
+          ((Ranges.Range0Max == COUNT_RANGE_HIGH) || (Ranges.Range0Max < Ranges.Range1Min)) &&
+          ((FirstCount < COUNT_RANGE_HIGH) && (SecondCount < COUNT_RANGE_HIGH)));
+
+  return (BOOLEAN) (((FirstCount <= Ranges.Range0Max) && (FirstCount >= Ranges.Range0Min)) ||
+                   ((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
+}
+
+/*-------------------------------------------------------------------------------------*/
+/**
+ * Returns the performance profile features list of the currently running processor core.
+ *
+ * @param[out]      Features          The performance profile features supported by this platform
+ * @param[in]       PlatformConfig    Config handle for platform specific information
+ * @param[in]       StdHeader         Header for library and services
+ *
+ */
+VOID
+GetPerformanceFeatures (
+     OUT   PERFORMANCE_PROFILE_FEATS    *Features,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+
+  Features->PerformanceProfileValue = 0;
+  // Reflect Probe Filter Configuration.
+  Features->PerformanceProfileFeatures.ProbeFilter = 0;
+  if (IsFeatureEnabled (HtAssist, PlatformConfig, StdHeader)) {
+    Features->PerformanceProfileFeatures.ProbeFilter = 1;
+  }
+
+  // Reflect Display Refresh Requests use 32 bytes Configuration.
+  Features->PerformanceProfileFeatures.RefreshRequest32Byte = 0;
+  if (PlatformConfig->PlatformProfile.Use32ByteRefresh) {
+    Features->PerformanceProfileFeatures.RefreshRequest32Byte = 1;
+  }
+  // Reflect Mct Isoc Read Priority set to variable Configuration.
+  Features->PerformanceProfileFeatures.MctIsocVariable = 0;
+  if (PlatformConfig->PlatformProfile.UseVariableMctIsocPriority) {
+    Features->PerformanceProfileFeatures.MctIsocVariable = 1;
+  }
+  // Indicate if this boot is a warm reset.
+  Features->PerformanceProfileFeatures.IsWarmReset = 0;
+  if (IsWarmReset (StdHeader)) {
+    Features->PerformanceProfileFeatures.IsWarmReset = 1;
+  }
+
+  // Get L3 Cache present as indicated by CPUID
+  Features->PerformanceProfileFeatures.L3Cache = 0;
+  Features->PerformanceProfileFeatures.NoL3Cache = 1;
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuidDataStruct, StdHeader);
+  if (((CpuidDataStruct.EDX_Reg & 0xFFFC0000) >> 18) != 0) {
+    Features->PerformanceProfileFeatures.L3Cache = 1;
+    Features->PerformanceProfileFeatures.NoL3Cache = 0;
+  }
+
+  // Get VRM select high speed from build option.
+  Features->PerformanceProfileFeatures.VrmHighSpeed = 0;
+  if (PlatformConfig->VrmProperties.HiSpeedEnable) {
+    Features->PerformanceProfileFeatures.VrmHighSpeed = 1;
+  }
+
+  // Get some family, model specific performance type info.
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+
+  // Is the Northbridge P-State feature enabled
+  Features->PerformanceProfileFeatures.NbPstates = 0;
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, StdHeader)) {
+    Features->PerformanceProfileFeatures.NbPstates = 1;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the MSR Register Entry.
+ *
+ * @TableEntryTypeMethod{::MsrRegister}.
+ *
+ * Read - Modify - Write the MSR, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The MSR register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForMsrEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64          MsrData;
+
+  // Even for only single bit fields, use those in the mask.  "Mask nothing" is a bug, even if just by policy.
+  ASSERT (Entry->MsrEntry.Mask != 0);
+
+  LibAmdMsrRead (Entry->MsrEntry.Address, &MsrData, StdHeader);
+  MsrData = MsrData & (~(Entry->MsrEntry.Mask));
+  MsrData = MsrData | Entry->MsrEntry.Data;
+  LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::PciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32          TempVar32_a;
+  UINT32          MySocket;
+  UINT32          MyModule;
+  UINT32          Ignored;
+  PCI_ADDR        MyPciAddress;
+  AGESA_STATUS    IgnoredSts;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  // Even for only single bit fields, use those in the mask.  "Mask nothing" is a bug, even if just by policy.
+  ASSERT ((Entry->InitialValues[4] == 0) &&
+          (Entry->InitialValues[3] == 0) &&
+          (Entry->PciEntry.Mask != 0));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, MySocket, MyModule, &MyPciAddress, &IgnoredSts);
+  MyPciAddress.Address.Function = Entry->PciEntry.Address.Address.Function;
+  MyPciAddress.Address.Register = Entry->PciEntry.Address.Address.Register;
+  LibAmdPciRead (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
+  TempVar32_a = TempVar32_a & (~(Entry->PciEntry.Mask));
+  TempVar32_a = TempVar32_a | Entry->PciEntry.Data;
+  LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Errata Workaround Register Entry.
+ *
+ * @TableEntryTypeMethod{::ErrataWorkaround}.
+ *
+ * Call the function, passing the data.
+ *
+ * See if you can use the other entries or make an entry that covers the fix.
+ * After all, the purpose of having a table entry is to @b NOT have code which
+ * isn't generic feature code, but is family/model code specific to one case.
+ *
+ * @param[in]     Entry             The Errata Workaround register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForErrataWorkaroundEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  ASSERT (Entry->ErrataEntry.DoAction != NULL);
+
+  Entry->ErrataEntry.DoAction (Entry->ErrataEntry.Data, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Finds the HT link capability set for a particular node/link.
+ *
+ * This function traverses the desired node's PCI capabilities searching
+ * for the HT capabilities associated with the desired HT link.  If found,
+ * the PCI address of the capability block will be returned.
+ *
+ * @param[in]      Link             Zero based link number on Node
+ * @param[in,out]  CapabilitySet    PCI address of the link's capability block
+ * @param[in]      StdHeader        Config handle for library and services
+ *
+ * @retval     TRUE             Node/link capabilities found
+ * @retval     FALSE            Node/link capabilities not found
+ *
+ */
+BOOLEAN
+FindHtHostCapability (
+  IN       UINTN              Link,
+  IN OUT   PCI_ADDR           *CapabilitySet,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32    CapabilityReg;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   Result;
+
+  Result = FALSE;
+  PciAddress = *CapabilitySet;
+  PciAddress.Address.Register = 0;
+  // Convert link from zero base to one base and adjust for sub link 0/1 split.
+  Link++;
+  PciAddress.Address.Function = ((Link > 4) ? 4 : 0);
+  Link = ((Link > 4) ? (Link - 4) : Link);
+
+  // Until either all capabilities are done or until the desired link is found,
+  // keep looking for HT Host Capabilities.
+  while (Link != 0) {
+    LibAmdPciFindNextCap (&PciAddress, StdHeader);
+    if (PciAddress.AddressValue != ILLEGAL_SBDFO) {
+      LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader);
+      if ((CapabilityReg & 0xE00000FF) == 0x20000008) {
+        Link--;
+      }
+      // A capability other than an HT capability, keep looking.
+    } else {
+      // end of capabilities
+      break;
+    }
+  }
+  if (Link == 0) {
+    // If we found the link, update the caller's pointer and success.
+    *CapabilitySet = PciAddress;
+    Result = TRUE;
+  }
+  return Result ;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program HT Phy PCI registers using BKDG values.
+ *
+ * @TableEntryTypeMethod{::HtPhyRegister}.
+ *
+ *
+ * @param[in]       Entry               The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForHtPhyEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->InitialValues[4] == 0) &&
+          ((Entry->HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->HtPhyEntry.Address < HTPHY_REGISTER_MAX));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (Link < 4) {
+    if (FindHtHostCapability (Link, &CapabilitySet, StdHeader)) {
+      if (FamilySpecificServices->DoesLinkHaveHtPhyFeats (
+            FamilySpecificServices,
+            CapabilitySet,
+            Link,
+            &Entry->HtPhyEntry.TypeFeats,
+            &MatchedSublink1,
+            &Freq0,
+            &Freq1,
+            StdHeader)) {
+        FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyEntry, CapabilitySet, Link, StdHeader);
+      }
+    } else {
+      //  No more Capabilities, no more links present
+      break;
+    }
+    Link ++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program a range of HT Phy PCI registers using BKDG values.
+ *
+ * @TableEntryTypeMethod{::HtPhyRangeRegister}.
+ *
+ *
+ * @param[in]       Entry               The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForHtPhyRangeEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  HT_PHY_TYPE_ENTRY_DATA CurrentHtPhyRegister;
+  BOOLEAN                MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtPhyRangeEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->HtPhyRangeEntry.LowAddress <= Entry->HtPhyRangeEntry.HighAddress) &&
+          (Entry->HtPhyRangeEntry.HighAddress < HTPHY_REGISTER_MAX) &&
+          (Entry->HtPhyRangeEntry.HighAddress != 0));
+
+  CurrentHtPhyRegister.Mask = Entry->HtPhyRangeEntry.Mask;
+  CurrentHtPhyRegister.Data = Entry->HtPhyRangeEntry.Data;
+  CurrentHtPhyRegister.TypeFeats = Entry->HtPhyRangeEntry.TypeFeats;
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (Link < 4) {
+    if (FindHtHostCapability (Link, &CapabilitySet, StdHeader)) {
+      if (FamilySpecificServices->DoesLinkHaveHtPhyFeats (
+            FamilySpecificServices,
+            CapabilitySet,
+            Link,
+            &Entry->HtPhyRangeEntry.TypeFeats,
+            &MatchedSublink1,
+            &Freq0,
+            &Freq1,
+            StdHeader)) {
+        for (CurrentHtPhyRegister.Address = Entry->HtPhyRangeEntry.LowAddress;
+             CurrentHtPhyRegister.Address <= Entry->HtPhyRangeEntry.HighAddress;
+             CurrentHtPhyRegister.Address++) {
+          FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &CurrentHtPhyRegister, CapabilitySet, Link, StdHeader);
+        }
+      }
+    } else {
+      //  No more Capabilities, no more links present
+      break;
+    }
+    Link ++;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is PackageLink an Internal Link?
+ *
+ * This is a test for the logical link match codes in the user interface, not a test for
+ * the actual northbridge links.
+ *
+ * @param[in]    PackageLink   The link
+ *
+ * @retval       TRUE          This is an internal link
+ * @retval       FALSE         This is not an internal link
+ */
+BOOLEAN
+STATIC
+IsDeemphasisLinkInternal (
+  IN       UINT32  PackageLink
+  )
+{
+  return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Package Link number, for the current node and real link number.
+ *
+ * Based on the link to package link mapping from BKDG, look up package link for
+ * the input link on the internal node number corresponding to the current core's node.
+ * For single module processors, the northbridge link and package link are the same.
+ *
+ * @param[in]   Link                      the link on the current node.
+ * @param[in]   FamilySpecificServices    CPU specific support interface.
+ * @param[in]   StdHeader                 Config params for library, services.
+ *
+ * @return      the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
+ *
+ */
+UINT32
+STATIC
+LookupPackageLink (
+  IN       UINT32                 Link,
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32 PackageLinkMapItem;
+  UINT32 PackageLink;
+  AP_MAIL_INFO ApMailbox;
+
+  PackageLink = HT_LIST_TERMINAL;
+
+  GetApMailbox (&ApMailbox.Info, StdHeader);
+
+  if (ApMailbox.Fields.ModuleType != 0) {
+    ASSERT (FamilySpecificServices->PackageLinkMap != NULL);
+    // Use table to find this module's package link
+    PackageLinkMapItem = 0;
+    while ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
+      if (((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Module == ApMailbox.Fields.Module) &&
+          ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
+        PackageLink = (*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].PackageLink;
+        break;
+      }
+      PackageLinkMapItem++;
+    }
+  } else {
+    PackageLink = Link;
+  }
+  return PackageLink;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the platform's specified deemphasis levels for the current link.
+ *
+ * Search the platform's list for a match to the current link and also matching frequency.
+ * If a match is found, use the specified deemphasis levels.
+ *
+ * @param[in]       Socket                    The current Socket.
+ * @param[in]       Link                      The link on that socket.
+ * @param[in]       Frequency                 The frequency the link is set to.
+ * @param[in]       PlatformConfig            Config handle for platform specific information
+ * @param[in]       FamilySpecificServices    CPU specific support interface.
+ * @param[in]       StdHeader                 Config params for library, services.
+ *
+ * @return          The Deemphasis values for the link.
+ */
+UINT32
+STATIC
+GetLinkDeemphasis (
+  IN       UINT32                  Socket,
+  IN       UINT32                  Link,
+  IN       HT_FREQUENCIES          Frequency,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 Result;
+  CPU_HT_DEEMPHASIS_LEVEL *Match;
+  UINT32 PackageLink;
+
+  PackageLink = LookupPackageLink (Link, FamilySpecificServices, StdHeader);
+  // All External and Internal links have deemphasis level none as the default.
+  // However, it is expected that the platform BIOS will provide deemphasis levels for the external links.
+  Result = ((DCV_LEVEL_NONE) | (DEEMPHASIS_LEVEL_NONE));
+
+  if (PlatformConfig->PlatformDeemphasisList != NULL) {
+    Match = PlatformConfig->PlatformDeemphasisList;
+    while (Match->Socket != HT_LIST_TERMINAL) {
+      if (((Match->Socket == Socket) || (Match->Socket == HT_LIST_MATCH_ANY)) &&
+          ((Match->Link == PackageLink) ||
+           ((Match->Link == HT_LIST_MATCH_ANY) && (!IsDeemphasisLinkInternal (PackageLink))) ||
+           ((Match->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsDeemphasisLinkInternal (PackageLink)))) &&
+          ((Match->LoFreq <= Frequency) && (Match->HighFreq >= Frequency))) {
+        // Found a match, get the deemphasis value.
+        ASSERT ((MaxPlatformDeemphasisLevel > Match->DcvDeemphasis) | (MaxPlatformDeemphasisLevel > Match->ReceiverDeemphasis));
+        Result = ((1 << Match->DcvDeemphasis) | (1 << Match->ReceiverDeemphasis));
+        break;
+      } else {
+        Match++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program Deemphasis registers using BKDG values, for the platform specified levels.
+ *
+ * @TableEntryTypeMethod{::DeemphasisRegister}.
+ *
+ *
+ * @param[in]    Entry            The type specific entry data to be implemented (that is written).
+ * @param[in]    PlatformConfig   Config handle for platform specific information
+ * @param[in]    StdHeader        Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForDeemphasisEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->DeemphasisEntry.Levels.DeemphasisValues & ~(VALID_DEEMPHASIS_LEVELS)) == 0) &&
+          ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->DeemphasisEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (Link < 4) {
+    if (FindHtHostCapability (Link, &CapabilitySet, StdHeader)) {
+      if (FamilySpecificServices->DoesLinkHaveHtPhyFeats (
+            FamilySpecificServices,
+            CapabilitySet,
+            Link,
+            &Entry->DeemphasisEntry.HtPhyEntry.TypeFeats,
+            &MatchedSublink1,
+            &Freq0,
+            &Freq1,
+            StdHeader)) {
+        if (DoesEntryTypeSpecificInfoMatch (
+              GetLinkDeemphasis (
+                MySocket,
+                (MatchedSublink1 ? (Link + 4) : Link),
+                (MatchedSublink1 ? Freq1 : Freq0),
+                PlatformConfig,
+                FamilySpecificServices,
+                StdHeader),
+              Entry->DeemphasisEntry.Levels.DeemphasisValues)) {
+          FamilySpecificServices->SetHtPhyRegister (
+            FamilySpecificServices,
+            &Entry->DeemphasisEntry.HtPhyEntry,
+            CapabilitySet,
+            Link,
+            StdHeader
+            );
+        }
+      }
+    } else {
+      //  No more Capabilities, no more links present
+      break;
+    }
+    Link ++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program HT Phy PCI registers which have complex frequency dependencies.
+ *
+ * @TableEntryTypeMethod{::HtPhyFreqRegister}.
+ *
+ *
+ * @param[in]       Entry               The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ *
+ */
+VOID
+SetRegisterForHtPhyFreqEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                Link;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  PCI_ADDR              CapabilitySet;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  BOOLEAN               MatchedSublink1;
+  HT_FREQUENCIES        Freq0;
+  HT_FREQUENCIES        Freq1;
+  BOOLEAN               Temp;
+  UINT32                NbFreq;
+
+  // Errors:  extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
+          (Entry->HtPhyFreqEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX));
+
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  Link = 0;
+  while (Link < 4) {
+    if (FindHtHostCapability (Link, &CapabilitySet, StdHeader)) {
+      if (FamilySpecificServices->DoesLinkHaveHtPhyFeats (
+            FamilySpecificServices,
+            CapabilitySet,
+            Link,
+            &Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats,
+            &MatchedSublink1,
+            &Freq0,
+            &Freq1,
+            StdHeader)) {
+        // Check the HT Frequency for match to the range.
+        if (IsEitherCountInRange (
+              (MatchedSublink1 ? Freq1 : Freq0),
+              (MatchedSublink1 ? Freq1 : Freq0),
+              Entry->HtPhyFreqEntry.HtFreqCounts.HtFreqCountRanges)) {
+          // Get the NB Frequency, convert to 100's of MHz, then convert to equivalent HT encoding.  This supports
+          // NB frequencies from 800 MHz to 2600 MHz, which is currently greater than any processor supports.
+          OptionMultiSocketConfiguration.GetSystemNbCof (&NbFreq, &Temp, StdHeader);
+          NbFreq = (NbFreq / 100);
+          NbFreq = (NbFreq / 2) + 1;
+          if (IsEitherCountInRange (NbFreq, NbFreq, Entry->HtPhyFreqEntry.NbFreqCounts.HtFreqCountRanges)) {
+            FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyFreqEntry.HtPhyEntry, CapabilitySet, Link, StdHeader);
+          }
+        }
+      }
+    } else {
+      //  No more Capabilities, no more links present
+      break;
+    }
+    Link ++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Performance Profile PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::ProfileFixup}.
+ *
+ * Check the entry's performance profile features to the platform's and do the
+ * PCI register entry if they match.
+ *
+ * @param[in]     Entry             The Performance Profile register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForPerformanceProfileEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->InitialValues[4] == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                      Entry->FixupEntry.TypeFeats.PerformanceProfileValue)) {
+    LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+    PciEntry.PciEntry = Entry->FixupEntry.PciEntry;
+    SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Phy Performance Profile Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtPhyProfileRegister}.
+ *
+ * @param[in]     Entry             The HT Phy register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtPhyProfileEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  TABLE_ENTRY_DATA          HtPhyEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->InitialValues[5] == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                      Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue)) {
+    LibAmdMemFill (&HtPhyEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+    HtPhyEntry.HtPhyEntry = Entry->HtPhyProfileEntry.HtPhyEntry;
+    SetRegisterForHtPhyEntry (&HtPhyEntry, PlatformConfig, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Host PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtHostPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * For all HT links, check the link's feature set for a match to the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtHostEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINTN                 LinkCount;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  UINT32                RegisterData;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->InitialValues[4] == 0) &&
+          ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
+          (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX));
+
+  HtHostFeats.HtHostValue = 0;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+  LinkCount = 0;
+  while (LinkCount < 8) {
+    if (FindHtHostCapability (LinkCount, &CapabilitySet, StdHeader)) {
+      FamilySpecificServices->GetHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader);
+      if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) {
+        // Do the HT Host PCI register update.
+        CapabilitySet.Address.Register += Entry->HtHostEntry.Address.Address.Register;
+        LibAmdPciRead (AccessWidth32, CapabilitySet, &RegisterData, StdHeader);
+        RegisterData = RegisterData & (~(Entry->HtHostEntry.Mask));
+        RegisterData = RegisterData | Entry->HtHostEntry.Data;
+        LibAmdPciWrite (AccessWidth32, CapabilitySet, &RegisterData, StdHeader);
+      }
+    } else {
+      // No more Capabilities.  Switch to sublink 1's if we are just done with sublink 0's.
+      // (This case handles less than 4 links are implemented in the processor.)
+      if (CapabilitySet.Address.Function == 0) {
+        CapabilitySet.Address.Function = 4;
+        LinkCount = 3;
+      } else {
+        break;
+      }
+    }
+    LinkCount ++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Core Counts Performance PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::CoreCountsPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForCoreCountsPerformanceEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN ActualCoreCount;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue)) {
+    ActualCoreCount = GetActiveCoresInCurrentModule (StdHeader);
+    // Check if the actual core count is in either range.
+    if (IsEitherCountInRange (ActualCoreCount, ActualCoreCount, Entry->CoreCountEntry.CoreCounts.CoreRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->CoreCountEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Processor Counts PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::ProcCountsPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForProcessorCountsEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN ProcessorCount;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue)) {
+    ProcessorCount = GetNumberOfProcessors (StdHeader);
+    // Check if the actual processor count is in either range.
+    if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->ProcCountEntry.ProcessorCounts.ProcessorCountRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the Processor Token Counts PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::TokenPciRegister}.
+ *
+ * The table criteria then translate as:
+ * - 2 Socket, half populated  ==   Degree 1
+ * - 4 Socket, half populated   ==  Degree 2
+ * - 2 Socket, fully populated  ==  Degree 3
+ * - 4 Socket, fully populated  ==  Degree > 3.  (4 or 5 if 3P, 6 if 4P)
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForTokenPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN                     SystemDegree;
+  TABLE_ENTRY_DATA          PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
+
+  GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue)) {
+    SystemDegree = GetSystemDegree (StdHeader);
+    // Check if the system degree is in the range.
+    if (IsEitherCountInRange (SystemDegree, SystemDegree, Entry->TokenPciEntry.ConnectivityCount.ConnectivityCountRanges)) {
+      LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+      PciEntry.PciEntry = Entry->TokenPciEntry.PciEntry;
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Link Feature PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtFeatPciRegister}.
+ *
+ * Set a single field (that is, the register field is not in HT Host capability or a
+ * set of per link registers) in PCI config, based on HT link features and package type.
+ * This code is used for two cases: single link processors and multilink processors.
+ * For single link cases, the link will be tested for a match to the HT Features for the link.
+ * For multilink processors, the entry will match if @b any link is found which matches.
+ * For example, a setting can be applied based on coherent HT3 by matching coherent AND HT3.
+ *
+ * Make the core's PCI address.  Check the package type (currently more important to the single link case),
+ * and if matching, iterate through all links checking for an HT feature match until found or exhausted.
+ * If a match was found, pass the PCI entry data to the implementer for writing for the current core.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtFeaturePciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINTN                 LinkCount;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  UINT32                ProcessorPackageType;
+  BOOLEAN               IsMatch;
+  TABLE_ENTRY_DATA      PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->HtFeatPciEntry.PciEntry.Mask != 0) &&
+          ((Entry->HtFeatPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0));
+
+  HtHostFeats.HtHostValue = 0;
+  LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+  PciEntry.PciEntry = Entry->HtFeatPciEntry.PciEntry;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0);
+
+  ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+  if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->HtFeatPciEntry.PackageType.PackageTypeValue)) {
+    IsMatch = FALSE;
+    for (LinkCount = 0; LinkCount < 8; LinkCount++) {
+      if (FindHtHostCapability (LinkCount, &CapabilitySet, StdHeader)) {
+        FamilySpecificServices->GetHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader);
+        if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtFeatPciEntry.LinkFeats.HtHostValue)) {
+          IsMatch = TRUE;
+          break;
+        }
+      } else {
+        break;
+      }
+    }
+    if (IsMatch) {
+      // Do the PCI register update.
+      SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the HT Link PCI Register Entry.
+ *
+ * @TableEntryTypeMethod{::HtLinkPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * Registers are processed for match per link, assuming sequential PCI address per link.
+ * Read - Modify - Write each matching link's PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The PCI register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegisterForHtLinkPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINTN                 LinkCount;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  TABLE_ENTRY_DATA      PciEntry;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT ((Entry->HtLinkPciEntry.PciEntry.Mask != 0) &&
+          ((Entry->HtLinkPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0));
+
+  HtHostFeats.HtHostValue = 0;
+  LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
+  PciEntry.PciEntry = Entry->HtLinkPciEntry.PciEntry;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  LinkCount = 0;
+  while (LinkCount < 8) {
+    if (FindHtHostCapability (LinkCount, &CapabilitySet, StdHeader)) {
+      FamilySpecificServices->GetHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader);
+      if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtLinkPciEntry.LinkFeats.HtHostValue)) {
+        // Do the update to the link's non-Host PCI register, based on the entry address.
+        PciEntry.PciEntry.Address = Entry->HtLinkPciEntry.PciEntry.Address;
+        PciEntry.PciEntry.Address.Address.Register = PciEntry.PciEntry.Address.Address.Register + ((UINT32)Link * 4);
+        SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
+      }
+    } else {
+      // No more Capabilities.  Switch to sublink 1's if we are just done with sublink 0's.
+      // (This case handles less than 4 links are implemented in the processor.)
+      if (CapabilitySet.Address.Function == 0) {
+        CapabilitySet.Address.Function = 4;
+        LinkCount = 3;
+      } else {
+        break;
+      }
+    }
+    LinkCount ++;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ * Returns the platform features list of the currently running processor core.
+ *
+ * @param[out]      Features          The Features supported by this platform
+ * @param[in]       PlatformConfig    Config handle for platform specific information
+ * @param[in]       StdHeader         Header for library and services
+ *
+ */
+VOID
+GetPlatformFeatures (
+     OUT   PLATFORM_FEATS         *Features,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    CapabilityReg;
+  UINT32     Link;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  UINT32     CoreCount;
+
+  // Start with none.
+  Features->PlatformValue = 0;
+
+  switch (PlatformConfig->PlatformProfile.PlatformControlFlowMode) {
+  case Nfcm:
+    Features->PlatformFeatures.PlatformNfcm = 1;
+    break;
+  case UmaDr:
+    Features->PlatformFeatures.PlatformUma = 1;
+    break;
+  case UmaIfcm:
+    Features->PlatformFeatures.PlatformUmaIfcm = 1;
+    break;
+  case Ifcm:
+    Features->PlatformFeatures.PlatformIfcm = 1;
+    break;
+  case Iommu:
+    Features->PlatformFeatures.PlatformIommu = 1;
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  // Check - Single Link?
+  // This is based on the implemented links on the package regardless of their
+  // connection status.  All processors must match the BSP, so we only check it and
+  // not the current node.  We don't care exactly how many links there are, as soon
+  // as we find more than one we are done.
+  Link = 0;
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0);
+  // Until either all capabilities are done or until the desired link is found,
+  // keep looking for HT Host Capabilities.
+  while (Link < 2) {
+    LibAmdPciFindNextCap (&PciAddress, StdHeader);
+    if (PciAddress.AddressValue != ILLEGAL_SBDFO) {
+      LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader);
+      if ((CapabilityReg & 0xE00000FF) == 0x20000008) {
+        Link++;
+      }
+      // A capability other than an HT capability, keep looking.
+    } else {
+      // end of capabilities
+      break;
+    }
+  }
+  if (Link < 2) {
+    Features->PlatformFeatures.PlatformSingleLink = 1;
+  } else {
+    Features->PlatformFeatures.PlatformMultiLink = 1;
+  }
+
+  // Set the legacy core count bits.
+  GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+  switch (CoreCount) {
+  case 1:
+    Features->PlatformFeatures.PlatformSingleCore = 1;
+    break;
+  case 2:
+    Features->PlatformFeatures.PlatformDualCore = 1;
+    break;
+  default:
+    Features->PlatformFeatures.PlatformMultiCore = 1;
+  }
+
+  //
+  // Get some specific platform type info, VC...etc.
+  //
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+  FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader);
+
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks if a register table entry applies to the executing core.
+ *
+ * This function uses a combination of logical ID and platform features to
+ * determine whether or not a register table entry applies to the executing core.
+ *
+ * @param[in]     CoreCpuRevision         The current core's logical ID
+ * @param[in]     EntryCpuRevision        The entry's desired logical IDs
+ * @param[in]     PlatformFeatures        The platform features
+ * @param[in]     EntryFeatures           The entry's desired platform features
+ *
+ * @retval        TRUE           This entry should be applied
+ * @retval        FALSE          This entry does not apply
+ *
+ */
+BOOLEAN
+STATIC
+DoesEntryMatchPlatform (
+  IN       CPU_LOGICAL_ID   CoreCpuRevision,
+  IN       CPU_LOGICAL_ID   EntryCpuRevision,
+  IN       PLATFORM_FEATS   PlatformFeatures,
+  IN       PLATFORM_FEATS   EntryFeatures
+  )
+{
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  if (((CoreCpuRevision.Family & EntryCpuRevision.Family) != 0) &&
+      ((CoreCpuRevision.Revision & EntryCpuRevision.Revision) != 0)) {
+    if (EntryFeatures.PlatformFeatures.AndPlatformFeats == 0) {
+      // Match if ANY entry feats match a platform feat (an OR test)
+      if ((EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue) != 0) {
+        Result = TRUE;
+      }
+    } else {
+      // Match if ALL entry feats match a platform feat (an AND test)
+      if ((EntryFeatures.PlatformValue & ~(AMD_PF_AND)) ==
+          (EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue)) {
+        Result = TRUE;
+      }
+    }
+  }
+
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks register table entry type specific criteria to the platform.
+ *
+ * Entry Data Type implementer methods can use this generically to check their own
+ * specific criteria.  The method collects the actual platform characteristics and
+ * provides them along with the table entry's criteria to this service.
+ *
+ * There are a couple considerations for any implementer method using this service.
+ * The criteria value has to be representable as a UINT32.  The MSB, Bit 31, has to
+ * be used as a AND test request if set in the entry.  (The platform value should never
+ * have that bit set.)
+ *
+ * @param[in]     PlatformTypeSpecificFeatures        The platform features
+ * @param[in]     EntryTypeFeatures                   The entry's desired platform features
+ *
+ * @retval        TRUE                                This entry should be applied
+ * @retval        FALSE                               This entry does not apply
+ *
+ */
+BOOLEAN
+DoesEntryTypeSpecificInfoMatch (
+  IN       UINT32   PlatformTypeSpecificFeatures,
+  IN       UINT32   EntryTypeFeatures
+  )
+{
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  if ((EntryTypeFeatures & BIT31) == 0) {
+    // Match if ANY entry feats match a platform feat (an OR test)
+    if ((EntryTypeFeatures & PlatformTypeSpecificFeatures) != 0) {
+      Result = TRUE;
+    }
+  } else {
+    // Match if ALL entry feats match a platform feat (an AND test)
+    if ((EntryTypeFeatures & ~(BIT31)) == (EntryTypeFeatures & PlatformTypeSpecificFeatures)) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determine this core's Selector matches.
+ *
+ * @param[in]  Selector    Is the current core this selector type?
+ * @param[in]  StdHeader   Config handle for library and services.
+ *
+ * @retval  TRUE           Yes, it is.
+ * @retval  FALSE          No, it is not.
+ */
+BOOLEAN
+STATIC
+IsCoreSelector (
+  IN       TABLE_CORE_SELECTOR       Selector,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  BOOLEAN Result;
+  AGESA_STATUS  CalledStatus;
+
+  Result = TRUE;
+  ASSERT (Selector < TableCoreSelectorMax);
+
+  if ((Selector == PrimaryCores) && !IsCurrentCorePrimary (StdHeader)) {
+    Result = FALSE;
+  }
+  if ((Selector == BSCCORE) && (!IsBsp (StdHeader, &CalledStatus))) {
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the registers for this core based on entries in a list of Register Tables.
+ *
+ * Determine the platform features and this core's logical id.  Get the specific table
+ * entry type implementations for the logical model, which may be either generic (the ones
+ * in this file) or specific.
+ *
+ * Scan the tables starting the with ones for all cores and progressively narrowing the selection
+ * based on this core's role (ex. primary core).  For a selected table, check for each entry
+ * matching the current core and platform, and call the implementer method to perform the
+ * register set operation if it matches.
+ *
+ * @param[in]  PlatformConfig    Config handle for platform specific information
+ * @param[in]  StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+SetRegistersFromTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPU_LOGICAL_ID         CpuLogicalId;
+  PLATFORM_FEATS         PlatformFeatures;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  TABLE_ENTRY_FIELDS    *Entries;
+  TABLE_CORE_SELECTOR    Selector;
+  TABLE_ENTRY_TYPE       EntryType;
+  REGISTER_TABLE       **TableHandle;
+  UINTN                  NumberOfEntries;
+  UINTN                  CurrentEntryCount;
+  TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer;
+  PF_DO_TABLE_ENTRY       DoTableEntry[TableEntryTypeMax];
+
+  // Did you really mean to increase the size of ALL table entries??!!
+  // While it is not necessarily a bug to increase the size of table entries:
+  //   - Is this warning a surprise?  Please fix it.
+  //   - If expected, is this really a feature which is worth the increase?  Then let other entries also use the space.
+  ASSERT (sizeof (TABLE_ENTRY_DATA) == (MAX_ENTRY_TYPE_ITEMS32 * sizeof (UINT32)));
+
+  PlatformFeatures.PlatformValue = 0;
+  GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+  GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, StdHeader);
+
+  // Build a non-sparse table of implementer methods, so we don't have to keep searching.
+  // It is a bug to not include a descriptor for a type that is in the table (but the
+  // descriptor can point to a non-assert stub).
+  // Also, it is not a bug to have no register table implementations, but it is a bug to have none and call this routine.
+  for (EntryType = MSRREGISTER; EntryType < TableEntryTypeMax; EntryType++) {
+    DoTableEntry[EntryType] = (PF_DO_TABLE_ENTRY)CommonAssert;
+  }
+  TypeImplementer = FamilySpecificServices->TableEntryTypeDescriptors;
+  ASSERT (TypeImplementer != NULL);
+  while (TypeImplementer->EntryType < TableEntryTypeMax) {
+    DoTableEntry[TypeImplementer->EntryType] = TypeImplementer->DoTableEntry;
+    TypeImplementer++;
+  }
+
+  for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) {
+    if (IsCoreSelector (Selector, StdHeader)) {
+      // If the current core is the selected type of core, work the table list for tables for that type of core.
+      TableHandle = NULL;
+      Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader);
+      while (Entries != NULL) {
+        for (CurrentEntryCount = 0; CurrentEntryCount < NumberOfEntries; CurrentEntryCount++, Entries++) {
+          if (DoesEntryMatchPlatform (CpuLogicalId, Entries->CpuRevision, PlatformFeatures, Entries->Features)) {
+            // The entry matches this config, Do It!
+            // Find the implementer for this entry type and pass the entry data to it.
+            ASSERT (Entries->EntryType < TableEntryTypeMax);
+            DoTableEntry[Entries->EntryType] (&Entries->Entry, PlatformConfig, StdHeader);
+          }
+        }
+        Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader);
+      }
+    } else {
+      // Once a selector does not match the current core, quit looking.
+      break;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the registers for this core based on entries in a list of Register Tables.
+ *
+ * This function acts as a wrapper for calling the SetRegistersFromTables
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+SetRegistersFromTablesAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader);
+  SetRegistersFromTables (&EarlyParams->PlatformConfig, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
new file mode 100755
index 0000000000..475272d65c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Table.h
@@ -0,0 +1,1174 @@
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains code to initialize the CPU MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_TABLE_H_
+#define _CPU_TABLE_H_
+
+#define MAX_ENTRY_TYPE_ITEMS32 6        // The maximum number of initializer items for UINT32 entry data types.
+
+/**
+ * @page regtableimpl Register Table Implementation Guide
+ *
+ * This register table implementation is modular and extensible, so that support code as
+ * well as table data can be family specific or built out if not needed, and new types
+ * of table entries can be added with low overhead.  Because many aspects are now generic,
+ * there can be common implementations for CPU revision and platform feature matching and for
+ * finding and iterating tables.
+ *
+ * @par Adding a new table entry type.
+ *
+ * To add a new table entry type follow these steps.
+ * <ul>
+ * <li>  Add a member to the enum TABLE_ENTRY_TYPE which is a descriptive name of the entry's purpose
+ *       or distinct characteristics.
+ *
+ * <li>  Create an entry data struct with the customized data needed.  For example, custom register designations,
+ *       data and mask sizes, or feature comparisons.  Name your struct by adding "_" and upper-casing the enum name
+ *       and adding "_TYPE_ENTRY_DATA" at the end.
+ *
+ * <li>  Add the entry data type as a member of the TABLE_ENTRY_DATA union.  Be aware of the size of your
+ *       entry data struct; all table entries in all tables will share any size increase you introduce!
+ *
+ * <li>  If your data entry contains any member types except for UINT32, you can't use the generic first union member
+ *       for the initializers that make up the actual tables (it's just UINT32's). The generic MSR entry is
+ *       an example. Follow the steps below:
+ *
+ *       <ul>
+ *       <li>  Make a union which has your entry data type as the first member.  Use TABLE_ENTRY_DATA as the
+ *             second member.  Name this with your register followed by "_DATA_INITIALIZER".
+ *
+ *       <li>  Make a copy of TABLE_ENTRY_FIELDS, and rename it your register "_TYPE_ENTRY_INITIALIZER".  Rename
+ *             the TABLE_ENTRY_DATA member of that struct to have the type you created in the previous step.
+ *             This type can be used to declare an array of entries and make a register table in some family specific
+ *             file.
+ *       </ul>
+ *
+ * <li>  Add the descriptor that will link table entries of your data type to an implementation for it.
+ *       <ul>
+ *       <li>  Find the options file which instantiates the CPU_SPECIFIC_SERVICES for each logical model that will
+ *             support the new entry type.
+ *
+ *       <li> From there find the instantiation of its TABLE_ENTRY_TYPE_DESCRIPTOR.  Add a descriptor to the
+ *            to the list for your new type.  Provide the name of a function which will implement the
+ *            entry data.  The function name should reflect that it implements the action for the entry type.
+ *            The function must be an instance of F_DO_TABLE_ENTRY.
+ *       </ul>
+ *
+ * <li>  Implement the function for your entry type data.  (If parts of it are family specific add methods to
+ *       CPU_SPECIFIC_SERVICES for that and implement them for each family or model required.)  @n
+ *       The definition of the function must conform to F_DO_TABLE_ENTRY.
+ *       In the function preamble, include a cross reference to the entry enum:
+ *       @code
+ *       *
+ *       * @TableEntryTypeMethod{::MyRegister}
+ *       *
+ *       @endcode
+ *
+ * </ul>
+ *
+ * @par  Adding a new Register Table
+ *
+ * To add a new register table for a logical CPU model follow the steps below.
+ *
+ * <ul>
+ * <li>  Find the options file which instantiates the CPU_SPECIFIC_SERVICES for the logical model that
+ *       should include the table.
+ *
+ * <li>  From there find the instantiation of its REGISTER_TABLE list. Add the name of the new register table.
+ * </ul>
+ *
+ */
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Define the supported table entries.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * These are the available types of table entries.
+ *
+ * Each type corresponds to:
+ * - a semantics for the type specific data, for example semantics for a Register value,
+ * Data value, and Mask value.
+ * - optionally, including a method for type specific matching criteria
+ * - a method for writing the desired update to the hardware.
+ *
+ * All types share in common a method to match CPU Family and Model and a method to match
+ * platform feature set.
+ *
+ */
+typedef enum {
+  MSRREGISTER,                 ///< Processor MSR registers.
+  PCIREGISTER,                 ///< Processor Config Space registers.
+  ErrataWorkaround,            ///< Processor Errata Workarounds which are @b not practical using the other types.
+  HtPhyRegister,               ///< Processor HT Phy registers.
+  HtPhyRangeRegister,          ///< Processor HT Phy range of contiguous registers (ex. 40h:48h).
+  DeemphasisRegister,          ///< Processor Deemphasis register (HT Phy special case).
+  HtPhyFreqRegister,           ///< Processor Frequency dependent HT Phy settings.
+  ProfileFixup,                ///< Processor Performance Profile fixups to PCI Config Registers.
+  HtHostPciRegister,           ///< Processor Ht Host capability registers (PCI Config).
+  HtTokenPciRegister,          ///< Processor Ht Link Token count registers.
+  CoreCountsPciRegister,       ///< Processor PCI Config Registers which depend on core counts.
+  ProcCountsPciRegister,       ///< Processor PCI Config Registers which depend on processor counts.
+  TokenPciRegister,            ///< Processor northbridge Token Count register which may be dependent on connectivity.
+  HtFeatPciRegister,           ///< Processor HT Link feature dependant PCI Config Registers.
+  HtPhyProfileRegister,        ///< Processor HT Phy registers which depend on performance features.
+  HtLinkPciRegister,           ///< Processor HT Link registers (one per link) not part of HT Host capability.
+  TableEntryTypeMax            ///< Not a valid entry type, use for limit checking.
+} TABLE_ENTRY_TYPE;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Useful types and defines: Selectors, Platform Features, and type specific features.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * Select tables for the current core.
+ *
+ * This allows more efficient register table processing, by allowing cores to skip
+ * redundantly setting PCI registers, for example.  This feature is not intended to
+ * be relied on for function:  it is valid to have a single register table with all settings
+ * processed by every core; it's just slower.
+ *
+ */
+typedef enum {
+  AllCores,                   ///< Select only tables which apply to all cores.
+  PrimaryCores,               ///< Select tables which apply to primary cores.
+  BSCCORE,                    ///< Select tables which apply to the boot core.
+  TableCoreSelectorMax        ///< Not a valid selector, use for limit checking.
+} TABLE_CORE_SELECTOR;
+
+// Initializer bit pattern values for platform features.
+// Keep in synch with the PLATFORM_FEATURES struct!
+
+// The 5 control flow modes.
+#define AMD_PF_NFCM           BIT0
+#define AMD_PF_UMA            BIT1    // UMA_DR
+#define AMD_PF_UMA_IFCM       BIT2
+#define AMD_PF_IFCM           BIT3
+#define AMD_PF_IOMMU          BIT4
+// Degree of HT connectivity possible.
+#define AMD_PF_SINGLE_LINK    BIT5
+#define AMD_PF_MULTI_LINK     BIT6
+// For some legacy MSRs, define a couple core count bits.  Do not continue adding
+// core counts to the platform feats, if you need more than this design a table entry type.
+// Here, provide exactly 1, exactly 2, or anything else.
+#define AMD_PF_SINGLE_CORE    BIT7
+#define AMD_PF_DUAL_CORE      BIT8
+#define AMD_PF_MULTI_CORE     BIT9
+
+// Not a platform type, but treat all others as AND
+#define AMD_PF_AND            BIT31
+
+#define AMD_PF_ALL    (AMD_PF_NFCM          | \
+                       AMD_PF_UMA           | \
+                       AMD_PF_UMA_IFCM      | \
+                       AMD_PF_IFCM          | \
+                       AMD_PF_IOMMU         | \
+                       AMD_PF_SINGLE_LINK   | \
+                       AMD_PF_MULTI_LINK    | \
+                       AMD_PF_SINGLE_CORE   | \
+                       AMD_PF_DUAL_CORE     | \
+                       AMD_PF_MULTI_CORE)
+// Do not include AMD_PF_AND in AMD_PF_ALL !
+
+/**
+ * The current platform features.
+ *
+ * Keep this in sync with defines above that are used in the initializers!
+ *
+ * The comments with the bit number are useful for the computing the reserved member size, but
+ * do not write code that assumes you know what bit number one of these members is.
+ *
+ * These platform features are standard for all logical families and models.
+ */
+typedef struct {
+  UINT32          PlatformNfcm:1;             ///< BIT_0 Normal Flow Control Mode.
+  UINT32          PlatformUma:1;              ///< BIT_1 UMA (Display Refresh) Flow Control.
+  UINT32          PlatformUmaIfcm:1;          ///< BIT_2 UMA using Isochronous Flow Control.
+  UINT32          PlatformIfcm:1;             ///< BIT_3 Isochronous Flow Control Mode (not UMA).
+  UINT32          PlatformIommu:1;            ///< BIT_4 IOMMU (a special case Isochronous mode).
+  UINT32          PlatformSingleLink:1;       ///< BIT_5 The processor is in a package which implements only a single HT Link.
+  UINT32          PlatformMultiLink:1;        ///< BIT_6 The processor is in a package which implements more than one HT Link.
+  UINT32          PlatformSingleCore:1;       ///< BIT_7 Single Core processor, for legacy entries.
+  UINT32          PlatformDualCore:1;         ///< BIT_8 Dual Core processor, for legacy entries.
+  UINT32          PlatformMultiCore:1;        ///< BIT_9 More than dual Core processor, for legacy entries.
+  UINT32          :(30 - 9);                  ///< The possibilities are (not quite) endless.
+  UINT32          AndPlatformFeats:1;         ///< BIT_31
+} PLATFORM_FEATURES;
+
+/**
+ * Platform Features
+ */
+typedef union {
+  UINT32            PlatformValue;            ///< Describe Platform Features in UINT32.
+  ///< This one goes first, because then initializers use it automatically for the union.
+  PLATFORM_FEATURES PlatformFeatures;         ///< Describe Platform Features in structure
+} PLATFORM_FEATS;
+
+// Sublink Types are defined so they can match each attribute against either
+// sublink zero or one.  The table entry must contain the correct matching
+// values based on the register. This is available in the BKDG, for each register
+// which sublink it controls.  If the register is independent of sublink, OR values
+// together or use HT_LINKTYPE_ALL to match if either sublink matches (ex. E0 - E5).
+// Sublink 0 types, bits 0 thru 14
+#define HTPHY_LINKTYPE_SL0_HT3          BIT0
+#define HTPHY_LINKTYPE_SL0_HT1          BIT1
+#define HTPHY_LINKTYPE_SL0_COHERENT     BIT2
+#define HTPHY_LINKTYPE_SL0_NONCOHERENT  BIT3
+#define HTPHY_LINKTYPE_SL0_LINK0        BIT4
+#define HTPHY_LINKTYPE_SL0_LINK1        BIT5
+#define HTPHY_LINKTYPE_SL0_LINK2        BIT6
+#define HTPHY_LINKTYPE_SL0_LINK3        BIT7
+// bit 15 is reserved
+
+// SubLink 1 types, bits 16 thru 30
+#define HTPHY_LINKTYPE_SL1_HT3          BIT16
+#define HTPHY_LINKTYPE_SL1_HT1          BIT17
+#define HTPHY_LINKTYPE_SL1_COHERENT     BIT18
+#define HTPHY_LINKTYPE_SL1_NONCOHERENT  BIT19
+#define HTPHY_LINKTYPE_SL1_LINK4        BIT20
+#define HTPHY_LINKTYPE_SL1_LINK5        BIT21
+#define HTPHY_LINKTYPE_SL1_LINK6        BIT22
+#define HTPHY_LINKTYPE_SL1_LINK7        BIT23
+// bit 31 is reserved
+
+#define HTPHY_LINKTYPE_SL0_ALL          (HTPHY_LINKTYPE_SL0_HT3        | \
+                                         HTPHY_LINKTYPE_SL0_HT1        | \
+                                         HTPHY_LINKTYPE_SL0_COHERENT   | \
+                                         HTPHY_LINKTYPE_SL0_NONCOHERENT | \
+                                         HTPHY_LINKTYPE_SL0_LINK0       | \
+                                         HTPHY_LINKTYPE_SL0_LINK1       | \
+                                         HTPHY_LINKTYPE_SL0_LINK2       | \
+                                         HTPHY_LINKTYPE_SL0_LINK3)
+#define HTPHY_LINKTYPE_SL1_ALL          (HTPHY_LINKTYPE_SL1_HT3        | \
+                                         HTPHY_LINKTYPE_SL1_HT1        | \
+                                         HTPHY_LINKTYPE_SL1_COHERENT   | \
+                                         HTPHY_LINKTYPE_SL1_NONCOHERENT | \
+                                         HTPHY_LINKTYPE_SL1_LINK4       | \
+                                         HTPHY_LINKTYPE_SL1_LINK5       | \
+                                         HTPHY_LINKTYPE_SL1_LINK6       | \
+                                         HTPHY_LINKTYPE_SL1_LINK7)
+#define HTPHY_LINKTYPE_ALL              (HTPHY_LINKTYPE_SL0_ALL | HTPHY_LINKTYPE_SL1_ALL)
+
+#define HTPHY_REGISTER_MAX              0x0000FFFFul
+/**
+ * HT PHY Link Features
+ */
+typedef struct {
+  UINT32 HtPhySL0Ht3:1;                       ///< Ht Phy Sub-link 0 Ht3
+  UINT32 HtPhySL0Ht1:1;                       ///< Ht Phy Sub-link 0 Ht1
+  UINT32 HtPhySL0Coh:1;                       ///< Ht Phy Sub-link 0 Coherent
+  UINT32 HtPhySL0NonCoh:1;                    ///< Ht Phy Sub-link 0 NonCoherent
+  UINT32 HtPhySL0Link0:1;                     ///< Ht Phy Sub-link 0 specifically for node link 0.
+  UINT32 HtPhySL0Link1:1;                     ///< Ht Phy Sub-link 0 specifically for node link 1.
+  UINT32 HtPhySL0Link2:1;                     ///< Ht Phy Sub-link 0 specifically for node link 2.
+  UINT32 HtPhySL0Link3:1;                     ///< Ht Phy Sub-link 0 specifically for node link 3.
+  UINT32 :(15 - 7);                           ///< Ht Phy Sub-link 0 Pad
+  UINT32 HtPhySL1Ht3:1;                       ///< Ht Phy Sub-link 1 Ht3
+  UINT32 HtPhySL1Ht1:1;                       ///< Ht Phy Sub-link 1 Ht1
+  UINT32 HtPhySL1Coh:1;                       ///< Ht Phy Sub-link 1 Coherent
+  UINT32 HtPhySL1NonCoh:1;                    ///< Ht Phy Sub-link 1 NonCoherent
+  UINT32 HtPhySL0Link4:1;                     ///< Ht Phy Sub-link 1 specifically for node link 4.
+  UINT32 HtPhySL0Link5:1;                     ///< Ht Phy Sub-link 1 specifically for node link 5.
+  UINT32 HtPhySL0Link6:1;                     ///< Ht Phy Sub-link 1 specifically for node link 6.
+  UINT32 HtPhySL0Link7:1;                     ///< Ht Phy Sub-link 1 specifically for node link 7.
+  UINT32 :(31 - 23);                          ///< Ht Phy Sub-link 1 Pad
+} HT_PHY_LINK_FEATURES;
+
+/**
+ * Ht Phy Link Features
+ */
+typedef union {
+  UINT32                  HtPhyLinkValue;     ///< Describe HY Phy Features in UINT32.
+  ///< This one goes first, because then initializers use it automatically for the union.
+  HT_PHY_LINK_FEATURES    HtPhyLinkFeatures;  ///< Describe HT Phy Features in structure.
+} HT_PHY_LINK_FEATS;
+
+// DB Level for initializing Deemphasis
+// This must be in sync with DEEMPHASIS_FEATURES and PLATFORM_DEEMPHASIS_LEVEL (agesa.h)
+#define DEEMPHASIS_LEVEL_NONE   BIT0
+#define DEEMPHASIS_LEVEL__3     BIT1
+#define DEEMPHASIS_LEVEL__6     BIT2
+#define DEEMPHASIS_LEVEL__8     BIT3
+#define DEEMPHASIS_LEVEL__11    BIT4
+#define DEEMPHASIS_LEVEL__11_8  BIT5
+#define DCV_LEVEL_NONE          BIT16
+#define DCV_LEVEL__2            BIT17
+#define DCV_LEVEL__3            BIT18
+#define DCV_LEVEL__5            BIT19
+#define DCV_LEVEL__6            BIT20
+#define DCV_LEVEL__7            BIT21
+#define DCV_LEVEL__8            BIT22
+#define DCV_LEVEL__9            BIT23
+#define DCV_LEVEL__11           BIT24
+// Note that an "AND" feature doesn't make any sense, levels are mutually exclusive.
+
+// An error check value.
+#define VALID_DEEMPHASIS_LEVELS  (DEEMPHASIS_LEVEL_NONE    | \
+                                  DEEMPHASIS_LEVEL__3      | \
+                                  DEEMPHASIS_LEVEL__6      | \
+                                  DEEMPHASIS_LEVEL__8      | \
+                                  DEEMPHASIS_LEVEL__11     | \
+                                  DEEMPHASIS_LEVEL__11_8   | \
+                                  DCV_LEVEL_NONE           | \
+                                  DCV_LEVEL__2             | \
+                                  DCV_LEVEL__3             | \
+                                  DCV_LEVEL__5             | \
+                                  DCV_LEVEL__6             | \
+                                  DCV_LEVEL__7             | \
+                                  DCV_LEVEL__8             | \
+                                  DCV_LEVEL__9             | \
+                                  DCV_LEVEL__11)
+
+/**
+ * Deemphasis Ht Phy Link Deemphasis.
+ *
+ * This must be in sync with defines above and ::PLATFORM_DEEMPHASIS_LEVEL (agesa.h)
+ */
+typedef struct {
+  UINT32          DeemphasisLevelNone:1;         ///< The deemphasis level None.
+  UINT32          DeemphasisLevelMinus3:1;       ///< The deemphasis level minus 3 db.
+  UINT32          DeemphasisLevelMinus6:1;       ///< The deemphasis level minus 6 db.
+  UINT32          DeemphasisLevelMinus8:1;       ///< The deemphasis level minus 8 db.
+  UINT32          DeemphasisLevelMinus11:1;      ///< The deemphasis level minus 11 db.
+  UINT32          DeemphasisLevelMinus11w8:1;    ///< The deemphasis level minus 11 db, minus 8 precursor.
+  UINT32          :(15 - 5);                     ///< reserved.
+  UINT32          DcvLevelNone:1;                ///< The level for DCV None.
+  UINT32          DcvLevelMinus2:1;              ///< The level for DCV minus 2 db.
+  UINT32          DcvLevelMinus3:1;              ///< The level for DCV minus 3 db.
+  UINT32          DcvLevelMinus5:1;              ///< The level for DCV minus 5 db.
+  UINT32          DcvLevelMinus6:1;              ///< The level for DCV minus 6 db.
+  UINT32          DcvLevelMinus7:1;              ///< The level for DCV minus 7 db.
+  UINT32          DcvLevelMinus8:1;              ///< The level for DCV minus 8 db.
+  UINT32          DcvLevelMinus9:1;              ///< The level for DCV minus 9 db.
+  UINT32          DcvLevelMinus11:1;             ///< The level for DCV minus 11 db.
+  UINT32          :(15 - 8);                     ///< reserved.
+} DEEMPHASIS_FEATURES;
+
+/**
+ * Deemphasis Ht Phy Link Features.
+ */
+typedef union {
+  UINT32                  DeemphasisValues;      ///< Initialize HT Deemphasis in UINT32.
+  DEEMPHASIS_FEATURES     DeemphasisLevels;      ///< HT Deemphasis levels.
+} DEEMPHASIS_FEATS;
+
+// Initializer bit patterns for PERFORMANCE_PROFILE_FEATS.
+#define PERFORMANCE_REFRESH_REQUEST_32B       BIT0
+#define PERFORMANCE_PROBEFILTER               BIT1
+#define PERFORMANCE_L3_CACHE                  BIT2
+#define PERFORMANCE_NO_L3_CACHE               BIT3
+#define PERFORMANCE_MCT_ISOC_VARIABLE         BIT4
+#define PERFORMANCE_IS_WARM_RESET             BIT5
+#define PERFORMANCE_VRM_HIGH_SPEED_ENABLE     BIT6
+#define PERFORMANCE_NB_PSTATES_ENABLE         BIT7
+#define PERFORMANCE_AND                       BIT31
+
+#define PERFORMANCE_PROFILE_ALL   (PERFORMANCE_REFRESH_REQUEST_32B | \
+                                   PERFORMANCE_PROBEFILTER         | \
+                                   PERFORMANCE_L3_CACHE            | \
+                                   PERFORMANCE_NO_L3_CACHE         | \
+                                   PERFORMANCE_MCT_ISOC_VARIABLE   | \
+                                   PERFORMANCE_IS_WARM_RESET       | \
+                                   PERFORMANCE_VRM_HIGH_SPEED_ENABLE | \
+                                   PERFORMANCE_NB_PSTATES_ENABLE)
+
+/**
+ * Performance Profile specific Type Features.
+ *
+ * Register settings for the different control flow modes can have additional dependencies
+ */
+typedef struct {
+  UINT32       RefreshRequest32Byte:1;         ///< BIT_0.   Display Refresh Requests use 32 bytes (32BE).
+  UINT32       ProbeFilter:1;                  ///< BIT_1    Probe Filter will be enabled.
+  UINT32       L3Cache:1;                      ///< BIT_2    L3 Cache is present.
+  UINT32       NoL3Cache:1;                    ///< BIT_3    L3 Cache is NOT present.
+  UINT32       MctIsocVariable:1;              ///< BIT_4    Mct Isoc Read Priority set to variable.
+  UINT32       IsWarmReset:1;                  ///< BIT_5    This boot is on a warm reset, cold reset pass is already completed.
+  UINT32       VrmHighSpeed:1;                 ///< BIT_6    Select high speed VRM.
+  UINT32       NbPstates:1;                    ///< BIT_7    Northbridge PStates are enabled
+  UINT32       :(30 - 7);                      ///< available for future expansion.
+  UINT32       AndPerformanceFeats:1;          ///< BIT_31.  AND other selected features.
+} PERFORMANCE_PROFILE_FEATURES;
+
+/**
+ * Performance Profile features.
+ */
+typedef union {
+  UINT32                        PerformanceProfileValue;     ///< Initializer value.
+  PERFORMANCE_PROFILE_FEATURES  PerformanceProfileFeatures;  ///< The performance profile features.
+} PERFORMANCE_PROFILE_FEATS;
+
+/**
+ * Package Type Features
+ *
+ */
+typedef struct {
+  UINT32        PkgType0:1;                 ///< Package Type 0
+  UINT32        PkgType1:1;                 ///< Package Type 1
+  UINT32        PkgType2:1;                 ///< Package Type 2
+  UINT32        PkgType3:1;                 ///< Package Type 3
+  UINT32        PkgType4:1;                 ///< Package Type 4
+  UINT32        PkgType5:1;                 ///< Package Type 5
+  UINT32        PkgType6:1;                 ///< Package Type 6
+  UINT32        PkgType7:1;                 ///< Package Type 7
+  UINT32        PkgType8:1;                 ///< Package Type 8
+  UINT32        PkgType9:1;                 ///< Package Type 9
+  UINT32        PkgType10:1;                ///< Package Type 10
+  UINT32        PkgType11:1;                ///< Package Type 11
+  UINT32        PkgType12:1;                ///< Package Type 12
+  UINT32        PkgType13:1;                ///< Package Type 13
+  UINT32        PkgType14:1;                ///< Package Type 14
+  UINT32        PkgType15:1;                ///< Package Type 15
+  UINT32        Reserved:15;                ///< Package Type Reserved
+  UINT32        ReservedAndFeats:1;         ///< BIT_31.  AND other selected features. Always zero here.
+} PACKAGE_TYPE_FEATURES;
+
+// Initializer Values for Package Type
+#define PACKAGE_TYPE_ALL              0XFFFF       ///< Package Type apply all packages
+
+// Initializer Values for Ht Host Pci Config Registers
+#define HT_HOST_FEAT_COHERENT          BIT0
+#define HT_HOST_FEAT_NONCOHERENT       BIT1
+#define HT_HOST_FEAT_GANGED            BIT2
+#define HT_HOST_FEAT_UNGANGED          BIT3
+#define HT_HOST_FEAT_HT3               BIT4
+#define HT_HOST_FEAT_HT1               BIT5
+#define HT_HOST_AND                    BIT31
+
+#define HT_HOST_FEATURES_ALL    (HT_HOST_FEAT_COHERENT    | \
+                                 HT_HOST_FEAT_NONCOHERENT | \
+                                 HT_HOST_FEAT_GANGED      | \
+                                 HT_HOST_FEAT_UNGANGED    | \
+                                 HT_HOST_FEAT_HT3         | \
+                                 HT_HOST_FEAT_HT1)
+
+/**
+ * HT Host PCI register features.
+ *
+ * Links which are not connected do not match any of these features.
+ */
+typedef struct {
+  UINT32       Coherent:1;                 ///< BIT_0 Apply to links with a coherent connection.
+  UINT32       NonCoherent:1;              ///< BIT_1 Apply to links with a non-coherent connection.
+  UINT32       Ganged:1;                   ///< BIT_2 Apply to links with a ganged connection.
+  UINT32       UnGanged:1;                 ///< BIT_3 Apply to links with a unganged connection.
+  UINT32       Ht3:1;                      ///< BIT_4 Apply to links with HT3 frequency (> 1000 MHz)
+  UINT32       Ht1:1;                      ///< BIT_5 Apply to links with HT1 frequency (< 1200 MHz)
+  UINT32       :(30 - 5);                  ///< Future expansion.
+  UINT32       AndHtHostFeats:1;           ///< BIT_31.  AND other selected features.
+} HT_HOST_FEATURES;
+
+/**
+ * HT Host features for table data.
+ */
+typedef union {
+  UINT32                 HtHostValue;                ///< Initializer value.
+  HT_HOST_FEATURES       HtHostFeatures;             ///< The HT Host Features.
+} HT_HOST_FEATS;
+
+// Core Range Initializer values.
+#define COUNT_RANGE_LOW            0ul
+#define COUNT_RANGE_HIGH           0xFFul
+
+// A count range matching none is often useful as the second range, matching will then be
+// based on the first range.  A count range all is provided as a first range for default settings.
+#define COUNT_RANGE_NONE           ((((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) << 16)
+#define COUNT_RANGE_ALL            (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_LOW))
+
+#define CORE_RANGE_0(min, max)            ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define CORE_RANGE_1(min, max)            (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define PROCESSOR_RANGE_0(min, max)       ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define PROCESSOR_RANGE_1(min, max)       (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define DEGREE_RANGE_0(min, max)          ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define DEGREE_RANGE_1(min, max)          (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+#define FREQ_RANGE_0(min, max)          ((((UINT32)(max)) << 8) | (UINT32)(min))
+#define FREQ_RANGE_1(min, max)          (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
+
+/**
+ * Count Range Feature, two count ranges for core counts, processor counts, or node counts.
+ */
+typedef struct {
+  UINT32       Range0Min:8;           ///< The minimum of the first count range.
+  UINT32       Range0Max:8;           ///< The maximum of the first count range.
+  UINT32       Range1Min:8;           ///< The minimum of the second count range.
+  UINT32       Range1Max:8;           ///< The maximum of the second count range.
+} COUNT_RANGE_FEATURE;
+
+/**
+ * Core Count Ranges for table data.
+ *
+ * Provide a pair of core count ranges. If the actual core count is included in either range (OR),
+ * the feature should be considered a match.
+ */
+typedef union {
+  UINT32       CoreRangeValue;          ///< Initializer value.
+  COUNT_RANGE_FEATURE CoreRanges;       ///< The Core Counts.
+} CORE_COUNT_RANGES;
+
+/**
+ * Processor count ranges for table data.
+ *
+ * Provide a pair of processor count ranges.  If the actual counts are included in either range (OR),
+ * the feature should be considered a match.
+ */
+typedef union {
+  UINT32       ProcessorCountRangeValue;             ///< Initializer value.
+  COUNT_RANGE_FEATURE ProcessorCountRanges;          ///< The Processor and Node Counts.
+} PROCESSOR_COUNTS;
+
+/**
+ * Connectivity count ranges for table data.
+ *
+ * Provide a processor count range and a system degree range.  The degree of a system is
+ * the maximum degree of any node.  The degree of a node is the number of nodes to which
+ * it is directly connected (not considering width or redundant links). If both the actual
+ * counts are included in each range (AND), the feature should be considered a match.
+ */
+typedef union {
+  UINT32       ConnectivityCountRangeValue;             ///< Initializer value.
+  COUNT_RANGE_FEATURE ConnectivityCountRanges;          ///< The Processor and Degree Counts.
+} CONNECTIVITY_COUNT;
+
+/**
+ * HT Frequency Count Range.
+ *
+ * Provide a pair of Frequency count ranges, with the frequency encoded as an HT Frequency value
+ * (such as would be programmed into the HT Host Link Frequency register).  By converting a NB freq,
+ * the same count can be applied for it.  If the actual value is included in either range
+ */
+typedef union {
+  UINT32       HtFreqCountRangeValue;                  ///< Initializer value.
+  COUNT_RANGE_FEATURE HtFreqCountRanges;               ///< The HT Freq counts.
+} HT_FREQ_COUNTS;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * The specific data for each table entry.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ *  Make an extra type so we can use compilers that don't support designated initializers.
+ *
+ *  All the entry type unions are no more than 5 UINT32's in size.  For entry types which are a struct of UINT32's,
+ *  this type can be used so that initializers can be declared TABLE_ENTRY_FIELDS, instead of a special non-union type.
+ *  A non-union type then has to be cast back to TABLE_ENTRY_FIELDS in order to process the table, and you can't mix
+ *  entry types with non-union initializers in the same table with any other type.
+ *
+ *  If the entry type contains anything but UINT32's, then it must have a non-union initializer type for creating the
+ *  actual tables.  For example, MSR entry has UINT64 and workaround entry has a function pointer.
+ */
+typedef UINT32 GENERIC_TYPE_ENTRY_INITIALIZER[MAX_ENTRY_TYPE_ITEMS32];
+
+/**
+ * Table Entry Data for MSR Registers.
+ *
+ * Apply data to register after mask, for MSRs.
+ */
+typedef struct {
+  UINT32  Address;                    ///< MSR address
+  UINT64  Data;                       ///< Data to set in the MSR
+  UINT64  Mask;                       ///< Mask to be applied to the MSR. Set every bit of all updated fields.
+} MSR_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for PCI Registers.
+ *
+ * Apply data to register after mask, for PCI Config registers.
+ */
+typedef struct {
+  PCI_ADDR  Address;                  ///< Address should contain Function, Offset only.  It will apply to all CPUs
+  UINT32    Data;                     ///< Data to be written into PCI device
+  UINT32    Mask;                     ///< Mask to be used before data write. Set every bit of all updated fields.
+} PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Registers.
+ *
+ * Apply data to register after mask, for HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  HT_PHY_LINK_FEATS TypeFeats;        ///< HT Phy Link Features
+  UINT32            Address;          ///< Address of Ht Phy Register
+  UINT32            Data;             ///< Data to be written into PCI device
+  UINT32            Mask;             ///< Mask to be used before data write.  Set every bit of all updated fields.
+} HT_PHY_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Register Ranges.
+ *
+ * Apply data to register after mask, for a range of HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  HT_PHY_LINK_FEATS TypeFeats;        ///< HT Phy Link Features
+  UINT32            LowAddress;       ///< Low address of Ht Phy Register range.
+  UINT32            HighAddress;      ///< High address of register range.
+  UINT32            Data;             ///< Data to be written into PCI device.
+  UINT32            Mask;             ///< Mask to be used before data write.  Set every bit of all updated fields.
+} HT_PHY_RANGE_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Deemphasis Registers.
+ *
+ * Apply data to register after mask, for HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  DEEMPHASIS_FEATS        Levels;       ///< The DCV and Deemphasis levels to match
+  HT_PHY_TYPE_ENTRY_DATA  HtPhyEntry;   ///< The HT Phy Entry to set the deemphasis values
+} DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Date for HT Phy Frequency Count Register updates.
+ *
+ * Compare the NB freq to a range, the HT freq to a range, the link features.
+ * Apply data to register after mask, if all three matched.
+ */
+typedef struct {
+  HT_FREQ_COUNTS       HtFreqCounts;      ///< Specify the HT Frequency range.
+  HT_FREQ_COUNTS       NbFreqCounts;      ///< Specify the NB Frequency range.
+  HT_PHY_TYPE_ENTRY_DATA HtPhyEntry;      ///< The HT Phy register update to perform.
+} HT_PHY_FREQ_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for Profile Fixup Registers.
+ *
+ * If TypeFeats matches current config, apply data to register after mask for PCI Config registers.
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
+  PCI_TYPE_ENTRY_DATA PciEntry;        ///< The PCI Register entry data.
+} PROFILE_FIXUP_TYPE_ENTRY_DATA;
+
+/**
+ * A variation of PCI register for the HT Host registers.
+ *
+ * A setting to the HT Host buffer counts needs to be made to all the registers for
+ * all the links.  There are also link specific criteria to check.
+ */
+typedef struct {
+  HT_HOST_FEATS     TypeFeats;        ///< Link Features.
+  PCI_ADDR          Address;          ///< Address of PCI Register to Fixed Up.
+  UINT32            Data;             ///< Data to be written into PCI device
+  UINT32            Mask;             ///< Mask to be used before data write.  Set every bit of all updated fields.
+} HT_HOST_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * A variation of HT Host PCI register for the Link Token registers.
+ *
+ * Use Link Features, Performance Fixup features, and processor counts to match entries.
+ * Link Features are iterated through the connected links.  All the matching Link Token count
+ * registers are updated.
+ */
+typedef struct {
+  PROCESSOR_COUNTS            ProcessorCounts;     ///< Specify a processor count range.
+  PERFORMANCE_PROFILE_FEATS   PerformanceFeats;    ///< Performance Profile features.
+  HT_HOST_FEATS               LinkFeats;           ///< Link Features.
+  UINT32                      Data;                ///< Data to be written into PCI device
+  UINT32                      Mask;                ///< Mask to be used before data write. Set every bit of all updated fields.
+} HT_TOKEN_PCI_REGISTER;
+
+/**
+ * Core Count dependent PCI registers.
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
+  CORE_COUNT_RANGES CoreCounts;        ///< Specify up to two core count ranges to match.
+  PCI_TYPE_ENTRY_DATA PciEntry;        ///< The PCI Register entry data.
+} CORE_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Processor Count dependent PCI registers.
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
+  PROCESSOR_COUNTS  ProcessorCounts;   ///< Specify a processor count range.
+  PCI_TYPE_ENTRY_DATA PciEntry;        ///< The PCI Register entry data.
+} PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * System connectivity dependent PCI registers.
+ *
+ * The topology specific recommended settings are based on the different connectivity of nodes
+ * in each configuration:  the more connections, the fewer resources each connection gets.
+ * The connectivity criteria translate as:
+ * - 2 Socket, half populated  ==   Degree 1
+ * - 4 Socket, half populated   ==  Degree 2
+ * - 2 Socket, fully populated  ==  Degree 3
+ * - 4 Socket, fully populated  ==  Degree > 3.  (4 or 5 if 3P, 6 if 4P)
+ *
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS TypeFeats;     ///< Profile Fixup Features.
+  CONNECTIVITY_COUNT  ConnectivityCount;   ///< Specify a system degree range.
+  PCI_TYPE_ENTRY_DATA PciEntry;            ///< The PCI Register entry data.
+} CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * An Errata Workaround method.
+ *
+ * \@TableTypeErrataInstances.
+ *
+ * When called, the entry's CPU Logical ID and Platform Features matched the current config.
+ * The method must implement any specific criteria checking for the workaround.
+ *
+ * See if you can use the other entries or make an entry specifically for the fix.
+ * After all, the purpose of having a table entry is to @b NOT have code which
+ * isn't generic feature code, but is family/model specific.
+ *
+ * @param[in]     Data       The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]     StdHeader  Config params for library, services.
+ */
+typedef VOID F_ERRATA_WORKAROUND (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/// Reference to a method.
+typedef F_ERRATA_WORKAROUND *PF_ERRATA_WORKAROUND;
+
+/**
+ * Table Entry Data for Errata Workarounds.
+ *
+ * See if you can use the other entries or make an entry specifically for the fix.
+ * After all, the purpose of having a table entry is to @b NOT have code which
+ * isn't generic feature code, but is family/model specific.
+ *
+ * Call DoAction passing Data.
+ */
+typedef struct {
+  PF_ERRATA_WORKAROUND  DoAction;       ///< A function implementing the workaround.
+  UINT32                Data;           ///< This data is passed to DoAction().
+} ERRATA_WORKAROUND_TYPE_ENTRY_DATA;
+
+/**
+ * Package Type Features
+ *
+ * FamilyPackageType are various among CPU families.
+ *
+ */
+typedef union {
+  UINT32                      PackageTypeValue;    ///< Package Type
+  PACKAGE_TYPE_FEATURES       FamilyPackageType;   ///< Package Type of CPU family
+} PACKAGE_TYPE_FEATS;
+
+/**
+ * HT Features dependent Global PCI registers.
+ *
+ */
+typedef struct {
+  HT_HOST_FEATS               LinkFeats;           ///< Link Features.
+  PACKAGE_TYPE_FEATS          PackageType;         ///< Package Type
+  PCI_TYPE_ENTRY_DATA         PciEntry;            ///< The PCI Register entry data.
+} HT_FEATURES_PCI_TYPE_ENTRY_DATA;
+
+/**
+ * Table Entry Data for HT Phy Registers which depend on performance profile features.
+ *
+ * Match performance profile features and link features.
+ * Apply data to register after mask, for HT Phy registers, repeated for all active links.
+ */
+typedef struct {
+  PERFORMANCE_PROFILE_FEATS  TypeFeats;            ///< Profile Fixup Features.
+  HT_PHY_TYPE_ENTRY_DATA     HtPhyEntry;           ///< The HT Phy Entry to set the deemphasis values
+} PROFILE_HT_PHY_TYPE_ENTRY_DATA;
+
+/**
+ * HT Link PCI registers that are not in the HT Host capability.
+ *
+ * Some HT Link registers have an instance per link, but are just sequential.  Specify the base register
+ * in the table register address (link 0 sublink 0).
+ */
+typedef struct {
+  HT_HOST_FEATS               LinkFeats;           ///< Link Features.
+  PCI_TYPE_ENTRY_DATA         PciEntry;            ///< The PCI Register entry data.
+} HT_LINK_PCI_TYPE_ENTRY_DATA;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * A complete register table and table entries.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * All the available entry data types.
+ */
+typedef union {
+  GENERIC_TYPE_ENTRY_INITIALIZER      InitialValues;     ///< Not a valid entry type; as the first union item,
+                                                         ///< it can be used with initializers.
+  MSR_TYPE_ENTRY_DATA                 MsrEntry;          ///< Msr entry.
+  PCI_TYPE_ENTRY_DATA                 PciEntry;          ///< PCI entry.
+  ERRATA_WORKAROUND_TYPE_ENTRY_DATA   ErrataEntry;       ///< Errata Workaround entry.
+  HT_PHY_TYPE_ENTRY_DATA              HtPhyEntry;        ///< HT Phy entry.
+  HT_PHY_RANGE_TYPE_ENTRY_DATA        HtPhyRangeEntry;   ///< A range of Ht Phy Registers
+  DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA   DeemphasisEntry;   ///< A HT Deemphasis level's settings.
+  HT_PHY_FREQ_TYPE_ENTRY_DATA         HtPhyFreqEntry;    ///< A frequency dependent Ht Phy Register setting.
+  PROFILE_FIXUP_TYPE_ENTRY_DATA       FixupEntry;        ///< Profile Fixup entry.
+  HT_HOST_PCI_TYPE_ENTRY_DATA         HtHostEntry;       ///< HT Host PCI entry.
+  HT_TOKEN_PCI_REGISTER               HtTokenEntry;      ///< HT Link Token Count entry.
+  CORE_COUNTS_PCI_TYPE_ENTRY_DATA     CoreCountEntry;    ///< Core count dependent settings.
+  PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA ProcCountEntry;   ///< Processor count entry.
+  CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA TokenPciEntry; ///< System connectivity dependent Token register.
+  HT_FEATURES_PCI_TYPE_ENTRY_DATA     HtFeatPciEntry;    ///< HT Features PCI entry.
+  PROFILE_HT_PHY_TYPE_ENTRY_DATA      HtPhyProfileEntry; ///< Performance dependent HT Phy register.
+  HT_LINK_PCI_TYPE_ENTRY_DATA         HtLinkPciEntry;    ///< Per Link, non HT Host, PCI registers.
+} TABLE_ENTRY_DATA;
+
+/**
+ * Register Table Entry common fields.
+ *
+ * All the various types of register table entries are subclasses of this object.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       EntryType;                  ///< The type of table entry this is.
+  CPU_LOGICAL_ID         CpuRevision;                ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS         Features;                   ///< Common Platform Features match criteria.
+  TABLE_ENTRY_DATA       Entry;                      ///< The type dependent entry data (ex. register, data, mask).
+} TABLE_ENTRY_FIELDS;
+
+/**
+ * An entire register table.
+ */
+typedef struct {
+  TABLE_CORE_SELECTOR  Selector;                     ///< For efficiency, these cores should process this table
+  UINTN                NumberOfEntries;              ///< The number of entries in the table.
+  CONST TABLE_ENTRY_FIELDS  *Table;                  ///< The table entries.
+} REGISTER_TABLE;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Describe implementers for table entries.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * Implement the semantics of a Table Entry Type.
+ *
+ * @TableEntryTypeInstances.
+ *
+ * @param[in]       CurrentEntry        The type specific entry data to be implemented (that is written).
+ * @param[in]       PlatformConfig      Config handle for platform specific information
+ * @param[in]       StdHeader           Config params for library, services.
+ */
+typedef VOID F_DO_TABLE_ENTRY (
+  IN       TABLE_ENTRY_DATA       *CurrentEntry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a method
+typedef F_DO_TABLE_ENTRY *PF_DO_TABLE_ENTRY;
+
+/**
+ * Describe the attributes of a Table Entry Type.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       EntryType;                  ///< The type of table entry this describes.
+  PF_DO_TABLE_ENTRY      DoTableEntry;               ///< Provide all semantics associated with TABLE_ENTRY_DATA
+} TABLE_ENTRY_TYPE_DESCRIPTOR;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Non-union initializers for entry data which is not just UINT32.
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * A union of data types, that can be initialized with MSR data.
+ *
+ * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
+ */
+typedef union {
+  MSR_TYPE_ENTRY_DATA    MsrInitializer;            ///< The data in the table initializer is assigned to this member.
+  TABLE_ENTRY_DATA       Reserved;                  ///< Make sure the size is the same as the real union.
+} MSR_DATA_INITIALIZER;
+
+/**
+ * A type suitable for an initializer for MSR Table entries.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       Type;                       ///< The type of table entry this is.
+  CPU_LOGICAL_ID         CpuRevision;                ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS         Features;                   ///< Common Platform Features match criteria.
+  MSR_DATA_INITIALIZER    EntryData;                 ///< The special union which accepts msr data initializer.
+} MSR_TYPE_ENTRY_INITIALIZER;
+
+/**
+ * A union of data types, that can be initialized with Errata Workaround data.
+ *
+ * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
+ */
+typedef union {
+  ERRATA_WORKAROUND_TYPE_ENTRY_DATA    ErrataInitializer; ///< The data in the table initializer is assigned to this member.
+  TABLE_ENTRY_DATA       Reserved;                        ///< Make sure the size is the same as the real union.
+} ERRATA_WORKAROUND_DATA_INITIALIZER;
+
+/**
+ * A type suitable for an initializer for Errata Workaround Table entries.
+ */
+typedef struct {
+  TABLE_ENTRY_TYPE       Type;                       ///< The type of table entry this is.
+  CPU_LOGICAL_ID         CpuRevision;                ///< Common CPU Logical ID match criteria.
+  PLATFORM_FEATS         Features;                   ///< Common Platform Features match criteria.
+  ERRATA_WORKAROUND_DATA_INITIALIZER    EntryData;   ///< Special union accepts errata workaround data initializer.
+} ERRATA_WORKAROUND_TYPE_ENTRY_INITIALIZER;
+
+/*------------------------------------------------------------------------------------------*/
+/*
+ * Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
+ */
+/*------------------------------------------------------------------------------------------*/
+
+/**
+ * Set the registers for this core based on entries in a list of Register Tables.
+ */
+VOID SetRegistersFromTables (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Find the features of the running platform.
+ */
+VOID
+GetPlatformFeatures (
+     OUT   PLATFORM_FEATS    *Features,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Checks register table entry type specific criteria to the platform.
+ */
+BOOLEAN
+DoesEntryTypeSpecificInfoMatch (
+  IN       UINT32   PlatformTypeSpecificFeatures,
+  IN       UINT32   EntryTypeFeatures
+  );
+
+/**
+ * Perform the MSR Register Entry.
+ */
+VOID
+SetRegisterForMsrEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the PCI Register Entry.
+ */
+VOID
+SetRegisterForPciEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Performance Profile PCI Register Entry.
+ */
+VOID
+SetRegisterForPerformanceProfileEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the HT Host PCI Register Entry.
+ */
+VOID
+SetRegisterForHtHostEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Core Counts Performance PCI Register Entry.
+ */
+VOID
+SetRegisterForCoreCountsPerformanceEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Processor Counts PCI Register Entry.
+ */
+VOID
+SetRegisterForProcessorCountsEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Perform the Errata Workaround Register Entry.
+ */
+VOID
+SetRegisterForErrataWorkaroundEntry (
+  IN       TABLE_ENTRY_DATA      *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/**
+ * Program HT Phy PCI registers.
+ */
+VOID
+SetRegisterForHtPhyEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Program a range of HT Phy PCI registers.
+ */
+VOID
+SetRegisterForHtPhyRangeEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Program Deemphasis registers, for the platform specified levels.
+ */
+VOID
+SetRegisterForDeemphasisEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Program HT Phy PCI registers which have complex frequency dependencies.
+ */
+VOID
+SetRegisterForHtPhyFreqEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the Processor Token Counts PCI Register Entry.
+ */
+VOID
+SetRegisterForTokenPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the HT Link Feature PCI Register Entry.
+ */
+VOID
+SetRegisterForHtFeaturePciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the HT Phy Performance Profile Register Entry.
+ */
+VOID
+SetRegisterForHtPhyProfileEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Perform the HT Link PCI Register Entry.
+ */
+VOID
+SetRegisterForHtLinkPciEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * Compare counts to a pair of ranges.
+ */
+BOOLEAN
+IsEitherCountInRange (
+  IN       UINTN                FirstCount,
+  IN       UINTN                SecondCount,
+  IN       COUNT_RANGE_FEATURE  Ranges
+  );
+
+/**
+ * Returns the performance profile features list of the currently running processor core.
+ */
+VOID
+GetPerformanceFeatures (
+     OUT   PERFORMANCE_PROFILE_FEATS    *Features,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+/**
+ * Finds the HT link capability set for a particular node/link.
+ */
+BOOLEAN
+FindHtHostCapability (
+  IN       UINTN              Link,
+  IN OUT   PCI_ADDR           *CapabilitySet,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#endif  // _CPU_TABLE_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
new file mode 100755
index 0000000000..0b796c8510
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
@@ -0,0 +1,319 @@
+;/**
+; * @file
+; *
+; * Agesa pre-memory miscellaneous support, including ap halt loop.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    INCLUDE agesa.inc
+    INCLUDE cpcarmac.inc
+    .LIST
+
+    .586P
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   A B S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .MODEL flat
+    .CODE
+;======================================================================
+; ExecuteFinalHltInstruction:  Disables the stack and performs
+;                              a hlt instruction on an AP.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       eax, ebx, ecx, edx, esp
+;
+;======================================================================
+ExecuteFinalHltInstruction PROC NEAR C PUBLIC
+
+  pop esi   ; StdHeader
+  pop esi   ; pointer to ApMtrrSettingsList, set through build configuration
+
+  mov     eax, CR0                 ; Make sure cache is disabled for all APs
+  or      eax, CR0_CD OR CR0_NW    ; Disable cache
+  mov     cr0, eax                 ; Write back to CR0
+
+  ; Configure the MTRRs on the AP so
+  ; when it runs remote code it will execute
+  ; out of RAM instead of ROM.
+
+  ; Disable MTRRs and turn on modification enable bit
+  mov ecx, MTRR_SYS_CFG
+  _RDMSR
+  btr eax, MtrrVarDramEn    ; Disable
+  bts eax, MtrrFixDramModEn ; Enable
+  btr eax, MtrrFixDramEn    ; Disable
+  bts eax, SysUcLockEn
+  _WRMSR
+
+  ; Setup default values for Fixed-Sized MTRRs
+  ; Set 7FFFh-00000h as WB
+  mov ecx, AMD_AP_MTRR_FIX64k_00000
+  mov eax, 1E1E1E1Eh
+  mov edx, eax
+  _WRMSR
+
+  ; Set 9FFFFh-80000h also as WB
+  mov ecx, AMD_AP_MTRR_FIX16k_80000
+  _WRMSR
+
+  ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
+  mov ecx, AMD_AP_MTRR_FIX16k_A0000
+  xor eax, eax
+  xor edx, edx
+  _WRMSR
+
+  ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
+  xor eax, eax
+  xor edx, edx
+  mov ecx, AMD_AP_MTRR_FIX4k_C0000
+
+CDLoop:
+  _WRMSR
+  inc ecx
+  cmp ecx, AMD_AP_MTRR_FIX4k_D8000
+  jbe CDLoop
+
+  ; Set FFFFFh-E0000h as Uncacheable Memory
+  mov eax, 18181818h
+  mov edx, eax
+
+  mov ecx, AMD_AP_MTRR_FIX4k_E0000
+
+EFLoop:
+  _WRMSR
+  inc ecx
+  cmp ecx, AMD_AP_MTRR_FIX4k_F8000
+  jbe EFLoop
+
+  ; If IBV provided settings for Fixed-Sized MTRRs,
+  ; overwrite the default settings.
+  .if (esi != 0)
+    mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
+    ; While we are not at the end of the list
+    .while (ecx != CPU_LIST_TERMINAL)
+      ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
+      .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
+             (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
+        mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
+        mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
+        _WRMSR
+      .endif
+      add esi, sizeof (AP_MTRR_SETTINGS)
+      mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
+    .endw
+  .endif
+
+  ; restore variable MTTR6 and MTTR7 to default states
+  mov ecx, AMD_MTRR_VARIABLE_BASE6    ; clear MTRRPhysBase6 MTRRPhysMask6
+  xor eax, eax                        ; and MTRRPhysBase7 MTRRPhysMask7
+  xor edx, edx
+  .while (cl < 010h)
+    _WRMSR
+    inc cl
+  .endw
+
+  ; Enable fixed-range and variable-range MTRRs
+  mov ecx, AMD_MTRR_DEFTYPE
+  _RDMSR
+  or  ax, 0C00h       ; Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
+  _WRMSR
+
+  ; Enable Top-of-Memory setting
+  ; Enable use of RdMem/WrMem bits attributes
+  mov ecx, MTRR_SYS_CFG
+  _RDMSR
+  bts eax, MtrrVarDramEn    ; Enable
+  btr eax, MtrrFixDramModEn ; Disable
+  bts eax, MtrrFixDramEn    ; Enable
+  _WRMSR
+
+  ; Enable the self modifying code check buffer and Enable hardware prefetches
+  mov     ecx, 0C0011022h
+  _RDMSR
+  btr     eax, DC_DIS_SPEC_TLB_RLD    ; Disable speculative TLB reloads bit
+  btr     eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable the self modifying code check buffer bit
+  btr     eax, DIS_HW_PF              ; Disable hardware prefetches bit
+  _WRMSR
+
+  dec     cx                          ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
+  _RDMSR
+  btr     eax, IC_DIS_SPEC_TLB_RLD    ; turn on Disable speculative TLB reloads bit
+  _WRMSR
+
+  AMD_DISABLE_STACK_FAMILY_HOOK   ; Re-Enable L3 cache to accept clear lines
+
+  xor     eax, eax
+
+@@:
+  cli
+  hlt
+  jmp @B ;ExecuteHltInstruction
+ExecuteFinalHltInstruction ENDP
+
+;======================================================================
+; ExecuteHltInstruction:  Performs a hlt instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       eax, ebx, ecx, edx, esp
+;
+;======================================================================
+ExecuteHltInstruction PROC NEAR C PUBLIC
+  cli
+  hlt
+  ret
+ExecuteHltInstruction ENDP
+
+;======================================================================
+; NmiHandler:  Simply performs an IRET.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+NmiHandler PROC NEAR C PUBLIC
+  iretd
+NmiHandler ENDP
+
+;======================================================================
+; GetCsSelector:  Returns the current protected mode CS selector.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+GetCsSelector PROC NEAR C PUBLIC, CsSelector:PTR
+  push ax
+  push ebx
+
+  call FarCallGetCs
+  mov  ebx, CsSelector
+  mov  [ebx], ax
+  pop  ebx
+  pop  ax
+  ret
+GetCsSelector ENDP
+
+;======================================================================
+; FarCallGetCs:
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+; WARNING: This routine has a mirror routine in the PREMEM segment.
+;   These two routines MUST be sync'd for content.
+;======================================================================
+FarCallGetCs PROC FAR PRIVATE
+
+  mov  ax, ss:[esp + 4]
+  retf
+
+FarCallGetCs ENDP
+
+;======================================================================
+; SetIdtr:
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       none
+;
+; WARNING: This routine has a mirror routine in the PREMEM segment.
+;   These two routines MUST be sync'd for content.
+;======================================================================
+SetIdtr PROC NEAR C PUBLIC USES EBX, IdtPtr:PTR
+  mov   ebx, IdtPtr
+  lidt  fword ptr ss:[ebx]
+  ret
+SetIdtr ENDP
+
+;======================================================================
+; ExecuteWbinvdInstruction:  Performs a wbinvd instruction.
+;
+;   In:
+;       None
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+ExecuteWbinvdInstruction PROC NEAR C PUBLIC
+  wbinvd                        ; Write back the cache tag RAMs
+  ret
+ExecuteWbinvdInstruction ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
new file mode 100755
index 0000000000..2421bb9570
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
@@ -0,0 +1,309 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 35978 $   @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+
+ /*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// typedef unsigned int   uintptr_t;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+ExecuteFinalHltInstruction (
+  IN       AP_MTRR_SETTINGS  *ApMtrrSettingsList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetIdtr (
+  IN     IDT_BASE_LIMIT *IdtInfo,
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  );
+
+VOID
+GetCsSelector (
+  IN     UINT16 *Selector,
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  );
+
+VOID
+NmiHandler (
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  );
+
+VOID
+ExecuteHltInstruction (
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  );
+
+VOID
+ExecuteWbinvdInstruction (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+ /*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+//----------------------------------------------------------------------------
+
+STATIC
+VOID
+PrimaryCoreFunctions (AP_MTRR_SETTINGS  *ApMtrrSettingsList)
+   {
+   UINT64 data;
+   UINT32 msrno;
+   // Configure the MTRRs on the AP so
+   // when it runs remote code it will execute
+   // out of RAM instead of ROM.
+   // Disable MTRRs and turn on modification enable bit
+
+   data = __readmsr (0xC0010010);         // MTRR_SYS_CFG
+   data &= ~(1 << 18);                    // MtrrFixDramEn
+   data &= ~(1 << 20);                    // MtrrVarDramEn
+   data |= (1 << 19);                     // MtrrFixDramModEn
+   data |= (1 << 17);                     // SysUcLockEn
+   __writemsr (0xC0010010, data);
+
+   // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM
+   __writemsr (0x250, 0x1E1E1E1E1E1E1E1Eull); // AMD_MTRR_FIX64k_00000
+   __writemsr (0x258, 0x1E1E1E1E1E1E1E1Eull); // AMD_MTRR_FIX16k_80000
+
+   // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO
+   __writemsr (0x259, 0);                 // AMD_AP_MTRR_FIX16k_A0000
+   __writemsr (0x268, 0);                 // AMD_MTRR_FIX4k_C0000
+   __writemsr (0x269, 0);                 // AMD_MTRR_FIX4k_C8000
+   __writemsr (0x26A, 0);                 // AMD_MTRR_FIX4k_D0000
+   __writemsr (0x26B, 0);                 // AMD_MTRR_FIX4k_D8000
+
+   // Set FFFFFh-E0000h as Uncacheable Memory
+   for (msrno = 0x26C; msrno <= 0x26F; msrno++)
+      __writemsr (msrno, 0x1818181818181818ull);
+
+   // If IBV provided settings for Fixed-Sized MTRRs,
+   // overwrite the default settings.
+   if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF)
+      {
+      int index;
+      for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++)
+         __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
+      }
+
+   // restore variable MTTR6 and MTTR7 to default states
+   for (msrno = 0x20F; msrno <= 0x20C; msrno--)  // decrement so that the pair is disable before the base is cleared
+      __writemsr (msrno, 0);
+
+   // Enable fixed-range and variable-range MTRRs
+   // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
+   __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00);
+
+   // Enable Top-of-Memory setting
+   // Enable use of RdMem/WrMem bits attributes
+   data = __readmsr (0xC0010010);         // MTRR_SYS_CFG
+   data |= (1 << 18);                     // MtrrFixDramEn
+   data |= (1 << 20);                     // MtrrVarDramEn
+   data &= ~(1 << 19);                    // MtrrFixDramModEn
+   __writemsr (0xC0010010, data);
+   }
+
+//----------------------------------------------------------------------------
+
+VOID
+ExecuteFinalHltInstruction (
+  IN       AP_MTRR_SETTINGS  *ApMtrrSettingsList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+   int abcdRegs [4];
+   UINT32 cr0val;
+   UINT64 data;
+
+   cr0val = __readcr0 ();
+    //Make sure cache is disabled for all APs
+    __writecr0 (cr0val | 0x60000000);
+
+    //Configure the MTRRs on the AP so when it runs remote code it will execute
+    //out of RAM instead of ROM.
+    PrimaryCoreFunctions (ApMtrrSettingsList);
+
+   // Make sure not to touch any Shared MSR from this point on
+
+   // Restore settings that were temporarily overridden for the cache as ram phase
+   data = __readmsr (0xC0011022);      // MSR_DC_CFG
+   data &= ~(1 << 4);                  // DC_DIS_SPEC_TLB_RLD
+   data &= ~(1 << 8);                  // DIS_CLR_WBTOL2_SMC_HIT
+   data &= ~(1 << 13);                 // DIS_HW_PF
+   __writemsr (0xC0011022, data);
+
+   data = __readmsr (0xC0011021);      // MSR_IC_CFG - C001_1021
+   data &= ~(1 << 9);                  // IC_DIS_SPEC_TLB_RLD
+   __writemsr (0xC0011021, data);
+
+   // AMD_DISABLE_STACK_FAMILY_HOOK
+   __cpuid (abcdRegs, 1);
+   if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only-----
+      {
+      data = __readmsr (0xC0011022);
+      data &= ~(1 << 4);
+      data &= ~(1 << 8);
+      data &= ~(1 << 13);
+      __writemsr (0xC0011022, data);
+
+      data = __readmsr (0xC0011021);
+      data &= ~(1 << 14);
+      data &= ~(1 << 9);
+      __writemsr (0xC0011021, data);
+
+      data = __readmsr (0xC001102A);
+      data &= ~(1 << 15);
+      data &= ~(1ull << 35);
+      __writemsr (0xC001102A, data);
+      }
+   else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only-----
+      {
+      data = __readmsr (0xC0011020);
+      data &= ~(1 << 28);
+      __writemsr (0xC0011020, data);
+
+      data = __readmsr (0xC0011021);
+      data &= ~(1 << 9);
+      __writemsr (0xC0011021, data);
+
+      data = __readmsr (0xC0011022);
+      data &= ~(1 << 4);
+      data &= ~(1l << 13);
+      __writemsr (0xC0011022, data);
+      }
+
+   for (;;)
+     {
+     _disable ();
+     __halt ();
+     }
+  }
+
+//----------------------------------------------------------------------------
+
+/// Structure needed to load the IDTR using the lidt instruction
+
+VOID
+SetIdtr (
+  IN     IDT_BASE_LIMIT *IdtInfo,
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  )
+{
+   __lidt (IdtInfo);
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+GetCsSelector (
+  IN     UINT16 *Selector,
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  )
+{
+  static const UINT8 opcode [] = {0x8C, 0xC8, 0xC3}; // mov eax, cs; ret
+  *Selector = ((UINT16 (*)(void)) (size_t) opcode) ();
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+NmiHandler (
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  )
+{
+  static const UINT8 opcode [] = {0xCF};  // iret
+  ((void (*)(void)) (size_t) opcode) ();
+}
+
+//----------------------------------------------------------------------------
+
+VOID
+ExecuteHltInstruction (
+  IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
+  )
+{
+  _disable ();
+  __halt ();
+}
+
+//---------------------------------------------------------------------------
+
+VOID
+ExecuteWbinvdInstruction (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  __wbinvd ();
+}
+
+//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c
new file mode 100755
index 0000000000..8565084605
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.c
@@ -0,0 +1,1474 @@
+/**
+ * @file
+ *
+ * AMD CPU APIC related utility functions.
+ *
+ * Contains code that provides mechanism to invoke and control APIC communication.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUAPICUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* ApFlags bits */
+#define AP_TASK_HAS_INPUT    0x00000001
+#define AP_TASK_HAS_OUTPUT   0x00000002
+#define AP_RETURN_PARAMS     0x00000004
+#define AP_END_AT_HLT        0x00000008
+#define AP_PASS_EARLY_PARAMS 0x00000010
+
+#define SEG_DESC_PRESENT     0x80
+
+#define SEG_DESC_TYPE_LDT    0x02
+#define SEG_DESC_TYPE_CALL16 0x04
+#define SEG_DESC_TYPE_TASK   0x05
+#define SEG_DESC_TYPE_INT16  0x06
+#define SEG_DESC_TYPE_TRAP16 0x07
+#define SEG_DESC_TYPE_CALL32 0x0C
+#define SEG_DESC_TYPE_INT32  0x0E
+#define SEG_DESC_TYPE_TRAP32 0x0F
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef VOID F_CPU_AMD_NMI_HANDLER (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER;
+
+/// Interrupt Descriptor Table entry
+typedef struct {
+  UINT16 OffsetLo;     ///< Lower 16 bits of the interrupt handler routine's offset
+  UINT16 Selector;     ///< Interrupt handler routine's selector
+  UINT8  Rsvd;         ///< Reserved
+  UINT8  Flags;        ///< Interrupt flags
+  UINT16 OffsetHi;     ///< Upper 16 bits of the interrupt handler routine's offset
+  UINT32 Offset64;     ///< High order 32 bits of the handler's offset needed when in 64 bit mode
+  UINT32 Rsvd64;       ///< Reserved
+} IDT_DESCRIPTOR;
+
+#include "cpuRegisters.h"
+#if 0
+/// Structure needed to load the IDTR using the lidt instruction
+typedef struct {
+  UINT16 Limit;        ///< Interrupt Descriptor Table size
+  UINT64 Base;         ///< Interrupt Descriptor Table base address
+} IDT_BASE_LIMIT;
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+ApUtilSetupIdtForHlt (
+  IN       IDT_DESCRIPTOR *NmiIdtDescPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+STATIC
+ApUtilRemoteRead (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       UINT8 RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilLocalWrite (
+  IN       UINT32 RegAddr,
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+STATIC
+ApUtilLocalRead (
+  IN       UINT32 RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilGetLocalApicBase (
+     OUT   UINT64 *ApicBase,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+STATIC
+ApUtilCalculateUniqueId (
+  IN      UINT8 Socket,
+  IN      UINT8 Core,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilFireDirectedNmi (
+  IN      UINT8 Socket,
+  IN      UINT8 Core,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilReceivePointer (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+     OUT   VOID  **ReturnPointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+ApUtilTransmitPointer (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       VOID  **Pointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+PerformFinalHalt (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern
+VOID
+ExecuteHltInstruction (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern
+VOID
+GetCsSelector (
+  IN       UINT16 *Selector,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern
+VOID
+NmiHandler (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern
+VOID
+SetIdtr (
+  IN       IDT_BASE_LIMIT *IdtInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern
+VOID
+ExecuteFinalHltInstruction (
+  IN       AP_MTRR_SETTINGS  *ApMtrrSettingsList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern BUILD_OPT_CFG UserOptions;
+
+VOID
+LocalApicInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Local APIC.
+ *
+ * This function determines and programs the appropriate APIC ID value
+ * for the executing core.  This code must be run after HT initialization
+ * is complete.
+ *
+ *  @param[in]     CpuEarlyParamsPtr  Service parameters.
+ *  @param[in]     StdHeader          Config handle for library and services.
+ *
+ */
+STATIC VOID
+LocalApicInitialization (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT32    CurrentCore;
+  UINT32    CurrentNodeNum;
+  UINT32    CoreIdBits;
+  UINT32    Mnc;
+  UINT32    ProcessorCount;
+  UINT32    ProcessorApicIndex;
+  UINT32    IoApicNum;
+  UINT32    StartLocalApicId;
+  UINT64    LocalApicBase;
+  UINT32    TempVar_a;
+  UINT64    MsrData;
+  UINT64    Address;
+  CPUID_DATA  CpuidData;
+
+  // Local variables default values
+  IoApicNum = CpuEarlyParamsPtr->PlatformConfig.NumberOfIoApics;
+
+  GetCurrentCore (&CurrentCore, StdHeader);
+  GetCurrentNodeNum (&CurrentNodeNum, StdHeader);
+
+  // Get Mnc
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader);
+  CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12;
+  Mnc = 1 << (CoreIdBits & 0x000F);
+
+  // Get ProcessorCount in the system
+  ProcessorCount = GetNumberOfProcessors (StdHeader);
+
+  // Get the APIC Index of this processor.
+  ProcessorApicIndex = GetProcessorApicIndex (CurrentNodeNum, StdHeader);
+
+  TempVar_a = (Mnc * ProcessorCount) + IoApicNum;
+  ASSERT (TempVar_a < 255);
+
+  // Apply apic enumeration rules
+  // For systems with >= 16 APICs, put the IO-APICs at 0..n and
+  // put the local-APICs at m..z
+  // For systems with < 16 APICs, put the Local-APICs at 0..n and
+  // put the IO-APICs at (n + 1)..z
+  // This is needed because many IO-APIC devices only have 4 bits
+  // for their APIC id and therefore must reside at 0..15
+  StartLocalApicId = 0;
+  if (TempVar_a >= 16) {
+    if (IoApicNum >= 1) {
+      StartLocalApicId = (IoApicNum - 1) / Mnc;
+      StartLocalApicId = (StartLocalApicId + 1) * Mnc;
+    }
+  }
+
+  // Set local apic id
+  TempVar_a = (ProcessorApicIndex * Mnc) + CurrentCore + StartLocalApicId;
+  TempVar_a = TempVar_a << APIC20_ApicId;
+
+  // Enable local apic id
+  LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader);
+  MsrData |= APIC_ENABLE_BIT;
+  LibAmdMsrWrite (MSR_APIC_BAR, &MsrData, StdHeader);
+
+  // Get local apic base Address
+  ApUtilGetLocalApicBase (&LocalApicBase, StdHeader);
+
+  Address = LocalApicBase + APIC_ID_REG;
+  LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
+
+  /**
+   * print the debug information.
+   * For MCM processor:
+   *  Node 0x00 Core 0x00 is intenal Node 0 Core 0
+   *  Node 0x01 Core 0x04 is intenal Node 1 Core 0
+   */
+  printk(BIOS_DEBUG, "Node: 0x%02lx Core: 0x%02lx, Apicid = 0x%02lx\n",
+		  CurrentNodeNum, CurrentCore, TempVar_a >> APIC20_ApicId);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Local APIC at the AmdInitEarly entry point.
+ *
+ * This function acts as a wrapper for calling the LocalApicInitialization
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+LocalApicInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuLocalApicInit, StdHeader);
+  LocalApicInitialization (EarlyParams, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for all APs in the system.
+ *
+ * This routine puts the AP cores in an infinite loop in which the cores
+ * will poll their masters, waiting to be told to perform a task.  At early,
+ * all socket-relative core zeros will receive their tasks from the BSC.
+ * All others will receive their tasks from the core zero of their local
+ * processor.  At the end of AmdInitEarly, all cores will switch to receiving
+ * their tasks from the BSC.
+ *
+ * @param[in]     StdHeader       Handle to config for library and services.
+ * @param[in]     CpuEarlyParams  AMD_CPU_EARLY_PARAMS pointer.
+ *
+ */
+VOID
+ApEntry (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  UINT8   RemoteCmd;
+  UINT8   SourceSocket;
+  UINT8   CommandStart;
+  UINT32  ApFlags;
+  UINT32  FuncType;
+  UINT32  ReturnCode;
+  UINT32  CurrentSocket;
+  UINT32  CurrentCore;
+  UINT32  *InputDataPtr;
+  UINT32  BscSocket;
+  UINT32  Ignored;
+  AP_FUNCTION_PTR FuncAddress;
+  IDT_DESCRIPTOR IdtDesc;
+  AP_DATA_TRANSFER DataTransferInfo;
+  AGESA_STATUS IgnoredSts;
+
+  ASSERT (!IsBsp (StdHeader, &IgnoredSts));
+
+  // Initialize local variables
+  ReturnCode = 0;
+  DataTransferInfo.DataTransferFlags = 0;
+  InputDataPtr = NULL;
+
+  // Determine the executing core's socket and core numbers
+  IdentifyCore (StdHeader, &CurrentSocket, &Ignored, &CurrentCore, &IgnoredSts);
+
+  // Determine the BSC's socket number
+  GetSocketModuleOfNode ((UINT32) 0x00000000, &BscSocket, &Ignored, StdHeader);
+
+  // Setup Interrupt Descriptor Table for sleep mode
+  ApUtilSetupIdtForHlt (&IdtDesc, StdHeader);
+
+  // Indicate to the BSC that we have reached the tasking engine
+  ApUtilWriteControlByte (CORE_IDLE, StdHeader);
+
+  if (CurrentCore == 0) {
+    // Core 0s receive their tasks from the BSC
+    SourceSocket = (UINT8) BscSocket;
+  } else {
+    // All non-zero cores receive their tasks from the core 0 of their socket
+    SourceSocket = (UINT8) CurrentSocket;
+  }
+
+  // Determine the unique value that the master will write when it has a task
+  // for this core to perform.
+  CommandStart = ApUtilCalculateUniqueId (
+                   (UINT8)CurrentSocket,
+                   (UINT8)CurrentCore,
+                   StdHeader
+                   );
+  for (;;) {
+    RemoteCmd = ApUtilReadRemoteControlByte (SourceSocket, 0, StdHeader);
+    if (RemoteCmd == CommandStart) {
+      ApFlags = ApUtilReadRemoteDataDword (SourceSocket, 0, StdHeader);
+
+      ApUtilReceivePointer (SourceSocket, 0, (VOID **) &FuncAddress, StdHeader);
+
+      FuncType = ApFlags & (UINT32) (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS);
+      if ((ApFlags & AP_TASK_HAS_INPUT) != 0) {
+        DataTransferInfo.DataSizeInDwords = 0;
+        DataTransferInfo.DataPtr = NULL;
+        DataTransferInfo.DataTransferFlags = 0;
+        if (ApUtilReceiveBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader) == AGESA_ERROR) {
+          // There is not enough space to put the input data on the heap.  Undefined behavior is about
+          // to result.
+          IDS_ERROR_TRAP;
+        }
+        InputDataPtr = (UINT32 *) DataTransferInfo.DataPtr;
+      }
+      ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+      switch (FuncType) {
+      case 0:
+        FuncAddress.PfApTask (StdHeader);
+        break;
+      case AP_TASK_HAS_INPUT:
+        FuncAddress.PfApTaskI (InputDataPtr, StdHeader);
+        break;
+      case AP_PASS_EARLY_PARAMS:
+        FuncAddress.PfApTaskC (StdHeader, CpuEarlyParams);
+        break;
+      case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS):
+        FuncAddress.PfApTaskIC (InputDataPtr, StdHeader, CpuEarlyParams);
+        break;
+      case AP_TASK_HAS_OUTPUT:
+        ReturnCode = FuncAddress.PfApTaskO (StdHeader);
+        break;
+      case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT):
+        ReturnCode = FuncAddress.PfApTaskIO (InputDataPtr, StdHeader);
+        break;
+      case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+        ReturnCode = FuncAddress.PfApTaskOC (StdHeader, CpuEarlyParams);
+        break;
+      case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+        ReturnCode = FuncAddress.PfApTaskIOC (InputDataPtr, StdHeader, CpuEarlyParams);
+        break;
+      default:
+        ReturnCode = 0;
+        break;
+      }
+      if (((ApFlags & AP_RETURN_PARAMS) != 0)) {
+        ApUtilTransmitBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader);
+      }
+      if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) {
+        ApUtilWriteDataDword (ReturnCode, StdHeader);
+      }
+      if ((ApFlags & AP_END_AT_HLT) != 0) {
+        RemoteCmd = CORE_IDLE_HLT;
+      } else {
+        ApUtilWriteControlByte (CORE_IDLE, StdHeader);
+      }
+    }
+    if (RemoteCmd == CORE_IDLE_HLT) {
+      SourceSocket = (UINT8) BscSocket;
+      ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader);
+      ExecuteHltInstruction (StdHeader);
+      ApUtilWriteControlByte (CORE_IDLE, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads the 'control byte' on the designated remote core.
+ *
+ * This function will read the current contents of the control byte
+ * on the designated core using the APIC remote read inter-
+ * processor interrupt sequence.
+ *
+ * @param[in]      Socket        Socket number of the desired core
+ * @param[in]      Core          Core number of the desired core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ * @return         The current value of the remote cores control byte
+ *
+ */
+UINT8
+ApUtilReadRemoteControlByte (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  ControlByte;
+  UINT32 ApicRegister;
+
+  ApicRegister = ApUtilRemoteRead (Socket, Core, APIC_CTRL_DWORD, StdHeader);
+  ControlByte = (UINT8) ((ApicRegister & APIC_CTRL_MASK) >> APIC_CTRL_SHIFT);
+  return (ControlByte);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Writes the 'control byte' on the executing core.
+ *
+ * This function writes data to a local APIC offset used in inter-
+ * processor communication.
+ *
+ * @param[in]       Value
+ * @param[in]       StdHeader
+ *
+ */
+VOID
+ApUtilWriteControlByte (
+  IN       UINT8 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ApicRegister;
+
+  ApicRegister = ApUtilLocalRead (APIC_CTRL_REG, StdHeader);
+  ApicRegister = ((ApicRegister & ~APIC_CTRL_MASK) | (UINT32) (Value << APIC_CTRL_SHIFT));
+  ApUtilLocalWrite (APIC_CTRL_REG, ApicRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads the 'data dword' on the designated remote core.
+ *
+ * This function will read the current contents of the data dword
+ * on the designated core using the APIC remote read inter-
+ * processor interrupt sequence.
+
+ * @param[in]      Socket        Socket number of the desired core
+ * @param[in]      Core          Core number of the desired core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ * @return         The current value of the remote core's data dword
+ *
+ */
+UINT32
+ApUtilReadRemoteDataDword (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return (ApUtilRemoteRead (Socket, Core, APIC_DATA_DWORD, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Writes the 'data dword' on the executing core.
+ *
+ * This function writes data to a local APIC offset used in inter-
+ * processor communication.
+ *
+ * @param[in]      Value        Value to write
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+ApUtilWriteDataDword (
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ApUtilLocalWrite (APIC_DATA_REG, Value, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the given task on the specified local core.
+ *
+ * This function is used to invoke an AP to run a specified AGESA
+ * procedure.  It can only be called by cores that have subordinate
+ * APs -- the BSC at POST, or any socket-relative core 0s at Early.
+ *
+ * @param[in]      Socket       Socket number of the target core
+ * @param[in]      Core         Core number of the target core
+ * @param[in]      TaskPtr      Function descriptor
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @return         Return value of the task that the AP core ran,
+ *                 or zero if the task was VOID.
+ *
+ */
+UINT32
+ApUtilRunCodeOnSocketCore (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  CoreId;
+  UINT8  CurrentStatus;
+  UINT8  WaitStatus[3];
+  UINT32 ApFlags;
+  UINT32 ReturnCode;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  ApFlags = 0;
+  ReturnCode = 0;
+
+  CoreId = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
+
+  if (TaskPtr->DataTransfer.DataSizeInDwords != 0) {
+    ApFlags |= AP_TASK_HAS_INPUT;
+    if (((TaskPtr->ExeFlags & RETURN_PARAMS) != 0) &&
+        ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) {
+      ApFlags |= AP_RETURN_PARAMS;
+    }
+  }
+
+  if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) {
+    ApFlags |= AP_TASK_HAS_OUTPUT;
+  }
+
+  if ((TaskPtr->ExeFlags & END_AT_HLT) != 0) {
+    ApFlags |= AP_END_AT_HLT;
+  }
+
+  if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) {
+    ApFlags |= AP_PASS_EARLY_PARAMS;
+  }
+
+  WaitStatus[0] = CORE_IDLE;
+  WaitStatus[1] = CORE_IDLE_HLT;
+  WaitStatus[2] = CORE_UNAVAILABLE;
+  WaitForStatus.Status = WaitStatus;
+  WaitForStatus.NumberOfElements = 3;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+  CurrentStatus = ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+
+  if (CurrentStatus != CORE_UNAVAILABLE) {
+    ApUtilWriteDataDword (ApFlags, StdHeader);
+    ApUtilWriteControlByte (CoreId, StdHeader);
+
+    if (CurrentStatus == CORE_IDLE_HLT) {
+      ApUtilFireDirectedNmi (Socket, Core, StdHeader);
+    }
+
+    ApUtilTransmitPointer (Socket, Core, (VOID **) &TaskPtr->FuncAddress, StdHeader);
+
+    if ((ApFlags & AP_TASK_HAS_INPUT) != 0) {
+      ApUtilTransmitBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader);
+    }
+
+    if ((TaskPtr->ExeFlags & WAIT_FOR_CORE) != 0) {
+      if (((ApFlags & AP_TASK_HAS_INPUT) != 0) &&
+          ((ApFlags & AP_RETURN_PARAMS) != 0) &&
+          ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) {
+        if (ApUtilReceiveBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader) == AGESA_ERROR) {
+          // There is not enough space to put the return data.  This should never occur.  If it
+          // does, this would point to strange heap corruption.
+          IDS_ERROR_TRAP;
+        }
+      }
+
+      ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+      if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) {
+        ReturnCode = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
+      }
+    }
+  } else {
+    ReturnCode = 0;
+  }
+  return (ReturnCode);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Waits for a remote core's control byte value to either be equal or
+ * not equal to any number of specified values.
+ *
+ * This function will loop doing remote read IPIs until the remote core's
+ * control byte becomes one of the values in the input array if the input
+ * flags are set for equality.  Otherwise, the loop will continue until
+ * the control byte value is not equal to one of the elements in the
+ * array.  The caller can also specify an iteration count for timeout
+ * purposes.
+ *
+ * @param[in]      Socket
+ * @param[in]      Core
+ * @param[in]      WaitParamsPtr
+ * @param[in]      StdHeader
+ *
+ * @return         The current value of the remote core's control byte
+ *
+ */
+UINT8
+ApUtilWaitForCoreStatus (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AP_WAIT_FOR_STATUS *WaitParamsPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BOOLEAN  IsEqual;
+  UINT8 CoreStatus;
+  UINT8 i;
+  UINT8 j;
+
+  CoreStatus = 0;
+  for (i = 0; (WaitParamsPtr->RetryCount == WAIT_INFINITELY) ||
+              (i < WaitParamsPtr->RetryCount); ++i) {
+    CoreStatus = ApUtilReadRemoteControlByte (Socket, Core, StdHeader);
+    // Determine whether or not the current remote status is equal
+    // to an element in the array.
+    IsEqual = FALSE;
+    for (j = 0; !IsEqual && j < WaitParamsPtr->NumberOfElements; ++j) {
+      if (CoreStatus == WaitParamsPtr->Status[j]) {
+        IsEqual = TRUE;
+      }
+    }
+    if ((((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) != 0) && IsEqual) ||
+        (((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) == 0) && !IsEqual)) {
+      break;
+    }
+  }
+  return (CoreStatus);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the AP task on the executing core.
+ *
+ * @param[in]      TaskPtr      Function descriptor
+ * @param[in]      StdHeader    Configuration parameters pointer
+ * @param[in]      ConfigParams Entry point CPU parameters pointer
+ *
+ * @return         Return value of the task, or zero if the task
+ *                 was VOID.
+ *
+ */
+UINT32
+ApUtilTaskOnExecutingCore (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  )
+{
+  UINT32   InvocationOptions;
+  UINT32   ReturnCode;
+
+  ReturnCode = 0;
+  InvocationOptions = 0;
+
+  if (TaskPtr->DataTransfer.DataSizeInDwords != 0) {
+    InvocationOptions |= AP_TASK_HAS_INPUT;
+  }
+  if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) {
+    InvocationOptions |= AP_TASK_HAS_OUTPUT;
+  }
+  if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) {
+    InvocationOptions |= AP_PASS_EARLY_PARAMS;
+  }
+
+  switch (InvocationOptions) {
+  case 0:
+    TaskPtr->FuncAddress.PfApTask (StdHeader);
+    break;
+  case AP_TASK_HAS_INPUT:
+    TaskPtr->FuncAddress.PfApTaskI (TaskPtr->DataTransfer.DataPtr, StdHeader);
+    break;
+  case AP_PASS_EARLY_PARAMS:
+    TaskPtr->FuncAddress.PfApTaskC (StdHeader, ConfigParams);
+    break;
+  case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS):
+    TaskPtr->FuncAddress.PfApTaskIC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams);
+    break;
+  case AP_TASK_HAS_OUTPUT:
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskO (StdHeader);
+    break;
+  case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT):
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskIO (TaskPtr->DataTransfer.DataPtr, StdHeader);
+    break;
+  case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskOC (StdHeader, ConfigParams);
+    break;
+  case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
+    ReturnCode = TaskPtr->FuncAddress.PfApTaskIOC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams);
+    break;
+  default:
+    ReturnCode = 0;
+    break;
+  }
+  return (ReturnCode);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
+ *
+ * This function prepares the executing AP core for recovering from a hlt
+ * instruction by initializing its IDTR.
+ *
+ * @param[in]        NmiIdtDescPtr Pointer to a writable IDT entry to
+ *                                 be used for NMIs
+ * @param[in]        StdHeader     Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilSetupIdtForHlt (
+  IN       IDT_DESCRIPTOR *NmiIdtDescPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   DescSize;
+  UINT64  HandlerOffset;
+  UINT64  EferRegister;
+  IDT_BASE_LIMIT IdtInfo;
+
+  LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader);
+  if ((EferRegister & 0x100) != 0) {
+    DescSize = 16;
+  } else {
+    DescSize = 8;
+  }
+
+  HandlerOffset = (UINT32) NmiHandler;
+  NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF;
+  NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16);
+  GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);
+  NmiIdtDescPtr->Flags = SEG_DESC_PRESENT | SEG_DESC_TYPE_INT32;
+  NmiIdtDescPtr->Rsvd = 0;
+  NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32);
+  NmiIdtDescPtr->Rsvd64 = 0;
+  IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1);
+  IdtInfo.Base = (UINT32) NmiIdtDescPtr - (DescSize * 2);
+  SetIdtr (&IdtInfo , StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate the APIC ID for a given core.
+ *
+ * Get the current node's apic id and deconstruct it to the base id of local apic id space.
+ * Then construct the target's apic id using that base.
+ * @b Assumes: The target Socket and Core exist!
+ * Other Notes:
+ *  - Must run after HT initialization is complete.
+ *  - Code sync: This calculation MUST match the assignment
+ *    calculation done above in LocalApicInitializationAtEarly function.
+ *  - Assumes family homogeneous population of all sockets.
+ *
+ *  @param[in]      TargetSocket   The socket in which the Core's Processor is installed.
+ *  @param[in]      TargetCore     The Core on that Processor
+ *  @param[out]     LocalApicId    Its APIC Id
+ *  @param[in]      StdHeader      Handle to header for library and services.
+ *
+ */
+VOID
+GetLocalApicIdForCore (
+  IN       UINT32            TargetSocket,
+  IN       UINT32            TargetCore,
+     OUT   UINT32            *LocalApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  CoreIdBits;
+  UINT32  CurrentNode;
+  UINT32  CurrentCore;
+  UINT32  TargetNode;
+  UINT32  MaxCoresInProcessor;
+  UINT32  TotalCores;
+  UINT32  CurrentLocalApicId;
+  UINT64  LocalApicBase;
+  UINT32  TempVar_a;
+  UINT64  Address;
+  UINT32  ProcessorApicIndex;
+  BOOLEAN ReturnResult;
+  CPUID_DATA  CpuidData;
+
+  TargetNode = 0;
+
+  // Get local apic base Address
+  ApUtilGetLocalApicBase (&LocalApicBase, StdHeader);
+  Address = LocalApicBase + APIC_ID_REG;
+
+  LibAmdMemRead (AccessWidth32, Address, &TempVar_a, StdHeader);
+
+  // ApicId [7:0]
+  CurrentLocalApicId = (TempVar_a >> APIC20_ApicId) & 0x000000FF;
+
+  GetCurrentNodeAndCore (&CurrentNode, &CurrentCore, StdHeader);
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader);
+  CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12;
+  MaxCoresInProcessor = (1 << CoreIdBits);
+
+  // Get the APIC Index of this processor.
+  ProcessorApicIndex = GetProcessorApicIndex (CurrentNode, StdHeader);
+
+  TotalCores = (MaxCoresInProcessor * ProcessorApicIndex) + CurrentCore;
+  CurrentLocalApicId -= TotalCores;
+
+  // Use the Node Id of TargetSocket, Module 0.  No socket transitions are missed or added,
+  // even if the TargetCore is not on Module 0 in that processor and that's all that matters now.
+  ReturnResult = GetNodeId (TargetSocket, 0, (UINT8 *)&TargetNode, StdHeader);
+  ASSERT (ReturnResult);
+
+  // Get the APIC Index of this processor.
+  ProcessorApicIndex = GetProcessorApicIndex (TargetNode, StdHeader);
+
+  CurrentLocalApicId += ((MaxCoresInProcessor * ProcessorApicIndex) + TargetCore);
+  *LocalApicId = CurrentLocalApicId;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely passes a buffer to the designated remote core.
+ *
+ * This function uses a sequence of remote reads to transmit a data
+ * buffer, one UINT32 at a time.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[in]      BufferInfo   Information about the buffer to pass, and
+ *                              how to pass it
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+ApUtilTransmitBuffer (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN       AP_DATA_TRANSFER  *BufferInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  TargetCore;
+  UINT8  MyUniqueId;
+  UINT8  CurrentStatus;
+  UINT32 *CurrentPtr;
+  UINT32 i;
+  UINT32 MyCore;
+  UINT32 MySocket;
+  UINT32 Ignored;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+  AGESA_STATUS IgnoredSts;
+
+  if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
+    ApUtilWriteDataDword ((UINT32) 0x00000000, StdHeader);
+  } else {
+    ApUtilWriteDataDword ((UINT32) BufferInfo->DataSizeInDwords, StdHeader);
+  }
+  TargetCore = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
+
+  ApUtilWriteControlByte (TargetCore, StdHeader);
+
+  IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &IgnoredSts);
+
+  MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader);
+
+  WaitForStatus.Status = &MyUniqueId;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+
+  ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+  ApUtilWriteDataDword (BufferInfo->DataTransferFlags, StdHeader);
+
+  ApUtilWriteControlByte (CORE_DATA_FLAGS_READY, StdHeader);
+  WaitForStatus.WaitForStatusFlags = 0;
+  ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+  if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
+    ApUtilTransmitPointer (Socket, Core, (VOID **) &BufferInfo->DataPtr, StdHeader);
+  } else {
+    ApUtilWriteControlByte (CORE_STS_DATA_READY_1, StdHeader);
+    CurrentStatus = CORE_STS_DATA_READY_0;
+    WaitForStatus.Status = &CurrentStatus;
+    WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+    ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+    WaitForStatus.WaitForStatusFlags = 0;
+    CurrentPtr = (UINT32 *) BufferInfo->DataPtr;
+    for (i = 0; i < BufferInfo->DataSizeInDwords; ++i) {
+      ApUtilWriteDataDword (*CurrentPtr++, StdHeader);
+      ApUtilWriteControlByte (CurrentStatus, StdHeader);
+      ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+      CurrentStatus ^= 0x01;
+    }
+  }
+  ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely receives a buffer from the designated remote core.
+ *
+ * This function uses a sequence of remote reads to receive a data
+ * buffer, one UINT32 at a time.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[in]      BufferInfo   Information about where to place the buffer
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @retval         AGESA_SUCCESS Transaction was successful
+ * @retval         AGESA_ALERT   The non-NULL desired location to place
+ *                               the buffer was not used as the buffer
+ *                               resides in a shared memory space.  The
+ *                               input data pointer has changed.
+ * @retval         AGESA_ERROR   There is not enough room to receive the
+ *                               buffer.
+ *
+ */
+AGESA_STATUS
+ApUtilReceiveBuffer (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN OUT   AP_DATA_TRANSFER  *BufferInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    MyUniqueId;
+  UINT8    SourceUniqueId;
+  UINT8    CurrentStatus;
+  UINT32   i;
+  UINT32   MySocket;
+  UINT32   MyCore;
+  UINT32   Ignored;
+  UINT32   *CurrentPtr;
+  UINT32   TransactionSize;
+  AGESA_STATUS ReturnStatus;
+  ALLOCATE_HEAP_PARAMS HeapMalloc;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  ReturnStatus = AGESA_SUCCESS;
+  IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &ReturnStatus);
+
+  MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader);
+
+  WaitForStatus.Status = &MyUniqueId;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+
+  ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+  TransactionSize = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
+
+  if (BufferInfo->DataPtr == NULL && TransactionSize != 0) {
+    HeapMalloc.BufferHandle = AMD_CPU_AP_TASKING_HANDLE;
+    HeapMalloc.Persist = HEAP_LOCAL_CACHE;
+    // Deallocate the general purpose heap structure, if it exists.  Ignore
+    // the status in case it does not exist.
+    HeapDeallocateBuffer (HeapMalloc.BufferHandle, StdHeader);
+    HeapMalloc.RequestedBufferSize = (UINT16) (TransactionSize << 2);
+    if (HeapAllocateBuffer (&HeapMalloc, StdHeader) == AGESA_SUCCESS) {
+      BufferInfo->DataPtr = (UINT32 *) HeapMalloc.BufferPtr;
+      BufferInfo->DataSizeInDwords = HeapMalloc.RequestedBufferSize >> 2;
+    } else {
+      BufferInfo->DataSizeInDwords = 0;
+    }
+  }
+
+  if (TransactionSize <= BufferInfo->DataSizeInDwords) {
+    SourceUniqueId = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
+    ApUtilWriteControlByte (SourceUniqueId, StdHeader);
+    CurrentStatus = CORE_DATA_FLAGS_READY;
+    WaitForStatus.Status = &CurrentStatus;
+    ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+    BufferInfo->DataTransferFlags =  ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
+    ApUtilWriteControlByte (CORE_DATA_FLAGS_ACKNOWLEDGE, StdHeader);
+    if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
+      if (BufferInfo->DataPtr != NULL) {
+        ReturnStatus = AGESA_ALERT;
+      }
+      ApUtilReceivePointer (Socket, Core, (VOID **) &BufferInfo->DataPtr, StdHeader);
+    } else {
+      CurrentStatus = CORE_STS_DATA_READY_1;
+      ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+      CurrentStatus = CORE_STS_DATA_READY_0;
+      ApUtilWriteControlByte (CurrentStatus, StdHeader);
+      CurrentPtr = BufferInfo->DataPtr;
+      for (i = 0; i < TransactionSize; ++i) {
+        ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+        *CurrentPtr++ = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
+        CurrentStatus ^= 0x01;
+        ApUtilWriteControlByte (CurrentStatus, StdHeader);
+      }
+    }
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+  } else {
+    BufferInfo->DataSizeInDwords = (UINT16) TransactionSize;
+    ReturnStatus = AGESA_ERROR;
+  }
+  return (ReturnStatus);
+}
+
+
+VOID
+RelinquishControlOfAllAPs (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32        BscSocket;
+  UINT32        Ignored;
+  UINT32        BscCore;
+  UINT32        Core;
+  UINT32        Socket;
+  UINT32        NumberOfSockets;
+  UINT32        NumberOfCores;
+  AP_TASK       TaskPtr;
+  AGESA_STATUS  IgnoredSts;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  TaskPtr.FuncAddress.PfApTask = PerformFinalHalt;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The last AGESA code that an AP performs
+ *
+ * This function, run only by APs, breaks down their cache subsystem, sets up
+ * for memory to be present upon wake (from IBV Init/Startup IPIs), and halts.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+PerformFinalHalt (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ApUtilWriteControlByte (CORE_UNAVAILABLE, StdHeader);
+  ExecuteFinalHltInstruction (UserOptions.CfgApMtrrSettingsList, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads the APIC register on the designated remote core.
+ *
+ * This function uses the remote read inter-processor interrupt protocol
+ * to read an APIC register from the remote core
+ *
+ * @param[in]        Socket       Socket number of remote core
+ * @param[in]        Core         Core number of remote core
+ * @param[in]        RegAddr      APIC register to read
+ * @param[in]        StdHeader    Configuration parameters pointer
+ *
+ * @return           The current value of the remote core's desired APIC register
+ *
+ */
+UINT32
+STATIC
+ApUtilRemoteRead (
+  IN       UINT8             Socket,
+  IN       UINT8             Core,
+  IN       UINT8             RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ApicRegister;
+  UINT32 TargetApicId;
+  UINT64 ApicBase;
+  UINT64 ApicAddr;
+
+  ApUtilGetLocalApicBase (&ApicBase, StdHeader);
+  GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader);
+  TargetApicId <<= LOCAL_APIC_ID;
+
+  do {
+    ApicAddr = ApicBase + APIC_CMD_HI_REG;
+    LibAmdMemWrite (AccessWidth32, ApicAddr, &TargetApicId, StdHeader);
+    ApicAddr = ApicBase + APIC_CMD_LO_REG;
+    ApicRegister = CMD_REG_TO_READ | (UINT32) RegAddr;
+    LibAmdMemWrite (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+    do {
+      LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+    } while ((ApicRegister & CMD_REG_DELIVERY_STATUS) != 0);
+    while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) == CMD_REG_REMOTE_DELIVERY_PENDING) {
+      LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+    }
+  } while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) != CMD_REG_REMOTE_DELIVERY_DONE);
+  ApicAddr = ApicBase + APIC_REMOTE_READ_REG;
+  LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+  return (ApicRegister);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Writes an APIC register on the executing core.
+ *
+ * This function gets the base address of the executing core's local APIC,
+ * and writes a UINT32 value to a specified offset.
+ *
+ * @param[in]      RegAddr      APIC register to write to
+ * @param[in]      Value        Data to be written to the desired APIC register
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilLocalWrite (
+  IN       UINT32 RegAddr,
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 ApicAddr;
+
+  ApUtilGetLocalApicBase (&ApicAddr, StdHeader);
+  ApicAddr += RegAddr;
+
+  LibAmdMemWrite (AccessWidth32, ApicAddr, &Value, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Reads an APIC register on the executing core.
+ *
+ * This function gets the base address of the executing core's local APIC,
+ * and reads a UINT32 value from a specified offset.
+ *
+ * @param[in]      RegAddr      APIC register to read from
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @return         The current value of the local APIC register
+ *
+ */
+UINT32
+STATIC
+ApUtilLocalRead (
+  IN       UINT32  RegAddr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ApicRegister;
+  UINT64 ApicAddr;
+
+  ApUtilGetLocalApicBase (&ApicAddr, StdHeader);
+  ApicAddr += RegAddr;
+  LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
+
+  return (ApicRegister);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the 64-bit base address of the executing core's local APIC.
+ *
+ * This function reads the APICBASE MSR and isolates the programmed address.
+ *
+ * @param[out]     ApicBase     Base address
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilGetLocalApicBase (
+     OUT   UINT64 *ApicBase,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdMsrRead (MSR_APIC_BAR, ApicBase, StdHeader);
+  *ApicBase &= LAPIC_BASE_ADDR_MASK;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the unique ID of the input Socket/Core.
+ *
+ * This routine converts a socket-core combination to to a number
+ * that will be used to directly address a particular core.  This
+ * unique value must be less than 128 because we only have a byte
+ * to use for status.  APIC IDs are not guaranteed to be below
+ * 128.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ * @return         The unique ID of the desired core
+ *
+ */
+UINT8
+STATIC
+ApUtilCalculateUniqueId (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 UniqueId;
+
+  UniqueId = ((Core << 3) | Socket);
+  ASSERT ((UniqueId & 0x80) == 0);
+  return (UniqueId);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Wakes up a core from the halted state.
+ *
+ * This function sends a directed NMI inter-processor interrupt to
+ * the input Socket/Core.
+ *
+ * @param[in]      Socket          Socket number of remote core to wake up
+ * @param[in]      Core            Socket-relative core number of the remote core to wake up
+ * @param[in]      StdHeader       Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilFireDirectedNmi (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 TargetApicId;
+
+  GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader);
+  TargetApicId <<= LOCAL_APIC_ID;
+
+  ApUtilLocalWrite ((UINT32) APIC_CMD_HI_REG, TargetApicId, StdHeader);
+  ApUtilLocalWrite ((UINT32) APIC_CMD_LO_REG, (UINT32) CMD_REG_TO_NMI, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely receives a pointer from the designated remote core.
+ *
+ * This function uses a sequence of remote reads to receive a pointer,
+ * one UINT32 at a time.
+ *
+ * @param[in]      Socket        Socket number of the remote core
+ * @param[in]      Core          Core number of the remote core
+ * @param[out]     ReturnPointer Pointer passed from remote core
+ * @param[in]      StdHeader     Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilReceivePointer (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+     OUT   VOID  **ReturnPointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   i;
+  UINT8   WaitStatus;
+  UINT32  *AddressScratchPtr;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  WaitStatus = CORE_STS_DATA_READY_0;
+  WaitForStatus.Status = &WaitStatus;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+  AddressScratchPtr = (UINT32 *) ReturnPointer;
+  for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); ++i) {
+    ApUtilWriteControlByte (CORE_NEEDS_PTR, StdHeader);
+    WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+    ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+    *AddressScratchPtr++ = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+    WaitForStatus.WaitForStatusFlags = 0;
+    ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Securely transmits a pointer to the designated remote core.
+ *
+ * This function uses a sequence of remote reads to transmit a pointer,
+ * one UINT32 at a time.
+ *
+ * @param[in]      Socket       Socket number of the remote core
+ * @param[in]      Core         Core number of the remote core
+ * @param[out]     Pointer      Pointer passed from remote core
+ * @param[in]      StdHeader    Configuration parameters pointer
+ *
+ */
+VOID
+STATIC
+ApUtilTransmitPointer (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       VOID  **Pointer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   i;
+  UINT8   WaitStatus;
+  UINT32  *AddressScratchPtr;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+
+  WaitStatus = CORE_NEEDS_PTR;
+  WaitForStatus.Status = &WaitStatus;
+  WaitForStatus.NumberOfElements = 1;
+  WaitForStatus.RetryCount = WAIT_INFINITELY;
+
+  AddressScratchPtr = (UINT32 *) Pointer;
+
+  for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); i++) {
+    WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+    ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+    ApUtilWriteDataDword (*AddressScratchPtr++, StdHeader);
+    ApUtilWriteControlByte (CORE_STS_DATA_READY_0, StdHeader);
+    WaitForStatus.WaitForStatusFlags = 0;
+    ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h
new file mode 100755
index 0000000000..1762aac6ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuApicUtilities.h
@@ -0,0 +1,260 @@
+/**
+ * @file
+ *
+ * AMD CPU APIC related utility functions and structures
+ *
+ * Contains code that provides mechanism to invoke and control APIC communication.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_APIC_UTILITIES_H_
+#define _CPU_APIC_UTILITIES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define APIC_CTRL_DWORD 0xF
+#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
+#define APIC_CTRL_MASK 0xFF
+#define APIC_CTRL_SHIFT 0
+
+#define APIC_DATA_DWORD 0x38
+#define APIC_DATA_REG (APIC_DATA_DWORD << 4)
+
+#define APIC_REMOTE_READ_REG 0xC0
+#define APIC_CMD_LO_REG 0x300
+#define APIC_CMD_HI_REG 0x310
+
+// APIC_CMD_LO_REG bits
+#define CMD_REG_DELIVERY_STATUS 0x1000
+#define CMD_REG_TO_READ 0x300
+#define CMD_REG_REMOTE_RD_STS_MSK 0x30000
+#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000
+#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000
+#define CMD_REG_TO_NMI 0x400
+
+// ExeFlags bits
+#define WAIT_FOR_CORE     0x00000001
+#define TASK_HAS_OUTPUT   0x00000002
+#define RETURN_PARAMS     0x00000004
+#define END_AT_HLT        0x00000008
+#define PASS_EARLY_PARAMS 0x00000010
+
+// Control Byte Values
+// bit 7 indicates the type of message
+// 1 - control message
+// 0 - launch + APIC ID = message to go
+//
+#define CORE_UNAVAILABLE            0xFF
+#define CORE_IDLE                   0xFE
+#define CORE_IDLE_HLT               0xFD
+#define CORE_ACTIVE                 0xFC
+#define CORE_NEEDS_PTR              0xFB
+#define CORE_NEEDS_DATA_SIZE        0xFA
+#define CORE_STS_DATA_READY_1       0xF9
+#define CORE_STS_DATA_READY_0       0xF8
+#define CORE_DATA_FLAGS_READY       0xF7
+#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
+#define CORE_DATA_PTR_READY         0xF5
+
+// Macro used to determine the number of dwords to transmit to the AP as input
+#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+
+/// Function pointer union representing the eight different
+/// types of functions that an AP can be asked to perform.
+typedef union {
+  PF_AP_TASK     PfApTask;      ///< AMD_CONFIG_PARAMS *  input with no output
+  PF_AP_TASK_I   PfApTaskI;     ///< VOID * + AMD_CONFIG_PARAMS *  input with no output
+  PF_AP_TASK_C   PfApTaskC;     ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS *  input with no output
+  PF_AP_TASK_IC  PfApTaskIC;    ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS *  input with no output
+  PF_AP_TASK_O   PfApTaskO;     ///< AMD_CONFIG_PARAMS * input with UINT32 output
+  PF_AP_TASK_IO  PfApTaskIO;    ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
+  PF_AP_TASK_OC  PfApTaskOC;    ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
+  PF_AP_TASK_IOC PfApTaskIOC;   ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS *  input with UINT32 output
+} AP_FUNCTION_PTR;
+
+/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
+/// containing information about the data transfer from one core
+/// to another.
+typedef struct {
+  IN OUT   UINT16 DataSizeInDwords;   ///< Size of the data to be transferred rounded up to the nearest dword
+  IN OUT   VOID   *DataPtr;           ///< Pointer to the data
+  IN       UINT32 DataTransferFlags;  ///< Flags dictating certain aspects of the data transfer
+} AP_DATA_TRANSFER;
+
+/// Input structure for ApUtilRunCodeOnSocketCore.
+typedef struct _AP_TASK {
+  AP_FUNCTION_PTR  FuncAddress;   ///< Pointer to the function that the AP will run
+  AP_DATA_TRANSFER DataTransfer;  ///< Data transfer struct for optionally passing data that the AP should use as input to the function
+  UINT32           ExeFlags;      ///< Flags dictating certain aspects of the AP tasking sequence
+} AP_TASK;
+
+/// Input structure for ApUtilWaitForCoreStatus.
+typedef struct {
+  IN       UINT8  *Status;            ///< Pointer to the 1st element of an array of values to wait for
+  IN       UINT8  NumberOfElements;   ///< Number of elements in the array
+  IN       UINT32 RetryCount;         ///< Number of remote read cycles to complete before quitting
+  IN       UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
+} AP_WAIT_FOR_STATUS;
+
+#define WAIT_STATUS_EQUALITY 0x00000001
+#define WAIT_INFINITELY 0
+
+// Data Transfer Flags
+#define DATA_IN_MEMORY 0x00000001
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+//                   These are   P U B L I C   functions, used by AGESA
+UINT8
+ApUtilReadRemoteControlByte (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApUtilWriteControlByte (
+  IN       UINT8 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+ApUtilReadRemoteDataDword (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApUtilWriteDataDword (
+  IN       UINT32 Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+ApUtilRunCodeOnSocketCore (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+ApUtilWaitForCoreStatus (
+  IN       UINT8 Socket,
+  IN       UINT8 Core,
+  IN       AP_WAIT_FOR_STATUS *WaitParamsPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApEntry (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+UINT32
+ApUtilTaskOnExecutingCore (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID    *ConfigParams
+  );
+
+VOID
+ApUtilTransmitBuffer (
+  IN     UINT8   Socket,
+  IN     UINT8   Core,
+  IN     AP_DATA_TRANSFER *BufferInfo,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+ApUtilReceiveBuffer (
+  IN       UINT8   Socket,
+  IN       UINT8   Core,
+  IN OUT   AP_DATA_TRANSFER  *BufferInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetLocalApicIdForCore (
+  IN       UINT32 TargetSocket,
+  IN       UINT32 TargetCore,
+     OUT   UINT32 *LocalApicId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ApUtilRunCodeOnAllLocalCoresAtEarly (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+VOID
+RelinquishControlOfAllAPs (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif  /* _CPU_APIC_UTILITIES_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c
new file mode 100755
index 0000000000..931f92018a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBist.c
@@ -0,0 +1,168 @@
+/**
+ * @file
+ *
+ * AMD CPU BIST Status Check Implementation.
+ *
+ * Implement CPU BIST Status checking
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUBIST_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+UINT32
+STATIC
+GetBistResults (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+ /*----------------------------------------------------------------------------------------
+  *                          E X P O R T E D    F U N C T I O N S
+  *----------------------------------------------------------------------------------------
+ */
+
+ /*---------------------------------------------------------------------------------------*/
+ /**
+  *
+  * This function checks the status of BIST and places the error status in the event log
+  * if there are any errors
+  *
+  * @param[in]      StdHeader              Header for library and services
+  *
+  * @retval         AGESA_SUCCESS          No BIST errors have been logged.
+  * @retval         AGESA_ALERT            BIST errors have been detected and added to the
+  *                                        event log.
+  */
+AGESA_STATUS
+CheckBistStatus (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                Socket;
+  UINT32                Core;
+  UINT32                BscSocket;
+  UINT32                BscCore;
+  UINT32                NumberOfSockets;
+  UINT32                NumberOfCores;
+  UINT32                Ignored;
+  UINT32                ReturnCode;
+  AGESA_STATUS          IgnoredSts;
+  AGESA_STATUS          AgesaStatus;
+  AP_TASK               TaskPtr;
+
+  // Make sure that Standard Header is valid
+  ASSERT (StdHeader != NULL);
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Get the BscSocket, BscCore and NumberOfSockets in the system
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  // Setup TaskPtr struct to execute routine on APs
+  TaskPtr.FuncAddress.PfApTaskO = GetBistResults;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCore)) {
+          ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+        } else {
+          ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader);
+        }
+
+        // If BIST value is non-zero, add to BSP's event log
+        if (ReturnCode != 0) {
+          AgesaStatus = AGESA_ALERT;
+          PutEventLog (AGESA_ALERT,
+                       CPU_EVENT_BIST_ERROR,
+                       ReturnCode, Socket, Core, 0, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L          F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+*/
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Reads the lower 32 bits of the BIST register
+ *
+ * @param[in]      StdHeader              Header for library and services
+ *
+ * @retval         Value of the BIST register
+*/
+UINT32
+STATIC
+GetBistResults (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64   BistResults;
+
+  // Read MSRC001_0060 BIST Results Register
+  LibAmdMsrRead (MSR_BIST, &BistResults, StdHeader);
+
+  return (UINT32) (BistResults & 0xFFFFFFFF);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c
new file mode 100755
index 0000000000..3541c03556
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuBrandId.c
@@ -0,0 +1,311 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuEarlyInit.h"
+#include "cpuRegisters.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUBRANDID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST CHAR8 ROMDATA strEngSample[] = "AMD Engineering Sample";
+CONST CHAR8 ROMDATA strTtkSample[] = "AMD Thermal Test Kit";
+CONST CHAR8 ROMDATA strUnknown[] = "AMD Processor Model Unknown";
+
+CONST AMD_CPU_BRAND ROMDATA EngSample_Str = {0, 0, 0, SOCKET_IGNORE, strEngSample, sizeof (strEngSample)};
+CONST AMD_CPU_BRAND ROMDATA TtkSample_Str = {0, 1, 0, SOCKET_IGNORE, strTtkSample, sizeof (strTtkSample)};
+CONST AMD_CPU_BRAND ROMDATA Dflt_Str1 = {0, 0, 0, SOCKET_IGNORE, strUnknown, sizeof (strUnknown)};
+CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, DR_NO_STRING};
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program BrandID registers (CPUIDNameStringPtr[0-5])
+ *
+ * This function determines the appropriate brand string for the executing
+ * core, and programs the namestring MSRs.
+ *
+ * @param[in,out] StdHeader   Config handle for library and services.
+ *
+ */
+VOID
+SetBrandIdRegisters (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   SocketIndex;
+  UINT8   SuffixStatus;
+  UINT8   TableElements;
+  UINT8   TableEntryCount;
+  UINT8   TableEntryIndex;
+  CHAR8   TempChar;
+  CHAR8   *NameStringPtr;
+  CHAR8   *SuffixStringPtr;
+  CHAR8   *BrandStringPtr;
+  CHAR8   *TempNameCharPtr;
+  UINT32  MsrIndex;
+  UINT32  Quotient;
+  UINT32  Remainder;
+  UINT64  *MsrNameStringPtrPtr;
+  CPUID_DATA    CpuId;
+  CPU_LOGICAL_ID CpuLogicalId;
+  CPU_BRAND_TABLE *SocketTableEntry;
+  CPU_BRAND_TABLE **SocketTableEntry1;
+  AMD_CPU_BRAND *SocketTablePtr;
+  AMD_CPU_BRAND_DATA Data;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  SuffixStatus = 0;
+  FamilySpecificServices = NULL;
+  SocketTablePtr = NULL;
+  SocketTableEntry = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  // Step1: Allocate 48 bytes from Heap space
+  AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH;
+  AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    // Clear NameBuffer
+    BrandStringPtr = (CHAR8 *) AllocHeapParams.BufferPtr;
+    LibAmdMemFill (BrandStringPtr, 0, CPU_BRAND_ID_LENGTH, StdHeader);
+  } else {
+    PutEventLog (
+      AGESA_ERROR,
+      CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE,
+      0, 0, 0, 0, StdHeader
+      );
+    return;
+  }
+
+  // Step2: Get brandid from model number and model string
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+
+  // @todo: BrandId should be the common routine. Read from CPUID should move to Cpu Family Specific Service...
+  // Step3: Figure out Socket/Page/Model/String1/String2/Core Number
+  Data.String2 = (UINT8) (CpuId.EBX_Reg & 0x0f);
+  Data.Model   = (UINT8) ((CpuId.EBX_Reg >> 4) & 0x7f);
+  Data.String1 = (UINT8) ((CpuId.EBX_Reg >> 11) & 0x0f);
+  Data.Page    = (UINT8) ((CpuId.EBX_Reg >> 15) & 0x01);
+  Data.Socket  = (UINT8) ((CpuId.EBX_Reg >> 28) & 0x0f);
+  Data.Cores = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
+
+  // Step4: If NN = 0, we have an engineering sample, no suffix; then jump to Step6
+  if (Data.Model == 0) {
+    if (Data.Page == 0) {
+      SocketTablePtr = (AMD_CPU_BRAND *)&EngSample_Str;
+    } else {
+      SocketTablePtr = (AMD_CPU_BRAND *)&TtkSample_Str;
+    }
+  } else {
+
+    // Model is not equal to zero, so decrement it
+    // For family 10 if PkgType[3:0] is greater than or equal to 2h and families >= 12h
+    GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+    if ((((CpuLogicalId.Family & AMD_FAMILY_10) != 0) && (Data.Socket >= DR_SOCKET_S1G3)) ||
+        ((CpuLogicalId.Family & AMD_FAMILY_GE_12) != 0)) {
+      Data.Model--;
+    }
+
+    // Step5: Search for String1 (there can be only 1)
+    FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (CONST VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
+    SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
+    for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
+         && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
+      if (*SocketTableEntry1 == NULL) {
+        break;
+      }
+      SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table;
+      TableElements = (*SocketTableEntry1)->NumberOfEntries;
+      for (SocketIndex = 0; (SocketIndex < TableElements)
+           && SuffixStatus == 0; SocketIndex++) {
+        if ((SocketTablePtr->Page == Data.Page) &&
+            (SocketTablePtr->Index == Data.String1) &&
+            (SocketTablePtr->Socket == Data.Socket) &&
+            (SocketTablePtr->Cores == Data.Cores)) {
+          SuffixStatus = 1;
+        } else {
+          SocketTablePtr++;
+        }
+      }
+    }
+    if (SuffixStatus == 0) {
+      SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str1;  // We did not find one, make 'Unknown'
+    }
+  }
+
+  // Step6: Copy String into NameBuffer
+  // We now have data structure pointing to correct type in (*SocketTablePtr)
+  LibAmdMemCopy  (BrandStringPtr,
+                  (CHAR8 *)SocketTablePtr->Stringstart,
+                  SocketTablePtr->Stringlength,
+                  StdHeader);
+
+  // Step7: Get suffix, determine addition to BRANDSPEED
+  if (SuffixStatus != 0) {
+    // Turn our value into a decimal string
+    // We have a value like 37d which we need to turn into '3' '7'
+    // Divide by 10, store remainder as an ASCII char on stack, repeat until Quotient is 0
+    NameStringPtr = BrandStringPtr + SocketTablePtr->Stringlength - 1;
+    TempNameCharPtr = NameStringPtr;
+    Quotient = Data.Model;
+    do {
+      Remainder = Quotient % 10;
+      Quotient = Quotient / 10;
+      *TempNameCharPtr++ = (CHAR8) (Remainder + '0');   // Put suffix into our NameBuffer
+    } while (Quotient != 0);
+    if (Data.Model < 10) {
+      *TempNameCharPtr++ = '0';
+    }
+
+    // Step8: Reverse the string sequence and copy into NameBuffer
+    SuffixStringPtr = TempNameCharPtr--;
+    while (NameStringPtr < TempNameCharPtr) {
+      TempChar = *NameStringPtr;
+      *NameStringPtr = *TempNameCharPtr;
+      *TempNameCharPtr = TempChar;
+      NameStringPtr++;
+      TempNameCharPtr--;
+    }
+
+    // Step9: Search for String2
+    SuffixStatus = 0;
+    FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (CONST VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
+    SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
+    for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
+         && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
+      if (*SocketTableEntry1 == NULL) {
+        break;
+      }
+      SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table;
+      TableElements = (*SocketTableEntry1)->NumberOfEntries;
+      for (SocketIndex = 0; (SocketIndex < TableElements)
+           && SuffixStatus == 0; SocketIndex++) {
+        if ((SocketTablePtr->Page == Data.Page) &&
+            (SocketTablePtr->Index == Data.String2) &&
+            (SocketTablePtr->Socket == Data.Socket) &&
+            (SocketTablePtr->Cores == Data.Cores)) {
+          SuffixStatus = 1;
+        } else {
+          SocketTablePtr++;
+        }
+      }
+    }
+    if (SuffixStatus == 0) {
+      SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str2;
+    }
+
+    // Step10: Copy String2 into our NameBuffer
+    if (SocketTablePtr->Stringlength != 0) {
+      LibAmdMemCopy (SuffixStringPtr,
+                      (CHAR8 *)SocketTablePtr->Stringstart,
+                      SocketTablePtr->Stringlength,
+                      StdHeader);
+    }
+  }
+
+  // Step11: Put values into name MSRs,  Always write the full 48 bytes
+  MsrNameStringPtrPtr = (UINT64 *) BrandStringPtr;
+  for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
+    LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
+    MsrNameStringPtrPtr++;
+  }
+  HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Program BrandID registers (CPUIDNameStringPtr[0-5])
+ *
+ * This function acts as a wrapper for calling the SetBrandIdRegisters
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuSetBrandID, StdHeader);
+  SetBrandIdRegisters (StdHeader);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c
new file mode 100755
index 0000000000..905fa01fef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.c
@@ -0,0 +1,363 @@
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "Table.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "Topology.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUEARLYINIT_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+McaInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by AmdCpuEarly to initialize the input
+ * structure for the Cpu Init @ Early routine.
+ *
+ * @param[in]       StdHeader         Opaque handle to standard config header
+ * @param[in]       PlatformConfig    Config handle for platform specific information
+ * @param[in,out]   CpuEarlyParamsPtr Service Interface structure to initialize.
+ *
+ * @retval          AGESA_SUCCESS     Always Succeeds
+ */
+STATIC VOID
+AmdCpuEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr
+  )
+{
+  ASSERT (CpuEarlyParamsPtr != NULL);
+
+  CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
+  CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the early entry point
+ *
+ * This function performs a large list of initialization items.  These items
+ * include:
+ *
+ *    -1      local APIC initialization
+ *    -2      MSR table initialization
+ *    -3      PCI table initialization
+ *    -4      HT Phy PCI table initialization
+ *    -5      microcode patch loading
+ *    -6      namestring determination/programming
+ *    -7      AP initialization
+ *    -8      power management initialization
+ *    -9      core leveling
+ *
+ * This routine must be run by all cores in the system.  Please note that
+ * all APs that enter will never exit.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  PlatformConfig    Config handle for platform specific information
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+AmdCpuEarly (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  )
+{
+  UINT8         WaitStatus;
+  UINT8         i;
+  UINT8         j;
+  UINT8         StartCore;
+  UINT8         EndCore;
+  UINT32        NodeNum;
+  UINT32        PrimaryCore;
+  UINT32        SocketNum;
+  UINT32        ModuleNum;
+  UINT32        HighCore;
+  UINT32        ApHeapIndex;
+  AP_WAIT_FOR_STATUS WaitForStatus;
+  AGESA_STATUS  Status;
+  AGESA_STATUS  CalledStatus;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+  PF_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore;
+
+  Status = AGESA_SUCCESS;
+  CalledStatus = AGESA_SUCCESS;
+
+  AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams);
+  ASSERT (CpuEarlyParams.PlatformConfig.VrmProperties.CurrentLimit >= CpuEarlyParams.PlatformConfig.VrmProperties.LowPowerThreshold);
+
+  IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader);
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  EarlyTableOnCore = NULL;
+  FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (CONST PF_PERFORM_EARLY_INIT_ON_CORE  **)&EarlyTableOnCore, &CpuEarlyParams, StdHeader);
+  if (EarlyTableOnCore != NULL) {
+    for (i = 0; EarlyTableOnCore[i] != NULL; i++) {
+      EarlyTableOnCore[i] (FamilySpecificServices, &CpuEarlyParams, StdHeader);
+    }
+  }
+
+  // B S P    C O D E    T O    I N I T I A L I Z E    A Ps
+  // -------------------------------------------------------
+  // -------------------------------------------------------
+  // IMPORTANT: Here we determine if we are BSP or AP
+  if (IsBsp (StdHeader, &CalledStatus)) {
+
+    // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization.
+    // Use '0' as a dummy heap index value.
+    GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader);
+    GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader);
+    FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader);
+    FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader);
+
+    // Clear BSP's Status Byte
+    ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
+
+    NodeNum = 1;
+    ApHeapIndex = 1;
+    for (i = 0; i < 2; i++) {
+      while (NodeNum < MAX_NODES &&
+             GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) {
+        GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader);
+        GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader);
+        if (i == 0) {
+          StartCore = (UINT8) PrimaryCore;
+          EndCore = (UINT8) PrimaryCore;
+        } else {
+          StartCore = (UINT8) PrimaryCore + 1;
+          EndCore = (UINT8) HighCore;
+        }
+        for (j = StartCore; j <= EndCore; j++) {
+          FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader);
+          if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, j, PrimaryCore, StdHeader)) {
+            WaitStatus = CORE_IDLE;
+            WaitForStatus.Status = &WaitStatus;
+            WaitForStatus.NumberOfElements = 1;
+            WaitForStatus.RetryCount = WAIT_INFINITELY;
+            WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
+            ApUtilWaitForCoreStatus (
+                                      (UINT8) SocketNum,
+                                      j,
+                                      &WaitForStatus,
+                                      StdHeader
+                                      );
+            ApHeapIndex++;
+          }
+        }
+        NodeNum++;
+      }
+      NodeNum = 0;
+    }
+
+    // B S P    P h a s e - 1   E N D
+    AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader);
+    CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader);
+    if (CalledStatus > Status) {
+      Status = CalledStatus;
+    }
+
+    AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader);
+    CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader);
+
+    // Sleep all APs
+    ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader);
+  } // if (amdIsBsp()) - END
+  else {
+    ApEntry (StdHeader, &CpuEarlyParams);
+  }
+
+  if (CalledStatus > Status) {
+    Status = CalledStatus;
+  }
+
+  return (Status);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize Machine Check Architecture registers
+ *
+ * This function initializes the MCA MSRs.  On cold reset, these registers
+ * have an invalid data that must be cleared on all cores.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *---------------------------------------------------------------------------------------
+ */
+STATIC VOID
+McaInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16      TempVar16_a;
+  UINT32      MsrAddress;
+  UINT64      MsrData;
+  CPUID_DATA  CpuIdDataStruct;
+
+  if (!(IsWarmReset (StdHeader))) {
+    // Run CPUID to verify that the processor supports MCE and MCA
+    // i.e. edx[7], and edx[14]
+    // CPUID_MODEL = 1
+    LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader);
+    if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) {
+      // Check to see if the MCG_CTL_P bit is set
+      // MCG = Global Machine Check Exception Reporting Control Register
+      LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
+      if ((MsrData & MCG_CTL_P) != 0) {
+        TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2);
+        TempVar16_a += MSR_MC0_CTL;
+
+        // Initialize the data
+        MsrData = 0;
+        for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) {
+          LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize Machine Check Architecture registers
+ *
+ * This function acts as a wrapper for calling the McaInitialization
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+McaInitializationAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  McaInitialization (StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the given task on all cores (including self) on the socket of the executing
+ * core 0.
+ *
+ * This function is used to invoke all APs on the socket of the executing core 0 to
+ * run a specified AGESA procedure.
+ *
+ * @param[in]  TaskPtr      Function descriptor
+ * @param[in]  StdHeader    Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+ApUtilRunCodeOnAllLocalCoresAtEarly (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  UINT32 Core;
+  UINT32 Socket;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  UINT32 ActiveCores;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+  GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
+
+  for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+    ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader);
+  }
+  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h
new file mode 100755
index 0000000000..48c7961fbf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEarlyInit.h
@@ -0,0 +1,228 @@
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_EARLY_INIT_H_
+#define _CPU_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+typedef struct _CPU_CORE_LEVELING_FAMILY_SERVICES CPU_CORE_LEVELING_FAMILY_SERVICES;
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+#define CPU_BRAND_ID_LENGTH     48            // Total number of characters supported
+#define LOW_NODE_DEVICEID       24
+#define NB_CAPABILITIES         0xE8          //Function 3 Registers
+//----------------------------------------------------------------------------
+//                         CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/* All lengths are in bytes */
+#define MICROCODE_TRIADE_SIZE           28
+#define MICROCODE_HEADER_LENGTH         64
+
+/* Offsets in UCODE PATCH Header */
+/* Note: Header is 64 bytes      */
+#define DATE_CODE_OFFSET                0   // 4 bytes
+#define PATCH_ID                        4   // 4 bytes
+#define MICROCODE_PATH_DATA_ID          8   // 2 bytes
+#define MICROCODE_PATCH_DATA_LENGTH     10  // 1 byte
+#define MICROCODE_PATCH_DATA_CHECKSUM   12  // 4 bytes
+#define CHIPSET_1_DEVICE_ID             16  // 4 bytes
+#define CHIPSET_2_DEVICE_ID             20  // 4 bytes
+#define PROCESSOR_REV_ID                24  // 2 bytes
+#define CHIPSET_1_REV_ID                26  // 1 byte
+#define CHIPSET_2_REV_ID                27  // 1 byte
+
+#define MICROCODE_PATCH_SIZE    2048
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// A structure representing BrandId[15:0] from
+/// CPUID Fn8000_0001_EBX
+typedef struct {
+  UINT8           String1:4;   ///< An index to a string value used to create the name string
+  UINT8           String2:4;   ///< An index to a string value used to create the name string
+  UINT8           Page:1;      ///< An index to the appropriate page for the String1, String2, and Model values
+  UINT8           Model:7;     ///< A field used to create the model number in the name string
+  UINT8           Socket:4;    ///< Specifies the package type
+  UINT8           Cores:4;     ///< Identifies how many physical cores are present
+} AMD_CPU_BRAND_DATA;
+
+/// A structure containing string1 and string2 values
+/// as well as information pertaining to their usage
+typedef struct {
+  IN       UINT8  Cores;              ///< Appropriate number of physical cores
+  IN       UINT8  Page;               ///< This string's page number
+  IN       UINT8  Index;              ///< String index
+  IN       UINT8  Socket;             ///< Package type information
+  IN       CONST CHAR8 *Stringstart;  ///< The literal string
+  IN       UINT8  Stringlength;       ///< Number of characters in the string
+} AMD_CPU_BRAND;
+
+/// An entire CPU brand table.
+typedef struct {
+  UINT8 NumberOfEntries;        ///< The number of entries in the table.
+  CONST AMD_CPU_BRAND  *Table;  ///< The table entries.
+} CPU_BRAND_TABLE;
+
+//----------------------------------------------------------------------------
+//                         CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Microcode patch field definitions
+typedef struct {
+  UINT32   DateCode;                   ///< Date of patch creation
+  UINT32   PatchID;                    ///< Patch level
+  UINT16   MicrocodePatchDataID;       ///< Internal use only
+  UINT8    MicrocodePatchDataLength;   ///< Internal use only
+  UINT8    InitializationFlag;         ///< Internal use only
+  UINT32   MicrocodePatchDataChecksum; ///< Doubleword sum of data block
+  UINT32   Chipset1DeviceID;           ///< Device ID of 1st HT device to match
+  UINT32   Chipset2DeviceID;           ///< Device ID of 2nd HT device to match
+  UINT16   ProcessorRevisionID;        ///< Equivalent ID
+  UINT8    Chipset1RevisionID;         ///< Revision level of 1st HT device to match
+  UINT8    Chipset2RevisionID;         ///< Revision level of 2nd HT device to match
+  UINT8    BiosApiRevision;            ///< BIOS INT 15 API revision required
+  UINT8    Reserved1[3];               ///< Reserved
+  UINT32   MatchRegister0;             ///< Internal use only
+  UINT32   MatchRegister1;             ///< Internal use only
+  UINT32   MatchRegister2;             ///< Internal use only
+  UINT32   MatchRegister3;             ///< Internal use only
+  UINT32   MatchRegister4;             ///< Internal use only
+  UINT32   MatchRegister5;             ///< Internal use only
+  UINT32   MatchRegister6;             ///< Internal use only
+  UINT32   MatchRegister7;             ///< Internal use only
+  UINT8    PatchDataBlock[896];        ///< Raw patch data
+  UINT8    Reserved2[896];             ///< Reserved
+  UINT8    X86CodePresent;             ///< Boolean to determine if executable code exists
+  UINT8    X86CodeEntry[191];          ///< Code to execute if X86CodePresent != 0
+} MICROCODE_PATCH;
+
+/// Two kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+  IN       UINT8   MicrocodePatches[MICROCODE_PATCH_SIZE];  ///< 2k UINT8 elements
+} MICROCODE_PATCHES;
+
+/**
+ *  Set down core register
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices  The current Family Specific Services.
+ * @param[in]      Socket        Socket ID.
+ * @param[in]      Module        Module ID in socket.
+ * @param[in]      LeveledCores  Number of core.
+ * @param[in]      StdHeader     Header for library and services.
+ *
+ */
+typedef VOID (F_CPU_SET_DOWN_CORE_REGISTER) (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES  *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
+
+/**
+ * Provide the interface to the Core Leveling Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CORE_LEVELING_FAMILY_SERVICES {
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister;    ///< Method: Set down core register.
+};
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+//                   These are   P U B L I C   functions, used by IBVs
+AGESA_STATUS
+AmdCpuEarly (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  );
+
+//                   These are   P U B L I C   functions, used by AGESA
+VOID
+SetBrandIdRegisters (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+PmInitializationAtEarly (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+BOOLEAN
+LoadMicrocodePatch (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _CPU_EARLY_INIT_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEnvInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEnvInit.h
new file mode 100755
index 0000000000..9d73d8f4cb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEnvInit.h
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * AMD CPU Env Init API functions Prototypes.
+ *
+ * Contains code for doing any Env CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 8361 $   @e \$Date: 2008-09-19 21:22:28 +0800 (Fri, 19 Sep 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_ENV_INIT_H_
+#define _CPU_ENV_INIT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+// HobTransfer
+AGESA_STATUS
+CopyHeapToMainRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif // _CPU_ENV_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c
new file mode 100755
index 0000000000..2d296d2d21
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c
@@ -0,0 +1,379 @@
+/**
+ * @file
+ *
+ * AMD Event (Error) Log APIs, and related functions.
+ *
+ * Contains code that records and returns the events and errors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUEVENTLOG_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define TOTAL_EVENT_LOG_BUFFERS  16
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * A wrapper for each Event Log entry.
+ */
+typedef struct {
+  UINT16      Count;         ///< Entry number
+  AGESA_EVENT AgesaEvent;    ///< The entry itself.
+} AGESA_EVENT_STRUCT;
+
+/**
+ * The Event Log.
+ */
+typedef struct {
+  UINT16        ReadWriteFlag;   ///< Read Write flag.
+  UINT16        Count;           ///< The total number of active entries.
+  UINT16        ReadRecordPtr;   ///< The next entry to read.
+  UINT16        WriteRecordPtr;  ///< The next entry to write.
+  AGESA_EVENT_STRUCT AgesaEventStruct[TOTAL_EVENT_LOG_BUFFERS];   ///< The entries.
+} AGESA_STRUCT_BUFFER;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetEventLogHeapPointer (
+     OUT  AGESA_STRUCT_BUFFER **EventLog,
+  IN      AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * External AGESA interface to read an Event from the Event Log.
+ *
+ * This is the implementation of the external AGESA interface entry, as a thin wrapper
+ * around the internal log services.
+ *
+ * @param[in]  Event           The event class, id, and any associated data.
+ *
+ * @retval     AGESA_SUCCESS   Always Succeeds.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+  )
+{
+  AGESA_EVENT  LogEvent;
+  AGESA_STATUS Status;
+
+  AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader);
+
+  ASSERT (Event != NULL);
+  Status = GetEventLog (&LogEvent, &Event->StdHeader);
+
+  Event->EventClass = LogEvent.EventClass;
+  Event->EventInfo = LogEvent.EventInfo;
+  Event->DataParam1 = LogEvent.DataParam1;
+  Event->DataParam2 = LogEvent.DataParam2;
+  Event->DataParam3 = LogEvent.DataParam3;
+  Event->DataParam4 = LogEvent.DataParam4;
+
+  AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader);
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function prepares the Event Log for use.
+ *
+ * Allocate the memory for an event log on the heap.  Set the read pointer, write pointer,
+ * and count to reflect the log is empty.
+ *
+ * @param[in]  StdHeader      Our configuration, for passing to services.
+ *
+ * @retval      AGESA_SUCCESS     The event log is initialized.
+ * @retval      AGESA_ERROR       Allocate Heap Buffer returned an error.
+ *
+ */
+AGESA_STATUS
+EventLogInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS  AllocateHeapParams;
+  AGESA_STRUCT_BUFFER   *AgesaEventAlloc;
+  AGESA_STATUS          Status;
+
+  AllocateHeapParams.BufferHandle = EVENT_LOG_BUFFER_HANDLE;
+  AllocateHeapParams.RequestedBufferSize = sizeof (AGESA_STRUCT_BUFFER);
+  AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader);
+  AgesaEventAlloc = (AGESA_STRUCT_BUFFER *) AllocateHeapParams.BufferPtr;
+  AgesaEventAlloc->Count = 0;
+  AgesaEventAlloc->ReadRecordPtr = 0;
+  AgesaEventAlloc->WriteRecordPtr = 0;
+  AgesaEventAlloc->ReadWriteFlag = 1;
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function logs AGESA events into the event log.
+ *
+ * It will put the information in a circular buffer consisting of 16 such log
+ * entries. If the buffer gets full, then the next event log entry will be written
+ * over the oldest event log entry.
+ *
+ * @param[in]   EventClass   The severity of the event, its associated AGESA_STATUS.
+ * @param[in]   EventInfo    Uniquely identifies the event.
+ * @param[in]   DataParam1   Event specific additional data
+ * @param[in]   DataParam2   Event specific additional data
+ * @param[in]   DataParam3   Event specific additional data
+ * @param[in]   DataParam4   Event specific additional data
+ * @param[in]   StdHeader    Header for library and services
+ *
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 Index;
+  AGESA_STRUCT_BUFFER *AgesaEventAlloc;
+
+  AgesaEventAlloc = NULL;
+  GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
+  ASSERT (AgesaEventAlloc != NULL);
+  Index = AgesaEventAlloc->WriteRecordPtr;
+
+  // Add the new event log data into a circular buffer
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass = EventClass;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo  = EventInfo;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1 = DataParam1;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2 = DataParam2;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3 = DataParam3;
+  AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4 = DataParam4;
+
+ if ((AgesaEventAlloc->WriteRecordPtr == AgesaEventAlloc->ReadRecordPtr) &&
+             (AgesaEventAlloc->ReadWriteFlag == 0)) {
+    AgesaEventAlloc->WriteRecordPtr += 1;
+    AgesaEventAlloc->ReadRecordPtr += 1;
+    if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) {
+      AgesaEventAlloc->WriteRecordPtr = 0;
+      AgesaEventAlloc->ReadRecordPtr  = 0;
+    }
+  } else {
+    AgesaEventAlloc->WriteRecordPtr += 1;
+    if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) {
+      AgesaEventAlloc->WriteRecordPtr = 0;
+    }
+    AgesaEventAlloc->ReadWriteFlag = 0;
+  }
+  AgesaEventAlloc->Count = AgesaEventAlloc->Count + 1;
+
+  if (AgesaEventAlloc->Count <= TOTAL_EVENT_LOG_BUFFERS) {
+    AgesaEventAlloc->AgesaEventStruct[Index].Count = Index;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function gets event logs from the circular buffer.
+ *
+ * It will read the oldest entry from the circular buffer and place that information to the structure
+ * pointed to by the parameter. The read pointers will be incremented to remove the entry from buffer
+ * so that a subsequent call will return the next entry from the buffer. If the buffer is empty the
+ * returned log event will have EventInfo zero, which is not a valid event id.
+ *
+ * @param[out]  EventRecord    The next log event.
+ * @param[in]   StdHeader    Header for library and services
+ *
+ * @retval      AGESA_SUCCESS     Always succeeds.
+ *
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 Index;
+  AGESA_STRUCT_BUFFER *AgesaEventAlloc;
+
+  AgesaEventAlloc = NULL;
+
+  GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
+  ASSERT (AgesaEventAlloc != NULL);
+
+  if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) &&
+      (AgesaEventAlloc->ReadWriteFlag == 1)) {
+    // EventInfo == zero, means no more data.
+    LibAmdMemFill (EventRecord, 0, sizeof (AGESA_EVENT), StdHeader);
+  } else {
+    Index = AgesaEventAlloc->ReadRecordPtr;
+    EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass;
+    EventRecord->EventInfo  = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo;
+    EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1;
+    EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2;
+    EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3;
+    EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4;
+    if (AgesaEventAlloc->ReadRecordPtr == (TOTAL_EVENT_LOG_BUFFERS - 1)) {
+      AgesaEventAlloc->ReadRecordPtr = 0;
+    } else {
+      AgesaEventAlloc->ReadRecordPtr = AgesaEventAlloc->ReadRecordPtr + 1;
+    }
+    if (AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) {
+      AgesaEventAlloc->ReadWriteFlag = 1;
+    }
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function gets event logs from the circular buffer without flushing the entry.
+ *
+ * It will read the desired entry from the circular buffer and place that information to the structure
+ * pointed to by the parameter. The read pointers will not be incremented to remove the entry from the
+ * buffer. If the buffer is empty, or the desired entry does not exist, FALSE will be returned.
+ *
+ * @param[out]  EventRecord  The next log event.
+ * @param[in]   Index        Zero-based unread entry index
+ * @param[in]   StdHeader    Header for library and services
+ *
+ * @retval      TRUE         Entry exists
+ * @retval      FALSE        Entry does not exist
+ *
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 ActualIndex;
+  UINT16 UnreadEntries;
+  AGESA_STRUCT_BUFFER *AgesaEventAlloc;
+
+  AgesaEventAlloc = NULL;
+
+  GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
+  ASSERT (AgesaEventAlloc != NULL);
+
+  if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) &&
+      (AgesaEventAlloc->ReadWriteFlag == 1)) {
+    // EventInfo == zero, means no more data.
+    return FALSE;
+  }
+  if (AgesaEventAlloc->ReadRecordPtr < AgesaEventAlloc->WriteRecordPtr) {
+    UnreadEntries = AgesaEventAlloc->WriteRecordPtr - AgesaEventAlloc->ReadRecordPtr;
+  } else {
+    UnreadEntries = TOTAL_EVENT_LOG_BUFFERS - (AgesaEventAlloc->ReadRecordPtr - AgesaEventAlloc->WriteRecordPtr);
+  }
+  if (Index >= UnreadEntries) {
+    return FALSE;
+  }
+  ActualIndex = Index + AgesaEventAlloc->ReadRecordPtr;
+  if (ActualIndex >= TOTAL_EVENT_LOG_BUFFERS) {
+    ActualIndex -= TOTAL_EVENT_LOG_BUFFERS;
+  }
+
+  EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventClass;
+  EventRecord->EventInfo  = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventInfo;
+  EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam1;
+  EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam2;
+  EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam3;
+  EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam4;
+
+  return TRUE;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function gets the Event Log pointer.
+ *
+ * It will locate the Event Log on the heap using the heap locate service.  If the Event
+ * Log is not located, NULL is returned.
+ *
+ * @param[out]  EventLog  Pointer to the Event Log, or NULL.
+ * @param[in]   StdHeader Our Configuration, for passing to services.
+ *
+ */
+VOID
+STATIC
+GetEventLogHeapPointer (
+     OUT   AGESA_STRUCT_BUFFER **EventLog,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateHeapStruct;
+
+  LocateHeapStruct.BufferHandle = EVENT_LOG_BUFFER_HANDLE;
+  LocateHeapStruct.BufferPtr = NULL;
+  HeapLocateBuffer (&LocateHeapStruct, StdHeader);
+  *EventLog = (AGESA_STRUCT_BUFFER *)LocateHeapStruct.BufferPtr;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c
new file mode 100755
index 0000000000..207af8457a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.c
@@ -0,0 +1,481 @@
+/**
+ * @file
+ *
+ * AMD CPU Family Translation functions.
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Interface
+ * @e \$Revision: 6155 $   @e \$Date: 2008-05-27 04:48:33 -0500 (Tue, 27 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "CommonReturns.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUFAMILYTRANSLATION_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuNullServices =
+{
+  0,
+  (PF_CPU_GET_PSTATE_POWER) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_PSTATE_FREQ) CommonReturnAgesaSuccess,
+  (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess,
+  (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+  (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess,
+  (PF_CPU_PSTATE_TRANSITION_LATENCY) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_PSTATE_REGISTER_INFO) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_PSTATE_MAX_STATE) CommonReturnAgesaSuccess,
+  (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_NB_FREQ) CommonReturnAgesaSuccess,
+  (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess,
+  (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse,
+  (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
+  (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess,
+  (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+  (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnZero32,
+  (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+  (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess,
+  (PF_CPU_SAVE_FEATURES) CommonReturnAgesaSuccess,
+  (PF_CPU_WRITE_FEATURES) CommonReturnAgesaSuccess,
+  (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess,
+  (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  GetEmptyArray,
+  (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+  (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+  (PF_DOES_LINK_HAVE_HTFPY_FEATS) CommonReturnFalse,
+  (PF_SET_HT_PHY_REGISTER) CommonVoid,
+  (PF_GET_HT_LINK_FEATURES) CommonVoid,
+  NULL,
+  NULL,
+  NULL,
+  (PF_GET_EARLY_INIT_TABLE) CommonVoid
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetCpuServices (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT64            *MatchData,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
+extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Returns the logical ID of the desired processor. This will be obtained by
+ *  reading the CPUID and converting it into a "logical ID" which is not package
+ *  dependent.
+ *
+ *  @param[in]      Socket             Socket
+ *  @param[out]     LogicalId          The Processor's Logical ID
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetLogicalIdOfSocket (
+  IN       UINT32 Socket,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32      RawCpuid;
+  PCI_ADDR    PciAddress;
+  AGESA_STATUS AssumedSuccess;
+
+  RawCpuid = 0;
+
+  if (GetPciAddress (StdHeader, (UINT8)Socket, 0, &PciAddress, &AssumedSuccess)) {
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = CPUID_FMR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RawCpuid, StdHeader);
+    GetLogicalIdFromCpuid (RawCpuid, LogicalId, StdHeader);
+  } else {
+    LogicalId->Family = 0;
+    LogicalId->Revision = 0;
+    // Logical ID was not found.
+    IDS_ERROR_TRAP;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Returns the logical ID of the executing core. This will be obtained by reading
+ *  the CPUID and converting it into a "logical ID" which is not package dependent.
+ *
+ *  @param[out]     LogicalId          The Processor's Logical ID
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetLogicalIdOfCurrentCore (
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader);
+  GetLogicalIdFromCpuid (CpuidDataStruct.EAX_Reg, LogicalId, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Returns the logical ID of a processor with the given CPUID value. This
+ *  will be obtained by converting it into a "logical ID" which is not package
+ *  dependent.
+ *
+ *  @param[in]      RawCpuid           The unprocessed CPUID value to be translated
+ *  @param[out]     LogicalId          The Processor's Logical ID
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services
+ *
+ */
+VOID
+GetLogicalIdFromCpuid (
+  IN       UINT32 RawCpuid,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8       i;
+  UINT8       k;
+  UINT8       NumberOfFamiliesSupported;
+  UINT8       NumberOfLogicalSubFamilies;
+  UINT8       LogicalIdEntries;
+  UINT32      j;
+  UINT32      RawFamily;
+  UINT32      CpuModelAndExtendedModel;
+  UINT64      LogicalFamily;
+  BOOLEAN     IdNotFound;
+  BOOLEAN     FamilyNotFound;
+  CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdPtr;
+  CPU_LOGICAL_ID_XLAT *CpuLogicalIdAndRevPtr;
+  CONST CPU_LOGICAL_ID_FAMILY_XLAT *ImageSupportedId;
+
+  IdNotFound = TRUE;
+  FamilyNotFound = TRUE;
+  CpuLogicalIdAndRevPtr = NULL;
+  ImageSupportedId = CpuSupportedFamilyIdTable.FamilyIdTable;
+  NumberOfFamiliesSupported = CpuSupportedFamilyIdTable.Elements;
+
+  RawFamily = ((RawCpuid & 0xF00) >> 8) + ((RawCpuid & 0xFF00000) >> 20);
+  RawCpuid &= (UINT32) CPU_FMS_MASK;
+  CpuModelAndExtendedModel = (UINT16) ((RawCpuid >> 8) | RawCpuid);
+
+  LogicalId->Family = 0;
+  LogicalId->Revision = 0;
+
+  for (i = 0; i < NumberOfFamiliesSupported && FamilyNotFound; i++) {
+    if (ImageSupportedId[i].Family == RawFamily) {
+      FamilyNotFound = FALSE;
+      LogicalId->Family = ImageSupportedId[i].UnknownRevision.Family;
+      LogicalId->Revision = ImageSupportedId[i].UnknownRevision.Revision;
+
+      NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements;
+      SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable;
+      for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) {
+        SubFamilyIdPtr[j] ((CONST CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader);
+        ASSERT (CpuLogicalIdAndRevPtr != NULL);
+        for (k = 0; k < LogicalIdEntries; k++) {
+          if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) {
+            IdNotFound = FALSE;
+            LogicalId->Family = LogicalFamily;
+            LogicalId->Revision = CpuLogicalIdAndRevPtr[k].LogicalId;
+            break;
+          }
+        }
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ *
+ *  @param[in]      Socket             The Processor in this Socket.
+ *  @param[out]     FunctionTable      The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetCpuServicesOfSocket (
+  IN       UINT32 Socket,
+  OUT      CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable,
+                              Socket,
+                              (CONST VOID **)FunctionTable,
+                              StdHeader);
+  if (*FunctionTable == NULL) {
+    *FunctionTable = (CPU_SPECIFIC_SERVICES *)&cpuNullServices;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[in]      Socket             The Processor in this Socket.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetFeatureServicesOfSocket (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT32            Socket,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID CpuFamilyRevision;
+
+  GetLogicalIdOfSocket (Socket, &CpuFamilyRevision, StdHeader);
+  GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the executing core's family specific services structure.
+ *
+ *  @param[out]     FunctionTable      The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetCpuServicesOfCurrentCore (
+  OUT      CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable,
+                                   (CONST VOID **)FunctionTable,
+                                   StdHeader);
+  if (*FunctionTable == NULL) {
+    *FunctionTable = (CPU_SPECIFIC_SERVICES *)&cpuNullServices;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetFeatureServicesOfCurrentCore (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID CpuFamilyRevision;
+
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ *
+ *  @param[in]      LogicalId          The Processor's logical ID.
+ *  @param[out]     FunctionTable      The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetCpuServicesFromLogicalId (
+  IN       CPU_LOGICAL_ID *LogicalId,
+  OUT      CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable,
+                                   LogicalId,
+                                   (CONST VOID **)FunctionTable,
+                                   StdHeader);
+  if (*FunctionTable == NULL) {
+    *FunctionTable = (CPU_SPECIFIC_SERVICES *)&cpuNullServices;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[in]      LogicalId          The Processor's logical ID.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetFeatureServicesFromLogicalId (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       CPU_LOGICAL_ID    *LogicalId,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetCpuServices (FamilyTable, &LogicalId->Family, CpuServices, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Finds a family match in the given table, and returns the pointer to the
+ *  appropriate table.  If no match is found in the table, NULL will be returned.
+ *
+ *  @param[in]      FamilyTable        The table to search in.
+ *  @param[in]      MatchData          Family data that must match.
+ *  @param[out]     CpuServices        The Processor's Family Specific services.
+ *  @param[in]      StdHeader          Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+STATIC
+GetCpuServices (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT64            *MatchData,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN IsFamily;
+  UINT8   i;
+  UINT8   NumberOfFamiliesSupported;
+  CONST CPU_SPECIFIC_SERVICES_XLAT *ImageSupportedFamiliesPtr;
+
+  ImageSupportedFamiliesPtr = FamilyTable->FamilyTable;
+  NumberOfFamiliesSupported = FamilyTable->Elements;
+  IsFamily = FALSE;
+  for (i = 0; i < NumberOfFamiliesSupported; i++) {
+    if ((ImageSupportedFamiliesPtr[i].Family & *MatchData) != 0) {
+      IsFamily = TRUE;
+      break;
+    }
+  }
+  if (IsFamily) {
+    *CpuServices = ImageSupportedFamiliesPtr[i].TablePtr;
+  } else {
+    *CpuServices = NULL;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Used to stub out various family specific tables of information.
+ *
+ *  @param[in]      FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]      Empty                   NULL, to indicate no data.
+ *  @param[out]     NumberOfElements        Zero, to indicate no data.
+ *  @param[in]      StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+GetEmptyArray (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   CONST VOID **Empty,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 0;
+  *Empty = NULL;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
new file mode 100755
index 0000000000..d34d4dac57
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuFamilyTranslation.h
@@ -0,0 +1,1030 @@
+/**
+ * @file
+ *
+ * AMD CPU Family Translation functions.
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6155 $   @e \$Date: 2008-05-27 04:48:33 -0500 (Tue, 27 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FAMILY_TRANSLATION_H_
+#define _CPU_FAMILY_TRANSLATION_H_
+
+/**
+ * @page cpuimplfss CPU Family Specific Services Implementation Guide
+ *
+ * CPU Family Specific Services provides access to supported family service functions and data,
+ * in a manner that isolates calling code from knowledge about particular families or which
+ * families are supported in the current build.
+ *
+ * @par Adding a Method to Family Specific Services
+ *
+ * To add a new method to Family Specific Services, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (*PF_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (*PF_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> [Optionally make the type F_<name> and provide a separate:
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME> </tt> @n
+ *     and provide a single line "///" doxygen comment brief description on the PF_ type.]
+ *   </ul>
+ *
+ * <li> The first parameter to @b all Family Specific Service Methods is @b required to be a reference to
+ *   their Family Service struct.
+ *   @n <tt> IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices </tt> @n
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef.  Begin the
+ *   detailed description by provide a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @CpuServiceInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::CPU_SPECIFIC_SERVICES struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing a Family Specific Instance of the method.
+ *
+ * To implement an instance of a method for a specific family follow these steps.
+ *
+ * - In appropriate files in the family specific directory, implement the method with the return type
+ *   and parameters matching the method typedef.
+ *
+ * - Name the function FnnMethodName(), where nn is the family number.
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @CpuServiceMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other family specific services as part of the method implementation, the function
+ *   @b must use FamilySpecificServices->OtherMethod().  Do not directly call other family specific
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple families.
+ *
+ * - Do @b not call Family translation services from a family specific instance.  Use the parameter.
+ *
+ * - Add the instance to the family specific ::CPU_SPECIFIC_SERVICES instance.
+ *
+ * - If a family does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking Family Specific Services.
+ *
+ * The following example shows how to invoke a family specific method.
+ * @n @code
+ *        CPU_SPECIFIC_SERVICES *FamilyServices;
+ *
+ *        GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ *        ASSERT (FamilyServices != NULL);
+ *        FamilyServices->MethodName (FamilyServices, StdHeader);
+ * @endcode
+ *
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+#include "cpuPostInit.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "Table.h"
+#include "Ids.h"
+#include "Topology.h"
+
+// Forward declaration.
+AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/**
+ *  Get the desired P-state's rated power in milliwatts.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             P-state number.
+ *  @param[out]    PowerInMw               P-state power in milliwatts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_POWER (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_POWER *PF_CPU_GET_PSTATE_POWER;
+
+/**
+ *  Get the desired P-state's frequency in megahertz.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             P-state number.
+ *  @param[out]    PowerInMw               P-state frequency in megahertz.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_FREQ (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FreqInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_FREQ *PF_CPU_GET_PSTATE_FREQ;
+
+/**
+ *  Disable the desired P-state.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             P-state number.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_DISABLE_PSTATE (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE;
+
+/**
+ *  Transition the current core to the desired P-state.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             P-state number.
+ *  @param[in]     WaitForChange           Wait/don't wait for P-state change to complete.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       BOOLEAN WaitForChange,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE;
+
+/**
+ *  Get the desired P-state's maximum current required in milliamps.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StateNumber             The desired P-state number.
+ *  @param[out]    ProcIddMax              The P-state's maximum current.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    The P-state is enabled, and ProcIddMax is valid.
+ *  @retval        FALSE                   The P-state is disabled.
+ *
+ */
+typedef BOOLEAN F_CPU_GET_IDD_MAX (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX;
+
+/**
+ *  Get CPU pstate transition latency for current socket.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[in]     PStateLevelingBufferStructPtr  Pstate row data buffer pointer.
+ *  @param[in]     PciAddress                     Pci address struct.
+ *  @param[out]    TransitionLatency              Pstate Transition latency result.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_PSTATE_TRANSITION_LATENCY (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_PSTATE_TRANSITION_LATENCY *PF_CPU_PSTATE_TRANSITION_LATENCY;
+
+/**
+ *  Get CPU pstate register Informations.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[in]     PState                         Input Pstate number for query.
+ *  @param[out]    PStateEnabled                  Boolean flag return pstate enable.
+ *  @param[in,out] IddVal                         Pstate current value.
+ *  @param[in,out] IddDiv                         Pstate current divisor.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_REGISTER_INFO (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_REGISTER_INFO *PF_CPU_GET_PSTATE_REGISTER_INFO;
+
+/**
+ *  Get CPU Pstate Max State.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[out]    MaxPStateNumber                The value return max pstate value current socket.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PSTATE_MAX_STATE (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32              *MaxPStateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PSTATE_MAX_STATE *PF_CPU_GET_PSTATE_MAX_STATE;
+
+
+/**
+ *  Set the system wide P-state settings on the current core.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     CpuAmdPState            The current core's P-state data.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_SET_PSTATE_LEVELING_REG (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       S_CPU_AMD_PSTATE   *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_SET_PSTATE_LEVELING_REG *PF_CPU_SET_PSTATE_LEVELING_REG;
+
+/**
+ *  Returns the rate at which the current core's timestamp counter increments in megahertz.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    FreqInMHz               The rate at which the TSC increments in megahertz.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_TSC_RATE (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32 *FreqInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE;
+
+/**
+ *  Returns the processor north bridge's clock rate in megahertz.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PciAddress              The PCI address of the node in question.
+ *  @param[out]    FreqInMHz               The desired node's frequency in megahertz.
+ *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_NB_FREQ (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FreqInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ;
+
+/**
+ *  Launches the desired core from the reset vector.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     SocketNumber            The desired core's socket number.
+ *  @param[in]     ModuleNumber            The desired core's die number.
+ *  @param[in]     CoreNumber              The desired core's die relative core number.
+ *  @param[in]     PrimaryCoreNumber       SocketNumber / ModuleNumber's primary core number.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    The core was launched successfully.
+ *  @retval        FALSE                   The core was previously launched, or has a problem.
+ */
+typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32 SocketNumber,
+  IN       UINT32 ModuleNumber,
+  IN       UINT32 CoreNumber,
+  IN       UINT32 PrimaryCoreNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH;
+
+/**
+ *  Returns the appropriate number of processor cores for brandstring detection
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        One-based number of cores on current processor
+ */
+typedef UINT8 F_CPU_NUMBER_OF_BRANDSTRING_CORES (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_NUMBER_OF_BRANDSTRING_CORES *PF_CPU_NUMBER_OF_BRANDSTRING_CORES;
+
+/**
+ *  Returns whether or not the NB frequency initialization sequence is required
+ *  to be performed by the BIOS.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PciAddress              The northbridge to query by pci base address.
+ *  @param[out]    NbVidUpdateAll          Do all NbVids need to be updated as well.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED;
+
+/**
+ *  Returns a family specific table of information pointer and size.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    FamilySpecificArray     Pointer to the appropriate list for the core.
+ *  @param[out]    NumberOfElements        Number of valid entries FamilySpecificArray.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   CONST VOID **FamilySpecificArray,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY;
+
+/**
+ *  Returns a model specific list of logical IDs.
+ *
+ *  @param[out]    LogicalIdXlat           Installed logical ID table.
+ *  @param[out]    NumberOfElements        Number of entries in the Logical ID translate table.
+ *  @param[out]    LogicalFamily           Base logical family bit mask.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_CPU_GET_SUBFAMILY_ID_ARRAY (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **LogicalIdXlat,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a method.
+typedef F_CPU_GET_SUBFAMILY_ID_ARRAY *PF_CPU_GET_SUBFAMILY_ID_ARRAY;
+
+/**
+ *  Use the Mailbox Register to get the Ap Mailbox info for the current core.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    ApMailboxInfo           The AP Mailbox info
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE *PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE;
+
+/**
+ *  Set the AP core number in the AP's Mailbox.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     Socket                  The AP's socket
+ *  @param[in]     Module                  The AP's module
+ *  @param[in]     ApCoreNumber            The AP's unique core number
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_SET_AP_CORE_NUMBER) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32                 Socket,
+  IN       UINT32                 Module,
+  IN       UINT32                 ApCoreNumber,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_SET_AP_CORE_NUMBER *PF_CPU_SET_AP_CORE_NUMBER;
+
+/**
+ *  Get the AP core number from hardware.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_GET_AP_CORE_NUMBER *PF_CPU_GET_AP_CORE_NUMBER;
+
+/**
+ *  Move the AP's core number from the mailbox to hardware.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+typedef VOID (F_CPU_TRANSFER_AP_CORE_NUMBER) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_TRANSFER_AP_CORE_NUMBER *PF_CPU_TRANSFER_AP_CORE_NUMBER;
+
+/**
+ * Core ID position in the initial APIC ID, reflected as a number zero or one.
+ */
+typedef enum {
+  CoreIdPositionZero, ///< Zero, the Core Id bits are the Most Significant bits.
+  CoreIdPositionOne,  ///< One, the Core Id bits are the Least Significant bits.
+  CoreIdPositionMax   ///< Limit check.
+} CORE_ID_POSITION;
+
+/**
+ * Return a number zero or one, based on the Core ID position in the initial APIC Id.
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @retval        CoreIdPositionZero      Core Id is not low
+ * @retval        CoreIdPositionOne       Core Id is low
+ */
+typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID;
+
+/**
+ *  Get least common features set of all CPUs and save them to CPU_FEATURES_LIST
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in,out] cpuFeatureListPtr       The CPU Features List
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_SAVE_FEATURES) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST      *cpuFeatureListPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_SAVE_FEATURES *PF_CPU_SAVE_FEATURES;
+
+/**
+ *  Get least common features from CPU_FEATURES_LIST and write them to CPU
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in,out] cpuFeatureListPtr       The CPU Features List
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_WRITE_FEATURES) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST      *cpuFeatureListPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_CPU_WRITE_FEATURES *PF_CPU_WRITE_FEATURES;
+
+/**
+ *  Set Warm Reset Flag
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices  The current Family Specific Services.
+ * @param[in]      StdHeader     Header for library and services.
+ * @param[in]      Request       Value to set the flags to.
+ *
+ */
+typedef VOID (F_CPU_SET_WARM_RESET_FLAG) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+/// Reference to a method
+typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG;
+
+/**
+ *  Get Warm Reset Flag
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices  The current Family Specific Services.
+ * @param[in]      StdHeader     Header for library and services.
+ * @param[out]     BiosRstDet    Indicate warm reset status.
+ *
+ */
+typedef VOID (F_CPU_GET_WARM_RESET_FLAG) (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  );
+
+/// Reference to a method
+typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG;
+
+
+/**
+ *  Get CPU Specific Platform Type Info.
+ *
+ *  @CpuServiceInstances
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[in,out] FeaturesUnion                  The Features supported by this platform.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ */
+typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PLATFORM_FEATS         *FeaturesUnion,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO;
+
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+typedef BOOLEAN F_IS_NB_PSTATE_ENABLED (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a method
+typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED;
+
+/**
+ * Checks to see if the HT phy register table entry type features match the link features.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]     FamilySpecificServices   The current Family Specific Services.
+ * @param[in]     CapabilitySet    Address of the HT capability block
+ * @param[in]     Link             Zero based HT link to check
+ * @param[in]     HtPhyLinkType    Link type field from a register table entry to compare against
+ * @param[out]    MatchedSublink1  TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
+ * @param[out]    Frequency0       The frequency of sublink0 (200 MHz if not connected).
+ * @param[out]    Frequency1       The frequency of sublink1 (200 MHz if not connected).
+ * @param[in]     StdHeader        Standard Head Pointer
+ *
+ * @retval        TRUE             Link matches
+ * @retval        FALSE            Link does not match
+ *
+ */
+typedef BOOLEAN F_DOES_LINK_HAVE_HTFPY_FEATS (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR           CapabilitySet,
+  IN       UINT32             Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+     OUT   BOOLEAN            *MatchedSublink1,
+     OUT   HT_FREQUENCIES     *Frequency0,
+     OUT   HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+/// Reference to a Method.
+typedef F_DOES_LINK_HAVE_HTFPY_FEATS *PF_DOES_LINK_HAVE_HTFPY_FEATS;
+
+/**
+ * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]  FamilySpecificServices    The current Family Specific Services.
+ * @param[in]  HtPhyEntry                HT Phy register table entry to apply
+ * @param[in]  CapabilitySet             The link's HT Host base address.
+ * @param[in]  Link                      Zero based, node, link number (not package link), always a sublink0 link.
+ * @param[in]  StdHeader                 Config handle for library and services
+ *
+ */
+typedef VOID F_SET_HT_PHY_REGISTER (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                CapabilitySet,
+  IN       UINT32                  Link,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_SET_HT_PHY_REGISTER *PF_SET_HT_PHY_REGISTER;
+
+/**
+ * Performs an early initialization function on the executing core.
+ *
+ * @param[in]  FamilyServices            The current Family Specific Services.
+ * @param[in]  EarlyParams               CPU module early paramters.
+ * @param[in]  StdHeader                 Config handle for library and services
+ *
+ */
+typedef VOID F_PERFORM_EARLY_INIT_ON_CORE (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_PERFORM_EARLY_INIT_ON_CORE *PF_PERFORM_EARLY_INIT_ON_CORE;
+
+/**
+ * Returns the initialization steps that the executing core should
+ * perform at AmdInitEarly.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]  FamilyServices            The current Family Specific Services.
+ * @param[out] Table                     Table of appropriate init steps for the executing core.
+ * @param[in]  EarlyParams               CPU module early paramters.
+ * @param[in]  StdHeader                 Config handle for library and services
+ *
+ */
+typedef VOID F_GET_EARLY_INIT_TABLE (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_EARLY_INIT_TABLE *PF_GET_EARLY_INIT_TABLE;
+
+/**
+ * Provide the features of the given HT link.
+ *
+ *  @CpuServiceInstances
+ *
+ * This method is different than the HT Phy Features method, because for the phy registers
+ * sublink 1 matches and should be programmed if the link is ganged but for PCI config
+ * registers sublink 1 is reserved if the link is ganged.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[out]    Link                      The link number, for accessing non-capability set registers.
+ * @param[in]     LinkBase                  The base HT Host capability PCI address for the link.
+ * @param[out]    HtHostFeats               The link's features.
+ * @param[in]     StdHeader                 Standard Head Pointer
+ */
+typedef VOID F_GET_HT_LINK_FEATURES (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINTN                  *Link,
+  IN       PCI_ADDR               *LinkBase,
+     OUT   HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_HT_LINK_FEATURES *PF_GET_HT_LINK_FEATURES;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the interface to all cpu Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ * See CPU Family Specific Services Implementation Guide for adding new services.
+ */
+struct _CPU_SPECIFIC_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_CPU_GET_PSTATE_POWER GetPstatePower;                               ///< Method: Get the desired P-state's rated power in milliwatts.
+  PF_CPU_GET_PSTATE_FREQ GetPstateFrequency;                            ///< Method: Get the desired P-state's frequency in megahertz.
+  PF_CPU_DISABLE_PSTATE DisablePstate;                                  ///< Method: Disable the desired P-state.
+  PF_CPU_TRANSITION_PSTATE TransitionPstate;                            ///< Method: Transition the current core to the desired P-state.
+  PF_CPU_GET_IDD_MAX GetProcIddMax;                                     ///< Method: Gets P-state maximum current required
+  PF_CPU_GET_TSC_RATE GetTscRate;                                       ///< Method: Returns the rate at which the current core's timestamp counter increments in megahertz.
+  PF_CPU_PSTATE_TRANSITION_LATENCY GetPstateLatency;                    ///< Method: Get pstate transition latency.
+  PF_CPU_GET_PSTATE_REGISTER_INFO GetPstateRegisterInfo;                ///< Method: Get pstate register Informations.
+  PF_CPU_GET_PSTATE_MAX_STATE GetPstateMaxState;                        ///< Method: Get pstate max state number.
+  PF_CPU_SET_PSTATE_LEVELING_REG SetPStateLevelReg;                     ///< Method: Set the system wide P-state settings on the current core.
+  PF_CPU_GET_NB_FREQ GetNbFrequency;                                    ///< Method: Returns the processor north bridge's clock rate in megahertz.
+  PF_CPU_IS_NBCOF_INIT_NEEDED IsNbCofInitNeeded;                        ///< Method: Returns whether or not the NB frequency initialization sequence is required to be performed by the BIOS.
+  PF_CPU_AP_INITIAL_LAUNCH LaunchApCore;                                ///< Method: Launches the desired core from the reset vector.
+  PF_CPU_NUMBER_OF_BRANDSTRING_CORES GetNumberOfCoresForBrandstring;    ///< Method: Get the current core's number of cores used in the brandstring calculation.
+  PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE GetApMailboxFromHardware;     ///< Method: Get the AP's topology info from the hardware mailbox.
+  PF_CPU_SET_AP_CORE_NUMBER SetApCoreNumber;                            ///< Method: Set the AP's core number to the hardware mailbox.
+  PF_CPU_GET_AP_CORE_NUMBER GetApCoreNumber;                            ///< Method: Get the AP's core number from hardware.
+  PF_CPU_TRANSFER_AP_CORE_NUMBER TransferApCoreNumber;                  ///< Method: Move the AP's core number from the mailbox to hardware.
+  PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID CoreIdPositionInInitialApicId; ///< Method: Which bits in initial APIC Id are the Core Id.
+  PF_CPU_SAVE_FEATURES SaveFeatures;                                    ///< Method: Get least common features set of all CPUs and save them to CPU_FEATURES_LIST
+  PF_CPU_WRITE_FEATURES WriteFeatures;                                  ///< Method: Get least common features from CPU_FEATURES_LIST and write them to CPU
+  PF_CPU_SET_WARM_RESET_FLAG SetWarmResetFlag;                          ///< Method: Set Warm Reset Flag
+  PF_CPU_GET_WARM_RESET_FLAG GetWarmResetFlag;                          ///< Method: Get Warm Reset Flag
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString1;                     ///< Method: Get a Brand String table
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString2;                     ///< Method: Get a Brand String table
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicroCodePatchesStruct;           ///< Method: Get microcode patches
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicrocodeEquivalenceTable;        ///< Method: Get CPU equivalence for loading microcode patches.
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetCacheInfo;                        ///< Method: Get setup for cache use and initialization.
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetSysPmTableStruct;                 ///< Method: Get Power Management settings.
+  PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetWheaInitData;                     ///< Method: Get Whea Initial Data.
+  PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO GetPlatformTypeSpecificInfo;   ///< Method: Get Specific platform Type features.
+  PF_IS_NB_PSTATE_ENABLED IsNbPstateEnabled;                            ///< Method: Get whether Northbridge PStates feature is enabled.
+  PF_DOES_LINK_HAVE_HTFPY_FEATS DoesLinkHaveHtPhyFeats;                 ///< Method: Get Link features and match for HT Phy Table Entry.
+  PF_SET_HT_PHY_REGISTER SetHtPhyRegister;                              ///< Method: Set an Ht Phy register based on table entry.
+  PF_GET_HT_LINK_FEATURES GetHtLinkFeatures;                            ///< Method: Get the Ht link features for the HT Host capability.
+  REGISTER_TABLE **RegisterTableList;                                   ///< Public Data: The available register tables.
+  TABLE_ENTRY_TYPE_DESCRIPTOR *TableEntryTypeDescriptors;               ///< Public Data: implemented register table entry types.
+  PACKAGE_HTLINK_MAP PackageLinkMap;                                    ///< Public Data: translate northbridge HT links to package level links, or NULL.
+  PF_GET_EARLY_INIT_TABLE GetEarlyInitOnCoreTable;                      ///< Method: Get the initialization steps needed at AmdInitEarly.
+};
+
+/**
+ * A Family Id and an interface to it's implementations of Family Specific Services.
+ *
+ * Note that this is a logical family id, which may specify family, model (or even stepping).
+ */
+typedef struct {
+  UINT64          Family;                         ///< The Family to which this interface belongs.
+  CONST VOID      *TablePtr;                      ///< The interface to its Family Specific Services.
+} CPU_SPECIFIC_SERVICES_XLAT;
+
+/**
+ * A collection of Family specific interfaces to Family Specific services.
+ */
+typedef struct {
+  UINT8  Elements;                                       ///< The number of tables to search.
+  CONST    CPU_SPECIFIC_SERVICES_XLAT *FamilyTable;      ///< The family interfaces.
+} CPU_FAMILY_SUPPORT_TABLE;
+
+/**
+ * Implement the translation of a logical CPU id to an id that can be used to get Family specific services.
+ */
+typedef struct {
+  UINT32 Family;                                              ///< Provide translation for this family
+  CPU_LOGICAL_ID UnknownRevision;                             ///< In this family, unrecognized models (or steppings) are treated as though they were this model and stepping.
+  CONST    PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdTable;   ///< Method: Get family specific model (and stepping) resolution.
+  UINT8  Elements;                                            ///< The number of family specific model tables pointed to by SubFamilyIdTable
+} CPU_LOGICAL_ID_FAMILY_XLAT;
+
+/**
+ * A collection of all available family id translations.
+ */
+typedef struct {
+  UINT8  Elements;                                            ///< The number of family translation items to search.
+  CONST    CPU_LOGICAL_ID_FAMILY_XLAT *FamilyIdTable;         ///< The family translation items.
+} CPU_FAMILY_ID_XLAT_TABLE;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a logical identifier for the specified processor, based on CPUID, but independent of CPUID formatting.
+ */
+VOID
+GetLogicalIdOfSocket (
+  IN       UINT32 Socket,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get a logical identifier for the executing core, based on CPUID, but independent of CPUID formatting.
+ */
+VOID
+GetLogicalIdOfCurrentCore (
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get a logical identifier for the specified CPUID value.
+ */
+VOID
+GetLogicalIdFromCpuid (
+  IN       UINT32 RawCpuid,
+     OUT   CPU_LOGICAL_ID *LogicalId,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ */
+VOID
+GetCpuServicesOfSocket (
+  IN       UINT32 Socket,
+  OUT      CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the desired processor's family specific services structure.
+ */
+VOID
+GetFeatureServicesOfSocket (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       UINT32            Socket,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the executing core's family specific services structure.
+ */
+VOID
+GetCpuServicesOfCurrentCore (
+  OUT      CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the executing core's family specific services structure.
+ */
+VOID
+GetFeatureServicesOfCurrentCore (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ */
+VOID
+GetCpuServicesFromLogicalId (
+  IN       CPU_LOGICAL_ID *LogicalId,
+  OUT      CPU_SPECIFIC_SERVICES **FunctionTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Retrieves a pointer to the family specific services structure for a processor
+ *  with the given logical ID.
+ */
+VOID
+GetFeatureServicesFromLogicalId (
+  IN       CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
+  IN       CPU_LOGICAL_ID    *LogicalId,
+     OUT   CONST VOID        **CpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Used by logical families which don't need a certain register setting table or other data array.
+ */
+VOID
+GetEmptyArray (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   CONST VOID **Empty,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_FAMILY_TRANSLATION_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c
new file mode 100755
index 0000000000..218813cfbf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuGeneralServices.c
@@ -0,0 +1,1050 @@
+/**
+ * @file
+ *
+ * Implement External, AGESA Common, and CPU component General Services.
+ *
+ * Contains implementation of the interfaces: General Services API in AGESA.h,
+ * GeneralServices.h, and cpuServices.h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Options.h"
+#include "Topology.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUGENERALSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTIONS_CONFIG_TOPOLOGY TopologyConfiguration;
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - External General Services API
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * Invoke corresponding Cpu Service for external user.
+ *
+ * @param[in,out]    AmdParamApic    Our interface struct
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT   AMD_APIC_PARAMS *AmdParamApic
+  )
+{
+  AGESA_STATUS AgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdGetApicIdEntry, &AmdParamApic->StdHeader);
+
+  AmdParamApic->IsPresent = GetApicId (
+    &AmdParamApic->StdHeader,
+    AmdParamApic->Socket,
+    AmdParamApic->Core,
+    &AmdParamApic->ApicAddress,
+    &AgesaStatus
+    );
+
+  AGESA_TESTPOINT (TpIfAmdGetApicIdExit, &AmdParamApic->StdHeader);
+  return AgesaStatus;
+}
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * Invoke corresponding Cpu Service for external user.
+ *
+ * @param[in,out]    AmdParamGetPci    Our interface struct
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+  )
+{
+  AGESA_STATUS AgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdGetPciAddressEntry, &AmdParamGetPci->StdHeader);
+
+  AmdParamGetPci->IsPresent = GetPciAddress (
+    &AmdParamGetPci->StdHeader,
+    AmdParamGetPci->Socket,
+    AmdParamGetPci->Module,
+    &AmdParamGetPci->PciAddress,
+    &AgesaStatus
+    );
+
+  AGESA_TESTPOINT (TpIfAmdGetPciAddressExit, &AmdParamGetPci->StdHeader);
+  return AgesaStatus;
+}
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * Invoke corresponding Cpu Service for external user.
+ *
+ * @param[in,out]    AmdParamIdentify    Our interface struct
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT   AMD_IDENTIFY_PARAMS *AmdParamIdentify
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Core;
+
+  AGESA_TESTPOINT (TpIfAmdIdentifyCoreEntry, &AmdParamIdentify->StdHeader);
+
+  IdentifyCore (
+    &AmdParamIdentify->StdHeader,
+    &Socket,
+    &Module,
+    &Core,
+    &AgesaStatus
+    );
+  AmdParamIdentify->Socket = (UINT8)Socket;
+  AmdParamIdentify->Module = (UINT8)Module;
+  AmdParamIdentify->Core = (UINT8)Core;
+
+  AGESA_TESTPOINT (TpIfAmdIdentifyCoreExit, &AmdParamIdentify->StdHeader);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - AGESA common General Services
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * Code sync: This calculation MUST match the assignment
+ *    calculation done in LocalApicInitializationAtEarly function.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The socket in which the Core's Processor is installed.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+*/
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  BOOLEAN ReturnValue;
+  UINT32  CoreCount;
+  UINT32  ApicID;
+
+  ReturnValue = FALSE;
+  if (GetActiveCoresInGivenSocket (Socket, &CoreCount, StdHeader)) {
+    if (Core < CoreCount) {
+      ReturnValue = TRUE;
+      GetLocalApicIdForCore (Socket, Core, &ApicID, StdHeader);
+      *ApicAddress = (UINT8) ApicID;
+    }
+  }
+
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  return ReturnValue;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  UINT8        Node;
+  BOOLEAN      Result;
+
+  ASSERT (Socket < MAX_SOCKETS);
+  ASSERT (Module < MAX_DIES);
+
+  Result = TRUE;
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  if (GetNodeId (Socket, Module, &Node, StdHeader)) {
+    // socket is populated
+    PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    PciAddress->Address.Device = PciAddress->Address.Device + Node;
+  } else {
+    // socket is not populated
+    PciAddress->AddressValue = ILLEGAL_SBDFO;
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  AP_MAIL_INFO ApMailboxInfo;
+  UINT32 CurrentCore;
+
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS);
+  ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES);
+  *Socket = (UINT8)ApMailboxInfo.Fields.Socket;
+  *Module = (UINT8)ApMailboxInfo.Fields.Module;
+
+  // Get Core Id
+  GetCurrentCore (&CurrentCore, StdHeader);
+  *Core = (UINT8)CurrentCore;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - cpu component General Services
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the current Platform's number of Sockets, regardless of how many are populated.
+ *
+ * The Options component can provide how many sockets are available in system.
+ * This can be used to avoid testing presence of Processors in Sockets which don't exist.
+ * The result can be one socket to the maximum possible sockets of any supported processor family.
+ * You cannot assume that all sockets contain a processor or that the sockets have processors
+ * installed in any particular order.  Do not convert this number to a number of nodes.
+ *
+ * @return   The number of available sockets for the platform.
+ *
+ */
+UINT32
+GetPlatformNumberOfSockets ()
+{
+  return TopologyConfiguration.PlatformNumberOfSockets;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the number of Modules to check presence in each Processor.
+ *
+ * The Options component can provide how many modules need to be check for presence in each
+ * processor, regardless whether all, or any, processor have that many modules present on this boot.
+ * The result can be one module to the maximum possible modules of any supported processor family.
+ * You cannot assume that Modules are in any particular order, especially with respect to node id.
+ *
+ * @return   The maximum number of modules in each processor.
+ *
+ */
+UINT32
+GetPlatformNumberOfModules ()
+{
+  return TopologyConfiguration.PlatformNumberOfModules;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is a processor present in Socket?
+ *
+ * Check to see if any possible module of the processor is present.  This provides
+ * support for a few cases where a PCI address isn't needed, but code still needs to
+ * iterate by Socket.
+ *
+ * @param[in]   Socket  The socket which is being tested
+ * @param[in]   StdHeader    Header for library and services.
+ *
+ * @retval      TRUE    The socket has a processor installed
+ * @retval      FALSE   The socket is empty (or the processor is dead).
+ *
+ */
+BOOLEAN
+IsProcessorPresent (
+  IN       UINT32             Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+  UINT32 Module;
+
+  ASSERT (Socket < MAX_SOCKETS);
+  Result = FALSE;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT (pSocketDieMap != NULL);
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
+      Result = TRUE;
+      break;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the number of installed processors (not Nodes! and not Sockets!)
+ *
+ * Iterate over the Socket, Module to Node Map, counting the number of present nodes.
+ * Do not use this as a Node Count!  Do not use this as the number of Sockets!  (This
+ * is for APIC ID utilities.)
+ *
+ * @param[in]   StdHeader    Header for library and services.
+ *
+ * @return      the number of processors installed
+ *
+ */
+UINT32
+GetNumberOfProcessors (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  UINT32 Result;
+  UINT32 Socket;
+  UINT32 Module;
+
+  Result = 0;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT (pSocketDieMap != NULL);
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+      if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
+        Result++;
+        break;
+      }
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * For a specific Node, get its Socket and Module ids.
+ *
+ * If asking for the current running Node, read the mailbox socket, module. Specific Node,
+ * locate the Node to Socket/Module Map in heap, and return the ids, if present.
+ *
+ * @param[in]    Node         What Socket and Module is this Node?
+ * @param[out]   Socket       The Socket containing that Node.
+ * @param[out]   Module       The Processor Module of that Node.
+ * @param[in]    StdHeader    Header for library and services.
+ *
+ * @retval TRUE Node is present, Socket, Module are valid.
+ * @retval FALSE Node is not present, why do you ask?
+ */
+BOOLEAN
+GetSocketModuleOfNode (
+  IN       UINT32    Node,
+     OUT   UINT32    *Socket,
+     OUT   UINT32    *Module,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  NODE_TO_SOCKET_DIE_MAP  pNodeMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  ASSERT (Node < MAX_NODES);
+
+  //  Get Map from heap
+  SocketDieHeapDataBlock.BufferHandle = NODE_ID_MAP_HANDLE;
+  HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pNodeMap = (NODE_TO_SOCKET_DIE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT (pNodeMap != NULL);
+  *Socket = (*pNodeMap)[Node].Socket;
+  *Module = (*pNodeMap)[Node].Die;
+  if ((*pNodeMap)[Node].Socket != 0xFF) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the current core's Processor APIC Index.
+ *
+ * The Processor APIC Index is the position of the current processor in the APIC id
+ * assignment.  Processors are ordered in node id order.  This is not the same, however,
+ * as the node id of the current socket and module or the current socket id.
+ *
+ * @param[in]    Node      The current desired core's node id (usually the current core).
+ * @param[in]    StdHeader Header for library and services.
+ *
+ * @return  Processor APIC Index
+ *
+ */
+UINT32
+GetProcessorApicIndex (
+  IN       UINT32            Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProcessorApicIndex;
+  UINT32 PreviousSocket;
+  UINT32 CurrentSocket;
+  UINT32 Ignored;
+  UINT32 i;
+
+  ASSERT (Node < MAX_NODES);
+
+  // Calculate total APIC devices up to Current Node, Core.
+  ProcessorApicIndex = 0;
+  PreviousSocket = 0xFF;
+  for (i = 0; i < (Node + 1); i++) {
+    GetSocketModuleOfNode (i, &CurrentSocket, &Ignored, StdHeader);
+    if (CurrentSocket != PreviousSocket) {
+      ProcessorApicIndex++;
+      PreviousSocket = CurrentSocket;
+    }
+  }
+  // Convert to Index (zero based) from count (one based).
+  ProcessorApicIndex--;
+  return ProcessorApicIndex;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns current node number
+ *
+ *  @param[out]      Node       This Core's Node id
+ *  @param[in]        StdHeader  Header for library and services.
+ *
+ */
+VOID
+GetCurrentNodeNum (
+     OUT   UINT32 *Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_MAIL_INFO ApMailboxInfo;
+
+  // Get the Node Id from the Mailbox.
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
+  *Node = ApMailboxInfo.Fields.Node;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Writes to all nodes on the executing core's socket.
+ *
+ *  @param[in]     PciAddress    The Function and Register to update
+ *  @param[in]     Mask          The bitwise AND mask to apply to the current register value
+ *  @param[in]     Data          The bitwise OR mask to apply to the current register value
+ *  @param[in]     StdHeader     Header for library and services.
+ *
+ */
+VOID
+ModifyCurrentSocketPci (
+  IN       PCI_ADDR          *PciAddress,
+  IN       UINT32            Mask,
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Core;
+  UINT32 PciRegister;
+  AGESA_STATUS AgesaStatus;
+  PCI_ADDR Reg;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
+
+  for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
+      Reg.Address.Function = PciAddress->Address.Function;
+      Reg.Address.Register = PciAddress->Address.Register;
+      LibAmdPciRead (AccessWidth32, Reg, &PciRegister, StdHeader);
+      PciRegister &= Mask;
+      PciRegister |= Data;
+      LibAmdPciWrite (AccessWidth32, Reg, &PciRegister, StdHeader);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns Total number of active cores in the current socket
+ *
+ * @param[out]     CoreCount    The cores in this processor.
+ * @param[in]      StdHeader    Header for library and services.
+ *
+ */
+VOID
+GetActiveCoresInCurrentSocket (
+     OUT   UINT32 *CoreCount,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+  UINT32 TotalCoresCount;
+
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader);
+  TotalCoresCount = (CpuidDataStruct.ECX_Reg & 0x000000FF) + 1;
+  *CoreCount = TotalCoresCount;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provides the Total number of active cores in the current core's node.
+ *
+ * @param[in]      StdHeader   Header for library and services.
+ *
+ * @return         The current node core count
+ */
+UINTN
+GetActiveCoresInCurrentModule (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Core;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 ProcessorCoreCount;
+  AGESA_STATUS AgesaStatus;
+
+  ProcessorCoreCount = 0;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
+  if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+    ProcessorCoreCount = ((HighCore - LowCore) + 1);
+  }
+  return ProcessorCoreCount;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provides the Total number of active cores in the given socket.
+ *
+ * @param[in]      Socket      Get a core count for the processor in this socket.
+ * @param[out]     CoreCount   Its core count
+ * @param[in]      StdHeader   Header for library and services.
+ *
+ * @retval     TRUE    A processor is present in the Socket and the CoreCount is valid.
+ * @retval     FALSE   The Socket does not have a Processor
+ */
+BOOLEAN
+GetActiveCoresInGivenSocket (
+  IN       UINT32             Socket,
+     OUT   UINT32             *CoreCount,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32 Module;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 ProcessorCoreCount;
+  BOOLEAN Result;
+
+  Result = FALSE;
+  ProcessorCoreCount = 0;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+      ProcessorCoreCount = ProcessorCoreCount + ((HighCore - LowCore) + 1);
+      Result = TRUE;
+    } else {
+      break;
+    }
+  }
+  *CoreCount = ProcessorCoreCount;
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provides the range of Cores in a Processor which are in a Module.
+ *
+ * Cores are named uniquely in a processor, 0 to TotalCores.  Any module in the processor has
+ * a set of those cores, named from LowCore to HighCore.
+ *
+ * @param[in]      Socket      Get a core range for the processor in this socket.
+ * @param[in]      Module      Get a core range for this Module in the processor.
+ * @param[out]     LowCore     The lowest Processor Core in the Module.
+ * @param[out]     HighCore    The highest Processor Core in the Module.
+ * @param[in]      StdHeader   Header for library and services.
+ *
+ * @retval     TRUE    A processor is present in the Socket and the Core Range is valid.
+ * @retval     FALSE   The Socket does not have a Processor
+ */
+BOOLEAN
+GetGivenModuleCoreRange (
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   UINT32            *LowCore,
+     OUT   UINT32            *HighCore,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+
+  ASSERT (Socket < MAX_SOCKETS);
+  ASSERT (Module < MAX_DIES);
+  Result = FALSE;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT (pSocketDieMap != NULL);
+  *LowCore = (*pSocketDieMap)[Socket][Module].LowCore;
+  *HighCore = (*pSocketDieMap)[Socket][Module].HighCore;
+  if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the current running core number.
+ *
+ * @param[out]     Core       The core id.
+ * @param[in]      StdHeader  Header for library and services.
+ *
+ */
+VOID
+GetCurrentCore (
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPUID_DATA  CpuidDataStruct;
+  UINT32      LocalApicId;
+  UINT32      ApicIdCoreIdSize;
+  CORE_ID_POSITION      InitApicIdCpuIdLo;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  //  Read CPUID ebx[31:24] to get initial APICID
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader);
+  LocalApicId = (CpuidDataStruct.EBX_Reg & 0xFF000000) >> 24;
+
+  // Find the core ID size.
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader);
+  ApicIdCoreIdSize = (CpuidDataStruct.ECX_Reg & 0x0000F000) >> 12;
+
+  InitApicIdCpuIdLo = FamilyServices->CoreIdPositionInInitialApicId (FamilyServices, StdHeader);
+  ASSERT (InitApicIdCpuIdLo < CoreIdPositionMax);
+
+  // Now extract the core ID from the Apic ID by right justifying the id and masking off non-core Id bits.
+  *Core = ((LocalApicId >> ((1 - (UINT32)InitApicIdCpuIdLo) * (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))) &
+             (MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns current node, and core number.
+ *
+ * @param[out]     Node         The node id of the current core's node.
+ * @param[out]     Core         The core id if the current core.
+ * @param[in]      StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+GetCurrentNodeAndCore (
+     OUT   UINT32 *Node,
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  // Get Node Id
+  GetCurrentNodeNum (Node, StdHeader);
+
+  // Get Core Id
+  GetCurrentCore (Core, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Is the current core a primary core of it's node?
+ *
+ *  @param[in]  StdHeader   Config handle for library and services.
+ *
+ *  @retval        TRUE  Is Primary Core
+ *  @retval        FALSE Is not Primary Core
+ *
+ */
+BOOLEAN
+IsCurrentCorePrimary (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN Result;
+  UINT32 Core;
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 PrimaryCore;
+  UINT32 IgnoredCore;
+  AGESA_STATUS IgnoredSts;
+
+  Result = FALSE;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetGivenModuleCoreRange (Socket, Module, &PrimaryCore, &IgnoredCore, StdHeader);
+  if (Core == PrimaryCore) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns node id based on SocketId and ModuleId.
+ *
+ * @param[in]  SocketId       The socket to look up
+ * @param[in]  ModuleId       The module in that socket
+ * @param[out] NodeId         Provide the corresponding Node Id.
+ * @param[in]  StdHeader   Handle of Header for calling lib functions and services.
+ *
+ * @retval     TRUE       The socket is populated
+ * @retval     FALSE      The socket is not populated
+ *
+ */
+BOOLEAN
+GetNodeId (
+  IN       UINT32  SocketId,
+  IN       UINT32  ModuleId,
+     OUT   UINT8   *NodeId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  SOCKET_DIE_TO_NODE_MAP  pSocketDieMap;
+  LOCATE_HEAP_PTR  SocketDieHeapDataBlock;
+  BOOLEAN Result;
+
+  Result = FALSE;
+  SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+
+  //  Get data block from heap
+  HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
+  pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
+  ASSERT (pSocketDieMap != NULL);
+  *NodeId = (*pSocketDieMap)[SocketId][ModuleId].Node;
+  if ((*pSocketDieMap)[SocketId][ModuleId].Node != 0xFF) {
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the cached AP Mailbox Info if available, or read the info from the hardware.
+ *
+ * Locate the known AP Mailbox Info Cache buffer in this core's local heap.  If it
+ * doesn't exist, read the hardware to get the info.
+ * This routine gets the main AP mailbox, not the system degree.
+ *
+ * @param[out]    ApMailboxInfo  Provide the info in this AP core's mailbox
+ * @param[in]     StdHeader      Config handle for library and services.
+ *
+ */
+VOID
+GetApMailbox (
+     OUT   UINT32               *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AGESA_STATUS     Ignored;
+  LOCATE_HEAP_PTR  LocalApMailboxCache;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+  AP_MAILBOXES     ApMailboxes;
+  BOOLEAN IamBsp;
+
+  IamBsp = IsBsp (StdHeader, &Ignored);
+  LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  if (((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || IamBsp) &&
+      (HeapLocateBuffer (&LocalApMailboxCache, StdHeader) == AGESA_SUCCESS)) {
+    // If during HEAP_LOCAL_CACHE stage, we always try to get ApMailbox from heap
+    // If we're not in HEAP_LOCAL_CACHE stage, only BSP can get ApMailbox from heap
+    *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info;
+  } else if (!IamBsp) {
+    // If this is an AP, the hardware register should be good.
+    GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
+    *ApMailboxInfo = ApMailboxes.ApMailInfo.Info;
+  } else {
+    // This is the BSC.  The hardware mailbox has not been set up yet.
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Cache the Ap Mailbox info in our local heap for later use.
+ *
+ * This enables us to use the info even after the mailbox register is initialized
+ * with operational values.  Get all the AP mailboxes and keep them in one buffer.
+ *
+ * @param[in]     StdHeader   Config handle for library and services.
+ *
+ */
+VOID
+CacheApMailbox (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AP_MAILBOXES ApMailboxes;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  // Get mailbox from hardware.
+  FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
+
+  // Allocate heap for the info
+  AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES);
+  AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = ApMailboxes;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Compute the degree of the system.
+ *
+ * The degree of a system is the maximum degree of any node.  The degree of a node is the
+ * number of nodes to which it is directly connected (not considering width or redundant
+ * links).
+ *
+ * @param[in]     StdHeader            Config handle for library and services.
+ *
+ */
+UINTN
+GetSystemDegree (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_MAILBOXES *ApMailboxes;
+  LOCATE_HEAP_PTR  LocalApMailboxCache;
+
+  //  Get data block from heap
+  LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  HeapLocateBuffer (&LocalApMailboxCache, StdHeader);
+  // non-Success handled by ASSERT not NULL below.
+  ApMailboxes = (AP_MAILBOXES *)LocalApMailboxCache.BufferPtr;
+  ASSERT (ApMailboxes != NULL);
+  return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Spins until the number of microseconds specified have
+ *  expired regardless of CPU operational frequency.
+ *
+ *  @param[in]   Microseconds  Wait time in microseconds
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+WaitMicroseconds (
+  IN       UINT32 Microseconds,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 TscRateInMhz;
+  UINT64 NumberOfTicks;
+  UINT64 InitialTsc;
+  UINT64 CurrentTsc;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  LibAmdMsrRead (TSC, &InitialTsc, StdHeader);
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
+  NumberOfTicks = Microseconds * TscRateInMhz;
+  do {
+    LibAmdMsrRead (TSC, &CurrentTsc, StdHeader);
+  } while ((CurrentTsc - InitialTsc) < NumberOfTicks);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ *
+ *  @param[in,out]   StdHeader        Header for library and services
+ *  @param[out]      AgesaStatus      Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  )
+{
+  UINT64 MsrData;
+
+  // Always Succeeds.
+  *AgesaStatus = AGESA_SUCCESS;
+
+  //  Read APIC_BASE register (0x1B), bit[8] returns 1 for BSP
+  LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader);
+  if ((MsrData & BIT8) != 0 ) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ *
+ * @param[in]      StdHeader               Pointer to structure containing the function call
+ *                                         whose parameter structure is to be created, the
+ *                                         allocation method, and a pointer to the newly
+ *                                         created structure.
+ *
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8        EncodedSize;
+  UINT64       MsrRegister;
+
+  // Make sure that Standard header is valid
+  ASSERT (StdHeader != NULL);
+
+  if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) {
+    EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize);
+    MsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2));
+    LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c
new file mode 100755
index 0000000000..db71d7d7f6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuInitEarlyTable.c
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * Initialize the 'common' way of running early initialization.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUINITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
+
+CONST PF_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
+{
+  McaInitializationAtEarly,
+  SetRegistersFromTablesAtEarly,
+  SetBrandIdRegistersAtEarly,
+  LocalApicInitializationAtEarly,
+  LoadMicrocodePatchAtEarly,
+  NULL
+};
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
+ * processor that uses the standard initialization steps should take.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetCommonEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+VOID
+GetCommonEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  *Table = CommonEarlyInitOnCoreTable;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c
new file mode 100755
index 0000000000..1e93f64357
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.c
@@ -0,0 +1,281 @@
+/**
+ * @file
+ *
+ * AMD CPU Late Init API
+ *
+ * Contains code for doing any late CPU initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPULATEINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+DisableCf8ExtCfg (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the late entry point
+ *
+ * This function should be the last function run by the AGESA
+ * CPU module and prepares the processor for the operating system
+ * bootstrap load process.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+AmdCpuLate (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  DisableCf8ExtCfg (StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Clear EnableCf8ExtCfg on all socket
+ *
+ * Clear F3x8C bit 14 EnableCf8ExtCfg
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *
+ */
+VOID
+DisableCf8ExtCfg (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  PCI_ADDR PciAddress;
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 PciData;
+  UINT32 LegacyPciAccess;
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+        PciAddress.Address.Function = FUNC_3;
+        PciAddress.Address.Register = NB_CFG_HIGH_REG;
+        LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
+        // read from PCI register
+        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+        LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader);
+        // Disable Cf8ExtCfg
+        PciData &= 0xFFFFBFFF;
+        // write to PCI register
+        LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+        LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader);
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate an ACPI style checksum
+ *
+ * Computes the checksum and stores the value to the checksum
+ * field of the passed in ACPI table's header.
+ *
+ * @param[in]  Table             ACPI table to checksum
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+ChecksumAcpiTable (
+  IN OUT   ACPI_TABLE_HEADER *Table,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  *BuffTempPtr;
+  UINT8  Checksum;
+  UINT32 BufferOffset;
+
+  Table->Checksum = 0;
+  Checksum = 0;
+  BuffTempPtr = (UINT8 *) Table;
+  for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) {
+    Checksum = Checksum - *(BuffTempPtr + BufferOffset);
+  }
+
+  Table->Checksum = Checksum;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Run code on every AP in the system.
+ *
+ * @param[in] ApParams       AP task pointer.
+ * @param[in] StdHeader      Handle to config for library and services
+ *
+ * @return    The most severe AGESA_STATUS returned by an AP.
+ *
+ */
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  UINT8                   Socket;
+  UINT8                   Core;
+  UINT8                   ApicId;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  AGESA_STATUS            CalledStatus;
+  AGESA_STATUS            IgnoredStatus;
+  AGESA_STATUS            AgesaStatus;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredStatus));
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredStatus);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCore)) {
+          GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);
+          AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);
+          CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
+          AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader);
+          if (CalledStatus > AgesaStatus) {
+            AgesaStatus = CalledStatus;
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Run code on core 0 of every socket in the system.
+ *
+ * @param[in] ApParams       AP task pointer.
+ * @param[in] StdHeader      Handle to config for library and services
+ *
+ * @return    The most severe AGESA_STATUS returned by an AP.
+ *
+ */
+AGESA_STATUS
+RunLateApTaskOnAllCore0s (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32                  NumberOfSockets;
+  UINT8                   Socket;
+  UINT8                   ApicId;
+  UINT32                  BscSocket;
+  UINT32                  IgnoredModule;
+  UINT32                  IgnoredCore;
+  AGESA_STATUS            CalledStatus;
+  AGESA_STATUS            IgnoredStatus;
+  AGESA_STATUS            AgesaStatus;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredStatus));
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      if (Socket != BscSocket) {
+        GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus);
+        AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader);
+        CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
+        AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader);
+        if (CalledStatus > AgesaStatus) {
+          AgesaStatus = CalledStatus;
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h
new file mode 100755
index 0000000000..8b461c9031
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuLateInit.h
@@ -0,0 +1,797 @@
+/**
+ * @file
+ *
+ * AMD CPU Late Init API functions Prototypes.
+ *
+ * Contains code for doing any late CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_LATE_INIT_H_
+#define _CPU_LATE_INIT_H_
+
+#include "Filecode.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         DMI DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
+// SMBIOS constant definition
+#define CENTRAL_PROCESSOR   0x03
+#define EXTERNAL_CLOCK      200
+#define UNKNOWN             0x02
+#define P_CHARACTERISTICS   0x4
+#define CACHE_CFG_L1        0x180
+#define CACHE_CFG_L2        0x181
+#define CACHE_CFG_L3        0x182
+#define SRAM_TYPE           0x10
+#define ERR_CORRECT_TYPE    0x06
+#define CACHE_TYPE          0x05
+#define ASSOCIATIVE_2_WAY   0x04
+#define ASSOCIATIVE_16_WAY  0x08
+#define ASSOCIATIVE_OTHER   0x01
+
+// Processor Upgrade Definition
+#define P_UPGRADE_UNKNOWN   0x02
+#define P_UPGRADE_NONE      0x06
+#define P_UPGRADE_AM2       0x17
+#define P_UPGRADE_F1207     0x18
+#define P_UPGRADE_G34       0x1A
+#define P_UPGRADE_AM3       0x1B
+#define P_UPGRADE_C32       0x1C
+#define P_UPGRADE_S1GX      0x1C
+
+//----------------------------------------------------------------------------
+//                         SRAT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define NorthbridgeCapabilities 0xE8
+#define DRAMBase0 0x40
+#define MMIOBase0 0x80
+#define TOP_MEM 0xC001001A
+#define LOW_NODE_DEVICEID 24
+#define LOW_APICID 0
+
+
+// Miscellaneous AMD related values
+#define MAX_NUMBER_NODES  8
+#define MAX_NUMBER_CORES  6       // GH is 4 and RR is 6
+
+// Flags
+#define ENABLED         1   // Bit 0
+#define DISABLED        0   // Bit 0
+#define HOTPLUGGABLE    2   // Bit 1
+
+// Affinity Entry Structures
+#define AE_APIC     0
+#define AE_MEMORY   1
+
+
+// Memory Types
+#define TYPE_MEMORY   1
+#define TYPE_RESERVED 2
+#define TYPE_ACPI     3
+#define TYPE_NVS      4
+
+//----------------------------------------------------------------------------
+//                         SLIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define PROBE_FILTER_CTRL_REG             0x1D4
+#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH   8
+
+//----------------------------------------------------------------------------
+//                         P-STATE DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+//-------------------------------------
+//          ERROR Codes
+//-------------------------------------
+#define     NO_ERROR                    0x0
+#define     USER_DISABLE_ERROR          0x01            // User disabled SSDT generation
+#define     CORES_MISSMATCH_PSS_ERROR   0x02            // No PSS match
+#define     PNOW_SUPPORT_ERROR          0x04            // One of the Cores do not support PNOW!
+#define     PWR_FREQ_MATCH_ERROR        0x08            // FREQ and PWR mismatch
+#define     NO_PSS_SIZE_ERROR           0x10            // Error in PSS Size
+#define     INVALID_PSTATE_ERROR        0x20            // Invalid Max or only 1 P-State available
+#define     NO_PSS_ENTRY                0x0FFFF
+#define     INVALID_FREQ                0x0FFFFFFFF
+
+//-------------------------
+// Default definitions
+// AMD BKDG default values
+//-------------------------
+#define DEFAULT_ISOCH_RELIEF_TIME       IRT_80uS
+#define DEFAULT_RAMP_VOLTAGE_OFFSET     RVO_50mV
+#define DEFAULT_MAX_VOLTAGE_STEP        MVS_25mV
+#define DEFAULT_PERF_PRESENT_CAP        0           // default for Desktop
+#define DEFAULT_VOLTAGE_STABLE_TIME     (100 / 20)  // 100uS
+#define DEFAULT_PLL_LOCK_TIME           2           // 2uS
+#define DEFAULT_TRANSITION_LATENCY      100         // 100uS
+#define DEFAULT_BUS_MASTER_LATENCY      9           // 9uS
+#define DEFAULT_CPU_SCOPE_NUMBER        "0UPC"
+
+// Defines for Common ACPI
+// -----------------------------
+#define     SCOPE_OPCODE            0x10
+#define     NAME_OPCODE             0x08
+#define     PACKAGE_OPCODE          0x12
+#define     BUFFER_OPCODE           0x11
+#define     BYTE_PREFIX_OPCODE      0x0A
+#define     DWORD_PREFIX_OPCODE     0x0C
+#define     ACPI_BUFFER             0x080A0B11
+
+// Generic Register Descriptor (GDR) Fields
+#define     GDR_ASI_SYSTEM_IO       0x01    // Address Space ID
+#define     GDR_ASZ_BYTE_ACCESS     0x01    // Address Size
+
+// Defines for ACPI Scope Table
+// ----------------------------
+#define     SCOPE_LENGTH    (SCOPE_STRUCT_SIZE + \
+                            PCT_STRUCT_SIZE + \
+                            PSS_HEADER_STRUCT_SIZE + \
+                            PSS_BODY_STRUCT_SIZE + \
+                            PPC_HEADER_BODY_STRUCT_SIZE)
+#define     SCOPE_VALUE1    0x5C
+#define     SCOPE_VALUE2    0x2E
+#define     SCOPE_NAME__    '_'
+#define     SCOPE_NAME_P    'P'
+#define     SCOPE_NAME_R    'R'
+#define     SCOPE_NAME_S    'S'
+#define     SCOPE_NAME_B    'B'
+#define     SCOPE_NAME_C    'C'
+#define     SCOPE_NAME_U    'U'
+#define     SCOPE_NAME_0    '0'
+#define     SCOPE_NAME_1    '1'
+#define     SCOPE_NAME_2    '2'
+#define     SCOPE_NAME_3    '3'
+#define     SCOPE_NAME_A    'A'
+
+#ifdef OEM_SCOPE_NAME
+  #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
+    #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
+  #endif
+  #define     SCOPE_NAME_VALUE    OEM_SCOPE_NAME
+#else
+  #define     SCOPE_NAME_VALUE    SCOPE_NAME_C
+#endif  // OEM_SCOPE_NAME
+
+#ifdef OEM_SCOPE_NAME1
+  #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
+         ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
+         (OEM_SCOPE_NAME1 == '_')))
+    #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
+  #endif
+  #define     SCOPE_NAME_VALUE1   OEM_SCOPE_NAME1
+#else
+  #define     SCOPE_NAME_VALUE1   SCOPE_NAME_0
+#endif  // OEM_SCOPE_NAME
+
+// Defines for PCT Control and Status Table
+// ----------------------------------------
+#define     PCT_NAME__                  '_'
+#define     PCT_NAME_P                  'P'
+#define     PCT_NAME_C                  'C'
+#define     PCT_NAME_T                  'T'
+#define     PCT_VALUE1                  0x11022C12
+#define     PCT_VALUE2                  0x0A14
+#define     PCT_VALUE3                  0x11
+#define     GENERIC_REG_DESCRIPTION     0x82
+#define     PCT_LENGTH                  0x0C
+#define     PCT_ADDRESS_SPACE_ID        0x7F
+#define     PCT_REGISTER_BIT_WIDTH      0x40
+#define     PCT_REGISTER_BIT_OFFSET     0x00
+#define     PCT_RESERVED                0x00
+#define     PCT_CONTROL_REG_LO          0xC0010062
+#define     PCT_CONTROL_REG_HI          0x00
+#define     PCT_VALUE4                  0x14110079
+#define     PCT_VALUE5                  0x110A
+#define     PCT_STATUS_REG_LO           0x00
+#define     PCT_STATUS_REG_HI           0x00
+#define     PCT_VALUE6                  0x0079
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define     PSS_NAME__          '_'
+#define     PSS_NAME_X          'X'
+#define     PSS_NAME_P          'P'
+#define     PSS_NAME_S          'S'
+#define     PSS_LENGTH          (sizeof pssBodyStruct + 3)
+#define     NUM_OF_ITEMS_IN_PSS 0x00
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define     PSS_PKG_LENGTH              0x20  // PSS_BODY_STRUCT_SIZE - 1
+#define     PSS_NUM_OF_ELEMENTS         0x06
+#define     PSS_FREQUENCY               0x00
+#define     PSS_POWER                   0x00
+#define     PSS_TRANSITION_LATENCY      DEFAULT_TRANSITION_LATENCY
+#define     PSS_BUS_MASTER_LATENCY      DEFAULT_BUS_MASTER_LATENCY
+#define     PSS_CONTROL                 ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
+                                         (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
+                                         (DEFAULT_EXT_TYPE << 27) + \
+                                         (DEFAULT_PLL_LOCK_TIME << 20) + \
+                                         (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
+                                         (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
+                                         (PSS_VID << 6) + PSS_FID)
+#define     PSS_STATUS                  (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
+
+// Defines for XPSS Header Table
+// ----------------------------
+#define     XPSS_PKG_LENGTH             0x47  // XPSS_BODY_STRUCT_SIZE - 1
+#define     XPSS_NUM_OF_ELEMENTS        0x08
+#define     XPSS_ACPI_BUFFER            0x080A0B11
+
+
+// Defines for PPC Header Table
+// ----------------------------
+#define     PPC_NAME__  '_'
+#define     PPC_NAME_P  'P'
+#define     PPC_NAME_C  'C'
+#define     PPC_VALUE1  0x0A;
+
+// Defines for PSD Header Table
+// ----------------------------
+#define     PSD_NAME__          '_'
+#define     PSD_NAME_P          'P'
+#define     PSD_NAME_S          'S'
+#define     PSD_NAME_D          'D'
+#define     PSD_HEADER_LENGTH   (PSD_BODY_STRUCT_SIZE + 2)
+#define     PSD_VALUE1          0x01
+
+
+// Defines for PSD Header Table
+// ----------------------------
+#define     PSD_PKG_LENGTH          (PSD_BODY_STRUCT_SIZE - 1)
+#define     NUM_OF_ENTRIES          0x05
+#define     PSD_NUM_OF_ENTRIES      0x05
+#define     PSD_REVISION            0x00
+#define     PSD_DEPENDENCY_DOMAIN   0x00
+#define     PSD_COORDINATION_TYPE_SW_ANY   0xFD
+#define     PSD_COORDINATION_TYPE_SW_ALL   0xFC
+#define     PSD_NUM_OF_PROCESSORS   0x01
+
+#define     CUSTOM_PSTATE_FLAG      0x55
+#define     PSTATE_FLAG_1           0x55
+#define     TARGET_PSTATE_FLAG      0xAA
+#define     PSTATE_FLAG_2           0xAA
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+//--------------------------------------------
+//              AML code definition
+//                   (Scope)
+//---------------------------------------------
+/// SCOPE
+typedef struct _SCOPE {
+  UINT8   ScopeOpcode;                  ///< Opcode
+  UINT16  ScopeLength;                  ///< Scope Length
+  UINT8   ScopeValue1;                  ///< Value1
+  UINT8   ScopeValue2;                  ///< Value2
+  UINT8   ScopeNamePt1a__;              ///< Name Pointer
+  UINT8   ScopeNamePt1a_P;              ///< Name Pointer
+  UINT8   ScopeNamePt1a_R;              ///< Name Pointer
+  UINT8   ScopeNamePt1b__;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_C;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_P;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_U;              ///< Name Pointer
+  UINT8   ScopeNamePt2a_0;              ///< Name Pointer
+} SCOPE;
+#define     SCOPE_STRUCT_SIZE   13      // 13 Bytes
+
+//--------------------------------------------
+//              AML code definition
+//             (PCT Header and Body)
+//---------------------------------------------
+
+///Performance Control Header
+typedef struct _PCT_HEADER_BODY {
+  UINT8   NameOpcode;                   ///< Opcode
+  UINT8   PctName_a__;                  ///< String "_"
+  UINT8   PctName_a_P;                  ///< String "P"
+  UINT8   PctName_a_C;                  ///< String "C"
+  UINT8   PctName_a_T;                  ///< String "T"
+  UINT32  Value1;                       ///< Value1
+  UINT16  Value2;                       ///< Value2
+  UINT8   Value3;                       ///< Value3
+  UINT8   GenericRegDescription1;       ///< Generic Reg Description
+  UINT16  Length1;                      ///< Length1
+  UINT8   AddressSpaceId1;              ///< PCT Address Space ID
+  UINT8   RegisterBitWidth1;            ///< PCT Register Bit Width
+  UINT8   RegisterBitOffset1;           ///< PCT Register Bit Offset
+  UINT8   Reserved1;                    ///< Reserved
+  UINT32  ControlRegAddressLo;          ///< Control Register Address Low
+  UINT32  ControlRegAddressHi;          ///< Control Register Address High
+  UINT32  Value4;                       ///< Value4
+  UINT16  Value5;                       ///< Value 5
+  UINT8   GenericRegDescription2;       ///< Generic Reg Description
+  UINT16  Length2;                      ///< Length2
+  UINT8   AddressSpaceId2;              ///< PCT Address Space ID
+  UINT8   RegisterBitWidth2;            ///< PCT Register Bit Width
+  UINT8   RegisterBitOffset2;           ///< PCT Register Bit Offset
+  UINT8   Reserved2;                    ///< Reserved
+  UINT32  StatusRegAddressLo;           ///< Control Register Address Low
+  UINT32  StatusRegAddressHi;           ///< Control Register Address High
+  UINT16  Value6;                       ///< Values
+} PCT_HEADER_BODY;
+#define     PCT_STRUCT_SIZE     50      // 50 Bytes
+
+
+//--------------------------------------------
+//              AML code definition
+//                 (PSS Header)
+//--------------------------------------------
+///Performance Supported States Header
+typedef struct  _PSS_HEADER {
+  UINT8   NameOpcode;                   ///< Opcode
+  UINT8   PssName_a__;                  ///< String "_"
+  UINT8   PssName_a_P;                  ///< String "P"
+  UINT8   PssName_a_S;                  ///< String "S"
+  UINT8   PssName_b_S;                  ///< String "S"
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT16  PssLength;                    ///< PSS Length
+  UINT8   NumOfItemsInPss;              ///< Number of Items in PSS
+} PSS_HEADER;
+#define     PSS_HEADER_STRUCT_SIZE  9   // 9 Bytes
+
+
+//--------------------------------------------
+//              AML code definition
+//                 (PSS Body)
+//--------------------------------------------
+///Performance Supported States Body
+typedef struct _PSS_BODY {
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT8   PkgLength;                    ///< Package Length
+  UINT8   NumOfElements;                ///< Number of Elements
+  UINT8   DwordPrefixOpcode1;           ///< Prefix Opcode1
+  UINT32  Frequency;                    ///< Frequency
+  UINT8   DwordPrefixOpcode2;           ///< Prefix Opcode2
+  UINT32  Power;                        ///< Power
+  UINT8   DwordPrefixOpcode3;           ///< Prefix Opcode3
+  UINT32  TransitionLatency;            ///< Transition Latency
+  UINT8   DwordPrefixOpcode4;           ///< Prefix Opcode4
+  UINT32  BusMasterLatency;             ///< Bus Master Latency
+  UINT8   DwordPrefixOpcode5;           ///< Prefix Opcode5
+  UINT32  Control;                      ///< Control
+  UINT8   DwordPrefixOpcode6;           ///< Prefix Opcode6
+  UINT32  Status;                       ///< Status
+} PSS_BODY;
+#define     PSS_BODY_STRUCT_SIZE    33  // 33 Bytes
+
+
+/*--------------------------------------------
+ *              AML code definition
+ *                 (XPSS Header)
+ *--------------------------------------------
+ */
+/// Extended PSS Header
+typedef struct  _XPSS_HEADER {
+  UINT8   NameOpcode;                   ///< 08h
+  UINT8   XpssName_a_X;                 ///< String "X"
+  UINT8   XpssName_a_P;                 ///< String "P"
+  UINT8   XpssName_a_S;                 ///< String "S"
+  UINT8   XpssName_b_S;                 ///< String "S"
+  UINT8   PkgOpcode;                    ///< 12h
+  UINT16  XpssLength;                   ///< XPSS Length
+  UINT8   NumOfItemsInXpss;             ///< Number of Items in XPSS
+} XPSS_HEADER;
+#define     XPSS_HEADER_STRUCT_SIZE  9  // 9 Bytes
+
+/*--------------------------------------------
+ *              AML code definition
+ *                 (XPSS Body)
+ *--------------------------------------------
+ */
+/// Extended PSS Body
+typedef struct  _XPSS_BODY {
+  UINT8   PkgOpcode;                    ///< 12h
+  UINT8   PkgLength;                    ///< Package Length
+  UINT8   XpssValueTbd;                 ///< XPSS Value
+  UINT8   NumOfElements;                ///< Number of Elements
+  UINT8   DwordPrefixOpcode1;           ///< Prefix Opcode1
+  UINT32  Frequency;                    ///< Frequency
+  UINT8   DwordPrefixOpcode2;           ///< Prefix Opcode2
+  UINT32  Power;                        ///< Power
+  UINT8   DwordPrefixOpcode3;           ///< Prefix Opcode3
+  UINT32  TransitionLatency;            ///< Transition Latency
+  UINT8   DwordPrefixOpcode4;           ///< Prefix Opcode4
+  UINT32  BusMasterLatency;             ///< Bus Master Latency
+  UINT32  ControlBuffer;                ///< Control Buffer
+  UINT32  ControlLo;                    ///< Control Low
+  UINT32  ControlHi;                    ///< Control High
+  UINT32  StatusBuffer;                 ///< Status Buffer
+  UINT32  StatusLo;                     ///< Status Low
+  UINT32  StatusHi;                     ///< Status High
+  UINT32  ControlMaskBuffer;            ///< Control Mask Buffer
+  UINT32  ControlMaskLo;                ///< Control Mask Low
+  UINT32  ControlMaskHi;                ///< Control Mask High
+  UINT32  StatusMaskBuffer;             ///< Status Mask Buffer
+  UINT32  StatusMaskLo;                 ///< Status Mask Low
+  UINT32  StatusMaskHi;                 ///< Status Mask High
+} XPSS_BODY;
+#define     XPSS_BODY_STRUCT_SIZE    72 // 72 Bytes
+
+/*--------------------------------------------
+ *              AML code definition
+ *             (PPC Header and Body)
+ *--------------------------------------------
+ */
+/// Performance Present Capabilities Header
+typedef struct _PPC_HEADER_BODY {
+  UINT8   NameOpcode;                   ///< Name Opcode
+  UINT8   PpcName_a__;                  ///< String "_"
+  UINT8   PpcName_a_P;                  ///< String "P"
+  UINT8   PpcName_b_P;                  ///< String "P"
+  UINT8   PpcName_a_C;                  ///< String "C"
+  UINT8   Value1;                       ///< Value
+  UINT8   DefaultPerfPresentCap;        ///< Default Perf Present Cap
+} PPC_HEADER_BODY;
+#define     PPC_HEADER_BODY_STRUCT_SIZE     7 // 7 Bytes
+
+
+/*--------------------------------------------
+ *              AML code definition
+ *                (PSD Header)
+ *--------------------------------------------
+ */
+/// P-State Dependency Header
+typedef struct  _PSD_HEADER {
+  UINT8   NameOpcode;                   ///< Name Opcode
+  UINT8   PsdName_a__;                  ///< String "_"
+  UINT8   PsdName_a_P;                  ///< String "P"
+  UINT8   PsdName_a_S;                  ///< String "S"
+  UINT8   PsdName_a_D;                  ///< String "D"
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT8   PsdLength;                    ///< PSD Length
+  UINT8   Value1;                       ///< Value
+} PSD_HEADER;
+#define     PSD_HEADER_STRUCT_SIZE  8   // 8 Bytes
+
+/*--------------------------------------------
+ *              AML code definition
+ *                 (PSD Body)
+ *--------------------------------------------
+ */
+/// P-State Dependency Body
+typedef struct _PSD_BODY {
+  UINT8   PkgOpcode;                    ///< Package Opcode
+  UINT8   PkgLength;                    ///< Package Length
+  UINT8   NumOfEntries;                 ///< Number of Entries
+  UINT8   BytePrefixOpcode1;            ///< Prefix Opcode1 in Byte
+  UINT8   PsdNumOfEntries;              ///< PSD Number of Entries
+  UINT8   BytePrefixOpcode2;            ///< Prefix Opcode2 in Byte
+  UINT8   PsdRevision;                  ///< PSD Revision
+  UINT8   DwordPrefixOpcode1;           ///< Prefix Opcode1 in DWord
+  UINT32  DependencyDomain;             ///< Dependency Domain
+  UINT8   DwordPrefixOpcode2;           ///< Prefix Opcode2 in DWord
+  UINT32  CoordinationType;             ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
+  UINT8   DwordPrefixOpcode3;           ///< Prefix Opcode3 in DWord
+  UINT32  NumOfProcessors;              ///< Number of Processors
+} PSD_BODY;
+#define     PSD_BODY_STRUCT_SIZE    22  // 22 Bytes
+
+
+//typedef struct _S_PSTATE_ACPI_BUFFER {
+//  SCOPE             AcpiScopeStruct;
+//  PCT_HEADER_BODY   AcpiPctHeaderBodyStruct;
+//  PSS_HEADER        AcpiPssHeaderStruct;
+//  PSS_BODY          AcpiPssBodyStruct[MPPSTATE_MAXIMUM_STATES];
+//  XPSS_HEADER       AcpiXpssHeaderStruct;
+//  XPSS_BODY         AcpiXpssBodyStruct[MPPSTATE_MAXIMUM_STATES];
+//  PSD_HEADER        AcpiPsdHeaderStruct;
+//  PSD_BODY          AcpiPsdBodyStruct;
+//  PPC_HEADER_BODY   AcpiPpcHeaderBodyStruct;
+//} S_PSTATE_ACPI_BUFFER;
+
+//----------------------------------------------------------------------------
+//                         WHEA TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// HEST MCE TABLE
+typedef struct _AMD_HEST_MCE_TABLE {
+  UINT16 TblLength;               ///< Length, in bytes, of entire AMD_HEST_MCE structure.
+  UINT32 GlobCapInitDataLSD;      ///< Holds the value that the OS will program into
+  UINT32 GlobCapInitDataMSD;      ///< the machine check global capability register(MCG_CAP).
+  UINT32 GlobCtrlInitDataLSD;     ///< Holds the value that the OS will program into
+  UINT32 GlobCtrlInitDataMSD;     ///< the machine check global control register(MCG_CTL).
+  UINT8 NumHWBanks;               ///< The number of hardware error reporting banks.
+  UINT8 Rsvd[7];                  ///< reserve 7 bytes as spec's required
+} AMD_HEST_MCE_TABLE;
+
+/// HEST CMC TABLE
+typedef struct _AMD_HEST_CMC_TABLE {
+  UINT16 TblLength;               ///< Length, in bytes, of entire AMD_HEST_CMC structure.
+  UINT8 NumHWBanks;               ///< The number of hardware error reporting banks.
+  UINT8 Rsvd[3];                  ///< reserve 3 bytes as spec's required
+} AMD_HEST_CMC_TABLE;
+
+/// HEST BANK
+typedef struct _AMD_HEST_BANK {
+  UINT8 BankNum;                  ///< Zero-based index identifies the machine check error bank.
+  UINT8 ClrStatusOnInit;          ///< Indicates if the status information in this machine check bank
+                                  ///< is to be cleared during system initialization.
+  UINT8 StatusDataFormat;         ///< Indicates the format of the data in the status register
+  UINT8 ConfWriteEn;              ///< This field indicates whether configuration parameters may be
+                                  ///< modified by the OS. If the bit for the associated parameter is
+                                  ///< set, the parameter is writable by the OS.
+  UINT32 CtrlRegMSRAddr;          ///< Address of the hardware bank's control MSR. Ignored if zero.
+
+  UINT32 CtrlInitDataLSD;         ///< This is the value the OS will program into the machine check
+  UINT32 CtrlInitDataMSD;         ///< bank's control register
+  UINT32 StatRegMSRAddr;          ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
+  UINT32 AddrRegMSRAddr;          ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
+  UINT32 MiscRegMSRAddr;          ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
+} AMD_HEST_BANK;
+
+/// Initial data of AMD_HEST_BANK
+typedef struct _AMD_HEST_BANK_INIT_DATA {
+  UINT32 CtrlInitDataLSD;         ///< Initial data of CtrlInitDataLSD
+  UINT32 CtrlInitDataMSD;         ///< Initial data of CtrlInitDataMSD
+  UINT32 CtrlRegMSRAddr;          ///< Initial data of CtrlRegMSRAddr
+  UINT32 StatRegMSRAddr;          ///< Initial data of StatRegMSRAddr
+  UINT32 AddrRegMSRAddr;          ///< Initial data of AddrRegMSRAddr
+  UINT32 MiscRegMSRAddr;          ///< Initial data of MiscRegMSRAddr
+} AMD_HEST_BANK_INIT_DATA;
+
+/// MSR179 Global Machine Check Capabilities data struct
+typedef struct _MSR_MCG_CAP_STRUCT {
+  UINT64 Count:8;                 ///< Indicates the number of
+                                  ///< error-reporting banks visible to each core
+  UINT64 McgCtlP:1;               ///< 1=The machine check control registers
+  UINT64 Rsvd:55;                 ///< reserved
+} MSR_MCG_CAP_STRUCT;
+
+/// Initial data of WHEA
+typedef struct _AMD_WHEA_INIT_DATA {
+  UINT32 GlobCapInitDataLSD;      ///< Holds the value that the OS will program into the machine
+  UINT32 GlobCapInitDataMSD;      ///< Check global capability register
+  UINT32 GlobCtrlInitDataLSD;     ///< Holds the value that the OS will grogram into the machine
+  UINT32 GlobCtrlInitDataMSD;     ///< Check global control register
+  UINT8  ClrStatusOnInit;         ///< Indicates if the status information in this machine check
+                                  ///< bank is to be cleared during system initialization
+  UINT8  StatusDataFormat;        ///< Indicates the format of the data in the status register
+  UINT8  ConfWriteEn;             ///< This field indicates whether configuration parameters may be
+                                  ///< modified by the OS. If the bit for the associated parameter is
+                                  ///< set, the parameter is writable by the OS.
+  UINT8  HestBankNum;             ///< Number of HEST Bank
+  AMD_HEST_BANK_INIT_DATA *HestBankInitData;  ///< Pointer to Initial data of HEST Bank
+} AMD_WHEA_INIT_DATA;
+
+//----------------------------------------------------------------------------
+//                         DMI TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// DMI brand information
+typedef struct {
+  UINT16 String1:4;                 ///< String1
+  UINT16 String2:4;                 ///< String2
+  UINT16 Model:7;                   ///< Model
+  UINT16 Pg:1;                      ///< Page
+} BRAND_ID;
+
+/// DMI processor information
+typedef struct {
+  UINT8  ExtendedFamily;            ///< Extended Family
+  UINT8  ExtendedModel;             ///< Extended Model
+  UINT8  BaseFamily;                ///< Base Family
+  UINT8  BaseModel;                 ///< Base Model
+  UINT8  Stepping;                  ///< Stepping
+  UINT8  PackageType;               ///< PackageType
+  BRAND_ID BrandId;                 ///< BrandId which contains information about String1, String2, Model and Page
+  UINT8  TotalCoreNumber;           ///< Number of total cores
+  UINT8  EnabledCoreNumber;         ///< Number of enabled cores
+  UINT8  ProcUpgrade;               ///< ProcUpdrade
+} CPU_TYPE_INFO;
+
+/*  Transfer vectors for DMI family specific routines   */
+typedef VOID  OPTION_DMI_GET_CPU_INFO (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef UINT8 OPTION_DMI_GET_VOLTAGE (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+typedef UINT16  OPTION_DMI_GET_MAX_SPEED (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Brand table entry format
+typedef struct {
+  UINT8 PackageType;                ///< Package type
+  UINT8 PgOfBrandId;                ///< Page
+  UINT8 NumberOfCores;              ///< Number of cores
+  UINT8 String1ofBrandId;           ///< String1
+  UINT8 ValueSetToDmiTable;         ///< The value which will should be set to DMI table
+} DMI_BRAND_ENTRY;
+
+/// Family specific data table structure
+typedef struct {
+  UINT64                    ProcessorFamily;  ///< processor
+  OPTION_DMI_GET_CPU_INFO   *DmiGetCpuInfo;   ///< transfer vectors
+  OPTION_DMI_GET_VOLTAGE    *DmiGetVoltage;   ///< vector for reading voltage
+  OPTION_DMI_GET_MAX_SPEED  *DmiGetMaxSpeed;  ///< vector for reading speed
+  UINT8                     LenBrandList;     ///< size of brand table
+  CONST DMI_BRAND_ENTRY     *DmiBrandList;    ///< translate brand info to DMI identifier
+} PROC_FAMILY_TABLE;
+
+//----------------------------------------------------------------------------
+//                         SLIT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct {
+  UINT8   Sign[4];                      ///< Signature
+  UINT32  TableLength;                  ///< Table Length
+  UINT8   Revision;                     ///< Revision
+  UINT8   Checksum;                     ///< Checksum
+  UINT8   OemId[6];                     ///< OEM ID
+  UINT8   OemTableId[8];                ///< OEM Tabled ID
+  UINT32  OemRev;                       ///< OEM Revision
+  UINT8   CreatorId[4];                 ///< Creator ID
+  UINT32  CreatorRev;                   ///< Creator Revision
+} ACPI_TABLE_HEADER;
+
+//----------------------------------------------------------------------------
+//                         SRAT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct _CPU_SRAT_HEADER {
+  UINT8   Sign[4];                      ///< Signature
+  UINT32  TableLength;                  ///< Table Length
+  UINT8   Revision;                     ///< Revision
+  UINT8   Checksum;                     ///< Checksum
+  UINT8   OemId[6];                     ///< OEM ID
+  UINT8   OemTableId[8];                ///< OEM Tabled ID
+  UINT32  OemRev;                       ///< OEM Revision
+  UINT8   CreatorId[4];                 ///< Creator ID
+  UINT32  CreatorRev;                   ///< Creator Revision
+  UINT32  TableRev;                     ///< Table Revision
+  UINT8   Reserved[8];                  ///< Reserved
+} CPU_SRAT_HEADER;
+
+
+/// Format for SRAT APIC Affinity Entry
+typedef struct _CPU_SRAT_APIC_ENTRY {
+  UINT8   Type;                         ///< Type
+  UINT8   Length;                       ///< Length
+  UINT8   Domain;                       ///< Domain
+  UINT8   ApicId;                       ///< Apic ID
+  UINT32  Flags;                        ///< Flags
+  UINT8   LSApicEid;                    ///< Local SAPIC EID
+  UINT8   Reserved[7];                  ///< Reserved
+} CPU_SRAT_APIC_ENTRY;
+
+
+/// Format for SRAT Memory Affinity Entry
+typedef struct _CPU_SRAT_MEMORY_ENTRY {
+  UINT8   Type;                         ///< 0: Memory affinity = 1
+  UINT8   Length;                       ///< 1: Length = 40 bytes
+  UINT32  Domain;                       ///< 2: Proximity domain
+  UINT8   Reserved1[2];                 ///< 6: Reserved
+  UINT32  BaseAddrLow;                  ///< 8:  Low 32bits address base
+  UINT32  BaseAddrHigh;                 ///< 12: High 32bits address base
+  UINT32  LengthAddrLow;                ///< 16: Low 32bits address limit
+  UINT32  LengthAddrHigh;               ///< 20: High 32bits address limit
+  UINT8   Reserved2[4];                 ///< 24: Memory Type
+  UINT32  Flags;                        ///< 28: Flags
+  UINT8   Reserved3[8];                 ///< 32: Reserved
+} CPU_SRAT_MEMORY_ENTRY;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdCpuLate (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+CreateAcpiWhea (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+AGESA_STATUS
+CreateDmiRecords (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   DMI_INFO             **DmiTable
+  );
+
+AGESA_STATUS
+GetType4Type7Info (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+AGESA_STATUS
+CreateAcpiSrat (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **SratPtr
+  );
+
+AGESA_STATUS
+CreateAcpiSlit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+
+VOID
+ChecksumAcpiTable (
+  IN OUT   ACPI_TABLE_HEADER *Table,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+RunLateApTaskOnAllCore0s (
+  IN       AP_EXE_PARAMS     *ApParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c
new file mode 100755
index 0000000000..bd84e34d2a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuMicrocodePatch.c
@@ -0,0 +1,441 @@
+/**
+ * @file
+ *
+ * AMD CPU Microcode Patch Related Functions
+ *
+ * Contains code to program a microcode into the CPU
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *---------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuEarlyInit.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUMICROCODEPATCH_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef union {
+  UINT64           RawData;
+  PATCH_LOADER_MSR BitFields;
+} PATCH_LOADER;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+LoadMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+BOOLEAN
+STATIC
+GetPatchEquivalentId (
+  IN OUT   UINT16             *ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+BOOLEAN
+STATIC
+ValidateMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN       UINT16             ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+STATIC
+GetMicrocodeVersion (
+     OUT   UINT32             *pMicrocodeVersion,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+LoadMicrocodePatchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  Update microcode patch in current processor.
+ *
+ *  Then reads the patch id, and compare it to the expected, in the Microprocessor
+ *  patch block.
+ *
+ *  @param[in] StdHeader   - Config handle for library and services.
+ *
+ *  @retval    TRUE   - Patch Loaded Successfully.
+ *  @retval    FALSE  - Patch Did Not Get Loaded.
+ *
+ */
+BOOLEAN
+LoadMicrocodePatch (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    PatchNumber;
+  UINT8    TotalPatches;
+  UINT16   ProcessorEquivalentId;
+  BOOLEAN  Status;
+  MICROCODE_PATCH **MicrocodePatchPtr;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  // Get the patch pointer
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (CONST VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader);
+
+  IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader);
+
+  // Get the processor microcode path equivalent ID
+  Status = GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader);
+  if (!Status) {
+    return (Status);
+  }
+
+  // parse the patch table to see if we have one for the current cpu
+  for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) {
+    Status = ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader);
+    if (Status) {
+      Status = LoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader);
+      if (!Status) {
+        PutEventLog (AGESA_ERROR,
+                     CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED,
+                     0, 0, 0, 0, StdHeader);
+      }
+      return (Status);
+    }
+  }
+
+  return (FALSE);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  LoadMicrocode
+ *
+ *    Update microcode patch in current processor, then reads the
+ *    patch id, and compare it to the expected, in the Microprocessor
+ *    patch block.
+ *
+ *    @param[in]       MicrocodePatchPtr  - Pointer to Microcode Patch.
+ *    @param[in,out]   StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          TRUE  - Patch Loaded Successfully.
+ *    @retval          FALSE - Patch Did Not Get Loaded.
+ *
+ */
+BOOLEAN
+STATIC
+LoadMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32       MicrocodeVersion;
+  PATCH_LOADER PatchLoaderMsr;
+
+  // Load microcode patch into CPU
+  PatchLoaderMsr.RawData = (UINT32) MicrocodePatchPtr;
+  PatchLoaderMsr.BitFields.SBZ = 0;
+  LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader);
+
+  // Do ucode patch Authentication
+  // Read microcode version back from CPU, determine if
+  // it is the same patch level as contained in the source
+  // microprocessor patch block passed in
+  GetMicrocodeVersion (&MicrocodeVersion, StdHeader);
+  if (MicrocodeVersion == MicrocodePatchPtr->PatchID) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  GetPatchEquivalentId
+ *
+ *    Return the equivalent ID for microcode patching
+ *
+ *    @param[in,out]   ProcessorEquivalentId   - Pointer to Processor Equivalent ID table.
+ *    @param[in,out]   StdHeader               - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          TRUE  - ID Found.
+ *    @retval          FALSE - ID Not Found.
+ *
+ */
+BOOLEAN
+STATIC
+GetPatchEquivalentId (
+  IN OUT   UINT16             *ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8        i;
+  UINT8        EquivalencyEntries;
+  UINT16       ProcessorRevisionId;
+  UINT16       *MicrocodeEquivalenceTable;
+  CPUID_DATA   CpuIdData;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  //
+  // compute the processor revision ID
+  //
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuIdData, StdHeader);
+  // high byte contains extended model and extended family
+  ProcessorRevisionId  = (UINT16) ((CpuIdData.EAX_Reg & (CPU_EMODEL | CPU_EFAMILY)) >> 8);
+  // low byte contains model and family
+  ProcessorRevisionId |= (CpuIdData.EAX_Reg & (CPU_STEPPING | CPU_MODEL));
+
+  //
+  // find the equivalent ID for microcode purpose using the equivalence table
+  //
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices,
+                                                        (CONST VOID **)&MicrocodeEquivalenceTable,
+                                                        &EquivalencyEntries,
+                                                        StdHeader);
+
+  // parse the equivalence table
+  for (i = 0; i < (EquivalencyEntries * 2); i += 2) {
+    // check for equivalence
+    if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) {
+      *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1];
+      return (TRUE);
+    }
+  }
+  // end of table reach, this processor is not supported
+  *ProcessorEquivalentId = 0x0000;
+  return (FALSE);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  ValidateMicrocode
+ *
+ *    Determine if the microcode patch block, currently pointed to
+ *    is valid, and is appropriate for the current processor
+
+ *    @param[in]       MicrocodePatchPtr      - Pointer to Microcode Patch.
+ *    @param[in]       ProcessorEquivalentId  - Pointer to Processor Equivalent ID table.
+ *    @param[in,out]   StdHeader              - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          TRUE  - Patch Found.
+ *    @retval          FALSE - Patch Not Found.
+ *
+ */
+BOOLEAN
+STATIC
+ValidateMicrocode (
+  IN       MICROCODE_PATCH    *MicrocodePatchPtr,
+  IN       UINT16             ProcessorEquivalentId,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BOOLEAN   Chipset1Matched;
+  BOOLEAN   Chipset2Matched;
+  PCI_ADDR  PciAddress;
+  UINT32    PciDeviceVidDid;
+  UINT8     PciDeviceRevision;
+  UINT8     DevCount;
+  UINT8     FunCount;
+  UINT32    Chipset1DeviceID;
+  UINT32    Chipset2DeviceID;
+  UINT8     MulitFunction;
+
+  Chipset1Matched = FALSE;
+  Chipset2Matched = FALSE;
+  PciDeviceVidDid = 0;
+  PciDeviceRevision = 0;
+  Chipset1DeviceID = MicrocodePatchPtr->Chipset1DeviceID;
+  Chipset2DeviceID = MicrocodePatchPtr->Chipset2DeviceID;
+  MulitFunction = 0;
+
+  //
+  // parse the supplied microcode to see if it is compatible with the processor
+  //
+  if (MicrocodePatchPtr->ProcessorRevisionID !=  ProcessorEquivalentId) {
+    return (FALSE);
+  }
+
+  if (Chipset1DeviceID == 0) {
+    Chipset1Matched = TRUE;
+  }
+  if (Chipset2DeviceID == 0) {
+    Chipset2Matched = TRUE;
+  }
+
+  if ((!Chipset1Matched) || (!Chipset2Matched)) {
+    //
+    // Scan all PCI devices in Bus 0, try to find out matched case.
+    //
+    for (DevCount = 0; DevCount < 32; DevCount++) {
+      for (FunCount = 0; FunCount < 8; FunCount++) {
+        PciAddress.AddressValue = MAKE_SBDFO (0, 0, DevCount, FunCount, 0);
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciDeviceVidDid, StdHeader);
+        if (PciDeviceVidDid == 0xFFFFFFFF) {
+          if (FunCount == 0) {
+            break;
+          } else {
+            continue;
+          }
+        }
+        PciAddress.Address.Register = 0x8;
+        LibAmdPciRead (AccessWidth8, PciAddress, &PciDeviceRevision, StdHeader);
+        if ((!Chipset1Matched) && (PciDeviceVidDid == Chipset1DeviceID)) {
+          if (PciDeviceRevision == MicrocodePatchPtr->Chipset1RevisionID) {
+            Chipset1Matched = TRUE;
+          }
+        }
+        if ((!Chipset2Matched) && (PciDeviceVidDid == Chipset2DeviceID)) {
+          if (PciDeviceRevision == MicrocodePatchPtr->Chipset2RevisionID) {
+            Chipset2Matched = TRUE;
+          }
+        }
+        if (Chipset1Matched && Chipset2Matched) {
+          break;
+        }
+        //
+        // Check multi-function. If it doesen't exist, we don't have to loop functions to 7.
+        //
+        if (FunCount == 0) {
+          MulitFunction = 0;
+          PciAddress.Address.Register = 0xE;
+          LibAmdPciRead (AccessWidth8, PciAddress, &MulitFunction, StdHeader);
+          if ((MulitFunction & 0x80) == 0) {
+            break;
+          }
+        }
+      } // end FunCount for loop.
+
+      if (Chipset1Matched && Chipset2Matched) {
+        break;
+      }
+    }  // end DevCount for loop.
+  }
+
+  return (Chipset1Matched && Chipset2Matched);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  GetMicrocodeVersion
+ *
+ *    Return the version of the currently loaded microcode patch, if any.
+ *    Read from the patch level MSR, return the value in eax. If no patch
+ *    has been loaded, 0 will be returned.
+ *
+ *    @param[out]      pMicrocodeVersion  - Pointer to Microcode Version.
+ *    @param[in,out]   StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+GetMicrocodeVersion (
+     OUT   UINT32             *pMicrocodeVersion,
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT64  MsrData;
+
+  MsrData = 0;
+  LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrData, StdHeader);
+
+  *pMicrocodeVersion = (UINT32) MsrData;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Update microcode patch in current processor.
+ *
+ * This function acts as a wrapper for calling the LoadMicrocodePatch
+ * routine at AmdInitEarly.
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+LoadMicrocodePatchAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
+  LoadMicrocodePatch (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPage.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPage.h
new file mode 100755
index 0000000000..e2b2926668
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPage.h
@@ -0,0 +1,60 @@
+/**
+ * @file
+ *
+ * Create outline and references for CPU Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page cpumain CPU Component Documentation
+ *
+ * Additional documentation for the CPU component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage cpuimplfss "CPU Family Specific Services Implementation Guide"
+ *   - @subpage regtableimpl  "Register Table Implementation Guide"
+ *   - @subpage cpufeatimpl  "CPU Generic Feature Implementation Guide"
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c
new file mode 100755
index 0000000000..ea97e73dbb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.c
@@ -0,0 +1,480 @@
+/**
+ * @file
+ *
+ * AMD CPU POST API, and related functions.
+ *
+ * Contains code that initialized the CPU after memory init.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6708 $   @e \$Date: 2008-07-10 18:04:19 -0500 (Thu, 10 Jul 2008) $
+ *
+ */
+/*
+ ****************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * Description: cpuPostInit.c - Cpu POST Initialization Functions.
+ *
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Options.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "GeneralServices.h"
+#include "cpuPostInit.h"
+#include "cpuPstateTables.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUPOSTINIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SyncVariableMTRR (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+STATIC
+SetCoresTscFreqSel (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+extern
+VOID
+ExecuteWbinvdInstruction (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+PstateCreateHeapInfo (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the POST entry point
+ *
+ * This function performs a large list of initialization items.  These items
+ * include:
+ *
+ *    -1      AP MTRR sync
+ *    -2      feature leveling
+ *    -3      P-state data gather
+ *    -4      P-state leveling
+ *    -5      AP cache breakdown & release
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  PlatformConfig    Config handle for platform specific information
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+AmdCpuPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+  //
+  // Sync variable MTRR
+  //
+  AGESA_TESTPOINT (TpProcCpuApMtrrSync, StdHeader);
+  SyncVariableMTRR (StdHeader);
+
+  AGESA_TESTPOINT (TpProcCpuPostFeatureInit, StdHeader);
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_POST_MTRR_SYNC, PlatformConfig, StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+  //
+  // Feature Leveling
+  //
+  AGESA_TESTPOINT (TpProcCpuFeatureLeveling, StdHeader);
+  FeatureLeveling (StdHeader);
+  //
+  // P-state Gathered and set heap info
+  //
+  PstateCreateHeapInfo (StdHeader);
+
+  // Set TscFreqSel at the rate specified by the core P0 after core frequency leveling.
+  SetCoresTscFreqSel (StdHeader);
+
+  // Relinquish control of all APs to IBV.
+  RelinquishControlOfAllAPs (StdHeader);
+
+  return (AgesaStatus);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the address in system DRAM that should be used for p-state data
+ * gather and leveling.
+ *
+ * @param[out] Ptr               Address to utilize
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+STATIC AGESA_STATUS
+GetPstateGatherDataAddressAtPost (
+     OUT   UINT64            **Ptr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 AddressValue;
+
+  AddressValue = (UINT32) P_STATE_DATA_GATHER_TEMP_ADDR;
+
+  *Ptr = (UINT64 *)(AddressValue);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * AP task to sync memory subsystem MSRs with the BSC
+ *
+ * This function processes a list of MSRs and the BSC's current values for those
+ * MSRs.  This will allow the APs to see system RAM.
+ *
+ * @param[in]  MtrrTable         Memory related MSR table
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+STATIC VOID
+SyncAllApMtrrToBsc (
+  IN       VOID *MtrrTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8   i;
+
+  for (i = 0; ((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress != 0; i++) {
+    LibAmdMsrWrite (((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress,
+                    &((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterValue,
+                    StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Creates p-state information on the heap
+ *
+ * This function gathers p-state information from all processors in the system,
+ * determines a level set of p-states, and places that information into the
+ * heap.  This heap data will be used by CreateAcpiTables to generate the
+ * final _PSS and XPSS objects.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS     No error
+ * @retval     AGESA_ERROR       CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE
+ */
+AGESA_STATUS
+PstateCreateHeapInfo (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS            AgesaStatus;
+  S_CPU_AMD_PSTATE        *PStateBufferPtr;
+  ALLOCATE_HEAP_PARAMS    AllocHeapParams;
+  UINT8                   *PStateBufferPtrInHeap;
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  //
+  //Get proper address for gather data pool address
+  //Zero P-state gather data pool
+  //
+  GetPstateGatherDataAddressAtPost ((UINT64 **)&PStateBufferPtr, StdHeader);
+  LibAmdMemFill (PStateBufferPtr, 0, sizeof (S_CPU_AMD_PSTATE), StdHeader);
+
+  //
+  //Get all the CPUs P-States and fill the PStateBufferPtr for each core
+  //
+  AgesaStatus = PStateGatherData (StdHeader, PStateBufferPtr);
+  if (AgesaStatus != AGESA_SUCCESS) {
+    return AgesaStatus;
+  }
+
+  //
+  //Do Pstate Leveling for each core if needed.
+  //
+  AgesaStatus = PStateLeveling (PStateBufferPtr, StdHeader);
+
+  //
+  //Create Heap and store p-state data for ACPI table in CpuLate
+  //
+  AllocHeapParams.RequestedBufferSize = (UINT16) (PStateBufferPtr->SizeOfBytes);
+  AllocHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    //
+    // Zero Buffer
+    //
+    PStateBufferPtrInHeap = (UINT8 *) AllocHeapParams.BufferPtr;
+    LibAmdMemFill (PStateBufferPtrInHeap, 0, PStateBufferPtr->SizeOfBytes, StdHeader);
+    LibAmdMemCopy  (PStateBufferPtrInHeap, PStateBufferPtr, PStateBufferPtr->SizeOfBytes, StdHeader);
+
+  } else {
+    PutEventLog (AGESA_ERROR,
+                   CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE,
+                 0, 0, 0, 0, StdHeader);
+  }
+
+  return AgesaStatus;
+}
+
+VOID
+SyncApMsrsToBsc (
+  IN OUT   BSC_AP_MSR_SYNC    *ApMsrSync,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT16                  i;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  //
+  //Sync all MTRR settings with BSP
+  //
+  for (i = 0; ApMsrSync[i].RegisterAddress != 0; i++) {
+    LibAmdMsrRead (ApMsrSync[i].RegisterAddress, &ApMsrSync[i].RegisterValue, StdHeader);
+  }
+
+  TaskPtr.FuncAddress.PfApTaskI = SyncAllApMtrrToBsc;
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((((sizeof (BSC_AP_MSR_SYNC)) * i) + 4) >> 2);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = ApMsrSync;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * SyncVariableMTRR
+ *
+ * Sync variable MTRR
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+SyncVariableMTRR (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BSC_AP_MSR_SYNC ApMsrSync[20];
+
+  ApMsrSync[0].RegisterAddress = SYS_CFG;
+  ApMsrSync[1].RegisterAddress = TOP_MEM;
+  ApMsrSync[2].RegisterAddress = TOP_MEM2;
+  ApMsrSync[3].RegisterAddress = 0x200;
+  ApMsrSync[4].RegisterAddress = 0x201;
+  ApMsrSync[5].RegisterAddress = 0x202;
+  ApMsrSync[6].RegisterAddress = 0x203;
+  ApMsrSync[7].RegisterAddress = 0x204;
+  ApMsrSync[8].RegisterAddress = 0x205;
+  ApMsrSync[9].RegisterAddress = 0x206;
+  ApMsrSync[10].RegisterAddress = 0x207;
+  ApMsrSync[11].RegisterAddress = 0x208;
+  ApMsrSync[12].RegisterAddress = 0x209;
+  ApMsrSync[13].RegisterAddress = 0x20A;
+  ApMsrSync[14].RegisterAddress = 0x20B;
+  ApMsrSync[15].RegisterAddress = 0xC0010016;
+  ApMsrSync[16].RegisterAddress = 0xC0010017;
+  ApMsrSync[17].RegisterAddress = 0xC0010018;
+  ApMsrSync[18].RegisterAddress = 0xC0010019;
+  ApMsrSync[19].RegisterAddress = 0;
+  SyncApMsrsToBsc (ApMsrSync, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The function suppose to do any thing need to be done at the end of AmdInitPost.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+FinalizeAtPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  //
+  // Execute wbinvd to ensure heap data in cache write back to memory.
+  //
+  ExecuteWbinvdInstruction (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set TSC Frequency Selection.
+ *
+ * This function set TSC Frequency Selection.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+SetTscFreqSel (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
+
+  FamilyServices = NULL;
+
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  if (FamilyServices != NULL) {
+    FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader);
+  }
+
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set TSC Frequency Selection to all cores.
+ *
+ * This function set TscFreqSel to all cores in the system.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+SetCoresTscFreqSel (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  SetTscFreqSel (StdHeader);
+
+  TaskPtr.FuncAddress.PfApTask = SetTscFreqSel;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != BscSocket) || (Core != BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h
new file mode 100755
index 0000000000..2534e8d1b2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPostInit.h
@@ -0,0 +1,234 @@
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-03 13:01:02 -0500 (Thu, 03 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POST_INIT_H_
+#define _CPU_POST_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+typedef struct _CPU_CFOH_FAMILY_SERVICES CPU_CFOH_FAMILY_SERVICES;
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define P_STATE_DATA_GATHER_TEMP_ADDR     0x200000 ///< Fixed the row data at 2M memory address.
+#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address.
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// CPU FEATURE LIST
+typedef struct {
+  UINT8  ABM:1;             ///< byte 0 bit 0
+  UINT8  AES:1;             ///< byte 0 bit 1
+  UINT8  AltMovCr8:1;       ///< byte 0 bit 2
+  UINT8  APIC:1;            ///< byte 0 bit 3
+  UINT8  AVX:1;             ///< byte 0 bit 4
+  UINT8  CLFSH:1;           ///< byte 0 bit 5
+  UINT8  CMOV:1;            ///< byte 0 bit 6
+  UINT8  CmpLegacy:1;       ///< byte 0 bit 7
+  UINT8  CMPXCHG8B:1;       ///< byte 1 bit 0
+  UINT8  CMPXCHG16B:1;      ///< byte 1 bit 1
+  UINT8  DE:1;              ///< byte 1 bit 2
+  UINT8  ExtApicSpace:1;    ///< byte 1 bit 3
+  UINT8  FFXSR:1;           ///< byte 1 bit 4
+  UINT8  FMA:1;             ///< byte 1 bit 5
+  UINT8  FPU:1;             ///< byte 1 bit 6
+  UINT8  FXSR:1;            ///< byte 1 bit 7
+  UINT8  HTT:1;             ///< byte 2 bit 0
+  UINT8  IBS:1;             ///< byte 2 bit 1
+  UINT8  LahfSahf:1;        ///< byte 2 bit 2
+  UINT8  LM:1;              ///< byte 2 bit 3
+  UINT8  MCA:1;             ///< byte 2 bit 4
+  UINT8  MCE:1;             ///< byte 2 bit 5
+  UINT8  MisAlignSse:1;     ///< byte 2 bit 6
+  UINT8  MMX:1;             ///< byte 2 bit 7
+  UINT8  MmxExt:1;          ///< byte 3 bit 0
+  UINT8  Monitor:1;         ///< byte 3 bit 1
+  UINT8  MSR:1;             ///< byte 3 bit 2
+  UINT8  MTRR:1;            ///< byte 3 bit 3
+  UINT8  NX:1;              ///< byte 3 bit 4
+  UINT8  OSVW:1;            ///< byte 3 bit 5
+  UINT8  OSXSAVE:1;         ///< byte 3 bit 6
+  UINT8  PAE:1;             ///< byte 3 bit 7
+  UINT8  Page1GB:1;         ///< byte 4 bit 0
+  UINT8  PAT:1;             ///< byte 4 bit 1
+  UINT8  PGE:1;             ///< byte 4 bit 2
+  UINT8  POPCNT:1;          ///< byte 4 bit 3
+  UINT8  PSE:1;             ///< byte 4 bit 4
+  UINT8  PSE36:1;           ///< byte 4 bit 5
+  UINT8  RDTSCP:1;          ///< byte 4 bit 6
+  UINT8  SKINIT:1;          ///< byte 4 bit 7
+  UINT8  SSE:1;             ///< byte 5 bit 0
+  UINT8  SSE2:1;            ///< byte 5 bit 1
+  UINT8  SSE3:1;            ///< byte 5 bit 2
+  UINT8  SSE4A:1;           ///< byte 5 bit 3
+  UINT8  SSE41:1;           ///< byte 5 bit 4
+  UINT8  SSE42:1;           ///< byte 5 bit 5
+  UINT8  SSE5:1;            ///< byte 5 bit 6
+  UINT8  SVM:1;             ///< byte 5 bit 7
+  UINT8  SysCallSysRet:1;   ///< byte 6 bit 0
+  UINT8  SysEnterSysExit:1; ///< byte 6 bit 1
+  UINT8  ThreeDNow:1;       ///< byte 6 bit 2
+  UINT8  ThreeDNowExt:1;    ///< byte 6 bit 3
+  UINT8  ThreeDNowPrefetch:1; ///< byte 6 bit 4
+  UINT8  TimeStampCounter:1;  ///< byte 6 bit 5
+  UINT8  VME:1;             ///< byte 6 bit 6
+  UINT8  WDT:1;             ///< byte 6 bit 7
+  UINT8  X2APIC:1;          ///< byte 7 bit 0
+  UINT8  XSAVE:1;           ///< byte 7 bit 1
+  UINT8  NodeId:1;          ///< byte 7 bit 2
+  UINT8  Reserve:5;         ///< Reserved
+} CPU_FEATURES_LIST;
+
+//----------------------------------------------------------------------------
+//                         POST INIT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// BSC to AP MSR sync up
+typedef struct {
+  UINT32 RegisterAddress;   ///< MSR Address
+  UINT64 RegisterValue;     ///< BSC's MSR Value
+} BSC_AP_MSR_SYNC;
+
+/**
+ *  Get Cache Flush On Halt Register.
+ *
+ *  @CpuServiceInstances
+ *
+ * @param[in]          FamilySpecificServices  The current Family Specific Services.
+ * @param[in, out]     PciAddress    Pci address struct.
+ * @param[in, out]     AndMask       AND mask to be applied to the value before saving.
+ * @param[in, out]     OrMask        OR mask to be applied to the value before saving.
+ * @param[in]          StdHeader     Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID (F_CPU_GET_CFOH_REG) (
+  IN       CPU_CFOH_FAMILY_SERVICES  *FamilySpecificServices,
+  IN OUT   PCI_ADDR *PciAddress,
+  IN OUT   UINT32 *AndMask,
+  IN OUT   UINT32 *OrMask,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+ /// Reference to a Method.
+typedef F_CPU_GET_CFOH_REG *PF_CPU_GET_CFOH_REG;
+
+/**
+ * Provide the interface to the Cache Flush On Halt Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CFOH_FAMILY_SERVICES {
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_CPU_GET_CFOH_REG GetCacheFlushOnHaltRegister;    ///< Method: Set down core register.
+};
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+//                   These are   P U B L I C   functions, used by IBVs
+AGESA_STATUS
+AmdCpuPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  );
+
+//                   These are   P U B L I C   functions, used by AGESA
+
+VOID
+FeatureLeveling (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CopyHeapToTempRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+PStateGatherData (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+AGESA_STATUS
+PStateLeveling (
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CpuGetPStateLevelStructure (
+     OUT   PSTATE_LEVELING     **PStateBufferPtr,
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       UINT32              LogicalSocketNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+SyncApMsrsToBsc (
+  IN OUT   BSC_AP_MSR_SYNC    *ApMsrSync,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+FinalizeAtPost (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _CPU_POST_INIT_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c
new file mode 100755
index 0000000000..e686f71b87
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmt.c
@@ -0,0 +1,243 @@
+/**
+ * @file
+ *
+ * AMD CPU Power Management functions.
+ *
+ * Contains code for doing early power management
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMultiSocket.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PerformThisPmStep (
+  IN       VOID *Step,
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+VOID
+STATIC
+GoToMemInitPstateCore0 (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+VOID
+STATIC
+GoToMemInitPstateCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform the "BIOS Requirements for P-State Initialization and Transitions."
+ *
+ * This is the generic arbiter code to be executed by the BSC.  The system power
+ * management init tables will be traversed.  This must be run by the system BSC
+ * only.
+ *
+ * @param[in]  CpuEarlyParams    Required input parameters for early CPU initialization
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return     Most severe AGESA_STATUS level that any system processor encountered
+ *
+ */
+AGESA_STATUS
+PmInitializationAtEarly (
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8        i;
+  UINT8        NumberOfSystemWideSteps;
+  AP_TASK      TaskPtr;
+  AGESA_STATUS ReturnCode;
+
+  // Determine the number of steps to perform
+  OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader);
+
+  // Traverse the PM init table
+  TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep;
+  TaskPtr.DataTransfer.DataSizeInDwords = 1;
+  TaskPtr.DataTransfer.DataPtr = &i;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  for (i = 0; i < NumberOfSystemWideSteps; ++i) {
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
+  }
+
+  if (IsWarmReset (StdHeader)) {
+    TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0;
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
+  }
+
+  // Retrieve/Process any errors
+  ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader);
+
+  return (ReturnCode);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs the next step in the executing core 0's family specific power
+ * management table.
+ *
+ * This function determines if the input step is valid, and invokes the power
+ * management step if appropriate.  This must be run by processor core 0s only.
+ *
+ * @param[in]  Step              Zero based step number
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+STATIC
+PerformThisPmStep (
+  IN       VOID *Step,
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  UINT8  MyNumberOfSteps;
+  SYS_PM_TBL_STEP *FamilyTablePtr;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **)&FamilyTablePtr, &MyNumberOfSteps, StdHeader);
+
+  if (*(UINT8 *)Step < MyNumberOfSteps) {
+    if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) {
+      if (!(BOOLEAN) (FamilyTablePtr[*(UINT8 *)Step].ExeFlags & PM_EXEFLAGS_WARM_ONLY) ||
+          IsWarmReset (StdHeader)) {
+        FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Transitions the executing processor to the desired P-state.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is
+ * run by all processor core 0s.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+STATIC
+GoToMemInitPstateCore0 (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  AP_TASK      TaskPtr;
+
+  TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Transitions the executing core to the desired P-state.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is
+ * run by all system cores.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  CpuEarlyParamsPtr Required input parameters for early CPU initialization
+ *
+ */
+VOID
+STATIC
+GoToMemInitPstateCore (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c
new file mode 100755
index 0000000000..795d148dd7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.c
@@ -0,0 +1,394 @@
+/**
+ * @file
+ *
+ * AMD CPU Power Management Multisocket Functions.
+ *
+ * Contains code for doing power management for multisocket CPUs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuPowerMgmtMultiSocket.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+GetNextEvent (
+  IN OUT   VOID  *EventLogEntryPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
+ *
+ * This function loops through all possible socket locations, starting core 0 of
+ * each populated socket to perform the passed in AP_TASK.  After starting all
+ * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by
+ * the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ */
+VOID
+RunCodeOnAllSystemCore0sMulti (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  )
+{
+  UINT32 BscSocket;
+  UINT32 BscModule;
+  UINT32 BscCore;
+  UINT8  Socket;
+  UINT32 NumberOfSockets;
+  AGESA_STATUS DummyStatus;
+
+  ASSERT (IsBsp (StdHeader, &DummyStatus));
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader);
+      }
+    }
+  }
+  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket BSC call to determine the maximum number of steps that any single
+ * processor needs to execute.
+ *
+ * This function loops through all possible socket locations, gathering the number
+ * of power management steps each populated socket requires, and returns the
+ * highest number.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+GetNumberOfSystemPmStepsPtrMulti (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  NumberOfSteps;
+  UINT32 NumberOfSockets;
+  UINT32 Socket;
+  SYS_PM_TBL_STEP *Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  *NumSystemSteps = 0;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
+      FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **)&Ignored, &NumberOfSteps, StdHeader);
+      if (NumberOfSteps > *NumSystemSteps) {
+        *NumSystemSteps = NumberOfSteps;
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket call to determine the frequency that the northbridges must run.
+ *
+ * This function loops through all possible socket locations, comparing the
+ * maximum NB frequencies to determine the slowest.  This function also
+ * determines if all coherent NB frequencies are equivalent.
+ *
+ * @param[out] SystemNbCof       NB frequency for the system in MHz
+ * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS     Always succeeds.
+ *
+ */
+AGESA_STATUS
+GetSystemNbCofMulti (
+     OUT   UINT32  *SystemNbCof,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32   Socket;
+  UINT8    Module;
+  UINT32   NumberOfSockets;
+  UINT32   CurrentNbCof;
+  UINT32   Ignored32;
+  BOOLEAN  FirstCofNotFound;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS ReturnCode;
+  AGESA_STATUS Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  ReturnCode = AGESA_SUCCESS;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  // Find the slowest NB COF in the system & whether or not all are equivalent
+  *SystemNbCofsMatch = TRUE;
+  FirstCofNotFound = TRUE;
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) {
+          break;
+        }
+      }
+      if ((FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, &CurrentNbCof, &Ignored32, StdHeader)) == AGESA_SUCCESS) {
+        if (FirstCofNotFound) {
+          *SystemNbCof = CurrentNbCof;
+          FirstCofNotFound = FALSE;
+        } else {
+          if (CurrentNbCof != *SystemNbCof) {
+            *SystemNbCofsMatch = FALSE;
+            if (CurrentNbCof < *SystemNbCof) {
+              *SystemNbCof = CurrentNbCof;
+            }
+          }
+        }
+      }
+    }
+  }
+  return (ReturnCode);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket call to determine if the BIOS is responsible for updating the
+ * northbridge operating frequency and voltage.
+ *
+ * This function loops through all possible socket locations, checking whether
+ * any populated sockets require NB COF VID programming.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     TRUE    BIOS needs to set up NB frequency and voltage
+ * @retval     FALSE   BIOS does not need to set up NB frequency and voltage
+ *
+ */
+BOOLEAN
+GetSystemNbCofVidUpdateMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8    Module;
+  UINT32   Socket;
+  UINT32   NumberOfSockets;
+  BOOLEAN  IgnoredBool;
+  BOOLEAN  AtLeast1RequiresUpdate;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  AtLeast1RequiresUpdate = FALSE;
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) {
+          break;
+        }
+      }
+      if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) {
+        AtLeast1RequiresUpdate = TRUE;
+        break;
+      }
+    }
+  }
+  return AtLeast1RequiresUpdate;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Multisocket call to determine the most severe AGESA_STATUS return value after
+ * processing the power management initialization tables.
+ *
+ * This function loops through all possible socket locations, collecting any
+ * power management initialization errors that may have occurred.  These errors
+ * are transferred from the core 0s of the socket in which the errors occurred
+ * to the BSC's heap.  The BSC's heap is then searched for the most severe error
+ * that occurred, and returns it.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return     The most severe error code from power management init
+ *
+ */
+AGESA_STATUS
+GetEarlyPmErrorsMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 i;
+  UINT32 BscSocket;
+  UINT32 BscModule;
+  UINT32 BscCore;
+  UINT32 Socket;
+  UINT32 NumberOfSockets;
+  AP_TASK      TaskPtr;
+  AGESA_EVENT  EventLogEntry;
+  AGESA_STATUS ReturnCode;
+  AGESA_STATUS DummyStatus;
+
+  ASSERT (IsBsp (StdHeader, &ReturnCode));
+
+  ReturnCode = AGESA_SUCCESS;
+  EventLogEntry.EventClass = AGESA_SUCCESS;
+  EventLogEntry.EventInfo = 0;
+  EventLogEntry.DataParam1 = 0;
+  EventLogEntry.DataParam2 = 0;
+  EventLogEntry.DataParam3 = 0;
+  EventLogEntry.DataParam4 = 0;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus);
+
+  TaskPtr.FuncAddress.PfApTaskI = GetNextEvent;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT);
+  TaskPtr.DataTransfer.DataPtr = &EventLogEntry;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS;
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        do {
+          ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader);
+          if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
+            PutEventLog (
+              EventLogEntry.EventClass,
+              EventLogEntry.EventInfo,
+              EventLogEntry.DataParam1,
+              EventLogEntry.DataParam2,
+              EventLogEntry.DataParam3,
+              EventLogEntry.DataParam4,
+              StdHeader
+              );
+          }
+        } while (EventLogEntry.EventInfo != 0);
+      }
+    }
+  }
+
+  for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
+    if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
+      if (EventLogEntry.EventClass > ReturnCode) {
+        ReturnCode = EventLogEntry.EventClass;
+      }
+    }
+  }
+  return (ReturnCode);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                           L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * AP task to return the next event log entry to the BSC.
+ *
+ * This function calls to the event log manager to retrieve the next error out
+ * of the heap.
+ *
+ * @param[out] EventLogEntryPtr  The AP's next event log entry
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+GetNextEvent (
+  IN OUT   VOID  *EventLogEntryPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.h
new file mode 100755
index 0000000000..e87155ba29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtMultiSocket.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD CPU Power Management Multisocket Functions.
+ *
+ * Contains code for doing power management for multisocket CPUs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POWER_MGMT_MULTI_SOCKET_H_
+#define _CPU_POWER_MGMT_MULTI_SOCKET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+RunCodeOnAllSystemCore0sMulti (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+VOID
+GetNumberOfSystemPmStepsPtrMulti (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GetSystemNbCofMulti (
+     OUT   UINT32 *SystemNbCof,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetSystemNbCofVidUpdateMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GetEarlyPmErrorsMulti (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_POWER_MGMT_MULTI_SOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
new file mode 100755
index 0000000000..fda1e9f18b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.c
@@ -0,0 +1,224 @@
+/**
+ * @file
+ *
+ * AMD CPU Power Management Single Socket Functions.
+ *
+ * Contains code for doing power management for single socket CPU
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuPowerMgmtSingleSocket.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
+ *
+ * This function will simply invoke the task on the executing core.  This must be
+ * run by the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ */
+VOID
+RunCodeOnAllSystemCore0sSingle (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  )
+{
+  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket BSC call to determine the maximum number of steps that any single
+ * processor needs to execute.
+ *
+ * This function simply returns the number of steps that the BSC needs.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+GetNumberOfSystemPmStepsPtrSingle (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  SYS_PM_TBL_STEP *Ignored;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **)&Ignored, NumSystemSteps, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket call to determine the frequency that the northbridges must run.
+ *
+ * This function simply returns the executing core's NB frequency, and that all
+ * NB frequencies are equivalent.
+ *
+ * @param[out] SystemNbCof       NB frequency for the system in MHz
+ * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @retval     AGESA_SUCCESS
+ *
+ */
+AGESA_STATUS
+GetSystemNbCofSingle (
+     OUT   UINT32 *SystemNbCof,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Ignored;
+  PCI_ADDR PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+  *SystemNbCofsMatch = TRUE;
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  return (FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, SystemNbCof, &Ignored, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket call to determine if the BIOS is responsible for updating the
+ * northbridge operating frequency and voltage.
+ *
+ * This function simply returns whether or not the executing core needs NB COF
+ * VID programming.
+ *
+ * @param[in]  StdHeader              Config handle for library and services
+ *
+ * @retval     TRUE    BIOS needs to set up NB frequency and voltage
+ * @retval     FALSE   BIOS does not need to set up NB frequency and voltage
+ *
+ */
+BOOLEAN
+GetSystemNbCofVidUpdateSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN   Ignored;
+  PCI_ADDR PciAddress;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Single socket call to determine the most severe AGESA_STATUS return value after
+ * processing the power management initialization tables.
+ *
+ * This function searches the event log for the most severe error and returns
+ * the status code.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return     The most severe error code from power management init
+ *
+ */
+AGESA_STATUS
+GetEarlyPmErrorsSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16       i;
+  AGESA_EVENT  EventLogEntry;
+  AGESA_STATUS ReturnCode;
+
+  ASSERT (IsBsp (StdHeader, &ReturnCode));
+
+  ReturnCode = AGESA_SUCCESS;
+  for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
+    if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
+      if (EventLogEntry.EventClass > ReturnCode) {
+        ReturnCode = EventLogEntry.EventClass;
+      }
+    }
+  }
+
+  return (ReturnCode);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.h
new file mode 100755
index 0000000000..8f00865564
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSingleSocket.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD CPU Power Management Single Socket Functions.
+ *
+ * Contains code for doing power management for single socket CPU
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POWER_MGMT_SINGLE_SOCKET_H_
+#define _CPU_POWER_MGMT_SINGLE_SOCKET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+RunCodeOnAllSystemCore0sSingle (
+  IN       AP_TASK *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+VOID
+GetNumberOfSystemPmStepsPtrSingle (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GetSystemNbCofSingle (
+     OUT   UINT32 *SystemNbCof,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetSystemNbCofVidUpdateSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GetEarlyPmErrorsSingle (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_POWER_MGMT_SINGLE_SOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h
new file mode 100755
index 0000000000..124085850c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuPowerMgmtSystemTables.h
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Power Management Table declarations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_POWER_MGMT_SYSTEM_TABLES_H_
+#define _CPU_POWER_MGMT_SYSTEM_TABLES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define PM_EXEFLAGS_WARM_ONLY    0x00000001   /* Skip step if set && cold reset */
+#define PM_EXEFLAGS_NOT_ON_S3    0x00000002   /* Skip step if S3 resume */
+#define PM_EXEFLAGS_SYSTEM_TASK  0x00000004   /* Future use */
+#define PM_EXEFLAGS_SERIAL_EXE   0x00000008   /* BSC will wait for remote core 0 to complete the step*/
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+typedef VOID F_PM_STEP_FUNCTION (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PM_STEP_FUNCTION *PF_PM_STEP_FUNCTION;
+
+
+/// A structure representing a step in a power management
+/// initialization process to be invoked at AmdInitEarly
+typedef struct {
+  UINT32  ExeFlags;                                   ///< Execution flags
+  PF_PM_STEP_FUNCTION FuncPtr;                        ///< Function pointer
+} SYS_PM_TBL_STEP;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h
new file mode 100755
index 0000000000..6a280871a1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuRegisters.h
@@ -0,0 +1,359 @@
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_REGISTERS_H_
+#define _CPU_REGISTERS_H_
+
+#include "cpuFamRegisters.h"
+/*
+ *--------------------------------------------------------------
+ *
+ *                      M O D U L E S    U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      D E F I N I T I O N S  /  M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+#define BIT0        0x0000000000000001ull
+#define BIT1        0x0000000000000002ull
+#define BIT2        0x0000000000000004ull
+#define BIT3        0x0000000000000008ull
+#define BIT4        0x0000000000000010ull
+#define BIT5        0x0000000000000020ull
+#define BIT6        0x0000000000000040ull
+#define BIT7        0x0000000000000080ull
+#define BIT8        0x0000000000000100ull
+#define BIT9        0x0000000000000200ull
+#define BIT10       0x0000000000000400ull
+#define BIT11       0x0000000000000800ull
+#define BIT12       0x0000000000001000ull
+#define BIT13       0x0000000000002000ull
+#define BIT14       0x0000000000004000ull
+#define BIT15       0x0000000000008000ull
+#define BIT16       0x0000000000010000ull
+#define BIT17       0x0000000000020000ull
+#define BIT18       0x0000000000040000ull
+#define BIT19       0x0000000000080000ull
+#define BIT20       0x0000000000100000ull
+#define BIT21       0x0000000000200000ull
+#define BIT22       0x0000000000400000ull
+#define BIT23       0x0000000000800000ull
+#define BIT24       0x0000000001000000ull
+#define BIT25       0x0000000002000000ull
+#define BIT26       0x0000000004000000ull
+#define BIT27       0x0000000008000000ull
+#define BIT28       0x0000000010000000ull
+#define BIT29       0x0000000020000000ull
+#define BIT30       0x0000000040000000ull
+#define BIT31       0x0000000080000000ull
+#define BIT32       0x0000000100000000ull
+#define BIT33       0x0000000200000000ull
+#define BIT34       0x0000000400000000ull
+#define BIT35       0x0000000800000000ull
+#define BIT36       0x0000001000000000ull
+#define BIT37       0x0000002000000000ull
+#define BIT38       0x0000004000000000ull
+#define BIT39       0x0000008000000000ull
+#define BIT40       0x0000010000000000ull
+#define BIT41       0x0000020000000000ull
+#define BIT42       0x0000040000000000ull
+#define BIT43       0x0000080000000000ull
+#define BIT44       0x0000100000000000ull
+#define BIT45       0x0000200000000000ull
+#define BIT46       0x0000400000000000ull
+#define BIT47       0x0000800000000000ull
+#define BIT48       0x0001000000000000ull
+#define BIT49       0x0002000000000000ull
+#define BIT50       0x0004000000000000ull
+#define BIT51       0x0008000000000000ull
+#define BIT52       0x0010000000000000ull
+#define BIT53       0x0020000000000000ull
+#define BIT54       0x0040000000000000ull
+#define BIT55       0x0080000000000000ull
+#define BIT56       0x0100000000000000ull
+#define BIT57       0x0200000000000000ull
+#define BIT58       0x0400000000000000ull
+#define BIT59       0x0800000000000000ull
+#define BIT60       0x1000000000000000ull
+#define BIT61       0x2000000000000000ull
+#define BIT62       0x4000000000000000ull
+#define BIT63       0x8000000000000000ull
+
+/// CPUID related registers
+#define AMD_CPUID_FMF               0x80000001  // Family Model Features information
+#define AMD_CPUID_APICID_LPC_BID    0x00000001  // Local APIC ID, Logical Processor Count, Brand ID
+#define AMD_CPUID_L2L3Cache_L2TLB   0x80000006
+#define AMD_CPUID_TLB_L1Cache       0x80000005
+#define AMD_CPUID_APM               0x80000007
+#define LOCAL_APIC_ID               24
+#define LOGICAL_PROCESSOR_COUNT     16
+#define AMD_CPUID_ASIZE_PCCOUNT     0x80000008  // Address Size, Physical Core Count
+
+/// CPU Logical ID Transfer
+typedef struct {
+  UINT32         RawId;                         ///< RawID
+  UINT64         LogicalId;                     ///< LogicalID
+} CPU_LOGICAL_ID_XLAT;
+
+/// Logical CPU ID Table
+typedef struct {
+  IN       UINT32  Elements;                    ///< Number of Elements
+  IN       CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
+} LOGICAL_ID_TABLE;
+
+// MSRs
+// ------------------------
+#define MCG_CTL_P                   0x00000100              // bit 8  for MCG_CTL_P under MSRR
+#define MSR_MCG_CAP                 0x00000179
+#define MSR_MC0_CTL                 0x00000400
+
+#define MSR_APIC_BAR                0x0000001B
+#define MSR_PATCH_LEVEL             0x0000008B
+
+#define CPUID_LONG_MODE_ADDR        0x80000008
+#define AMD_CPUID_FMF               0x80000001
+
+#define MSR_EXTENDED_FEATURE_EN     0xC0000080
+#define MSR_MC_MISC_LINK_THRESHOLD  0xC0000408
+#define MSR_MC_MISC_L3_THRESHOLD    0xC0000409
+#define MSR_PATCH_LOADER            0xC0010020
+
+/// Patch Loader Register
+typedef struct {
+  UINT64 PatchBase:32;                ///< Linear address of patch header address block
+  UINT64 SBZ:32;                      ///< Should be zero
+} PATCH_LOADER_MSR;
+
+#define MSR_SYS_CFG                 0xC0010010      // SYSCFG
+#define MSR_TOM2                    0xC001001D      // TOP_MEM2
+#define MSR_MC4_CTL_MASK            0xC0010048      // MC4 Control Mask
+
+#define MSR_CPUID_FEATS             0xC0011004      // CPUID Features
+#define MSR_CPUID_EXT_FEATS         0xC0011005      // CPUID Extended Features
+#define MSR_HWCR                    0xC0010015
+#define MSR_NB_CFG                  0xC001001F      // NB Config
+#define ENABLE_CF8_EXT_CFG          0x00004000      // [46]
+#define INIT_APIC_CPUID_LO          0x00400000      // [54]
+#define MSR_LS_CFG                  0xC0011020
+#define MSR_IC_CFG                  0xC0011021      // ICache Config
+#define MSR_DC_CFG                  0xC0011022
+#define MSR_BU_CFG                  0xC0011023
+#define MSR_DE_CFG                  0xC0011029
+#define MSR_BU_CFG2                 0xC001102A
+#define MSR_BU_CFG3                 0xC001102B
+#define MSR_IBS_OP_DATA3            0xC0011037
+#define MSR_CPUID_NAME_STRING0      0xC0010030      // First CPUID namestring register
+#define MSR_CPUID_NAME_STRING1      0xC0010031
+#define MSR_CPUID_NAME_STRING2      0XC0010032
+#define MSR_CPUID_NAME_STRING3      0xC0010033
+#define MSR_CPUID_NAME_STRING4      0xC0010034
+#define MSR_CPUID_NAME_STRING5      0xC0010035      // Last CPUID namestring register
+#define MSR_MMIO_Cfg_Base           0xC0010058      // MMIO Configuration Base Address Register
+#define MSR_BIST                    0xC0010060      // BIST Results register
+#define MSR_OSVW_ID_Length          0xC0010140
+#define MSR_OSVW_Status             0xC0010141
+#define MSR_PERF_CONTROL3           0xC0010003      // Perfromance control register number 3
+#define MSR_PERF_COUNTER3           0xC0010007      // Performance counter register number 3
+#define PERF_RESERVE_BIT_MASK       0x030FFFDFFFFFull  // Mask of the Performance control Reserve bits
+#define PERF_CAR_CORRUPTION_EVENT   0x040040F0E2ull    // Configure the controller to capture the
+                                                    // CAR Corruption
+// FUNC_0 registers
+// ----------------
+#define HT_LINK_FREQ_OFFSET         8           // Link HT Frequency from capability base
+#define HT_LINK_TYPE_REG_OFFSET     0x18
+#define HT_LINK_EXTENDED_FREQ       0x1C
+#define HT_LINK_HOST_CAP_MAX        0x20        // HT Host Capability offsets are less than its size.
+#define HT_CAPABILITIES_POINTER     0x34
+#define NODE_ID                     0x60
+#define HT_INIT_CTRL                0x6C
+#define HT_INIT_CTRL_REQ_DIS        0x02        // [1] = ReqDis
+#define HI_INIT_COLD_RST_DET        BIT4
+#define HT_INIT_BIOS_RST_DET_0      BIT5
+#define HT_INIT_BIOS_RST_DET_1      BIT9
+#define HT_INIT_BIOS_RST_DET_2      BIT10
+#define HT_INIT_BIOS_RST_DET        BIT9 | BIT10
+#define HT_TRANS_CTRL               0x68
+#define HT_TRANS_CTRL_CPU1_EN       0x00000020  // [5] = CPU1 Enable
+#define HT_LINK_CONTROL_0           0x84
+#define HT_LINK_FREQ_0              0x88        // Link HT Frequency
+#define EXTENDED_NODE_ID            0x160
+#define ECS_HT_TRANS_CTRL           0x168
+#define ECS_HT_TRANS_CTRL_CPU2_EN   0x00000001  // [0] = CPU2 Enable
+#define ECS_HT_TRANS_CTRL_CPU3_EN   0x00000002  // [1] = CPU3 Enable
+#define ECS_HT_TRANS_CTRL_CPU4_EN   0x00000004  // [2] = CPU4 Enable
+#define ECS_HT_TRANS_CTRL_CPU5_EN   0x00000008  // [3] = CPU5 Enable
+
+// FUNC_3 registers
+// ----------------
+#define HARDWARE_THERMAL_CTRL_REG       0x64
+#define SOFTWARE_THERMAL_CTRL_REG       0x68
+
+#define ACPI_PSC_0_REG                  0x80    // ACPI Power State Control Registers
+#define ACPI_PSC_4_REG                  0x84
+
+#define NB_CFG_HIGH_REG                 0x8C
+#define POWER_CTRL_MISCELLANEOUS_REG    0xA0
+#define CLOCK_POWER_TIMING_CTRL2_REG    0xDC
+#define NORTH_BRIDGE_CAPABILITIES_REG   0xE8
+#define MULTI_NODE_CPU                  29
+#define CPUID_FMR                       0xFC    // Family / Model registers
+#define DOWNCORE_CTRL                   0x190   // Downcore Control Register
+
+#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
+#define REG_HT4_PHY_OFFSET_BASE_4X180    0x180
+#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
+
+#define HTPHY_OFFSET_MASK         0xE00001FF
+#define HTPHY_WRITE_CMD           0x40000000
+#define HTPHY_IS_COMPLETE_MASK    0x80000000
+#define HTPHY_DIRECT_MAP          0x20000000
+#define HTPHY_DIRECT_OFFSET_MASK  0xE000FFFF
+
+// Misc. defines.
+#define PCI_DEV_BASE    24
+
+#define CPU_STEPPING    0x0000000F
+#define CPU_MODEL       0x000000F0
+#define CPU_EMODEL      0x000F0000
+#define CPU_EFAMILY     0x00F00000
+#define CPU_FMS_MASK    CPU_EFAMILY | CPU_EMODEL | CPU_MODEL | CPU_STEPPING
+
+#define HTPHY_SELECT        2
+#define PCI_SELECT          1
+#define MSR_SELECT          0
+
+#define LOGICAL_ID      1
+#define F_SCHEME        0
+#define DR_SCHEME       1
+#define GR_SCHEME       2
+
+#define DR_NO_STRING        0
+#define DR_SOCKET_C32       5
+#define DR_SOCKET_ASB2      4
+#define DR_SOCKET_G34       3
+#define DR_SOCKET_S1G3      2
+#define DR_SOCKET_S1G4      2
+#define DR_SOCKET_AM3       1
+#define DR_SOCKET_1207      0
+#define LN_SOCKET_FM1       2
+#define LN_SOCKET_FS1       1
+#define LN_SOCKET_FP1       0
+#define SOCKET_IGNORE       0xF
+
+#define LAPIC_BASE_ADDR_MASK    0x0000FFFFFFFFF000ull
+#define APIC_EXT_BRDCST_MASK    0x000E0000
+#define APIC_ENABLE_BIT         0x00000800
+#define LOCAL_APIC_ADDR         0xFEE00000
+#define INT_CMD_REG_LO          0x300
+#define INT_CMD_REG_HI          0x310
+#define REMOTE_MSG_REG          0x380
+#define REMOTE_READ_REG         0xC0
+#define APIC_ID_REG             0x20
+#define APIC20_ApicId           24
+#define CMD_REG_TO_READ_DATA    0x338
+
+#define MAX_CORE_ID_SIZE 8
+#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
+
+/*-------------------------
+ * Default definitions
+ *-------------------------
+ */
+#define DOWNCORE_MASK_SINGLE    0x3E
+#define DOWNCORE_MASK_DUAL      0x3C
+#define DOWNCORE_MASK_TRI       0x38
+#define DOWNCORE_MASK_FOUR      0x30
+#define DOWNCORE_MASK_FIVE      0x20
+
+#define DELIVERY_STATUS             BIT13
+#define REMOTE_READ_STAT_MASK       0x00030000
+#define REMOTE_DELIVERY_PENDING     0x00010000
+#define REMOTE_DELIVERY_DONE        0x00020000
+
+/*
+ * --------------------------------------------------------------------------------------
+ *
+ *             D E F I N E S    /   T Y P E D E F S   /  S T R U C T U R E S
+ *
+ * --------------------------------------------------------------------------------------
+ */
+
+/// CpuEarly param type
+typedef struct {
+  IN       UINT8                  MemInitPState;        ///< Pstate value during memory initial
+  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< Runtime configurable user options
+} AMD_CPU_EARLY_PARAMS;
+
+/// Enum - Will be used to access each structure
+///        related to each CPU family
+typedef enum {
+  REVF,                                       ///< NPT, RevF
+  REVG,                                       ///< NPT, RevG
+  DEERHOUND,                                  ///< Family 10h, Deerhound
+  GRIFFIN                                     ///< Family 11h, Griffin
+} CPU_FAMILY;
+
+/// CPUID
+typedef enum {
+  REG_EAX,                                    ///< EAX
+  REG_EBX,                                    ///< EBX
+  REG_ECX,                                    ///< ECX
+  REG_EDX                                     ///< EDX
+} CPUID_REG;
+
+typedef struct {
+  UINT16 Limit;        ///< Interrupt Descriptor Table size
+  UINT64 Base;         ///< Interrupt Descriptor Table base address
+} IDT_BASE_LIMIT;
+
+
+#endif      // _CPU_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuServices.h
new file mode 100755
index 0000000000..2eba7b7d52
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuServices.h
@@ -0,0 +1,256 @@
+/**
+ * @file
+ *
+ * AMD CPU Services
+ *
+ * Related to the General Services API's, but for the CPU component.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_SERVICES_H_
+#define _CPU_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+ /// WARM RESET STATE_BITS
+#define WR_STATE_COLD  00
+#define WR_STATE_RESET 01
+#define WR_STATE_EARLY 02
+#define WR_STATE_POST  03
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+//                         CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// SYSTEM INFO
+typedef struct _SYSTEM_INFO {
+  UINT32            TotalNumberOfSockets;               ///< Total Number of Sockets
+  UINT32            TotalNumberOfCores;                 ///< Total Number Of Cores
+  UINT32            CurrentSocketNum;                   ///< Current Socket Number
+  UINT32            CurrentCoreNum;                     ///< Current Core Number
+  UINT32            CurrentCoreApicId;                  ///< Current Core Apic ID
+  UINT32            CurrentLogicalCpuId;                ///< Current Logical CPU ID
+} SYSTEM_INFO;
+
+/// WARM_RESET
+typedef struct _WARM_RESET_REQUEST {
+  UINT8             RequestBit:1;                       ///< Request Bit
+  UINT8             StateBits:2;                        ///< State Bits
+  UINT8             Reserved:(8-3);                     ///< Reserved
+} WARM_RESET_REQUEST;
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GetCurrentNodeNum (
+     OUT   UINT32 *Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get the current Platform's number of Sockets, regardless of how many are populated.
+ *
+ */
+UINT32
+GetPlatformNumberOfSockets (VOID);
+
+/**
+ * Get the number of Modules to check presence in each Processor.
+ *
+ */
+UINT32
+GetPlatformNumberOfModules (VOID);
+
+BOOLEAN
+IsProcessorPresent (
+  IN       UINT32            Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * For a specific Node, get its Socket and Module ids.
+ *
+ */
+BOOLEAN
+GetSocketModuleOfNode (
+  IN       UINT32    Node,
+     OUT   UINT32    *Socket,
+     OUT   UINT32    *Module,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Get the current core's Processor APIC Index.
+ */
+UINT32
+GetProcessorApicIndex (
+  IN       UINT32            Node,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  Writes to all nodes on the executing core's socket.
+ *
+ */
+VOID
+ModifyCurrentSocketPci (
+  IN       PCI_ADDR          *PciAddress,
+  IN       UINT32            Mask,
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * Provide the number of installed processors (not Nodes! and not Sockets!)
+ */
+UINT32
+GetNumberOfProcessors (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetActiveCoresInCurrentSocket (
+     OUT   UINT32 *CoreCount,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+GetActiveCoresInGivenSocket (
+  IN       UINT32             Socket,
+     OUT   UINT32             *CoreCount,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINTN
+GetActiveCoresInCurrentModule (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+BOOLEAN
+GetGivenModuleCoreRange (
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   UINT32            *LowCore,
+     OUT   UINT32            *HighCore,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetCurrentCore (
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetCurrentNodeAndCore (
+     OUT   UINT32 *Node,
+     OUT   UINT32 *Core,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+IsCurrentCorePrimary (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+GetApMailbox (
+     OUT   UINT32               *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+CacheApMailbox (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+UINTN
+GetSystemDegree (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+GetNodeId (
+  IN       UINT32  SocketId,
+  IN       UINT32  ModuleId,
+     OUT   UINT8   *NodeId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+WaitMicroseconds (
+  IN       UINT32 Microseconds,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+VOID
+GetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  );
+
+BOOLEAN
+IsWarmReset (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+CheckBistStatus (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _CPU_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
new file mode 100755
index 0000000000..af4cb1b0e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuWarmReset.c
@@ -0,0 +1,188 @@
+/**
+ * @file
+ *
+ * AMD CPU Warm Reset Implementation.
+ *
+ * Implement Warm Reset Interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_CPUWARMRESET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will set the CPU register warm reset bits.
+ *
+ *    Note: This function will be called by UEFI BIOS's
+ *    The UEFI wrapper code should register this function, to be called back later point
+ *    in time, before the wrapper code does warm reset.
+ *
+ *    @param[in] StdHeader Config handle for library and services
+ *    @param[in] Request   Indicate warm reset status
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+SetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will get the CPU register warm reset bits.
+ *
+ *    Note: This function will be called by UEFI BIOS's
+ *    The UEFI wrapper code should register this function, to be called back later point
+ *    in time, before the wrapper code does warm reset.
+ *
+ *    @param[in] StdHeader Config handle for library and services
+ *    @param[out] Request   Indicate warm reset status
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+GetWarmResetFlag (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
+}
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S - (AGESA ONLY)
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is this boot a warm reset?
+ *
+ * This function reads the CPU register warm reset bit that is preserved after a warm reset.
+ * Which in fact gets set before issuing warm reset.  We just use the BSP's register always.
+ *
+ * @param[in]       StdHeader       Config handle for library and services
+ *
+ * @retval      TRUE            Warm Reset
+ * @retval      FALSE           Not Warm Reset
+ *
+ */
+BOOLEAN
+IsWarmReset (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 PostStage;
+  WARM_RESET_REQUEST Request;
+  BOOLEAN  WarmReset;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  FamilySpecificServices = NULL;
+
+  switch (StdHeader->Func) {
+  case AMD_INIT_RESET:
+    PostStage = WR_STATE_RESET;
+    break;
+  case AMD_INIT_EARLY:
+    PostStage = WR_STATE_EARLY;
+    break;
+  case AMD_INIT_POST:
+  default:
+    PostStage = WR_STATE_POST;
+    break;
+  }
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
+
+  if (Request.StateBits >= PostStage) {
+    WarmReset = TRUE;
+  } else {
+    WarmReset = FALSE;
+  }
+
+  return WarmReset;
+}
+
+/*----------------------------------------------------------------------------------------
+ *                            L O C A L    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
new file mode 100755
index 0000000000..b5be972444
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
@@ -0,0 +1,593 @@
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_HEAPMANAGER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  This function initializes the heap for each CPU core.
+ *
+ *  Check for already initialized.  If not, determine offset of local heap in CAS and
+ *  setup initial heap markers and bookkeeping status.  Initialize a couple heap items
+ *  all cores need, for convenience.  Currently these are caching the AP mailbox info and
+ *  an initial event log.
+ *
+ *  @param[in]  StdHeader          Handle of Header for calling lib functions and services.
+ *
+ *  @retval     AGESA_SUCCESS      This core's heap is initialized (always succeeds)
+ *
+ */
+AGESA_STATUS
+HeapManagerInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // First Time Initialization
+  // Note: First 16 bytes of buffer is reserved for Heap Manager use
+  UINT16                HeapAlreadyInitSizeDword;
+  UINT8                 *HeapBufferPtr;
+  UINT32                *HeapDataPtr;
+  UINT64                MsrData;
+  UINT8                 Ignored;
+  CACHE_INFO            *CacheInfoPtr;
+  AGESA_STATUS          IgnoredSts;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader);
+
+  if (!IsBsp (StdHeader, &IgnoredSts)) {
+    // APs must transfer their system core number from the mailbox to
+    // a local register while it is still valid.
+    FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader);
+  }
+
+  HeapBufferPtr = (UINT8 *) HeapGetCurrentBase (StdHeader);
+  // check whether the heap manager is already initialized
+  LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
+  if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) {
+    LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
+    if ((MsrData & 0xFFFFFFFFFFFFFF00ull) == (UINT32) HeapBufferPtr) {
+      // This is not a bug, there are multiple premem basic entry points,
+      // and each will call heap init to make sure create struct will succeed.
+      // If that is later deemed a problem, there needs to be a reasonable test
+      // for the calling code to make to determine if it needs to init heap or not.
+      // In the mean time, add this to the event log
+      PutEventLog (AGESA_SUCCESS,
+                   CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED,
+                   0, 0, 0, 0, StdHeader);
+      return AGESA_SUCCESS;
+    }
+  }
+
+  // set variable MTRR base and mask
+  MsrData = (UINT32) HeapBufferPtr;
+  MsrData |= 0x06;
+  LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
+  MsrData = CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK;
+  LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
+
+  // set top of memory to a temp value
+  MsrData = (UINT64) (AMD_TEMP_TOM);
+  LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
+
+  // Enable variable MTTRs
+  LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
+  MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
+  LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
+
+  // Initialize Heap Space
+  HeapDataPtr = (UINT32 *) HeapBufferPtr;
+  for (HeapAlreadyInitSizeDword = 0; HeapAlreadyInitSizeDword < AMD_HEAP_SIZE_DWORD_PER_CORE; HeapAlreadyInitSizeDword++) {
+    *HeapDataPtr = 0;
+    HeapDataPtr++;
+  }
+
+  // Save size of heap (which is contiguous right now) for later use
+  // Note: We are reserving the first 16 bytes for Heap Manager use
+  ((HEAP_MANAGER*) HeapBufferPtr)->AvailableSize = (AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER));
+
+  StdHeader->HeapStatus = HEAP_LOCAL_CACHE;
+  if (!IsBsp (StdHeader, &IgnoredSts)) {
+    // The BSP's hardware mailbox has not been initialized, so only APs
+    // can do this at this point.
+    CacheApMailbox (StdHeader);
+  }
+  EventLogInitialization (StdHeader);
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap
+ *
+ * This function determines if whether or not there is enough space for the
+ * new structure.  If so, it will zero out the buffer, and return a pointer
+ * to the region.
+ *
+ * @param[in,out]  AllocateHeapParamsPtr Structure containing the size of the
+ *                                   desired new region, its handle, and the
+ *                                   return pointer.
+ * @param[in,out]  StdHeader         Config handle for library and services.
+ *
+ * @retval         AGESA_SUCCESS     No error
+ * @retval         AGESA_BOUNDS_CHK  Handle already exists, or not enough
+ *                                   free space
+ *
+ */
+AGESA_STATUS
+HeapAllocateBuffer (
+  IN OUT   ALLOCATE_HEAP_PARAMS *AllocateHeapParamsPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8       *HeapBufferPtr;
+  UINT8       *StartOfBufferPtr;
+  HEAP_MANAGER *HeapManagerPtr;
+  BUFFER_NODE *HeadNodePtr;
+  BUFFER_NODE *CurrentNodePtr;
+  BUFFER_NODE *NextNodePtr;
+  AGESA_BUFFER_PARAMS  AgesaBuffer;
+  UINT32      AmdHeapRamAddress;
+
+  AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
+
+  // Buffer pointer is NULL unless we return a buffer.
+  AllocateHeapParamsPtr->BufferPtr = NULL;
+
+  // check to see where the heap is
+  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
+    HeapBufferPtr = (UINT8 *) HeapGetCurrentBase (StdHeader);
+  } else if (StdHeader->HeapStatus == HEAP_TEMP_MEM) {
+    HeapBufferPtr = (UINT8 *) AmdHeapRamAddress;
+  } else if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
+    AgesaBuffer.StdHeader = *StdHeader;
+    AgesaBuffer.BufferHandle = AllocateHeapParamsPtr->BufferHandle;
+    AgesaBuffer.BufferLength = AllocateHeapParamsPtr->RequestedBufferSize;
+
+    AGESA_TESTPOINT (TpIfBeforeAllocateHeapBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+      AllocateHeapParamsPtr->BufferPtr = NULL;
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpIfAfterAllocateHeapBuffer, StdHeader);
+
+    AllocateHeapParamsPtr->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer);
+    return AGESA_SUCCESS;
+  } else if (StdHeader->HeapStatus == HEAP_S3_RESUME) {
+    HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+  } else {
+    AllocateHeapParamsPtr->BufferPtr = NULL;
+    // Heap buffer is not present.
+    return AGESA_BOUNDS_CHK;
+  }
+
+  HeapManagerPtr = (HEAP_MANAGER *) HeapBufferPtr;
+  StartOfBufferPtr = HeapBufferPtr + sizeof (HEAP_MANAGER);
+  HeadNodePtr = (BUFFER_NODE *) StartOfBufferPtr;
+  CurrentNodePtr = HeadNodePtr;
+
+  // Check if we can allocate space
+  if (AllocateHeapParamsPtr->RequestedBufferSize > (HeapManagerPtr->AvailableSize - sizeof (BUFFER_NODE) - 2 * SIZE_OF_SENTINEL)) {
+    PutEventLog (AGESA_BOUNDS_CHK,
+                 CPU_ERROR_HEAP_IS_FULL,
+                 AllocateHeapParamsPtr->BufferHandle, 0, 0, 0, StdHeader);
+    return AGESA_BOUNDS_CHK;
+  }
+
+  if (HeadNodePtr->BufferSize == 0) {
+    NextNodePtr = CurrentNodePtr;
+  } else {
+    // locate the last heap, but if there already has been a heap with the incoming BufferHandle, we return AGESA_BOUNDS_CHK.
+    while (CurrentNodePtr->NextNodePtr != NULL) {
+      if (CurrentNodePtr->BufferHandle == AllocateHeapParamsPtr->BufferHandle) {
+        PutEventLog (AGESA_BOUNDS_CHK,
+                     CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED,
+                     AllocateHeapParamsPtr->BufferHandle, 0, 0, 0, StdHeader);
+        return AGESA_BOUNDS_CHK;
+      }
+      if (StdHeader->HeapStatus == HEAP_S3_RESUME) {
+        HeapBufferPtr = (UINT8 *) CurrentNodePtr;
+        CurrentNodePtr = (BUFFER_NODE *) &HeapBufferPtr[CurrentNodePtr->BufferSize + sizeof (BUFFER_NODE) + (2 * SIZE_OF_SENTINEL)];
+      } else {
+        CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+      }
+    }
+    if (CurrentNodePtr->BufferHandle == AllocateHeapParamsPtr->BufferHandle) {
+      PutEventLog (AGESA_BOUNDS_CHK,
+                   CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED,
+                   AllocateHeapParamsPtr->BufferHandle, 0, 0, 0, StdHeader);
+      return AGESA_BOUNDS_CHK;
+    }
+
+    // Create a new node and link it with previous node
+    CurrentNodePtr->NextNodePtr = (BUFFER_NODE *)
+                                  (((UINT8 *) CurrentNodePtr) +
+                                   sizeof (BUFFER_NODE) +
+                                   CurrentNodePtr->BufferSize +
+                                   2 * SIZE_OF_SENTINEL);
+    NextNodePtr = CurrentNodePtr->NextNodePtr;
+  }
+  NextNodePtr->BufferSize = AllocateHeapParamsPtr->RequestedBufferSize;
+  NextNodePtr->NextNodePtr = NULL;
+  NextNodePtr->BufferHandle = AllocateHeapParamsPtr->BufferHandle;
+
+  // Debug feature
+  SET_SENTINEL_BEFORE (NextNodePtr);
+  SET_SENTINEL_AFTER (NextNodePtr);
+
+ // Persist
+  if ((AllocateHeapParamsPtr->Persist == HEAP_TEMP_MEM) || (AllocateHeapParamsPtr->Persist == HEAP_SYSTEM_MEM)) {
+    NextNodePtr->Persist = AllocateHeapParamsPtr->Persist;
+  } else {
+    NextNodePtr->Persist = HEAP_LOCAL_CACHE;
+  }
+
+  // Update global variables
+  HeapManagerPtr->AvailableSize -= NextNodePtr->BufferSize + sizeof (BUFFER_NODE) + 2 * SIZE_OF_SENTINEL;
+
+  // Now fill in the incoming structure
+  AllocateHeapParamsPtr->BufferPtr = (UINT8 *) ((UINT8 *) NextNodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL);
+  Heap_Check (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Deallocates a previously allocated buffer in the heap
+ *
+ * This function finds the buffer to deallocate, defragments the remaining
+ * heap, clears the new remainder, and updates the size of the heap.
+ *
+ * @param[in]      BufferHandle      Handle of the buffer to free.
+ * @param[in]      StdHeader         Config handle for library and services.
+ *
+ * @retval         AGESA_SUCCESS     No error
+ * @retval         AGESA_BOUNDS_CHK  Handle does not exist on the heap
+ *
+ */
+AGESA_STATUS
+HeapDeallocateBuffer (
+  IN       UINT32 BufferHandle,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16      AboveDeallocationHeapSize;
+  UINT16      DeallocationHeapSize;
+  UINT16      BelowDeallocationHeapSize;
+  UINT16      i;
+  UINT8       *HeapBufferPtr;
+  UINT8       *HeapDataPtr1;
+  UINT8       *HeapDataPtr2;
+  HEAP_MANAGER *HeapManagerPtr;
+  BUFFER_NODE *HeadNodePtr;
+  BUFFER_NODE *PreviousNodePtr;
+  BUFFER_NODE *CurrentNodePtr;
+  BUFFER_NODE *NextNodePtr;
+  AGESA_BUFFER_PARAMS  AgesaBuffer;
+  UINT32      AmdHeapRamAddress;
+
+  AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
+
+  AboveDeallocationHeapSize = 0;
+
+  // Step 1: locate the heap which is expected to be deallocated.
+  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
+    HeapBufferPtr = (UINT8 *) HeapGetCurrentBase (StdHeader);
+  } else if (StdHeader->HeapStatus == HEAP_TEMP_MEM) {
+    HeapBufferPtr = (UINT8 *) AmdHeapRamAddress;
+  } else if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
+    AgesaBuffer.StdHeader = *StdHeader;
+    AgesaBuffer.BufferHandle = BufferHandle;
+
+    AGESA_TESTPOINT (TpIfBeforeDeallocateHeapBuffer, StdHeader);
+    if (AgesaDeallocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpIfAfterDeallocateHeapBuffer, StdHeader);
+
+    return AGESA_SUCCESS;
+  } else {
+    // Heap buffer is not present.
+    IDS_ERROR_TRAP;
+    return AGESA_BOUNDS_CHK;
+  }
+
+  HeapManagerPtr = (HEAP_MANAGER *) HeapBufferPtr;
+  HeadNodePtr = (BUFFER_NODE *) ((HeapBufferPtr + sizeof (HEAP_MANAGER)));
+  CurrentNodePtr = HeadNodePtr;
+  PreviousNodePtr = CurrentNodePtr;
+
+  while (CurrentNodePtr->BufferHandle != BufferHandle) {
+    AboveDeallocationHeapSize += (CurrentNodePtr->BufferSize) + sizeof (BUFFER_NODE) + 2 * SIZE_OF_SENTINEL;
+    PreviousNodePtr = CurrentNodePtr;
+    if (CurrentNodePtr->NextNodePtr == NULL) {
+      // If we are at the end of the heap and still unable to locate the buffer handle, return AGESA_BOUNDS_CHK
+      PutEventLog (AGESA_BOUNDS_CHK,
+                   CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT,
+                   BufferHandle, 0, 0, 0, StdHeader);
+      return AGESA_BOUNDS_CHK;
+    } else {
+      CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+    }
+  }
+
+  // Step 2: defragment
+
+  // Before:
+  //  ------------------------ <- UINT8 * HeapBufferPtr
+  //  | Heap Manager 16 Bytes|
+  //  ------------------------  ---
+  //  | Heap 1               |  AboveDeallocationHeapSize
+  //  |                      |
+  //  ------------------------  ---
+  //  | Heap 2               | <- Deallocate
+  //  |                      |  DeallocationHeapSize
+  //  ------------------------  ---
+  //  | Heap 3               |  BelowDeallocationHeapSize
+  //  |                      |
+  //  ------------------------  ---
+  //  | Unused               |  UnusedSize = HeapManagerPtr->AvailableSize
+  //  ------------------------  ---
+  //  After deallocating: shift all subsequent heap buffers up
+  //  ------------------------
+  //  | Heap Manager 16 Bytes|
+  //  ------------------------
+  //  | Heap 1               |
+  //  |                      |
+  //  ------------------------
+  //  | Heap 3               |
+  //  |                      |
+  //  ------------------------
+  //  |                      |
+  //  |                      |
+  //  | Unused               |
+  //  ------------------------
+  DeallocationHeapSize = (CurrentNodePtr->BufferSize) + sizeof (BUFFER_NODE) + 2 * SIZE_OF_SENTINEL;
+  BelowDeallocationHeapSize = AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER)
+                              - HeapManagerPtr->AvailableSize
+                              - AboveDeallocationHeapSize
+                              - DeallocationHeapSize;
+  HeapDataPtr1 = (UINT8 *) CurrentNodePtr;
+
+  // if this is the last Heap, then PreviousNodePtr->NextNodePtr = NULL and return
+  if (CurrentNodePtr->NextNodePtr == NULL) {
+    PreviousNodePtr->NextNodePtr = NULL;
+  } else {
+    HeapDataPtr2 = (UINT8 *) (CurrentNodePtr->NextNodePtr);
+    // subtract DeallocationHeapSize from all subsequent NextNodePtr
+    CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+    while (CurrentNodePtr->NextNodePtr != NULL) {
+      NextNodePtr = CurrentNodePtr->NextNodePtr;
+      CurrentNodePtr->NextNodePtr = (BUFFER_NODE *) ((UINT8 *) (CurrentNodePtr->NextNodePtr) - DeallocationHeapSize);
+      CurrentNodePtr = NextNodePtr;
+    }
+    // shift subsequent heap buffers up
+    for (i = 0; i < BelowDeallocationHeapSize; i++) {
+      *HeapDataPtr1 = *HeapDataPtr2;
+      HeapDataPtr1++;
+      HeapDataPtr2++;
+    }
+  }
+
+  // Step 3: clear remainder useless data
+  LibAmdMemFill (HeapDataPtr1, 0, DeallocationHeapSize, StdHeader);
+
+  // Step 4: update unused size
+  HeapManagerPtr->AvailableSize = HeapManagerPtr->AvailableSize + DeallocationHeapSize;
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locates a previously allocated buffer on the heap.
+ *
+ * This function searches the heap for a buffer with the desired handle, and
+ * returns a pointer to the buffer.
+ *
+ * @param[in,out]  LocateHeapPtr     Structure containing the buffer's handle,
+ *                                   and the return pointer.
+ * @param[in]      StdHeader         Config handle for library and services.
+ *
+ * @retval         AGESA_SUCCESS     No error
+ * @retval         AGESA_BOUNDS_CHK  Handle does not exist on the heap
+ *
+ */
+AGESA_STATUS
+HeapLocateBuffer (
+  IN OUT   LOCATE_HEAP_PTR *LocateHeapPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8       *HeapBufferPtr;
+  UINT8       *StartOfBufferPtr;
+  HEAP_MANAGER *HeapManagerPtr;
+  BUFFER_NODE *HeadNodePtr;
+  BUFFER_NODE *CurrentNodePtr;
+  BOOLEAN     BufferHandleFlag;
+  AGESA_BUFFER_PARAMS  AgesaBuffer;
+  UINT32  AmdHeapRamAddress;
+
+  AmdHeapRamAddress = (UINT32) UserOptions.CfgHeapDramAddress;
+
+  ASSERT (StdHeader != NULL);
+
+  BufferHandleFlag = TRUE;
+
+  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
+    HeapBufferPtr = (UINT8 *) HeapGetCurrentBase (StdHeader);
+  } else if (StdHeader->HeapStatus == HEAP_TEMP_MEM) {
+    HeapBufferPtr = (UINT8 *) AmdHeapRamAddress;
+  } else if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
+    AgesaBuffer.StdHeader = *StdHeader;
+    AgesaBuffer.BufferHandle = LocateHeapPtr->BufferHandle;
+
+    AGESA_TESTPOINT (TpIfBeforeLocateHeapBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+      LocateHeapPtr->BufferPtr = NULL;
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateHeapBuffer, StdHeader);
+
+    LocateHeapPtr->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer);
+    return AGESA_SUCCESS;
+  } else if (StdHeader->HeapStatus == HEAP_S3_RESUME) {
+    HeapBufferPtr = (UINT8 *) (UINT32) StdHeader->HeapBasePtr;
+  } else {
+    return AGESA_BOUNDS_CHK;
+  }
+
+  HeapManagerPtr = (HEAP_MANAGER *) HeapBufferPtr;
+  StartOfBufferPtr = HeapBufferPtr + sizeof (HEAP_MANAGER);
+  HeadNodePtr = (BUFFER_NODE *) StartOfBufferPtr;
+  CurrentNodePtr = HeadNodePtr;
+
+  while (CurrentNodePtr->BufferHandle != LocateHeapPtr->BufferHandle) {
+    if (CurrentNodePtr->NextNodePtr == NULL) {
+      BufferHandleFlag = FALSE;
+      break;
+    } else {
+      if (StdHeader->HeapStatus == HEAP_S3_RESUME) {
+        HeapBufferPtr = (UINT8 *) CurrentNodePtr;
+        CurrentNodePtr = (BUFFER_NODE *) &HeapBufferPtr[CurrentNodePtr->BufferSize + sizeof (BUFFER_NODE) + (2 * SIZE_OF_SENTINEL)];
+      } else {
+        CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+      }
+    }
+  }
+
+  if (BufferHandleFlag) {
+    LocateHeapPtr->BufferPtr = (UINT8 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL);
+    return AGESA_SUCCESS;
+  } else {
+    LocateHeapPtr->BufferPtr = NULL;
+    PutEventLog (AGESA_BOUNDS_CHK,
+                 CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT,
+                 LocateHeapPtr->BufferHandle, 0, 0, 0, StdHeader);
+    return AGESA_BOUNDS_CHK;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Determines the base address of the executing core's heap.
+ *
+ * This function uses the executing core's socket/core numbers to determine
+ * where it's heap should be located.
+ *
+ * @param[in]      StdHeader      Config handle for library and services.
+ *
+ * @return         A pointer to the executing core's heap.
+ *
+ */
+VOID *
+HeapGetCurrentBase (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32      SystemCoreNumber;
+  UINT64      ReturnPtr;
+  AGESA_STATUS          IgnoredStatus;
+  CPU_SPECIFIC_SERVICES *FamilyServices;
+
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    ReturnPtr = AMD_HEAP_START_ADDRESS;
+  } else {
+    GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+
+    SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader);
+    ASSERT (SystemCoreNumber != 0);
+    ASSERT (SystemCoreNumber < 64);
+    ReturnPtr = ((SystemCoreNumber * AMD_HEAP_SIZE_PER_CORE) + AMD_HEAP_START_ADDRESS);
+  }
+  ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
+  return ((VOID *) (UINT32) ReturnPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.h
new file mode 100755
index 0000000000..81f784ccb0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.h
@@ -0,0 +1,221 @@
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _HEAP_MANAGER_H_
+#define _HEAP_MANAGER_H_
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define AMD_END_OF_NODE             0x5F4F4E45  // _EON - END OF NODE
+#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
+#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
+
+#define AMD_HEAP_START_ADDRESS  0x400000
+#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF
+#define AMD_HEAP_SIZE_PER_CORE  0x010000
+#define AMD_HEAP_MTRR_MASK (((0xFFFFFFFFFFFFF800ull & ((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800))
+#define AMD_HEAP_SIZE_DWORD_PER_CORE  (AMD_HEAP_SIZE_PER_CORE / 4)
+
+#define AMD_TEMP_TOM            0x20000000  // Set TOM to 512 MB (temporary value)
+#define AMD_VAR_MTRR_ENABLE_BIT 0x100000    // bit 20
+
+#define AMD_HEAP_RAM_ADDRESS    0xB0000
+#define AMD_HEAP_COPY_SIZE_DWORD  AMD_HEAP_SIZE_PER_CORE / 4
+
+#define MAX_CORES_PER_CPU       16
+
+///Heap Manager Life cycle
+#define HEAP_DO_NOT_EXIST_YET        1
+#define HEAP_LOCAL_CACHE             2
+#define HEAP_TEMP_MEM                3
+#define HEAP_SYSTEM_MEM              4
+#define HEAP_DO_NOT_EXIST_ANYMORE    5
+#define HEAP_S3_RESUME               6
+
+
+#define AMD_MTRR_FIX64k_00000    0x250
+#define AMD_MTRR_FIX16k_80000    0x258
+#define AMD_MTRR_FIX16k_A0000    0x259
+#define AMD_MTRR_FIX4k_C0000     0x268
+#define AMD_MTRR_FIX4k_C8000     0x269
+#define AMD_MTRR_FIX4k_D0000     0x26A
+#define AMD_MTRR_FIX4k_D8000     0x26B
+#define AMD_MTRR_FIX4k_E0000     0x26C
+#define AMD_MTRR_FIX4k_E8000     0x26D
+#define AMD_MTRR_FIX4k_F0000     0x26E
+#define AMD_MTRR_FIX4k_F8000     0x26F
+
+#define AMD_MTRR_FIX64K_WB_DRAM  0x1E
+#define AMD_MTRR_FIX64K_WT_DRAM  0x1C
+#define AMD_MTRR_FIX16K_WB_DRAM  0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX16K_WT_DRAM  0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX4K_WB_DRAM   0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX4K_WT_DRAM   0x1C1C1C1C1C1C1C1Cull
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Allocate Heap Parameters
+typedef struct _ALLOCATE_HEAP_PARAMS {
+  IN  UINT16  RequestedBufferSize;                ///< Size of buffer.
+  IN  UINT32  BufferHandle;                       ///< An unique ID of buffer.
+  UINT8       Persist;                            ///< A flag. If marked, to be stored and passed to AmdInitLate.
+  OUT UINT8   *BufferPtr;                         ///< Pointer to buffer.
+} ALLOCATE_HEAP_PARAMS;
+
+/// Locate Heap Parameters
+typedef struct _LOCATE_HEAP_PTR {
+  UINT32  BufferHandle;                           ///< An unique ID of buffer.
+  UINT8   *BufferPtr;                             ///< Pointer to buffer.
+} LOCATE_HEAP_PTR;
+
+/// Heap Node Header
+typedef struct _BUFFER_NODE {
+  UINT32        BufferHandle;                     ///< An unique ID of buffer.
+  UINT16        BufferSize;                       ///< Size of buffer.
+  UINT8         Persist;                          ///< A flag. If marked, to be stored and passed to AmdInitLate.
+  struct  _BUFFER_NODE  *NextNodePtr;             ///< Pointer to next Node.
+} BUFFER_NODE;
+
+/// Heap Manager
+typedef struct _HEAP_MANAGER {
+  UINT16 AvailableSize;                           ///< Available size of heap.
+  UINT16 Reserved1;                               ///< This space is reserved for future use.
+  UINT32 Reserved2;                               ///< This space is reserved for future use.
+  UINT64 Reserved3;                               ///< This space is reserved for future use.
+} HEAP_MANAGER;
+
+/// AGESA Buffer Handles (These are reserved)
+typedef enum {
+  AMD_INIT_RESET_HANDLE = 0x000A000,              ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
+  AMD_INIT_EARLY_HANDLE,                          ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
+  AMD_INIT_POST_HANDLE,                           ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
+  AMD_INIT_ENV_HANDLE,                            ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
+  AMD_INIT_MID_HANDLE,                            ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
+  AMD_INIT_LATE_HANDLE,                           ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
+  AMD_INIT_RESUME_HANDLE,                         ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
+  AMD_LATE_RUN_AP_TASK_HANDLE,                    ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
+  AMD_S3_SAVE_HANDLE,                             ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
+  AMD_S3_LATE_RESTORE_HANDLE,                     ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
+  AMD_S3_SCRIPT_SAVE_TABLE_HANDLE,                ///< Assign 0x000A00A buffer handle to be used for S3 save table
+  AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE,               ///< Assign 0x000A00B buffer handle to be used for S3 save table
+  AMD_CPU_AP_TASKING_HANDLE,                      ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
+  AMD_REC_MEM_SOCKET_HANDLE,                      ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
+  AMD_MEM_AUTO_HANDLE,                            ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
+  AMD_MEM_SPD_HANDLE,                             ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
+  AMD_MEM_DATA_HANDLE,                            ///< Assign 0x000A010 buffer handle to MemData
+  AMD_MEM_TRAIN_BUFFER_HANDLE,                    ///< Assign 0x000A011 buffer handle to allocate buffer for training
+  AMD_MEM_S3_DATA_HANDLE,                         ///< Assign 0x000A012 buffer handle to special case register for S3
+  AMD_MEM_S3_NB_HANDLE,                           ///< Assign 0x000A013 buffer handle to NB block for S3
+  AMD_UMA_INFO_HANDLE,                            ///< Assign 0x000A014 buffer handle to be used for Uma information
+  AMD_DMI_MEM_DEV_INFO_HANDLE,                    ///< Assign 0x000A015 buffer handle to DMI Type16 17 19 20 information
+  HT_STATE_DATA_HANDLE,                           ///< Assign 0x000A016 buffer handle to HT State Data
+  PRESERVE_MAIL_BOX_HANDLE,                       ///< Assign 0x000A017 buffer handle for Preserve Mailbox Feature.
+  EVENT_LOG_BUFFER_HANDLE,                        ///< Assign 0x000A018 buffer handle to Event Log
+  IDS_CONTROL_HANDLE,                             ///< Assign 0x000A019 buffer handle to AmdIds routine.
+  IDS_HT_DATA_HANDLE,                             ///< Assign 0x000A01A buffer handle to Ht IDS control
+  IDS_HDT_OUT_BUFFER_HANDLE,                      ///< Assign 0x000A01B buffer handle to be used for HDTOUT support.
+  IDS_CHECK_POINT_PERF_HANDLE,                    ///< Assign 0x000A01C buffer handle to Performance analysis
+  IDS_GRA_HANDLE,                                 ///< Assign 0x000A01D buffer handle to be used for GRA support
+  AMD_PCIE_COMPLEX_DATA_HANDLE,                   ///< Assign 0x000A01E buffer handle to be used for PCIe support
+  AMD_GNB_SMU_CONFIG_HANDLE,                      ///< Assign 0x000A01F buffer handle to be used for GNB SMU configuration
+  AMD_PP_FUSE_TABLE_HANDLE,                       ///< Assign 0x000A020 buffer handle to be used for TT fuse table
+  AMD_GFX_PLATFORM_CONFIG_HANDLE,                 ///< Assign 0x000A021 buffer handle to be used for Gfx platform configuration
+  AMD_MEM_MISC_HANDLES_START = 0x1000000,         ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
+  AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF,           ///< miscellaneous memory init tasks' buffers.
+  AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000,     ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
+  SOCKET_DIE_MAP_HANDLE = 0x534F4B54,             ///< 'sokt'
+  NODE_ID_MAP_HANDLE = 0x4E4F4445,                ///< 'node'
+  HOP_COUNT_TABLE_HANDLE = 0x484F5053,            ///< 'hops'
+  LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258     ///< 'ambx'
+} AGESA_BUFFER_HANDLE;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+HeapManagerInit (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+HeapAllocateBuffer (
+  IN OUT   ALLOCATE_HEAP_PARAMS *AllocateHeapParamsPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+  IN       UINT32 BufferHandle,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+HeapLocateBuffer (
+  IN OUT   LOCATE_HEAP_PTR *LocateHeapPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID *
+HeapGetCurrentBase (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+EventLogInitialization (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif // _HEAP_MANAGER_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
new file mode 100755
index 0000000000..582bc6ac14
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEarly.c
@@ -0,0 +1,255 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "AdvancedApi.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "CommonInits.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+EXECUTION_CACHE_REGION InitExeCacheMap[] =
+{
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitEarly stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AmdEarlyPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by the wrapper to initialize the input
+ * structure for the AllocateExecutionCache.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   AmdExeAddrMapPtr  Our Service interface struct
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AllocateExecutionCacheInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  UINT8 i;
+  ASSERT (AmdExeAddrMapPtr != NULL);
+
+  for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr;
+    AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Initializer routine that will be invoked by the wrapper to initialize the input
+ *  structure for the AmdInitEarly.
+ *
+ *  @param[in]      StdHeader       AMD standard header config param.
+ *  @param[in,out]  EarlyParams     The service interface struct to initialize.
+ *
+ *  @retval         AGESA_SUCCESS   Always succeeds.
+ */
+AGESA_STATUS
+AmdInitEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (EarlyParams != NULL);
+
+  EarlyParams->StdHeader = *StdHeader;
+
+  // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED.
+  //
+
+  AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
+
+  AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig);
+
+  AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform initialization services required at the Early Init POST time point.
+ *
+ * Execution Cache, HyperTransport, and AP Init advanced services are performed.
+ *
+ * @param[in]     EarlyParams  The interface struct for all early services
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.
+ *
+ */
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  )
+{
+  AGESA_STATUS  CalledAgesaStatus;
+  AGESA_STATUS  EarlyInitStatus;
+  WARM_RESET_REQUEST Request;
+
+  AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
+  ASSERT (EarlyParams != NULL);
+  EarlyInitStatus = AGESA_SUCCESS;
+
+  GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+
+  IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader);
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // Full Hypertransport Initialization
+  // IMPORTANT: All AP cores call Ht Init.  HT Init handles full init for the BSC, and map init for APs.
+  CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // AP launch
+  CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig);
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+
+  // Warm Rest, should be at the end of AmdInitEarly
+  GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    Request.RequestBit = FALSE;
+    Request.StateBits = WR_STATE_EARLY;
+    SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+    AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader);
+  } else {
+    if (Request.StateBits < WR_STATE_EARLY) {
+      Request.StateBits = WR_STATE_EARLY;
+      SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
+    }
+  }
+
+  CalledAgesaStatus = GnbInitAtEarly (
+                        &EarlyParams->StdHeader,
+                        &EarlyParams->PlatformConfig,
+                        &EarlyParams->GnbConfig
+                        );
+  if (CalledAgesaStatus > EarlyInitStatus) {
+    EarlyInitStatus = CalledAgesaStatus;
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_AFTER_WARM_RESET, EarlyParams, &EarlyParams->StdHeader);
+  IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader);
+  return  EarlyInitStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
new file mode 100755
index 0000000000..0b58c60498
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitEnv.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuEnvInit.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "GnbInterface.h"
+#include "CommonInits.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITENV_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitEnv
+ *
+ *  @param[in,out]  EnvParamsPtr   Newly created interface parameters for AmdInitEnv
+ *
+ *  @retval         AGESA_SUCCESS  Always succeeds
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitEnvInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_ENV_PARAMS    *EnvParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (EnvParamsPtr != NULL);
+
+  EnvParamsPtr->StdHeader = *StdHeader;
+
+  CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_ENV function.
+ *
+ * This entry point is responsible for copying the heap contents from the
+ * temp RAM area to main memory.
+ *
+ * @param[in,out] EnvParams         Required input parameters for the AMD_INIT_ENV
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD env calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS  *EnvParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitEnvStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
+
+  ASSERT (EnvParams != NULL);
+  AmdInitEnvStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
+
+  //Copy Temp Ram heap content to Main Ram
+  AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+  EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+
+  AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+
+  AgesaStatus = GnbInitAtEnv (&EnvParams->StdHeader);
+  if (AgesaStatus > AmdInitEnvStatus) {
+    AmdInitEnvStatus = AgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
+  return  AmdInitEnvStatus;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
new file mode 100755
index 0000000000..aedd8964f7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitLate.c
@@ -0,0 +1,269 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionDmi.h"
+#include "OptionSlit.h"
+#include "cpuLateInit.h"
+#include "cpuFeatures.h"
+#include "CommonInits.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_DMI_CONFIGURATION    OptionDmiConfiguration;  // global user config record
+extern OPTION_SLIT_CONFIGURATION   OptionSlitConfiguration; // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitLate stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AmdLatePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitLateInitializer
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitLate
+ *
+ *  @param[in, out]    IN OUT   AMD_LATE_PARAMS *LateParamsPtr
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitLateInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_LATE_PARAMS   *LateParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (LateParamsPtr != NULL);
+
+  LateParamsPtr->StdHeader = *StdHeader;
+
+  AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader);
+
+  LateParamsPtr->AcpiSlit = NULL;
+
+  LateParamsPtr->AcpiSrat = NULL;
+
+  LateParamsPtr->AcpiWheaMce = NULL;
+  LateParamsPtr->AcpiWheaCmc = NULL;
+
+  LateParamsPtr->AcpiPState = NULL;
+
+  LateParamsPtr->DmiTable = NULL;
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitLateDestructor
+ *
+ *  Destruct routine that provide a chance if something need to be done
+ *  before the end of AmdInitLate.
+ *
+ *  @param[in]    StdHeader       The standard header.
+ *  @param[in]    LateParamsPtr   AMD init late param.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitLateDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_LATE_PARAMS   *LateParamsPtr
+  )
+{
+
+  ASSERT (LateParamsPtr != NULL);
+
+  (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader);
+  (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_LATE function.
+ *
+ * This entry point is responsible for creating any desired ACPI tables, providing
+ * information for DMI, and to prepare the processors for the operating system
+ * bootstrap load process.
+ *
+ * @param[in,out] LateParams     Required input parameters for the AMD_INIT_LATE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD late calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS *LateParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitLateStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
+
+  ASSERT (LateParams != NULL);
+  AmdInitLateStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader);
+
+  // _PSS, XPSS, _PCT, _PSD, _PPC Tables
+  if (LateParams->PlatformConfig.UserOptionPState) {
+    AgesaStatus = CreateAcpiTables (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // SRAT Table Generation
+  if (LateParams->PlatformConfig.UserOptionSrat) {
+    AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // SLIT Table Generation
+  if (LateParams->PlatformConfig.UserOptionSlit) {
+    AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // WHEA Table Generation
+  if (LateParams->PlatformConfig.UserOptionWhea) {
+    AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // DMI Table Generation
+  if (LateParams->PlatformConfig.UserOptionDmi) {
+    AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable);
+    if (AgesaStatus > AmdInitLateStatus) {
+      AmdInitLateStatus = AgesaStatus;
+    }
+  }
+
+  // Cpu Features
+  AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader);
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  // It is the last function run by the AGESA CPU module and prepares the processor
+  // for the operating system bootstrap load process.
+  AgesaStatus = AmdCpuLate (&LateParams->StdHeader);
+  if (AgesaStatus > AmdInitLateStatus) {
+    AmdInitLateStatus = AgesaStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader);
+  AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader);
+  return  AmdInitLateStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
new file mode 100755
index 0000000000..88c0da5c9d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitMid.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "CommonInits.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITMID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitMid
+ *
+ *  @param[in,out]  MidParamsPtr   Newly created interface parameters for AmdInitMid
+ *
+ *  @retval         AGESA_SUCCESS  Always succeeds
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitMidInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_MID_PARAMS    *MidParamsPtr
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (MidParamsPtr != NULL);
+
+  MidParamsPtr->StdHeader = *StdHeader;
+  CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_MID function.
+ *
+ * This entry point is responsible for performing any necessary functions needed
+ * after PCI bus enumeration and just before control is passed to the video option ROM.
+ *
+ * @param[in,out] MidParams      Required input parameters for the AMD_INIT_MID
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD mid calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS *MidParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  CalledStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);
+  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  ASSERT (MidParams != NULL);
+  IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);
+
+
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  CalledStatus = GnbInitAtMid (&MidParams->StdHeader);
+  if (CalledStatus > AgesaStatus) {
+    AgesaStatus = CalledStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);
+
+  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);
+
+  return AgesaStatus;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
new file mode 100755
index 0000000000..50b22c1bae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitPost.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuPostInit.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "CommonInits.h"
+#include "cpuServices.h"
+#include "GnbInterface.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdInitPost stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+AmdPostPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitPostInitializer
+ *
+ *  Initializer routine that will be invoked by the wrapper
+ *  to initialize the input structure for the AmdInitPost
+ *
+ *  @param[in, out]    IN OUT   AMD_POST_PARAMS *PostParamsPtr
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitPostInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_POST_PARAMS   *PostParamsPtr
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PostParamsPtr != NULL);
+
+  PostParamsPtr->StdHeader = *StdHeader;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+  AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader);
+
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
+    PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig);
+    PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader;
+    AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader);
+    AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig);
+  }
+  return AgesaStatus;
+}
+
+/*
+ *---------------------------------------------------------------------------------------
+ *
+ *  AmdInitPostDestructor
+ *
+ *  Destruct routine that provide a chance if something need to be done
+ *  before the end of AmdInitPost.
+ *
+ *  @param[in]    StdHeader       The standard header.
+ *  @param[in]    PostParamsPtr   AMD init post param.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdInitPostDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_POST_PARAMS   *PostParamsPtr
+  )
+{
+
+  ASSERT (PostParamsPtr != NULL);
+
+  PostParamsPtr->StdHeader = *StdHeader;
+  PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader;
+
+  //
+  // AmdMemAuto completed. Here, release heap space which is used for memory init.
+  //
+  MemAmdFinalize (PostParamsPtr->MemConfig.MemData);
+  HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+
+  //
+  // AmdCpuPost completed.
+  //
+  FinalizeAtPost (StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_POST function.
+ *
+ * This entry point is responsible for initializing all system memory,
+ * gathering important data out of the pre-memory cache storage into a
+ * temporary holding buffer in main memory. After that APs will be
+ * shutdown in preparation for the host environment to take control.
+ * Note: pre-memory stack will be disabled also.
+ *
+ * @param[in,out] PostParams     Required input parameters for the AMD_INIT_POST
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD POST calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS *PostParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  AmdInitPostStatus;
+  WARM_RESET_REQUEST Request;
+
+  AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
+
+  IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
+
+  ASSERT (PostParams != NULL);
+  AmdInitPostStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_MEM_INIT, PostParams, &PostParams->StdHeader);
+
+  GetWarmResetFlag (&PostParams->StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  SetWarmResetFlag (&PostParams->StdHeader, &Request);
+
+  AgesaStatus = GnbInitAtPost (
+                  &PostParams->StdHeader,
+                  &PostParams->MemConfig
+                  );
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
+  if (AgesaStatus > AmdInitPostStatus) {
+    AmdInitPostStatus = AgesaStatus;
+  }
+
+  if (AgesaStatus != AGESA_FATAL) {
+
+    IDS_OPTION_HOOK (IDS_INIT_POST_MID, PostParams, &PostParams->StdHeader);
+
+    // Check BIST status
+    AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+
+    //
+    // P-State data gathered, then, Relinquish APs
+    //
+    AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+
+    // Warm Reset
+    GetWarmResetFlag (&PostParams->StdHeader, &Request);
+    if (Request.RequestBit == TRUE) {
+      Request.RequestBit = FALSE;
+      Request.StateBits = WR_STATE_POST;
+      SetWarmResetFlag (&PostParams->StdHeader, &Request);
+      AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
+    } else {
+      if (Request.StateBits < WR_STATE_POST) {
+        Request.StateBits = WR_STATE_POST;
+        SetWarmResetFlag (&PostParams->StdHeader, &Request);
+      }
+    }
+
+    IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
+
+    IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
+    AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
+
+    // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
+    AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
+    if (AgesaStatus > AmdInitPostStatus) {
+      AmdInitPostStatus = AgesaStatus;
+    }
+    PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
+  return  AmdInitPostStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
new file mode 100755
index 0000000000..096efe20f9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitRecovery.c
@@ -0,0 +1,165 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 7359 $   @e \$Date: 2008-08-13 01:53:23 +0800 (Wed, 13 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "mm.h"
+#include "GnbInterface.h"
+#include "cpuRecovery.h"
+#include "cpuCacheInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITRECOVERY_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Perform initialization services required at the Early Init POST time point.
+ *
+ * Execution Cache, HyperTransport, C1e, and AP Init advanced services are performed.
+ *
+ * @param[in, out]     RecoveryParams  The interface struct for Recovery services
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.
+ *
+ */
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS      *RecoveryParams
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  CalledAgesaStatus;
+
+  AGESA_TESTPOINT (TpIfAmdInitRecoveryEntry, &RecoveryParams->StdHeader);
+
+  ASSERT (RecoveryParams != NULL);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&RecoveryParams->StdHeader, &RecoveryParams->CacheRegion[0]);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdHtInitRecovery (&RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdCpuRecovery ((AMD_CPU_RECOVERY_PARAMS *) &RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdMemRecovery (RecoveryParams->MemConfig.MemData);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  CalledAgesaStatus = AmdGnbRecovery (&RecoveryParams->StdHeader);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdInitRecoveryExit, &RecoveryParams->StdHeader);
+  return  AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Initialize defaults and options for Amd Init Reset.
+ *
+ * @param[in]  StdHeader              AMD standard header config param.
+ * @param[in]  AmdRecoveryParamsPtr   The Reset Init interface to initialize.
+ *
+ * @retval     AGESA_SUCCESS    Always Succeeds.
+ */
+AGESA_STATUS
+AmdInitRecoveryInitializer (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN OUT   AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (AmdRecoveryParamsPtr != NULL);
+
+  AmdRecoveryParamsPtr->StdHeader = *StdHeader;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+  AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &AmdRecoveryParamsPtr->StdHeader) == AGESA_SUCCESS) {
+    AmdRecoveryParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
+    AmdRecoveryParamsPtr->MemConfig.MemData->ParameterListPtr = &(AmdRecoveryParamsPtr->MemConfig);
+    LibAmdMemCopy ((VOID *) AmdRecoveryParamsPtr->MemConfig.MemData,
+                   (VOID *) AmdRecoveryParamsPtr,
+                   (UINTN) sizeof (AmdRecoveryParamsPtr->StdHeader),
+                   &AmdRecoveryParamsPtr->StdHeader
+                  );
+    AmdMemInitDataStructDefRecovery (AmdRecoveryParamsPtr->MemConfig.MemData);
+    return AGESA_SUCCESS;
+  } else {
+    return AGESA_ERROR;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
new file mode 100755
index 0000000000..cc7b682b0a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitReset.c
@@ -0,0 +1,207 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuCacheInit.h"
+#include "cpuServices.h"
+#include "AdvancedApi.h"
+#include "GeneralServices.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST OPTION_HT_INIT_RESET HtOptionInitReset;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+EXECUTION_CACHE_REGION InitResetExeCacheMap[] =
+{
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000},
+  {0x00000000, 0x00000000}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that will be invoked by the wrapper to initialize the input
+ * structure for the AllocateExecutionCache.
+ *
+ *  Parameters:
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   AmdExeAddrMapPtr  Our Service interface struct
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdInitResetExecutionCacheAllocateInitializer (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  UINT8 i;
+  ASSERT (AmdExeAddrMapPtr != NULL);
+
+  for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitResetExeCacheMap[i].ExeCacheStartAddr;
+    AmdExeAddrMapPtr[i].ExeCacheSize = InitResetExeCacheMap[i].ExeCacheSize;
+  }
+
+  return AGESA_SUCCESS;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_RESET function.
+ *
+ * This entry point is responsible for establishing the HT links to the program
+ * ROM and for performing basic processor initialization.
+ *
+ * @param[in,out] ResetParams    Required input parameters for the AMD_INIT_RESET
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD reset calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS *ResetParams
+  )
+{
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledAgesaStatus;
+  WARM_RESET_REQUEST Request;
+
+  AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
+  ASSERT (ResetParams != NULL);
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  GetWarmResetFlag (&ResetParams->StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+
+  // Setup ROM execution cache
+  CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]);
+  if (CalledAgesaStatus > AgesaStatus) {
+    AgesaStatus = CalledAgesaStatus;
+  }
+
+  // Initialize the PCI MMIO access mechanism
+  InitializePciMmio (&ResetParams->StdHeader);
+
+  // Initialize Hyper Transport Registers
+  if (HtOptionInitReset.HtInitReset != NULL) {
+    CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig);
+    if (CalledAgesaStatus > AgesaStatus) {
+      AgesaStatus = CalledAgesaStatus;
+    }
+  }
+
+  // Warm Rest, should be at the end of AmdInitReset
+  GetWarmResetFlag (&ResetParams->StdHeader, &Request);
+  if (Request.RequestBit == TRUE) {
+    Request.RequestBit = FALSE;
+    Request.StateBits = WR_STATE_RESET;
+    SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+    AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader);
+  } else {
+    if (Request.StateBits < WR_STATE_RESET) {
+      Request.StateBits = WR_STATE_RESET;
+      SetWarmResetFlag (&ResetParams->StdHeader, &Request);
+    }
+  }
+  // Check for Cache As Ram Corruption
+  IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader);
+
+  AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader);
+  return  AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initialize defaults and options for Amd Init Reset.
+ *
+ * @param[in]  StdHeader        Header
+ * @param[in]  AmdResetParams   The Reset Init interface to initialize.
+ *
+ * @retval     AGESA_SUCCESS    Always Succeeds.
+ */
+AGESA_STATUS
+AmdInitResetConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_RESET_PARAMS     *AmdResetParams
+  )
+{
+  ASSERT (AmdResetParams != NULL);
+
+  AmdResetParams->StdHeader = *StdHeader;
+
+  AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]);
+  AmdHtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig);
+
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
new file mode 100755
index 0000000000..3c6c04a7fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdInitResume.c
@@ -0,0 +1,223 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "Filecode.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuPostInit.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "CommonInits.h"
+#include "cpuFeatures.h"
+#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_INIT_RESUME function.
+ *
+ * This entry point is responsible for performing silicon device and memory
+ * re-initialization for the resume boot path.
+ *
+ * @param[in]     ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD resume calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  VOID   *OrMaskPtr;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS AmdInitResumeStatus;
+  BSC_AP_MSR_SYNC ApMsrSync[4];
+
+  AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader);
+
+  AmdInitResumeStatus = AGESA_SUCCESS;
+
+  ASSERT (ResumeParams != NULL);
+
+  if (ResumeParams->S3DataBlock.NvStorage != NULL) {
+
+    MemS3ResumeInitNB (&ResumeParams->StdHeader);
+
+    // Restore registers before exiting self refresh
+    RestorePreESRContext (&OrMaskPtr,
+                          ResumeParams->S3DataBlock.NvStorage,
+                          INIT_RESUME,
+                          &ResumeParams->StdHeader);
+    // Exit self refresh
+    ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader);
+    if (ReturnStatus > AmdInitResumeStatus) {
+      AmdInitResumeStatus = ReturnStatus;
+    }
+    if (ReturnStatus == AGESA_SUCCESS) {
+
+      // Restore registers after exiting self refresh
+      RestorePostESRContext (OrMaskPtr,
+                             ResumeParams->S3DataBlock.NvStorage,
+                             INIT_RESUME,
+                             &ResumeParams->StdHeader);
+
+      ApMsrSync[0].RegisterAddress = SYS_CFG;
+      ApMsrSync[1].RegisterAddress = TOP_MEM;
+      ApMsrSync[2].RegisterAddress = TOP_MEM2;
+      ApMsrSync[3].RegisterAddress = 0;
+      SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader);
+
+      ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
+      if (ReturnStatus > AmdInitResumeStatus) {
+        AmdInitResumeStatus = ReturnStatus;
+      }
+    }
+  }
+
+  RelinquishControlOfAllAPs (&ResumeParams->StdHeader);
+
+  AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader);
+  return (AmdInitResumeStatus);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_INIT_RESUME function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_INIT_RESUME entry point.
+ *
+ * @param[in]     StdHeader       The standard header.
+ * @param[in,out] ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdInitResumeInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (ResumeParams != NULL);
+
+  ResumeParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&ResumeParams->S3DataBlock);
+  CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Destructor for the AMD_INIT_RESUME function.
+ *
+ * This routine is responsible for deallocation of heap space allocated during
+ * AMD_INIT_RESUME entry point.
+ *
+ * @param[in]    StdHeader       The standard header.
+ * @param[in,out] ResumeParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+AmdInitResumeDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  )
+{
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS RetVal;
+
+  ASSERT (ResumeParams != NULL);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  // Deallocate heap space allocated during memory S3 resume
+  RetVal = MemS3Deallocate (&ResumeParams->StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  return ReturnStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
new file mode 100755
index 0000000000..cbb0b75639
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdLateRunApTask.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "Options.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST DISPATCH_TABLE ApDispatchTable[];
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Application Processor perform a function as directed by the BSC.
+ *
+ * This is needed for an AP task that must run after AGESA has relinquished control
+ * of the APs to the IBV.
+ *
+ * @param[in]     AmdApExeParams  The interface struct for any required routine.
+ *
+ * @return        The most severe AGESA_STATUS returned by any called service.  Note
+ *                that this will be the return value passed back to the BSC as the
+ *                return value for the call out.
+ *
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  )
+{
+  AGESA_STATUS        CalledAgesaStatus;
+  AGESA_STATUS        ApLateTaskStatus;
+  DISPATCH_TABLE      *Entry;
+
+  AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader);
+
+  ASSERT (AmdApExeParams != NULL);
+  ApLateTaskStatus = AGESA_SUCCESS;
+  CalledAgesaStatus = AGESA_UNSUPPORTED;
+
+  // Dispatch, if valid
+  Entry = (DISPATCH_TABLE *) ApDispatchTable;
+  while (Entry->FunctionId != 0) {
+    if (AmdApExeParams->FunctionNumber == Entry->FunctionId) {
+      CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams);
+      break;
+    }
+    Entry++;
+  }
+
+  if (CalledAgesaStatus > ApLateTaskStatus) {
+    ApLateTaskStatus = CalledAgesaStatus;
+  }
+
+  AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader);
+  return  ApLateTaskStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_LATE_RUN_AP_TASK function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3_SAVE entry point.
+ *
+ * @param[in]     StdHeader      The standard header.
+ * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdLateRunApTaskInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AP_EXE_PARAMS     *AmdApExeParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (AmdApExeParams != NULL);
+
+  AmdApExeParams->StdHeader = *StdHeader;
+  AmdApExeParams->FunctionNumber = 0;
+  AmdApExeParams->RelatedDataBlock = NULL;
+  AmdApExeParams->RelatedBlockLength = 0;
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
new file mode 100755
index 0000000000..5cdf954d2c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3LateRestore.c
@@ -0,0 +1,207 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "S3.h"
+#include "cpuFeatures.h"
+#include "S3SaveState.h"
+#include "CommonInits.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdS3LateRestorePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_S3LATE_RESTORE function.
+ *
+ * This entry point is responsible for restoring saved registers and preparing the
+ * silicon components for OS restart.
+ *
+ * @param[in,out] S3LateParams   Required input parameters for the AMD_S3LATE_RESTORE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD S3 late restore calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  )
+{
+  UINT8  *BufferPointer;
+  VOID   *OrMaskPtr;
+  VOID   *LateContextPtr;
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS CalledStatus;
+
+  AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  ASSERT (S3LateParams != NULL);
+
+  BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
+  S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+  ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));
+
+  if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {
+    LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];
+    // Restore registers before exiting self refresh
+    RestorePreESRContext (&OrMaskPtr,
+                          LateContextPtr,
+                          S3_LATE_RESTORE,
+                          &S3LateParams->StdHeader);
+    // Restore registers after exiting self refresh
+    RestorePostESRContext (OrMaskPtr,
+                           LateContextPtr,
+                           S3_LATE_RESTORE,
+                           &S3LateParams->StdHeader);
+  }
+
+  // Dispatch any features needing to run at this time point
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,
+                                      &S3LateParams->PlatformConfig,
+                                      &S3LateParams->StdHeader);
+  if (CalledStatus > ReturnStatus) {
+    ReturnStatus = CalledStatus;
+  }
+
+  CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);
+  if (CalledStatus > ReturnStatus) {
+    ReturnStatus = CalledStatus;
+  }
+
+  IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);
+  return  ReturnStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3LATE_RESTORE function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3LATE_RESTORE entry point.
+ *
+ * @param[in]     StdHeader         AMD standard header config param.
+ * @param[in,out] S3LateParams      Required input parameters for the
+ *                                  AMD_S3LATE_RESTORE entry point.
+ *
+ * @retval        AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestoreInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (S3LateParams != NULL);
+
+  S3LateParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&S3LateParams->S3DataBlock);
+
+  AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdS3Save stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval          AGESA_SUCCESS    Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3LateRestorePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
new file mode 100755
index 0000000000..4458d20a53
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/AmdS3Save.c
@@ -0,0 +1,370 @@
+/**
+ * @file
+ *
+ * AMD AGESA Basic Level Public APIs
+ *
+ * Contains basic Level Initialization routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Interface
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "CommonInits.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Topology.h"
+#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST UINT32 ROMDATA S3LateHeapTable[] =
+{
+  EVENT_LOG_BUFFER_HANDLE,
+  SOCKET_DIE_MAP_HANDLE,
+  NODE_ID_MAP_HANDLE,
+  LOCAL_AP_MAIL_BOX_CACHE_HANDLE,
+  IDS_CONTROL_HANDLE,
+  AMD_S3_SCRIPT_SAVE_TABLE_HANDLE
+};
+
+#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT))
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdS3SavePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Main entry point for the AMD_S3_SAVE function.
+ *
+ * This entry point is responsible for saving silicon component registers to the
+ * SMM save area in preparation of entering system suspend-to-RAM mode.
+ *
+ * @param[in,out] AmdS3SaveParams   Required input parameters for the AMD_S3_SAVE
+ *                                  entry point.
+ *
+ * @return        Aggregated status across all internal AMD S3 save calls invoked.
+ *
+ */
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS *AmdS3SaveParams
+  )
+{
+  UINTN  i;
+  UINT32 EarlyBufferSize;
+  UINT32 LateBufferSize;
+  UINT32 LateContextSize;
+  UINT32 HeapSize;
+  UINT8  *BufferPointer;
+  UINT8  HeapStatus;
+  ALLOCATE_HEAP_PARAMS HeapParams;
+  AGESA_BUFFER_PARAMS AllocParams;
+  DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList;
+  DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList;
+  AGESA_STATUS ReturnStatus;
+  VOID   *HeapPtrs[S3LATE_TABLE_SIZE];
+  UINT32 HeapSizes[S3LATE_TABLE_SIZE];
+  UINT32 HeapBuffersPresent;
+  HEAP_MANAGER *HeapPtr;
+
+  AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader);
+
+  ASSERT (AmdS3SaveParams != NULL);
+
+  HeapBuffersPresent = 0;
+  EarlyBufferSize = 0;
+  LateBufferSize = 0;
+  LateContextSize = 0;
+  HeapSize = 0;
+  NonMemoryRelatedDeviceList = NULL;
+  ReturnStatus = AGESA_SUCCESS;
+
+  IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) {
+
+    // Get memory device list
+    MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
+    if (MemoryRelatedDeviceList != NULL) {
+      // Determine size needed
+      EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader);
+    }
+
+    if (UserOptions.CfgS3LateRestore) {
+      AllocParams.StdHeader = AmdS3SaveParams->StdHeader;
+      for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
+        AllocParams.BufferHandle = S3LateHeapTable[i];
+        AllocParams.BufferLength = 0;
+        if (AgesaLocateBuffer (0, &AllocParams) == AGESA_SUCCESS) {
+          ASSERT (AllocParams.BufferLength != 0);
+          HeapBuffersPresent++;
+          HeapSize += AllocParams.BufferLength; //S3LateHeapTable[i].BufferLength;
+          HeapPtrs[i] = AllocParams.BufferPointer;
+          HeapSizes[i] = AllocParams.BufferLength;
+        } else {
+          HeapPtrs[i] = NULL;
+          HeapSizes[i] = 0;
+        }
+      }
+
+      // Determine heap data size requirements
+      if (HeapBuffersPresent != 0) {
+        HeapSize += (((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * (sizeof (BUFFER_NODE)))) + (HeapBuffersPresent * (2 * SIZE_OF_SENTINEL)));
+      }
+
+      // Get non memory device list
+      GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
+
+      if (NonMemoryRelatedDeviceList != NULL) {
+        // Determine size needed
+        LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader);
+      }
+      LateBufferSize = HeapSize + LateContextSize;
+      if (LateBufferSize != 0) {
+        LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER);
+      }
+    }
+
+    if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) {
+      //
+      // Allocate a buffer by callback function
+      //
+      AllocParams.StdHeader = AmdS3SaveParams->StdHeader;
+      AllocParams.BufferLength = EarlyBufferSize + LateBufferSize;
+      AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE;
+
+      AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
+      if (AgesaAllocateBuffer (0, &AllocParams) != AGESA_SUCCESS) {
+        if (AGESA_ERROR > ReturnStatus) {
+          ReturnStatus = AGESA_ERROR;
+        }
+      }
+      AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
+
+      if (EarlyBufferSize != 0) {
+        AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPointer;
+        SaveDeviceListContext (MemoryRelatedDeviceList,
+                           AmdS3SaveParams->S3DataBlock.NvStorage,
+                           INIT_RESUME,
+                           &EarlyBufferSize,
+                           &AmdS3SaveParams->StdHeader);
+
+        AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize;
+      }
+
+      if (LateBufferSize != 0) {
+        BufferPointer = AllocParams.BufferPointer;
+        AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]);
+
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0;
+        ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize;
+
+        if (HeapSize != 0) {
+          // Transfer heap contents
+          ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER);
+          HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)];
+          HeapPtr->AvailableSize = (UINT16) (HeapSize - sizeof (HEAP_MANAGER));
+
+          HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
+          AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+          AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT32) HeapPtr;
+
+          for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
+            if (HeapPtrs[i] != NULL) {
+              HeapParams.RequestedBufferSize = (UINT16) HeapSizes[i]; // S3LateHeapTable[i].BufferLength;
+              HeapParams.BufferHandle = S3LateHeapTable[i];
+              HeapParams.Persist = HEAP_S3_RESUME;
+              if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
+                LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader);
+              }
+            }
+          }
+
+          AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus;
+        }
+
+
+        if (LateContextSize != 0) {
+
+          ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
+
+          SaveDeviceListContext (NonMemoryRelatedDeviceList,
+                                &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]),
+                                S3_LATE_RESTORE,
+                                &LateContextSize,
+                                &AmdS3SaveParams->StdHeader);
+        }
+
+        AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
+      }
+    }
+  }
+  IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader);
+  AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader);
+  return  ReturnStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Constructor for the AMD_S3_SAVE function.
+ *
+ * This routine is responsible for setting default values for the
+ * input parameters needed by the AMD_S3_SAVE entry point.
+ *
+ * @param[in]    StdHeader       The standard header.
+ * @param[in,out] S3SaveParams   Required input parameters for the AMD_S3_SAVE
+ *                               entry point.
+ *
+ * @retval        AGESA_SUCCESS  Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3SaveInitializer (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  )
+{
+  ASSERT (StdHeader != NULL);
+  ASSERT (S3SaveParams != NULL);
+
+  S3SaveParams->StdHeader = *StdHeader;
+
+  AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock);
+
+  AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Destructor for the AMD_S3_SAVE function.
+ *
+ * This routine is responsible for deallocation of heap space allocated during
+ * AMD_S3_SAVE entry point.
+ *
+ * @param[in]     StdHeader       The standard header.
+ * @param[in,out] S3SaveParams   Required input parameters for the AMD_INIT_RESUME
+ *                               entry point.
+ *
+ * @retval        AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+AmdS3SaveDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  )
+{
+  AGESA_STATUS ReturnStatus;
+  AGESA_STATUS RetVal;
+
+  ASSERT (S3SaveParams != NULL);
+
+  ReturnStatus = AGESA_SUCCESS;
+
+  // Deallocate heap space allocated during memory S3 save
+  RetVal = MemS3Deallocate (&S3SaveParams->StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader);
+  if (RetVal > ReturnStatus) {
+    ReturnStatus = RetVal;
+  }
+
+  return ReturnStatus;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initialize AmdS3Save stage platform profile and user option input.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval          AGESA_SUCCESS    Always Succeeds.
+ *
+ */
+AGESA_STATUS
+AmdS3SavePlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  CommonPlatformConfigInit (PlatformConfig, StdHeader);
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
new file mode 100755
index 0000000000..17726cb27e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.c
@@ -0,0 +1,114 @@
+/**
+ * @file
+ *
+ * Common initialization routines.
+ *
+ * Contains common initialization routines across AGESA entries of phases.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "CommonInits.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_COMMONINITS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+
+/**
+ * Common routine to initialize PLATFORM_CONFIGURATION.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+CommonPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile;
+  PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList;
+  PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode;
+  PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode;
+  PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData;
+  PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode;
+  PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData;
+  PlatformConfig->UserOptionDmi = UserOptions.OptionDmi;
+  PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates;
+  PlatformConfig->UserOptionSrat = UserOptions.OptionSrat;
+  PlatformConfig->UserOptionSlit = UserOptions.OptionSlit;
+  PlatformConfig->UserOptionWhea = UserOptions.OptionWhea;
+  PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue;
+  PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent;
+  PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics;
+  PlatformConfig->VrmProperties = UserOptions.CfgPlatVrmCfg;
+  PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb;
+  PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0;
+  PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1;
+
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
new file mode 100755
index 0000000000..93a9304e70
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonInits.h
@@ -0,0 +1,65 @@
+/**
+ * @file
+ *
+ * Common initialization routines.
+ *
+ * Contains common initialization routines across AGESA entries of phases.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 7735 $   @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _COMMON_INITS_H_
+#define _COMMON_INITS_H_
+
+/**
+ * Common routine to initialize PLATFORM_CONFIGURATION.
+ *
+ * @param[in,out]   PlatformConfig   Platform profile/build option config structure
+ * @param[in,out]   StdHeader        AMD standard header config param
+ *
+ * @retval      AGESA_SUCCESS     Always Succeeds.
+ *
+ */
+AGESA_STATUS
+CommonPlatformConfigInit (
+  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+#endif // _COMMON_INITS_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonPage.h
new file mode 100755
index 0000000000..c16af47566
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonPage.h
@@ -0,0 +1,116 @@
+/**
+ * @file
+ *
+ * Create outline and references for Processor Common Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page commonmain Processor Common Component Documentation
+ *
+ * Additional documentation for the Common component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS"
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+/**
+ * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS
+ * @par
+ * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code.
+ * <ul>
+ *
+ * <li>
+ * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named
+ * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a
+ * typedef of a function prototype) in AGESA code. Examples:
+ * @n @code
+ * VOID
+ *   LibAmdPciFindNextCap (
+ *     IN OUT   PCI_ADDR *Address,
+ *     IN       AMD_CONFIG_PARAMS *StdHeader
+ *     )
+ *
+ * typedef VOID F_DO_TABLE_ENTRY (
+ *   IN       TABLE_ENTRY_DATA       *CurrentEntry,
+ *   IN       PLATFORM_CONFIGURATION *PlatformConfig,
+ *   IN       AMD_CONFIG_PARAMS      *StdHeader
+ *   );
+ *
+ * @endcode
+ *
+ * <li>
+ * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples:
+ * @n @code
+   /// Example of struct member naming.
+ * typedef struct {
+ *   IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard Header
+ *   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+ * } AMD_CPU_RECOVERY_PARAMS;
+ *
+ * @endcode
+ *
+ * <li>
+ * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should
+ * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example:
+ * @n @code
+ * AMD_CONFIG_PARAMS *NewStdHeader;
+ * [...]
+ * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+ * @endcode
+ *
+ * <li>
+ * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not
+ * checked.  Freedom is allowed in order to conform to these guidelines in a practical, readable
+ * way.  This includes typecast arguments.  Examples:
+ * @n @code
+ * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event);
+ *
+ * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader);
+ * @endcode
+ *
+ * </ul>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
new file mode 100755
index 0000000000..f395dc1916
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CommonReturns.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return False.
+*
+* @retval FALSE  Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse (VOID)
+{
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 (VOID)
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 (VOID)
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 (VOID)
+{
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL (VOID)
+{
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess (VOID)
+{
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid (VOID)
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert (VOID)
+{
+  ASSERT (FALSE);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
new file mode 100755
index 0000000000..990a10c1c0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.c
@@ -0,0 +1,291 @@
+/**
+ * @file
+ *
+ * AMD AGESA Input Structure Creation
+ *
+ * Contains AGESA input structure creation support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 6913 $   @e \$Date: 2008-07-23 11:34:49 -0500 (Wed, 23 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[];
+extern CONST UINTN InitializerCount;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocate and initialize Config headers and Service Interface structures.
+ *
+ * This function will be called for each AGESA public APIs.
+ * This function will do the following:
+ * -# Locate the AGESA API structure parameters initializer function information.
+ * -# Find the size of the structure that gets passed to each public APIs as
+ *    the entry parameter. Allocate heap space using the size for PreMemHeap, callout for
+ *    memory allocation for PostMemDram, and just set the config and service interface
+ *    pointers for ByHost.
+ * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams.
+ *    For ByHost, we're using the caller's existing config params.
+ * -# Call the initializer function, and pass a reference to the Config params and to
+ *    the Service Interface struct.  On return the constructor will have filled the
+ *    remaining structure with default values.
+ * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS
+ *    area (i.e. Fill *newStructPtr with the pointer to the newly created structure)
+ * -# Set the appropriate AGESA function number in the StdHeader member of the input
+ *    parameter structure.
+ *
+ * @param[in,out]  InterfaceParams         Pointer to structure containing the function call
+ *                                         whose parameter structure is to be created, the
+ *                                         allocation method, and a pointer to the newly
+ *                                         created structure.
+ *
+ * @retval         AGESA_SUCCESS           The interface struct is allocated and initialized.
+ * @retval         AGESA_UNSUPPORTED       The Service is not supported.
+ *
+ */
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  )
+{
+  UINTN                     ServiceIndex;
+  ALLOCATE_HEAP_PARAMS      AllocHeapParams;
+  AMD_CONFIG_PARAMS         *NewlyCreatedConfig;
+  VOID                      *NewlyCreatedServiceInterface;
+  AGESA_STATUS              AgesaStatus;
+  AGESA_STATUS              TempStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  ASSERT (InterfaceParams != NULL);
+
+  switch (InterfaceParams->AgesaFunctionName) {
+  case AMD_INIT_RESET:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET;
+    AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader);
+    break;
+  case AMD_INIT_EARLY:
+  case AMD_INIT_RECOVERY:
+  case AMD_INIT_RESUME:
+  case AMD_INIT_POST:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  case AMD_INIT_ENV:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+    break;
+  case AMD_INIT_LATE:
+  case AMD_INIT_MID:
+  case AMD_S3_SAVE:
+  case AMD_LATE_RUN_AP_TASK:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_S3LATE_RESTORE:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+    break;
+  default:
+    ASSERT (FALSE);
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  }
+
+  // Step 1
+  for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) {
+    if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
+      break;
+    }
+  }
+  if (ServiceIndex >= InitializerCount) {
+    // A call was made to AGESA with an invalid function number.  This wrapper error may be due to the build target
+    // not containing the desired entry point.
+    return AGESA_UNSUPPORTED;
+  }
+
+  // Step 2
+  LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader);
+
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    // Allocate one buffer to contain the config params and the service struct.
+    // The service struct begins immediately after the config params.
+    AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS);
+    AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle;
+    TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader));
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+    NewlyCreatedConfig++;
+    NewlyCreatedServiceInterface =  NewlyCreatedConfig;
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
+  } else {
+    // The caller (example, agesa basic interface implementation) already has a buffer to use.
+    NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams;
+    NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr;
+    ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize);
+  }
+  ASSERT (NewlyCreatedConfig != NULL);
+  ASSERT (NewlyCreatedServiceInterface != NULL);
+
+  // Step 3
+  if (InterfaceParams->AllocationMethod != ByHost) {
+    *NewlyCreatedConfig = InterfaceParams->StdHeader;
+  }
+
+  // Step 4
+  TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface);
+  AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+
+  // Step 5
+  if (InterfaceParams->AllocationMethod != ByHost) {
+    InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface;
+    InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize;
+  }
+
+  // Step 6
+  ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName;
+  return AgesaStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Clears storage space from allocation for a parameter block of an
+ *  AGESA software call entry.
+ *
+ *  @param[in,out]  InterfaceParams         Pointer to structure containing the function call
+ *                                          whose parameter structure is to be deallocated.
+ *
+ *  @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  )
+{
+  UINT8 i;
+  UINT8 *BufferPtr;
+  VOID  *ServicePtr;
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  TempStatus;
+  LOCATE_HEAP_PTR LocHeap;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  switch (InterfaceParams->AgesaFunctionName) {
+  case AMD_INIT_RESET:
+  case AMD_INIT_EARLY:
+  case AMD_INIT_RECOVERY:
+  case AMD_INIT_RESUME:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  case AMD_INIT_POST:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
+    break;
+  case AMD_INIT_ENV:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_INIT_LATE:
+  case AMD_INIT_MID:
+  case AMD_S3_SAVE:
+  case AMD_LATE_RUN_AP_TASK:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+    break;
+  case AMD_S3LATE_RESTORE:
+    InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
+    break;
+  default:
+    ASSERT (FALSE);
+    InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
+    break;
+  }
+
+// Step 1
+  for (i = 0; i < InitializerCount; i++) {
+    if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
+      break;
+    }
+  }
+  if (i >= InitializerCount) {
+    return AGESA_BOUNDS_CHK;
+  }
+
+  // Step 2
+  LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle;
+  if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) {
+    BufferPtr = (UINT8 *) LocHeap.BufferPtr;
+    ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)];
+    TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr);
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+  }
+
+  // Step 3
+  if (InterfaceParams->AllocationMethod < ByHost) {
+    TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader));
+    AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
+  } else {
+    // Unless we define service specific destructors, nothing to do for ByHost.
+    return AGESA_SUCCESS;
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
new file mode 100755
index 0000000000..b19147b0bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/CreateStruct.h
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * AMD AGESA Input Structure Creation
+ *
+ * Contains AGESA input creation structures.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 6913 $   @e \$Date: 2008-07-23 11:34:49 -0500 (Wed, 23 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CREATE_STRUCT_H_
+#define _CREATE_STRUCT_H_
+
+/**
+ * A constructor method.
+ *
+ * Sets inputs to valid, basic level, defaults for the specific service instance.
+ * Constructors should avoid using the header, since these routines should not
+ * do operations which may fail or require status back to the user.  The constructor
+ * should always SUCCEED.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header
+ * @param[in]   ServiceInterface  Service Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+typedef AGESA_STATUS
+F_AGESA_FUNCTION (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       VOID                 *ServiceInterface
+  );
+
+/// Reference to a Method.
+typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION;
+
+/**
+ * A Destructor method.
+ *
+ * Sets inputs to valid, basic level, defaults for the specific service instance.
+ * The constructor should always SUCCEED.
+ *
+ * @param[in]   StdHeader         Opaque handle to standard config header.
+ * @param[in]   ServiceInterface  Service Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+typedef AGESA_STATUS
+F_AGESA_DESTRUCTOR (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       VOID                 *ServiceInterface
+  );
+
+/// Reference to a Method.
+typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR;
+
+/**
+ * Provide the information needed to invoke each service constructor.
+ */
+typedef struct {
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< Identifies the service
+  IN       UINT16              CreateStructSize;   ///< The service's input struct size.
+                                                   ///  Do NOT include a config params header!
+     OUT   PF_AGESA_FUNCTION   AgesaFunction;      ///< The constructor function
+     OUT   PF_AGESA_DESTRUCTOR AgesaDestructor;    ///< The destructor function.
+  IN       AGESA_BUFFER_HANDLE BufferHandle;       ///< The buffer handle id for the service.
+} FUNCTION_PARAMS_INFO;
+
+/**
+ * All available services have their constructor info here.
+ */
+AGESA_STATUS
+AmdInitResetConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_RESET_PARAMS     *AmdResetParams
+  );
+
+AGESA_STATUS
+AmdInitRecoveryInitializer (
+  IN       AMD_CONFIG_PARAMS   *StdHeader,
+  IN OUT   AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitEarlyInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_EARLY_PARAMS  *EarlyParams
+  );
+
+AGESA_STATUS
+AmdInitPostInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_POST_PARAMS *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitPostDestructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_POST_PARAMS      *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitEnvInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_ENV_PARAMS *EnvParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitMidInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_MID_PARAMS *MidParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitLateInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_LATE_PARAMS *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitLateDestructor (
+  IN   AMD_CONFIG_PARAMS *StdHeader,
+  IN   AMD_LATE_PARAMS   *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdInitResumeInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  );
+
+AGESA_STATUS
+AmdInitResumeDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_RESUME_PARAMS *ResumeParams
+  );
+
+AGESA_STATUS
+AmdS3SaveInitializer (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  );
+
+AGESA_STATUS
+AmdS3SaveDestructor (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3SAVE_PARAMS *S3SaveParams
+  );
+
+AGESA_STATUS
+AmdS3LateRestoreInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AMD_S3LATE_PARAMS *S3LateParams
+  );
+
+AGESA_STATUS
+AmdLateRunApTaskInitializer (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   AP_EXE_PARAMS     *AmdApExeParams
+  );
+#endif // _CREATE_STRUCT_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
new file mode 100755
index 0000000000..3d98b388e4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3RestoreState.c
@@ -0,0 +1,304 @@
+/**
+ * @file
+ *
+ * S3 save/restore script
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20539 $   @e \$Date: 2009-10-14 10:48:54 -0700 (Wed, 14 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+AGESA_STATUS
+STATIC
+S3RestoreStateFromTable (
+  IN      S3_SAVE_TABLE_HEADER  *S3SaveTablePtr,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestore (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return OptionS3ScriptConfiguration.Restore (StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestoreStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptRestoreState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  S3_SAVE_TABLE_HEADER  *S3SaveTablePtr;
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    IDS_ERROR_TRAP;
+    return  AGESA_FATAL;
+  }
+  Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] S3SaveTablePtr     Pointer to S3 Save Table
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+STATIC
+S3RestoreStateFromTable (
+  IN      S3_SAVE_TABLE_HEADER  *S3SaveTablePtr,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  VOID                  *S3SaveTableRecordPtr;
+  PCI_ADDR              PciAddress;
+  S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER);
+  IDS_HDT_CONSOLE ("Start S3 restore\n");
+  while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) {
+    switch  (*(UINT16 *) S3SaveTableRecordPtr) {
+    case  SAVE_STATE_IO_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 IO Write %x\n", (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdIoWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_IO_READ_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 IO RMW %x\n", (UINT16) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdIoRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Mem Write %llx\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdMemWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_READ_WRITE_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Mem RMW %llx\n", ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdMemRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      IDS_HDT_CONSOLE ("  S3 PCI Write %lx\n", PciAddress.AddressValue);
+
+      LibAmdPciWrite (
+        ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_WRITE_OP_HEADER) +
+                              LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      IDS_HDT_CONSOLE ("  S3 PCI RMW %lx\n", PciAddress.AddressValue);
+      LibAmdPciRMW (
+        ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_READ_WRITE_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_STALL_OPCODE:
+      break;
+    case  SAVE_STATE_INFORMATION_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Info [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER));
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                             sizeof (S3_INFO_OP_HEADER) +
+                             ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length;
+      break;
+    case  SAVE_STATE_IO_POLL_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 IO Poll %x\n", (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdIoPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_MEM_POLL_OPCODE:
+      IDS_HDT_CONSOLE ("  S3 Mem Poll %llx\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+      LibAmdMemPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    case  SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
+      PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address;
+      IDS_HDT_CONSOLE ("  S3 PCI Poll %lx\n", PciAddress.AddressValue);
+      LibAmdPciPoll (
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
+        PciAddress,
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
+        (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
+        ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
+        StdHeader
+        );
+      S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
+                              sizeof (S3_POLL_OP_HEADER) +
+                              2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
+      break;
+    default:
+      IDS_HDT_CONSOLE (" ERROR!!! Invalid S3 restore opcode\n");
+      ASSERT (FALSE);
+      return AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (" End S3 Restore \n");
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
new file mode 100755
index 0000000000..73dc8d2ed9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.c
@@ -0,0 +1,453 @@
+/**
+ * @file
+ *
+ * S3 save/restore script
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20539 $   @e \$Date: 2009-10-14 10:48:54 -0700 (Wed, 14 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInit (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return OptionS3ScriptConfiguration.Init (StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInitStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ */
+AGESA_STATUS
+S3ScriptInitState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status == AGESA_SUCCESS) {
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH;
+    ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER);
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in]     StdHeader          Pointer to standard header
+ * @param[in,out] S3SaveTable        S3 save table header
+ */
+STATIC AGESA_STATUS
+S3SaveStateExtendTableLenth (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+  VOID                  *TempBuffer;
+  UINT16                NewTableLength;
+  UINT16                CurrentTableLength;
+  //Allocate temporary buffer
+  NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT;
+  AllocHeapParams.RequestedBufferSize = NewTableLength;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  //Save current table length
+  CurrentTableLength = (*S3SaveTable)->TableLength;
+  //Update table length
+  (*S3SaveTable)->TableLength = NewTableLength;
+  //Copy S3 save toable to temporary location
+  LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader);
+  //Save pointer to temp buffer
+  TempBuffer = AllocHeapParams.BufferPtr;
+  // Free original S3 save buffer
+  HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader);
+
+  AllocHeapParams.RequestedBufferSize = NewTableLength;
+  AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  AllocHeapParams.Persist = StdHeader->HeapStatus;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader);
+  *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr;
+  HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize S3 Script framework
+ *
+ *
+ *
+ * @param[in]  StdHeader          Pointer to standard header
+ * @param[out] S3SaveTable        S3 save table header
+ */
+AGESA_STATUS
+S3ScriptGetS3SaveTable (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   S3_SAVE_TABLE_HEADER  **S3SaveTable
+  )
+{
+  AGESA_STATUS          Status;
+  LOCATE_HEAP_PTR       LocHeapParams;
+  LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
+  Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    *S3SaveTable = NULL;
+    return Status;
+  }
+  *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 write opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Count              Number of register writes
+ * @param[in] Buffer             Pointer to write buffer
+ */
+AGESA_STATUS
+S3SaveStateSaveWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      UINT32              Count,
+  IN      VOID                *Buffer
+  )
+{
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_WRITE_OP_HEADER      *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+  SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Count = Count;
+  SaveOffsetPtr->Address = Address;
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER),
+    Buffer,
+    WidthLength * Count,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 write opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Data               Pointer to data
+ * @param[in] DataMask           Pointer data mask
+ */
+AGESA_STATUS
+S3SaveStateSaveReadWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_READ_WRITE_OP_HEADER *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+
+  SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Address = Address;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER),
+    Data,
+    WidthLength,
+    StdHeader
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength,
+    DataMask,
+    WidthLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 poll opcode
+ *
+ *
+ *
+ * @param[in] StdHeader          Pointer to standard header
+ * @param[in] OpCode             Operation opcode
+ * @param[in] Width              Width
+ * @param[in] Address            Register address
+ * @param[in] Data               Pointer to data
+ * @param[in] DataMask           Pointer data mask
+ * @param[in] Delay              Time delay for poll
+ */
+AGESA_STATUS
+S3SaveStateSavePollOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask,
+  IN      UINT64              Delay
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_POLL_OP_HEADER       *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+  UINT32                  WidthLength;
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  WidthLength = LibAmdAccessWidth (Width);
+  OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+
+  SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Width = Width;
+  SaveOffsetPtr->Delay = Delay;
+  SaveOffsetPtr->Address = Address;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER),
+    Data,
+    WidthLength,
+    StdHeader
+    );
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength,
+    DataMask,
+    WidthLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save S3 poll opcode
+ *
+ *
+ *
+ * @param[in] StdHeader              Pointer to standard header
+ * @param[in] OpCode                  Operation opcode
+ * @param[in] InformationLength  Info length
+ * @param[in] Information             Pointer to information
+ */
+AGESA_STATUS
+S3SaveStateSaveInfoOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT32              InformationLength,
+  IN      VOID                *Information
+  )
+{
+
+  S3_SAVE_TABLE_HEADER    *S3SaveTablePtr;
+  S3_INFO_OP_HEADER       *SaveOffsetPtr;
+  UINT32                  OpCodeLength;
+
+  AGESA_STATUS            Status;
+
+  Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength;
+  if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
+    Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
+    if (Status != AGESA_SUCCESS) {
+      return Status;
+    }
+  }
+
+  SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
+  SaveOffsetPtr->OpCode = OpCode;
+  SaveOffsetPtr->Length = InformationLength;
+
+  LibAmdMemCopy (
+    (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
+    Information,
+    InformationLength,
+    StdHeader
+    );
+  S3SaveTablePtr->SaveOffset += OpCodeLength;
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.h
new file mode 100755
index 0000000000..60d0d8e743
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Common/S3SaveState.h
@@ -0,0 +1,287 @@
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 20270 $   @e \$Date: 2009-10-09 10:09:20 -0700 (Fri, 09 Oct 2009) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _S3SAVESTATE_H_
+#define _S3SAVESTATE_H_
+
+
+#define SAVE_STATE_IO_WRITE_OPCODE              0x00
+#define SAVE_STATE_IO_READ_WRITE_OPCODE         0x01
+#define SAVE_STATE_MEM_WRITE_OPCODE             0x02
+#define SAVE_STATE_MEM_READ_WRITE_OPCODE        0x03
+#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE      0x04
+#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05
+#define SAVE_STATE_STALL_OPCODE                 0x07
+#define SAVE_STATE_INFORMATION_OPCODE           0x0A
+#define SAVE_STATE_IO_POLL_OPCODE               0x0D
+#define SAVE_STATE_MEM_POLL_OPCODE              0x0E
+#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE       0x0F
+
+
+#define S3_TABLE_LENGTH             8 * 1024
+#define S3_TABLE_LENGTH_INCREMENT   1 * 1024
+
+/// S3 Save Table
+typedef struct {
+  UINT16                      TableLength;        ///< Table Length
+  UINT32                      SaveOffset;         ///< Save Location
+} S3_SAVE_TABLE_HEADER;
+
+/// S3 write operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register address
+  UINT32                      Count;              ///< Write count
+} S3_WRITE_OP_HEADER;
+
+/// S3 Read and Write Operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register Address
+} S3_READ_WRITE_OP_HEADER;
+
+/// S3 Poll operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  ACCESS_WIDTH                Width;              ///< Data width (byte, word, dword)
+  UINT64                      Address;            ///< Register address
+  UINT64                      Delay;              ///< Time delay
+} S3_POLL_OP_HEADER;
+
+/// Information operation header
+typedef struct {
+  UINT16                      OpCode;             ///< Opcode
+  UINT32                      Length;             ///< Length of info
+} S3_INFO_OP_HEADER;
+
+typedef AGESA_STATUS (*S3_SCRIPT_INIT) (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInit (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInitState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptInitStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+typedef AGESA_STATUS (*S3_SCRIPT_RESTORE) (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestore (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestoreState (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptRestoreStateStub (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+S3ScriptGetS3SaveTable (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  OUT     S3_SAVE_TABLE_HEADER  **S3SaveTable
+  );
+
+/// S3 Script Configuration
+typedef struct {
+  S3_SCRIPT_INIT              Init;               ///< Script initialization
+  S3_SCRIPT_RESTORE           Restore;            ///< Script restore
+} S3_SCRIPT_CONFIGURATION;
+
+AGESA_STATUS
+S3SaveStateSaveWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      UINT32              Count,
+  IN      VOID                *Buffer
+  );
+
+AGESA_STATUS
+S3SaveStateSaveReadWriteOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask
+  );
+
+AGESA_STATUS
+S3SaveStateSavePollOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT64              Address,
+  IN      VOID                *Data,
+  IN      VOID                *DataMask,
+  IN      UINT64              Delay
+  );
+
+AGESA_STATUS
+S3SaveStateSaveInfoOp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader,
+  IN      UINT16              OpCode,
+  IN      UINT32              InformationLength,
+  IN      VOID                *Information
+  );
+
+//PCI write
+#define S3_SAVE_PCI_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_WRITE_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    1,  \
+    DataPtr  \
+    )
+
+//PCI read modify write
+#define S3_SAVE_PCI_RMW (StdHeader, Address, Width, DataPtr, DataMaskPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    DataPtr,  \
+    DataMask  \
+    )
+
+//PCI read modify write
+#define S3_SAVE_PCI_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
+  S3SaveStateSavePollOp (  \
+    StdHeader,  \
+    SAVE_STATE_PCI_CONFIG_POLL_OPCODE,  \
+    Width,  \
+    Address.AddressValue, \
+    DataPtr,  \
+    DataMask,  \
+    Delay  \
+    )
+
+//Memory/MMIO write
+#define S3_SAVE_MEM_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    1,  \
+    DataPtr  \
+    )
+
+//Memory/MMIO read modify write
+#define S3_SAVE_MEM_RMW(StdHeader, Address, Width, DataPtr, DataMaskPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    DataPtr,  \
+    DataMask  \
+    )
+
+//Memory/MMIO read modify write
+#define S3_SAVE_MEM_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
+  S3SaveStateSavePollOp (  \
+    StdHeader,  \
+    SAVE_STATE_MEM_POLL_OPCODE,  \
+    Width,  \
+    Address, \
+    DataPtr,  \
+    DataMask,  \
+    Delay \
+    )
+
+// I/O write
+#define S3_SAVE_IO_WRITE(StdHeader, Address, Width, DataPtr) \
+  S3SaveStateSaveWriteOp (  \
+    StdHeader,  \
+    SAVE_STATE_IO_READ_WRITE_OPCODE,  \
+    Width,  \
+    Address, \
+    1,  \
+    DataPtr  \
+    )
+
+// Save information
+#define S3_SAVE_INFORMATION(StdHeader, InformationLength, Information) \
+  S3SaveStateSaveInfoOp (  \
+    StdHeader,  \
+    SAVE_STATE_INFORMATION_OPCODE,  \
+    InformationLength,  \
+    Information \
+    )
+
+// Save information string S3_SAVE_INFORMATION_STRING (StdHeader, "Message")
+#define S3_SAVE_INFORMATION_STRING(StdHeader, Information) \
+  S3SaveStateSaveInfoOp (  \
+    StdHeader,  \
+    SAVE_STATE_INFORMATION_OPCODE,  \
+    sizeof (Information),  \
+    Information \
+    )
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
new file mode 100755
index 0000000000..d0f1e4a0d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * Coherent Family 10h Routines.
+ *
+ * Coherent feature Northbridge implementation specific to Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbCoherentFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return whether the current configuration exceeds the capability.
+ *
+ * @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}.
+ *
+ * Get Node capability and update the minimum supported system capability.
+ *
+ * @param[in]     Node     the Node
+ * @param[in]     State    sysMpCap (updated) and NodesDiscovered
+ * @param[in]     Nb       this northbridge
+ *
+ * @retval        TRUE     system is not capable of current config.
+ * @retval        FALSE    system is capable of current config.
+ */
+BOOLEAN
+Fam10IsExceededCapable (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  UINT8 MaxNodes;
+  PCI_ADDR Reg;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+
+  LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle);
+
+  if (Temp != 0) {
+    MaxNodes = (UINT8) (1 << (~Temp & 0x3));  // That is, 1, 2, 4, or 8
+  } else {
+    MaxNodes = 8;
+  }
+  if (State->SysMpCap > MaxNodes) {
+    State->SysMpCap = MaxNodes;
+  }
+  // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true
+  //
+  return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered));
+}
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ *
+ * @HtNbMethod{::F_STOP_LINK}.
+ *
+ * Use is for fatal incompatible configurations, or for user interface
+ * request to power off a link (IgnoreLink, SkipRegang).
+ * Set ConnDly to make the power effective at the warm reset.
+ * Set XMT and RCV off.
+ *
+ * @param[in] Node   the node to stop a link on.
+ * @param[in] Link   the link to stop.
+ * @param[in] State  access to special routine for writing link control register
+ * @param[in] Nb     this northbridge.
+ */
+VOID
+Fam10StopLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  // Set ConnDly
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_GLOBAL_EXT_CONTROL_0x16C);
+  Temp = 1;
+  LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
+  // Set TransOff and EndOfChain
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+  Temp = 3;
+  State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h
new file mode 100755
index 0000000000..c903ce3bd1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h
@@ -0,0 +1,66 @@
+/**
+ * @file
+ *
+ * Coherent Family 10h specific Routines.
+ *
+ * Coherent feature Northbridge implementation specific to Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return whether the current configuration exceeds the capability.
+ *
+ */
+BOOLEAN
+Fam10IsExceededCapable (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ */
+VOID
+Fam10StopLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c
new file mode 100755
index 0000000000..1e593ec6ab
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * Initializers for Family 10h northbridge support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "CommonReturns.h"
+#include "htNbCoherent.h"
+#include "htNbCoherentFam10.h"
+#include "htNbNonCoherent.h"
+#include "htNbNonCoherentFam10.h"
+#include "htNbOptimization.h"
+#include "htNbOptimizationFam10.h"
+#include "htNbSystemFam10.h"
+#include "htNbUtilities.h"
+#include "htNbUtilitiesFam10.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/**
+ * Map Northbridge links to package links for Family 10h, Rev D, multi-module.
+ *
+ * Unfortunately, there is no way to do this except to type the BKDG text into this data structure.
+ * Note that there is one entry per package external sublink and each connected internal link.
+ */
+CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] =
+{
+  {0, 0, 0},        ///< Module zero, link 0: package link 0
+  {4, 0, 4},        ///< Module zero, link 4: package link 4
+  {0, 1, 1},        ///< Module one,  link 0: package link 1
+  {4, 1, 5},        ///< Module one,  link 4: package link 5
+  {3, 0, 2},        ///< Module zero, link 3: package link 2
+  {7, 0, 6},        ///< Module zero, link 7: package link 6
+  {2, 0, 3},        ///< Module zero, link 2: package link 3
+  {1, 1, 7},        ///< Module one,  link 1: package link 7
+  {1, 0, HT_LIST_MATCH_INTERNAL_LINK_0},        ///< Internal Link
+  {5, 0, HT_LIST_MATCH_INTERNAL_LINK_1},        ///< Internal Link
+  {6, 0, HT_LIST_MATCH_INTERNAL_LINK_2},        ///< Internal Link
+  {2, 1, HT_LIST_MATCH_INTERNAL_LINK_0},        ///< Internal Link
+  {6, 1, HT_LIST_MATCH_INTERNAL_LINK_1},        ///< Internal Link
+  {5, 1, HT_LIST_MATCH_INTERNAL_LINK_2},        ///< Internal Link
+  {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End
+};
+
+/**
+ * A default Ignore Link list for rev D to power off the 3rd internal sublink.
+ */
+STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = {
+  {HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF},
+  {HT_LIST_TERMINAL}
+};
+
+/**
+ * Initial construction data for Family 10h North Bridge, default, full features.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbDefault =
+{
+  8,
+  WriteRoutingTable,
+  WriteNodeID,
+  ReadDefaultLink,
+  EnableRoutingTables,
+  DisableRoutingTables,
+  VerifyLinkIsCoherent,
+  ReadToken,
+  WriteToken,
+  WriteFullRoutingTable,
+  IsIllegalTypeMix,
+  Fam10IsExceededCapable,
+  Fam10StopLink,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  HandleSpecialNodeCase,
+  ReadSouthbridgeLink,
+  VerifyLinkIsNonCoherent,
+  Fam10SetConfigAddrMap,
+  Fam10NorthBridgeFreqMask,
+  GatherLinkFeatures,
+  SetLinkRegang,
+  SetLinkFrequency,
+  SetLinkUnitIdClumping,
+  Fam10WriteTrafficDistribution,
+  Fam10WriteLinkPairDistribution,
+  Fam10BufferOptimizations,
+  Fam10GetNumCoresOnNode,
+  SetTotalNodesAndCores,
+  GetNodeCount,
+  LimitNodes,
+  ReadTrueLinkFailStatus,
+  Fam10GetNextLink,
+  GetPackageLink,
+  MakeLinkBase,
+  Fam10GetModuleInfo,
+  Fam10PostMailbox,
+  Fam10RetrieveMailbox,
+  Fam10GetSocket,
+  0x00000001,
+  0x00000200,
+  18,
+  TRUE,
+  TRUE,
+  ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY)),
+  NULL,
+  0,
+  NULL,
+  MakeKey,
+  NULL
+};
+
+/**
+ * Initial construction data for Family 10h North Bridge, default, full features.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault =
+{
+  8,
+  WriteRoutingTable,
+  WriteNodeID,
+  ReadDefaultLink,
+  EnableRoutingTables,
+  DisableRoutingTables,
+  VerifyLinkIsCoherent,
+  ReadToken,
+  WriteToken,
+  WriteFullRoutingTable,
+  IsIllegalTypeMix,
+  Fam10IsExceededCapable,
+  Fam10StopLink,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  HandleSpecialNodeCase,
+  ReadSouthbridgeLink,
+  VerifyLinkIsNonCoherent,
+  Fam10SetConfigAddrMap,
+  Fam10RevDNorthBridgeFreqMask,
+  GatherLinkFeatures,
+  SetLinkRegang,
+  SetLinkFrequency,
+  SetLinkUnitIdClumping,
+  Fam10WriteTrafficDistribution,
+  Fam10WriteLinkPairDistribution,
+  Fam10RevDBufferOptimizations,
+  Fam10RevDGetNumCoresOnNode,
+  SetTotalNodesAndCores,
+  GetNodeCount,
+  LimitNodes,
+  ReadTrueLinkFailStatus,
+  Fam10GetNextLink,
+  GetPackageLink,
+  MakeLinkBase,
+  Fam10GetModuleInfo,
+  Fam10PostMailbox,
+  Fam10RetrieveMailbox,
+  Fam10RevDGetSocket,
+  0x00000001,
+  0x00000200,
+  18,
+  TRUE,
+  TRUE,
+  AMD_FAMILY_10_HY,
+  (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
+  0,
+  (IGNORE_LINK *)&Fam10RevDIgnoreLinkList,
+  MakeKey,
+  NULL
+};
+
+/**
+ * Initial construction data for Family 10h North Bridge, for non-coherent only builds.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly =
+{
+  8,
+  (PF_WRITE_ROUTING_TABLE)CommonVoid,
+  (PF_WRITE_NODEID)CommonVoid,
+  (PF_READ_DEFAULT_LINK)CommonReturnZero8,
+  (PF_ENABLE_ROUTING_TABLES)CommonVoid,
+  (PF_DISABLE_ROUTING_TABLES)CommonVoid,
+  (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
+  (PF_READ_TOKEN)CommonReturnZero8,
+  (PF_WRITE_TOKEN)CommonVoid,
+  (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
+  (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
+  (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
+  (PF_STOP_LINK)CommonVoid,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
+  ReadSouthbridgeLink,
+  VerifyLinkIsNonCoherent,
+  Fam10SetConfigAddrMap,
+  Fam10NorthBridgeFreqMask,
+  GatherLinkFeatures,
+  SetLinkRegang,
+  SetLinkFrequency,
+  SetLinkUnitIdClumping,
+  (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
+  Fam10BufferOptimizations,
+  Fam10GetNumCoresOnNode,
+  SetTotalNodesAndCores,
+  GetNodeCount,
+  LimitNodes,
+  ReadTrueLinkFailStatus,
+  Fam10GetNextLink,
+  GetPackageLink,
+  MakeLinkBase,
+  Fam10GetModuleInfo,
+  Fam10PostMailbox,
+  Fam10RetrieveMailbox,
+  Fam10GetSocket,
+  0x00000001,
+  0x00000200,
+  18,
+  TRUE,
+  TRUE,
+  ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY)),
+  NULL,
+  0,
+  NULL,
+  MakeKey,
+  NULL
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
new file mode 100755
index 0000000000..dbe48f051f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * Northbridge non-coherent support for Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbNonCoherentFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
+ *
+ * @param[in]     ConfigMapIndex the map entry to set
+ * @param[in]     SecBus         The secondary bus number to use
+ * @param[in]     SubBus         The subordinate bus number to use
+ * @param[in]     TargetNode     The Node  that shall be the recipient of the traffic
+ * @param[in]     TargetLink     The Link that shall be the recipient of the traffic
+ * @param[in]     State          our global state
+ * @param[in]     Nb             this northbridge
+ */
+VOID
+Fam10SetConfigAddrMap (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT8 CurNode;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
+
+  ASSERT (SecBus <= SubBus);
+  ASSERT (TargetNode <= State->NodesDiscovered);
+  ASSERT (TargetLink < Nb->MaxLinks);
+  Temp = SecBus;
+  Reg.Address.Register += HTHOST_ISOC_REG;
+  LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
+
+  Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
+    ((UINT32)TargetNode << 4) + (UINT32)3;
+  for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
+    Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
+                                   MakePciBusFromNode (CurNode),
+                                   MakePciDeviceFromNode (CurNode),
+                                   CPU_ADDR_FUNC_01,
+                                   REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
+    LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h
new file mode 100755
index 0000000000..29b84d67c4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * Northbridge non-coherent support for Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ */
+VOID
+Fam10SetConfigAddrMap (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
new file mode 100755
index 0000000000..4a5c515228
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
@@ -0,0 +1,214 @@
+/**
+ * @file
+ *
+ * Link optimization support specific to family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htNbOptimizationFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node           Result could (later) be for a specific Node
+ * @param[in]     Interface      Access to non-HT support functions.
+ * @param[in]     Nb             this northbridge
+ *
+ * @return Frequency mask
+ */
+UINT32
+Fam10NorthBridgeFreqMask (
+  IN       UINT8        Node,
+  IN       HT_INTERFACE *Interface,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  UINT32 NbCoreFreq;
+  UINT32 Supported;
+
+  ASSERT (Node < MAX_NODES);
+  ASSERT (Interface != NULL);
+  // The interface to power management will return a system based result.
+  // So we only need to call it once, not on every link.  Save the answer,
+  // and check to see if we can use a saved answer on subsequent calls.
+  //
+  if (Nb->CoreFrequency == 0) {
+    NbCoreFreq = Interface->GetMinNbCoreFreq (Nb->ConfigHandle);
+    NbCoreFreq = (NbCoreFreq / 100);
+    ASSERT (NbCoreFreq != 0);
+    Nb->CoreFrequency = NbCoreFreq;
+  } else {
+    NbCoreFreq = Nb->CoreFrequency;
+  }
+
+  //
+  // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
+  // HT can not go faster than the minimum speed of the northbridge.
+  //
+  if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
+    //  Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1.
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
+  } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
+    // Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1, noting that
+    // next power of two is two greater than non-extended frequencies
+    // (because of the register break).
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
+  } else if (NbCoreFreq > 32) {
+    Supported = HT_FREQUENCY_LIMIT_MAX;
+  } else if (NbCoreFreq == 4) {
+    // unlikely cases, but include as a defensive measure, also avoid trick above
+    Supported = HT_FREQUENCY_LIMIT_400M;
+  } else if (NbCoreFreq == 2) {
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  } else {
+    ASSERT (FALSE);
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  }
+
+  return (Supported);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node           Result could (later) be for a specific Node
+ * @param[in]     Interface      Access to non-HT support functions.
+ * @param[in]     Nb             this northbridge
+ *
+ * @return Frequency mask
+ */
+UINT32
+Fam10RevDNorthBridgeFreqMask (
+  IN       UINT8        Node,
+  IN       HT_INTERFACE *Interface,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  UINT32 NbCoreFreq;
+  UINT32 Supported;
+
+  ASSERT (Node < MAX_NODES);
+  ASSERT (Interface != NULL);
+  // The interface to power management will return a system based result.
+  // So we only need to call it once, not on every link.  Save the answer,
+  // and check to see if we can use a saved answer on subsequent calls.
+  //
+  if (Nb->CoreFrequency == 0) {
+    NbCoreFreq = Interface->GetMinNbCoreFreq (Nb->ConfigHandle);
+    NbCoreFreq = (NbCoreFreq / 100);
+    ASSERT (NbCoreFreq != 0);
+    Nb->CoreFrequency = NbCoreFreq;
+  } else {
+    NbCoreFreq = Nb->CoreFrequency;
+  }
+
+  // For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3.
+  // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3,
+  //  to avoid complicated recovery if the final speed is HT1.)
+  if (NbCoreFreq > 10) {
+    NbCoreFreq = NbCoreFreq * 2;
+  }
+  //
+  // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
+  // HT can not go faster than the minimum speed of the northbridge.
+  //
+  if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
+    //  Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1.
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
+  } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
+    // Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1, noting that
+    // next power of two is two greater than non-extended frequencies
+    // (because of the register break).
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
+  } else if (NbCoreFreq > 32) {
+    Supported = HT_FREQUENCY_LIMIT_MAX;
+  } else if (NbCoreFreq == 4) {
+    // unlikely cases, but include as a defensive measure, also avoid trick above
+    Supported = HT_FREQUENCY_LIMIT_400M;
+  } else if (NbCoreFreq == 2) {
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  } else {
+    ASSERT (FALSE);
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  }
+
+  return (Supported);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.h
new file mode 100755
index 0000000000..e98b9d311e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Link optimization support specific to family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ */
+UINT32
+Fam10NorthBridgeFreqMask (
+  IN       UINT8            Node,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  );
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ */
+UINT32
+Fam10RevDNorthBridgeFreqMask (
+  IN       UINT8            Node,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
new file mode 100755
index 0000000000..d275f060ee
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
@@ -0,0 +1,398 @@
+/**
+ * @file
+ *
+ * System Tuning Family 10h specific routines
+ *
+ * Support for Traffic Distribution and buffer tunings which
+ * can not be done in a register table.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbSystemFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Register Fields for an individual link pair.
+ */
+typedef struct {
+  UINT32 Enable:1;            ///< Enable distribution on this pair.
+  UINT32 Asymmetric:1;        ///< Links are different widths.
+  UINT32 MasterSelect:3;      ///< The master link.
+  UINT32 AlternateSelect:3;   ///< The alternate link.
+} PAIR_SELECT_FIELDS;
+
+/**
+ * Register access union for ::PAIR_SELECT_FIELDS.
+ */
+typedef union {
+  UINT32 Value;               ///< access as a 32 bit value or register.
+  PAIR_SELECT_FIELDS Fields;  ///< access individual fields.
+} PAIR_SELECT;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION}
+ *
+ * @param[in]     Links01   coherent Links from Node 0 to 1
+ * @param[in]     Links10   coherent Links from Node 1 to 0
+ * @param[in]     Nb        this northbridge
+ */
+VOID
+Fam10WriteTrafficDistribution (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR TrafficDistReg;
+
+  TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
+                                            MakePciBusFromNode (0),
+                                            MakePciDeviceFromNode (0),
+                                            CPU_HTNB_FUNC_00,
+                                            REG_HT_TRAFFIC_DIST_0X164);
+
+  // Node 0
+  // DstLnk
+  LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle);
+  // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
+  Temp = 0x0107;
+  LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
+
+  TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1),
+                                            MakePciBusFromNode (1),
+                                            MakePciDeviceFromNode (1),
+                                            CPU_HTNB_FUNC_00,
+                                            REG_HT_TRAFFIC_DIST_0X164);
+
+  // Node 1
+  // DstLnk
+  LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle);
+  // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
+  Temp = 0x0007;
+  LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION}
+ *
+ * Set the links as a pair using the link pair index provided.  Set asymmetric attribute as
+ * provided. If the Master Link is not currently used as the route, fixup the routes for all
+ * nodes which specify the alternate link.
+ *
+ * @param[in]    Node           Set the pair on this node
+ * @param[in]    ConnectedNode  The Node to which this link pair directly connects.
+ * @param[in]    Pair           Using this pair set in the register
+ * @param[in]    Asymmetric     True if different widths
+ * @param[in]    MasterLink     Set this as the master link and in the route
+ * @param[in]    AlternateLink  Set this as the alternate link
+ * @param[in]    Nb             this northbridge
+ *
+ */
+VOID
+Fam10WriteLinkPairDistribution (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 CurrentRoute;
+  UINT32 MasterRoute;
+  UINT32 AlternateRoute;
+  PAIR_SELECT Selection;
+  UINT32 RouteIndex;
+
+  ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES));
+  ASSERT (Pair < MAX_LINK_PAIRS);
+  ASSERT (MasterLink < Nb->MaxLinks);
+  ASSERT (AlternateLink < Nb->MaxLinks);
+
+  // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of
+  // Alternate link with Master link.  If routing used the master link, no update is necessary.
+  MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1));
+  AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_ROUTE0_0X40);
+  for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) {
+    Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4);
+    LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
+    if ((CurrentRoute & AlternateRoute) != 0) {
+      // Since Master and Alternate are redundant, the route must use one or the other but not both.
+      ASSERT ((CurrentRoute & MasterRoute) == 0);
+      // Set the master route for Request, Response or Broadcast only if the alternate was used for that case.
+      // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response.
+      CurrentRoute = ((CurrentRoute & ~AlternateRoute) |
+                      ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute));
+      LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
+    }
+  }
+
+  // Set the Link Pair and Enable it
+  Selection.Fields.Enable = 1;
+  Selection.Fields.Asymmetric = Asymmetric;
+  Selection.Fields.MasterSelect = MasterLink;
+  Selection.Fields.AlternateSelect = AlternateLink;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_PAIR_DIST_0X1E0);
+  LibAmdPciWriteBits (
+    Reg,
+    ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1),
+    (PAIR_SELECT_OFFSET * Pair),
+    &Selection.Value,
+    Nb->ConfigHandle
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Family 10h specific tunings.
+ *
+ * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State  global state
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+Fam10BufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR currentPtr;
+  PCI_ADDR GangedReg;
+  UINT8 i;
+
+  ASSERT (Node < MAX_NODES);
+
+  //
+  // Link to XCS Token Count Tuning
+  //
+  // For each active Link that we reganged (so this unfortunately can't go into the PCI reg
+  // table), we have to switch the Link to XCS Token Counts to the ganged state.
+  // We do this here for the non - uma case, which is to write the values that would have
+  // been power on defaults if the Link was ganged at cold reset.
+  //
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+    if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
+      // If the Link is greater than 4, this is a subLink 1, so it is not reganged.
+      if ((*State->PortList)[i].Link < 4) {
+        currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                              MakePciBusFromNode (Node),
+                                              MakePciDeviceFromNode (Node),
+                                              CPU_NB_FUNC_03,
+                                              REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link)
+          );
+        if ((*State->PortList)[i].SelRegang) {
+          // Handle all the regang Token count adjustments
+
+          // SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2
+          Temp = 0xAA;
+          LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle);
+          // SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0
+          Temp = 0;
+          LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle);
+          // [FreeTok] = 3
+          Temp = 3;
+          LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
+
+        } else {
+          // Read the regang bit in hardware
+          GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID),
+                                               MakePciBusFromNode ((*State->PortList)[i].NodeID),
+                                               MakePciDeviceFromNode ((*State->PortList)[i].NodeID),
+                                               CPU_HTNB_FUNC_00,
+                                               REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
+          LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle);
+          if (Temp == 1) {
+            // handle a minor adjustment for strapped ganged Links.  If SelRegang is false we
+            // didn't do the regang, so if the bit is on then it's hardware strapped.
+            //
+
+            // [FreeTok] = 3
+            Temp = 3;
+            LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Family 10h specific tunings.
+ *
+ * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State  global state
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+Fam10RevDBufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+  UINT8 i;
+  FINAL_LINK_STATE FinalLinkState;
+  UINT32 Widthin;
+  UINT32 Widthout;
+
+  ASSERT (Node < MAX_NODES);
+
+  //
+  // Internal link fixup.
+  // When powering off internal link 2, a performance optimization may be possible where its buffers
+  // can be made available to the external paired sublink.  If the conditions are met, do the fix up here.
+  //
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+    if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
+      // Is this a sublink 0 paired with internal link 2?
+      if (((*State->PortList)[i].Link < 4) &&
+          (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) {
+        FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State);
+        // Are we ignoring the internal link 2 with Power Off?
+        if (FinalLinkState == POWERED_OFF) {
+          // Read the regang bit in hardware.
+          Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                         MakePciBusFromNode (Node),
+                                         MakePciDeviceFromNode (Node),
+                                         CPU_HTNB_FUNC_00,
+                                         REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
+          LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+          // If it's already ganged, skip to the width fix up.
+          if (Temp == 0) {
+            // Clear EndOfChain / XmitOff on internal sublink
+            Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb);
+            Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+            Temp = 0;
+            State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
+
+            // Gang the link
+            Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb);
+          }
+
+          // Set InLnSt = PHY_OFF in register table.
+          // Set sublink 0 widths to 8 bits
+          if ((*State->PortList)[i].SelWidthOut > 8) {
+            (*State->PortList)[i].SelWidthOut = 8;
+          }
+          if ((*State->PortList)[i].SelWidthIn > 8) {
+            (*State->PortList)[i].SelWidthIn = 8;
+          }
+          Widthout = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
+          Widthin = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
+          Temp = (Widthin & 7) | ((Widthout & 7) << 4);
+          Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb);
+          Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+          State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
+        }
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h
new file mode 100755
index 0000000000..4994df0593
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ *
+ * System Tuning Family 10h specific routines
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ */
+VOID
+Fam10WriteTrafficDistribution (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  );
+
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ */
+VOID
+Fam10WriteLinkPairDistribution (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  );
+
+/**
+ * Family 10h specific tunings.
+ *
+ */
+VOID
+Fam10BufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Family 10h Rev D specific tunings.
+ *
+ */
+VOID
+Fam10RevDBufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
new file mode 100755
index 0000000000..8f7cacf4fd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
@@ -0,0 +1,441 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * These routines are needed for support of more than one feature area.
+ * Collect them in this file so build options don't remove them.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbUtilitiesFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+UINT8
+Fam10GetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Result;
+  UINT32 Leveling;
+  UINT32 Cores;
+  UINT8 i;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Read CmpCap
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+
+  LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
+
+  // Support Downcoring
+  Result = Cores;
+  Cores++;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_DOWNCORE_3X190);
+  LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle);
+  for (i = 0; i < Cores; i++) {
+    if ((Leveling & ((UINT32) 1 << i)) != 0) {
+      Result--;
+    }
+  }
+  return (UINT8) (Result + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}.
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+UINT8
+Fam10RevDGetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Result;
+  UINT32 Leveling;
+  UINT32 Cores;
+  UINT32 Cores2;
+  UINT8 i;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Read CmpCap
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+
+  LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle);
+  Cores = Cores + (Cores2 << 2);
+
+  // Support Downcoring
+  Result = Cores;
+  Cores++;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_DOWNCORE_3X190);
+  LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle);
+  for (i = 0; i < Cores; i++) {
+    if ((Leveling & ((UINT32) 1 << i)) != 0) {
+      Result--;
+    }
+  }
+  return (UINT8) (Result + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ * @HtNbMethod{::F_GET_NEXT_LINK}
+ *
+ * Family 10h specific implementation use the Internal Link field in
+ * the northbridge to prioritize internal links in the order.
+ *
+ * @param[in]     Node The node on which to iterate links.
+ * @param[in,out] Link IN: the current iteration context, OUT: the next link.
+ * @param[in]     Nb   This Northbridge, access to config pointer.
+ *
+ * @retval LinkIteratorExternal    The current Link is an external link.
+ * @retval LinkIteratorInternal    The current Link is an internal link.
+ * @retval LinkIteratorEnd         There is no next link (Link is back to BEGIN).
+ *
+ */
+LINK_ITERATOR_STATUS
+Fam10GetNextLink (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32   InternalLinks;
+  UINT32   ExternalLinks;
+  UINT32   HigherLinks;
+  BOOLEAN  IsInternalLink;
+  LINK_ITERATOR_STATUS Status;
+
+  ASSERT ((Node < MAX_NODES));
+  ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN));
+  InternalLinks = 0;
+  ExternalLinks = 0;
+
+  // Read IntLnkRoute from the Link Initialization Status register.
+  // (Note that this register field is not reserved prior to rev D, but should be zero.)
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_INITIALIZATION_0X1A0);
+
+  LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle);
+  // The external links are all possible links which are not Internal
+  ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks);
+  // Can't have no possible links!
+  ASSERT ((ExternalLinks != 0) || (InternalLinks != 0));
+
+
+  if (*Link == LINK_ITERATOR_BEGIN) {
+    // If the request is for the first link (BEGIN), get it
+    if (InternalLinks != 0) {
+      *Link = LibAmdBitScanForward (InternalLinks);
+      Status = LinkIteratorInternal;
+    } else {
+      *Link = LibAmdBitScanForward (ExternalLinks);
+      Status = LinkIteratorExternal;
+    }
+  } else {
+    // If the iterator is not at the beginning, search for the next Link starting from the
+    // current link.
+    HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1);
+    IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0);
+    if (IsInternalLink && (HigherLinks != 0)) {
+      // We are still on internal links and there are more to do.
+      *Link = LibAmdBitScanForward (HigherLinks);
+      Status = LinkIteratorInternal;
+    } else {
+      if (IsInternalLink) {
+        // We are transitioning now from internal to external, so get the first external link
+        HigherLinks = ExternalLinks;
+      } else {
+        // We are already iterating over external links, so get the next one
+        HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1);
+      }
+      if (HigherLinks != 0) {
+        *Link = LibAmdBitScanForward (HigherLinks);
+        Status = LinkIteratorExternal;
+      } else {
+        // The end of all links
+        *Link = LINK_ITERATOR_BEGIN;
+        Status = LinkIteratorEnd;
+      }
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ * @HtNbMethod{::F_GET_MODULE_INFO}
+ *
+ * Provide the Processor module type, single or multi, and the node's module id.
+ *
+ * @param[in]     Node                the Node
+ * @param[out]    ModuleType          0 for Single, 1 for Multi
+ * @param[out]    Module              The module number of this node (0 if Single)
+ * @param[in]     Nb                  this northbridge
+ *
+ */
+VOID
+Fam10GetModuleInfo (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 MultNodeCpu;
+  UINT32 IntNodeNum;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+  LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle);
+
+  *ModuleType = (UINT8) MultNodeCpu;
+  *Module = (UINT8) IntNodeNum;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbMethod{::F_GET_SOCKET}
+ *
+ * The hardware socket naming method is not available for Family 10h prior to rev D.
+ *
+ * @param[in]   Node    The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb      Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+UINT8
+Fam10GetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  ASSERT ((Node < MAX_NODES));
+  ASSERT (TempNode < MAX_NODES);
+  ASSERT (Nb != NULL);
+  return (Node);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbMethod{::F_GET_SOCKET}
+ *
+ * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr.
+ *
+ * @param[in]   Node    The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb      Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+UINT8
+Fam10RevDGetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Socket;
+  PCI_ADDR Reg;
+
+  ASSERT ((TempNode < MAX_NODES));
+  ASSERT ((Node < MAX_NODES));
+  // Read SbiAddr
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode),
+                                 MakePciBusFromNode (TempNode),
+                                 MakePciDeviceFromNode (TempNode),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_SBI_CONTROL_3X1E4);
+  LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle);
+  return ((UINT8) Socket);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ * @HtNbMethod{::F_POST_MAILBOX}
+ *
+ * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
+ * and module info.
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailboxes   The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+VOID
+Fam10PostMailbox (
+  IN       UINT8 Node,
+  IN       AP_MAILBOXES ApMailboxes,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_MCA_LINK_THRESHOLD_3X168);
+  LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle);
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_MCA_L3_THRESHOLD_3X170);
+  LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Retrieve info from a node's mailbox.
+ *
+ * @HtNbMethod{::F_RETRIEVE_MAILBOX}
+ *
+ * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
+ * and module info.
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     Nb            this northbridge
+ *
+ * @return        The ap mailbox info
+ *
+ */
+AP_MAIL_INFO
+Fam10RetrieveMailbox (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  AP_MAIL_INFO ApMailInfo;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_MCA_LINK_THRESHOLD_3X168);
+  LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle);
+  return ApMailInfo;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h
new file mode 100755
index 0000000000..f78fccd52e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h
@@ -0,0 +1,128 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ */
+UINT8
+Fam10GetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ */
+UINT8
+Fam10RevDGetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ */
+LINK_ITERATOR_STATUS
+Fam10GetNextLink (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ */
+VOID
+Fam10GetModuleInfo (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ */
+UINT8
+Fam10GetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ */
+UINT8
+Fam10RevDGetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ */
+VOID
+Fam10PostMailbox (
+  IN       UINT8 Node,
+  IN       AP_MAILBOXES ApMailboxes,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Retrieve info from a node's mailbox.
+ *
+ */
+AP_MAIL_INFO
+Fam10RetrieveMailbox (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
new file mode 100755
index 0000000000..56ed891e8c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
@@ -0,0 +1,779 @@
+/**
+ * @file
+ *
+ * Coherent Discovery Routines.
+ *
+ * Contains routines for discovery, along with Temporary routing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htFeatDynamicDiscovery.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define LOGICAL_PROCESSOR_NONE 0xFF
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Status result from exploring for a new node on a link.
+ */
+typedef enum {
+  ExploreNodeStatusNew,    ///< A new node was discovered
+  ExploreNodeStatusGood,   ///< A new link to an already known node was discovered
+  ExploreNodeStatusStop,   ///< Discovery must halt now.
+  ExploreNodeStatusIgnore, ///< A new node was ignored on purpose.
+  ExploreNodeStatusMax     ///< Use for bounds check and limit only
+} EXPLORE_NODE_STATUS;
+
+/**
+ * Save all the information needed about a node at its discovery.
+ *
+ * When we can access the node at a known temporary route, read everything needed
+ * to do node to socket mapping, post to ap mailbox at later times.
+ */
+typedef struct {
+  UINT8       LogicalProcessor;     ///< Independent of Node,Socket group nodes into logical
+                                    ///< processors based on discovery.
+  UINT8       CurrentNode;          ///< The node from which discovery occurred.
+  UINT8       CurrentLink;          ///< The link on that node which we explored.
+  UINT8       PackageLink;          ///< The package level link corresponding to CurrentLink.
+  UINT8       CurrentModuleType;    ///< The current node's module type, Single or Multiple.
+  UINT8       CurrentModule;        ///< This current node's module id.
+  UINT8       HardwareSocket;       ///< Save the hardware socket strap (for hardware socket method).
+  UINT8       NewModuleType;        ///< The new node's module type, Single or Multiple.
+  UINT8       NewModule;            ///< The new node's module id.
+} NEW_NODE_SAVED_INFO_ITEM;
+
+/**
+ * A "no info" initializer for saved new node info.
+ */
+STATIC CONST NEW_NODE_SAVED_INFO_ITEM ROMDATA NoInfoSavedYet =
+{
+  LOGICAL_PROCESSOR_NONE, 0, 0, 0, 0, 0, 0, 0
+};
+
+/**
+ * A list of all the new node info, indexed by each new node's nodeid.
+ */
+typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***              GENERIC HYPERTRANSPORT DISCOVERY CODE                  ***
+ ***************************************************************************/
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Ensure a request / response route from target Node to bsp.
+ *
+ * Since target Node is always a predecessor of actual target Node, each Node gets a
+ * route to actual target on the Link that goes to target.  The routing produced by
+ * this routine is adequate for config access during discovery, but NOT for coherency.
+ *
+ * @param[in] TargetNode     the path to actual target goes through target
+ * @param[in] ActualTarget   the ultimate target being routed to
+ * @param[in] State           our global state, port config info
+ *
+ */
+VOID
+STATIC
+routeFromBSP (
+  IN       UINT8        TargetNode,
+  IN       UINT8        ActualTarget,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT8 PredecessorNode;
+  UINT8 PredecessorLink;
+  UINT8 CurrentPair;
+
+  if (TargetNode == 0) {
+    return;  //  BSP has no predecessor, stop
+  }
+
+  // Search for the Link that connects TargetNode to its predecessor
+  CurrentPair = 0;
+  while ((*State->PortList)[CurrentPair*2 + 1].NodeID != TargetNode) {
+    CurrentPair++;
+    ASSERT (CurrentPair < State->TotalLinks);
+  }
+
+  PredecessorNode = (*State->PortList)[ (CurrentPair * 2)].NodeID;
+  PredecessorLink = (*State->PortList)[ (CurrentPair * 2)].Link;
+
+  // Recursively call self to ensure the route from the BSP to the Predecessor
+  // Node is established
+  routeFromBSP (PredecessorNode, ActualTarget, State);
+
+  State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Test Compatibility of a new node, and handle failure.
+ *
+ * Make the compatibility test call for the northbridge.
+ * If the new node is incompatible, force 1P.  Notify the event.
+ * Additionally, invoke the northbridge stop link method, to
+ * implement isolation of the BSP from any incompatible node.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ * @retval TRUE            Check is Ok
+ * @retval FALSE           Check failed and is handled
+ */
+BOOLEAN
+STATIC
+CheckCompatible (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 NodeToKill;
+  BOOLEAN Result;
+
+  Result = TRUE;
+
+  // Check the northbridge of the Node we just found, to make sure it is compatible
+  // before doing anything else to it.
+  //
+  if (State->Nb->IsIllegalTypeMix ((CurrentNode + 1), State->Nb)) {
+    IDS_ERROR_TRAP;
+
+    // Notify BIOS of event
+    NotifyFatalCohProcessorTypeMix (
+      CurrentNode,
+      CurrentLink,
+      State->NodesDiscovered,
+      State
+      );
+
+    // If Node is not compatible, force boot to 1P
+    // If they are not compatible stop cHT init and:
+    //     1. Disable all cHT Links on the BSP
+    //     2. Configure the BSP routing tables as a UP.
+    //     3. Notify main BIOS.
+    //
+    State->NodesDiscovered = 0;
+    State->TotalLinks = 0;
+    // Abandon our coherent Link data structure.  At this point there may
+    // be coherent Links on the BSP that are not yet in the portList, and
+    // we have to turn them off anyway.  So depend on the hardware to tell us.
+    //
+    for (CurrentLink = 0; CurrentLink < State->Nb->MaxLinks; CurrentLink++) {
+      // Stop all Links which are connected, coherent, and ready
+      if (State->Nb->VerifyLinkIsCoherent (0, CurrentLink, State->Nb)) {
+        State->Nb->StopLink (0, CurrentLink, State, State->Nb);
+      }
+    }
+
+    for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
+      State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
+    }
+
+    State->HtInterface->CleanMapsAfterError (State);
+
+    // End Coherent Discovery
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check the system MP capability with a new node and handle any failure.
+ *
+ * Invoke the northbridge MP capability check.  If it fails, notify the event and force
+ * 1P.  Should not need to stop links on the BSP.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ * @retval TRUE            Check is Ok
+ * @retval FALSE           Check Failed and is handled
+ */
+BOOLEAN
+STATIC
+CheckCapable (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 NodeToKill;
+  BOOLEAN Result;
+
+  Result = TRUE;
+
+  // Check the capability of northbridges against the currently known configuration
+  if (State->Nb->IsExceededCapable ((CurrentNode + 1), State, State->Nb)) {
+    IDS_ERROR_TRAP;
+    // Notify BIOS of event
+    NotifyFatalCohMpCapMismatch (
+      CurrentNode,
+      CurrentLink,
+      State->SysMpCap,
+      State->NodesDiscovered,
+      State
+      );
+
+    State->NodesDiscovered = 0;
+    State->TotalLinks = 0;
+
+    for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
+      State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
+    }
+
+    State->HtInterface->CleanMapsAfterError (State);
+
+    // End Coherent Discovery
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make all the tests needed to determine if a link should be added to the system data structure.
+ *
+ * The link should be added to the system data structure if it is:
+ * - not being Ignored on this boot
+ * - not having a hard failure
+ * - coherent and connected
+ * - not already in the system data structure
+ * - not subject to some special handling case.
+ * .
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ * @retval FALSE          This link should not be added.
+ * @retval TRUE           This link should explored and added to the system.
+ */
+BOOLEAN
+STATIC
+IsLinkToAdd (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       STATE_DATA  *State
+  )
+{
+  BOOLEAN Linkfound;
+  UINTN Port;
+  FINAL_LINK_STATE FinalLinkState;
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  FinalLinkState = State->HtInterface->GetIgnoreLink (CurrentNode, CurrentLink, State->Nb->DefaultIgnoreLinkList, State);
+  if ((FinalLinkState != MATCHED) && (FinalLinkState != POWERED_OFF)) {
+    if (!State->Nb->ReadTrueLinkFailStatus (CurrentNode, CurrentLink, State, State->Nb)) {
+      // Make sure that the Link is connected, coherent, and ready
+      if (State->Nb->VerifyLinkIsCoherent (CurrentNode, CurrentLink, State->Nb)) {
+        // Test to see if the CurrentLink has already been explored
+        Linkfound = FALSE;
+        for (Port = 0; Port < State->TotalLinks; Port++) {
+          if ((((*State->PortList)[ (Port * 2 + 1)].NodeID == CurrentNode) &&
+               ((*State->PortList)[ (Port * 2 + 1)].Link == CurrentLink)) ||
+              (((*State->PortList)[ (Port * 2)].NodeID == CurrentNode) &&
+               ((*State->PortList)[ (Port * 2)].Link == CurrentLink))) {
+            Linkfound = TRUE;
+            break;
+          }
+        }
+        if (!Linkfound) {
+          if (!State->Nb->HandleSpecialLinkCase (CurrentNode, CurrentLink, State, State->Nb)) {
+            Result = TRUE;
+          }
+        }
+      }
+    }
+  } else {
+    if (FinalLinkState == POWERED_OFF) {
+      State->Nb->StopLink (CurrentNode, CurrentLink, State, State->Nb);
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Explore for a new node over a link, handling whatever is found.
+ *
+ * Open a temporary route over a link on the current node.
+ * Make checks for compatibility and capability in the proper sequence.
+ * If the node found is new, set a token to it, so it will be recognized in the
+ * future, and notify an event for finding a new node.
+ * If the node is already found (token is set), just return status.
+ *
+ * @param[in]     CurrentNode         The node we are exploring from
+ * @param[in]     CurrentLink         The Link on that node to explore.
+ * @param[in]     LogicalProcessor    The processor to update in the maps.
+ * @param[in,out] NewNodeSavedInfo    The saved info for nodes in that processor.
+ * @param[in]     State               Access to Northbridge interface.
+ *
+ * @retval ExploreNodeStatusNew    A new node was found
+ * @retval ExploreNodeStatusGood   This is a good link to an already known node
+ * @retval ExploreNodeStatusStop   Stop Coherent Discovery
+ */
+EXPLORE_NODE_STATUS
+STATIC
+ExploreNode (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       UINT8       LogicalProcessor,
+  IN OUT   NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 Token;
+  EXPLORE_NODE_STATUS Status;
+
+  // Modify CurrentNode's routing table to use CurrentLink to send
+  // traffic to CurrentNode + 1
+  //
+  State->Nb->WriteRoutingTable (CurrentNode, (CurrentNode + 1), CurrentLink, State->Nb);
+  if (!State->Nb->HandleSpecialNodeCase ((CurrentNode + 1), CurrentLink, State, State->Nb)) {
+    if (CheckCompatible (CurrentNode, CurrentLink, State)) {
+      // Read Token from Current + 1
+      Token = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
+      ASSERT (Token <= State->NodesDiscovered);
+      if (Token == 0) {
+        State->NodesDiscovered++;
+        ASSERT (State->NodesDiscovered < MAX_NODES);
+        if (CheckCapable (CurrentNode, CurrentLink, State)) {
+          Token = State->NodesDiscovered;
+          State->Nb->WriteToken ((CurrentNode + 1), Token, State->Nb);
+          // Fill in Saved New Node info for the discovered node.
+          // We do this so we don't have to keep a temporary route open to it.
+          // So we save everything that might be needed to set the socket and node
+          // maps for either the software or hardware method.
+          //
+          (*NewNodeSavedInfo)[Token].LogicalProcessor = LogicalProcessor;
+          (*NewNodeSavedInfo)[Token].CurrentNode = CurrentNode;
+          (*NewNodeSavedInfo)[Token].CurrentLink = CurrentLink;
+          (*NewNodeSavedInfo)[Token].PackageLink = State->Nb->GetPackageLink (CurrentNode, CurrentLink, State->Nb);
+          (*NewNodeSavedInfo)[Token].HardwareSocket = State->Nb->GetSocket (Token, (CurrentNode + 1), State->Nb);
+          State->Nb->GetModuleInfo (
+            CurrentNode,
+            &((*NewNodeSavedInfo)[Token].CurrentModuleType),
+            &((*NewNodeSavedInfo)[Token].CurrentModule),
+            State->Nb
+            );
+          State->Nb->GetModuleInfo (
+            (CurrentNode + 1),
+            &((*NewNodeSavedInfo)[Token].NewModuleType),
+            &((*NewNodeSavedInfo)[Token].NewModule),
+            State->Nb
+            );
+
+          // Notify BIOS with info
+          NotifyInfoCohNodeDiscovered (
+            CurrentNode,
+            CurrentLink,
+            Token,
+            (CurrentNode + 1),
+            State
+            );
+          Status = ExploreNodeStatusNew;
+        } else {
+          // Failed Capable
+          Status = ExploreNodeStatusStop;
+        }
+      } else {
+        // Not a new node, token already set
+        Status = ExploreNodeStatusGood;
+      }
+    } else {
+      // Failed Compatible
+      Status = ExploreNodeStatusStop;
+    }
+  } else {
+    // Ignore this node
+    Status = ExploreNodeStatusIgnore;
+  }
+
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process all the saved new node info for the current processor.
+ *
+ * When all nodes in the processor have been discovered, we can process all the saved
+ * info about the nodes.  We add each node to the socket and node maps.
+ *
+ * @param[in]    LogicalProcessor    The processor to update in the maps.
+ * @param[in]    NewNodeSavedInfo    The saved info for nodes in that processor.
+ * @param[in]    State               Our system representation.
+ */
+VOID
+STATIC
+ProcessSavedNodeInfo (
+  IN       UINT8                    LogicalProcessor,
+  IN       NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 NewNode;
+  UINT8 HardwareSocket;
+
+  // Can't have more processors than nodes, just more (or equal) nodes than processors.
+  ASSERT (LogicalProcessor <= (State->NodesDiscovered));
+  HardwareSocket = 0xFF;
+  // Find the Hardware Socket value to use (if we are using the hardware socket naming method).
+  // The new nodes are the ones in this processor, so find the one that is module 0.
+  for (NewNode = 0; NewNode < (State->NodesDiscovered + 1); NewNode++) {
+    if (((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) &&
+        ((*NewNodeSavedInfo)[NewNode].NewModule == 0)) {
+      HardwareSocket = (*NewNodeSavedInfo)[NewNode].HardwareSocket;
+      break;
+    }
+  }
+  // We must have found a result, however, the hardware socket value doesn't have to be correct
+  // unless we are using the hardware socket naming method.  Northbridge code should return the
+  // node number for the hardware socket if hardware socket strapping is not supported (i.e. no sbi).
+  ASSERT (HardwareSocket != 0xFF);
+
+  // Set the node to socket maps for this processor.  Node zero is always handled specially,
+  // so skip it in this loop.
+  for (NewNode = 1; NewNode < (State->NodesDiscovered + 1); NewNode++) {
+    if ((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) {
+      // For the currently discovered logical processor, update node to socket
+      // map for all the processor's nodes.
+      State->HtInterface->SetNodeToSocketMap (
+        (*NewNodeSavedInfo)[NewNode].CurrentNode,
+        (*NewNodeSavedInfo)[NewNode].CurrentModule,
+        (*NewNodeSavedInfo)[NewNode].PackageLink,
+        NewNode,
+        HardwareSocket,
+        (*NewNodeSavedInfo)[NewNode].NewModule,
+        State);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create and add a new link to the system data structure.
+ *
+ * Add the two port list data structures, source first, initializing
+ * the two node ids and the link values.  The node id of the remote
+ * node is its token value.  Also, update the adjacency matrix and
+ * node degree table.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  TempRoute   The temporary node route that goes over that link.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ */
+VOID
+STATIC
+AddLinkToSystem (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       UINT8       TempRoute,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 Token;
+
+  ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
+
+  Token = State->Nb->ReadToken (TempRoute, State->Nb);
+
+  (*State->PortList)[State->TotalLinks * 2].Type = PORTLIST_TYPE_CPU;
+  (*State->PortList)[State->TotalLinks * 2].Link = CurrentLink;
+  (*State->PortList)[State->TotalLinks * 2].NodeID = CurrentNode;
+
+  (*State->PortList)[State->TotalLinks * 2 + 1].Type = PORTLIST_TYPE_CPU;
+  (*State->PortList)[State->TotalLinks * 2 + 1].Link = State->Nb->ReadDefaultLink (TempRoute, State->Nb);
+  (*State->PortList)[State->TotalLinks * 2 + 1].NodeID = Token;
+
+  State->TotalLinks++;
+
+  if ( !State->Fabric->SysMatrix[CurrentNode][Token] ) {
+    State->Fabric->SysDegree[CurrentNode]++;
+    State->Fabric->SysDegree[Token]++;
+    State->Fabric->SysMatrix[CurrentNode][Token] = TRUE;
+    State->Fabric->SysMatrix[Token][CurrentNode] = TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Start discovery from a new node.
+ *
+ * If the node is not the BSP, establish a route between the node and the
+ * BSP for request/response.
+ * Set the node id, and enable routing on this node.  This gives us control
+ * on that node to isolate links, by specifying each link in turn as the route
+ * to a possible new node.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ */
+VOID
+STATIC
+StartFromANewNode (
+  IN       UINT8       CurrentNode,
+  IN       STATE_DATA  *State
+  )
+{
+  if (CurrentNode != 0) {
+    // Set path from BSP to CurrentNode
+    routeFromBSP (CurrentNode, CurrentNode, State);
+
+    // Set path from BSP to CurrentNode for CurrentNode + 1 if
+    // CurrentNode + 1 != MAX_NODES
+    //
+    if ((CurrentNode + 1) != MAX_NODES) {
+      routeFromBSP (CurrentNode, (CurrentNode + 1), State);
+    }
+
+    // Configure CurrentNode to route traffic to the BSP through its
+    // default Link
+    //
+    State->Nb->WriteRoutingTable (CurrentNode, 0, State->Nb->ReadDefaultLink (CurrentNode, State->Nb), State->Nb);
+  }
+
+  // Set CurrentNode's NodeID field to CurrentNode
+  State->Nb->WriteNodeID (CurrentNode, CurrentNode, State->Nb);
+
+  // Enable routing tables on CurrentNode
+  State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Back up from exploring a one-deep internal node.
+ *
+ * When a newly discovered node has internal package links to another
+ * node in the same processor, discovery moves to that node to do the
+ * internal links.  Afterwards, this routine provides recovery from that.
+ * The node needs to respond again using deflnk rather than routing, so
+ * that connections from other nodes to that one can be identified.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ */
+VOID
+STATIC
+BackUpFromANode (
+  IN       UINT8       CurrentNode,
+  IN       STATE_DATA  *State
+  )
+{
+  if (CurrentNode != 0) {
+    // Disable routing tables on CurrentNode
+    State->Nb->DisableRoutingTables (CurrentNode, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dynamically Discover all coherent devices in the system.
+ *
+ * @HtFeatMethod{::F_COHERENT_DISCOVERY}
+ *
+ * Initialize some basics like Node IDs and total Nodes found in the
+ * process. As we go we also build a representation of the discovered
+ * system which we will use later to program the routing tables.
+ * During this step, the routing is via default Link back to BSP and
+ * to each new Node on the Link it was discovered on (no coherency is
+ * active yet).
+ *
+ * In the case of multiple nodes per processor, do a one deep exploration of internal links
+ * to ensure those node pairs are always numbered n, n + 1.
+ *
+ * @param[in,out] State     our global state
+ *
+ */
+VOID
+CoherentDiscovery (
+  IN OUT   STATE_DATA *State
+  )
+{
+  UINT8 CurrentNode;
+  UINT8 OneDeepNode;
+  UINT8 OneDeepLink;
+  UINT8 CurrentLink;
+  UINT8 LogicalProcessor;
+  EXPLORE_NODE_STATUS ExplorationStatus;
+  LINK_ITERATOR_STATUS LinkIteratorStatus;
+  NEW_NODE_SAVED_INFO_ITEM NewNodeSavedInfoItems [MAX_NODES];
+  NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo;
+
+  // Initially no info exists for any node, but the BSP is part of logical processor zero.
+  for (CurrentNode = 0; CurrentNode < MAX_NODES; CurrentNode++) {
+    NewNodeSavedInfoItems [CurrentNode] = NoInfoSavedYet;
+  }
+  NewNodeSavedInfoItems[0].LogicalProcessor = 0;
+  NewNodeSavedInfoItems[0].HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
+  State->Nb->GetModuleInfo (0, &NewNodeSavedInfoItems[0].NewModuleType, &NewNodeSavedInfoItems[0].NewModule, State->Nb);
+  NewNodeSavedInfo = (NEW_NODE_SAVED_INFO_LIST) NewNodeSavedInfoItems;
+
+  CurrentNode = 0;
+  CurrentLink = LINK_ITERATOR_BEGIN;
+  LogicalProcessor = 0;
+  // An initial status, for node zero if you will.
+  ExplorationStatus = ExploreNodeStatusGood;
+
+  //
+  // Entries are always added in pairs, the even indices are the 'source'
+  // side closest to the BSP, the odd indices are the 'destination' side
+  //
+
+  while ((CurrentNode <= State->NodesDiscovered) && (ExplorationStatus != ExploreNodeStatusStop)) {
+    StartFromANewNode (CurrentNode, State);
+
+    //
+    // Explore all internal links
+    //
+    LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
+
+    while ((LinkIteratorStatus == LinkIteratorInternal) &&
+           (ExplorationStatus != ExploreNodeStatusStop)) {
+      if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
+        ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
+        if ((ExplorationStatus == ExploreNodeStatusGood) ||
+            (ExplorationStatus == ExploreNodeStatusNew)) {
+          AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
+        }
+      }
+      LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
+    }
+    if (CurrentNode == 0) {
+      // The BSP processor is completely discovered now.
+      ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
+      LogicalProcessor++;
+    }
+
+    //
+    // Explore all the external links from this node.
+    //
+
+    // Starting this iteration using the link that we last got in the iteration above.
+    while ((LinkIteratorStatus == LinkIteratorExternal) &&
+           (ExplorationStatus != ExploreNodeStatusStop)) {
+      if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
+        ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
+        if (ExplorationStatus == ExploreNodeStatusNew) {
+          AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
+          // If this is a new node, we need to explore to its internal mate, if any.
+          // This allows us to keep internal node pairs as ids n, n+1
+          // We use special link and node variables so we can keep our context.
+          OneDeepLink = 0xFF;
+          OneDeepNode = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
+          StartFromANewNode (OneDeepNode, State);
+          LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
+          while ((LinkIteratorStatus == LinkIteratorInternal) &&
+                 (ExplorationStatus != ExploreNodeStatusStop)) {
+            if (IsLinkToAdd (OneDeepNode, OneDeepLink, State)) {
+              ExplorationStatus = ExploreNode (OneDeepNode, OneDeepLink, LogicalProcessor, NewNodeSavedInfo, State);
+              if ((ExplorationStatus == ExploreNodeStatusGood) ||
+                  (ExplorationStatus == ExploreNodeStatusNew)) {
+                AddLinkToSystem (OneDeepNode, OneDeepLink, (OneDeepNode + 1), State);
+              }
+            }
+            LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
+          }
+          // Since we completed all the node's internal links, we found all the nodes in that processor.
+          ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
+          LogicalProcessor++;
+          // Restore node to discoverable state.  Otherwise you can't tell what links it is connected on.
+          BackUpFromANode (OneDeepNode, State);
+        } else {
+          if (ExplorationStatus == ExploreNodeStatusGood) {
+            AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
+          }
+        }
+      }
+      LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
+    }
+    CurrentNode++;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
new file mode 100755
index 0000000000..9331540e35
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * Coherent Discovery Interface.
+ *
+ * Contains interface to the coherent discovery feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_DYNAMIC_DISCOVERY_H_
+#define _HT_FEAT_DYNAMIC_DISCOVERY_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Dynamically Discover all coherent devices in the system.
+ *
+ */
+VOID
+CoherentDiscovery (
+  IN OUT   STATE_DATA *State
+  );
+
+#endif  /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
new file mode 100755
index 0000000000..1b25dd7c41
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
@@ -0,0 +1,215 @@
+/**
+ * @file
+ *
+ * Routines for re-ganging Links.
+ *
+ * Implement the reganging feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htFeatGanging.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATGANGING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ * @HtFeatMethod{::F_REGANG_LINKS}
+ *
+ * If they do, update the port list data to indicate that this should be done.
+ * @note  no actual hardware state is changed in this routine.
+ *
+ * @param[in,out] State          Our global state
+ */
+VOID
+RegangLinks (
+  IN OUT   STATE_DATA *State
+  )
+{
+  FINAL_LINK_STATE FinalLinkState;
+  UINT8 i;
+  UINT8 j;
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    // Data validation
+    ASSERT ((*State->PortList)[i].Type < 2 && (*State->PortList)[i].Link < State->Nb->MaxLinks);
+    ASSERT ((*State->PortList)[i + 1].Type < 2 && (*State->PortList)[i + 1].Link < State->Nb->MaxLinks);
+
+    // Regang is false unless we pass all conditions below
+    (*State->PortList)[i].SelRegang = FALSE;
+    (*State->PortList)[i + 1].SelRegang = FALSE;
+
+    // Only process cpu to cpu Links
+    if ( ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) ||
+         ((*State->PortList)[i + 1].Type != PORTLIST_TYPE_CPU)) {
+      continue;
+    }
+
+    for (j = i + 2; j < State->TotalLinks*2; j += 2) {
+      // Only process cpu to cpu Links
+      if ( ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) ||
+           ((*State->PortList)[j + 1].Type != PORTLIST_TYPE_CPU) ) {
+        continue;
+      }
+
+      // Links must be from the same source
+      if ((*State->PortList)[i].NodeID != (*State->PortList)[j].NodeID) {
+        continue;
+      }
+
+      // Link must be to the same target
+      if ((*State->PortList)[i + 1].NodeID != (*State->PortList)[j + 1].NodeID) {
+        continue;
+      }
+
+      // Ensure same source base port
+      if (((*State->PortList)[i].Link & 3) != ((*State->PortList)[j].Link & 3)) {
+        continue;
+      }
+
+      // Ensure same destination base port
+      if (((*State->PortList)[i + 1].Link & 3) != ((*State->PortList)[j + 1].Link & 3)) {
+        continue;
+      }
+
+      // Ensure subLink0 routes to subLink0
+      if (((*State->PortList)[i].Link & 4) != ((*State->PortList)[i + 1].Link & 4)) {
+        continue;
+      }
+
+      // (therefore subLink1 routes to subLink1)
+      ASSERT (((*State->PortList)[j].Link & 4) == ((*State->PortList)[j + 1].Link & 4));
+
+      FinalLinkState = State->HtInterface->GetSkipRegang ((*State->PortList)[i].NodeID,
+                                         (*State->PortList)[i].Link & 0x03,
+                                         (*State->PortList)[i + 1].NodeID,
+                                         (*State->PortList)[i + 1].Link & 0x03,
+                                         State);
+      if (FinalLinkState == MATCHED) {
+        continue;
+      } else if (FinalLinkState == POWERED_OFF) {
+        // StopLink will be done on the sublink 1, thus OR in 4 to the link to ensure it.
+        State->Nb->StopLink ((*State->PortList)[i].NodeID, ((*State->PortList)[i].Link | 4), State, State->Nb);
+        State->Nb->StopLink ((*State->PortList)[i + 1].NodeID, ((*State->PortList)[i + 1].Link | 4), State, State->Nb);
+      }
+
+      //
+      // Create a ganged portlist entry for the two regang-able subLinks.
+      //
+      // All info will be that of subLink zero.
+      // (If Link discovery order was other than ascending, fix the .Pointer field too.)
+      //
+      //
+      if (((*State->PortList)[i].Link & 4) != 0) {
+        (*State->PortList)[i].Pointer = (*State->PortList)[j].Pointer;
+        (*State->PortList)[i + 1].Pointer = (*State->PortList)[j + 1].Pointer;
+      }
+      (*State->PortList)[i].Link &= 0x03;                       // Force to point to subLink0
+      (*State->PortList)[i + 1].Link &= 0x03;
+      // If powered off, sublink 1 is removed but the link is still 8 bits.
+      if (FinalLinkState != POWERED_OFF) {
+        (*State->PortList)[i].SelRegang = TRUE;                   // Enable Link reganging
+        (*State->PortList)[i + 1].SelRegang = TRUE;
+        (*State->PortList)[i].PrvWidthOutCap = HT_WIDTH_16_BITS;
+        (*State->PortList)[i + 1].PrvWidthOutCap = HT_WIDTH_16_BITS;
+        (*State->PortList)[i].PrvWidthInCap = HT_WIDTH_16_BITS;
+        (*State->PortList)[i + 1].PrvWidthInCap = HT_WIDTH_16_BITS;
+      }
+
+      // Delete PortList[j, j + 1], slow but easy to debug implementation
+      State->TotalLinks--;
+      LibAmdMemCopy (&((*State->PortList)[j]),
+                     &((*State->PortList)[j + 2]),
+                     sizeof (PORT_DESCRIPTOR)*(State->TotalLinks* 2 - j),
+                     State->ConfigHandle);
+      LibAmdMemFill (&((*State->PortList)[State->TotalLinks * 2]), INVALID_LINK, (sizeof (PORT_DESCRIPTOR) * 2), State->ConfigHandle);
+
+      break; // Exit loop, advance to PortList[i + 2]
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
new file mode 100755
index 0000000000..48ba35b121
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * Link Reganging Interface.
+ *
+ * Contains interface to the Reganging feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_GANGING_H_
+#define _HT_FEAT_GANGING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ */
+VOID
+RegangLinks (
+  IN OUT   STATE_DATA *State
+  );
+
+#endif  /* _HT_FEAT_GANGING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
new file mode 100755
index 0000000000..24fd5cc9a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
@@ -0,0 +1,313 @@
+/**
+ * @file
+ *
+ * Non-Coherent Discovery Routines.
+ *
+ * Contains routines for enumerating and initializing non-coherent devices.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htFeatNoncoherent.h"
+#include "htFeatOptimization.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                             Algorithms                              ***
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process a non-coherent Link.
+ *
+ * @HtFeatMethod{::F_PROCESS_LINK}
+ *
+ * Enable a range of bus numbers, and set the device ID for all devices found.  Add
+ * non-coherent devices, links to the system data structure.
+ *
+ * @param[in]     Node          Node on which to process nc init
+ * @param[in]     Link          The non-coherent Link on that Node
+ * @param[in]     IsCompatChain Is this the chain with the southbridge? TRUE if yes.
+ * @param[in,out] State         our global state
+ */
+VOID
+ProcessLink (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 SecBus;
+  UINT8 SubBus;
+  UINT32 CurrentBuid;
+  UINT32 Temp;
+  UINT32 UnitIdCount;
+  PCI_ADDR CurrentPtr;
+  UINT8 Depth;
+  BUID_SWAP_LIST *SwapPtr;
+  UINT8  LastLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < State->Nb->MaxLinks));
+
+  if (!State->HtInterface->GetOverrideBusNumbers (Node, Link, &SecBus, &SubBus, State)) {
+    // Assign Bus numbers
+    if (State->AutoBusCurrent >= State->HtBlock->AutoBusMax) {
+      //  If we run out of Bus Numbers, notify and skip this chain
+      //
+      IDS_ERROR_TRAP;
+      NotifyErrorNcohBusMaxExceed (Node, Link, State->AutoBusCurrent, State);
+      return;
+    }
+
+    if (State->UsedCfgMapEntries >= 4) {
+      // If we have used all the PCI Config maps we can't add another chain.
+      // Notify and if call back is unimplemented or returns, skip this chain.
+      //
+      IDS_ERROR_TRAP;
+      NotifyErrorNcohCfgMapExceed (Node, Link, State);
+      return;
+    }
+
+    SecBus = State->AutoBusCurrent;
+    SubBus = SecBus + State->HtBlock->AutoBusIncrement - 1;
+    State->AutoBusCurrent = State->AutoBusCurrent + State->HtBlock->AutoBusIncrement;
+  }
+
+  State->Nb->SetConfigAddrMap (State->UsedCfgMapEntries, SecBus, SubBus, Node, Link, State, State->Nb);
+  State->UsedCfgMapEntries++;
+
+  if (State->HtInterface->GetManualBuidSwapList (Node, Link, &SwapPtr, State)) {
+    // Manual non-coherent BUID assignment
+    AGESA_TESTPOINT (TpProcHtManualNc, State->ConfigHandle);
+
+
+    if (!IsCompatChain || !State->IsUsingRecoveryHt) {
+      //  If this is the not southbridge chain or Recovery HT was not used
+      // then we need to assign BUIDs here.
+      //
+      Depth = 0;
+      // Assign BUID's per manual override
+      while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
+        CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, SwapPtr->Swaps[Depth].FromId, 0, 0);
+        if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
+          // Set the device's BUID field [20:16] to the current buid
+          CurrentBuid = SwapPtr->Swaps[Depth].ToId;
+          LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
+          Depth++;
+        } else {
+          // All non-coherent devices must have a slave interface capability.
+          ASSERT (FALSE);
+          break;
+        }
+      }
+    }
+
+    // Build chain of devices. Do this even if Recovery HT assign BUIDs for this chain.
+    Depth = 0;
+    while (SwapPtr->FinalIds[Depth] != 0xFF) {
+      ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
+      (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
+      // Note: depth == 0 is true before depth > 0. This makes LastLink variable work.
+      if (Depth == 0) {
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
+      } else {
+        // Fill in the host side port.  Link and base pointer can be deduced from the upstream link's
+        // downstream port.
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
+        (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Pointer;
+      }
+
+      (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
+
+      CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, (SwapPtr->FinalIds[Depth] & 0x3F), 0, 0);
+      if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
+        (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
+      } else {
+        // All non-coherent devices must have a slave interface capability.
+        ASSERT (FALSE);
+        break;
+      }
+
+      // Bit 6 indicates whether orientation override is desired.
+      // Bit 7 indicates the upstream Link if overriding.
+      //
+      // assert catches at least the one known incorrect setting, that a non-zero link
+      // is specified, but override desired is not set.
+      ASSERT (((SwapPtr->FinalIds[Depth] & 0x40) != 0) || ((SwapPtr->FinalIds[Depth] & 0x80) == 0));
+      if ((SwapPtr->FinalIds[Depth] & 0x40) != 0) {
+        // Override the device's orientation
+        LastLink = SwapPtr->FinalIds[Depth] >> 7;
+      } else {
+        // Detect the device's orientation, by reading the Master Host bit [26]
+        LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
+        LastLink = (UINT8)Temp;
+      }
+      (*State->PortList)[(State->TotalLinks * 2) + 1].Link = LastLink;
+
+      Depth++;
+      State->TotalLinks++;
+    }
+  } else {
+    // Automatic non-coherent device detection
+    AGESA_TESTPOINT (TpProcHtAutoNc, State->ConfigHandle);
+    Depth = 0;
+    CurrentBuid = 1;
+    for (; ; ) {
+      CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, 0, 0, 0);
+
+      LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
+      if (Temp == ((UINT32)0xFFFFFFFF)) {
+        // No device found at CurrentPtr
+        break;
+      }
+
+      ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
+
+      (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
+      if (Depth == 0) {
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
+      } else {
+        // Fill in the host side port.  Link and base pointer can be deduced from the upstream link's
+        // downstream port.
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
+        (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Pointer;
+      }
+
+      (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
+
+      if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
+
+        // Get device's unit id count [25:21]
+        LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIdCount, State->ConfigHandle);
+        if (((UnitIdCount + CurrentBuid) > MAX_BUID) || ((SecBus == 0) && ((UnitIdCount + CurrentBuid) > 24))) {
+          // An error handler for the case where we run out of BUID's on a chain
+          NotifyErrorNcohBuidExceed (Node, Link, Depth, (UINT8)CurrentBuid, (UINT8)UnitIdCount, State);
+          IDS_ERROR_TRAP;
+          break;
+        }
+        LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
+
+        CurrentPtr.Address.Device = CurrentBuid;
+        LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
+        if (Temp != CurrentBuid) {
+          // An error handler for this error,
+          // this often occurs in new BIOS ports and it means you need to use a Manual BUID Swap List.
+          NotifyErrorNcohDeviceFailed (Node, Link, Depth, (UINT8)CurrentBuid, State);
+          IDS_ERROR_TRAP;
+          break;
+        }
+
+        LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
+        (*State->PortList)[(State->TotalLinks * 2) + 1].Link = (UINT8)Temp;
+        (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
+
+        Depth++;
+        State->TotalLinks++;
+        CurrentBuid += UnitIdCount;
+      } else {
+        // All non-coherent devices must have a slave interface capability.
+        ASSERT (FALSE);
+        break;
+      }
+    }
+    // Provide information on automatic device results
+    NotifyInfoNcohAutoDepth (Node, Link, (Depth - 1), State);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.h
new file mode 100755
index 0000000000..f19fffd602
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * Non-Coherent Discovery Interface.
+ *
+ * Contains interface to the Non-Coherent Link processing feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_NONCOHERENT_H_
+#define _HT_FEAT_NONCOHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Process a non-coherent Link.
+ *
+ */
+VOID
+ProcessLink (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  );
+
+#endif  /* _HT_FEAT_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
new file mode 100755
index 0000000000..21f033067d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
@@ -0,0 +1,886 @@
+/**
+ * @file
+ *
+ * Link Optimization Routines.
+ *
+ * Contains routines for determining width, frequency, and other
+ * Link features
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htFeatOptimization.h"
+#include "htNotify.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE
+
+extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define PCI_CONFIG_COMMAND_REG04  4
+#define PCI_CONFIG_REVISION_REG08 8
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Given the bits set in the register field, return the width it represents.
+ *
+ * As invalid width values or encodings are rare except during debug, catch those using
+ * ASSERT().  This means theoretically we are returning an incorrect result if that
+ * happens.  The default chosen for the result is arbitrarily 8 bits.  This is likely
+ * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
+ * Hardware often ignores writes of invalid width encodings.
+ *
+ * @note This routine is used for CPUs as well as IO devices, as all comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]     Value The bits for the register
+ *
+ * @return The width
+ */
+UINT8
+STATIC
+ConvertBitsToWidth (
+  IN       UINT8       Value
+  )
+{
+  UINT8 Result;
+
+  Result = 0;
+
+  switch (Value) {
+
+  case  1:
+    Result = 16;
+    break;
+
+  case  0:
+    Result = 8;
+    break;
+
+  case 3:
+    Result = 32;
+    break;
+
+  case  5:
+    Result = 4;
+    break;
+
+  case  4:
+    Result = 2;
+    break;
+
+  default:
+    ASSERT (FALSE);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ *
+ * As invalid width values or encodings are rare except during debug, catch those using
+ * ASSERT().  This means theoretically we are returning an incorrect result if that
+ * happens.  The default chosen for the result is arbitrarily 8 bits.  This is likely
+ * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
+ * Hardware often ignores writes of invalid width encodings.
+ *
+ * @note This routine is used for CPUs as well as IO devices, as all comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]     Value   the width Value
+ *
+ * @return The bits for the register
+ */
+UINT8
+ConvertWidthToBits (
+  IN       UINT8       Value
+  )
+{
+  UINT8 Result;
+
+  Result = 8;
+
+  switch (Value) {
+
+  case 16:
+    Result = 1;
+    break;
+
+  case 8:
+    Result = 0;
+    break;
+
+  case 32:
+    Result = 3;
+    break;
+
+  case 4:
+    Result = 5;
+    break;
+
+  case 2:
+    Result = 4;
+    break;
+
+  default:
+    ASSERT (FALSE);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Access HT Link Control Register.
+ *
+ * @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS}
+ *
+ * Provide a common routine for accessing the HT Link Control registers (84, a4, c4,
+ * e4), to enforce not clearing the HT CRC error bits.  Replaces direct use of
+ * AmdPCIWriteBits().
+ *
+ * @note: This routine is called for CPUs as well as IO Devices! All comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]     Reg      the PCI config address the control register
+ * @param[in]     HiBit    the high bit number
+ * @param[in]     LoBit    the low bit number
+ * @param[in]     Value    the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]     State    Our state, config handle for lib
+ */
+VOID
+SetHtControlRegisterBits (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT32 Temp;
+  UINT32 mask;
+
+  ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0));
+  ASSERT ((HiBit < 8) || (LoBit > 9));
+
+  // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
+  if ((HiBit - LoBit) != 31) {
+    mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1);
+  } else {
+    mask = (UINT32)0xFFFFFFFF;
+  }
+
+  LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+  Temp &= ~(mask << LoBit);
+  Temp |= (*Value & mask) << LoBit;
+  Temp &= (UINT32)HT_CONTROL_CLEAR_CRC;
+  LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set HT Frequency register for IO Devices
+ *
+ * Provide a common routine for accessing the HT Link Frequency registers at offset 8
+ * and 0x10, to enforce not clearing the HT Link error bits.  Replaces direct use of
+ * AmdPCIWriteBits().
+ *
+ * @note This routine is called for IO Devices only!! All comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]    Reg       the PCI config address the control register
+ * @param[in]    Hibit     the high bit number
+ * @param[in]    Lobit     the low bit number
+ * @param[in]    Value     the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]    State     Our state, config handle for lib
+ */
+VOID
+STATIC
+SetHtIoFrequencyRegisterBits (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       Hibit,
+  IN       UINT8       Lobit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT32 Mask;
+  UINT32 Temp;
+
+  ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
+  ASSERT ((Hibit < 12) || (Lobit > 14));
+
+  // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+  if ((Hibit - Lobit) != 31) {
+    Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
+  } else {
+    Mask = (UINT32)0xFFFFFFFF;
+  }
+
+  LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+  Temp &= ~(Mask << Lobit);
+  Temp |= (*Value & Mask) << Lobit;
+  Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
+  LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtFeatMethod{::F_GATHER_LINK_DATA}
+ *
+ * For all discovered Links, populate the port list with the frequency and width
+ * capabilities. Gather support data for:
+ * - Unit ID Clumping
+ *
+ * @param[in]     State our global state, port list
+ */
+VOID
+GatherLinkData (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 i;
+  PCI_ADDR LinkBase;
+  PCI_ADDR Reg;
+  UINT32 Bits;
+  UINT8 Revision;
+
+  // Get the capability base for whatever device type the link port is on
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+    if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+      LinkBase = State->Nb->MakeLinkBase ((*State->PortList)[i].NodeID, (*State->PortList)[i].Link, State->Nb);
+      (*State->PortList)[i].Pointer = LinkBase;
+    } else {
+      LinkBase = (*State->PortList)[i].Pointer;
+      if ((*State->PortList)[i].Link == 1) {
+        LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
+      }
+    }
+
+    // Getting the Width is standard across device types
+    Reg = LinkBase;
+    Reg.Address.Register += HTSLAVE_LINK_CONTROL_0_REG;
+    LibAmdPciReadBits (Reg, 22, 20, &Bits, State->ConfigHandle);
+    (*State->PortList)[i].PrvWidthOutCap = ConvertBitsToWidth ((UINT8)Bits);
+
+    LibAmdPciReadBits (Reg, 18, 16, &Bits, State->ConfigHandle);
+    (*State->PortList)[i].PrvWidthInCap = ConvertBitsToWidth ((UINT8)Bits);
+
+    // Get Frequency and other device type specific features
+    if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+      State->Nb->GatherLinkFeatures (&(*State->PortList)[i], State->HtInterface, State->Nb);
+    } else {
+      Reg = LinkBase;
+      Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
+      LibAmdPciReadBits (Reg, 31, 16, &Bits, State->ConfigHandle);
+      (*State->PortList)[i].PrvFrequencyCap = Bits;
+
+      // Unit ID Clumping Support
+      if (State->IsUsingUnitIdClumping) {
+        if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
+          Reg.Address.Register += HTUNIT_SUPPORT_REG;
+          LibAmdPciReadBits (Reg, 31, 0, &Bits, State->ConfigHandle);
+        } else {
+          // Not there, that's ok, we don't know that it should have one.
+          // Check for Passive support. (Bit 0 won't be set if full support is implemented,
+          // so we can use it to indicate passive support in our portlist struct).
+          Reg = LinkBase;
+          Reg.Address.Register += HTSLAVE_FEATURECAP_REG;
+          Bits = 1;
+          LibAmdPciWriteBits (Reg, 5, 5, &Bits, State->ConfigHandle);
+          LibAmdPciReadBits (Reg, 5, 5, &Bits, State->ConfigHandle);
+        }
+        (*State->PortList)[i].ClumpingSupport = Bits;
+      } else {
+        (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
+      }
+
+      Reg = LinkBase;
+      Reg.Address.Register = PCI_CONFIG_REVISION_REG08;
+      LibAmdPciReadBits ( LinkBase, 7, 0, &Bits, State->ConfigHandle);
+      Revision = (UINT8) Bits;
+
+      LinkBase.Address.Register = 0;
+      LibAmdPciRead (AccessWidth32, LinkBase, &Bits, State->ConfigHandle);
+
+      State->HtInterface->GetDeviceCapOverride ((*State->PortList)[i].NodeID,
+                           (*State->PortList)[i].HostLink,
+                           (*State->PortList)[i].HostDepth,
+                           (*State->PortList)[i].Pointer,
+                           Bits,
+                           Revision,
+                           (*State->PortList)[i].Link,
+                           &((*State->PortList)[i].PrvWidthInCap),
+                           &((*State->PortList)[i].PrvWidthOutCap),
+                           &((*State->PortList)[i].PrvFrequencyCap),
+                           &((*State->PortList)[i].ClumpingSupport),
+                           State);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Optimize Links.
+ *
+ * @HtFeatMethod{::F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY}
+ *
+ * For all Links:
+ * Examine both sides of a Link and determine the optimal frequency and width,
+ * taking into account externally provided limits and enforcing any other limit
+ * or matching rules as applicable except subLink balancing. Update the port
+ * list data with the optimal settings.
+ *
+ * @note no hardware state changes in this routine.
+ *
+ * @param[in,out]    State         Process and update portlist
+ */
+VOID
+SelectOptimalWidthAndFrequency (
+  IN OUT   STATE_DATA   *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 Freq;
+  UINT32 Temp;
+  UINT32 CbPcbFreqLimit;
+  UINT8 CbPcbABDownstreamWidth;
+  UINT8 CbPcbBAUpstreamWidth;
+
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    CbPcbFreqLimit = HT_FREQUENCY_NO_LIMIT;
+    CbPcbABDownstreamWidth = HT_WIDTH_16_BITS;
+    CbPcbBAUpstreamWidth = HT_WIDTH_16_BITS;
+
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+      State->HtInterface->GetCpu2CpuPcbLimits ((*State->PortList)[i].NodeID,
+                           (*State->PortList)[i].Link,
+                           (*State->PortList)[i + 1].NodeID,
+                           (*State->PortList)[i + 1].Link,
+                           &CbPcbABDownstreamWidth,
+                           &CbPcbBAUpstreamWidth,
+                           &CbPcbFreqLimit,
+                           State
+        );
+    } else {
+      State->HtInterface->GetIoPcbLimits ((*State->PortList)[i + 1].NodeID,
+                      (*State->PortList)[i + 1].HostLink,
+                      (*State->PortList)[i + 1].HostDepth,
+                      &CbPcbABDownstreamWidth,
+                      &CbPcbBAUpstreamWidth,
+                      &CbPcbFreqLimit,
+                      State
+        );
+    }
+
+    Temp = (*State->PortList)[i].PrvFrequencyCap;
+    Temp &= (*State->PortList)[i + 1].PrvFrequencyCap;
+    Temp &= CbPcbFreqLimit;
+    (*State->PortList)[i].CompositeFrequencyCap = (UINT32)Temp;
+    (*State->PortList)[i + 1].CompositeFrequencyCap = (UINT32)Temp;
+
+    ASSERT (Temp != 0);
+    Freq = LibAmdBitScanReverse (Temp);
+    (*State->PortList)[i].SelFrequency = Freq;
+    (*State->PortList)[i + 1].SelFrequency = Freq;
+
+    Temp = (*State->PortList)[i].PrvWidthOutCap;
+    if ((*State->PortList)[i + 1].PrvWidthInCap < Temp) {
+      Temp = (*State->PortList)[i + 1].PrvWidthInCap;
+    }
+    if (CbPcbABDownstreamWidth < Temp) {
+      Temp = CbPcbABDownstreamWidth;
+    }
+    (*State->PortList)[i].SelWidthOut = (UINT8)Temp;
+    (*State->PortList)[i + 1].SelWidthIn = (UINT8)Temp;
+
+    Temp = (*State->PortList)[i].PrvWidthInCap;
+    if ((*State->PortList)[i + 1].PrvWidthOutCap < Temp) {
+      Temp = (*State->PortList)[i + 1].PrvWidthOutCap;
+    }
+    if (CbPcbBAUpstreamWidth < Temp) {
+      Temp = CbPcbBAUpstreamWidth;
+    }
+    (*State->PortList)[i].SelWidthIn = (UINT8)Temp;
+    (*State->PortList)[i + 1].SelWidthOut = (UINT8)Temp;
+  }
+  // Calculate unit id clumping
+  //
+  // Find the root of each IO Chain, process the chain for clumping support.
+  // The root is always the first link of the chain in the port list.
+  // Clumping is not device link specific, so we can just look at the upstream ports (j+1). Use ASSERTs to sanity
+  // check the downstream ports (j).  If any device on the chain does not support clumping, the entire chain will be
+  // disabled for clumping.
+  // After analyzing the clumping support on the chain the CPU's portlist has the enable mask.  Update all the
+  // IO Devices on the chain with the enable mask.  If any device's only have passive support, that is already enabled.
+  //
+  if (State->IsUsingUnitIdClumping) {
+    for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+      if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_IO)) {
+        (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
+        if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
+          (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[i + 1].ClumpingSupport;
+          for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
+            if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
+              if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
+                  ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
+                ASSERT (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
+                        ((*State->PortList)[i].Link == (*State->PortList)[j].HostLink));
+                if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
+                  ASSERT ((((*State->PortList)[j + 1].ClumpingSupport & HT_CLUMPING_PASSIVE) == 0) ||
+                          (((*State->PortList)[j + 1].ClumpingSupport & ~(HT_CLUMPING_PASSIVE)) == 0));
+                  (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[j + 1].ClumpingSupport;
+                } else {
+                  (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
+                  break;
+                }
+              }
+            }
+          }
+          if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
+            (*State->PortList)[i + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
+          }
+          for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
+            if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
+              if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
+                  ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
+                if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
+                  (*State->PortList)[j + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
+                  // The downstream isn't really passive, just mark it so in order to write the device only once.
+                  (*State->PortList)[j].ClumpingSupport = HT_CLUMPING_PASSIVE;
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtFeatMethod{::F_SET_LINK_DATA}
+ *
+ * @param[in]     State   our global state, port list
+ */
+VOID
+SetLinkData (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 i;
+  PCI_ADDR LinkBase;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  UINT32 Widthin;
+  UINT32 Widthout;
+  UINT32 Bits;
+  PCI_ADDR CurrentPtr;
+  HTIDS_PORT_OVERRIDE_LIST PortOverrides;
+
+  PortOverrides = NULL;
+
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+
+    ASSERT ((*State->PortList)[i & 0xFE].SelWidthOut == (*State->PortList)[ (i & 0xFE) + 1].SelWidthIn);
+    ASSERT ((*State->PortList)[i & 0xFE].SelWidthIn == (*State->PortList)[ (i & 0xFE) + 1].SelWidthOut);
+    ASSERT ((*State->PortList)[i & 0xFE].SelFrequency == (*State->PortList)[ (i & 0xFE) + 1].SelFrequency);
+
+    if ((*State->PortList)[i].SelRegang) {
+      ASSERT ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU);
+      ASSERT ((*State->PortList)[i].Link < 4);
+      State->Nb->SetLinkRegang (
+        (*State->PortList)[i].NodeID,
+        (*State->PortList)[i].Link,
+        State->Nb
+        );
+    }
+
+    //
+    // IDS port override for CPUs and IO Devices
+    //
+    pf_HtIdsGetPortOverride ((BOOLEAN) ((i & 1) == 0), &(*State->PortList)[i], &(*State->PortList)[i + 1], &PortOverrides, State);
+
+    LinkBase = (*State->PortList)[i].Pointer;
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[i].Link == 1)) {
+      LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
+    }
+
+    // HT CRC Feature, set if configured.  The default is not to set it, because with some chipsets it
+    // will lock up if done here.
+    if (State->IsSetHtCrcFlood) {
+      Temp = 1;
+      Reg = LinkBase;
+      Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+      State->HtFeatures->SetHtControlRegisterBits (Reg, 1, 1, &Temp, State);
+      if ((*State->PortList)[i].Type == PORTLIST_TYPE_IO) {
+        // IO Devices also need to have SERR enabled.
+        Reg = LinkBase;
+        Reg.Address.Register = PCI_CONFIG_COMMAND_REG04;
+        LibAmdPciWriteBits (Reg, 8, 8, &Temp, State->ConfigHandle);
+      }
+    }
+
+    // Some IO devices don't work properly when setting widths, so write them in a single operation,
+    // rather than individually.
+    //
+    Widthout = ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
+    ASSERT (Widthout == 1 || Widthout == 0 || Widthout == 5 || Widthout == 4);
+    Widthin = ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
+    ASSERT (Widthin == 1 || Widthin == 0 || Widthin == 5 || Widthin == 4);
+
+    Temp = (Widthin & 7) | ((Widthout & 7) << 4);
+    Reg = LinkBase;
+    Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+    State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
+
+    Temp = (*State->PortList)[i].SelFrequency;
+    if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+      State->Nb->SetLinkFrequency (
+        (*State->PortList)[i].NodeID,
+        (*State->PortList)[i].Link,
+        (UINT8)Temp,
+        State->Nb
+        );
+      printk(BIOS_DEBUG, "Node:0x%02x Link:0x%02x, HT frequency = 0x%02x\n",
+		      (*State->PortList)[i].NodeID,
+		      (*State->PortList)[i].Link,
+		      (UINT8)Temp);
+    } else {
+      ASSERT (Temp <= HT_FREQUENCY_2600M);
+      // Write the frequency setting
+      Reg = LinkBase;
+      Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
+      SetHtIoFrequencyRegisterBits (Reg, 11, 8, &Temp, State);
+
+      // Handle additional HT3 frequency requirements, if needed,
+      // or clear them if switching down to ht1 on a warm reset.
+      // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
+      //
+      // Even though we assert if debugging, we need to check that the capability was
+      // found always, since this is an unknown hardware device, also we are taking
+      // unqualified frequency from the external interface (could be trying to do ht3
+      // on an ht1 IO device).
+      //
+
+      if (Temp > HT_FREQUENCY_1000M) {
+        // Enabling features if gen 3
+        Bits = 1;
+      } else {
+        // Disabling features if gen 1
+        Bits = 0;
+      }
+
+      // Retry Enable
+      if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_RETRY_CAPABILITY, &CurrentPtr, State)) {
+        ASSERT ((*State->PortList)[i].Link < 2);
+        CurrentPtr.Address.Register += HTRETRY_CONTROL_REG;
+        LibAmdPciWriteBits (CurrentPtr,
+                            ((*State->PortList)[i].Link * 16),
+                            ((*State->PortList)[i].Link * 16),
+                            &Bits,
+                            State->ConfigHandle);
+      } else {
+        //  If we are turning it off, that may mean the device was only ht1 capable,
+        // so don't complain that we can't do it.
+        //
+        if (Bits != 0) {
+          NotifyWarningOptRequiredCapRetry ((*State->PortList)[i].NodeID,
+                                            (*State->PortList)[i].HostLink,
+                                            (*State->PortList)[i].HostDepth,
+                                            State);
+        }
+      }
+
+      // Scrambling enable
+      if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_GEN3_CAPABILITY, &CurrentPtr, State)) {
+        ASSERT ((*State->PortList)[i].Link < 2);
+        CurrentPtr.Address.Register = CurrentPtr.Address.Register +
+          HTGEN3_LINK_TRAINING_0_REG +
+          ((*State->PortList)[i].Link * HTGEN3_LINK01_OFFSET);
+        LibAmdPciWriteBits (CurrentPtr, 3, 3, &Bits, State->ConfigHandle);
+      } else {
+        //  If we are turning it off, that may mean the device was only ht1 capable,
+        // so don't complain that we can't do it.
+        //
+        if (Bits != 0) {
+          NotifyWarningOptRequiredCapGen3 ((*State->PortList)[i].NodeID,
+                                           (*State->PortList)[i].HostLink,
+                                           (*State->PortList)[i].HostDepth,
+                                           State);
+        }
+      }
+    }
+    // Enable Unit ID Clumping if supported.
+    if (State->IsUsingUnitIdClumping) {
+      if (((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_PASSIVE) &&
+          ((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_DISABLE)) {
+        Bits = (*State->PortList)[i].ClumpingSupport;
+        if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+          State->Nb->SetLinkUnitIdClumping (
+            (*State->PortList)[i].NodeID,
+            (*State->PortList)[i].Link,
+            (*State->PortList)[i].ClumpingSupport,
+            State->Nb
+            );
+        } else {
+          if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
+            Reg.Address.Register += HTUNIT_ENABLE_REG;
+            LibAmdPciWriteBits (Reg, 31, 0, &Bits, State->ConfigHandle);
+          } else {
+            // If we found one when gathering support, we have to find one now.
+            ASSERT (FALSE);
+          }
+        }
+      }
+    }
+  }
+}
+
+/*------------------------------------------------------------------------------------------*/
+/**
+ * Find a specific HT capability type.
+ *
+ * Search all the PCI Config space capabilities on any type of device for an
+ * HT capability of the specific subtype.
+ *
+ * @param[in]  DevicePointer     A PCI Config address somewhere in the device config space
+ * @param[in]  CapSubType        The HT capability subtype to find
+ * @param[out] CapabilityBase    The Config space base address of the capability, if found.
+ * @param[in]  State             Our State
+ *
+ * @retval TRUE     the capability was found
+ * @retval FALSE    the capability was not found
+ */
+BOOLEAN
+DoesDeviceHaveHtSubtypeCap (
+  IN       PCI_ADDR         DevicePointer,
+  IN       UINT8            CapSubType,
+     OUT   PCI_ADDR         *CapabilityBase,
+  IN       STATE_DATA       *State
+  )
+{
+  BOOLEAN IsFound;
+  BOOLEAN IsDone;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  UINT32 RegSubType;
+  UINT32 RegSubTypeMask;
+
+  // Set the PCI Config Space base and the match value.
+  IsFound = FALSE;
+  IsDone = FALSE;
+  Reg = DevicePointer;
+  Reg.Address.Register = 0;
+  if (CapSubType < (HT_HOST_CAPABILITY + 1)) {
+    // HT Interface sub type
+    RegSubType = ((UINT32) (CapSubType << 29) | (UINT32)8);
+    RegSubTypeMask = HT_INTERFACE_CAP_SUBTYPE_MASK;
+  } else {
+    // Other HT capability subtype
+    RegSubType = ((UINT32) (CapSubType << 27) | (UINT32)8);
+    RegSubTypeMask = HT_CAP_SUBTYPE_MASK;
+  }
+  (*CapabilityBase).AddressValue = (UINT32)ILLEGAL_SBDFO;
+
+  // Find it
+  do {
+    LibAmdPciFindNextCap (&Reg, State->ConfigHandle);
+    if (Reg.AddressValue != (UINT32)ILLEGAL_SBDFO) {
+      LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+      // HyperTransport and subtype capability ?
+      if ((Temp & RegSubTypeMask) == RegSubType) {
+        *CapabilityBase = Reg;
+        IsFound = TRUE;
+      }
+      // Some other capability, keep looking
+    } else {
+      //  Not there
+      IsDone = TRUE;
+    }
+  } while (!IsFound && !IsDone);
+
+  return IsFound;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ * @HtFeatMethod{::F_SET_LINK_DATA}
+ *
+ * Effectively, this means HT3 on some links cannot be mixed with HT1 on others.
+ * Scan the CPU to CPU links for this condition and limit those frequencies to HT1
+ * if it is detected.
+ * (Non-coherent links are independent.)
+ *
+ * @param[in,out]   State       global state, port frequency settings.
+ *
+ * @retval          TRUE        Fixup occurred, all coherent links HT1
+ * @retval          FALSE       No changes
+ */
+BOOLEAN
+IsCoherentRetryFixup (
+  IN       STATE_DATA       *State
+  )
+{
+  UINT8 Freq;
+  UINT8 i;
+  UINT8 DetectedFrequencyState;
+  BOOLEAN IsMixed;
+  UINT32 Temp;
+
+  //
+  // detectedFrequencyState:
+  //   0 - initial state
+  //   1 - HT1 Frequencies detected
+  //   2 - HT3 Frequencies detected
+  //
+  IsMixed = FALSE;
+  DetectedFrequencyState = 0;
+
+  // Scan coherent links for a mix of HT3 / HT1
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+      // At this point, Frequency of port [i+1] must equal [i], so just check one of them.
+      switch (DetectedFrequencyState) {
+      case 0:
+        // Set current state to indicate what link frequency we found first
+        if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
+          // HT3 frequencies
+          DetectedFrequencyState = 2;
+        } else {
+          // HT1 frequencies
+          DetectedFrequencyState = 1;
+        }
+        break;
+      case 1:
+        // If HT1 frequency detected, fail any HT3 frequency
+        if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
+          IsMixed = TRUE;
+        }
+        break;
+      case 2:
+        // If HT3 frequency detected, fail any HT1 frequency
+        if ((*State->PortList)[i].SelFrequency <= HT_FREQUENCY_1000M) {
+          IsMixed = TRUE;
+        }
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+      if (IsMixed) {
+        // Don't need to keep checking after we find a mix.
+        break;
+      }
+    }
+  }
+
+  if (IsMixed) {
+    for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+      if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+        // Limit coherent links to HT 1 frequencies.
+        Temp = (*State->PortList)[i].CompositeFrequencyCap & (*State->PortList)[i + 1].CompositeFrequencyCap;
+        Temp &= HT_FREQUENCY_LIMIT_HT1_ONLY;
+        ASSERT (Temp != 0);
+        (*State->PortList)[i].CompositeFrequencyCap = Temp;
+        (*State->PortList)[i + 1].CompositeFrequencyCap = Temp;
+        Freq = LibAmdBitScanReverse (Temp);
+        (*State->PortList)[i].SelFrequency = Freq;
+        (*State->PortList)[i + 1].SelFrequency = Freq;
+      }
+    }
+  }
+  return (IsMixed);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.h
new file mode 100755
index 0000000000..1d1ea70ceb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.h
@@ -0,0 +1,139 @@
+/**
+ * @file
+ *
+ * Link Optimization Feature.
+ *
+ * Contains interface for Link Optimization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_OPTIMIZATION_H_
+#define _HT_FEAT_OPTIMIZATION_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ */
+UINT8
+ConvertWidthToBits (
+  IN       UINT8       Value
+  );
+
+/**
+ * Access HT Link Control Register.
+ *
+ */
+VOID
+SetHtControlRegisterBits (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  );
+
+/**
+ * Get Link features into system data structure.
+ *
+ */
+VOID
+GatherLinkData (
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Optimize Links.
+ *
+ */
+VOID
+SelectOptimalWidthAndFrequency (
+  IN OUT   STATE_DATA   *State
+  );
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ */
+VOID
+SetLinkData (
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ */
+BOOLEAN
+IsCoherentRetryFixup (
+  IN       STATE_DATA       *State
+  );
+
+/**
+ * Find a specific HT capability type.
+ *
+ * @retval FALSE    the capability was not found
+ */
+BOOLEAN
+DoesDeviceHaveHtSubtypeCap (
+  IN       PCI_ADDR         DevicePointer,
+  IN       UINT8            CapSubType,
+     OUT   PCI_ADDR         *CapabilityBase,
+  IN       STATE_DATA       *State
+  );
+
+#endif  /* _HT_FEAT_OPTIMIZATION_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
new file mode 100755
index 0000000000..f76b48a107
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
@@ -0,0 +1,467 @@
+/**
+ * @file
+ *
+ * Routing Routines
+ *
+ * Contains routines for isomorphic topology matching,
+ * routing determination, and routing initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htGraph.h"
+#include "htFeatRouting.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATROUTING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct {
+  UINT8   **CurrentPosition;
+  BOOLEAN IsCustomList;
+} TOPOLOGY_CONTEXT;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***          ISOMORPHISM BASED ROUTING TABLE GENERATION CODE            ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the Link on source Node which connects to target Node
+ *
+ * @param[in] SourceNode   The Node on which to find the Link
+ * @param[in] TargetNode   The Link will connect to this Node
+ * @param[in] State        Our global state
+ *
+ * @return    the Link to target
+ */
+UINT8
+STATIC
+FindLinkToNode (
+  IN       UINT8        SourceNode,
+  IN       UINT8        TargetNode,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT8 TargetLink;
+  UINT8 k;
+
+  // A node linked to itself is not a supported topology graph, this is probably an error in the
+  // topology data.  There is not going to be a portlist match for it.
+  ASSERT (SourceNode != TargetNode);
+  TargetLink = INVALID_LINK;
+  for (k = 0; k < State->TotalLinks*2; k += 2) {
+    if (((*State->PortList)[k].NodeID == SourceNode) && ((*State->PortList)[k + 1].NodeID == TargetNode)) {
+      TargetLink = (*State->PortList)[k].Link;
+      break;
+    } else if (((*State->PortList)[k + 1].NodeID == SourceNode) && ((*State->PortList)[k].NodeID == TargetNode)) {
+      TargetLink = (*State->PortList)[k + 1].Link;
+      break;
+    }
+  }
+  ASSERT (TargetLink != INVALID_LINK);
+
+  return TargetLink;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *      Is graphA isomorphic to graphB?
+ *
+ *  If this function returns true, then Perm will contain the permutation
+ *  required to transform graphB into graphA.
+ *  We also use the degree of each Node, that is the number of connections it has, to
+ *  speed up rejection of non-isomorphic graphs (if there is a Node in graphA with n
+ *  connections, there must be at least one unmatched in graphB with n connections).
+ *
+ * @param[in]     Node     the discovered Node which we are trying to match
+ *                      with a permutation the topology
+ * @param[in,out] State our global state, degree and adjacency matrix,
+ *                      output a permutation if successful
+ * @retval TRUE         the graphs are isomorphic
+ * @retval FALSE        the graphs are not isomorphic
+ *
+ */
+BOOLEAN
+STATIC
+IsIsomorphic (
+  IN       UINT8         Node,
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 j;
+  UINT8 k;
+  UINT8 Nodecnt;
+
+  // We have only been called if Nodecnt == pSelected->size !
+  Nodecnt = State->NodesDiscovered + 1;
+
+  if (Node != Nodecnt) {
+    // Keep building the permutation
+    for (j = 0; j < Nodecnt; j++) {
+      // Make sure the degree matches
+      if (State->Fabric->SysDegree[Node] != State->Fabric->DbDegree[j]) {
+        continue;
+      }
+
+      // Make sure that j hasn't been used yet (ought to use a "used"
+      // array instead, might be faster)
+      for (k = 0; k < Node; k++) {
+        if (State->Fabric->Perm[k] == j) {
+          break;
+        }
+      }
+      if (k != Node) {
+        continue;
+      }
+      State->Fabric->Perm[Node] = j;
+      if (IsIsomorphic (Node + 1, State)) {
+        return TRUE;
+      }
+    }
+    return FALSE;
+  } else {
+    // Test to see if the permutation is isomorphic
+    for (j = 0; j < Nodecnt; j++) {
+      for (k = 0; k < Nodecnt; k++) {
+        if (State->Fabric->SysMatrix[j][k] != State->Fabric->DbMatrix[State->Fabric->Perm[j]][State->Fabric->Perm[k]] ) {
+          return FALSE;
+        }
+      }
+    }
+    return TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Topology List iterator context to the Beginning and provide the first topology.
+ *
+ * Check the interface for a custom topology list.  If one is found, set context to the
+ * first item, and return that item. Otherwise return the first item in the built in list.
+ *
+ * @param[in,out] TopologyContextHandle  Initialize this context to beginning of lists.
+ * @param[out]     NextTopology           The next topology, NULL if end.
+ * @param[in]      State                  Access to interface, handles.
+ *
+ */
+VOID
+STATIC
+BeginTopologies (
+     OUT   TOPOLOGY_CONTEXT  *TopologyContextHandle,
+     OUT   UINT8             **NextTopology,
+  IN       STATE_DATA        *State
+  )
+{
+  if (State->HtBlock->Topolist != NULL) {
+    // Start with a custom list
+    TopologyContextHandle->CurrentPosition = State->HtBlock->Topolist;
+    TopologyContextHandle->IsCustomList = TRUE;
+  } else {
+    // Start with the built in list
+    GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
+    TopologyContextHandle->IsCustomList = FALSE;
+  }
+  *NextTopology = *TopologyContextHandle->CurrentPosition;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Iterate through available topologies.
+ *
+ * Increment to the next list item.  If we are doing a custom list, when we reach the end
+ * switch to the built in list.
+ *
+ * @param[in,out]  TopologyContextHandle  Maintain iterator's context from one call to the next
+ * @param[out]     NextTopology           The next topology, NULL if end.
+ *
+ */
+VOID
+STATIC
+GetNextTopology (
+  IN OUT   TOPOLOGY_CONTEXT  *TopologyContextHandle,
+     OUT   UINT8             **NextTopology
+  )
+{
+  // Not valid to continue calling this routine after reaching the end.
+  ASSERT (TopologyContextHandle->CurrentPosition != NULL);
+
+  if (TopologyContextHandle->IsCustomList) {
+    // We are iterating the custom list from the interface.
+    TopologyContextHandle->CurrentPosition++;
+    if (*TopologyContextHandle->CurrentPosition == NULL) {
+      // We are at the end of the custom list, switch to the built in list.
+      TopologyContextHandle->IsCustomList = FALSE;
+      GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
+    }
+  } else {
+    // We are iterating the built in list
+    TopologyContextHandle->CurrentPosition++;
+    // If we are at the end of the built in list, NextTopology == NULL is the AtEnd.
+  }
+  *NextTopology = *TopologyContextHandle->CurrentPosition;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ * @HtFeatMethod{::F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES}
+ *
+ * A supported topology description matches the discovered fabric if the Nodes can be
+ * matched in such a way that all the Nodes connected in one set are exactly the
+ * Nodes connected in the other (formally, that the graphs are isomorphic).  Which
+ * Links are used is not really important to matching.  If the graphs match, then
+ * there is a permutation of one that translates the Node positions and Linkages to
+ * the other.
+ *
+ * In order to make the isomorphism test efficient, we test for matched number of Nodes
+ * (a 4 Node fabric is not isomorphic to a 2 Node topology), and provide degrees of Nodes
+ * to the isomorphism test.
+ *
+ * The generic routing table solution for any topology is predetermined and represented
+ * as part of the topology.  The permutation we computed tells us how to interpret the
+ * routing onto the fabric we discovered.  We do this working backward from the last
+ * Node discovered to the BSP, writing the routing tables as we go.
+ *
+ * @param[in,out]    State    the discovered fabric, degree matrix, permutation
+ *
+ */
+VOID
+LookupComputeAndLoadRoutingTables (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  TOPOLOGY_CONTEXT   TopologyContextHandle;
+  UINT8 *Selected;
+  UINT8 Size;
+  UINT8 PairCounter;
+  UINT8 ReqTargetLink;
+  UINT8 RspTargetLink;
+  UINT8 ReqTargetNode;
+  UINT8 RspTargetNode;
+  UINT8 AbstractBcTargetNodes;
+  UINT32 BcTargetLinks;
+  UINT8 NodeCounter;
+  UINT8 NodeBeingRouted;
+  UINT8 NodeRoutedTo;
+  UINT8 BroadcastSourceNode;
+
+  Size = State->NodesDiscovered + 1;
+  BeginTopologies (&TopologyContextHandle, &Selected, State);
+  while (Selected != NULL) {
+    if (GraphHowManyNodes (Selected) == Size) {
+      // Build Degree vector and Adjacency Matrix for this entry
+      for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
+        State->Fabric->DbDegree[NodeCounter] = 0;
+        for (PairCounter = 0; PairCounter < Size; PairCounter++) {
+          if (GraphIsAdjacent (Selected, NodeCounter, PairCounter)) {
+            State->Fabric->DbMatrix[NodeCounter][PairCounter] = TRUE;
+            State->Fabric->DbDegree[NodeCounter]++;
+          } else {
+            State->Fabric->DbMatrix[NodeCounter][PairCounter] = FALSE;
+          }
+        }
+      }
+
+      if (IsIsomorphic (0, State)) {
+        break;  // A matching topology was found
+      }
+    }
+    GetNextTopology (&TopologyContextHandle, &Selected);
+  }
+
+  if (Selected != NULL) {
+    // Compute the reverse Permutation
+    for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
+      State->Fabric->ReversePerm[State->Fabric->Perm[NodeCounter]] = NodeCounter;
+    }
+
+    // Start with the last discovered Node, and move towards the BSP
+    for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
+      NodeBeingRouted = ((Size - 1) - NodeCounter);
+      for (NodeRoutedTo = 0; NodeRoutedTo < Size; NodeRoutedTo++) {
+        BcTargetLinks = 0;
+        AbstractBcTargetNodes = GraphGetBc (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
+
+        for (BroadcastSourceNode = 0; BroadcastSourceNode < MAX_NODES; BroadcastSourceNode++) {
+          if ((AbstractBcTargetNodes & ((UINT32)1 << BroadcastSourceNode)) != 0) {
+            // Accepting broadcast from yourself is handled in Nb, so in the topology graph it is an error.
+            ASSERT (NodeBeingRouted != State->Fabric->ReversePerm[BroadcastSourceNode]);
+            BcTargetLinks |= (UINT32)1 << FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[BroadcastSourceNode], State);
+          }
+        }
+
+        if (NodeBeingRouted == NodeRoutedTo) {
+          ReqTargetLink = ROUTE_TO_SELF;
+          RspTargetLink = ROUTE_TO_SELF;
+        } else {
+          ReqTargetNode = GraphGetReq (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
+          ReqTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[ReqTargetNode], State);
+
+          RspTargetNode = GraphGetRsp (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
+          RspTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[RspTargetNode], State);
+        }
+        State->Nb->WriteFullRoutingTable (NodeBeingRouted, NodeRoutedTo, ReqTargetLink, RspTargetLink, BcTargetLinks, State->Nb);
+      }
+      //  Clean up discovery 'footprint' that otherwise remains in the routing table.  It didn't hurt
+      // anything, but might cause confusion during debug and validation.  Do this by setting the
+      // route back to all self routes. Since it's the Node that would be one more than actually installed,
+      // this only applies if less than MaxNodes were found.
+      //
+      if (Size < MAX_NODES) {
+        State->Nb->WriteFullRoutingTable (NodeBeingRouted, Size, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
+      }
+    }
+  } else {
+    //
+    // No Matching Topology was found
+    // Error Strategy:
+    // Auto recovery doesn't seem likely, Force boot as 1P.
+    // For reporting, logging, provide number of Nodes
+    // If not implemented or returns, boot as BSP uniprocessor.
+    //
+    // This can be caused by not supplying an additional topology list, if your board is not one of the built-in topologies.
+    //
+    NotifyErrorCohNoTopology (State->NodesDiscovered, State);
+    IDS_ERROR_TRAP;
+    // Force 1P
+    State->NodesDiscovered = 0;
+    State->TotalLinks = 0;
+    State->Nb->EnableRoutingTables (0, State->Nb);
+    State->HtInterface->CleanMapsAfterError (State);
+  }
+  // Save the topology pointer, or NULL, for other features
+  State->Fabric->MatchedTopology = Selected;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ * @HtFeatMethod{::F_MAKE_HOP_COUNT_TABLE}
+ *
+ * For SLIT, create a node x node matrix with the number of hops.  We can do this
+ * using the topology and the permutation, counting the nodes visited in the routes between
+ * nodes.
+ *
+ * @param[in,out]   State    access topology, permutation, update hop table
+ *
+ */
+VOID
+MakeHopCountTable (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 Origin;
+  UINT8 Target;
+  UINT8 Current;
+  UINT8 Hops;
+  UINT8 Size;
+
+  ASSERT (State->Fabric != NULL);
+  if (State->HopCountTable != NULL) {
+    if (State->Fabric->MatchedTopology != NULL) {
+      Size = GraphHowManyNodes (State->Fabric->MatchedTopology);
+      State->HopCountTable->Size = Size;
+      //
+      // For each node, targeting each node, follow the request path through the database graph,
+      // counting the number of edges.
+      //
+      for (Origin = 0; Origin < Size; Origin++) {
+        for (Target = 0; Target < Size; Target++) {
+          // If both nodes are the same the answer will be zero
+          Hops = 0;
+          // Current starts as the database node corresponding to system node Origin.
+          Current = State->Fabric->Perm[Origin];
+          // Stop if Current is the database node corresponding to system node Target
+          while (Current != State->Fabric->Perm[Target]) {
+            // This is a hop, so count it. Move Current to the next intermediate database node.
+            Hops++;
+            Current = GraphGetReq (State->Fabric->MatchedTopology, Current, State->Fabric->Perm[Target]);
+          }
+          // Put the hop count in the table.
+          State->HopCountTable->Hops[ ((Origin * Size) + Target)] = Hops;
+        }
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
new file mode 100755
index 0000000000..c34dbd404e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * Routing Feature Interface.
+ *
+ * Interfaces to routing and isomorphism routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_ROUTING_H_
+#define _HT_FEAT_ROUTING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ */
+VOID
+LookupComputeAndLoadRoutingTables (
+  IN OUT   STATE_DATA    *State
+  );
+
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ */
+VOID
+MakeHopCountTable (
+  IN OUT   STATE_DATA    *State
+  );
+
+#endif  /* _HT_FEAT_ROUTING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSets.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSets.c
new file mode 100755
index 0000000000..d2b59acd47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSets.c
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * HyperTransport feature sets initializers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "CommonReturns.h"
+#include "htFeatDynamicDiscovery.h"
+#include "htFeatRouting.h"
+#include "htFeatNoncoherent.h"
+#include "htFeatOptimization.h"
+#include "htFeatGanging.h"
+#include "htFeatSublinks.h"
+#include "htFeatTrafficDistribution.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATSETS_FILECODE
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/**
+ * Initializer for the default feature set implementation,
+ * full features.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesDefault =
+{
+  CoherentDiscovery,
+  LookupComputeAndLoadRoutingTables,
+  MakeHopCountTable,
+  ProcessLink,
+  GatherLinkData,
+  SelectOptimalWidthAndFrequency,
+  RegangLinks,
+  SubLinkRatioFixup,
+  IsCoherentRetryFixup,
+  SetLinkData,
+  TrafficDistribution,
+  SetHtControlRegisterBits,
+  ConvertWidthToBits
+};
+
+/**
+ * Initializer for the non-coherent only build option.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesNonCoherentOnly =
+{
+  (PF_COHERENT_DISCOVERY)CommonVoid,
+  (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
+  (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
+  ProcessLink,
+  GatherLinkData,
+  SelectOptimalWidthAndFrequency,
+  (PF_REGANG_LINKS)CommonVoid,
+  (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
+  (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
+  SetLinkData,
+  (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
+  SetHtControlRegisterBits,
+  ConvertWidthToBits
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
new file mode 100755
index 0000000000..5574772a7b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
@@ -0,0 +1,228 @@
+/**
+ * @file
+ *
+ * SubLink management Routines.
+ *
+ * Contains routines for subLink frequency ratios.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htFeatSublinks.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+typedef struct {
+  UINT8 HiFreq;
+  UINT8 LoFreq;
+} VALID_RATIO_ITEM;
+
+STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
+{
+  {HT_FREQUENCY_3200M, HT_FREQUENCY_1600M},   // 3200MHz / 1600MHz 2:1
+  {HT_FREQUENCY_3200M, HT_FREQUENCY_800M},    // 3200MHz / 800MHz  4:1
+  {HT_FREQUENCY_3200M, HT_FREQUENCY_400M},    // 3200MHz / 400MHz  8:1
+  {HT_FREQUENCY_2800M, HT_FREQUENCY_1400M},   // 2800MHz / 1400MHz 2:1
+  {HT_FREQUENCY_2400M, HT_FREQUENCY_1200M},   // 2400MHz / 1200MHz 2:1
+  {HT_FREQUENCY_2400M, HT_FREQUENCY_600M},    // 2400MHz /  600MHz 4:1
+  {HT_FREQUENCY_2400M, HT_FREQUENCY_400M},    // 2400MHz /  400MHz 6:1
+  {HT_FREQUENCY_2000M, HT_FREQUENCY_1000M},   // 2000MHz / 1000MHz 2:1
+  {HT_FREQUENCY_1600M, HT_FREQUENCY_800M},    // 1600MHz /  800MHz 2:1
+  {HT_FREQUENCY_1600M, HT_FREQUENCY_400M},    // 1600MHz /  400MHz 4:1
+  {HT_FREQUENCY_1600M, HT_FREQUENCY_200M},    // 1600MHz /  200Mhz 8:1
+  {HT_FREQUENCY_1200M, HT_FREQUENCY_600M},    // 1200MHz /  600MHz 2:1
+  {HT_FREQUENCY_1200M, HT_FREQUENCY_200M},    // 1200MHz /  200MHz 6:1
+  {HT_FREQUENCY_800M,  HT_FREQUENCY_400M},    // 800MHz /  400MHz 2:1
+  {HT_FREQUENCY_800M,  HT_FREQUENCY_200M},    // 800MHz /  200MHz 4:1
+  {HT_FREQUENCY_400M,  HT_FREQUENCY_200M}     // 400MHz /  200MHz 2:1
+};
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ * @HtFeatMethod{::F_SUBLINK_RATIO_FIXUP}
+ *
+ * Make the adjustment to the port list data so that the frequencies
+ * are at a valid ratio, reducing frequency as needed to achieve
+ * this. (All Links support the minimum 200 MHz frequency.)  Repeat
+ * the above until no adjustments are needed.
+ * @note no hardware state changes in this routine.
+ *
+ * @param[in,out]     State     Link state and port list
+ *
+ */
+VOID
+SubLinkRatioFixup (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 ValidRatioItem;
+  BOOLEAN Changes;
+  BOOLEAN Downgrade;
+  UINT8 HiIndex;
+  UINT8 HiFreq;
+  UINT8 LoFreq;
+
+  UINT32 Temp;
+
+  do {
+    Changes = FALSE;
+    for (i = 0; i < State->TotalLinks*2; i++) {
+      // Must be a CPU Link
+      if ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) {
+        continue;
+      }
+      // Only look for subLink1's
+      if ((*State->PortList)[i].Link < 4) {
+        continue;
+      }
+
+      for (j = 0; j < State->TotalLinks*2; j++) {
+        // Step 1. Find the matching subLink0
+        if ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) {
+          continue;
+        }
+        if ((*State->PortList)[j].NodeID != (*State->PortList)[i].NodeID) {
+          continue;
+        }
+        if ((*State->PortList)[j].Link != ((*State->PortList)[i].Link & 0x03)) {
+          continue;
+        }
+
+        // Step 2. Check for an illegal frequency ratio
+        if ((*State->PortList)[i].SelFrequency >= (*State->PortList)[j].SelFrequency) {
+          HiIndex = i;
+          HiFreq = (*State->PortList)[i].SelFrequency;
+          LoFreq = (*State->PortList)[j].SelFrequency;
+        } else {
+          HiIndex = j;
+          HiFreq = (*State->PortList)[j].SelFrequency;
+          LoFreq = (*State->PortList)[i].SelFrequency;
+        }
+
+        // The frequencies are 1:1, no need to do anything
+        if (HiFreq == LoFreq) {
+          break;
+        }
+
+        Downgrade = TRUE;
+
+        for (ValidRatioItem = 0; ValidRatioItem < (sizeof (ValidRatioList) / sizeof (VALID_RATIO_ITEM)); ValidRatioItem++) {
+          if ((HiFreq == ValidRatioList[ValidRatioItem].HiFreq) &&
+              (LoFreq == ValidRatioList[ValidRatioItem].LoFreq)) {
+            Downgrade = FALSE;
+            break;
+          }
+        }
+
+        // Step 3. Downgrade the higher of the two frequencies, and set Changes to FALSE
+        if (Downgrade) {
+          // Although the problem was with the port specified by hiIndex, we need to
+          // Downgrade both ends of the Link.
+          HiIndex = HiIndex & 0xFE; // Select the 'upstream' (i.e. even) port
+
+          Temp = (*State->PortList)[HiIndex].CompositeFrequencyCap;
+
+          // Remove HiFreq from the list of valid frequencies
+          Temp = Temp & ~((UINT32)1 << HiFreq);
+          ASSERT (Temp != 0);
+          (*State->PortList)[HiIndex].CompositeFrequencyCap = (UINT32)Temp;
+          (*State->PortList)[HiIndex + 1].CompositeFrequencyCap = (UINT32)Temp;
+
+          HiFreq = LibAmdBitScanReverse (Temp);
+
+          (*State->PortList)[HiIndex].SelFrequency = HiFreq;
+          (*State->PortList)[HiIndex + 1].SelFrequency = HiFreq;
+
+          Changes = TRUE;
+        }
+      }
+    }
+  } while (Changes); // Repeat until a valid configuration is reached
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
new file mode 100755
index 0000000000..7a089001ae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * SubLink Interface.
+ *
+ * Contains interface to subLink management feature, for unganged subLinks.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_SUBLINKS_H_
+#define _HT_FEAT_SUBLINKS_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ */
+VOID
+SubLinkRatioFixup (
+  IN OUT   STATE_DATA    *State
+  );
+
+#endif  /* _HT_FEAT_SUBLINKS_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
new file mode 100755
index 0000000000..877c578ba7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -0,0 +1,265 @@
+/**
+ * @file
+ *
+ * Traffic Distribution Routines.
+ *
+ * Contains routines for traffic distribution
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htNotify.h"
+#include "htFeatTrafficDistribution.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ * @HtFeatMethod{::F_TRAFFIC_DISTRIBUTION}
+ *
+ * If there are redundant links between any nodes, traffic distribution allows the
+ * redundant links to be used to improve performance.
+ *
+ * There are two types of traffic distribution. Their use is mutually exclusive, both
+ * can not be used at once.
+ *
+ * Coherent Traffic Distribution is for systems of exactly two nodes only.  All links must
+ * be symmetrical (the same width).  As many links as are connected can be distributed over.
+ *
+ * Link Pair Traffic Distribution works with redundant pairs of links between any two nodes,
+ * it does not matter how many nodes are in the system or how many have a redundant link pair.
+ * A node can have redundant link pairs with more than one other node.
+ * The link pair can be asymmetric, the largest link must be used as the master.  However,
+ * between any pair of nodes there is only one pair of redundant links, and there is a limit
+ * to the total number of pairs each node can have.  So not all links will necessarily be
+ * made usable.
+ *
+ * @param[in]   State   port list data
+ */
+VOID
+TrafficDistribution (
+  IN       STATE_DATA *State
+  )
+{
+  UINT32 Links01;
+  UINT32 Links10;
+  UINT8  LinkCount;
+  UINT8  i;
+  UINT8  LastLink;
+  BOOLEAN IsAsymmetric;
+  UINT8 RedundantLinkCount[MAX_NODES][MAX_NODES];
+  UINT8 MasterLinkPort[MAX_NODES][MAX_NODES];
+  UINT8 AlternateLinkPort[MAX_NODES][MAX_NODES];
+  UINT8 NodeA;
+  UINT8 NodeB;
+  UINT8 PairCount;
+
+  LastLink = 0xFF;
+  IsAsymmetric = FALSE;
+
+  // Traffic Distribution is only used when there are exactly two Nodes in the system
+  // and when all the links are symmetric, same width.
+  if ((State->NodesDiscovered + 1) == 2) {
+    Links01 = 0;
+    Links10 = 0;
+    LinkCount = 0;
+    for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+      if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
+          ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+        if ((LastLink != 0xFF) &&
+            ((*State->PortList)[i].SelWidthOut != (*State->PortList)[LastLink].SelWidthOut) &&
+            ((*State->PortList)[i + 1].SelWidthOut != (*State->PortList)[LastLink + 1].SelWidthOut)) {
+          IsAsymmetric = TRUE;
+          break;
+        }
+        Links01 |= (UINT32)1 << (*State->PortList)[i].Link;
+        Links10 |= (UINT32)1 << (*State->PortList)[i + 1].Link;
+        LinkCount++;
+        LastLink = i;
+      }
+    }
+    ASSERT (LinkCount != 0);
+    //  Don't setup Traffic Distribution if only one Link is being used or there were asymmetric widths
+    if ((LinkCount != 1) && !IsAsymmetric) {
+      State->Nb->WriteTrafficDistribution (Links01, Links10, State->Nb);
+      // If we did Traffic Distribution, we must not do Link Pair, so get out of here.
+      return;
+    }
+  }
+  // Either there are more than two nodes, Asymmetric links, or no redundant links.
+  // See if we can use Link Pair Traffic Distribution
+  LibAmdMemFill (&RedundantLinkCount, 0, (MAX_NODES * MAX_NODES), State->ConfigHandle);
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
+        ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+      NodeA = (*State->PortList)[i].NodeID;
+      NodeB = (*State->PortList)[i + 1].NodeID;
+      if (RedundantLinkCount[NodeA][NodeB] == 0) {
+        // This is the first link connecting two nodes
+        ASSERT (RedundantLinkCount[NodeB][NodeA] == 0);
+        MasterLinkPort[NodeA][NodeB] = i;
+        MasterLinkPort[NodeB][NodeA] = i + 1;
+      } else {
+        // This is a redundant link.  If it is larger than the current master link,
+        // make it the new master link.
+        //
+        if (((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
+            ((*State->PortList)[MasterLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
+          // Make the old master link the alternate, we don't need to check, it is bigger.
+          AlternateLinkPort[NodeA][NodeB] = MasterLinkPort[NodeA][NodeB];
+          AlternateLinkPort[NodeB][NodeA] = MasterLinkPort[NodeB][NodeA];
+          MasterLinkPort[NodeA][NodeB] = i;
+          MasterLinkPort[NodeB][NodeA] = i + 1;
+        } else {
+          // Since the new link isn't bigger than the Master, check if it is bigger than the alternate,
+          // if we have an alternate. If we don't have an alternate yet, make this link the alternate.
+          if (RedundantLinkCount[NodeA][NodeB] == 1) {
+            AlternateLinkPort[NodeA][NodeB] = i;
+            AlternateLinkPort[NodeB][NodeA] = i + 1;
+          } else {
+            if (((*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
+                ((*State->PortList)[AlternateLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
+              // Warning: the alternate link is an unusable redundant link
+              // Then make the new link the alternate link.
+              NotifyWarningOptUnusedLinks (
+                NodeA,
+                (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
+                NodeB,
+                (*State->PortList)[AlternateLinkPort[NodeB][NodeA]].Link,
+                State
+                );
+              ASSERT (RedundantLinkCount[NodeB][NodeA] > 1);
+              AlternateLinkPort[NodeA][NodeB] = i;
+              AlternateLinkPort[NodeB][NodeA] = i + 1;
+            } else {
+              // Warning the current link is an unusable redundant link
+              NotifyWarningOptUnusedLinks (NodeA, (*State->PortList)[i].Link, NodeB, (*State->PortList)[i].Link, State);
+            }
+          }
+        }
+      }
+      RedundantLinkCount[NodeA][NodeB]++;
+      RedundantLinkCount[NodeB][NodeA]++;
+    }
+  }
+  // If we found any, now apply up to 4 per node
+  for (NodeA = 0; NodeA < MAX_NODES; NodeA++) {
+    PairCount = 0;
+    for (NodeB = 0; NodeB < MAX_NODES; NodeB++) {
+      if (RedundantLinkCount[NodeA][NodeB] > 1) {
+        // Then there is a pair of links (at least, but we only care about the pair not the extras)
+        if (PairCount < MAX_LINK_PAIRS) {
+          // Program it
+          if ((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut
+              != (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut) {
+            IsAsymmetric = TRUE;
+          } else {
+            IsAsymmetric = FALSE;
+          }
+          State->Nb->WriteLinkPairDistribution (
+            NodeA,
+            NodeB,
+            PairCount,
+            IsAsymmetric,
+            (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
+            (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
+            State->Nb
+            );
+          PairCount++;
+        } else {
+          // Warning: More link pairs than can be distributed
+          NotifyWarningOptLinkPairExceed (
+            NodeA, NodeB,
+            (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
+            (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
+            State);
+          // Disable the link pair from the other node, the analysis loop made sure there
+          // can only be a single link pair between a pair of nodes.
+          RedundantLinkCount[NodeB][NodeA] = 1;
+        }
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
new file mode 100755
index 0000000000..64beb89bea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * Traffic Distribution Interface.
+ *
+ * Interface to traffic distribution feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
+#define _H_TFEAT_TRAFFIC_DISTRIBUTION_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ */
+VOID
+TrafficDistribution (
+  IN       STATE_DATA *State
+  );
+
+#endif  /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
new file mode 100755
index 0000000000..72d9dfe641
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
@@ -0,0 +1,148 @@
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Implementation.
+ *
+ * Contains AMD AGESA Integrated Debug HT related support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
+
+
+/*-------------------------------------------------------------------------------------*/
+/**
+ * Apply an IDS port override to the desired HT link.
+ *
+ * The IDS port override allows absolute control of a link's frequency and width, such as
+ * would be used for board characterization and test.  The IDS backend code is responsible
+ * for handling the NV items and building them into a port override list.  Here we search
+ * that list for any overrides which apply, and update the data used by the HT feature code.
+ *
+ * @param[in]      IsSourcePort         Since we handle both ports on a match, only do that if TRUE.
+ * @param[in,out]  Port0                The PORTLIST item for the first endpoint of a link.
+ * @param[in,out]  Port1                The PORTLIST item for the second endpoint of a link.
+ * @param[in,out]  PortOverrideList     IN: A pointer to the port override list or NULL,
+ *                                      OUT: A pointer to the port override list.
+ * @param[in]      State                access to ht interface and nb support methods.
+ *
+ */
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  )
+{
+  LOCATE_HEAP_PTR LocHeapParams;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+  HTIDS_PORT_OVERRIDE_LIST   p;
+
+  if (IsSourcePort) {
+    ASSERT (PortOverrideList != NULL);
+    // The caller can cache the override list by providing the pointer (to the heap buffer).
+    // If the pointer to the port override list is null, then check if it is on the heap,
+    // and update the caller's pointer so it is cached.
+    // If the buffer is not in heap, call the IDS backend to get the NV data (which is likely also
+    // in heap).
+    if (*PortOverrideList == NULL) {
+      // locate the table in heap
+      LocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
+      if (HeapLocateBuffer (&LocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+        *PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST)LocHeapParams.BufferPtr;
+      } else {
+        // Ask IDS backend code for the list
+        IDS_OPTION_HOOK (IDS_HT_CONTROL, PortOverrideList, State->ConfigHandle);
+      }
+    }
+    ASSERT (*PortOverrideList != NULL);
+
+    // Search the port override list to see if there is an override that applies to this link.
+    // The match criteria are if either endpoint of the current port list item matches
+    // port override.
+    p = *PortOverrideList;
+    SocketA = State->HtInterface->GetSocketFromMap (Port0->NodeID, State);
+    PackageLinkA = State->Nb->GetPackageLink (Port0->NodeID, Port0->Link, State->Nb);
+    SocketB = State->HtInterface->GetSocketFromMap (Port1->NodeID, State);
+    PackageLinkB = State->Nb->GetPackageLink (Port1->NodeID, Port1->Link, State->Nb);
+
+    while ((p != NULL) && (p->Socket != HT_LIST_TERMINAL)) {
+      if ((((p->Socket == SocketA) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLinkA) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA))))) ||
+          (((p->Socket == SocketB) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLinkB) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB)))))) {
+        // Found a match, update width and frequency of both endpoints.
+        if (p->WidthIn != HT_LIST_TERMINAL) {
+          Port0->SelWidthIn = p->WidthIn;
+          Port1->SelWidthOut = p->WidthIn;
+        }
+        if (p->WidthOut != HT_LIST_TERMINAL) {
+          Port0->SelWidthOut = p->WidthOut;
+          Port1->SelWidthIn = p->WidthOut;
+        }
+        if (p->Frequency != HT_LIST_TERMINAL) {
+          Port0->SelFrequency = p->Frequency;
+          Port1->SelFrequency = p->Frequency;
+        }
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
new file mode 100755
index 0000000000..18cee2db47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
@@ -0,0 +1,488 @@
+/**
+ * @file
+ *
+ * Coherent Feature Northbridge routines.
+ *
+ * Provide access to hardware for routing, coherent discovery.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbCoherent.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Establish a Temporary route from one Node to another.
+ *
+ * @HtNbMethod{::F_WRITE_ROUTING_TABLE}
+ *
+ * This routine will modify the routing tables on the
+ * SourceNode to cause it to route both request and response traffic to the
+ * targetNode through the specified Link.
+ *
+ * @note: This routine is to be used for early discovery and initialization.  The
+ * final routing tables must be loaded some other way because this
+ * routine does not address the issue of probes, or independent request
+ * response paths.
+ *
+ * @param[in]     Node     the Node that will have it's routing tables modified.
+ * @param[in]     Target   For routing to Node target
+ * @param[in]     Link     Link from Node to target
+ * @param[in]     Nb       this northbridge
+ */
+VOID
+WriteRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES) && (Link < Nb->MaxLinks));
+  Temp = (Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (Link + 1);
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_ROUTE0_0X40 + (Target * 4));
+  LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ * @HtNbMethod{::F_WRITE_NODEID}
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     NodeID the new value for NodeID
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+WriteNodeID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = NodeID;
+  ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_NODE_ID_0X60);
+  LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read the Default Link
+ *
+ * @HtNbMethod{::F_READ_DEFAULT_LINK}
+ *
+ * Read the DefLnk (the source Link of the current packet) from Node. Since this code
+ * is running on the BSP, this should be the Link pointing back towards the BSP.
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     Nb     this northbridge
+ *
+ * @return The HyperTransport Link where the request to
+ *         read the default Link came from.
+ */
+UINT8
+ReadDefaultLink (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 DefaultLink;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  DefaultLink = 0;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_INIT_CONTROL_0X6C);
+
+  ASSERT ((Node < MAX_NODES));
+  LibAmdPciReadBits (Reg, 3, 2, &DefaultLink, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
+  DefaultLink |= (Temp << 2);
+  return (UINT8)DefaultLink;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Turns routing tables on for a given Node
+ *
+ * @HtNbMethod{::F_ENABLE_ROUTING_TABLES}
+ *
+ * @param[in] Node the Node that will have it's routing tables enabled
+ * @param[in] Nb   this northbridge
+ */
+VOID
+EnableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = 0;
+  ASSERT ((Node < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_INIT_CONTROL_0X6C);
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Turns routing tables off for a given Node
+ *
+ * @HtNbMethod{::F_DISABLE_ROUTING_TABLES}
+ *
+ * @param[in] Node the Node that will have it's routing tables disabled
+ * @param[in] Nb   this northbridge
+ */
+VOID
+DisableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = 1;
+  ASSERT ((Node < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_INIT_CONTROL_0X6C);
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+ * @HtNbMethod{::F_VERIFY_LINK_IS_COHERENT}
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link has the following status
+ *                        -  LinkCon=1,           Link is connected
+ *                        -  InitComplete=1,      Link initialization is complete
+ *                        -  NC=0,                Link is coherent
+ *                        -  UniP-cLDT=0,         Link is not Uniprocessor cLDT
+ *                        -  LinkConPend=0        Link connection is not pending
+ *  @retval       FALSE   The Link has some other status
+*/
+BOOLEAN
+VerifyLinkIsCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 LinkType;
+  PCI_ADDR LinkBase;
+
+  ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
+
+  LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
+
+  //  FN0_98/A4/C4 = LDT Type Register
+  LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
+  LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
+
+  //  Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0
+  return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) ==  HTHOST_TYPE_COHERENT);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ * @HtNbMethod{::F_READ_TOKEN}
+ *
+ * Use the CPU core count as a scratch pad.
+ *
+ * @note The location used to store the token is arbitrary.  The only requirement is
+ * that the location warm resets to zero, and that using it will have no ill-effects
+ * during HyperTransport initialization.
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ *
+ * @return        the Token read from the Node
+ */
+UINT8
+ReadToken (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Use CpuCnt as a scratch register
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_NODE_ID_0X60);
+  LibAmdPciReadBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
+
+  return (UINT8)Temp;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write the token stored in the scratchpad register
+ *
+ * @HtNbMethod{::F_WRITE_TOKEN}
+ *
+ * Use the CPU core count as a scratch pad.
+ *
+ * @note The location used to store the token is arbitrary.  The only requirement is
+ * that the location warm resets to zero, and that using it will have no ill-effects
+ * during HyperTransport initialization.
+ *
+ * @param[in]     Node  the Node that marked with token
+ * @param[in]     Value the token Value
+ * @param[in]     Nb    this northbridge
+ */
+VOID
+WriteToken (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = Value;
+  ASSERT ((Node < MAX_NODES));
+  // Use CpuCnt as a scratch register
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_NODE_ID_0X60);
+  LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Full Routing Table Register initialization
+ *
+ * @HtNbMethod{::F_WRITE_FULL_ROUTING_TABLE}
+ *
+ * Write the routing table entry for Node to target, using the request Link, response
+ * Link, and broadcast Links provided.
+ *
+ * @param[in]     Node            the Node that will be examined
+ * @param[in]     Target          the Target Node for these routes
+ * @param[in]     ReqLink         the Link for requests to Target
+ * @param[in]     RspLink         the Link for responses to Target
+ * @param[in]     BroadcastLinks  the broadcast Links
+ * @param[in]     Nb              this northbridge
+ */
+VOID
+WriteFullRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Value;
+
+  Value = 0;
+  ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES));
+  if (ReqLink == ROUTE_TO_SELF) {
+    Value |= Nb->SelfRouteRequestMask;
+  } else {
+    Value |= Nb->SelfRouteRequestMask << (ReqLink + 1);
+  }
+
+  if (RspLink == ROUTE_TO_SELF) {
+    Value |= Nb->SelfRouteResponseMask;
+  } else {
+    Value |= Nb->SelfRouteResponseMask << (RspLink + 1);
+  }
+
+  // Allow us to accept a Broadcast ourselves, then set broadcasts for routes
+  Value |= (UINT32)1 << Nb->BroadcastSelfBit;
+  Value |= (UINT32)BroadcastLinks << (Nb->BroadcastSelfBit + 1);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_ROUTE0_0X40 + (Target * 4));
+  LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ * @HtNbMethod{::F_IS_ILLEGAL_TYPE_MIX}.
+ *
+ * Currently, that means the family, extended family of the new Node are the
+ * same as the BSP's.
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @retval   TRUE    the new node is not compatible
+ * @retval   FALSE   the new node is compatible
+ */
+BOOLEAN
+IsIllegalTypeMix (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbMethod{::F_HANDLE_SPECIAL_NODE_CASE}.
+ *
+ * Currently, this routine is implemented for all coherent HT families to check
+ * vendor ID of coherent Node. If the vendor ID is 0x1022 then return FALSE,
+ * or return TRUE.
+ *
+ * @param[in] Node  The Node which need to be checked.
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This node received special handling.
+ * @retval    FALSE This node was not handled specially, handle it normally.
+ *
+ */
+BOOLEAN
+HandleSpecialNodeCase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  BOOLEAN Result;
+  PCI_ADDR Reg;
+  UINT32 VendorID;
+
+  Result = TRUE;
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 0,
+                                 0);
+
+  LibAmdPciReadBits (Reg, 15, 0, &VendorID, Nb->ConfigHandle);
+  if (VendorID == 0x1022) {
+    Result = FALSE;
+  }
+
+  return Result;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
new file mode 100755
index 0000000000..43053a8924
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
@@ -0,0 +1,177 @@
+/**
+ * @file
+ *
+ * Coherent Feature Northbridge common routines.
+ *
+ * Provide access to hardware for routing, coherent discovery.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE GENERIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/**
+ * Establish a Temporary route from one Node to another.
+ *
+ */
+VOID
+WriteRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ */
+VOID
+WriteNodeID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Read the Default Link
+ *
+ */
+UINT8
+ReadDefaultLink (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Turns routing tables on for a given Node
+ *
+ */
+VOID
+EnableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Turns routing tables off for a given Node
+ *
+ */
+VOID
+DisableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+*/
+BOOLEAN
+VerifyLinkIsCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ */
+UINT8
+ReadToken (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Write the token stored in the scratchpad register
+ *
+ */
+VOID
+WriteToken (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Full Routing Table Register initialization
+ *
+ */
+VOID
+WriteFullRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ */
+BOOLEAN
+IsIllegalTypeMix (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ */
+BOOLEAN
+HandleSpecialNodeCase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
new file mode 100755
index 0000000000..ba976458e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
@@ -0,0 +1,138 @@
+/**
+ * @file
+ *
+ *  Northbridge generic non-coherent support routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbNonCoherent.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                    Northbridge access routines                      ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the Link to the Southbridge
+ *
+ * @HtNbMethod{::F_READ_SB_LINK}
+ *
+ * @param[in] Nb this northbridge
+ *
+ * @return the Link to the southbridge
+ */
+UINT8
+ReadSouthbridgeLink (
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
+                                 MakePciBusFromNode (0),
+                                 MakePciDeviceFromNode (0),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_UNIT_ID_0X64);
+  LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
+  return (UINT8)Temp;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ * @HtNbMethod{::F_VERIFY_LINK_IS_NON_COHERENT}
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link has the following status
+ *                            - LinkCon=1,        Link is connected
+ *                            - InitComplete=1,   Link initialization is complete
+ *                            - NC=1,             Link is noncoherent
+ *                            - UniP-cLDT=0,      Link is not Uniprocessor cLDT
+ *                            - LinkConPend=0     Link connection is not pending
+ *  @retval       FALSE   The Link has some other status
+ */
+BOOLEAN
+VerifyLinkIsNonCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 LinkType;
+  PCI_ADDR LinkBase;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
+  LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
+
+  // FN0_98/A4/C4 = LDT Type Register
+  LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
+
+  // Verify LinkCon = 1, InitComplete = 1, NC = 1, UniP-cLDT = 0, LinkConPend = 0
+  return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) ==  HTHOST_TYPE_NONCOHERENT);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h
new file mode 100755
index 0000000000..3b161b61af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h
@@ -0,0 +1,61 @@
+/**
+ * @file
+ *
+ *  Northbridge generic non-coherent support routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return the Link to the Southbridge
+ */
+UINT8
+ReadSouthbridgeLink (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ */
+BOOLEAN
+VerifyLinkIsNonCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
new file mode 100755
index 0000000000..344aea7574
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
@@ -0,0 +1,252 @@
+/**
+ * @file
+ *
+ * Link optimization support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbOptimization.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtNbMethod{::F_GATHER_LINK_FEATURES}
+ *
+ * For a specific discovered CPU Link, populate the port list with the frequency
+ * capabilities.  Support for other link oriented capabilities, currently:
+ * - Unit ID Clumping. Set to disabled. This doesn't mean the CPU doesn't support clumping,
+ *   it just means:
+ *   - The CPU doesn't clump its host unit ids, and
+ *   - We don't have to check as carefully in SetLinkData whether the port is an IO host link.
+ *
+ * @param[in,out] ThisPort       The PortList structure entry for this link's port
+ * @param[in]     Interface      Access to non-HT support functions.
+ * @param[in]     Nb             this northbridge
+ */
+VOID
+GatherLinkFeatures (
+  IN OUT   PORT_DESCRIPTOR  *ThisPort,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Frequency;
+  UINT32 ExtendedFrequency;
+
+  Reg = ThisPort->Pointer;
+  Reg.Address.Register += HTHOST_FREQ_REV_REG;
+  LibAmdPciReadBits (Reg, 30, 16, &Frequency, Nb->ConfigHandle);
+  Reg = ThisPort->Pointer;
+  Reg.Address.Register += HTHOST_FREQ_EXTENSION;
+  LibAmdPciReadBits (Reg, 15, 1, &ExtendedFrequency, Nb->ConfigHandle);
+  ThisPort->PrvFrequencyCap = ((Frequency | (ExtendedFrequency << HT_FREQUENCY_2800M)) &
+                               Nb->NorthBridgeFreqMask (ThisPort->NodeID, Interface, Nb));
+  // Check for Internal link restriction not to run at 1000 MHz (but allow lower)
+  if (IsPackageLinkInternal (Nb->GetPackageLink (ThisPort->NodeID, ThisPort->Link, Nb))) {
+    ThisPort->PrvFrequencyCap &= ~(HT_FREQUENCY_LIMIT_1000M & ~HT_FREQUENCY_LIMIT_800M);
+  }
+  ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure for link reganging.
+ *
+ * @HtNbMethod{::F_SET_LINK_REGANG}
+ *
+ * @param[in]     Node   the node on which to regang a link
+ * @param[in]     Link   the sublink 0 of the sublink pair to regang
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+SetLinkRegang (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  Temp = 1;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
+
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure  for Unit Id Clumping.
+ *
+ * @HtNbMethod{::F_SET_LINK_UNITID_CLUMPING}
+ *
+ * This applies to the host root of a non-coherent chain.
+ *
+ * @param[in]     Node              the node on which to enable clumping
+ * @param[in]     Link              the link for which to enable clumping
+ * @param[in]     ClumpingEnables   the unit id clumping enables
+ * @param[in]     Nb                this northbridge
+ */
+VOID
+SetLinkUnitIdClumping (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       UINT32      ClumpingEnables,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+
+  // Host Unit Ids are not clumped.
+  ASSERT ((ClumpingEnables & 0x3) == 0);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_CLUMPING0_0X110 + (4 * Link));
+
+  LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure for link frequency.
+ *
+ * @HtNbMethod{::F_SET_LINK_FREQUENCY}
+ *
+ * Handle extended frequencies.  For HT3 frequencies, ensure Retry and Scrambling are
+ * set. For HT1, clear them.
+ *
+ * @param[in]     Node        the node on which to set frequency for a link
+ * @param[in]     Link        the link to set frequency
+ * @param[in]     Frequency   the frequency to set
+ * @param[in]     Nb          this northbridge
+ */
+VOID
+SetLinkFrequency (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  ASSERT ((Frequency >= HT_FREQUENCY_600M && Frequency <= HT_FREQUENCY_3200M)
+          || (Frequency == HT_FREQUENCY_200M) || (Frequency == HT_FREQUENCY_400M));
+
+  // Handle extended frequencies, 2800 MHz and above.  31 > Frequency > 16 in this case.
+  if (Frequency > HT_FREQUENCY_2600M) {
+    Temp = 1;
+  } else {
+    // Clear it if not extended.
+    Temp = 0;
+  }
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register += HTHOST_FREQ_EXTENSION;
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register += HTHOST_FREQ_REV_REG;
+  Temp = (Frequency & 0x0F);
+  LibAmdPciWriteBits (Reg, 11, 8, &Temp, Nb->ConfigHandle);
+  //  Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
+  if (Frequency > HT_FREQUENCY_1000M) {
+    // Enable  for Gen3 frequencies
+    Temp = 1;
+  } else {
+    // Disable  for Gen1 frequencies
+    Temp = 0;
+  }
+  // HT3 retry mode enable / disable
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_RETRY0_0X130 + (4 * Link));
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+  // and Scrambling enable / disable
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
+  LibAmdPciWriteBits (Reg, 3, 3, &Temp, Nb->ConfigHandle);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.h
new file mode 100755
index 0000000000..eb7d1503ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * Link optimization generic support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Get Link features into system data structure.
+ *
+ */
+VOID
+GatherLinkFeatures (
+  IN OUT   PORT_DESCRIPTOR  *ThisPort,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  );
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ */
+VOID
+SetLinkRegang (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Set the link's Unit Id Clumping enable.
+ *
+ */
+VOID
+SetLinkUnitIdClumping (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       UINT32      ClumpingEnables,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ */
+VOID
+SetLinkFrequency (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
new file mode 100755
index 0000000000..1c2e8af0a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
@@ -0,0 +1,331 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * These routines are needed for support of more than one feature area.
+ * Collect them in this file so build options don't remove them.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbUtilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ * @HtNbMethod{::F_MAKE_LINK_BASE}
+ *
+ * @param[in]     Node    the Node this Link is on
+ * @param[in]     Link    the Link
+ * @param[in]     Nb      this northbridge
+ *
+ * @return  the pci config address
+ */
+PCI_ADDR
+MakeLinkBase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR LinkBase;
+
+  ASSERT (Nb != NULL);
+  if (Link < 4) {
+    LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                        MakePciBusFromNode (Node),
+                                        MakePciDeviceFromNode (Node),
+                                        CPU_HTNB_FUNC_00,
+                                        REG_HT_CAP_BASE_0X80 + Link*HT_HOST_CAP_SIZE);
+  } else {
+    LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                        MakePciBusFromNode (Node),
+                                        MakePciDeviceFromNode (Node),
+                                        CPU_HTNB_FUNC_04,
+                                        REG_HT_CAP_BASE_0X80 + (Link - 4)*HT_HOST_CAP_SIZE);
+  }
+  return LinkBase;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ * @HtNbMethod{::F_READ_TRUE_LINK_FAIL_STATUS}
+ *
+ * Dependency!:  HT_FEATURES::SetHtControlRegisterBits
+ *
+ * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot.
+ *
+ * The table below summarizes correct responses of this routine.
+ * <TABLE>
+ *   <TR><TD> Family </TD> <TD> before </TD> <TD> after </TD> <TD> unconnected </TD> <TD> Notify? </TD> <TD> return </TD></TR>
+ *   <TR><TD>  10    </TD> <TD>   0    </TD> <TD>   0   </TD> <TD>     0       </TD> <TD>   No    </TD> <TD> FALSE  </TD></TR>
+ *   <TR><TD>  10    </TD> <TD>   1    </TD> <TD>   0   </TD> <TD>     0       </TD> <TD>   Yes   </TD> <TD> FALSE  </TD></TR>
+ *   <TR><TD>  10    </TD> <TD>   1    </TD> <TD>   0   </TD> <TD>     3       </TD> <TD>   No    </TD> <TD> TRUE   </TD></TR>
+ * </TABLE>
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Link   the Link on that Node to examine
+ * @param[in]     State  access to call back routine
+ * @param[in]     Nb     this northbridge
+ *
+ * @retval        TRUE   the Link is not connected or has hard error
+ * @retval        FALSE  the Link is connected
+ */
+BOOLEAN
+ReadTrueLinkFailStatus (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32    Before;
+  UINT32    After;
+  UINT32    Unconnected;
+  UINT32    Crc;
+  PCI_ADDR  Reg;
+
+  ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
+
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register +=  HTHOST_LINK_CONTROL_REG;
+
+  // Save the CRC status before doing anything else.
+  // Read, Clear, re-read the error bits in the Link Control Register
+  // (FN0_84/A4/C4[4] = LinkFail bit),
+  // and check the connection status, TransOff and EndOfChain.
+  //
+  LibAmdPciReadBits (Reg, 9, 8, &Crc, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 4, 4, &Before, Nb->ConfigHandle);
+  State->HtFeatures->SetHtControlRegisterBits (Reg, 4, 4, &Before, State);
+  LibAmdPciReadBits (Reg, 4, 4, &After, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 7, 6, &Unconnected, Nb->ConfigHandle);
+
+  if (Before != After) {
+    if (Unconnected == 0) {
+      if (Crc != 0) {
+        // A sync flood occurred due to HT CRC
+        // Pass the Node and Link on which the generic sync flood event occurred.
+        NotifyAlertHwHtCrc (Node, Link, (UINT8)Crc, State);
+      } else {
+        // Some sync flood occurred
+        // Pass the Node and Link on which the generic sync flood event occurred.
+        NotifyAlertHwSyncFlood (Node, Link, State);
+      }
+    }
+  }
+  return (BOOLEAN) ((After != 0) || (Unconnected != 0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ * @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES}
+ *
+ * @param[in]     Node         the Node that will be examined
+ * @param[in]     TotalNodes   the total number of Nodes
+ * @param[in]     TotalCores   the total number of cores
+ * @param[in]     Nb           this northbridge
+ */
+VOID
+SetTotalNodesAndCores (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR NodeIDReg;
+  UINT32 Temp;
+
+  ASSERT ((Node < MAX_NODES) && (TotalNodes <= MAX_NODES));
+  NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                       MakePciBusFromNode (Node),
+                                       MakePciDeviceFromNode (Node),
+                                       CPU_HTNB_FUNC_00,
+                                       REG_NODE_ID_0X60);
+
+  Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0);
+  LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
+  Temp = TotalNodes - 1;
+  LibAmdPciWriteBits (NodeIDReg,  6,  4, &Temp, Nb->ConfigHandle);
+
+  NodeIDReg.Address.Register = REG_HT_EXTENDED_NODE_ID_F0X160;
+
+  Temp = (((TotalCores - 1) & HTREG_EXTNODE_CPUCNT_7_5) >> 5);
+  LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Count (1 based) of Nodes in the system.
+ *
+ * @HtNbMethod{::F_GET_NODE_COUNT}
+ *
+ * This is intended to support AP Core HT init, since the Discovery State data is not
+ * available (State->NodesDiscovered), there needs to be this way to find the number
+ * of Nodes.  The Node count can be read from the BSP.
+ *
+ * @param[in]     Nb           this northbridge
+ *
+ * @return        The number of nodes
+ */
+UINT8
+GetNodeCount (
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR NodeIDReg;
+  UINT32 Temp;
+
+  NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
+                                       MakePciBusFromNode (0),
+                                       MakePciDeviceFromNode (0),
+                                       CPU_HTNB_FUNC_00,
+                                       REG_NODE_ID_0X60);
+  LibAmdPciReadBits (NodeIDReg,  6,  4, &Temp, Nb->ConfigHandle);
+  return ((UINT8) (++Temp));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ * @HtNbMethod{::F_LIMIT_NODES}
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ */
+VOID
+LimitNodes (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  Temp = 1;
+  ASSERT ((Node < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_TRANS_CONTROL_0X68);
+  LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ * @HtNbMethod{::F_GET_PACKAGE_LINK}
+ *
+ * Based on the link to package link mapping from BKDG, look up package link for
+ * the input link on the internal node number corresponding to Node id.
+ *
+ * @param[in]   Node       the node which has this link
+ * @param[in]   Link       the link on that node
+ * @param[in]   Nb         this northbridge
+ *
+ * @return      the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
+ *
+ */
+UINT8
+GetPackageLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT8 ModuleType;
+  UINT8 Module;
+  UINTN PackageLinkMapItem;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
+  PackageLink = HT_LIST_TERMINAL;
+
+  Nb->GetModuleInfo (Node, &ModuleType, &Module, Nb);
+
+  if (ModuleType != 0) {
+    ASSERT (Nb->PackageLinkMap != NULL);
+    // Use table to find this module's package link
+    PackageLinkMapItem = 0;
+    while ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
+      if (((*Nb->PackageLinkMap)[PackageLinkMapItem].Module == Module) &&
+          ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
+        PackageLink = (*Nb->PackageLinkMap)[PackageLinkMapItem].PackageLink;
+        break;
+      }
+      PackageLinkMapItem++;
+    }
+  } else {
+    PackageLink = Link;
+  }
+  return PackageLink;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h
new file mode 100755
index 0000000000..de8ab35758
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h
@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ */
+PCI_ADDR
+MakeLinkBase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ */
+BOOLEAN
+ReadTrueLinkFailStatus (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ */
+VOID
+SetTotalNodesAndCores (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the Count (1 based) of Nodes in the system.
+ *
+ */
+UINT8
+GetNodeCount (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ */
+VOID
+LimitNodes (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ */
+UINT8
+GetPackageLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
new file mode 100755
index 0000000000..2e555dd235
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
@@ -0,0 +1,108 @@
+/**
+ * @file
+ *
+ * HyperTransport features constructor.
+ *
+ * Initialize the set of available features.
+ * This file implements build options using conditional compilation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTFEAT_FILECODE
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/**
+ * A no features Initializer.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesNone =
+{
+  (PF_COHERENT_DISCOVERY)CommonVoid,
+  (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
+  (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
+  (PF_PROCESS_LINK)CommonVoid,
+  (PF_GATHER_LINK_DATA)CommonVoid,
+  (PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY)CommonVoid,
+  (PF_REGANG_LINKS)CommonVoid,
+  (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
+  (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
+  (PF_SET_LINK_DATA)CommonVoid,
+  (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_SET_HT_CONTROL_REGISTER_BITS)CommonVoid,
+  (PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Provide the current Feature set implementation.
+ *
+ * Initialize using the installed initializer.
+ *
+ * @param[in]   HtFeatures      A feature object to initialize
+ * @param[in]   StdHeader       Opaque handle to standard config header
+*/
+VOID
+NewHtFeatures (
+     OUT   HT_FEATURES         *HtFeatures,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) HtFeatures,
+    (VOID *) OptionHtConfiguration.HtOptionInternalFeatures ,
+    (UINT32) (sizeof (HT_FEATURES)),
+    StdHeader
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h
new file mode 100755
index 0000000000..aefdbda303
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h
@@ -0,0 +1,559 @@
+/**
+ * @file
+ *
+ * HT Features.
+ *
+ * This file provides definitions used in common by HT internal modules.  The
+ * data is private and not for external client access.
+ * Definitions include the HT global internal state data structures, and
+ * access to the available HT features from the main HT entry point.
+ *
+ * This file includes the feature constructor and feature support which is not
+ * removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_H_
+#define _HT_FEAT_H_
+
+/**
+ * @page htimplfeat HT Features Implementation Guide
+ *
+ * HT Features provides access to the HT Feature set, in a manner that isolates
+ * calling code from knowledge about the Feature set implementation or which
+ * features are supported in the current build.  In the case of feature sets, this
+ * is mostly used for build options to reduce code size by removing unneeded features.
+ *
+ * @par Adding a Method to HT Features
+ *
+ * To add a new method to the HT Features, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
+ *   </ul>
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtFeatInstances.
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::HT_FEATURES struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an HT Features Instance of the method.
+ *
+ * To implement an instance of a method for a specific feature follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the method typedef.
+ *
+ * - Name the function MethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtFeatMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other Ht feature routines or data as part of the method implementation, the function
+ *   must use HtFeatures->OtherMethod().  Do not directly access other HT feature
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple configurations.
+ *
+ * - Add the instance to the ::HT_FEATURES instances.
+ *
+ * - If a configuration does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking HT Features Methods.
+ *
+ * The first step is carried out only once by the top level HT entry point.
+ * @n @code
+ * HT_FEATURES HtFeatures;
+ *   // Get the current HT Feature Set
+ *   NewHtFeatures (&HtFeatures);
+ *   State->HtFeatures = &HtFeatures;
+ * @endcode
+ *
+ * The following example shows how to invoke a HT Features method.
+ * @n @code
+ *    State->HtFeatures->MethodName ();
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MAX_PLATFORM_LINKS 64
+#define MAX_LINK_PAIRS 4
+
+/* These following are internal definitions */
+#define ROUTE_TO_SELF 0x0F
+#define INVALID_LINK 0xCC     /* Used in port list data structure to mark unused data entries.
+                                 Can also be used for no Link found in a port list search */
+
+/* definitions for working with the port list structure */
+#define PORTLIST_TYPE_CPU 0
+#define PORTLIST_TYPE_IO  1
+
+/*
+ * Hypertransport Capability definitions and macros
+ *
+ */
+
+#define HT_INTERFACE_CAP_SUBTYPE_MASK        ((UINT32)0xE00000FF)
+#define HT_CAP_SUBTYPE_MASK                  ((UINT32)0xF80000FF)
+
+/* HT Host Capability */
+#define HT_HOST_CAPABILITY                    1
+#define HT_HOST_CAP_SIZE                      0x20
+
+/* Host CapabilityRegisters */
+#define HTHOST_LINK_CAPABILITY_REG            0x00
+#define HTHOST_LINK_CONTROL_REG               0x04
+#define HTHOST_FREQ_REV_REG                   0x08
+#define HTHOST_REV_REV3                       0x60
+#define HTHOST_FEATURE_CAP_REG                0x0C
+#define HTHOST_BUFFER_COUNT_REG               0x10
+#define HTHOST_ISOC_REG                       0x14
+#define HTHOST_LINK_TYPE_REG                  0x18
+#define HTHOST_FREQ_EXTENSION                 0x1C
+#define HTHOST_TYPE_COHERENT                  3
+#define HTHOST_TYPE_NONCOHERENT               7
+#define HTHOST_TYPE_MASK                      0x1F
+
+/* HT Slave Capability (HT1 compat) */
+#define HT_SLAVE_CAPABILITY                   0
+#define HTSLAVE_LINK01_OFFSET                 4
+#define HTSLAVE_LINK_CONTROL_0_REG            4
+#define HTSLAVE_FREQ_REV_0_REG                0xC
+#define HTSLAVE_FEATURECAP_REG                0x10
+#define HT_CONTROL_CLEAR_CRC                  (~(3 << 8))
+#define HT_FREQUENCY_CLEAR_LINK_ERRORS        (~(0x7 << 12))
+#define MAX_BUID                              31
+
+/* HT3 gen Capability */
+#define HT_GEN3_CAPABILITY                    (0xD << 1)
+#define HTGEN3_LINK01_OFFSET                  0x10
+#define HTGEN3_LINK_TRAINING_0_REG            0x10
+
+/* HT3 Retry Capability */
+#define HT_RETRY_CAPABILITY                   (0xC << 1)
+#define HTRETRY_CONTROL_REG                   4
+
+/* Unit ID Clumping Capability */
+#define HT_UNITID_CAPABILITY                  (0x9 << 1)
+#define HTUNIT_SUPPORT_REG                    4
+#define HTUNIT_ENABLE_REG                     8
+#define HT_CLUMPING_PASSIVE                   1
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// Forward declarations.
+/// Used for forward reference.
+typedef struct _NORTHBRIDGE NORTHBRIDGE;
+typedef struct _HT_FEATURES HT_FEATURES;
+typedef struct _HT_INTERFACE HT_INTERFACE;
+
+/**
+ * Coherent Init Data.
+ *
+ * Metrics representing the coherent fabric which was discovered:  Degree of nodes, adjacency,
+ * node numbering permutations, and the topology which it matched.
+ */
+typedef struct {
+  /** The number of coherent Links connected on each Node (the 'Degree' of the Node) */
+  UINT8 SysDegree[MAX_NODES];
+  /** The systems adjacency (sysMatrix[i][j] is true if Node_i has a Link to Node_j) */
+  BOOLEAN SysMatrix[MAX_NODES][MAX_NODES];
+
+  UINT8 DbDegree[MAX_NODES];               /**< Like sysDegree, but for the current database topology */
+  BOOLEAN DbMatrix[MAX_NODES][MAX_NODES];  /**< Like sysMatrix, but for the current database topology */
+
+  UINT8 Perm[MAX_NODES];           /**< The Node mapping from the system to the database */
+  UINT8 ReversePerm[MAX_NODES];    /**< The Node mapping from the database to the system */
+  UINT8 *MatchedTopology;          /**< The topology that matched the current system or NULL */
+} COHERENT_FABRIC;
+
+/**
+ * Represent the system as Links of matched port pairs.
+ * A pair consists of a source Node, a Link to the destination Node, the
+ * destination Node, and its Link back to source Node.  The even indices are
+ * the source Nodes and Links, and the odd indices are for the destination
+ * Nodes and Links.
+ * @note The Port pair 2*N and 2*N+1 are connected together to form a Link
+ * (e.g. 0,1 and 8,9 are ports on either end of an HT Link) The lower number
+ * port (2*N) is the source port.  The device that owns the source port is
+ * always the device closer to the BSP. (i.e. nearer the CPU in a
+ * non-coherent chain, or the CPU with the lower NodeID).
+ */
+typedef struct {
+  /* This section is where the Link is in the system and how to find it */
+  UINT8 Type;              /**< 0 = CPU, 1 = Device, all others reserved */
+  UINT8 Link;              /**< 0-1 for devices, 0-7 for CPUs */
+  UINT8 NodeID;            /**< The Node, or a pointer to the devices parent Node */
+  UINT8 HostLink;          /**< For Devices, the root CPU's Link to the chain */
+  UINT8 HostDepth;         /**< Link Depth in chain, only used by devices */
+  PCI_ADDR Pointer;        /**< A pointer to the device's slave HT capability, so we don't have to keep searching */
+
+  /* This section is for the final settings, which are written to hardware */
+  BOOLEAN SelRegang;          /**< Indicates to software regang Link, only used for CPU->CPU Links */
+  UINT8 SelWidthIn;           /**< Width in setting */
+  UINT8 SelWidthOut;          /**< Width out setting */
+  UINT8 SelFrequency;         /**< Frequency setting */
+
+  /* This section is for keeping track of capabilities and possible configurations */
+  BOOLEAN RegangCap;            /**< Is the port capable of reganging? CPUs only */
+  UINT32 PrvFrequencyCap;       /**< Possible frequency settings */
+  UINT8 PrvWidthInCap;          /**< Possible Width setting */
+  UINT8 PrvWidthOutCap;         /**< Possible Width setting */
+  UINT32 CompositeFrequencyCap; /**< Possible Link frequency setting */
+  UINT32 ClumpingSupport;       /**< Unit ID Clumping value (bit 0 = passive support) */
+} PORT_DESCRIPTOR;
+
+/// Reference to a set of PORT_DESCRIPTORs.
+typedef PORT_DESCRIPTOR (*PORT_LIST)[MAX_PLATFORM_LINKS*2];
+
+/**
+ * Our global state data structure
+ */
+typedef struct {
+  AMD_HT_INTERFACE *HtBlock;  /**< The input data structure. */
+
+  UINT8 NodesDiscovered;      /**< One less than the number of Nodes found in the system */
+  UINT8 TotalLinks;           /**< How many HT Links have we discovered so far. */
+  UINT8 SysMpCap;             /**< The maximum number of Nodes that all processors are capable of */
+  AGESA_STATUS MaxEventClass; /**< The event class of the highest severity event generated */
+
+  PORT_LIST PortList;         /**< Represent the system as a set of Links, each two Ports. */
+  COHERENT_FABRIC *Fabric;                        /**< Describe metrics about the coherent fabric.
+                                                   * Limited scope to CoherentInit().  */
+  /* Data interface to other Agesa Modules */
+  SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap;      /**< For each Socket, Die the Node ids */
+  NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap;      /**< For each Node id, Socket and Die */
+  HOP_COUNT_TABLE *HopCountTable;                 /**< Table of hops between nodes */
+
+  /* Data for non-coherent initialization */
+  UINT8 AutoBusCurrent;                      /**< The next bus number available */
+  UINT8 UsedCfgMapEntries;                   /**< The next Config address Map set available, Limit 4 (F1X[EC:E0]) */
+  BOOLEAN IsUsingRecoveryHt;                 /**< Manual BUID Swap List processing should assume that HT Recovery was used */
+  BOOLEAN IsSetHtCrcFlood;                   /**< Enable setting of HT CRC Flood */
+  BOOLEAN IsUsingUnitIdClumping;             /**< Enable automatic Unit Id Clumping configuration. */
+
+  HT_INTERFACE *HtInterface;   /**< Interface for feature code to external parameters */
+  HT_FEATURES *HtFeatures;     /**< The current feature implementations */
+  NORTHBRIDGE *Nb;             /**< The current northbridge */
+
+  PLATFORM_CONFIGURATION *PlatformConfiguration;     /**< The platform specific configuration customizations */
+  VOID *ConfigHandle;          /**< Config Pointer, opaque handle for passing to lib */
+} STATE_DATA;
+
+//
+// Feature Method types
+//
+
+/**
+ * Discover all coherent devices in the system.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out] State     our global state
+ *
+ */
+typedef VOID F_COHERENT_DISCOVERY (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_COHERENT_DISCOVERY *PF_COHERENT_DISCOVERY;
+
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]    State    the discovered fabric, degree matrix, permutation
+ *
+ */
+typedef VOID F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES *PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES;
+
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]   State    access topology, permutation, update hop table
+ *
+ */
+typedef VOID F_MAKE_HOP_COUNT_TABLE (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_MAKE_HOP_COUNT_TABLE *PF_MAKE_HOP_COUNT_TABLE;
+
+/**
+ * Process a non-coherent Link.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Node          Node on which to process nc init
+ * @param[in]     Link          The non-coherent Link on that Node
+ * @param[in]     IsCompatChain Is this the chain with the southbridge? TRUE if yes.
+ * @param[in,out] State         our global state
+ */
+typedef VOID F_PROCESS_LINK (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_PROCESS_LINK *PF_PROCESS_LINK;
+
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     State our global state, port list
+ */
+typedef VOID F_GATHER_LINK_DATA (
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GATHER_LINK_DATA *PF_GATHER_LINK_DATA;
+
+/**
+ * Optimize Links.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]    State         Process and update portlist
+ */
+typedef VOID F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY (
+  IN OUT   STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY *PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     State   our global state, port list
+ */
+typedef VOID F_SET_LINK_DATA (
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_SET_LINK_DATA *PF_SET_LINK_DATA;
+
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]   State       global state, port frequency settings.
+ *
+ * @retval          TRUE        Fixup occurred, all coherent links HT1
+ * @retval          FALSE       No changes
+ */
+typedef BOOLEAN F_IS_COHERENT_RETRY_FIXUP (
+  IN       STATE_DATA       *State
+  );
+/// Reference to a method.
+typedef F_IS_COHERENT_RETRY_FIXUP *PF_IS_COHERENT_RETRY_FIXUP;
+
+
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out] State          Our global state
+ */
+typedef VOID F_REGANG_LINKS (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_REGANG_LINKS *PF_REGANG_LINKS;
+
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]     State     Link state and port list
+ *
+ */
+typedef VOID F_SUBLINK_RATIO_FIXUP (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_SUBLINK_RATIO_FIXUP *PF_SUBLINK_RATIO_FIXUP;
+
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]   State   port list data
+ */
+typedef VOID F_TRAFFIC_DISTRIBUTION (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_TRAFFIC_DISTRIBUTION *PF_TRAFFIC_DISTRIBUTION;
+
+/**
+ * Access HT Link Control Register.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Reg      the PCI config address the control register
+ * @param[in]     HiBit    the high bit number
+ * @param[in]     LoBit    the low bit number
+ * @param[in]     Value    the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]     State    Our state, config handle for lib
+ */
+typedef VOID F_SET_HT_CONTROL_REGISTER_BITS (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  );
+/// Reference to a method.
+typedef F_SET_HT_CONTROL_REGISTER_BITS *PF_SET_HT_CONTROL_REGISTER_BITS;
+
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Value   the width Value
+ *
+ * @return The bits for the register
+ */
+typedef UINT8 F_CONVERT_WIDTH_TO_BITS (
+  IN       UINT8       Value
+  );
+/// Reference to a method.
+typedef F_CONVERT_WIDTH_TO_BITS *PF_CONVERT_WIDTH_TO_BITS;
+
+/**
+ * HT Feature Methods.
+ *
+ * Provides abstract methods which are bound to specific feature implementations.
+ */
+struct _HT_FEATURES {
+  PF_COHERENT_DISCOVERY CoherentDiscovery;    /**< Method: Coherent Discovery. */
+  PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES LookupComputeAndLoadRoutingTables;
+                                              /**< Method: Route the discovered system */
+  PF_MAKE_HOP_COUNT_TABLE MakeHopCountTable;  /**< Method: Compute slit hop counts */
+  PF_PROCESS_LINK ProcessLink;                /**< Method: Process a non-coherent Link. */
+  PF_GATHER_LINK_DATA GatherLinkData;         /**< Method: Gather Link Capabilities and data. */
+  PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY SelectOptimalWidthAndFrequency;
+                                              /**< Method: Optimize link features. */
+  PF_REGANG_LINKS RegangLinks;                /**< Method: Regang Sublinks. */
+  PF_SUBLINK_RATIO_FIXUP SubLinkRatioFixup;   /**< Method: Fix Sublink Frequency ratios */
+  PF_IS_COHERENT_RETRY_FIXUP IsCoherentRetryFixup;
+                                              /**< Method: Fix Retry mixed on coherent links. */
+  PF_SET_LINK_DATA SetLinkData;               /**< Method: Set optimized values. */
+  PF_TRAFFIC_DISTRIBUTION TrafficDistribution; /**< Method: Detect and Initialize Traffic Distribution */
+  PF_SET_HT_CONTROL_REGISTER_BITS SetHtControlRegisterBits; /**< Method: Access HT Link Control Reg. */
+  PF_CONVERT_WIDTH_TO_BITS ConvertWidthToBits; /**< Method: Convert a bit width to the value used for register setting. */
+};
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Provide the current Feature set implementation.
+ *
+ * Add an implementation reference for the constructor, just to make sure the page is created.
+ * @HtFeatMethod{::HT_FEATURES}.
+ *
+ */
+VOID
+NewHtFeatures (
+     OUT   HT_FEATURES          *HtFeatures,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+
+#endif  /* _HT_FEAT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
new file mode 100755
index 0000000000..e9aee6cbe7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
@@ -0,0 +1,143 @@
+/**
+ * @file
+ *
+ * Topology Interface.
+ *
+ * Contains interface to the topology data.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_GRAPH_H_
+#define _HT_GRAPH_H_
+
+/**
+ * @page htgraphdesign Graph Support routines
+ *
+ * These routines provide support for dealing with the graph representation
+ * of the topologies, along with the routing table information for that topology.
+ * The routing information is compressed and these routines currently decompress
+ * 'on the fly'.  A graph is represented as a set of routes. All the edges in the
+ * graph are routes; a direct route from Node i to Node j exists in the graph IFF
+ * there is an edge directly connecting Node i to Node j.  All other routes designate
+ * the edge which the route to that Node initially takes, by designating a Node
+ * to which a direct connection exists.  That is, the route to non-adjacent Node j
+ * from Node i specifies Node k where Node i directly connects to Node k.
+ *
+ *@code
+ * pseudo definition of compressed graph:
+ * typedef struct
+ * {
+ *     // First byte
+ *     UINT8 broadcast[8]:1;   // that is, 8 1-bit values
+ *     // Second byte
+ *     UINT8 requestRoute:4;   // [3:0]
+ *     UINT8 responseRoute:4;  // [7:4]
+ * } sRoute;
+ * typedef struct
+ * {
+ *     UINT8 size;
+ *     sRoute graph[size][size];
+ * } sGraph;
+ *@endcode
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+GetAmdTopolist (
+  OUT   UINT8    ***List
+  );
+
+UINT8
+GraphHowManyNodes (
+  IN       UINT8    *Graph
+  );
+
+BOOLEAN
+GraphIsAdjacent (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetRsp (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetReq (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetBc (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+#endif  /* _HT_GRAPH_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
new file mode 100755
index 0000000000..34215af04d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * Routines to deal with topology data.
+ *
+ * Access the topologies and information about a topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "htGraph.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTGRAPH_HTGRAPH_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the AGESA built in topology list
+ *
+ * @param[out]    List    a pointer to the built in topology list
+ */
+VOID
+GetAmdTopolist (
+  OUT   UINT8    ***List
+  )
+{
+  // Cast below to hush CONST warning. The built in list must be CONST to be in ROM statically.
+  // The caller of this routine may get a topolist pointer from the interface, however, and
+  // that is not CONST, since it could be on the stack.
+  //
+  *List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the number of Nodes in the compressed graph
+ *
+ * @param[in]     Graph   a compressed graph
+ *
+ * @return the number of Nodes in the graph
+ */
+UINT8
+GraphHowManyNodes (
+  IN       UINT8    *Graph
+  )
+{
+  return Graph[0];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns true if NodeA is directly connected to NodeB, false otherwise
+ *
+ * if NodeA == NodeB also returns false.
+ * Relies on rule that directly connected Nodes always route requests directly.
+ *
+ * @param[in]     Graph   the graph to examine
+ * @param[in]     NodeA   the Node number of the first Node
+ * @param[in]     NodeB   the Node number of the second Node
+ *
+ * @retval        TRUE    NodeA connects to NodeB
+ * @retval        FALSE   NodeA does not connect to NodeB
+ */
+BOOLEAN
+GraphIsAdjacent (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the graph Node used by NodeA to route responses targeted at NodeB.
+ *
+ *     This will be a Node directly connected to NodeA (possibly NodeB itself),
+ *     or "Route to Self" if NodeA and NodeB are the same Node.
+ *     Note that all Node numbers are abstract Node numbers of the topology graph,
+ *     it is the responsibility of the caller to apply any permutation needed.
+ *
+ * @param[in]     Graph the graph to examine
+ * @param[in]     NodeA the Node number of the first Node
+ * @param[in]     NodeB  the Node number of the second Node
+ *
+ * @return The response route Node
+ */
+UINT8
+GraphGetRsp (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the graph Node used by NodeA to route requests targeted at NodeB.
+ *
+ *     This will be a Node directly connected to NodeA (possibly NodeB itself),
+ *     or "Route to Self" if NodeA and NodeB are the same Node.
+ *     Note that all Node numbers are abstract Node numbers of the topology graph,
+ *     it is the responsibility of the caller to apply any permutation needed.
+ *
+ * @param[in]     Graph the graph to examine
+ * @param[in]     NodeA the Node number of the first Node
+ * @param[in]     NodeB the Node number of the second Node
+ *
+ * @return The request route Node
+ */
+UINT8
+GraphGetReq (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns a bit vector of Nodes that NodeA should forward a broadcast from
+ * NodeB towards
+ *
+ * @param[in]     Graph the graph to examine
+ * @param[in]     NodeA the Node number of the first Node
+ * @param[in]     NodeB the Node number of the second Node
+ *
+ * @return the broadcast routes for NodeA from NodeB
+ */
+UINT8
+GraphGetBc (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return Graph[1 + (NodeA*size + NodeB)*2];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph1.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph1.c
new file mode 100755
index 0000000000..b6eac6210f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph1.c
@@ -0,0 +1,66 @@
+/**
+ * @file
+ *
+ * Single node topology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   0
+ */
+/**
+ * single node
+ */
+/**
+ * @dot
+ strict graph one {
+     node [shape="plaintext"];
+     0;
+     }
+     @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySingleNode[] =
+{
+  0x01,
+  0x00, 0xFF  // Node 0
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph2.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph2.c
new file mode 100755
index 0000000000..32f952c1e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph2.c
@@ -0,0 +1,67 @@
+/**
+ * @file
+ *
+ * Two nodes.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *    0---1
+ */
+/**
+ * Two Nodes.
+ */
+/**
+ * @dot
+ strict graph two {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     }
+     @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyDualNode[] =
+{
+  0x02,
+  0x02, 0xFF,   0x00, 0x11,  // Node 0
+  0x00, 0x00,   0x01, 0xFF   // Node 1
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c
new file mode 100755
index 0000000000..68e8207c16
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * Three Line.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2
+ *   |
+ *   |
+ *   0---1
+ */
+/**
+ * Three Line
+ */
+/**
+ * @dot
+ strict graph three {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     0 -- 2 ;
+     }
+     @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyThreeLine[] =
+{
+  0x03,
+  0x06, 0xFF,  0x04, 0x11,  0x02, 0x22,  // Node 0
+  0x00, 0x00,  0x01, 0xFF,  0x00, 0x00,  // Node 1
+  0x00, 0x00,  0x00, 0x00,  0x01, 0xFF   // Node 2
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c
new file mode 100755
index 0000000000..97a7285f97
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * Three Triangle Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2
+ *   |\
+ *   |  \
+ *   0---1
+ */
+/**
+ * Three triangle
+ */
+/**
+ * @dot
+ strict graph triangle {
+ node [shape="plaintext"];
+ 0 -- 1 ;
+ 0 -- 2 ;
+ 1 -- 2 ;
+ }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyTriangle[] =
+{
+  0x03,
+  0x06, 0xFF,  0x00, 0x11,  0x00, 0x22,  // Node 0
+  0x00, 0x00,  0x05, 0xFF,  0x00, 0x22,  // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x03, 0xFF   // Node 2
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c
new file mode 100755
index 0000000000..193fa8f6ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c
@@ -0,0 +1,77 @@
+/**
+ * @file
+ *
+ * Four node degenerate.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2   3
+ *   |\  |
+ *   |  \|
+ *   0---1
+ */
+/**
+ * Four Node degenerate
+ */
+/**
+ * @dot
+   strict graph degen4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 2 ;
+     1 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[] =
+{
+  0x04,
+  0x06, 0xFF,   0x00, 0x11,   0x00, 0x22,   0x00, 0x11,  // Node 0
+  0x08, 0x00,   0x0D, 0xFF,   0x08, 0x22,   0x05, 0x33,  // Node 1
+  0x00, 0x00,   0x00, 0x11,   0x03, 0xFF,   0x00, 0x11,  // Node 2
+  0x00, 0x11,   0x00, 0x11,   0x00, 0x11,   0x02, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4FullyConnected.c
new file mode 100755
index 0000000000..4cb69084ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4FullyConnected.c
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * Four node fully connected.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |\ /|
+ *   |/ \|
+ *   0---1
+ */
+/**
+ * Four Node Fully
+ */
+/**
+ * @dot
+   strict graph full4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     0 -- 3 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourFully[] =
+{
+  0x04,
+  0x0E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  // Node 0
+  0x00, 0x00,  0x0D, 0xFF,  0x00, 0x22,  0x00, 0x33,  // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x0B, 0xFF,  0x00, 0x33,  // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x07, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c
new file mode 100755
index 0000000000..3b10b876ad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * Four node kite Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |\  |
+ *   |  \|
+ *   0---1
+ */
+/**
+ * Four Node kite
+ */
+/**
+ * @dot
+   strict graph kite4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourKite[] =
+{
+  0x04,
+  0x06, 0xFF,   0x00, 0x11,   0x00, 0x22,   0x00, 0x11,  // Node 0
+  0x08, 0x00,   0x0D, 0xFF,   0x00, 0x22,   0x00, 0x33,  // Node 1
+  0x00, 0x00,   0x00, 0x11,   0x0B, 0xFF,   0x01, 0x33,  // Node 2
+  0x00, 0x22,   0x00, 0x11,   0x00, 0x22,   0x06, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c
new file mode 100755
index 0000000000..013bac1fe7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Four node Line Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2   3
+ *   |   |
+ *   |   |
+ *   0---1
+ */
+/**
+ * Four Node line
+ */
+/**
+ * @dot
+   strict graph line4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourLine[] =
+{
+  0x04,
+  0x06, 0xFF,   0x04, 0x11,   0x02, 0x22,   0x04, 0x11,  // Node 0
+  0x08, 0x00,   0x09, 0xFF,   0x08, 0x00,   0x01, 0x33,  // Node 1
+  0x00, 0x00,   0x00, 0x00,   0x01, 0xFF,   0x00, 0x00,  // Node 2
+  0x00, 0x11,   0x00, 0x11,   0x00, 0x11,   0x02, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c
new file mode 100755
index 0000000000..1da11d3a90
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c
@@ -0,0 +1,77 @@
+/**
+ * @file
+ *
+ * Four node Square Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |   |
+ *   |   |
+ *   0---1
+ */
+/**
+ * Four Node square
+ */
+/**
+ * @dot
+   strict graph square4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourSquare[] =
+{
+  0x04,
+  0x06, 0xFF,   0x00, 0x11,   0x02, 0x22,   0x00, 0x22,  // Node 0
+  0x00, 0x00,   0x09, 0xFF,   0x00, 0x33,   0x01, 0x33,  // Node 1
+  0x08, 0x00,   0x00, 0x00,   0x09, 0xFF,   0x00, 0x33,  // Node 2
+  0x00, 0x11,   0x04, 0x11,   0x00, 0x22,   0x06, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c
new file mode 100755
index 0000000000..b3c9a8f366
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Four node Star Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |\
+ *   |  \
+ *   0   1
+ */
+/**
+ * Four Node Star
+ */
+/**
+ * @dot
+   strict graph star4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 2 ;
+     1 -- 2 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourStar[] =
+{
+  0x04,
+  0x04, 0xFF,   0x00, 0x22,   0x00, 0x22,   0x00, 0x22,  // Node 0
+  0x00, 0x22,   0x04, 0xFF,   0x00, 0x22,   0x00, 0x22,  // Node 1
+  0x0A, 0x00,   0x09, 0x11,   0x0B, 0xFF,   0x03, 0x33,  // Node 2
+  0x00, 0x22,   0x00, 0x22,   0x00, 0x22,   0x04, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5FullyConnected.c
new file mode 100755
index 0000000000..4910eb6d4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5FullyConnected.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Five node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * Five node fully connected
+ */
+/**
+ * @dot
+   strict graph full5 {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     0 -- 2 ;
+     0 -- 3 ;
+     0 -- 4 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     1 -- 4 ;
+     2 -- 3 ;
+     2 -- 4 ;
+     3 -- 4 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFiveFully[] =
+{
+  0x05,
+  0x1E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44, // Node 0
+  0x00, 0x00,  0x1D, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x1B, 0xFF,  0x00, 0x33,  0x00, 0x44, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x17, 0xFF,  0x00, 0x44, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x0F, 0xFF  // Node 4
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5TwistedLadder.c
new file mode 100755
index 0000000000..61369f4d23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5TwistedLadder.c
@@ -0,0 +1,85 @@
+/**
+ * @file
+ *
+ * Five node pop order twisted ladder Topology.
+ *
+ * The population order fall back to five nodes on a twisted ladder.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *
+ *  4
+ *  |\
+ *  |  \
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * Five node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl5 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     3 -- 4 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[] =
+{
+  0x05,
+  0x06, 0xFF,  0x04, 0x11,  0x02, 0x22,  0x00, 0x11,  0x00, 0x22, // Node0
+  0x08, 0x00,  0x09, 0xFF,  0x08, 0x00,  0x01, 0x33,  0x00, 0x30, // Node1
+  0x10, 0x00,  0x10, 0x00,  0x11, 0xFF,  0x00, 0x40,  0x01, 0x44, // Node2
+  0x00, 0x11,  0x00, 0x11,  0x00, 0x14,  0x12, 0xFF,  0x02, 0x44, // Node3
+  0x00, 0x22,  0x00, 0x23,  0x00, 0x22,  0x04, 0x33,  0x0C, 0xFF  // Node4
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonLower.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonLower.c
new file mode 100755
index 0000000000..592644f52a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonLower.c
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Six node hydra Topology using "Doubloon/Drachma", Lower nodes remain.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 6 node hydra doubloon lower nodes, 3 MCM processors.
+ * For partial populations, note nodes are removed in pairs.
+ */
+/**
+ * @dot
+   strict graph doubloon8lower {
+     node [shape="plaintext"];
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;
+     0 -- 2 ;    1 -- 2 ;   2 -- 4 ;   3 -- 5 ;
+     0 -- 4 ;    1 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[] =
+{
+  0x06,
+  0x16, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44, // Node 0
+  0x00, 0x00,  0x25, 0xFF,  0x00, 0x22,  0x00, 0x22,  0x00, 0x55,  0x01, 0x55, // Node 1
+  0x08, 0x00,  0x08, 0x11,  0x19, 0xFF,  0x03, 0x33,  0x08, 0x44,  0x00, 0x44, // Node 2
+  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0x24, 0xFF,  0x00, 0x55,  0x04, 0x55, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x25, 0xFF,  0x00, 0x55, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x1A, 0xFF, // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c
new file mode 100755
index 0000000000..afadd09c49
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Six node hydra Topology using "Doubloon/Drachma", Upper nodes remain.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 6 node hydra drachma, upper nodes remain, 3 MCM processors.
+ * For partial population cases, note that nodes are removed in pairs.
+ */
+/**
+ * @dot
+   strict graph doubloon6upper {
+     node [shape="plaintext"];
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;
+     0 -- 2 ;    1 -- 2 ;   2 -- 4 ;   3 -- 5 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 5 ;   3 -- 4 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[] =
+{
+  0x06,
+  0x16, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44, // Node 0
+  0x00, 0x00,  0x25, 0xFF,  0x00, 0x22,  0x00, 0x22,  0x00, 0x55,  0x01, 0x55, // Node 1
+  0x08, 0x00,  0x08, 0x11,  0x3B, 0xFF,  0x03, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 2
+  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0x34, 0xFF,  0x00, 0x44,  0x00, 0x55, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x00, 0x22,  0x00, 0x33,  0x2D, 0xFF,  0x00, 0x55, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x1E, 0xFF, // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6FullyConnected.c
new file mode 100755
index 0000000000..87364db493
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6FullyConnected.c
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * Six node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 6 node fully connected
+ */
+/**
+ * @dot
+   strict graph full6 {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     0 -- 2 ;
+     0 -- 3 ;
+     0 -- 4 ;
+     0 -- 5 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     1 -- 4 ;
+     1 -- 5 ;
+     2 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+     4 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixFully[] =
+{
+  0x06,
+  0x3E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 0
+  0x00, 0x00,  0x3D, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x3B, 0xFF,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x37, 0xFF,  0x00, 0x44,  0x00, 0x55, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x2F, 0xFF,  0x00, 0x55, // Node 4
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x1F, 0xFF  // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwinTriangles.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwinTriangles.c
new file mode 100755
index 0000000000..5e59d901eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwinTriangles.c
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * A six node Topology of three MCMs.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/* (2 fully connected three ways connected at the 'corners')
+ *
+ *       5
+ *      /| \
+ *     / 1 - 3
+ *    / /    /
+ *   4 /    /
+ *   | \   /
+ *   0 - 2-
+ */
+/**
+ * Six Node hydra
+ */
+/**
+ * @dot
+   strict graph hmcm6 {
+     node [shape="plaintext"];
+     subgraph even {
+     0 -- 2 ;    2 -- 4 ;
+     0 -- 4 ;
+     }
+     subgraph odd {
+     1 -- 3 ;   3 -- 5
+     1 -- 5 ;
+     }
+     {rank=same; 0; 2; 1; 3}
+     {rank=same; 4; 5}
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[] =
+{
+  0x06,
+  0x16, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44,  // Node 0
+  0x00, 0x00,  0x29, 0xFF,  0x00, 0x33,  0x01, 0x33,  0x00, 0x55,  0x01, 0x55,  // Node 1
+  0x08, 0x00,  0x00, 0x00,  0x19, 0xFF,  0x00, 0x33,  0x08, 0x44,  0x00, 0x44,  // Node 2
+  0x00, 0x11,  0x04, 0x11,  0x00, 0x22,  0x26, 0xFF,  0x00, 0x55,  0x04, 0x55,  // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x25, 0xFF,  0x00, 0x55,  // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x1A, 0xFF,  // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwistedLadder.c
new file mode 100755
index 0000000000..85e94ce614
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwistedLadder.c
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * Six node pop order twisted ladder Topology.
+ *
+ * The population order fall back to Six nodes on a twisted ladder.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *
+ *  4   5
+ *  |\ /|
+ *  |/ \|
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 6 node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl6 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[] =
+{
+  0x06,
+  0x06, 0xFF,  0x04, 0x11,  0x02, 0x22,  0x00, 0x11,  0x02, 0x22,  0x00, 0x12, // Node0
+  0x08, 0x00,  0x09, 0xFF,  0x00, 0x00,  0x01, 0x33,  0x00, 0x03,  0x01, 0x33, // Node1
+  0x30, 0x00,  0x00, 0x00,  0x31, 0xFF,  0x00, 0x54,  0x21, 0x44,  0x00, 0x55, // Node2
+  0x00, 0x11,  0x30, 0x11,  0x00, 0x45,  0x32, 0xFF,  0x00, 0x44,  0x12, 0x55, // Node3
+  0x00, 0x22,  0x00, 0x32,  0x08, 0x22,  0x00, 0x33,  0x0C, 0xFF,  0x00, 0x32, // Node4
+  0x00, 0x23,  0x00, 0x33,  0x00, 0x22,  0x04, 0x33,  0x00, 0x23,  0x0C, 0xFF  // Node5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7FullyConnected.c
new file mode 100755
index 0000000000..f0039d4239
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7FullyConnected.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * Seven node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 7 node fully connected
+ */
+/**
+ * @dot
+   strict graph full7 {
+     node [shape="plaintext"];
+     0 -- 1 ;    1 -- 2 ;   2 -- 3 ;     3 -- 4 ;   4 -- 5 ; 5 -- 6 ;
+     0 -- 2 ;    1 -- 3 ;   2 -- 4 ;     3 -- 5 ;   4 -- 6 ;
+     0 -- 3 ;    1 -- 4 ;   2 -- 5 ;     3 -- 6 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 6 ;
+     0 -- 5 ;    1 -- 6 ;
+     0 -- 6 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySevenFully[] =
+{
+  0x07,
+  0x7E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 0
+  0x00, 0x00,  0x7D, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x7B, 0xFF,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x77, 0xFF,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x6F, 0xFF,  0x00, 0x55,  0x00, 0x66, // Node 4
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x5F, 0xFF,  0x00, 0x66, // Node 5
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x3F, 0xFF  // Node 6
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7TwistedLadder.c
new file mode 100755
index 0000000000..cb25523d33
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7TwistedLadder.c
@@ -0,0 +1,91 @@
+/**
+ * @file
+ *
+ * Seven node pop order twisted ladder Topology.
+ *
+ * The population order fall back to Seven nodes on a twisted ladder.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*  6
+ *  |
+ *  4   5
+ *  |\ /|
+ *  |/ \|
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 7 node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl7 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     {rank=same; 6}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+     4 -- 6 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[] =
+{
+  0x07,
+  0x06, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x12,  0x00, 0x22,  0x00, 0x22,  0x00, 0x22, // Node0
+  0x00, 0x00,  0x09, 0xFF,  0x00, 0x03,  0x01, 0x33,  0x00, 0x33,  0x00, 0x33,  0x00, 0x33, // Node1
+  0x30, 0x00,  0x00, 0x50,  0x31, 0xFF,  0x00, 0x54,  0x21, 0x44,  0x01, 0x55,  0x21, 0x44, // Node2
+  0x00, 0x41,  0x30, 0x11,  0x00, 0x45,  0x32, 0xFF,  0x02, 0x44,  0x12, 0x55,  0x02, 0x44, // Node3
+  0x48, 0x22,  0x40, 0x33,  0x48, 0x22,  0x40, 0x33,  0x4C, 0xFF,  0x40, 0x32,  0x0C, 0x66, // Node4
+  0x00, 0x22,  0x04, 0x33,  0x00, 0x22,  0x04, 0x33,  0x00, 0x23,  0x0C, 0xFF,  0x00, 0x23, // Node5
+  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x10, 0xFF  // Node6
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c
new file mode 100755
index 0000000000..895ed1b8b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * Eight node hydra Topology using "Doubloon/Drachma".
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 8 node hydra doubloon, 4 MCM processors.
+ */
+/**
+ * @dot
+   strict graph doubloon8 {
+     node [shape="plaintext"];
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;   6 -- 7 ;
+     0 -- 2 ;    1 -- 2 ;   2 -- 4 ;   3 -- 5 ;   4 -- 6 ; 5 -- 6 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 6 ;   3 -- 7 ;
+     0 -- 6 ;    1 -- 7 ;   2 -- 7 ;   3 -- 6
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[] =
+{
+  0x08,
+  0x56, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44,  0x02, 0x66,  0x00, 0x66, // Node 0
+  0x00, 0x00,  0xA5, 0xFF,  0x00, 0x22,  0x00, 0x22,  0x00, 0x55,  0x01, 0x55,  0x00, 0x77,  0x01, 0x77, // Node 1
+  0x08, 0x00,  0x08, 0x11,  0xDB, 0xFF,  0x03, 0x33,  0x08, 0x44,  0x00, 0x44,  0x00, 0x66,  0x00, 0x77, // Node 2
+  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0xE4, 0xFF,  0x00, 0x55,  0x04, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x65, 0xFF,  0x00, 0x55,  0x00, 0x66,  0x00, 0x66, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x5A, 0xFF,  0x00, 0x66,  0x00, 0x66, // Node 5
+  0x80, 0x00,  0x00, 0x00,  0x00, 0x22,  0x00, 0x33,  0x80, 0x44,  0x80, 0x55,  0xBD, 0xFF,  0x30, 0x77, // Node 6
+  0x00, 0x11,  0x40, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x66,  0x00, 0x66,  0x00, 0x66,  0x4E, 0xFF  // Node 7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8FullyConnected.c
new file mode 100755
index 0000000000..edde208b89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8FullyConnected.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Eight node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 8 node fully connected
+ */
+/**
+ * @dot
+   strict graph full8 {
+     node [shape="plaintext"];
+     0 -- 1 ;    1 -- 2 ;   2 -- 3 ;   3 -- 4 ;   4 -- 5 ; 5 -- 6 ;  6 -- 7 ;
+     0 -- 2 ;    1 -- 3 ;   2 -- 4 ;   3 -- 5 ;   4 -- 6 ; 5 -- 7 ;
+     0 -- 3 ;    1 -- 4 ;   2 -- 5 ;   3 -- 6 ;   4 -- 7 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 6 ;   3 -- 7 ;
+     0 -- 5 ;    1 -- 6 ;   2 -- 7 ;
+     0 -- 6 ;    1 -- 7 ;
+     0 -- 7 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightFully[] =
+{
+  0x08,
+  0xFE, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 0
+  0x00, 0x00,  0xFD, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0xFB, 0xFF,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0xF7, 0xFF,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0xEF, 0xFF,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 4
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0xDF, 0xFF,  0x00, 0x66,  0x00, 0x77, // Node 5
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0xBF, 0xFF,  0x00, 0x77, // Node 6
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x7F, 0xFF  // Node 7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
new file mode 100755
index 0000000000..2b0e98b7bb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Eight node Ladder Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*  6---7
+ *  |   |
+ *  4---5
+ *  |   |
+ *  2---3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 8 node ladder
+ */
+/**
+ * @dot
+   strict graph ladder8 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     {rank=same; 6; 7}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 3 ;
+     3 -- 5 ;
+     4 -- 5 ;
+     4 -- 6 ;
+     5 -- 7 ;
+     6 -- 7 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
+{
+  0x08,
+  0x06, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x22,  0x00, 0x22,  0x02, 0x22,  0x00, 0x22, // Node0
+  0x00, 0x00,  0x09, 0xFF,  0x00, 0x33,  0x01, 0x33,  0x00, 0x33,  0x01, 0x33,  0x00, 0x33,  0x01, 0x33, // Node1
+  0x18, 0x00,  0x00, 0x00,  0x19, 0xFF,  0x00, 0x33,  0x09, 0x44,  0x00, 0x44,  0x09, 0x44,  0x00, 0x44, // Node2
+  0x00, 0x11,  0x24, 0x11,  0x00, 0x22,  0x26, 0xFF,  0x00, 0x55,  0x06, 0x55,  0x00, 0x55,  0x06, 0x55, // Node3
+  0x60, 0x22,  0x00, 0x22,  0x60, 0x22,  0x00, 0x22,  0x64, 0xFF,  0x00, 0x55,  0x24, 0x66,  0x00, 0x66, // Node4
+  0x00, 0x33,  0x90, 0x33,  0x00, 0x33,  0x90, 0x33,  0x00, 0x44,  0x98, 0xFF,  0x00, 0x77,  0x18, 0x77, // Node5
+  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x90, 0xFF,  0x00, 0x77, // Node6
+  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
new file mode 100755
index 0000000000..57f7d599d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Eight node Topology of two fully connected four ways.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/* (2 fully connected four ways connected at the 'corners')
+ *
+ *       5 - 7
+ *      /| X |
+ *     / 1 - 3
+ *    / / /  /
+ *   4 - 6  /
+ *   | X | /
+ *   0 - 2-
+ */
+/**
+ * 8 node twin fully connected four ways, connected by the MCM internal links.
+ */
+/**
+ * @dot
+   strict graph hydra8 {
+     node [shape="plaintext"];
+     subgraph even {
+     0 -- 2 ;    2 -- 4 ;   4 -- 6 ;
+     0 -- 4 ;    2 -- 6 ;
+     0 -- 6 ;
+     }
+     subgraph odd {
+     1 -- 3 ;   3 -- 5 ;   5 -- 7 ;
+     1 -- 5 ;   3 -- 7 ;
+     1 -- 7 ;
+     }
+     {rank=same; 0; 2; 1; 3}
+     {rank=same; 4; 6; 5; 7}
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;   6 -- 7 ;
+     }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[] =
+{
+  0x08,
+  0x56, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44,  0x02, 0x66,  0x00, 0x66, // Node 0
+  0x00, 0x00,  0xA9, 0xFF,  0x00, 0x33,  0x01, 0x33,  0x00, 0x55,  0x01, 0x55,  0x00, 0x77,  0x01, 0x77, // Node 1
+  0x08, 0x00,  0x00, 0x00,  0x59, 0xFF,  0x00, 0x33,  0x08, 0x44,  0x00, 0x44,  0x08, 0x66,  0x00, 0x66, // Node 2
+  0x00, 0x11,  0x04, 0x11,  0x00, 0x22,  0xA6, 0xFF,  0x00, 0x55,  0x04, 0x55,  0x00, 0x77,  0x04, 0x77, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x65, 0xFF,  0x00, 0x55,  0x20, 0x66,  0x00, 0x66, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x9A, 0xFF,  0x00, 0x77,  0x10, 0x77, // Node 5
+  0x80, 0x00,  0x00, 0x00,  0x80, 0x22,  0x00, 0x22,  0x80, 0x44,  0x00, 0x44,  0x95, 0xFF,  0x00, 0x77, // Node 6
+  0x00, 0x11,  0x40, 0x11,  0x00, 0x33,  0x40, 0x33,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x6A, 0xFF  // Node 7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwistedLadder.c
new file mode 100755
index 0000000000..5b19c721b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwistedLadder.c
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Eight node twisted ladder Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*  6---7
+ *  |   |
+ *  4   5
+ *  |\ /|
+ *  |/ \|
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 8 node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl8 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     {rank=same; 6; 7}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+     4 -- 6 ;
+     5 -- 7 ;
+     6 -- 7 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[] =
+{
+  0x08,
+  0x06, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x12,  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0x00, 0x22, // Node0
+  0x00, 0x00,  0x09, 0xFF,  0x00, 0x03,  0x01, 0x33,  0x00, 0x33,  0x00, 0x33,  0x00, 0x33,  0x00, 0x33, // Node1
+  0x30, 0x00,  0x00, 0x50,  0x31, 0xFF,  0x00, 0x54,  0x21, 0x44,  0x01, 0x55,  0x21, 0x44,  0x01, 0x55, // Node2
+  0x00, 0x41,  0x30, 0x11,  0x00, 0x45,  0x32, 0xFF,  0x02, 0x44,  0x12, 0x55,  0x02, 0x44,  0x12, 0x55, // Node3
+  0x48, 0x22,  0x40, 0x33,  0x48, 0x22,  0x40, 0x33,  0x4C, 0xFF,  0x00, 0x32,  0x0C, 0x66,  0x00, 0x36, // Node4
+  0x80, 0x22,  0x84, 0x33,  0x80, 0x22,  0x84, 0x33,  0x00, 0x23,  0x8C, 0xFF,  0x00, 0x27,  0x0C, 0x77, // Node5
+  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x74,  0x90, 0xFF,  0x00, 0x77, // Node6
+  0x00, 0x55,  0x00, 0x55,  0x00, 0x55,  0x00, 0x55,  0x00, 0x65,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
new file mode 100755
index 0000000000..1639a22735
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
@@ -0,0 +1,238 @@
+/**
+ * @file
+ *
+ * External Interface implementation.
+ *
+ * Contains routines for implementing the interface to the client BIOS.
+ * This file includes the interface access constructor.
+ * This file implements build options using conditional compilation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "CommonReturns.h"
+#include "htInterfaceGeneral.h"
+#include "htInterfaceCoherent.h"
+#include "htInterfaceNonCoherent.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACE_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * The default initializer for the HT internal interface, full features.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceDefault =
+{
+  GetCpu2CpuPcbLimits,
+  GetSkipRegang,
+  NewHopCountTable,
+  GetOverrideBusNumbers,
+  GetManualBuidSwapList,
+  GetDeviceCapOverride,
+  GetIoPcbLimits,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  CleanMapsAfterError,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * The non-coherent only build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceNonCoherentOnly =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  GetOverrideBusNumbers,
+  GetManualBuidSwapList,
+  GetDeviceCapOverride,
+  GetIoPcbLimits,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * Topology Maps only feature build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceMapsOnly =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
+  (PF_GET_IGNORE_LINK)CommonReturnFalse,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  SetNodeToSocketMap,
+  (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
+};
+
+/**
+ * No features build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceNone =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
+  (PF_GET_IGNORE_LINK)CommonReturnFalse,
+  (PF_POST_MAP_TO_AP)CommonVoid,
+  (PF_NEW_NODE_AND_SOCKET_TABLES)CommonVoid,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  (PF_SET_NODE_TO_SOCKET_MAP)CommonVoid,
+  (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
+};
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * A constructor for the internal Ht Interface.
+ *
+ * The install has a reference to the initializer appropriate to the user selected build
+ * options.  Use the selected initializer to construct the internal interface.
+ *
+ * @param[in,out]   HtInterface    Contains pointer to HT Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header
+ *
+*/
+VOID
+NewHtInterface (
+     OUT   HT_INTERFACE         *HtInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) HtInterface,
+    (VOID *) OptionHtConfiguration.HtOptionInternalInterface,
+    (sizeof (HT_INTERFACE)),
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * A "constructor" for the HyperTransport external interface.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * Copy the initial default values from the build options tables to the interface struct.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) AmdHtInterface,
+    (VOID *) OptionHtConfiguration.HtOptionPlatformDefaults,
+    (UINT32) (sizeof (AMD_HT_INTERFACE)),
+    StdHeader
+    );
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h
new file mode 100755
index 0000000000..84d1b59987
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h
@@ -0,0 +1,487 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * This file includes the interface access constructor and interface
+ * support which is not removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_H_
+#define _HT_INTERFACE_H_
+
+/**
+ * @page htimplintf HT Internal Interface Implementation Guide
+ *
+ * HT Internal Interface provides access to the HT Component external interface (see AGESA.h),
+ * in a manner that isolates calling code from knowledge about the external interface or which
+ * interfaces are supported in the current build.
+ *
+ * @par Adding a Method to HT Internal Interface
+ *
+ * To add a new method to the HT Internal Interface, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME  </tt> @n
+ *   </ul>
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtInterfaceInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::HT_INTERFACE struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an HT Internal Interface Instance of the method.
+ *
+ * To implement an instance of a method for a specific interface  follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the method typedef.
+ *
+ * - Name the function MethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtInterfaceMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other Ht internal interface routines or data as part of the method implementation, the function
+ *   must use HtInterface->OtherMethod().  Do not directly access other HT internal interface
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple families.
+ *
+ * - Add the instance to the ::HT_INTERFACE instances.
+ *
+ * - If a configuration does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking HT Internal Interface Methods.
+ *
+ * The first step is carried out only once by the top level HT entry point.
+ * @n @code
+ *   HT_INTERFACE HtInterface;
+ *   // Get the current HT internal interface (to HtBlock data)
+ *   NewHtInterface (&HtInterface);
+ *   State->HtInterface = &HtInterface;
+ * @endcode
+ *
+ * The following example shows how to invoke a HT Internal Interface method.
+ * @n @code
+ *    State->HtInterface->MethodName ();
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     NodeA            One Node on which this Link is located
+ * @param[in]     LinkA            The Link on this Node
+ * @param[in]     NodeB            The other Node on which this Link is located
+ * @param[in]     LinkB            The Link on that Node
+ * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
+ * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap       modify to change the Link's frequency capability
+ * @param[in]     State            the input data
+ *
+ */
+typedef VOID F_GET_CPU_2_CPU_PCB_LIMITS (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_CPU_2_CPU_PCB_LIMITS *PF_GET_CPU_2_CPU_PCB_LIMITS;
+
+/**
+ * Skip reganging of subLinks.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     NodeA    One Node on which this Link is located
+ * @param[in]     LinkA    The Link on this Node
+ * @param[in]     NodeB    The other Node on which this Link is located
+ * @param[in]     LinkB    The Link on that Node
+ * @param[in]     State    the input data
+ *
+ * @retval        MATCHED      leave Link unganged
+ * @retval        POWERED_OFF  leave link unganged and power off the paired sublink
+ * @retval        UNMATCHED    regang Link automatically
+ */
+typedef FINAL_LINK_STATE F_GET_SKIP_REGANG (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_SKIP_REGANG *PF_GET_SKIP_REGANG;
+
+/**
+ * Manually control bus number assignment.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node      The Node on which this chain is located
+ * @param[in]     Link      The Link on the host for this chain
+ * @param[out]    SecBus    Secondary Bus number for this non-coherent chain
+ * @param[out]    SubBus    Subordinate Bus number
+ * @param[in]     State     the input data
+ *
+ * @retval        TRUE      this routine is supplying the bus numbers
+ * @retval        FALSE     use auto Bus numbering
+ */
+typedef BOOLEAN F_GET_OVERRIDE_BUS_NUMBERS (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_OVERRIDE_BUS_NUMBERS *PF_GET_OVERRIDE_BUS_NUMBERS;
+
+/**
+ * Get Manual BUID assignment list.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]    Node    The Node on which this chain is located
+ * @param[in]    Link    The Link on the host for this chain
+ * @param[out]   List    a pointer to a list, if returns TRUE
+ * @param[in]    State   the input data
+ *
+ * @retval      TRUE     use manual List
+ * @retval      FALSE    initialize the Link automatically. List not valid.
+ */
+typedef BOOLEAN F_GET_MANUAL_BUID_SWAP_LIST (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  );
+/// Reference to a method.
+typedef F_GET_MANUAL_BUID_SWAP_LIST *PF_GET_MANUAL_BUID_SWAP_LIST;
+
+/**
+ * Override capabilities of a device.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     HostNode      The Node on which this chain is located
+ * @param[in]     HostLink      The Link on the host for this chain
+ * @param[in]     Depth         The Depth in the I/O chain from the Host
+ * @param[in]     PciAddress    The Device's PCI config address (for callout)
+ * @param[in]     DevVenId      The Device's PCI Vendor + Device ID (offset 0x00)
+ * @param[in]     Revision      The Device's PCI Revision
+ * @param[in]     Link          The Device's Link number (0 or 1)
+ * @param[in,out] LinkWidthIn   modify to change the Link Width In
+ * @param[in,out] LinkWidthOut  modify to change the Link Width Out
+ * @param[in,out] FreqCap       modify to change the Link's frequency capability
+ * @param[in,out] Clumping      modify to change unit id clumping capability
+ * @param[in]     State         the input data
+ *
+ */
+typedef VOID F_GET_DEVICE_CAP_OVERRIDE (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  );
+/// Reference to a method.
+typedef F_GET_DEVICE_CAP_OVERRIDE *PF_GET_DEVICE_CAP_OVERRIDE;
+
+/**
+ * Get limits for non-coherent Links.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     HostNode                   The Node on which this Link is located
+ * @param[in]     HostLink                   The Link about to be initialized
+ * @param[in]     Depth                      The Depth in the I/O chain from the Host
+ * @param[in,out] DownstreamLinkWidthLimit   modify to change the Link Width In
+ * @param[in,out] UpstreamLinkWidthLimit     modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap                 modify to change the Link's frequency capability
+ * @param[in]     State                      the input data
+ */
+typedef VOID F_GET_IO_PCB_LIMITS (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_IO_PCB_LIMITS *PF_GET_IO_PCB_LIMITS;
+
+/**
+ * Get the Socket number for a given Node number.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node    Node discovered event data.
+ * @param[in]     State   reference to Node to socket map
+ *
+ * @return the socket id
+ *
+ */
+typedef UINT8 F_GET_SOCKET_FROM_MAP (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_GET_SOCKET_FROM_MAP *PF_GET_SOCKET_FROM_MAP;
+
+/**
+ * Ignore a Link.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node   The Node on which this Link is located
+ * @param[in]     Link   The Link about to be initialized
+ * @param[in]     NbList The northbridge default ignore link list
+ * @param[in]     State   the input data
+ *
+ * @retval        MATCHED     ignore this Link and skip it
+ * @retval        POWERED_OFF ignore this link and power it off.
+ * @retval        UNMATCHED   initialize the Link normally
+ */
+typedef FINAL_LINK_STATE F_GET_IGNORE_LINK (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       IGNORE_LINK  *NbIgnoreLinkList,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_IGNORE_LINK *PF_GET_IGNORE_LINK;
+
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] State Our state
+ */
+typedef VOID F_POST_MAP_TO_AP (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_POST_MAP_TO_AP *PF_POST_MAP_TO_AP;
+
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] State Our state
+ */
+typedef VOID F_CLEAN_MAPS_AFTER_ERROR (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_CLEAN_MAPS_AFTER_ERROR *PF_CLEAN_MAPS_AFTER_ERROR;
+
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in,out] State global state
+ */
+typedef VOID F_NEW_NODE_AND_SOCKET_TABLES (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_NEW_NODE_AND_SOCKET_TABLES *PF_NEW_NODE_AND_SOCKET_TABLES;
+
+/**
+ * Fill in the socket's Node id when a processor is discovered in that socket.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] Node                Node from which a new node was discovered
+ * @param[in] CurrentNodeModule   The current node's module id in it's processor.
+ * @param[in] PackageLink         The package level link from Node to NewNode.
+ * @param[in] NewNode             The new node's id
+ * @param[in] HardwareSocket      If we use the hardware method (preferred), this is the socket of new node.
+ * @param[in] Module              The new node's module id in it's processor.
+ * @param[in] State               our State
+ */
+typedef VOID F_SET_NODE_TO_SOCKET_MAP (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_SET_NODE_TO_SOCKET_MAP *PF_SET_NODE_TO_SOCKET_MAP;
+
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in,out]   State    Keep our buffer handle.
+ *
+ */
+typedef VOID F_NEW_HOP_COUNT_TABLE (
+  IN OUT   STATE_DATA     *State
+  );
+/// Reference to a method.
+typedef F_NEW_HOP_COUNT_TABLE *PF_NEW_HOP_COUNT_TABLE;
+
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ * @HtInterfaceInstances.
+ *
+ * Invoke the CPU component power mgt interface.
+ *
+ * @param[in]    StdHeader    Config for library and services.
+ *
+ * @return Frequency in MHz.
+ *
+ */
+typedef UINT32 F_GET_MIN_NB_CORE_FREQ (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_MIN_NB_CORE_FREQ *PF_GET_MIN_NB_CORE_FREQ;
+
+/**
+ * The HT Interface, feature code uses these methods to get interface parameters.
+ */
+struct _HT_INTERFACE {
+  PF_GET_CPU_2_CPU_PCB_LIMITS GetCpu2CpuPcbLimits;    /**< Method: Get link limits for coherent links. */
+  PF_GET_SKIP_REGANG GetSkipRegang;                   /**< Method: Skip reganging for coherent links. */
+  PF_NEW_HOP_COUNT_TABLE NewHopCountTable;            /**< Method: Get a new hop count table. */
+  PF_GET_OVERRIDE_BUS_NUMBERS GetOverrideBusNumbers;  /**< Method: Control Bus number assignment. */
+  PF_GET_MANUAL_BUID_SWAP_LIST GetManualBuidSwapList; /**< Method: Assign device IDs. */
+  PF_GET_DEVICE_CAP_OVERRIDE GetDeviceCapOverride;    /**< Method: Override Device capabilities. */
+  PF_GET_IO_PCB_LIMITS GetIoPcbLimits;                /**< Method: Get link limits for noncoherent links. */
+  PF_GET_SOCKET_FROM_MAP GetSocketFromMap;            /**< Method: Get the Socket for a node id. */
+  PF_GET_IGNORE_LINK GetIgnoreLink;                   /**< Method: Ignore a link. */
+  PF_POST_MAP_TO_AP PostMapToAp;                      /**< Method: Post Socket and other info to AP cores. */
+  PF_NEW_NODE_AND_SOCKET_TABLES NewNodeAndSocketTables; /**< Method: Get new socket and node maps. */
+  PF_CLEAN_MAPS_AFTER_ERROR CleanMapsAfterError;       /**< Method: Clean up maps for forced 1P on error fall back. */
+  PF_SET_NODE_TO_SOCKET_MAP SetNodeToSocketMap;       /**< Method: Associate a node id with a socket. */
+  PF_GET_MIN_NB_CORE_FREQ GetMinNbCoreFreq;           /**< Method: Get the minimum northbridge frequency */
+};
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the internal Ht Interface.
+ *
+*/
+VOID
+NewHtInterface (
+     OUT   HT_INTERFACE         *HtInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif  /* _HT_INTERFACE_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
new file mode 100755
index 0000000000..35119addc1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
@@ -0,0 +1,260 @@
+/**
+ * @file
+ *
+ * External Interface implementation for coherent features.
+ *
+ * Contains routines for accessing the interface to the client BIOS,
+ * for support only required for coherent features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htInterfaceCoherent.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS}
+ *
+ * For each coherent connection this routine is called once.  Update the frequency
+ * and width if needed for this Link (usually based on board restriction).  This is
+ * used with CPU device capabilities and northbridge limits to compute the default
+ * settings.  The input width and frequency are valid, but do not necessarily reflect
+ * the minimum setting that will be chosen.
+ *
+ * @param[in]     NodeA One Node on which this Link is located
+ * @param[in]     LinkA The Link on this Node
+ * @param[in]     NodeB The other Node on which this Link is located
+ * @param[in]     LinkB The Link on that Node
+ * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
+ * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
+ * @param[in]     State the input data
+ *
+ */
+VOID
+GetCpu2CpuPcbLimits (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  )
+{
+  CPU_TO_CPU_PCB_LIMITS *p;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+
+  ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
+  ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
+
+  SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
+  PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
+  SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
+  PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
+
+  if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) {
+    p = State->HtBlock->CpuToCpuPcbLimitsList;
+
+    while (p->SocketA != HT_LIST_TERMINAL) {
+      if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
+          ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
+           ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
+        // Found a match, update width and frequency
+        *ABLinkWidthLimit = p->ABLinkWidthLimit;
+        *BALinkWidthLimit = p->BALinkWidthLimit;
+        *PcbFreqCap = p->PcbFreqCap;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Skip reganging of subLinks.
+ *
+ * @HtInterfaceMethod{::F_GET_SKIP_REGANG}
+ *
+ * This routine is called whenever two subLinks are both connected to the same CPUs.
+ * Normally, unganged sublinks between the same two CPUs are reganged.  Return true
+ * from this routine to leave the Links unganged.
+ *
+ * @param[in]     NodeA    One Node on which this Link is located
+ * @param[in]     LinkA    The Link on this Node
+ * @param[in]     NodeB    The other Node on which this Link is located
+ * @param[in]     LinkB    The Link on that Node
+ * @param[in]     State     the input data
+ *
+ * @retval        MATCHED      leave Link unganged
+ * @retval        POWERED_OFF  leave link unganged and power off the paired sublink
+ * @retval        UNMATCHED    regang Link automatically
+ */
+FINAL_LINK_STATE
+GetSkipRegang (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  )
+{
+  SKIP_REGANG *p;
+  FINAL_LINK_STATE Result;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+
+  ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
+  ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
+
+  Result = UNMATCHED;
+  SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
+  PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
+  SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
+  PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
+
+  if (State->HtBlock->SkipRegangList != NULL) {
+    p = State->HtBlock->SkipRegangList;
+
+    while (p->SocketA != HT_LIST_TERMINAL) {
+      if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+            ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
+          ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
+            ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
+        // Found a match return final link state
+        Result = p->LinkState;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE}
+ *
+ * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a
+ * known signature.
+ *
+ * @param[in,out]   State    Keep our buffer handle.
+ *
+ */
+VOID
+NewHopCountTable (
+  IN OUT   STATE_DATA     *State
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE);
+  AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr;
+  } else {
+    State->HopCountTable = NULL;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.h
new file mode 100755
index 0000000000..3e3875bba7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.h
@@ -0,0 +1,114 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface for coherent features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_COHERENT_H_
+#define _HT_INTERFACE_COHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ */
+VOID
+GetCpu2CpuPcbLimits (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Skip reganging of subLinks.
+ *
+ */
+FINAL_LINK_STATE
+GetSkipRegang (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ */
+VOID
+NewHopCountTable (
+  IN OUT   STATE_DATA     *State
+  );
+
+#endif  /* _HT_INTERFACE_COHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
new file mode 100755
index 0000000000..3da3550828
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
@@ -0,0 +1,529 @@
+/**
+ * @file
+ *
+ * External Interface implementation, general purpose features.
+ *
+ * Contains routines for implementing the interface to the client BIOS.  This file
+ * includes the interface support which is not removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMultiSocket.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNb.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACEGENERAL_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is PackageLink an Internal Link?
+ *
+ * This is a test for the logical link match codes in the user interface, not a test for
+ * the actual northbridge links.
+ *
+ * @param[in]    PackageLink   The link
+ *
+ * @retval       TRUE          This is an internal link
+ * @retval       FALSE         This is not an internal link
+ */
+BOOLEAN
+IsPackageLinkInternal (
+  IN       UINT8  PackageLink
+  )
+{
+  return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Ignore a Link.
+ *
+ * @HtInterfaceMethod{::F_GET_IGNORE_LINK}
+ *
+ * This routine is called every time a coherent Link is found and then every time a
+ * non-coherent Link from a CPU is found.  Any coherent or non-coherent Link from a
+ * CPU can be ignored and not used for discovery or initialization.  Useful for
+ * connection based systems.
+ *
+ * @note not called for IO device to IO Device Links.
+ *
+ * @param[in]     Node             The Node on which this Link is located
+ * @param[in]     Link             The Link about to be initialized
+ * @param[in]     NbIgnoreLinkList The northbridge default ignore link list
+ * @param[in]     State            the input data
+ *
+ * @retval        MATCHED     ignore this Link and skip it
+ * @retval        POWERED_OFF ignore this link and power it off.
+ * @retval        UNMATCHED   initialize the Link normally
+ */
+FINAL_LINK_STATE
+GetIgnoreLink (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+  IN       IGNORE_LINK     *NbIgnoreLinkList,
+  IN       STATE_DATA      *State
+  )
+{
+  IGNORE_LINK *p;
+  FINAL_LINK_STATE Result;
+  BOOLEAN IsFound;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  Result = UNMATCHED;
+  IsFound = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->IgnoreLinkList != NULL) {
+    p = State->HtBlock->IgnoreLinkList;
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
+        // Found a match return the desired link state.
+        ASSERT (Result < MaxFinalLinkState);
+        Result = p->LinkState;
+        IsFound = TRUE;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // If there wasn't a match in the user interface, see if the northbridge provides one.
+  if (!IsFound && (NbIgnoreLinkList != NULL)) {
+    p = NbIgnoreLinkList;
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
+        // Found a match return the desired link state.
+        ASSERT (Result < MaxFinalLinkState);
+        Result = p->LinkState;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Socket number for a given Node number.
+ *
+ * @HtInterfaceMethod{::F_GET_SOCKET_FROM_MAP}
+ *
+ * Return the id.
+ *
+ * @param[in]     Node    The Node to translate
+ * @param[in]     State   reference to Node to socket map
+ *
+ * @return the socket id
+ *
+ */
+UINT8
+GetSocketFromMap (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  )
+{
+  UINT8 Socket;
+
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  Socket = (*State->NodeToSocketDieMap)[Node].Socket;
+  return Socket;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ * @HtInterfaceMethod{::F_NEW_NODE_AND_SOCKET_TABLES}
+ *
+ * Put the Socket Die Table in heap with a known handle.  Content will be generated as
+ * each node is discovered.
+ *
+ * @param[in,out] State global state
+ */
+VOID
+NewNodeAndSocketTables (
+  IN OUT   STATE_DATA *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  // Allocate heap for the table
+  State->SocketDieToNodeMap = NULL;
+  AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM));
+  AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr;
+    // Initialize shared data structures
+    for (i = 0; i < MAX_SOCKETS; i++) {
+      for (j = 0; j < MAX_DIES; j++) {
+        (*State->SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Allocate heap for the table
+  State->NodeToSocketDieMap = NULL;
+  AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM));
+  AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr;
+    // Initialize shared data structures
+    for (i = 0; i < MAX_NODES; i++) {
+      (*State->NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL;
+      (*State->NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ * @HtInterfaceMethod{::F_GET_MIN_NB_CORE_FREQ}
+ *
+ * Invoke the CPU component power mgt interface.
+ *
+ * @param[in]    StdHeader    Config for library and services.
+ *
+ * @return Frequency in MHz.
+ *
+ */
+UINT32
+GetMinNbCoreFreq (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BOOLEAN Temp;
+  UINT32 Result;
+
+  OptionMultiSocketConfiguration.GetSystemNbCof (&Result, &Temp, StdHeader);
+  return Result;
+}
+
+/**
+ * @page physicalsockethowto Physical Socket Map, How To Create
+ *
+ *  To create a physical system socket map for a platform:
+ *
+ *  - Start at the Node which will be the BSP.
+ *
+ *  - Begin a breadth first enumeration of all the coherent Links between sockets
+ *  by creating a socket structure for each socket connection from the BSP.
+ *  For example, if the BSP is in socket zero and Link one connects to socket two,
+ *  create socket {0, 1, 2}.
+ *
+ *  - When all Links from the BSP are described, go to the first socket connected
+ *  to the BSP and continue the breadth first enumeration.
+ *
+ *  - It should not be necessary to describe the back Links; in the example above, there
+ *  should be no need to create {2, 1, 0} (assuming socket two connects back to
+ *  socket zero on its Link one).
+ *
+ *  - When completed:
+ *
+ *     - Every socket except the BSP's (usually zero) must be listed as a targetSocket,
+ *     at least once.  Some sockets may be listed more than once.
+ *
+ *     - There usually should be at least as many entries as Links. An exception is a
+ *     fully connected system, only the Links from the BSP are needed.
+ *
+ *     - Every socket but the last one in the breadth first order should usually have one
+ *     or more entries listing it as a currentSocket. (The last one has only back Links.)
+ *
+ *  There are no strict assumptions about the ordering of the socket structures.
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update maps between Sockets and Nodes for a specific newly discovered node.
+ *
+ * @HtInterfaceMethod{::F_SET_NODE_TO_SOCKET_MAP}
+ *
+ * There are two methods for providing socket naming of nodes.
+ *
+ * Hardware Method (preferred):  A value strapped in hardware by the board is read and
+ * passed to this routine.
+ *
+ * Software Method:  The current node's socket is looked up, since it was
+ * previously a new node and went through this process. The link is converted to
+ * a package level link.  A user data structure describing the package level
+ * layout of the system is searched for the current node's socket and package link,
+ * and now we know the new node's socket.
+ *
+ * In either case, the Socket, Module to Node map and the Node to Socket, Module
+ * map are updated with the new node, socket, and module.
+ *
+ * Data needed to do this is passed in to the routine as arguments rather than read by this routine,
+ * so that it is not necessary to know a valid temporary route to either node at the time this code runs.
+ *
+ * @param[in] Node           Node from which a new node was discovered
+ * @param[in] CurrentNodeModule  The current node's module id in it's processor.
+ * @param[in] PackageLink    The package link for the current node's link.
+ * @param[in] NewNode        The new node's id
+ * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node.
+ * @param[in] Module         The new node's module id in it's processor.
+ * @param[in] State          our State
+ */
+VOID
+SetNodeToSocketMap (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 SourceSocket;
+  UINT8 TargetSocket;
+  SYSTEM_PHYSICAL_SOCKET_MAP *Map;
+
+  // While this code could be written to recover from a NULL socket map, AGESA cannot function without one.
+  ASSERT (State->SocketDieToNodeMap != NULL);
+
+  if (State->HtBlock->SystemPhysicalSocketMap != NULL) {
+    if (NewNode != 0) {
+      // Find the logical Node from which a new Node was discovered in the Node field of
+      // some socket.  It must already be there, Nodes are assigned ascending.
+      //
+      for (SourceSocket = 0; SourceSocket < MAX_SOCKETS; SourceSocket++) {
+        if ((*State->SocketDieToNodeMap)[SourceSocket][CurrentNodeModule].Node == Node) {
+          break;
+        }
+      }
+      // This ASSERT should be understood as "the Node did not have a match", not as a limit check on SourceSocket.
+      ASSERT (SourceSocket != MAX_SOCKETS);
+
+      // Find the sourceSocket in the CurrentSocket field, for the Link on which a new Node
+      // was discovered.  When we find an entry with that socket and Link number, update the
+      // Node for that socket.
+      //
+      if (IsPackageLinkInternal (PackageLink)) {
+        // Internal Nodes are in the same socket, don't search the physical system map.
+        TargetSocket = SourceSocket;
+      } else {
+        // Find the target socket in the physical system map.
+        Map = State->HtBlock->SystemPhysicalSocketMap;
+        while ((Map->CurrentSocket != 0xFF) &&
+               ((Map->CurrentSocket != SourceSocket) || (Map->CurrentLink != PackageLink))) {
+          Map++;
+        }
+        ASSERT (Map->CurrentSocket != 0xFF);
+        TargetSocket = Map->TargetSocket;
+      }
+    } else {
+      // The BSP (BSN, if you will) has no predecessor node from which it is discovered.
+      TargetSocket = 0;
+    }
+  } else {
+    // Use the hardware method
+    // The hardware strapped socket id is passed to us in this case.
+    TargetSocket = HardwareSocket;
+  }
+  // If the target socket, module is already mapped to something, that's not good.  Socket labeling conflict.
+    // Check that the board is strapped correctly. If not you need a SystemPhysicalSocketMap.  If you have one,
+    // check it for correctness.
+  ASSERT ((*State->SocketDieToNodeMap)[TargetSocket][Module].Node == 0xFF);
+  // Update the map for the rest of agesa
+  (*State->SocketDieToNodeMap)[TargetSocket][Module].Node = NewNode;
+  // and the node to socket map
+  ASSERT (State->NodeToSocketDieMap != NULL);
+  (*State->NodeToSocketDieMap)[NewNode].Socket = TargetSocket;
+  (*State->NodeToSocketDieMap)[NewNode].Die = Module;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ * @HtInterfaceMethod{::F_CLEAN_MAPS_AFTER_ERROR}
+ *
+ * @param[in] State Our state, access to socket, node maps
+ *
+ */
+VOID
+CleanMapsAfterError (
+  IN       STATE_DATA *State
+  )
+{
+  UINTN  Socket;
+  UINTN  Module;
+  UINTN  Node;
+
+  ASSERT (State->NodeToSocketDieMap != NULL);
+  ASSERT (State->SocketDieToNodeMap != NULL);
+
+  // Clear all the socket, module items except for the socket and module containing node zero.
+  for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
+    for (Module = 0; Module < MAX_DIES; Module++) {
+      if (((*State->NodeToSocketDieMap)[0].Socket != Socket) || ((*State->NodeToSocketDieMap)[0].Die != Module)) {
+        (*State->SocketDieToNodeMap)[Socket][Module].Node = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[Socket][Module].LowCore = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[Socket][Module].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Clear all the node items except for node zero.
+  for (Node = 1; Node < MAX_NODES; Node++) {
+    (*State->NodeToSocketDieMap)[Node].Socket = HT_LIST_TERMINAL;
+    (*State->NodeToSocketDieMap)[Node].Die = HT_LIST_TERMINAL;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ * @HtInterfaceMethod{::F_POST_MAP_TO_AP}
+ *
+ * Since Ap's can not view map until after mp communication is established,
+ * provide them with initial context info via a mailbox register. A mailbox
+ * register is one that can be written in PCI space and read in MSR space.
+ *
+ * @param[in] State Our state, access to socket, node maps
+ */
+VOID
+PostMapToAp (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 ModuleType;
+  UINT8 Module;
+  AP_MAILBOXES ApMailboxes;
+  UINT8 Node;
+  UINT32 Degree;
+  AGESA_STATUS CalledStatus;
+
+  // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed.
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle);
+
+  ASSERT (State->Fabric != NULL);
+  Degree = 0;
+  // Compute the degree of the system by finding the maximum degree of any node.
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    if (State->Fabric->SysDegree[Node] > Degree) {
+      Degree = State->Fabric->SysDegree[Node];
+    }
+  }
+  // Post the information on all nodes.
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    ModuleType = 0;
+    Module = 0;
+    State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb);
+    ApMailboxes.ApMailInfo.Info = 0;
+    ApMailboxes.ApMailInfo.Fields.Node = Node;
+    ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State);
+    ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType;
+    ApMailboxes.ApMailInfo.Fields.Module = Module;
+    ApMailboxes.ApMailExtInfo.Info = 0;
+    ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree;
+    // other fields of the extended info are used during ap init, and will be initialized at that time.
+    State->Nb->PostMailbox (Node, ApMailboxes, State->Nb);
+  }
+  // Now that the mailboxes have been initialized, cache the info on the BSC.  The APs
+  // will cache during heap initialization.
+  CacheApMailbox (State->ConfigHandle);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.h
new file mode 100755
index 0000000000..f13dc545ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.h
@@ -0,0 +1,160 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface, general purpose features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * external interface.
+ *
+ * This file includes the interface support which is not removed with
+ * various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_GENERAL_H_
+#define _HT_INTERFACE_GENERAL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Is PackageLink an Internal Link?
+ */
+BOOLEAN
+IsPackageLinkInternal (
+  IN       UINT8  PackageLink
+  );
+
+/**
+ * Get the Socket number for a given Node number.
+ *
+ */
+UINT8
+GetSocketFromMap (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  );
+
+/**
+ * Ignore a Link.
+ *
+ */
+FINAL_LINK_STATE
+GetIgnoreLink (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       IGNORE_LINK  *NbIgnoreLinkList,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ */
+VOID
+NewNodeAndSocketTables (
+  IN OUT   STATE_DATA *State
+  );
+
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ */
+UINT32
+GetMinNbCoreFreq (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/**
+ * Fill in the socket's Node id when a processor is discovered in that socket.
+ *
+ */
+VOID
+SetNodeToSocketMap (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  );
+
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ */
+VOID
+CleanMapsAfterError (
+  IN       STATE_DATA *State
+  );
+
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ */
+VOID
+PostMapToAp (
+  IN       STATE_DATA *State
+  );
+
+#endif  /* _HT_INTERFACE_GENERAL_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
new file mode 100755
index 0000000000..07909bef8b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
@@ -0,0 +1,390 @@
+/**
+ * @file
+ *
+ * External Interface implementation for non-coherent features.
+ *
+ * Contains routines for accessing the interface to the client BIOS,
+ * for non-coherent features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceNonCoherent.h"
+#include "htNb.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACENONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_ZERO_32 ((UINT32)0)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Manual BUID assignment list.
+ *
+ * @HtInterfaceMethod{::F_GET_MANUAL_BUID_SWAP_LIST}
+ *
+ * This routine is called every time a non-coherent chain is processed.  BUID
+ * assignment may be controlled explicitly on a non-coherent chain. Swaps controls
+ * the BUID assignment and FinalIds provides the device to device Linking.  Device
+ * orientation can be detected automatically, or explicitly.  See documentation for
+ * more details.
+ *
+ * If a manual swap list is not supplied, automatic non-coherent init assigns BUIDs
+ * starting at 1 and incrementing sequentially based on each device's unit count.
+ *
+ * @param[in]    Node    The Node on which this chain is located
+ * @param[in]    Link    The Link on the host for this chain
+ * @param[out]   List    supply a pointer to a list.
+ *                       List is NOT valid unless routine returns TRUE.
+ * @param[in]    State   the input data
+ *
+ * @retval      TRUE     use a manual list
+ * @retval      FALSE    initialize the Link automatically
+ */
+BOOLEAN
+GetManualBuidSwapList (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  )
+{
+  MANUAL_BUID_SWAP_LIST *p;
+  BOOLEAN result;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (List != NULL));
+
+  result = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->ManualBuidSwapList != NULL) {
+    p = State->HtBlock->ManualBuidSwapList;
+
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
+        // Found a match implies TRUE, ignore the Link
+        result = TRUE;
+        *List = &(p->SwapList);
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // List is not valid if Result is FALSE.
+  return result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Override capabilities of a device.
+ *
+ * @HtInterfaceMethod{::F_GET_DEVICE_CAP_OVERRIDE}
+ *
+ * This routine is called once for every Link on every IO device.  Update the width
+ * and frequency capability if needed for this device.  This is used along with
+ * device capabilities, the limit call backs, and northbridge limits to compute the
+ * default settings.  The components of the device's PCI config address are provided,
+ * so its settings can be consulted if need be. The input width and frequency are the
+ * reported device capabilities.
+ *
+ * @param[in]     HostNode      The Node on which this chain is located
+ * @param[in]     HostLink      The Link on the host for this chain
+ * @param[in]     Depth         The Depth in the I/O chain from the Host
+ * @param[in]     PciAddress    The Device's PCI config address (for callout)
+ * @param[in]     DevVenId      The Device's PCI Vendor + Device ID (offset 0x00)
+ * @param[in]     Revision      The Device's PCI Revision
+ * @param[in]     Link          The Device's Link number (0 or 1)
+ * @param[in,out] LinkWidthIn   modify to change the Link Width In
+ * @param[in,out] LinkWidthOut  modify to change the Link Width Out
+ * @param[in,out] FreqCap       modify to change the Link's frequency capability
+ * @param[in,out] Clumping      modify to change unit id clumping capability
+ * @param[in]     State         the input data and config header
+ *
+ */
+VOID
+GetDeviceCapOverride (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  )
+{
+  DEVICE_CAP_OVERRIDE *p;
+  UINT8 HostSocket;
+  UINT8 PackageLink;
+  DEVICE_CAP_CALLOUT_PARAMS CalloutParams;
+  AGESA_STATUS CalloutStatus;
+
+  ASSERT ((HostNode < MAX_NODES) && (Depth < 32) && ((Link == 0) || (Link == 1)));
+
+  HostSocket = State->HtInterface->GetSocketFromMap (HostNode, State);
+  PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
+
+  if (State->HtBlock->DeviceCapOverrideList != NULL) {
+    p = State->HtBlock->DeviceCapOverrideList;
+
+    while (p->HostSocket != HT_LIST_TERMINAL) {
+      if (((p->HostSocket == HostSocket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
+          ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
+          ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == Link) || (p->Link == HT_LIST_MATCH_ANY)) &&
+          // Found a potential match. Check the additional optional matches.
+          ((p->Options.IsCheckDevVenId == 0) || (p->DevVenId == DevVenId)) &&
+          ((p->Options.IsCheckRevision == 0) || (p->Revision == Revision))) {
+        //
+        // Found a match.  Check what override actions are desired.
+        // Unlike the PCB limit routines, which handle the info returned,
+        // deviceCapOverride is actually overriding the settings, so we need
+        // to check that the field actually has an update.
+        // The Callout is a catch all for situations the data is not up to handling.
+        // It is expected, but not enforced, that either the data overrides are used,
+        // or the callout is used, rather than both.
+        //
+        if (p->Options.IsOverrideWidthIn != 0) {
+          *LinkWidthIn = p->LinkWidthIn;
+        }
+        if (p->Options.IsOverrideWidthOut != 0) {
+          *LinkWidthOut = p->LinkWidthOut;
+        }
+        if (p->Options.IsOverrideFreq != 0) {
+          *FreqCap = p->FreqCap;
+        }
+        if (p->Options.IsOverrideClumping != 0) {
+          *Clumping = p->Clumping;
+        }
+        if (p->Options.IsDoCallout != 0) {
+          //
+          // Pass the actual info being matched, not the matched struct data.
+          // This callout is expected to be built in as part of the options file, and does not use the
+          // callout interface, even though we use the consistent interface declaration for the routine.
+          // So, the first two int parameters have no meaning in this case.
+          // It is not meaningful for the callout to have any status but Success.
+          //
+          CalloutParams.HostSocket = HostSocket;
+          CalloutParams.HostLink = PackageLink;
+          CalloutParams.Depth = Depth;
+          CalloutParams.DevVenId = DevVenId;
+          CalloutParams.Revision = Revision;
+          CalloutParams.Link = Link;
+          CalloutParams.PciAddress = PciAddress;
+          CalloutParams.LinkWidthIn = LinkWidthIn;
+          CalloutParams.LinkWidthOut = LinkWidthOut;
+          CalloutParams.FreqCap = FreqCap;
+          CalloutParams.Clumping = Clumping;
+          CalloutParams.StdHeader = *((AMD_CONFIG_PARAMS *) (State->ConfigHandle));
+          CalloutStatus = p->Callout (UNUSED_ZERO_32, UNUSED_ZERO_32, (VOID *) &CalloutParams);
+          ASSERT (CalloutStatus == AGESA_SUCCESS);
+        }
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get limits for non-coherent Links.
+ *
+ * @HtInterfaceMethod{::F_GET_IO_PCB_LIMITS}
+ *
+ * For each non-coherent connection this routine is called once.  Update the
+ * frequency and width if needed for this Link (usually based on board restriction).
+ * This is used with device capabilities, device overrides, and northbridge limits to
+ * compute the default settings. The input width and frequency are valid, but do not
+ * necessarily reflect the minimum setting that will be chosen.
+ *
+ * @param[in]     HostNode                   The Node on which this Link is located
+ * @param[in]     HostLink                   The Link about to be initialized
+ * @param[in]     Depth                      The Depth in the I/O chain from the Host
+ * @param[in,out] DownstreamLinkWidthLimit   modify to change the Link Width In
+ * @param[in,out] UpstreamLinkWidthLimit     modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap                 modify to change the Link's frequency capability
+ * @param[in]     State                      the input data
+ */
+VOID
+GetIoPcbLimits (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  )
+{
+  IO_PCB_LIMITS *p;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((HostNode < MAX_NODES) && (HostLink < MAX_NODES));
+
+  Socket = State->HtInterface->GetSocketFromMap (HostNode, State);
+  PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
+
+  if (State->HtBlock->IoPcbLimitsList != NULL) {
+    p = State->HtBlock->IoPcbLimitsList;
+
+    while (p->HostSocket != HT_LIST_TERMINAL) {
+      if (((p->HostSocket == Socket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
+          ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
+          ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY))) {
+        // Found a match, return the override info
+        *DownstreamLinkWidthLimit = p->DownstreamLinkWidthLimit;
+        *UpstreamLinkWidthLimit = p->UpstreamLinkWidthLimit;
+        *PcbFreqCap = p->PcbFreqCap;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Manually control bus number assignment.
+ *
+ * @HtInterfaceMethod{::F_GET_OVERRIDE_BUS_NUMBERS}
+ *
+ * This routine is called every time a non-coherent chain is processed.  If a system
+ * can not use the auto Bus numbering feature for non-coherent chain bus assignments,
+ * this routine can provide explicit control.  For each chain, provide the bus number
+ * range to use.
+ *
+ * The outputs SecBus and SubBus are not valid unless this routine returns TRUE
+ *
+ * @param[in]     Node      The Node on which this chain is located
+ * @param[in]     Link      The Link on the host for this chain
+ * @param[out]    SecBus    Secondary Bus number for this non-coherent chain
+ * @param[out]    SubBus    Subordinate Bus number
+ * @param[in]     State     the input data
+ *
+ * @retval        TRUE      this routine is supplying the bus numbers.
+ * @retval        FALSE     use auto Bus numbering, bus outputs not valid.
+ */
+BOOLEAN
+GetOverrideBusNumbers (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  )
+{
+  OVERRIDE_BUS_NUMBERS *p;
+  BOOLEAN result;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  result = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->OverrideBusNumbersList != NULL) {
+    p = State->HtBlock->OverrideBusNumbersList;
+
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
+        // Found a match, return the bus overrides
+        *SecBus = p->SecBus;
+        *SubBus = p->SubBus;
+        ASSERT (*SubBus > *SecBus);
+        result = TRUE;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // SecBus, SubBus are not valid if Result is FALSE.
+  return result;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h
new file mode 100755
index 0000000000..822f4c56ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h
@@ -0,0 +1,137 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface, for non-coherent features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_NONCOHERENT_H_
+#define _HT_INTERFACE_NONCOHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Manually control bus number assignment.
+ *
+ */
+BOOLEAN
+GetOverrideBusNumbers (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get Manual BUID assignment list.
+ *
+ */
+BOOLEAN
+GetManualBuidSwapList (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  );
+
+/**
+ * Override capabilities of a device.
+ *
+ */
+
+VOID
+GetDeviceCapOverride (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  );
+
+/**
+ * Get limits for non-coherent Links.
+ *
+ */
+VOID
+GetIoPcbLimits (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+
+#endif  /* _HT_INTERFACE_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
new file mode 100755
index 0000000000..47aff2084f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
@@ -0,0 +1,536 @@
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTMAIN_FILECODE
+#define APIC_Base_BSP    8
+#define APIC_Base        0x1b
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update maps with the core range for each module.
+ *
+ * Cores are numbered relative to a Processor, but sometimes there is a need to know the
+ * starting and ending core ids on a particular node.  This same info is also useful for
+ * supporting the Core count on a node other than the one currently executing.
+ *
+ * For each Processor, get the core count of each node using the family specific PCI core count
+ * interface. The order of cores in a processor, and whether it is special for the BSP is family
+ * specific.  But whether the processor orders core ids by module or node, iterate in the right
+ * order and use the counts to determine each start and end range.
+ *
+ * @param[in]   State    number of Nodes discovered.
+*/
+VOID
+STATIC
+UpdateCoreRanges (
+  IN       STATE_DATA    *State
+    )
+{
+  UINT8 Node;
+  UINT8 ProcessorCores;
+  UINT8 ModuleCoreCount[MAX_DIES];
+  UINT8 Socket;
+  UINT8 Module;
+
+  ASSERT (State->SocketDieToNodeMap != NULL);
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
+    // Is a Processor present in Socket?
+    if ((*State->SocketDieToNodeMap)[Socket][0].Node != HT_LIST_TERMINAL) {
+      // Get all the Module core counts for this processor
+      // Note that the core counts are 1 based counts.
+      for (Module = 0; Module < MAX_DIES; Module++) {
+        if ((*State->SocketDieToNodeMap)[Socket][Module].Node != HT_LIST_TERMINAL) {
+          ModuleCoreCount[Module] = State->Nb->GetNumCoresOnNode ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
+        } else {
+          ModuleCoreCount[Module] = 0;
+        }
+      }
+      // Determine the core ordering rule for this processor.
+      if ((((*State->NodeToSocketDieMap)[0].Socket == Socket) && State->Nb->IsOrderBSPCoresByNode) ||
+          (!State->Nb->IsOrderCoresByModule)) {
+        // Order core ranges on this processor by Node Id.
+        ProcessorCores = 0;
+        for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
+          // Is this node a module in this processor?
+          if ((*State->NodeToSocketDieMap)[Node].Socket == Socket) {
+            Module = (*State->NodeToSocketDieMap)[Node].Die;
+            if (ModuleCoreCount[Module] != 0) {
+              (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
+              (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
+              ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
+            }
+          }
+        }
+      } else {
+        // Order core ranges in this processor by Module Id.
+        ProcessorCores = 0;
+        for (Module = 0; Module < MAX_DIES; Module++) {
+          if (ModuleCoreCount[Module] != 0) {
+            (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
+            (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
+            ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Complete the coherent init with any system level initialization.
+ *
+ * Find the total number of cores and update the number of Nodes and cores in all cpus.
+ * Limit cpu config access to installed cpus.
+ *
+ * @param[in]   State    number of Nodes discovered.
+*/
+VOID
+STATIC
+FinalizeCoherentInit (
+  IN       STATE_DATA    *State
+    )
+{
+  UINT8 Node;
+  UINT8 TotalCores;
+
+  TotalCores = 0;
+
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    TotalCores = TotalCores + State->Nb->GetNumCoresOnNode (Node, State->Nb);
+  }
+
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->SetTotalNodesAndCores (Node, State->NodesDiscovered + 1, TotalCores, State->Nb);
+  }
+
+  // Set all nodes to limit config space based on node count, after all nodes have a valid count.
+  // (just being cautious, probably we could combine the loops.)
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->LimitNodes (Node, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the coherent fabric.
+ *
+ * Perform discovery and initialization of the coherent fabric, for builds including
+ * support for multiple coherent nodes.
+ *
+ * @param[in]   State   global state
+ */
+VOID
+STATIC
+CoherentInit (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 ModuleType;
+  UINT8 Module;
+  UINT8 HardwareSocket;
+  COHERENT_FABRIC Fabric;
+
+  // Because Node 0, the BSP, is not discovered, initialize info about it specially here.
+  // Allocate Socket Die Map.
+  // While the BSP is always capable of being the only processor in the system, call the
+  // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system
+  // capability. We don't care to check the return value.
+  //
+  State->Fabric = &Fabric;
+  State->NodesDiscovered = 0;
+  State->TotalLinks = 0;
+  State->SysMpCap = MAX_NODES;
+  State->Nb->IsExceededCapable (0, State, State->Nb);
+  HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
+  ModuleType = 0;
+  Module = 0;
+  State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb);
+  // No predecessor info for BSP, so pass 0xFF for those parameters.
+  State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State);
+
+  // Initialize system state data structures
+  for (i = 0; i < MAX_NODES; i++) {
+    State->Fabric->SysDegree[i] = 0;
+    for (j = 0; j < MAX_NODES; j++) {
+      State->Fabric->SysMatrix[i][j] = 0;
+    }
+  }
+
+  //
+  // Call the coherent init features
+  //
+
+  // Discovery
+  State->HtFeatures->CoherentDiscovery (State);
+  State->HtInterface->PostMapToAp (State);
+  // Topology matching and Routing
+  AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle);
+  State->HtFeatures->LookupComputeAndLoadRoutingTables (State);
+  State->HtFeatures->MakeHopCountTable (State);
+
+  // UpdateCoreRanges requires the other maps to be initialized, and the node count set.
+  FinalizeCoherentInit (State);
+  UpdateCoreRanges (State);
+  State->Fabric = NULL;
+}
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                             Algorithms                              ***
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the non-coherent fabric.
+ *
+ * Begin with the Compat Link on the BSP, then find and initialize all other
+ * non-coherent chains.
+ *
+ * @param[in]   State    our global state
+ */
+VOID
+STATIC
+NcInit (
+  IN       STATE_DATA    *State
+  )
+{
+  UINT8 Node;
+  UINT8 Link;
+  UINT8 CompatLink;
+  FINAL_LINK_STATE FinalLinkState;
+
+  // Initialize the southbridge chain.
+  State->AutoBusCurrent = State->HtBlock->AutoBusStart;
+  State->UsedCfgMapEntries = 0;
+  CompatLink = State->Nb->ReadSouthbridgeLink (State->Nb);
+  State->HtFeatures->ProcessLink (0, CompatLink, TRUE, State);
+
+  // Find and initialize all other non-coherent chains.
+  for (Node = 0; Node <= State->NodesDiscovered; Node++) {
+    for (Link = 0; Link < State->Nb->MaxLinks; Link++) {
+      // Skip the Link, if any of these tests indicate
+      FinalLinkState = State->HtInterface->GetIgnoreLink (Node, Link, State->Nb->DefaultIgnoreLinkList, State);
+      if (FinalLinkState == UNMATCHED) {
+        if ( !((Node == 0) && (Link == CompatLink))) {
+          if ( !(State->Nb->ReadTrueLinkFailStatus (Node, Link, State, State->Nb))) {
+            if (State->Nb->VerifyLinkIsNonCoherent (Node, Link, State->Nb)) {
+              State->HtFeatures->ProcessLink (Node, Link, FALSE, State);
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Optimize Link Features.
+ *
+ * Based on Link capabilities, apply optimization rules to come up with the best
+ * settings, including several external limit decision from the interface. This includes
+ * handling of subLinks.  Finally, after the port list data is updated, set the hardware
+ * state for all Links.
+ *
+ * @param[in] State our global state
+ */
+VOID
+STATIC
+LinkOptimization (
+  IN       STATE_DATA *State
+  )
+{
+  AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle);
+  State->HtFeatures->GatherLinkData (State);
+
+  AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle);
+  State->HtFeatures->RegangLinks (State);
+
+  AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle);
+  State->HtFeatures->SelectOptimalWidthAndFrequency (State);
+
+  // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing
+  // so check this after doing the sublinks.
+  AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle);
+  State->HtFeatures->SubLinkRatioFixup (State);
+  if (State->HtFeatures->IsCoherentRetryFixup (State)) {
+    // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again.
+    State->HtFeatures->SubLinkRatioFixup (State);
+  }
+
+  AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle);
+  State->HtFeatures->SetLinkData (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Handle system and performance tunings.
+ *
+ * Including traffic distribution, fifo and
+ * buffer tuning that can't be placed in the register table,
+ * and special config tunings.
+ *
+ * @param[in] State    Total Nodes, port list data
+ */
+VOID
+STATIC
+Tuning (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 Node;
+
+  // See if traffic distribution can be done and do it if so.
+  //
+  AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle);
+  State->HtFeatures->TrafficDistribution (State);
+
+  // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table.
+  //
+  AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle);
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->BufferOptimizations (Node, State, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map.
+ * The mapping is filled in by reading the AP Mailboxes from PCI config on each node.
+ *
+ * @param[in]    State    global state, input data
+ *
+ */
+VOID
+STATIC
+InitApMaps (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 Node;
+  AP_MAIL_INFO NodeApMailBox;
+
+  // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug.
+  ASSERT (State->SocketDieToNodeMap != NULL);
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
+    NodeApMailBox = State->Nb->RetrieveMailbox (Node, State->Nb);
+    (*State->SocketDieToNodeMap)[NodeApMailBox.Fields.Socket][NodeApMailBox.Fields.Module].Node = Node;
+    (*State->NodeToSocketDieMap)[Node].Socket = (UINT8)NodeApMailBox.Fields.Socket;
+    (*State->NodeToSocketDieMap)[Node].Die = (UINT8)NodeApMailBox.Fields.Module;
+  }
+  // This requires the other maps to be initialized.
+  UpdateCoreRanges (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is the currently running core the BSC?
+ *
+ * Determine whether the init steps for BSC or AP core should be run.
+ *
+ * @param[in]    State    global state, input data
+ *
+ * @retval       TRUE    This is the boot core.
+ * @retval       FALSE   This is not the boot core.
+ */
+BOOLEAN
+STATIC
+IsBootCore (
+  IN       STATE_DATA    *State
+  )
+{
+  UINT64 Value;
+
+  LibAmdMsrRead (APIC_Base, &Value, State->ConfigHandle);
+
+  return ((BOOLEAN) (((UINT32) (Value & 0xFFFFFFFF) & ((UINT32)1 << APIC_Base_BSP)) != 0));
+}
+
+/***************************************************************************
+ ***                            HT Initialize                             ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  )
+{
+  STATE_DATA State;
+  NORTHBRIDGE Nb;
+  HT_FEATURES HtFeatures;
+  HT_INTERFACE HtInterface;
+  AGESA_STATUS DeallocateStatus;
+  AP_MAIL_INFO ApMailboxInfo;
+  UINT8 ApNode;
+
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  State.HtBlock = AmdHtInterface;
+  State.ConfigHandle = StdHeader;
+  State.PlatformConfiguration = PlatformConfiguration;
+
+  // Get the current HT internal interface (to HtBlock data)
+  NewHtInterface (&HtInterface, State.ConfigHandle);
+  State.HtInterface = &HtInterface;
+
+  // Get the current HT Feature Set
+  NewHtFeatures (&HtFeatures, State.ConfigHandle);
+  State.HtFeatures = &HtFeatures;
+
+  // Initialize from static options
+  State.IsUsingRecoveryHt = OptionHtConfiguration.IsUsingRecoveryHt;
+  State.IsSetHtCrcFlood = OptionHtConfiguration.IsSetHtCrcFlood;
+  State.IsUsingUnitIdClumping = OptionHtConfiguration.IsUsingUnitIdClumping;
+
+  // Initialize for status and event output
+  State.MaxEventClass = AGESA_SUCCESS;
+
+  // Allocate permanent heap structs that are interfaces to other AGESA services.
+  State.HtInterface->NewNodeAndSocketTables (&State);
+
+  if (IsBootCore (&State)) {
+    AGESA_TESTPOINT (TpProcHtEntry, State.ConfigHandle);
+    // Allocate Bsp only interface heap structs.
+    State.HtInterface->NewHopCountTable (&State);
+    // Allocate heap for our temporary working space.
+    AllocHeapParams.RequestedBufferSize = (sizeof (PORT_DESCRIPTOR) * (MAX_PLATFORM_LINKS * 2));
+    AllocHeapParams.BufferHandle = HT_STATE_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, State.ConfigHandle) == AGESA_SUCCESS) {
+      State.PortList = (PORT_LIST)AllocHeapParams.BufferPtr;
+      // Create the BSP's northbridge.
+      NewNorthBridge (0, &State, &Nb);
+      State.Nb = &Nb;
+
+      CoherentInit (&State);
+      NcInit (&State);
+      LinkOptimization (&State);
+      Tuning (&State);
+
+      DeallocateStatus = HeapDeallocateBuffer (HT_STATE_DATA_HANDLE, State.ConfigHandle);
+      ASSERT (DeallocateStatus == AGESA_SUCCESS);
+      AGESA_TESTPOINT (TpProcHtDone, State.ConfigHandle);
+    } else {
+      ASSERT (FALSE);
+      State.MaxEventClass = AGESA_ERROR;
+      // Cannot Log entry due to heap allocate failed.
+    }
+  } else {
+    // Do the AP HT Init, which produces Node and Socket Maps for the AP's use.
+    AGESA_TESTPOINT (TpProcHtApMapEntry, State.ConfigHandle);
+    GetApMailbox (&ApMailboxInfo.Info, State.ConfigHandle);
+    ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
+    ApNode = (UINT8)ApMailboxInfo.Fields.Node;
+    NewNorthBridge (ApNode, &State, &Nb);
+    State.Nb = &Nb;
+    InitApMaps (&State);
+    AGESA_TESTPOINT (TpProcHtApMapDone, State.ConfigHandle);
+  }
+  return State.MaxEventClass;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
new file mode 100755
index 0000000000..85fda1a11e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
@@ -0,0 +1,240 @@
+/**
+ * @file
+ *
+ * Construct a northbridge interface for a Node.
+ *
+ * Handle build options and run-time detection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "CommonReturns.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_HT_HTNB_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+
+/**
+ * Initial construction data for no HT Northbridge.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
+{
+  1,
+  (PF_WRITE_ROUTING_TABLE)CommonVoid,
+  (PF_WRITE_NODEID)CommonVoid,
+  (PF_READ_DEFAULT_LINK)CommonReturnZero8,
+  (PF_ENABLE_ROUTING_TABLES)CommonVoid,
+  (PF_DISABLE_ROUTING_TABLES)CommonVoid,
+  (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
+  (PF_READ_TOKEN)CommonReturnZero8,
+  (PF_WRITE_TOKEN)CommonVoid,
+  (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
+  (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
+  (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
+  (PF_STOP_LINK)CommonVoid,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
+  (PF_READ_SB_LINK)CommonReturnZero8,
+  (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse,
+  (PF_SET_CONFIG_ADDR_MAP)CommonVoid,
+  (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32,
+  (PF_GATHER_LINK_FEATURES)CommonVoid,
+  (PF_SET_LINK_REGANG)CommonVoid,
+  (PF_SET_LINK_FREQUENCY)CommonVoid,
+  (PF_SET_LINK_UNITID_CLUMPING)CommonVoid,
+  (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
+  (PF_BUFFER_OPTIMIZATIONS)CommonVoid,
+  (PF_GET_NUM_CORES_ON_NODE)CommonReturnZero8,
+  (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid,
+  (PF_GET_NODE_COUNT)CommonReturnZero8,
+  (PF_LIMIT_NODES)CommonVoid,
+  (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse,
+  (PF_GET_NEXT_LINK)CommonReturnZero32,
+  (PF_GET_PACKAGE_LINK)CommonReturnZero8,
+  (PF_MAKE_LINK_BASE)CommonReturnZero32,
+  (PF_GET_MODULE_INFO)CommonVoid,
+  (PF_POST_MAILBOX)CommonVoid,
+  (PF_RETRIEVE_MAILBOX)CommonReturnZero32,
+  (PF_GET_SOCKET)CommonReturnZero8,
+  0,
+  0,
+  0,
+  TRUE,
+  TRUE,
+  0,
+  NULL,
+  0,
+  NULL,
+  (PF_MAKE_KEY)CommonReturnZero64,
+  NULL
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make a compatibility key.
+ *
+ * @HtNbMethod{::F_MAKE_KEY}
+ *
+ * Private routine to northbridge code.
+ * Create a key which can be used to determine whether a Node is compatible with
+ * the discovered configuration so far.  Currently, that means the family,
+ * extended family of the new Node are the same as the BSP's.  Family specific
+ * implementations can add whatever else is necessary.
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @return the key
+ */
+UINT64
+MakeKey (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+  UINT32 RawCpuId;
+  PCI_ADDR Reg;
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CPUID_3XFC);
+
+  LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, Nb->ConfigHandle);
+  GetLogicalIdFromCpuid (RawCpuId, &LogicalId, Nb->ConfigHandle);
+  return LogicalId.Family;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Construct a new northbridge.
+ *
+ * This routine encapsulates knowledge of how to tell significant differences between
+ * families of supported northbridges and what routines can be used in common and
+ * which are unique.  A fully populated northbridge interface is provided by Nb.
+ *
+ * @param[in]     Node    create a northbridge interface for this Node.
+ * @param[in]     State   global state
+ * @param[out]    Nb      the caller's northbridge structure to initialize.
+ */
+VOID
+NewNorthBridge (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+     OUT   NORTHBRIDGE *Nb
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+  UINT64  Match;
+  UINT32 RawCpuId;
+  PCI_ADDR Reg;
+  NORTHBRIDGE **InitializerInstance;
+
+  // Start with enough of the key to identify the northbridge interface
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CPUID_3XFC);
+  LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle);
+  GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle);
+  Match = LogicalId.Family;
+
+  // Test each Northbridge interface in turn looking for a match.
+  // Use it to Init the Nb struct if a match is found.
+  //
+  ASSERT (OptionHtConfiguration.HtOptionFamilyNorthbridgeList != NULL);
+  InitializerInstance = (NORTHBRIDGE **) (OptionHtConfiguration.HtOptionFamilyNorthbridgeList);
+  while (*InitializerInstance != NULL) {
+    if ((Match & (*InitializerInstance)->CompatibleKey) != 0) {
+      LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle);
+      break;
+    }
+    InitializerInstance++;
+  }
+  // There must be an available northbridge implementation.
+  ASSERT (*InitializerInstance != NULL);
+
+  // Set the config handle for passing to the library.
+  Nb->ConfigHandle = State->ConfigHandle;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h
new file mode 100755
index 0000000000..1e0b29b738
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h
@@ -0,0 +1,1065 @@
+/**
+ * @file
+ *
+ * HT NorthBridge header
+ *
+ * Defines the interface to the HT NorthBridge module for use by other internal
+ * HT modules.  This is not a wrapper or external interface, "public" in the
+ * comments below is used in the class definition style and refers to HT client
+ * modules only ("private" being for use only by the HT NB module itself).
+ *
+ * It is expected that there will be multiple northbridge implementation files all
+ * conforming to this common interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NB_H_
+#define _HT_NB_H_
+
+/**
+ * @page htimplnb HT Northbridge Implementation Guide
+ *
+ * The HT Northbridge provides access to the Northbridge hardware, in a manner that
+ * isolates calling code from knowledge about the hardware implementation or which
+ * features are supported in the current build.  This is the mechanism in the HT code for
+ * supporting new Family or Model northbridges, as well as the means for supporting
+ * multiple northbridges in a single build or mixed revision northbridge sets.
+ *
+ * @par Adding a Method to the Northbridge
+ *
+ * To add a new method to the Northbridge, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same
+ *     name as the method table item, but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
+ *   </ul>
+ *
+ * <li> One of the parameters to @b all northbridge Methods is @b required to be a
+ *   reference to its current northbridge object.  By convention, this is the
+ *   last parameter.
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtNbInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::NORTHBRIDGE struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an Instance of a Northbridge method.
+ *
+ * To implement an instance of a method for a specific feature follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the Method typedef.
+ *   - If the Method implementation is common to all families, use the northbridge file
+ *   for the function area, for example, add a new coherent initialization support method to the
+ *   coherent northbridge file.
+ *   - If the Method implementation is unique to each supported northbridge, use the
+ *   family specific file for that function area (create it, if it doesn't already exist).
+ *   The family specific files have the same name as the common one suffixed with "FamNN",
+ *   or "FamNNRevX" if for a model or revision.
+ *
+ * - Name the function MethodName().  If Family specific, FamNNMethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtNbMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other northbridge routines or data as part of the method implementation,
+ *   the function must use Nb->OtherMethod().  Do not directly access other northbridge
+ *   routines, because in the table there may be overrides or this routine may be shared by
+ *   multiple configurations.
+ *
+ * - Add the instance, or the correct family specific instance, to the ::NORTHBRIDGE instances
+ *   used by the northbridge constructor.
+ *
+ * - If a northbridge does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Making common Northbridge Methods.
+ *
+ * In some cases, Northbridge methods can easily have a common implementation because the hardware
+ * is very compatible or is even standard.  In other cases, where processor family northbridges
+ * differ in their implementation, it may be possible to provide a single, common method
+ * implementation.  This can be accomplished by adding Northbridge data members.
+ *
+ * For example, a bit position or bit field mask can be used to accommodate different bit placement or size.
+ * Another example, a small table can be used to translate index values from a common set
+ * to specific sets.
+ *
+ * The Northbridge Method Instance must use its NORTHBRIDGE reference parameter to access
+ * private data members.
+ *
+ * @par Invoking HT Northbridge Methods.
+ *
+ * Each unique northbridge is constructed based on matching the current northbridge.
+ * @n @code
+ *   NORTHBRIDGE Nb;
+ *   // Create the BSP's northbridge.
+ *   NewNorthBridge (0, State, &Nb);
+ *   State->Nb = &Nb;
+ * @endcode
+ *
+ * The following example shows how to invoke a Northbridge method.
+ * @n @code
+ *   State->Nb->MethodName (State->Nb);
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/** Use a macro to convert a Node number to a PCI device.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 makePCIDeviceFromNode(UINT8 Node);
+ */
+#define MakePciDeviceFromNode(Node)             \
+  ((UINT8) (24 + (Node)))
+
+/** Use a macro to convert a Node number to a PCI bus.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 MakePciBusFromNode(UINT8 Node);
+ */
+#define MakePciBusFromNode(Node)                \
+  ((UINT8) (0))
+
+/** Use a macro to convert a Node number to a PCI Segment.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 MakePciSegmentFromNode(UINT8 Node);
+ */
+#define MakePciSegmentFromNode(Node)            \
+  ((UINT8) (0))
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Status for iterating through internal (if supported) and external links.
+ */
+typedef enum {
+  LinkIteratorEnd,         ///< This is the end of all links, no valid link.
+  LinkIteratorExternal,    ///< The next link (the one we got on this call) is an external link.
+  LinkIteratorInternal,    ///< The next link (the one we got on this call) is an internal link.
+  LinkIteratorMax          ///< For bounds checking and limit only.
+} LINK_ITERATOR_STATUS;
+
+#define LINK_ITERATOR_BEGIN 0xFF
+
+/**
+ * Write a temporary Route.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node The node on which to set a temporary route
+ * @param[in] Target A route to this node, which route table entry is to be set
+ * @param[in] Link The link which routes to the target node
+ * @param[in] Nb This northbridge
+ */
+typedef VOID F_WRITE_ROUTING_TABLE (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_ROUTING_TABLE *PF_WRITE_ROUTING_TABLE;
+
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     NodeID the new value for NodeID
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_WRITE_NODEID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_NODEID *PF_WRITE_NODEID;
+
+/**
+ * Read the Default Link
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     Nb     this northbridge
+ *
+ * @return The HyperTransport Link where the request to
+ *        read the default Link came from.  Since this code is running on the BSP,
+ *        this should be the Link pointing back towards the BSP.
+ */
+typedef UINT8 F_READ_DEFAULT_LINK (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_DEFAULT_LINK *PF_READ_DEFAULT_LINK;
+
+/**
+ * Turns routing tables on for a given Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node that will have it's routing tables enabled
+ * @param[in] Nb this northbridge
+ */
+typedef VOID F_ENABLE_ROUTING_TABLES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_ENABLE_ROUTING_TABLES *PF_ENABLE_ROUTING_TABLES;
+
+/**
+ * Turns routing tables off for a given Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node that will have it's routing tables disabled
+ * @param[in] Nb this northbridge
+ */
+typedef VOID F_DISABLE_ROUTING_TABLES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_DISABLE_ROUTING_TABLES *PF_DISABLE_ROUTING_TABLES;
+
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link is coherent
+ *  @retval       FALSE   The Link has some other status
+*/
+typedef BOOLEAN F_VERIFY_LINK_IS_COHERENT (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_VERIFY_LINK_IS_COHERENT *PF_VERIFY_LINK_IS_COHERENT;
+
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ *
+ * @return        the Token read from the Node
+ */
+typedef UINT8 F_READ_TOKEN (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_TOKEN *PF_READ_TOKEN;
+
+/**
+ * Write the token stored in the scratchpad register
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node the Node that marked with token
+ * @param[in]     Value the token Value
+ * @param[in]     Nb this northbridge
+ */
+typedef VOID F_WRITE_TOKEN (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_TOKEN *PF_WRITE_TOKEN;
+
+/**
+ * Full Routing Table Register initialization
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node            the Node that will be examined
+ * @param[in]     Target          the Target Node for these routes
+ * @param[in]     ReqLink         the Link for requests to Target
+ * @param[in]     RspLink         the Link for responses to Target
+ * @param[in]     BroadcastLinks  the broadcast Links
+ * @param[in]     Nb              this northbridge
+ */
+typedef VOID F_WRITE_FULL_ROUTING_TABLE (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_FULL_ROUTING_TABLE *PF_WRITE_FULL_ROUTING_TABLE;
+
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb this northbridge
+ *
+ * @retval   TRUE    the node is not compatible
+ * @retval   FALSE   the node is compatible
+ */
+typedef BOOLEAN F_IS_ILLEGAL_TYPE_MIX (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_IS_ILLEGAL_TYPE_MIX *PF_IS_ILLEGAL_TYPE_MIX;
+
+/**
+ * Return whether the current configuration exceeds the capability
+ * of the nodes detected.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node
+ * @param[in]     State    sysMpCap (updated) and NodesDiscovered
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE     system is not capable of current config.
+ * @retval        FALSE    system is capable of current config.
+ */
+typedef BOOLEAN F_IS_EXCEEDED_CAPABLE (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_IS_EXCEEDED_CAPABLE *PF_IS_EXCEEDED_CAPABLE;
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ *
+ * @HtNbInstances
+ *
+ * Use is for fatal incompatible configurations.
+ * While XMIT and RCV off are HT standard, the use of these bits
+ * is generally family specific.
+ *
+ * @param[in] Node   the node to stop a link on.
+ * @param[in] Link   the link to stop.
+ * @param[in] State  access to special routine for writing link control register
+ * @param[in] Nb     this northbridge.
+ */
+typedef VOID F_STOP_LINK (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_STOP_LINK *PF_STOP_LINK;
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbInstances
+ *
+ * This routine is expected to be unimplemented for most families.
+ * Some configurations may require that links be processed specially to prevent
+ * serious problems, like hangs.  Check for that condition in this routine,
+ * handle the link both for hardware and for adding to port list, if appropriate.
+ * If this routine adds the link to port list or the link should not be added, return TRUE.
+ *
+ * @param[in] Node  The Node which has this link
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This link received special handling.
+ * @retval    FALSE This link was not handled specially, handle it normally.
+ *
+ */
+typedef BOOLEAN F_HANDLE_SPECIAL_LINK_CASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_HANDLE_SPECIAL_LINK_CASE *PF_HANDLE_SPECIAL_LINK_CASE;
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbInstances
+ *
+ * This routine is expected to be unimplemented for most families.
+ * Some configurations may require that nodes be processed specially to prevent
+ * serious problems, like hangs.  Check for that condition in this routine,
+ * handle the node both for hardware and for adding to port list, if appropriate.
+ * If this routine adds the node to port list or the node should not be added, return TRUE.
+ *
+ * @param[in] Node  The Node which need to be checked.
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This node received special handling.
+ * @retval    FALSE This node was not handled specially, handle it normally.
+ *
+ */
+typedef BOOLEAN F_HANDLE_SPECIAL_NODE_CASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_HANDLE_SPECIAL_NODE_CASE *PF_HANDLE_SPECIAL_NODE_CASE;
+
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node                the Node
+ * @param[out]    ModuleType          0 for Single, 1 for Multi
+ * @param[out]    Module              The module number of this node (0 if Single)
+ * @param[in]     Nb                  this northbridge
+ *
+ */
+typedef VOID F_GET_MODULE_INFO (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_GET_MODULE_INFO *PF_GET_MODULE_INFO;
+
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailInfo    The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+typedef VOID F_POST_MAILBOX (
+  IN       UINT8        Node,
+  IN       AP_MAILBOXES ApMailInfo,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_POST_MAILBOX *PF_POST_MAILBOX;
+
+/**
+ * Retrieve info from a node's AP mailbox.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailInfo    The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+typedef AP_MAIL_INFO F_RETRIEVE_MAILBOX (
+  IN       UINT8        Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_RETRIEVE_MAILBOX *PF_RETRIEVE_MAILBOX;
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node     The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb       Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+typedef UINT8 F_GET_SOCKET (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_SOCKET *PF_GET_SOCKET;
+
+/**
+ * Return the Link to the Southbridge
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Nb this northbridge
+ *
+ * @return the Link to the southbridge
+ */
+typedef UINT8 F_READ_SB_LINK (
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_SB_LINK *PF_READ_SB_LINK;
+
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link is non-coherent.
+ * @retval        FALSE   The Link has some other status
+ */
+typedef BOOLEAN F_VERIFY_LINK_IS_NON_COHERENT (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_VERIFY_LINK_IS_NON_COHERENT *PF_VERIFY_LINK_IS_NON_COHERENT;
+
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     ConfigMapIndex the map entry to set
+ * @param[in]     SecBus         The secondary bus number to use
+ * @param[in]     SubBus         The subordinate bus number to use
+ * @param[in]     TargetNode     The Node  that shall be the recipient of the traffic
+ * @param[in]     TargetLink     The Link that shall be the recipient of the traffic
+ * @param[in]     State          our global state
+ * @param[in]     Nb             this northbridge
+ */
+typedef VOID F_SET_CONFIG_ADDR_MAP (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_CONFIG_ADDR_MAP *PF_SET_CONFIG_ADDR_MAP;
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbInstances
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node       Result could (later) be for a specific Node
+ * @param[in]     Interface  Access to non-HT support functions.
+ * @param[in]     Nb         this northbridge
+ *
+ * @return Frequency mask
+ */
+typedef UINT32 F_NORTH_BRIDGE_FREQ_MASK (
+  IN       UINT8       Node,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_NORTH_BRIDGE_FREQ_MASK *PF_NORTH_BRIDGE_FREQ_MASK;
+
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in,out] ThisPort   The PortList structure entry for this link's port
+ * @param[in]     Interface  Access to non-HT support functions.
+ * @param[in]     Nb         this northbridge
+ */
+typedef VOID F_GATHER_LINK_FEATURES (
+  IN OUT   PORT_DESCRIPTOR *ThisPort,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE     *Nb
+  );
+/// Reference to a method.
+typedef F_GATHER_LINK_FEATURES *PF_GATHER_LINK_FEATURES;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the node on which to regang a link
+ * @param[in]     Link   the sublink 0 of the sublink pair to regang
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_SET_LINK_REGANG (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_REGANG *PF_SET_LINK_REGANG;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node        the node on which to set frequency for a link
+ * @param[in]     Link        the link to set frequency
+ * @param[in]     Frequency   the frequency to set
+ * @param[in]     Nb          this northbridge
+ */
+typedef VOID F_SET_LINK_FREQUENCY (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_FREQUENCY *PF_SET_LINK_FREQUENCY;
+
+/**
+ * Set the link's Unit Id Clumping enable.
+ *
+ * @HtNbInstances
+ *
+ * This applies to the host root of a non-coherent chain.
+ *
+ * @param[in]     Node              the node on which to set frequency for a link
+ * @param[in]     Link              the link to set frequency
+ * @param[in]     ClumpingEnables   the unit id clumping enables to set
+ * @param[in]     Nb                this northbridge
+ */
+typedef VOID F_SET_LINK_UNITID_CLUMPING (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT32         ClumpingEnables,
+  IN       NORTHBRIDGE    *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_UNITID_CLUMPING *PF_SET_LINK_UNITID_CLUMPING;
+
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Links01   coherent Links from Node 0 to 1
+ * @param[in]     Links10   coherent Links from Node 1 to 0
+ * @param[in]     Nb        this northbridge
+ */
+typedef VOID F_WRITE_TRAFFIC_DISTRIBUTION (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_TRAFFIC_DISTRIBUTION *PF_WRITE_TRAFFIC_DISTRIBUTION;
+
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]    Node           Set the pair on this node
+ * @param[in]    ConnectedNode  The Node to which this link pair directly connects.
+ * @param[in]    Pair           Using this pair set in the register
+ * @param[in]    Asymmetric     True if different widths
+ * @param[in]    MasterLink     Set this as the master link and in the route
+ * @param[in]    AlternateLink  Set this as the alternate link
+ * @param[in]    Nb             this northbridge
+ *
+ */
+typedef VOID F_WRITE_LINK_PAIR_DISTRIBUTION (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Pointer to method WriteLinkPairDistribution
+typedef F_WRITE_LINK_PAIR_DISTRIBUTION *PF_WRITE_LINK_PAIR_DISTRIBUTION;
+
+/**
+ * Family specific tunings.
+ *
+ * @HtNbInstances
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State   global state
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_BUFFER_OPTIMIZATIONS (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_BUFFER_OPTIMIZATIONS *PF_BUFFER_OPTIMIZATIONS;
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+typedef UINT8 F_GET_NUM_CORES_ON_NODE (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_GET_NUM_CORES_ON_NODE *PF_GET_NUM_CORES_ON_NODE;
+
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node         the Node that will be examined
+ * @param[in]     TotalNodes   the total number of Nodes
+ * @param[in]     TotalCores   the total number of cores
+ * @param[in]     Nb           this northbridge
+ */
+typedef VOID F_SET_TOTAL_NODES_AND_CORES (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_TOTAL_NODES_AND_CORES *PF_SET_TOTAL_NODES_AND_CORES;
+
+/**
+ * Get the Count of Nodes in the system.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Nb    This Northbridge.
+ *
+ * @return    The Count (1 based) of Nodes in the system.
+ */
+typedef UINT8 F_GET_NODE_COUNT (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_NODE_COUNT *PF_GET_NODE_COUNT;
+
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ */
+typedef VOID F_LIMIT_NODES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_LIMIT_NODES *PF_LIMIT_NODES;
+
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node  the Node that will be examined
+ * @param[in]     Link  the Link on that Node to examine
+ * @param[in]     State  access to call back routine
+ * @param[in]     Nb    this northbridge
+ *
+ * @retval        TRUE   the Link is not connected or has hard error
+ * @retval        FALSE  the Link is connected
+ */
+typedef BOOLEAN F_READ_TRUE_LINK_FAIL_STATUS (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_TRUE_LINK_FAIL_STATUS *PF_READ_TRUE_LINK_FAIL_STATUS;
+
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node The node on which to iterate links.
+ * @param[in,out] Link IN: the current iteration context, OUT: the next link.
+ * @param[in]     Nb   This Northbridge, access to config pointer.
+ *
+ * @retval LinkIteratorEnd         There is no next link (Link is back to BEGIN).
+ * @retval LinkIteratorExternal    The next Link is an external link.
+ * @retval LinkIteratorInternal    The next Link is an internal link.
+ */
+typedef LINK_ITERATOR_STATUS F_GET_NEXT_LINK (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Pointer to method GetNextLink
+typedef F_GET_NEXT_LINK *PF_GET_NEXT_LINK;
+
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node       the node which has this link
+ * @param[in]   Link       the link on that node
+ * @param[in]   Nb         this northbridge
+ *
+ * @return                 the Package Link
+ *
+ */
+typedef UINT8 F_GET_PACKAGE_LINK (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method
+typedef F_GET_PACKAGE_LINK *PF_GET_PACKAGE_LINK;
+
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node this Link is on
+ * @param[in]     Link    the Link
+ * @param[in]     Nb      this northbridge
+ *
+ * @return  the pci config address
+ */
+typedef PCI_ADDR F_MAKE_LINK_BASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_MAKE_LINK_BASE *PF_MAKE_LINK_BASE;
+
+/**
+ * Make a compatibility key.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @return the key
+ */
+typedef UINT64 F_MAKE_KEY (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_MAKE_KEY *PF_MAKE_KEY;
+
+/**
+ * The northbridge interface.
+ *
+ * Abstract the hardware implementation of the processor northbridge.  Feature code does
+ * not need to be tailored to specific families.  Also, more than a single family (or
+ * model in some cases) can be supported at once.  Multiple family support can be for
+ * mixed revisions or for incompatible revisions where only one is used at a time.
+ *
+ * The northbridge object contains both HT component public and northbridge private
+ * members.  These sets are grouped together.  Within each group, members are grouped
+ * according to the function area they support.
+ *
+ */
+struct _NORTHBRIDGE {
+  /* Public data, clients of northbridge can access */
+  UINT8 MaxLinks;               /**< The maximum number of Links implemented by the northbridge */
+
+  /* Public Interfaces for northbridge clients, coherent init*/
+  PF_WRITE_ROUTING_TABLE WriteRoutingTable;    /**< Method: Write a Temporary route for discovery */
+  PF_WRITE_NODEID WriteNodeID;    /**< Method: Assign a Node ID*/
+  PF_READ_DEFAULT_LINK ReadDefaultLink;    /**< Method: Which link are we connected to on a remote node? */
+  PF_ENABLE_ROUTING_TABLES EnableRoutingTables;    /**< Method: Make the routing table active */
+  PF_DISABLE_ROUTING_TABLES DisableRoutingTables;    /**< Method: Put a node back in discoverable state (deflnk) */
+  PF_VERIFY_LINK_IS_COHERENT VerifyLinkIsCoherent;    /**< Method: is a link connected and coherent? */
+  PF_READ_TOKEN ReadToken;    /**< Method: Read the enumeration token from a node */
+  PF_WRITE_TOKEN WriteToken;    /**< Method: Assign an enumeration token to a node */
+  PF_WRITE_FULL_ROUTING_TABLE WriteFullRoutingTable;    /**< Method: Set a complete routing table entry on a node */
+  PF_IS_ILLEGAL_TYPE_MIX IsIllegalTypeMix;    /**< Method: Is this node compatible with the system */
+  PF_IS_EXCEEDED_CAPABLE IsExceededCapable;    /**< Method: Is this node capable of working in this system */
+  PF_STOP_LINK StopLink;    /**< Method: stop a link which must be unused */
+  PF_HANDLE_SPECIAL_LINK_CASE HandleSpecialLinkCase;    /**< Method: Fix broken configuration designs */
+  PF_HANDLE_SPECIAL_NODE_CASE HandleSpecialNodeCase;    /**< Method: Fix broken configuration designs */
+
+  /* Public Interfaces for northbridge clients, noncoherent init */
+  PF_READ_SB_LINK ReadSouthbridgeLink;    /**< Method: Which link goes to the southbridge? */
+  PF_VERIFY_LINK_IS_NON_COHERENT VerifyLinkIsNonCoherent;    /**< Method: is a link connected and non-coherent? */
+  PF_SET_CONFIG_ADDR_MAP SetConfigAddrMap;    /**< Method: Add a non-coherent chain to the PCI Config Bus Address Map */
+
+  /* Public Interfaces for northbridge clients, Optimization */
+  PF_NORTH_BRIDGE_FREQ_MASK NorthBridgeFreqMask;    /**< Method: Check for frequency limits other than HT */
+  PF_GATHER_LINK_FEATURES GatherLinkFeatures;        /**< Method: Get frequency and link features */
+  PF_SET_LINK_REGANG SetLinkRegang;              /**< Method: Set a Link to regang */
+  PF_SET_LINK_FREQUENCY SetLinkFrequency;        /**< Method: Set the link Frequency */
+  PF_SET_LINK_UNITID_CLUMPING SetLinkUnitIdClumping;   /**< Method: Set the link's Unit Id Clumping register */
+
+  /* Public Interfaces for northbridge clients, System and performance Tuning. */
+  PF_WRITE_TRAFFIC_DISTRIBUTION WriteTrafficDistribution;    /**< Method: traffic distribution setting */
+  PF_WRITE_LINK_PAIR_DISTRIBUTION WriteLinkPairDistribution;    /**< Method: Link Pair setting and fix up */
+  PF_BUFFER_OPTIMIZATIONS BufferOptimizations;    /**< Method: system tunings which can not be
+                                                   * done using register table */
+
+  /* Public Interfaces for northbridge clients, utility routines */
+  PF_GET_NUM_CORES_ON_NODE GetNumCoresOnNode;    /**< Method: Count cores */
+  PF_SET_TOTAL_NODES_AND_CORES SetTotalNodesAndCores;    /**< Method: Set Node and Core counts */
+  PF_GET_NODE_COUNT GetNodeCount;    /**< Method: Get the Count (1 based) of Nodes in the system. */
+  PF_LIMIT_NODES LimitNodes;    /**< Method: Set the Limit Config Space feature */
+  PF_READ_TRUE_LINK_FAIL_STATUS ReadTrueLinkFailStatus;    /**< Method: Get Fault status and connectivity of a link */
+  PF_GET_NEXT_LINK GetNextLink;    /**< Method: Iterate over a node's Internal, then External links. */
+  PF_GET_PACKAGE_LINK GetPackageLink;    /**< Method: the package link corresponding to a node's link */
+  PF_MAKE_LINK_BASE MakeLinkBase;    /**< Method: Provide the PCI Config Base register offset of a CPU link */
+  PF_GET_MODULE_INFO GetModuleInfo;    /**< Method: Get Module Type and internal Module number */
+  PF_POST_MAILBOX PostMailbox;     /**< Method: Post info to the mailbox register */
+  PF_RETRIEVE_MAILBOX RetrieveMailbox;     /**< Method: Retrieve info from the mailbox register */
+  PF_GET_SOCKET GetSocket;    /**< Method: Get a node's Socket, using the hardware naming method. */
+
+  /* Private Data for northbridge implementation use only */
+  UINT32 SelfRouteRequestMask;  /**< Bit pattern for route request to self in routing table register */
+  UINT32 SelfRouteResponseMask; /**< Bit pattern for route response to self in routing table register */
+  UINT8 BroadcastSelfBit;       /**< Bit offset of broadcast self bit in routing table register */
+  BOOLEAN IsOrderBSPCoresByNode; /**< This processor orders Cores by Node id on the BSP, if TRUE. */
+  BOOLEAN IsOrderCoresByModule;  /**< Processors other than the BSP order Cores by Module, if TRUE. */
+  UINT64 CompatibleKey;         /**< Used for checking compatibility of northbridges in the system */
+  PACKAGE_HTLINK_MAP PackageLinkMap;    /**< Tell GetPackageLink() how to assign link names */
+  UINT32 CoreFrequency;           /**< Cache the northbridge core frequency, so repeated interface calls are avoided.
+                                   *   A value of zero, means no value yet. */
+  IGNORE_LINK *DefaultIgnoreLinkList;   /**< After processing the user interface ignore link, process this list. */
+
+  /* Private Interfaces for northbridge implementation. */
+  PF_MAKE_KEY MakeKey;    /**< Method: make the compatibility key for this node */
+
+  /** Config Pointer, opaque handle for passing to lib */
+  VOID *ConfigHandle;
+};
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Make a compatibility key.
+ *
+ */
+UINT64
+MakeKey (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+VOID
+NewNorthBridge (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+     OUT   NORTHBRIDGE *Nb
+  );
+
+#endif  /* _HT_NB_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNbHardwareFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNbHardwareFam10.h
new file mode 100755
index 0000000000..66ac12559c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNbHardwareFam10.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * Northbridge hardware definitions for Family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+#ifndef _HT_NB_HARDWARE_FAM10_H_
+#define _HT_NB_HARDWARE_FAM10_H_
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* CPU Northbridge Functions */
+#define CPU_HTNB_FUNC_00                  0
+#define CPU_HTNB_FUNC_04                  4
+#define CPU_ADDR_FUNC_01                  1
+#define CPU_NB_FUNC_03                    3
+
+/* Function 0 registers */
+#define REG_ROUTE0_0X40                   0x40
+#define REG_ROUTE1_0X44                   0x44
+#define REG_NODE_ID_0X60                  0x60
+#define REG_UNIT_ID_0X64                  0x64
+#define REG_LINK_TRANS_CONTROL_0X68       0x68
+#define REG_LINK_INIT_CONTROL_0X6C        0x6C
+#define REG_HT_CAP_BASE_0X80              0x80
+#define REG_HT_LINK_CLUMPING0_0X110       0x110
+#define REG_HT_LINK_RETRY0_0X130          0x130
+#define REG_HT_EXTENDED_NODE_ID_F0X160    0x160
+#define HTREG_NODE_CPUCNT_4_0             0x1F
+#define HTREG_EXTNODE_CPUCNT_7_5          0xE0
+#define REG_HT_TRAFFIC_DIST_0X164         0x164
+#define REG_LINK_GLOBAL_EXT_CONTROL_0x16C 0x16C
+#define REG_HT_LINK_EXT_CONTROL0_0X170    0x170
+#define REG_HT_LINK_INITIALIZATION_0X1A0  0x1A0
+#define PAIR_SELECT_OFFSET                8
+#define REG_HT_LINK_PAIR_DIST_0X1E0       0x1E0
+
+/* Function 1 registers */
+#define REG_ADDR_CONFIG_MAP0_1XE0         0xE0
+#define CPU_ADDR_NUM_CONFIG_MAPS          4
+
+/* Function 3 registers */
+#define REG_NB_SRI_XBAR_BUF_3X70          0x70
+#define REG_NB_MCT_XBAR_BUF_3X78          0x78
+#define REG_NB_FIFOPTR_3XDC               0xDC
+#define REG_NB_CAPABILITY_3XE8            0xE8
+#define REG_NB_CPUID_3XFC                 0xFC
+#define REG_NB_LINK_XCS_TOKEN0_3X148      0x148
+#define REG_NB_MCA_LINK_THRESHOLD_3X168   0x168
+#define REG_NB_MCA_L3_THRESHOLD_3X170     0x170
+#define REG_NB_DOWNCORE_3X190             0x190
+#define REG_NB_SBI_CONTROL_3X1E4          0x1E4
+
+/* Function 4 registers */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif /* _HT_NB_HARDWARE_FAM10_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
new file mode 100755
index 0000000000..ae06ba254f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
@@ -0,0 +1,659 @@
+/**
+ * @file
+ *
+ * Code for detailed notification of events and status.
+ *
+ * Routines for logging and reporting details and summary status.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNotify.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTNOTIFY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Log an event.
+ *
+ * Errors, events, faults, warnings, and useful information are provided by
+ * calling this routine as often as necessary, once for each notification.
+ * @sa AGESA.h for class, and event definitions.
+ * @sa htNotify.h for event data definitions.
+ *
+ * @param[in]     EvtClass      What level event is this
+ * @param[in]     Event         A unique ID of this event
+ * @param[in]     EventData     useful data associated with the event.
+ * @param[in]     State         the log area and remaining free space
+ */
+VOID
+STATIC
+setEventNotify (
+  IN       AGESA_STATUS  EvtClass,
+  IN       UINT32        Event,
+  IN       CONST UINT8  *EventData,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT32 DataParam[NUMBER_OF_EVENT_DATA_PARAMS];
+
+  // Remember the highest event class notified, that becomes our return code.
+  if (State->MaxEventClass < EvtClass) {
+    State->MaxEventClass = EvtClass;
+  }
+
+  // Copy the event data to the log data
+  LibAmdMemCopy (
+    DataParam,
+    (VOID *)EventData,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  // Log the event
+  PutEventLog (
+    EvtClass,
+    Event,
+    DataParam[0],
+    DataParam[1],
+    DataParam[2],
+    DataParam[3],
+    State->ConfigHandle
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_HW_SYNCFLOOD
+ *
+ * @param[in] Node      The node on which the fault is reported
+ * @param[in] Link      The link from that node
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyAlertHwSyncFlood (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       STATE_DATA   *State
+  )
+{
+  HT_EVENT_DATA_HW_SYNCFLOOD Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  setEventNotify (AGESA_ALERT,
+                 HT_EVENT_HW_SYNCFLOOD,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_HW_HTCRC
+ *
+ * @param[in] Node      The node on which the error is reported
+ * @param[in] Link      The link from that node
+ * @param[in] LaneMask  The lanes which had CRC
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyAlertHwHtCrc (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      LaneMask,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_HW_HT_CRC Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.LaneMask = LaneMask;
+  setEventNotify (AGESA_ALERT,
+                 HT_EVENT_HW_HTCRC,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_BUS_MAX_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Bus       The bus number to assign
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohBusMaxExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Bus,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Bus = Bus;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_BUS_MAX_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_CFG_MAP_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohCfgMapExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_CFG_MAP_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_BUID_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] Id        The Id which was attempted to assigned
+ * @param[in] Units     The number of units in this device
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohBuidExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       UINT8      Units,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_BUID_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  Evt.CurrentBuid = Id;
+  Evt.UnitCount = Units;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_BUID_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_DEVICE_FAILED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] Id        The Id which was attempted to assigned
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohDeviceFailed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  Evt.AttemptedBuid = Id;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_DEVICE_FAILED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_AUTO_DEPTH
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyInfoNcohAutoDepth (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_AUTO_DEPTH Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_SUCCESS,
+                 HT_EVENT_NCOH_AUTO_DEPTH,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyWarningOptRequiredCapRetry (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_REQUIRED_CAP_RETRY,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyWarningOptRequiredCapGen3 (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_REQUIRED_CAP_GEN3,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_UNUSED_LINKS
+ *
+ * @param[in]  NodeA    One of the nodes connected
+ * @param[in]  NodeB    The other connected node
+ * @param[in]  LinkA    its unusable link
+ * @param[in]  LinkB    its unusable link
+ * @param[in]  State    our State
+ *
+ */
+VOID
+NotifyWarningOptUnusedLinks (
+  IN       UINT32    NodeA,
+  IN       UINT32    LinkA,
+  IN       UINT32    NodeB,
+  IN       UINT32    LinkB,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_UNUSED_LINKS Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.NodeA = NodeA;
+  Evt.LinkA = LinkA;
+  Evt.NodeB = NodeB;
+  Evt.LinkB = LinkB;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_UNUSED_LINKS,
+                 (UINT8 *)&Evt, State);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_LINK_PAIR_EXCEED
+ *
+ * @param[in]  NodeA      One of the nodes connected
+ * @param[in]  NodeB      The other connected node
+ * @param[in]  MasterLink its unusable Masterlink
+ * @param[in]  AltLink    its unusable Alternate link
+ * @param[in]  State      our State
+ *
+ */
+VOID
+NotifyWarningOptLinkPairExceed (
+  IN       UINT32    NodeA,
+  IN       UINT32    NodeB,
+  IN       UINT32    MasterLink,
+  IN       UINT32    AltLink,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.NodeA = NodeA;
+  Evt.MasterLink = MasterLink;
+  Evt.NodeB = NodeB;
+  Evt.AltLink = AltLink;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_LINK_PAIR_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_NO_TOPOLOGY
+ *
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorCohNoTopology (
+  IN       UINT8 Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_NO_TOPOLOGY Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_COH_NO_TOPOLOGY,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
+ *
+ * @param[in] Node      The node from which a new node was discovered
+ * @param[in] Link      The link from that node
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyFatalCohProcessorTypeMix (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_CRITICAL,
+                 HT_EVENT_COH_PROCESSOR_TYPE_MIX,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_NODE_DISCOVERED
+ *
+ * @param[in] Node       Node from which a new node was discovered
+ * @param[in] Link       The link to that new node
+ * @param[in] NewNode    The new node's id
+ * @param[in] TempRoute  Temporarily, during discovery, the new node is accessed at this id.
+ * @param[in] State      our State
+ *
+ */
+VOID
+NotifyInfoCohNodeDiscovered (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 NewNode,
+  IN       UINT8 TempRoute,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_NODE_DISCOVERED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.NewNode = NewNode;
+  Evt.TempRoute = TempRoute;
+  setEventNotify (AGESA_SUCCESS,
+                 HT_EVENT_COH_NODE_DISCOVERED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_MPCAP_MISMATCH
+ *
+ * @param[in] Node      The node from which a new node was discovered
+ * @param[in] Link      The link from that node
+ * @param[in] Cap       The aggregate system MP Capability
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyFatalCohMpCapMismatch (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Cap,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.SysMpCap = Cap;
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_CRITICAL,
+                 HT_EVENT_COH_MPCAP_MISMATCH,
+                 (UINT8 *)&Evt, State);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
new file mode 100755
index 0000000000..5059dcef2a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
@@ -0,0 +1,297 @@
+/**
+ * @file
+ *
+ * HT Notify interface.
+ *
+ * This file provides internal interface to event and status
+ * notification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NOTIFY_H_
+#define _HT_NOTIFY_H_
+
+/*----------------------------------------------------------------------------------------*/
+/* Event specific event data definitions.
+ * All structures must be 4 UINT32's in size, no more, no less.
+ */
+
+/// For event ::HT_EVENT_HW_SYNCFLOOD
+typedef struct {
+  UINT32 Node;                   ///< The Node on which observed
+  UINT32 Link;                   ///< The Link on that Node which reported synch flood
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+} HT_EVENT_DATA_HW_SYNCFLOOD;
+
+/// For event ::HT_EVENT_HW_HTCRC
+typedef struct {
+  UINT32 Node;                   ///< The Node on which event is observed
+  UINT32 Link;                   ///< The Link on that Node which reported CRC error
+  UINT32 LaneMask;               ///< The CRC lane mask for the Link
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_HW_HT_CRC;
+
+/// For event ::HT_EVENT_NCOH_BUS_MAX_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Bus;                    ///< the current bus number
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_CFG_MAP_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_BUID_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT16 CurrentBuid;            ///< the current available BUID
+  UINT16 UnitCount;              ///< the number of ids which would be consumed by this device
+} HT_EVENT_DATA_NCOH_BUID_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_DEVICE_FAILED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT32 AttemptedBuid;          ///< the BUID we tried to assign to that device
+} HT_EVENT_DATA_NCOH_DEVICE_FAILED;
+
+/// For event ::HT_EVENT_NCOH_AUTO_DEPTH
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain of the last device, zero is CPU host
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_AUTO_DEPTH;
+
+/// For event ::HT_EVENT_OPT_REQUIRED_CAP_RETRY,
+///           ::HT_EVENT_OPT_REQUIRED_CAP_GEN3.
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_OPT_REQUIRED_CAP;
+
+/// For event ::HT_EVENT_OPT_UNUSED_LINKS
+typedef struct {
+  UINT32 NodeA;                  ///< One of the nodes connected
+  UINT32 LinkA;                  ///< its unusable link
+  UINT32 NodeB;                  ///< The other connected node
+  UINT32 LinkB;                  ///< its unusable link
+} HT_EVENT_DATA_OPT_UNUSED_LINKS;
+
+/// For event ::HT_EVENT_OPT_LINK_PAIR_EXCEED
+typedef struct {
+  UINT32 NodeA;                  ///< One of the nodes connected
+  UINT32 NodeB;                  ///< The other connected node
+  UINT32 MasterLink;             ///< NodeA's unusable Master link
+  UINT32 AltLink;                ///< NodeA's unusable Alternatelink
+} HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED;
+
+/// For event ::HT_EVENT_COH_NO_TOPOLOGY.
+/// There is no routing for this system's topology.
+typedef struct {
+  UINT32 TotalNodes;             ///< the number of Nodes in the unmatched topology
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+  UINT32 Reserved3;              ///< Reserved.
+} HT_EVENT_DATA_COH_NO_TOPOLOGY;
+
+/// For event ::HT_EVENT_COH_PROCESSOR_TYPE_MIX
+typedef struct {
+  UINT32 Node;                   ///< the Node from which the incompatible family was found
+  UINT32 Link;                   ///< the Link to the incompatible Node
+  UINT32 TotalNodes;             ///< the number of Nodes found at that point
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX;
+
+/// For event ::HT_EVENT_COH_NODE_DISCOVERED
+typedef struct {
+  UINT32 Node;                   ///< the Node from which the new Node was found
+  UINT32 Link;                   ///< the Link to the new Node
+  UINT32 NewNode;                ///< the Node id of the newly discovered Node
+  UINT32 TempRoute;              ///< the new Node is temporarily at this id
+} HT_EVENT_DATA_COH_NODE_DISCOVERED;
+
+/// For event ::HT_EVENT_COH_MPCAP_MISMATCH
+typedef struct {
+  UINT32 Node;                   ///< the Node from which condition was observed
+  UINT32 Link;                   ///< the Link on the current Node
+  UINT32 SysMpCap;               ///< the current aggregate system capability (the minimum found so far)
+  UINT32 TotalNodes;             ///< the number of Nodes found, before this was observed
+} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
+
+/*----------------------------------------------------------------------------------------*/
+/* Event specific Notify functions.
+ */
+
+VOID
+NotifyAlertHwSyncFlood (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       STATE_DATA   *State
+  );
+
+VOID
+NotifyAlertHwHtCrc (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      LaneMask,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohBusMaxExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Bus,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohCfgMapExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohBuidExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       UINT8      Units,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohDeviceFailed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyInfoNcohAutoDepth (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptRequiredCapRetry (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptRequiredCapGen3 (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptUnusedLinks (
+  IN       UINT32    NodeA,
+  IN       UINT32    LinkA,
+  IN       UINT32    NodeB,
+  IN       UINT32    LinkB,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptLinkPairExceed (
+  IN       UINT32    NodeA,
+  IN       UINT32    NodeB,
+  IN       UINT32    MasterLink,
+  IN       UINT32    AltLink,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorCohNoTopology (
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyFatalCohProcessorTypeMix (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyInfoCohNodeDiscovered (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      NewNode,
+  IN       UINT8      TempRoute,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyFatalCohMpCapMismatch (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Cap,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+#endif /* _HT_NOTIFY_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h
new file mode 100755
index 0000000000..de71cf47e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h
@@ -0,0 +1,64 @@
+/**
+ * @file
+ *
+ * Create outline and references for HyperTransport Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page htmain HyperTransport Component Documentation
+ *
+ * Additional documentation for the HyperTransport component consists of
+ *
+ * - Member Cross References
+ *   - @subpage instanceshtnb "HT Northbridge Method Instances"
+ * - Maintenance Guides:
+ *   - @subpage htimplintf "HT Internal Interface Implementation Guide"
+ *   - @subpage htimplfeat "HT Feature Implementation Guide"
+ *   - @subpage htimplnb   "HT Northbridge Implementation Guide"
+ *   - add here >>>
+ * - Design Guides:
+ *   - @subpage htgraphdesign "Graph Support Design"
+ *   - @subpage physicalsockethowto "How to Create a Physical System Socket Map"
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htTopologies.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htTopologies.h
new file mode 100755
index 0000000000..38b13f7ece
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htTopologies.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Provide selection of available topologies.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+#ifndef _HT_TOPOLOGIES_H_
+#define _HT_TOPOLOGIES_H_
+
+extern CONST UINT8 ROMDATA amdHtTopologySingleNode[];
+extern CONST UINT8 ROMDATA amdHtTopologyDualNode[];
+extern CONST UINT8 ROMDATA amdHtTopologyThreeLine[];
+extern CONST UINT8 ROMDATA amdHtTopologyTriangle[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourLine[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourStar[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourSquare[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourKite[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyFiveFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySixFully[];
+extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[];
+extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[];
+extern CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySevenFully[];
+extern CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[];
+
+#endif // _HT_TOPOLOGIES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c
new file mode 100755
index 0000000000..f853496faf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsCtrl.c
@@ -0,0 +1,771 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Backend Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "cpuRegisters.h"
+#include "heapManager.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "IdsLib.h"
+#include "Filecode.h"
+#define FILECODE PROC_IDS_CONTROL_IDSCTRL_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+extern CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[];
+
+
+/**
+ * IDS option hooking function dispatcher.
+ *
+ * This is the top level interface for IDS option Backend code.
+ *
+ * @param[in]     IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION
+ * @param[in,out] DataPtr   Data pointer.
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_NV_ITEM *IdsNvPtr;
+  IDS_STATUS   ReturnFlag;
+  IDS_STATUS ExtendedFlag;
+
+  IdsNvPtr  = NULL;
+  ReturnFlag = IDS_SUCCESS;
+
+  ASSERT (StdHeader != NULL);
+  if (AmdGetIdsNvTable ((VOID **)&IdsNvPtr, StdHeader) != AGESA_SUCCESS) {
+    AmdIdsCtrlInitialize (StdHeader);
+    AmdGetIdsNvTable ((VOID **)&IdsNvPtr, StdHeader);
+  }
+
+  if (IdsNvPtr != NULL) {
+    ReturnFlag = IdsParseFeatTbl (IdsOption, IdsCommonFeats, DataPtr, IdsNvPtr, StdHeader);
+    ExtendedFlag = IDS_EXTENDED_HOOK (IdsOption, DataPtr, IdsNvPtr, StdHeader);
+    if (ExtendedFlag != IDS_SUCCESS) {
+      ReturnFlag = IDS_UNSUPPORTED;
+    }
+  }
+  return ReturnFlag;
+}
+
+/**
+ * Ids code for parse IDS feat table.
+ *
+ * Feat table in IDS is used to decribe the IDS support feat and its according family,handler.
+ *
+ * @param[in]     PIdsFeatTbl point to Ids Feat table
+ * @param[in]     IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION
+ * @param[in,out] DataPtr   Data pointer.
+ * @param[in]     IdsNvPtr   Ids Nvram pointer.
+ * @param[in,out] StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ **/
+IDS_STATUS
+IdsParseFeatTbl (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN       CONST IDS_FEAT_STRUCT * PIdsFeatTbl[],
+  IN OUT   VOID *DataPtr,
+  IN       IDS_NV_ITEM *IdsNvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT16 i;
+  AGESA_STATUS Tmpsts;
+  CPU_LOGICAL_ID CpuLogicalId;
+  BOOLEAN No_Check_Bsp;
+  CONST IDS_FEAT_STRUCT *PIdsFeat;
+  IDS_STATUS ReturnFlag;
+  IDS_STATUS status;
+
+  status = IDS_SUCCESS;
+  ReturnFlag = IDS_SUCCESS;
+
+  for (i = 0; PIdsFeatTbl[i] != NULL; i++) {
+    PIdsFeat = PIdsFeatTbl[i];
+    //Does specified IdsOption reached
+    if (PIdsFeat->IdsOption == IdsOption) {
+      //check if bsp only
+      if (PIdsFeat->IsBsp) {
+        No_Check_Bsp = 0;
+      } else {
+        No_Check_Bsp = 1;
+      }
+      if (No_Check_Bsp || IsBsp (StdHeader, &Tmpsts)) {
+        //Does Family Match required
+        GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+        if ((CpuLogicalId.Family) & (PIdsFeat->CpuFamily)) {
+          //Excute the code for specific Ids Feat
+          status = PIdsFeat->pf_idsoption (DataPtr, StdHeader, IdsNvPtr);
+          if (status != IDS_SUCCESS) {
+            ReturnFlag = status;
+          }
+        }
+      }
+    }
+  }
+  return ReturnFlag;
+}
+
+/**
+ *
+ *  IDS Object Initialization
+ *
+ *  Initializer routine that will be invoked by the wrapper to initialize
+ *  the data buffer in heap for the IDS object. It includes IDS control
+ *  structure, IDS mem table and IDS GRA table.
+ *
+ *  @param[in,out] StdHeader    The Pointer of IDS Initial Parameter
+ *
+ *  @retval AGESA_SUCCESS       Success to init IDS Object.
+ *  @retval AGESA_ERROR         Fail to init IDS Object.
+ *
+ **/
+
+#ifdef IDS_HEAP_2STAGES
+  #define IDS_HEAP_PERSIST_EARLY  HEAP_LOCAL_CACHE
+  #define IDS_HEAP_ASSERTION_LATE
+#else
+  #define IDS_HEAP_PERSIST_EARLY  HEAP_SYSTEM_MEM
+  #define IDS_HEAP_ASSERTION_LATE ASSERT(FALSE)
+#endif
+
+AGESA_STATUS
+AmdIdsCtrlInitialize (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  UINT16 NvTblSize;
+  UINT16 i;
+  IDS_NV_ITEM IdsNvTable[IDS_NUM_NV_ITEM];
+  IDS_NV_ITEM *NvTable;
+  IDS_NV_ITEM *NvPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+  IDS_CALLOUT_STRUCT IdsCalloutData;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT16 MemTblSize;
+  UINT8 HeapPersist;
+
+  NvTblSize = 0;
+  MemTblSize = 0;
+  HeapPersist = HEAP_SYSTEM_MEM;
+  //Heap status with HEAP_LOCAL_CACHE, will allocate heap with HEAP_LOCAL_CACHE
+  //with HEAP_TEMP_MEM  HEAP_SYSTEM_MEM  HEAP_DO_NOT_EXIST_ANYMORE  HEAP_S3_RESUME
+  // with allocate with HEAP_SYSTEM_MEM
+  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
+    MemTblSize = IDS_MAX_MEM_ITEMS;
+    HeapPersist = IDS_HEAP_PERSIST_EARLY;
+  } else if ((StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_YET) || (StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_ANYMORE)) {
+    return AGESA_ERROR;
+  } else {
+    IDS_HEAP_ASSERTION_LATE;
+  }
+
+  IdsCalloutData.IdsNvPtr = IdsNvTable;
+  IdsCalloutData.StdHeader = *StdHeader;
+//init IDS_CALLOUT_STRUCT before calling out, give NVITEM default value
+  for (i = AGESA_IDS_EXT_ID_START; i < IDS_NUM_NV_ITEM; i++) {
+    IdsNvTable[i].IdsNvId = i;
+    IdsNvTable[i].IdsNvValue = AGESA_IDS_DFT_VAL;
+  }
+
+  AGESA_TESTPOINT (TpIfBeforeGetIdsData, StdHeader);
+  if (AgesaGetIdsData (IDS_CALLOUT_INIT, &IdsCalloutData) == AGESA_SUCCESS) {
+    NvTable = IdsCalloutData.IdsNvPtr;
+    NvPtr = NvTable;
+    while (NvPtr->IdsNvId != AGESA_IDS_NV_END) {
+      NvTblSize  ++;
+      NvPtr ++;
+    }
+    NvTblSize  ++;
+
+    AllocHeapParams.RequestedBufferSize = sizeof (IDS_CONTROL_STRUCT);
+    AllocHeapParams.RequestedBufferSize += NvTblSize  * sizeof (IDS_NV_ITEM);
+    AllocHeapParams.RequestedBufferSize += MemTblSize * sizeof (MEM_TABLE_ALIAS);
+    AllocHeapParams.RequestedBufferSize += IDS_EXTENDED_HEAP_SIZE;
+    AllocHeapParams.BufferHandle = IDS_CONTROL_HANDLE;
+    AllocHeapParams.Persist = HeapPersist;
+
+    //
+    // Allocate data buffer in heap
+    //
+    if (HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader) == AGESA_SUCCESS) {
+      //
+      // Initialize IDS Date Buffer
+      //
+      IdsCtrlPtr = (IDS_CONTROL_STRUCT *) AllocHeapParams.BufferPtr;
+      IdsCtrlPtr->IdsHeapMemSize = AllocHeapParams.RequestedBufferSize;
+      IdsCtrlPtr->IdsNvTableOffset = sizeof (IDS_CONTROL_STRUCT);
+      IdsCtrlPtr->IdsMemTableOffset = IdsCtrlPtr->IdsNvTableOffset + NvTblSize  * sizeof (IDS_NV_ITEM);
+      IdsCtrlPtr->IdsExtendOffset = IdsCtrlPtr->IdsMemTableOffset + MemTblSize * sizeof (MEM_TABLE_ALIAS);
+
+      NvPtr = (IDS_NV_ITEM *) (AllocHeapParams.BufferPtr + IdsCtrlPtr->IdsNvTableOffset);
+      for (i = 0; i < NvTblSize ; i++) {
+        NvPtr->IdsNvId = NvTable->IdsNvId;
+        NvPtr->IdsNvValue = NvTable->IdsNvValue;
+        NvPtr ++;
+        NvTable ++;
+      }
+      status = AGESA_SUCCESS;
+    } else {
+      status = AGESA_ERROR;
+    }
+  } else {
+    status = AGESA_ERROR;
+  }
+  AGESA_TESTPOINT (TpIfAfterGetIdsData, StdHeader);
+
+  return status;
+}
+/**
+ *  IDS Backend Function for Target Pstate
+ *
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubTargetPstate (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS tarpst;
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+
+  IDS_NV_READ_SKIP (tarpst, AGESA_IDS_NV_TARGET_PSTATE, IdsNvPtr) {
+    GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) tarpst, (BOOLEAN) FALSE, StdHeader);
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for HdtOut
+ *
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubHdtOut (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS idsvalue;
+  AMD_EARLY_PARAMS *rptr;
+
+  rptr = (AMD_EARLY_PARAMS *)DataPtr;
+//set HDTOUT En/Dis
+  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_HDTOUT, IdsNvPtr) {
+//if HDTOUT set to enable, set the corresponding DR2 flag to 0x99cc
+    if (idsvalue == 1) {
+      LibAmdWriteCpuReg (DR2_REG, 0x99cc);
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Power down mode
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubPowerDownCtrl (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_POST_PARAMS *PostParamsPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  IDS_STATUS idsvalue;
+  MEM_DATA_STRUCT * memdataptr;
+
+  PostParamsPtr = (AMD_POST_PARAMS *)DataPtr;
+  memdataptr = PostParamsPtr->MemConfig.MemData;
+  RefPtr = memdataptr->ParameterListPtr;
+
+  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_MEMORY_POWER_DOWN, IdsNvPtr) {
+    if (idsvalue < (IDS_STATUS)0x2) {
+      RefPtr->EnablePowerDown = (BOOLEAN) idsvalue;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  Backend Function for IDS Option Hook Point: IDS_UCODE
+ *
+ *  This function is used to disable UCode Installation if IDS Option disables ucode.
+ *  The method is to force the number of total patches to ZERO.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of Data to Override.
+ *  @param[in,out]   StdHeader    The Pointer of AGESA Header.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubUCode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  UINT8 *TotalPatches;
+
+  TotalPatches = (UINT8 *) DataPtr;
+  if (AmdIdsNvReader (AGESA_IDS_NV_UCODE, IdsNvPtr) == (IDS_STATUS)  0x0) {
+    (*TotalPatches) = 0;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Post P-State
+ *
+ *  This function is used to set Post P-State which are CPU specifically.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_CPU_EARLY_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubPostPState (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_CPU_EARLY_PARAMS *PCpuEarlyParams;
+  IDS_STATUS idsvalue;
+  UINT8 curpstatesnum;
+
+  PCpuEarlyParams = (AMD_CPU_EARLY_PARAMS *)DataPtr;
+  curpstatesnum = IdsGetNumPstatesFamCommon (StdHeader);
+  idsvalue = AmdIdsNvReader (AGESA_IDS_NV_POSTPSTATE, IdsNvPtr);
+
+  if (idsvalue < (IDS_STATUS) (curpstatesnum + 3)) {
+    switch (idsvalue) {
+    case (IDS_STATUS) 0x0:
+      // Auto
+      break;
+    case (IDS_STATUS) 0x1:
+      // Maximum Performance
+      PCpuEarlyParams->MemInitPState = 0;
+      break;
+    case (IDS_STATUS) 0x2:
+      // Minimum Performance
+      PCpuEarlyParams->MemInitPState = curpstatesnum - 1;
+      break;
+    default:
+      PCpuEarlyParams->MemInitPState = (UINT8) (idsvalue - 3);
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+
+/**
+ *  IDS Backend Function for ECC symbol size
+ *
+ *  This function is used to override mem parameter
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+
+IDS_STATUS
+IdsSubEccSymbolSize (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  BOOLEAN *peccsymbolsize;
+  IDS_STATUS Status;
+  peccsymbolsize = (BOOLEAN *)DataPtr;
+  Status = AmdIdsNvReader (AGESA_IDS_NV_ECC_SYMBOL_SIZE, IdsNvPtr);
+  if (Status != IDS_UNSUPPORTED) {
+    if (Status == 0x1 || Status == 0x2) {
+      *peccsymbolsize = (BOOLEAN)(Status - 1);
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Memory Mode Unganged
+ *
+ *  This function is used to override Memory Mode Unganged.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubGangingMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS GangingMode;
+  IDS_NV_READ_SKIP (GangingMode, AGESA_IDS_NV_DCT_GANGING_MODE, IdsNvPtr) {
+    *((UINT8 *)DataPtr) = (UINT8) GangingMode;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Power Down Mode
+ *
+ *  This function is used to override Power Down Mode.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubPowerDownMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS PowerDownMode;
+  PowerDownMode = AmdIdsNvReader (AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, IdsNvPtr);
+  if (PowerDownMode < (IDS_STATUS)0x2) {
+    *((UINT8 *) DataPtr) = (UINT8)PowerDownMode;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Burst Length32
+ *
+ *  This function is used to override Burst Length32.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubBurstLength32 (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS BurstLength32;
+  BurstLength32 = AmdIdsNvReader (AGESA_IDS_NV_DRAM_BURST_LENGTH32, IdsNvPtr);
+  if (BurstLength32 < (IDS_STATUS)0x2) {
+    *((UINT8 *) DataPtr) = (UINT8)BurstLength32;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for All Memory Clks Enable
+ *
+ *  This function is used to override All Memory Clks Enable
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubAllMemClkEn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS AllMemClkEn;
+  AllMemClkEn = AmdIdsNvReader (AGESA_IDS_NV_ALL_MEMCLKS , IdsNvPtr);
+  if (AllMemClkEn < (IDS_STATUS)0x2) {
+    *((UINT8 *) DataPtr) = (UINT8)AllMemClkEn;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Dll Shut Down
+ *
+ *  This function is used to override Dll Shut Down Option
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubDllShutDownSR (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS DllShutDownSR;
+  IDS_NV_READ_SKIP (DllShutDownSR, AGESA_IDS_NV_DLL_SHUT_DOWN , IdsNvPtr) {
+    *((UINT8 *) DataPtr) = (UINT8)DllShutDownSR;
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for HT Link Configuration
+ *
+ *  Provide the nv settings to the HT code in the form of a port override list.
+ *  Create the list on the heap, so the HT code doesn't have to keep asking for it.
+ *
+ *  @param[out] Data         A reference to the HT Port Override List
+ *  @param[in]  StdHeader    Header for library and services.
+ *  @param[in] IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ */
+IDS_STATUS
+IdsSubHtLinkControl (
+     OUT   VOID  *Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  HTIDS_PORT_OVERRIDE_LIST   *ListReference;
+  HTIDS_PORT_OVERRIDE_LIST   PortOverrideList;
+  UINT32 HTlinkSocket;
+  UINT32 HTlinkPort;
+  UINT32 HTlinkFre;
+  UINT32 HTlinkWidthIn;
+  UINT32 HTlinkWidthOut;
+
+  ASSERT (IdsNvPtr != NULL);
+  ASSERT (Data != NULL);
+
+  ListReference = Data;
+  *ListReference = NULL;
+  // Allocated the number of portlist override option sets supported (currently 1) plus 1 more for terminal.
+  AllocHeapParams.RequestedBufferSize = (sizeof (HTIDS_PORT_OVERRIDE) * 2);
+  AllocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST) AllocHeapParams.BufferPtr;
+    LibAmdMemFill (PortOverrideList, HT_LIST_TERMINAL, AllocHeapParams.RequestedBufferSize, StdHeader);
+    *ListReference = PortOverrideList;
+
+    HTlinkSocket = AmdIdsNvReader (AGESA_IDS_NV_HTLINKSOCKET, IdsNvPtr);
+    if (HTlinkSocket != IDS_UNSUPPORTED) {
+      switch (HTlinkSocket) {
+      case (UINT32) 0xE:
+        HTlinkSocket = 0xFE;
+        break;
+      case (UINT32) 0xF:
+        HTlinkSocket = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->Socket = (UINT8) HTlinkSocket;
+    }
+    HTlinkPort = AmdIdsNvReader (AGESA_IDS_NV_HTLINKPORT, IdsNvPtr);
+    if (HTlinkPort != IDS_UNSUPPORTED) {
+      switch (HTlinkPort) {
+      case (UINT32) 0xC:
+        HTlinkPort = 0xFC;
+        break;
+      case (UINT32) 0xD:
+        HTlinkPort = 0xFD;
+        break;
+      case (UINT32) 0xE:
+        HTlinkPort = 0xFE;
+        break;
+      case (UINT32) 0xF:
+        HTlinkPort = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->Link = (UINT8) HTlinkPort;
+    }
+    HTlinkFre = AmdIdsNvReader (AGESA_IDS_NV_HTLINKFREQ, IdsNvPtr);
+    if (HTlinkFre != IDS_UNSUPPORTED) {
+      switch (HTlinkFre) {
+      case (UINT32) 0x1F:
+        HTlinkFre = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->Frequency = (UINT8) HTlinkFre;
+    }
+    HTlinkWidthIn = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHIN , IdsNvPtr);
+    if (HTlinkWidthIn != IDS_UNSUPPORTED) {
+      switch (HTlinkWidthIn) {
+      case (UINT32) 0x0:
+        HTlinkWidthIn = 0x8;
+        break;
+      case (UINT32) 0x01:
+        HTlinkWidthIn = 0x16;
+        break;
+      case (UINT32) 0x04:
+        HTlinkWidthIn = 0x2;
+        break;
+      case (UINT32) 0x5:
+        HTlinkWidthIn = 0x4;
+        break;
+      case (UINT32) 0x7:
+        HTlinkWidthIn = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn;
+    }
+    HTlinkWidthOut = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHOUT, IdsNvPtr);
+    if (HTlinkWidthOut != IDS_UNSUPPORTED) {
+      switch (HTlinkWidthOut) {
+      case (UINT32) 0x0:
+        HTlinkWidthOut = 0x8;
+        break;
+      case (UINT32) 0x01:
+        HTlinkWidthOut = 0x16;
+        break;
+      case (UINT32) 0x04:
+        HTlinkWidthOut = 0x2;
+        break;
+      case (UINT32) 0x5:
+        HTlinkWidthOut = 0x4;
+        break;
+      case (UINT32) 0x7:
+        HTlinkWidthOut = 0xFF;
+        break;
+      default:
+        break;
+      }
+      PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
new file mode 100755
index 0000000000..c8a5b96b5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib.c
@@ -0,0 +1,397 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "IdsLib.h"
+#include "heapManager.h"
+
+#include "mm.h"
+#include "mn.h"
+#include "cpuLateInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_IDS_CONTROL_IDSLIB_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdGetIdsImagebase (
+  IN OUT   UINT64 *IdsImageBase,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *
+ *  Get IDS NV table pointer in the AGESA Heap.
+ *
+ *  @param[in,out] IdsNvTable   The Pointer of IDS NV Table.
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of NV Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of NV Table.
+ **/
+AGESA_STATUS
+AmdGetIdsNvTable (
+  IN OUT   VOID  **IdsNvTable,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+
+  LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status == AGESA_SUCCESS) {
+    IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr;
+    *IdsNvTable = LocateHeapStructPtr.BufferPtr + IdsCtrlPtr->IdsNvTableOffset;
+  }
+  return status;
+}
+
+/**
+ *
+ *  Get IDS Override Image Base Address
+ *
+ *  @param[in,out] IdsImageBase The Base Address of IDS Override Image.
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of NV Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of NV Table.
+ *
+ **/
+AGESA_STATUS
+AmdGetIdsImagebase (
+  IN OUT   UINT64 *IdsImageBase,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  IDS_CONTROL_STRUCT *IdsCtrlPtr;
+
+  LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status == AGESA_SUCCESS) {
+    IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr;
+    *IdsImageBase = IdsCtrlPtr->IdsImageBase;
+  }
+  return status;
+}
+
+/**
+ *
+ * Read IDS NV value in NV table.
+ *
+ * It searches the table until the Nv Id is found and return the NV value
+ * in the table. Otherwise, return IDS_UNSUPPORTED.
+ *
+ * @param[in] IdsNvId       IDS NV ID
+ * @param[in] NvTablePtr    NV Table pointer.
+ *
+ * @retval IDS_UNSUPPORTED  NV ID is not found in the table
+ *         Other Value      The NV value
+ *
+ **/
+IDS_STATUS
+AmdIdsNvReader (
+  IN      UINT16 IdsNvId,
+  IN      IDS_NV_ITEM *NvTablePtr
+  )
+{
+  IDS_STATUS Status;
+  IDS_NV_ITEM *NvPtr;
+
+  Status = IDS_UNSUPPORTED;
+  NvPtr = NvTablePtr;
+
+  if (NvPtr != NULL) {
+    while (NvPtr->IdsNvId != AGESA_IDS_NV_END) {
+      if (NvPtr->IdsNvId == IdsNvId) {
+        break;
+      } else {
+        NvPtr ++;
+      }
+    }
+    if ((NvPtr->IdsNvId != AGESA_IDS_NV_END) && (NvPtr->IdsNvValue != AGESA_IDS_DFT_VAL)) {
+      Status = NvPtr->IdsNvValue;
+    }
+  }
+
+  return Status;
+}
+
+/**
+ * IDS function for only return IDS_SUCCESS
+ *
+ *
+ *  @param[in,out]   DataPtr      meaningless data pointer
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS          Always succeeds.
+ *
+ **/
+IDS_STATUS
+IdsCommonReturn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  return IDS_SUCCESS;
+}
+
+/**
+ *
+ *  set the MSR of AP
+ *
+ *  @param[in] PRegMsr  point to REG_MSR
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+AMDSetAPMsr (
+  IN       REG_MSR  *PRegMsr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 value;
+
+  LibAmdMsrRead (PRegMsr->msraddr, &value, StdHeader);
+  value &= ((UINT64)PRegMsr->andmaskhi << 32) | ((UINT64)PRegMsr->andmasklo);
+  value |= ((UINT64)PRegMsr->ormaskhi << 32) | ((UINT64)PRegMsr->ormasklo);
+  LibAmdMsrWrite (PRegMsr->msraddr, &value, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+/**
+ * IDS function for ap run specific task after amdinitpost
+ *
+ *
+ *  @param[in]   ApicIdOfCore      apic id of specific AP
+ *  @param[in]   ApLateTaskPtr    The Pointer of IDSAPLATETASK.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+IdsAgesaRunFcnOnApLate  (
+  IN       UINTN               ApicIdOfCore,
+  IN       IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS  Status;
+  AP_EXE_PARAMS LaunchApParams;
+
+//init AgesaRunFcnOnAp parameters
+  LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID;
+  LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK);
+  LaunchApParams.RelatedDataBlock = ApLateTaskPtr;
+  LaunchApParams.StdHeader = *StdHeader;
+
+  AGESA_TESTPOINT (TpIfBeforeRunApFromIds, StdHeader);
+  Status = AgesaRunFcnOnAp ((UINTN) ApicIdOfCore, &LaunchApParams);
+  AGESA_TESTPOINT (TpIfAfterRunApFromIds, StdHeader);
+
+  return Status;
+}
+
+/**
+ * IDS function force all cores run specific task after amdinitpost
+ *
+ *
+ *  @param[in]   ApLateTaskPtr    The Pointer of IDSAPLATETASK.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+IdsAgesaRunFcnOnAllCoresLate  (
+  IN       IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_EXE_PARAMS LaunchApParams;
+  AGESA_STATUS Status;
+
+//init AgesaRunFcnOnAp parameters
+  Status = AGESA_SUCCESS;
+  LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID;
+  LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK);
+  LaunchApParams.RelatedDataBlock = ApLateTaskPtr;
+  LaunchApParams.StdHeader = *StdHeader;
+
+  Status = RunLateApTaskOnAllAPs (&LaunchApParams, StdHeader);
+
+//do it on Bsp
+  Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, StdHeader);
+  return Status;
+}
+
+/**
+ * IDS call-back function for ApDispatchTable
+ *
+ *  @param[in] AmdApExeParams  AP_EXE_PARAMS.
+ *
+ *  @retval AGESA_SUCCESS       Success
+ *  @retval AGESA_ERROR         meet some error
+ *
+ **/
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  )
+{
+  IDSAPLATETASK *ApLateTaskPtr;
+  AGESA_STATUS Status;
+
+  ApLateTaskPtr = (IDSAPLATETASK *)AmdApExeParams->RelatedDataBlock;
+  Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, &AmdApExeParams->StdHeader);
+  return Status;
+}
+
+/**
+ *  Get the number of P-State to support
+ *
+ *  @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS.
+ *
+ *  @retval num    The number of P-State to support.
+ *
+ **/
+UINT8
+IdsGetNumPstatesFamCommon (
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 pstatesnum;
+  UINT8 i;
+  UINT32 IddVal;
+  UINT32 IddDiv;
+  BOOLEAN PStateEnabled;
+  UINT32 TempVar_c;
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+
+  pstatesnum = 0;
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->GetPstateMaxState (FamilySpecificServices, &TempVar_c, StdHeader);
+  for (i = 0; i <= TempVar_c; i++) {
+    // Check if PState is enabled
+    FamilySpecificServices->GetPstateRegisterInfo (FamilySpecificServices,
+                                                   (UINT32) i,
+                                                   &PStateEnabled,
+                                                   &IddVal,
+                                                   &IddDiv,
+                                                   StdHeader);
+    if (PStateEnabled) {
+      pstatesnum++;
+    }
+  }
+  return pstatesnum;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Runs the given task on all cores (including self) on the socket of the executing
+ * core 0.
+ *
+ * This function is used to invoke all APs on the socket of the executing core 0 to
+ * run a specified AGESA procedure.
+ *
+ * @param[in]  TaskPtr      Function descriptor
+ * @param[in]  StdHeader    Config handle for library and services
+ *
+ */
+VOID
+IdsApRunCodeOnAllLocalCores (
+  IN       AP_TASK *TaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Core;
+  UINT32 BscCore;
+  UINT32 Socket;
+  UINT32 BscSocket;
+  UINT32 IgnoredModule;
+  UINT32 NumberOfCores;
+  UINT32 NumberOfSockets;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+ // BSP codes
+  ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
new file mode 100755
index 0000000000..6cd8a28a96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
@@ -0,0 +1,138 @@
+;/**
+; * @file
+; *
+; * Ids Assembly library 32bit
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  IDS
+; * @e \$Revision: 14305 $   @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+public IdsDelay
+IdsDelay  PROC  NEAR C USES EAX EDX
+Local targetedx:dword, targeteax:dword
+  rdtsc
+;set target time
+  add eax,1500000000
+  adc edx,0
+  mov targetedx,edx
+  mov targeteax,eax
+
+  rdtsc
+;set "Si!=0" skip below loop
+  .while(1)
+    .if(si != 0)
+      jmp delay_exit
+    .endif
+    .if(edx > targetedx)
+      jmp delay_exit
+    .elseif (edx == targetedx)
+      .if(eax > targeteax)
+        jmp delay_exit
+      .endif
+    .endif
+    rdtsc
+  .endw
+delay_exit:
+  ret
+IdsDelay    ENDP
+;/*++
+;
+;Routine Description:
+;
+;  IdsErrorStop -- Function for Assert
+;
+;Arguments:
+;  Filecode
+;
+;Returns:
+;
+;  None
+;
+;--*/
+public IdsErrorStop
+IdsErrorStop PROC NEAR  C filecode:dword
+local tmpebx:dword,tmpedx:dword
+  pushad
+
+  mov     si,0                      ; Si is used as control flag, "Si!=0" skip postcode loop
+; send debug port 1st, then fire SimNow breakpoint
+  mov     ax,  0deadh
+  out     0e0h, ax
+  mov     eax, filecode
+  out     84h, eax
+  mov     eax, 0BACCD00Bh         ; Backdoor in SimNow
+  mov     ebx, 2                  ; Select breakpoint feature
+  cpuid
+
+  mov   ebx,0dead0000h
+  mov   edx,filecode
+  ror   edx,16
+  mov   bx,dx
+  mov   dx,0
+;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
+  mov   tmpebx,ebx
+  mov   tmpedx,edx
+
+  xor   eax,eax
+  mov   cl,6
+
+  .while((cl != 0) && (si == 0))
+    .if(cl <= 2)
+      shld  eax,edx,8
+      shl   edx,8
+    .else
+      shld  eax,ebx,8
+      shl   ebx,8
+    .endif
+
+    out   80h,eax
+    call IdsDelay
+    dec cl
+    .if(cl == 0)
+      mov   cl,6
+      mov   ebx,tmpebx
+      mov   edx,tmpedx
+    .endif
+  .endw
+
+  popad
+  xor eax,eax
+  ret
+IdsErrorStop  endp
+
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
new file mode 100755
index 0000000000..cec2bd8a32
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
@@ -0,0 +1,143 @@
+;/**
+; * @file
+; *
+; * Ids Assembly library 64bit
+; *
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  IDS
+; * @e \$Revision: 14126 $   @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+.code
+IdsDelay  PROC
+  push    rax
+  push    rdx
+  push    rbx
+  xor     rax,rax
+  xor     rdx,rdx
+  rdtsc
+;set target time
+  add     eax,1500000000
+  adc     edx,0
+  shl     rdx,32
+  add     rdx,rax
+  mov     rbx,rdx
+;rbx store the target
+;set "Si!=0" skip below loop
+__loop:
+  cmp     si,0
+  jnz     __loopexit
+  rdtsc
+  shl     rdx,32
+  add     rdx,rax
+  cmp     rdx,rbx
+  jae     __loopexit
+  jmp     __loop
+__loopexit:
+  pop     rbx
+  pop     rdx
+  pop     rax
+  ret
+IdsDelay    ENDP
+;/*++
+;
+;Routine Description:
+;
+;  IdsErrorStop -- Function for Assert
+;
+;Arguments:
+;  Filecode
+;
+;Returns:
+;
+;  None
+;
+;--*/
+public IdsErrorStop
+IdsErrorStop PROC
+;As x64 calling convention RCX is used as input parameters
+  push    rcx
+  push    rbx
+  push    si
+  push    dx
+  push    rbx
+
+  mov     si,0                      ; Si is used as control flag, "Si!=0" skip postcode loop
+; send debug port 1st, then fire SimNow breakpoint
+  mov     ax,  0deadh
+  out     0e0h, ax
+  mov     eax, ecx
+  out     84h, eax
+  mov     eax, 0BACCD00Bh         ; Backdoor in SimNow
+  mov     ebx, 2                  ; Select breakpoint feature
+  cpuid
+
+  mov     rax,0dead00000000h
+  or      rcx,rax
+;rcx= 0dead__FILECODE
+  shl     rcx,16
+;rcx= 0dead__FILECODE__0000
+  mov     rbx,rcx
+
+  xor     rax,rax
+  mov     dl,6
+
+IdsErrorStopLoop:
+  cmp     dl,0
+  jz      IdsErrorStopExit
+  cmp     si,0
+  jnz     IdsErrorStopExit
+
+  shld    rax,rcx,8
+  shl     rcx,8
+  out     80h,eax
+  call    IdsDelay
+
+  dec     dl
+  cmp     dl,0
+  jnz     _nextloop
+  mov     dl,6
+  mov     rcx,rbx
+_nextloop:
+  jmp     IdsErrorStopLoop
+IdsErrorStopExit:
+  pop     rbx
+  pop     dx
+  pop     si
+  pop     rbx
+  pop     rcx
+  xor     rax,rax
+  ret
+IdsErrorStop  endp
+END
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c
new file mode 100755
index 0000000000..95bb50941a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Debug/IdsDebug.c
@@ -0,0 +1,1323 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "amdlib.h"
+#include "AMD.h"
+#include "heapManager.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_IDS_DEBUG_IDSDEBUG_FILECODE
+
+extern BUILD_OPT_CFG UserOptions;
+typedef struct _IDS_CONSOLE IDS_CONSOLE;
+
+/*--------------------------------------------------------------------------------------*/
+/**
+ *  IDS back-end code for AGESA_TESTPOINT
+ *
+ *  @param[in] TestPoint  Progress indicator value, see @ref AGESA_TP
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+/*--------------------------------------------------------------------------------------*/
+VOID
+IdsAgesaTestPoint (
+  IN       AGESA_TP      TestPoint,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PORT, &TestPoint, StdHeader);
+  IDS_PERF_TIMESTAMP (StdHeader, TestPoint);
+  if (TestPoint == EndAgesaTps) {
+    IDS_PERF_ANALYSE (StdHeader);
+  }
+}
+
+#define DEBUG_PRINT_INIT        0x10BF0000
+#define DEBUG_PRINT_EXIT        0xE0BF0000
+#define DEBUG_PRINT_COMMAND     0xC0BF0000
+#define DEBUG_PRINT_BREAKPOINT  0xB0BF0000
+#define DEBUG_PRINT_EVENT       0x1EBF0000
+
+#define IDS_HDTOUT_BPFLAG_FORMAT_STR   0
+#define IDS_HDTOUT_BPFLAG_STATUS_STR   1
+
+#define HDTOUT_BP_ACTION_HALT          1
+#define HDTOUT_BP_ACTION_PRINTON       2
+#define HDTOUT_BP_ACTION_PRINTONE      3
+#define HDTOUT_BP_ACTION_PRINTOFF      4
+
+typedef struct _BREAKPOINT_UNIT {
+  UINT8 AndFlag : 1;        ///< Next string is ANDed to current string
+  UINT8 BpFlag : 1;         ///< Format string or Status string
+  UINT8 Action : 4;         ///< Halt, start HDTOUT, or stop HDT,...
+  UINT8 BpStrOffset;        ///< Offset from BreakpointList to the breakpoint string
+} BREAKPOINT_UNIT;
+
+typedef enum {
+  IDS_STATE_OFF = 0xF0,
+  IDS_STATE_ON
+} IDS_STATE_TYPE;
+
+typedef enum {
+  NON_CONSOLE = 0xD0,
+  HDT_CONSOLE,
+  IDS_CONSOLE_END
+} IDS_CONSOLE_TYPE;
+
+// IDS HdtOut Event Level
+typedef enum {
+  EVENT_OFF = 0x30,              ///< Default,no event triggered.
+  EVENT_WARNING,                 ///< Event warning.
+  EVENT_ERROR,                   ///< Event error.
+  EVENT_FAIL_BUFFER_ALLOCATION,  ///< Reserved, fail buffer allocation
+  EVENT_END                   ///< Event end sentinel.
+} CONSOLE_EVENT_TYPE;
+
+#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
+
+//
+// Also support coding convention rules for var arg macros
+//
+typedef CHAR8 *VA_LIST;
+#define VA_START(ap, v) (ap = (VA_LIST) & (v) + _INT_SIZE_OF (v))
+#define VA_ARG(ap, t)   (*(t *) ((ap += _INT_SIZE_OF (t)) - _INT_SIZE_OF (t)))
+#define VA_END(ap)      (ap = (VA_LIST) 0)
+
+#define LEFT_JUSTIFY    0x01
+#define PREFIX_SIGN     0x02
+#define PREFIX_BLANK    0x04
+#define COMMA_TYPE      0x08
+#define LONG_TYPE       0x10
+#define PREFIX_ZERO     0x20
+
+/**
+ *  Create console context
+ *
+ *  Do hardware settings related with specific console context
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+typedef VOID F_CREATE_CONSOLE_CONTEXT (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  );
+/// Reference to a method.
+typedef F_CREATE_CONSOLE_CONTEXT *PF_CREATE_CONSOLE_CONTEXT;
+
+/**
+ *  Initialize console context
+ *
+ *  Initilize preference settings related with specific console context
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+typedef VOID F_INIT_CONSOLE_CONTEXT (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  );
+/// Reference to a method.
+typedef F_INIT_CONSOLE_CONTEXT *PF_INIT_CONSOLE_CONTEXT;
+
+/**
+ *  Update console context
+ *
+ *  Update preference settings related with specific console context
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+typedef VOID F_UPDATE_CONSOLE_CONTEXT (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  );
+/// Reference to a method.
+typedef F_UPDATE_CONSOLE_CONTEXT *PF_UPDATE_CONSOLE_CONTEXT;
+
+/**
+ *  Save console context
+ *
+ *  Save console context snapshot
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+typedef VOID F_SAVE_CONSOLE_CONTEXT (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  );
+/// Reference to a method.
+typedef F_SAVE_CONSOLE_CONTEXT *PF_SAVE_CONSOLE_CONTEXT;
+
+/**
+ *  Destroy console context
+ *
+ *  Destroy console context snapshot
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+typedef VOID F_DESTROY_CONSOLE_CONTEXT (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  );
+/// Reference to a method.
+typedef F_DESTROY_CONSOLE_CONTEXT *PF_DESTROY_CONSOLE_CONTEXT;
+
+/**
+ *  Print function
+ *
+ *  Print function related with specific console
+ *
+ *  @param[in] PrintType             Print Type
+ *  @param[in] ConsoleBufferAddress  The address of console buffer
+ *  @param[in] ConsoleBufferSize     The size of console buffer
+ *  @param[in,out] IdsConsole        The Pointer of IDS console
+ *
+ **/
+typedef VOID F_PRINT (
+  IN       UINT32 PrintType,
+  IN       UINT32 ConsoleBufferAddress,
+  IN       UINT32 ConsoleBufferSize,
+  IN OUT   IDS_CONSOLE *IdsConsole
+  );
+/// Reference to a method.
+typedef F_PRINT *PF_PRINT;
+
+/// IDS Console Operations
+typedef struct _IDS_CONSOLE_OPERATIONS {
+  PF_CREATE_CONSOLE_CONTEXT CreateConsoleContext;
+  PF_INIT_CONSOLE_CONTEXT InitConsoleContext;
+  PF_UPDATE_CONSOLE_CONTEXT UpdateConsoleContext;
+  PF_DESTROY_CONSOLE_CONTEXT DestroyConsoleContext;
+  PF_PRINT Print;
+} IDS_CONSOLE_OPERATIONS;
+
+/// IDS Console Header
+typedef struct _IDS_CONSOLE_HEADER {
+  UINT32 Signature;               ///< Signature information.
+  UINT32 Version;                 ///< Version.
+  UINT8  ConsoleType;             ///< Console type
+  UINT8  Event;                   ///< Event type.
+  UINT8  PrintState;              ///< On or Off
+  UINT8  OutBufferMode;           ///< Off:stack mode, On: heap mode
+  UINT16 OutBufferSize;           ///< Buffer size
+  UINT16 OutBufferIndex;          ///< Buffer index
+  UINT32 NumBreakpointUnit;       ///< default 0 no bp unit others number of bp unit
+} IDS_CONSOLE_HEADER;
+
+/// IDS Console
+struct _IDS_CONSOLE
+{
+  IDS_CONSOLE_HEADER Header;      /**< IDS console header - 5 dwords */
+  UINT32 FuncListAddr;            /**< 32 bit address to the list of functions that script can execute */
+  UINT8  Reserved[56 - 24];       /**< ----------------- New fields must be added here. */
+  CHAR8  BreakpointList[300];     /**< Breakpoint list */
+  CHAR8  StatusStr[156];          /**< Shows current node, DCT, CS,... */
+  CHAR8  OutBuffer[2];            /**< Console Out content. Its size will be determined by BufferSize. */
+};
+
+/**
+ *  Create hdt console context
+ *
+ *  Do hardware settings for hdt console context
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+STATIC VOID
+CreateHdtConsoleContext (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  )
+{
+  UINT64 SMsr;
+  UINT32 CR4reg;
+
+  LibAmdMsrRead (0xC001100A, (UINT64*)&SMsr, NULL);
+  SMsr |= 1;
+  LibAmdMsrWrite (0xC001100A, (UINT64*)&SMsr, NULL);
+
+  LibAmdWriteCpuReg (DR2_REG, 0x99CC);
+  LibAmdWriteCpuReg (DR7_REG, 0x02000420);
+
+  LibAmdReadCpuReg (CR4_REG, &CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
+}
+
+/**
+ *  Initialize hdt console context
+ *
+ *  Initilize preference settings for hdt console context
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+STATIC VOID
+InitHdtConsoleContext (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  )
+{
+  IDS_FUNCLIST_EXTERN ();
+
+  IdsConsole->FuncListAddr = (UINT32) IDS_FUNCLIST_ADDR;
+  IdsConsole->StatusStr[0] = 0;
+
+}
+
+/**
+ *  Update hdt console context
+ *
+ *  Update preference settings for hdt console context
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+STATIC VOID
+UpdateHdtConsoleContext (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  )
+{
+  if (IdsConsole->Header.OutBufferMode == IDS_STATE_OFF) {
+    IdsConsole->Header.OutBufferSize = 0;
+  }
+
+}
+
+/**
+ *  Destroy hdt console context
+ *
+ *  Save hdt console context snapshot
+ *
+ *  @param[in,out] IdsConsole    The Pointer of IDS console
+ *
+ **/
+STATIC VOID
+DestroyHdtConsoleContext (
+  IN OUT   IDS_CONSOLE *IdsConsole
+  )
+{
+  UINT64 SMsr;
+
+  LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, NULL);
+  SMsr &= ~BIT0;
+  LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, NULL);
+
+  LibAmdWriteCpuReg (DR2_REG, 0);
+  LibAmdWriteCpuReg (DR3_REG, 0);
+  LibAmdWriteCpuReg (DR7_REG, 0);
+}
+
+/**
+ *  Hdt console print function
+ *
+ *  Print function related with hdt console
+ *
+ *  @param[in] PrintType             Print Type
+ *  @param[in] ConsoleBufferAddress  The address of console buffer
+ *  @param[in] ConsoleBufferSize     The size of console buffer
+ *  @param[in,out] IdsConsole        The Pointer of IDS console
+ *
+ **/
+STATIC VOID
+HdtConsolePrint (
+  IN       UINT32 PrintType,
+  IN       UINT32 ConsoleBufferAddress,
+  IN       UINT32 ConsoleBufferSize,
+  IN OUT   IDS_CONSOLE *IdsConsole
+  )
+{
+  IdsOutPort (PrintType | 0x99CC, ConsoleBufferAddress, ConsoleBufferSize);
+}
+
+/// Initial construction data for HDT console header.
+CONST IDS_CONSOLE_HEADER ROMDATA HdtConsoleHeader =
+{
+ 0xDB1099CC,
+ 0x0100,
+ IDS_STATE_ON,
+ EVENT_OFF,
+ IDS_STATE_ON,
+ IDS_STATE_ON,
+ 0x1000,
+ 0x0,
+ 0,
+};
+
+#define OPTION_HDT_CONSOLE_HEADER &HdtConsoleHeader
+
+/// Initial construction data for HDT console operations.
+CONST IDS_CONSOLE_OPERATIONS ROMDATA HdtConsoleOperations =
+{
+ CreateHdtConsoleContext,
+ InitHdtConsoleContext,
+ UpdateHdtConsoleContext,
+ DestroyHdtConsoleContext,
+ HdtConsolePrint
+};
+
+#define OPTION_HDT_CONSOLE_OPERATIONS &HdtConsoleOperations
+
+/**
+ *  Parses flag and width information from theFormat string and returns the next index
+ *  into the Format string that needs to be parsed. See file headed for details of Flag and Width.
+ *
+ *  @param[in]  Format  Current location in the AvSPrint format string.
+ *  @param[out] Flags  Returns flags
+ *  @param[out] Width  Returns width of element
+ *  @param[out] Marker Vararg list that may be partially consumed and returned.
+ *
+ *  @retval Pointer indexed into the Format string for all the information parsed by this routine.
+ *
+ **/
+STATIC CHAR8 *
+GetFlagsAndWidth (
+  IN       CHAR8 *Format,
+     OUT   UINTN *Flags,
+     OUT   UINTN *Width,
+  IN OUT   VA_LIST *Marker
+  )
+{
+  UINTN   Count;
+  BOOLEAN Done;
+
+  *Flags = 0;
+  *Width = 0;
+  for (Done = FALSE; !Done; ) {
+    Format++;
+
+    switch (*Format) {
+
+    case '-':
+      *Flags |= LEFT_JUSTIFY;
+      break;
+    case '+':
+      *Flags |= PREFIX_SIGN;
+      break;
+    case ' ':
+      *Flags |= PREFIX_BLANK;
+      break;
+    case ',':
+      *Flags |= COMMA_TYPE;
+      break;
+    case 'L':
+    case 'l':
+      *Flags |= LONG_TYPE;
+      break;
+
+    case '*':
+      *Width = VA_ARG (*Marker, UINTN);
+      break;
+
+    case '0':
+      *Flags |= PREFIX_ZERO;
+      break;
+
+    case '1':
+    case '2':
+    case '3':
+    case '4':
+    case '5':
+    case '6':
+    case '7':
+    case '8':
+    case '9':
+      Count = 0;
+      do {
+        Count = (Count * 10) + *Format - '0';
+        Format++;
+      } while ((*Format >= '0')  &&  (*Format <= '9'));
+      Format--;
+      *Width = Count;
+      break;
+
+    default:
+      Done = TRUE;
+    }
+  }
+  return Format;
+}
+
+CHAR8 STATIC HexStr[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+/**
+ *
+ *  @param[in] Buffer Location to place ascii hex string of Value.
+ *  @param[in] Value  - Hex value to convert to a string in Buffer.
+ *  @param[in] Flags  - Flags to use in printing Hex string, see file header for details.
+ *  @param[in] Width  - Width of hex value.
+ *
+ *  @retval Number of characters printed.
+ **/
+
+STATIC UINTN
+ValueTomHexStr (
+  IN OUT   CHAR8   *Buffer,
+  IN       UINT64      Value,
+  IN       UINTN       Flags,
+  IN       UINTN       Width
+  )
+{
+  CHAR8   TempBuffer[30];
+  CHAR8   *TempStr;
+  CHAR8   Prefix;
+  CHAR8   *BufferPtr;
+  UINTN   Count;
+  UINTN   Index;
+
+  TempStr = TempBuffer;
+  BufferPtr = Buffer;
+  //
+  // Count starts at one since we will null terminate. Each iteration of the
+  // loop picks off one nibble. Oh yea TempStr ends up backwards
+  //
+  Count = 0;
+  do {
+    *(TempStr++) = HexStr[Value & 0x0f];
+    Value >>= 4;
+    Count++;
+  } while (Value != 0);
+
+  if (Flags & PREFIX_ZERO) {
+    Prefix = '0';
+  } else if (!(Flags & LEFT_JUSTIFY)) {
+    Prefix = ' ';
+  } else {
+    Prefix = 0x00;
+  }
+  for (Index = Count; Index < Width; Index++) {
+    *(TempStr++) = Prefix;
+  }
+
+  //
+  // Reverse temp string into Buffer.
+  //
+  while (TempStr != TempBuffer) {
+    *(BufferPtr++) = *(--TempStr);
+  }
+
+  *BufferPtr = 0;
+  return Index;
+}
+
+/**
+ *  Prints a Value as a decimal number in Buffer
+ *
+ *  @param[in] Buffer  Location to place ascii decimal number string of Value.
+ *  @param[in] Value  Decimal value to convert to a string in Buffer.
+ *  @param[in] Flags  Flags to use in printing decimal string, see file header for details.
+ *
+ *  @retval Number of characters printed.
+ *
+**/
+
+STATIC UINTN
+ValueToString (
+  IN OUT   CHAR8   *Buffer,
+  IN       INT32       Value,
+  IN       UINTN       Flags
+  )
+{
+  CHAR8   TempBuffer[30];
+  CHAR8   *TempStr;
+  CHAR8   *BufferPtr;
+  UINTN   Count;
+  UINTN   Remainder;
+
+  TempStr = TempBuffer;
+  BufferPtr = Buffer;
+  Count = 0;
+
+  if (Value < 0) {
+    *(BufferPtr++) = '-';
+    Value = - Value;
+    Count++;
+  }
+
+  do {
+    Remainder = Value % 10;
+    Value /= 10;
+    *(TempStr++) = (CHAR8)(Remainder + '0');
+    Count++;
+    if ((Flags & COMMA_TYPE) == COMMA_TYPE) {
+      if (Count % 3 == 0) {
+        *(TempStr++) = ',';
+      }
+    }
+  } while (Value != 0);
+
+  //
+  // Reverse temp string into Buffer.
+  //
+  while (TempStr != TempBuffer) {
+    *(BufferPtr++) = *(--TempStr);
+  }
+
+  *BufferPtr = 0;
+  return Count;
+}
+
+/**
+ *  Check if String contain the substring
+ *
+ *  @param[in] String  Pointer of string.
+ *  @param[in] Substr  Pointer of sub string.
+ *
+ *  @retval TRUE S2 is substring of S1
+ *  @retval FALSE S2 isn't substring of S1
+ *
+**/
+STATIC BOOLEAN
+AmdIdsSubStr (
+  IN      CHAR8 *String,
+  IN      CHAR8 *Substr
+  )
+{
+  UINT16 i;
+  UINT16 j;
+
+  for (i = 0; String[i] != 0 ; i++) {
+    for (j = 0; (Substr[j] != 0) && (Substr[j] == String[i + j]); j++) {
+    }
+    if (Substr[j] == 0) {
+      return TRUE;
+    }
+  }
+
+  return FALSE;
+}
+
+/**
+ *  IDS Backend Function for Memory timeout control
+ *
+ *  This function is used to override Memory timeout control.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of UINT8.
+ *
+ **/
+VOID
+IdsMemTimeOut (
+  IN OUT   VOID *DataPtr
+  )
+{
+  UINT32 DR2reg;
+
+  LibAmdReadCpuReg (DR2_REG, &DR2reg);
+  if (DR2reg == 0x99CC) {
+    // Turn timeout off if HDTout is on
+    *((UINT8 *)DataPtr) = (UINT8)0;
+  }
+}
+
+/**
+ *
+ *  IDS Debug Function to check the sentinels are intact
+ *
+ * This function complete heap walk and check to be performed at any time.
+ *
+ * @param[in]      StdHeader         Config handle for library and services.
+ *
+ * @retval         TRUE     No error
+ *
+ **/
+BOOLEAN
+AmdHeapIntactCheck (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8       *HeapBufferPtr;
+  BUFFER_NODE       *StartOfBufferPtr;
+  BUFFER_NODE       *EndOfBufferPtr;
+  HEAP_MANAGER *HeapManagerPtr;
+  BUFFER_NODE *HeadNodePtr;
+  BUFFER_NODE *CurrentNodePtr;
+  UINT32  AmdHeapRamAddress;
+  UINT32 SentinelBefore;
+  UINT32 SentinelAfter;
+
+  ASSERT (StdHeader != NULL);
+
+  AmdHeapRamAddress = (UINT32)UserOptions.CfgHeapDramAddress;
+
+  if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) {
+    HeapBufferPtr = (UINT8 *) HeapGetCurrentBase (StdHeader);
+  } else if (StdHeader->HeapStatus == HEAP_TEMP_MEM) {
+    HeapBufferPtr = (UINT8 *) AmdHeapRamAddress;
+  } else {
+    return TRUE;
+  }
+
+  HeapManagerPtr = (HEAP_MANAGER *) HeapBufferPtr;
+  HeadNodePtr = (BUFFER_NODE *) (HeapBufferPtr + sizeof (HEAP_MANAGER));
+  CurrentNodePtr = HeadNodePtr;
+
+  if (HeapManagerPtr->AvailableSize != AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER)) {
+    while (CurrentNodePtr != NULL) {
+      StartOfBufferPtr = (BUFFER_NODE *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE) + CurrentNodePtr->BufferSize + 2 * SIZE_OF_SENTINEL);
+      EndOfBufferPtr = (BUFFER_NODE *) ((UINT8 *) HeadNodePtr + AMD_HEAP_SIZE_PER_CORE);
+      if (CurrentNodePtr->NextNodePtr != NULL) {
+        ASSERT ((CurrentNodePtr->NextNodePtr >= StartOfBufferPtr) && (CurrentNodePtr->NextNodePtr < EndOfBufferPtr));
+        SentinelBefore = *(UINT32 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE));
+        SentinelAfter = *(UINT32 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + CurrentNodePtr->BufferSize);
+
+        ASSERT ((SentinelBefore == SENTINEL_BEFORE_VALUE) && (SentinelAfter == SENTINEL_AFTER_VALUE));
+      } else {
+        ASSERT ((UINT8 *) StartOfBufferPtr == HeapBufferPtr + AMD_HEAP_SIZE_PER_CORE - HeapManagerPtr->AvailableSize);
+        SentinelBefore = *(UINT32 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE));
+        SentinelAfter = *(UINT32 *) ((UINT8 *) CurrentNodePtr + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + CurrentNodePtr->BufferSize);
+        ASSERT ((SentinelBefore == SENTINEL_BEFORE_VALUE) && (SentinelAfter == SENTINEL_AFTER_VALUE));
+      }
+      CurrentNodePtr = CurrentNodePtr->NextNodePtr;
+    }
+  }
+  return TRUE;
+}
+
+/**
+ *  Determine whether IDS console is enabled.
+ *
+ *  @param[in,out] IdsConsole    The Pointer of Ids console data
+ *
+ *  @retval       TRUE    Ids console is enabled.
+ *  @retval       FALSE   Ids console is disabled.
+ *
+ **/
+BOOLEAN
+STATIC
+IsIdsConsoleEnabled (
+  IN OUT   UINTN *IdsConsole
+  )
+{
+  BOOLEAN Result;
+  UINT32  DR2reg;
+
+  Result = FALSE;
+
+  LibAmdReadCpuReg (DR2_REG, &DR2reg);
+  if (DR2reg == 0x99CC) {
+    Result = TRUE;
+  }
+
+  return Result;
+}
+
+/**
+ *  Get IDS console.
+ *
+ *  @param[in,out] IdsConsolePtr  The Pointer of Ids console data
+ *
+ **/
+STATIC VOID
+GetIdsConsole (
+  IN OUT   UINTN *IdsConsolePtr
+  )
+{
+  UINT32 DR3Reg;
+
+  LibAmdReadCpuReg (DR3_REG, &DR3Reg);
+  *IdsConsolePtr = (UINTN) DR3Reg;
+}
+
+/**
+ *  Get IDS console operations.
+ *
+ *  @param[in,out] IdsConsoleOperations  The Pointer of Ids console operations
+ *
+ **/
+STATIC VOID
+GetIdsConsoleHeader (
+  IN OUT   UINTN *IdsConsoleHeader
+  )
+{
+  IDS_CONSOLE_TYPE IdsConsoleType;
+
+  IdsConsoleType = (IDS_CONSOLE_TYPE) OPTION_IDS_CONSOLE;
+
+  if (IdsConsoleType == HDT_CONSOLE) {
+    *IdsConsoleHeader = (UINTN) OPTION_HDT_CONSOLE_HEADER;
+  } else {
+    ASSERT (FALSE);
+  }
+}
+
+/**
+ *  Get IDS console operations.
+ *
+ *  @param[in,out] IdsConsoleOperations  The Pointer of Ids console operations
+ *
+ **/
+STATIC VOID
+GetIdsConsoleOperations (
+  IN OUT   UINTN *IdsConsoleOperations
+  )
+{
+  IDS_CONSOLE_TYPE IdsConsoleType;
+
+  IdsConsoleType = (IDS_CONSOLE_TYPE) OPTION_IDS_CONSOLE;
+
+  if (IdsConsoleType == HDT_CONSOLE) {
+    *IdsConsoleOperations = (UINTN) OPTION_HDT_CONSOLE_OPERATIONS;
+  } else {
+    ASSERT (FALSE);
+  }
+}
+
+/**
+ *  Create IDS console.
+ *
+ *  @param[in,out] IdsConsole    The Pointer of Ids console data
+ *  @param[in,out] StdHeader     The Pointer of AGESA Header
+ **/
+STATIC VOID
+NewIdsConsole (
+  IN OUT   IDS_CONSOLE *IdsConsole,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_CONSOLE_HEADER *IdsConsoleHeader;
+  UINTN IdsConsoleHeaderPtr;
+
+  GetIdsConsoleHeader (&IdsConsoleHeaderPtr);
+  IdsConsoleHeader = &(IdsConsole->Header);
+
+  LibAmdMemCopy ((VOID *)IdsConsoleHeader, (VOID *) (IdsConsoleHeaderPtr), (UINT32) sizeof (IDS_CONSOLE_HEADER), StdHeader);
+}
+
+/**
+ *  Destroy IDS console.
+ *
+ *  @param[in,out] IdsConsole    The Pointer of Ids console data
+ *  @param[in,out] StdHeader     The Pointer of AGESA Header
+ **/
+STATIC VOID
+DestroyIdsConsole (
+  IN OUT   IDS_CONSOLE *IdsConsole,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  HeapDeallocateBuffer (IDS_HDT_OUT_BUFFER_HANDLE, StdHeader);
+}
+
+/**
+ *  Save IDS console Snapshot.
+ *
+ *  @param[in,out] IdsConsole    The Pointer of Ids console data
+ *  @param[in,out] StdHeader     The Pointer of AGESA Header
+ **/
+STATIC VOID
+SaveIdsConsole (
+  IN OUT   IDS_CONSOLE *IdsConsole,
+  IN OUT   IDS_CONSOLE_OPERATIONS *IdsConsoleOps,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  do {
+    AllocHeapParams.RequestedBufferSize = IdsConsole->Header.OutBufferSize + sizeof (IDS_CONSOLE) - 2;
+    AllocHeapParams.BufferHandle = IDS_HDT_OUT_BUFFER_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+      break;
+    } else {
+      IdsConsole->Header.OutBufferSize -= 256;
+      IdsConsole->Header.Event = EVENT_FAIL_BUFFER_ALLOCATION;
+      IdsConsoleOps->Print (DEBUG_PRINT_EVENT, (UINT32)IdsConsole, 0, IdsConsole);
+    }
+  } while ((IdsConsole->Header.OutBufferSize & 0x8000) == 0);
+
+  if ((IdsConsole->Header.OutBufferSize & 0x8000) == 0) {
+    LibAmdWriteCpuReg (DR3_REG, (UINT32)AllocHeapParams.BufferPtr);
+    LibAmdMemCopy (AllocHeapParams.BufferPtr, (VOID *) IdsConsole, (UINT32) sizeof (IDS_CONSOLE) - 2, StdHeader);
+  }
+}
+
+/**
+ *
+ *  Initial function for IDS console.
+ *
+ *  Create IDS console context, let Ids console function to be ready.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsConsoleInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_CONSOLE IdsConsole;
+  IDS_CONSOLE_OPERATIONS *IdsConsoleOps;
+  UINTN IdsConsolePtr;
+  UINTN IdsConsoleOpsPtr;
+
+  if (IsIdsConsoleEnabled (&IdsConsolePtr)) {
+    GetIdsConsoleOperations (&IdsConsoleOpsPtr);
+    IdsConsoleOps = (IDS_CONSOLE_OPERATIONS *) IdsConsoleOpsPtr;
+    NewIdsConsole (&IdsConsole, StdHeader);
+
+    IdsConsoleOps->CreateConsoleContext (&IdsConsole);
+    IdsConsoleOps->InitConsoleContext (&IdsConsole);
+    IdsConsoleOps->Print (DEBUG_PRINT_INIT, (UINT32)&IdsConsole, 0, &IdsConsole);
+    IdsConsoleOps->UpdateConsoleContext (&IdsConsole);
+
+    SaveIdsConsole (&IdsConsole, IdsConsoleOps, StdHeader);
+  }
+}
+
+/**
+ *  Prints string to debug host like printf in C
+ *
+ *  @param[in] Format of string
+ *  @param[in] ... Variable parameter
+ *
+**/
+VOID
+AmdIdsConsolePrint (
+  IN      CHAR8 *Format,
+  IN      ...
+  )
+{
+  IDS_CONSOLE *IdsConsole;
+  UINTN IdsConsolePtr;
+  IDS_CONSOLE_OPERATIONS *IdsConsoleOps;
+  UINTN  IdsConsoleOpsPtr;
+  VA_LIST Marker;
+  CHAR8 LocalBuffer[256];
+  CHAR8 *ConsoleBuffer;
+  CHAR8 Null_Str[] = " < null string > ";
+  CHAR8 *AsciiStr;
+  UINTN Index;
+  UINTN Flags;
+  UINTN Width;
+  UINTN ConsoleBufferSize;
+  UINT64 Value;
+  UINT16 *Array;
+  UINT32 ArrayLength;
+  UINT32 ArrayIndex;
+  BOOLEAN SaveStatus;
+  UINT32 LastIndex;
+  UINT32 i;
+  UINT32 j;
+  UINT32 NumBpUnit;
+  BREAKPOINT_UNIT *Pbpunit;
+  CHAR8 *Pbpstr;
+  CHAR8 *PCmpStr;
+  CHAR8 *EventLevelStr;
+  BOOLEAN LastBpmatched;
+  BOOLEAN Bpmatched;
+  IDS_STATE_TYPE PrintCtrl;
+
+  //Init the default Value
+  IdsConsole = NULL;
+  IdsConsolePtr = 0;
+  ConsoleBuffer = LocalBuffer;
+  Index = 0;
+  LastIndex = 0;
+  ConsoleBufferSize = 256;
+  NumBpUnit = 0;
+  PrintCtrl = IDS_STATE_ON;
+
+  if (IsIdsConsoleEnabled (&IdsConsolePtr)) {
+    GetIdsConsole (&IdsConsolePtr);
+    IdsConsole = (IDS_CONSOLE *) IdsConsolePtr;
+    GetIdsConsoleOperations (&IdsConsoleOpsPtr);
+    IdsConsoleOps = (IDS_CONSOLE_OPERATIONS *) IdsConsoleOpsPtr;
+
+    if (IdsConsole->Header.OutBufferMode == IDS_STATE_ON) {
+      ConsoleBuffer = IdsConsole->OutBuffer;
+      Index = IdsConsole->Header.OutBufferIndex;
+      ConsoleBufferSize = (UINTN) (IdsConsole->Header.OutBufferSize);
+      NumBpUnit = IdsConsole->Header.NumBreakpointUnit;
+      PrintCtrl = IdsConsole->Header.PrintState;
+    }
+
+    if ((PrintCtrl != 0) || (NumBpUnit > 0)) {
+      VA_START(Marker,Format); //init marker to 1st dynamic parameters.
+
+      LastIndex = (UINT32) Index;
+
+      if (*Format != '@') {
+        if (*Format == '!') {
+          SaveStatus = TRUE;
+          Format++;
+        } else {
+          SaveStatus = FALSE;
+        }
+
+        for (; *Format != '\0'; Format++) {
+          if (*Format != '%') {
+            ConsoleBuffer[Index++] = *Format;
+          } else {
+            Format = GetFlagsAndWidth (Format, &Flags, &Width, &Marker);
+            switch (*Format) {
+            // Using %[EventType] style to catch predefined event.
+            case '[':
+              EventLevelStr = Format;
+              EventLevelStr++;
+              if ((*EventLevelStr > EVENT_OFF) && (*EventLevelStr < EVENT_END)) {
+                EventLevelStr++;
+                if (*EventLevelStr == ']') {
+                  EventLevelStr--;
+                  IdsConsole->Header.Event = (UINT8) (CONSOLE_EVENT_TYPE) (*EventLevelStr);
+                }
+              }
+              break;
+            case 'X':
+              Flags |= PREFIX_ZERO;
+              Width = sizeof (UINT64) * 2;
+              //
+              // break skipped on purpose
+              //
+            case 'x':
+              if ((Flags & LONG_TYPE) == LONG_TYPE) {
+                Value = VA_ARG (Marker, UINT64);
+              } else {
+                Value = VA_ARG (Marker, UINTN);
+              }
+              Index += ValueTomHexStr (&ConsoleBuffer[Index], Value, Flags, Width);
+              break;
+
+            case 'd':
+              Value = (UINTN)VA_ARG (Marker, UINT32);
+              Index += ValueToString (&ConsoleBuffer[Index], (UINT32)Value, Flags);
+              break;
+
+            case 's':
+            case 'S':
+              AsciiStr = (CHAR8 *)VA_ARG (Marker, CHAR8 *);
+              if (AsciiStr == NULL) {
+                AsciiStr = Null_Str; //" < null string > ";
+              }
+              while (*AsciiStr != '\0') {
+                ConsoleBuffer[Index++] = *AsciiStr++;
+              }
+              break;
+
+            case 'c':
+              ConsoleBuffer[Index++] = (CHAR8)VA_ARG (Marker, UINTN);
+              break;
+
+            case 'a':
+              Array = (UINT16 *) VA_ARG (Marker, VOID *);
+              ArrayLength = (UINT32) VA_ARG (Marker, UINT32);
+              for (ArrayIndex = 0; ArrayIndex < ArrayLength; ArrayIndex++) {
+                // Only support hex format of an array of UINT16 for now.
+                Width = 2;
+                Flags = PREFIX_ZERO;
+                ConsoleBuffer[Index++] = ' ';
+                Index += ValueTomHexStr (&ConsoleBuffer[Index], Array[ArrayIndex] & 0xFF, Flags, Width);
+
+                // If buffer is full
+                if (Index > (ConsoleBufferSize - 8)) {
+                  if (IdsConsole != NULL) {
+                    if (LastIndex != 0) {
+                      // Stream all out except current string
+                      if (PrintCtrl != 0) {
+                        IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)ConsoleBuffer, LastIndex, IdsConsole);
+                      }
+                      Index = Index - LastIndex;
+                      // Move current string too top
+                      for (i = 0; i < Index; i++) {
+                        ConsoleBuffer[i] = ConsoleBuffer[LastIndex + i];
+                      }
+                      LastIndex = 0;
+                    } else {
+                      // Buffer size is too small
+                      ASSERT (FALSE);
+                    }
+                  } else {
+                    break;
+                  }
+                }
+              }
+              break;
+
+            case 'v':
+              ConsoleBuffer[Index++] = '%';
+              ConsoleBuffer[Index++] = 'v';
+              Format++;
+              ConsoleBuffer[Index++] = *Format;
+              if (*Format == 'h') {
+                Format++;
+                ConsoleBuffer[Index++] = *Format;
+              }
+              break;
+
+            case '%':
+              ConsoleBuffer[Index++] = *Format;
+              break;
+
+            default:
+              //
+              // if the type is unknown print it to the screen
+              //
+              ConsoleBuffer[Index++] = '%';
+              ConsoleBuffer[Index++] = *Format;
+            }
+          }
+
+          // If buffer is full
+          if (Index > (ConsoleBufferSize - 32)) {
+            if (IdsConsole != NULL) {
+              if (LastIndex != 0) {
+                // Stream all out except current string
+                if (PrintCtrl != IDS_STATE_OFF) {
+                  IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)ConsoleBuffer, LastIndex, IdsConsole);
+                }
+                Index = Index - LastIndex;
+                // Move current string too top
+                for (i = 0; i < Index; i++) {
+                  ConsoleBuffer[i] = ConsoleBuffer[LastIndex + i];
+                }
+                LastIndex = 0;
+              } else {
+                // Buffer size is too small
+                ASSERT (FALSE);
+              }
+            } else {
+              break;
+            }
+          }
+        }
+
+        if (IdsConsole->Header.OutBufferMode == IDS_STATE_OFF) {
+          IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)ConsoleBuffer, (UINT32) Index, IdsConsole);
+          Index = 0;
+        }
+
+        if ((IdsConsole->Header.Event > EVENT_OFF) && (IdsConsole->Header.Event < EVENT_END) ) {
+          // if HdtOut Buffer is on, flush hdtout buffer contents out.
+          if (IdsConsole->Header.OutBufferMode == IDS_STATE_ON) {
+            IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)ConsoleBuffer, (UINT32) Index, IdsConsole);
+            Index = 0;
+          }
+
+          IdsConsoleOps->Print (DEBUG_PRINT_EVENT, (UINT32)IdsConsole, 0, IdsConsole);
+          IdsConsole->Header.Event = EVENT_OFF;
+        }
+
+        //
+        //  Check breakpoint
+        //
+        if (NumBpUnit) {
+          Pbpunit = (BREAKPOINT_UNIT *) IdsConsole->BreakpointList;
+          LastBpmatched = TRUE;
+          Bpmatched = TRUE;
+          for (i = 0; i < NumBpUnit; i++) {
+            Pbpstr = IdsConsole->BreakpointList + Pbpunit[i].BpStrOffset;
+            if (Pbpunit[i].BpFlag == IDS_HDTOUT_BPFLAG_FORMAT_STR) {
+              PCmpStr = &ConsoleBuffer[LastIndex];
+              ConsoleBuffer[Index] = 0;
+            } else {
+              PCmpStr = IdsConsole->StatusStr;
+            }
+
+            if (LastBpmatched) {
+              Bpmatched = AmdIdsSubStr (PCmpStr, Pbpstr);
+              if (Bpmatched) {
+                if (Pbpunit[i].AndFlag == 0) {
+                  // This is the last of matching string of an AND block, apply action here
+                  switch (Pbpunit[i].Action) {
+                  case HDTOUT_BP_ACTION_HALT:
+                    IdsConsoleOps->Print (DEBUG_PRINT_BREAKPOINT, (UINT32)(ConsoleBuffer + LastIndex), ( i << 16) | (UINT32) Index, IdsConsole);
+                    break;
+                  case HDTOUT_BP_ACTION_PRINTON:
+                    PrintCtrl = IDS_STATE_ON;
+                    IdsConsole->Header.PrintState = IDS_STATE_ON;
+                    break;
+                  case HDTOUT_BP_ACTION_PRINTOFF:
+                    if (IdsConsole->Header.PrintState != IDS_STATE_OFF) {
+                      IdsConsole->Header.PrintState = IDS_STATE_OFF;
+                      IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)ConsoleBuffer, (UINT32)Index, IdsConsole);
+                    }
+                    break;
+                  default:
+                    ASSERT (FALSE);
+                  }
+                  break;
+                }
+              }
+            }
+            if (Pbpunit[i].AndFlag == 1) {
+              LastBpmatched = Bpmatched;
+            } else {
+              LastBpmatched = TRUE;
+            }
+          }
+        }
+
+        //
+        //  Store status fields
+        //
+        if (SaveStatus) {
+          // Look for the start of the first word
+          for (; LastIndex < Index; LastIndex++) {
+            if ((ConsoleBuffer[LastIndex] > 32) && (ConsoleBuffer[LastIndex] < 127)) {
+              break;
+            }
+          }
+          if (LastIndex < Index) {
+            // Match the first word in StatusStr
+            SaveStatus = FALSE;
+            j = LastIndex;
+            for (i = 0; !SaveStatus && (IdsConsole->StatusStr[i] != 0); i++) {
+              ArrayLength = 1;
+              for (j = LastIndex; ConsoleBuffer[j] == IdsConsole->StatusStr[i]; j++) {
+                i++;
+                ArrayLength++;
+                if ((j == (Index - 1)) || (ConsoleBuffer[j] == ' ')) {
+                  // Find the length of this entry
+                  ArrayIndex = i;
+                  for (; IdsConsole->StatusStr[i] != '\n'; i++) {
+                    ArrayLength++;
+                  }
+
+                  // Remove old entry if it does not fit
+                  if (ArrayLength != ((UINT32) Index - LastIndex)) {
+                    for (i++; IdsConsole->StatusStr[i] != 0; i++) {
+                      IdsConsole->StatusStr[i - ArrayLength] = IdsConsole->StatusStr[i];
+                    }
+                    j = LastIndex;
+                    i = i - ArrayLength - 1;
+                    // Mark the end of string
+                    IdsConsole->StatusStr[i + ((UINT32) Index - LastIndex) + 1] = 0;
+                  } else {
+                    i = ArrayIndex - 2;
+                  }
+
+                  // Word match, exit for saving
+                  SaveStatus = TRUE;
+                  break;
+                }
+              }
+            }
+
+            // Copy string to StatusStr
+            for (; j < Index; j++, i++) {
+              IdsConsole->StatusStr[i] = ConsoleBuffer[j];
+            }
+            if (!SaveStatus) {
+              // Mark the end of string if not done so
+              IdsConsole->StatusStr[i] = 0;
+            }
+          }
+        }
+
+      }
+    }
+
+    if (IdsConsole != NULL) {
+      if (IdsConsole->Header.PrintState == IDS_STATE_OFF) {
+        Index = 0;    // Clear buffer if the data will not be printed out.
+      }
+      IdsConsole->Header.OutBufferIndex = (UINT16) Index;
+    } else {
+      IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)ConsoleBuffer, (UINT32)Index, IdsConsole);
+    }
+  }
+}
+
+/**
+ *
+ *  Exit function for IDS console Function.
+ *
+ *  Restore debug register and Deallocate heap.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+VOID
+AmdIdsConsoleExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_CONSOLE *IdsConsole;
+  UINTN IdsConsolePtr;
+  IDS_CONSOLE_OPERATIONS *IdsConsoleOps;
+  UINTN  IdsConsoleOpsPtr;
+
+  if (IsIdsConsoleEnabled (&IdsConsolePtr)) {
+    GetIdsConsole (&IdsConsolePtr);
+    IdsConsole = (IDS_CONSOLE *) IdsConsolePtr;
+    GetIdsConsoleOperations (&IdsConsoleOpsPtr);
+    IdsConsoleOps = (IDS_CONSOLE_OPERATIONS *) IdsConsoleOpsPtr;
+
+    if (IdsConsole != NULL) {
+      if (IdsConsole->Header.PrintState != IDS_STATE_OFF) {
+        IdsConsoleOps->Print (DEBUG_PRINT_COMMAND, (UINT32)(IdsConsole->OutBuffer), IdsConsole->Header.OutBufferIndex, IdsConsole);
+      }
+
+      IdsConsoleOps->Print (DEBUG_PRINT_EXIT, (UINT32)IdsConsole, 0, IdsConsole);
+
+      IdsConsoleOps->DestroyConsoleContext (IdsConsole);
+      DestroyIdsConsole (IdsConsole, StdHeader);
+
+    }
+  }
+}
+/**
+ * Check for CAR Corruption, the performance monitor number three programed to log the CAR Corruption.
+ * Check to see if control register is enabled and then check the preformance counter and stop the system by executing
+ * IDS_ERROR_TRAP if counter has any value other than zero.
+ *
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *
+ **/
+VOID
+IdsCarCorruptionCheck (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+
+  UINT64 Perf_Msr;
+
+  LibAmdMsrRead (MSR_PERF_CONTROL3, (UINT64*)&Perf_Msr, StdHeader);
+  if ((Perf_Msr & PERF_RESERVE_BIT_MASK) == PERF_CAR_CORRUPTION_EVENT) {
+    LibAmdMsrRead (MSR_PERF_COUNTER3, (UINT64*)&Perf_Msr, StdHeader);
+    if ((Perf_Msr != 0)) {
+      IDS_ERROR_TRAP;
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c
new file mode 100755
index 0000000000..4fe4ae3e42
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.c
@@ -0,0 +1,52 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for BL
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "IdsF10BLService.h"
+#include "Filecode.h"
+#define FILECODE PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.h
new file mode 100755
index 0000000000..e9fcc68636
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/BL/IdsF10BLService.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _IDS_F10_BLSERVICE_H_
+#define _IDS_F10_BLSERVICE_H_
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c
new file mode 100755
index 0000000000..7fa17e248d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.c
@@ -0,0 +1,53 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for DA
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "IdsF10DAService.h"
+#include "Filecode.h"
+#define FILECODE PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.h
new file mode 100755
index 0000000000..6363a1cf4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/DA/IdsF10DAService.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _IDS_F10_DASERVICE_H_
+#define _IDS_F10_DASERVICE_H_
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.c
new file mode 100755
index 0000000000..910744f1ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.c
@@ -0,0 +1,173 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for HY
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "IdsF10HYService.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE
+
+/**
+ *  IDS Backend Function for Probe Filter
+ *
+ *  This function is used to Enable or Disable Probe Filter.
+ *
+ *  @param[in,out]   DataPtr  The Pointer of PLATFORM_CONFIGURATION.
+ *  @param[in,out]   StdHeader       The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]       IdsNvPtr        The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubProbeFilter (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  IDS_STATUS idsvalue;
+  PLATFORM_CONFIGURATION *PlatformConfig;
+
+  PlatformConfig = (PLATFORM_CONFIGURATION *) DataPtr;
+//For SetRegistersFromTables in AmdCpuEarly will refer to probefilter status
+//So we will let it know the status such as others
+  IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_PROBEFILTER, IdsNvPtr) {
+    switch (idsvalue) {
+    case (IDS_STATUS) 0x1:
+      PlatformConfig->PlatformProfile.UseHtAssist = FALSE;
+      break;
+    case (IDS_STATUS) 0x2:
+      PlatformConfig->PlatformProfile.UseHtAssist = TRUE;
+      break;
+    default:
+      break;
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+/**
+ *  IDS Backend Function for Probe Filter ealry before
+ *
+ *  This function is used to Enable or Disable Probe Filter.
+ *
+ *  @param[in,out]   DataPtr  The Pointer of PLATFORM_CONFIGURATION.
+ *  @param[in,out]   StdHeader       The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]       IdsNvPtr        The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubProbeFilterEarlyBefore (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_EARLY_PARAMS * EarlyParams;
+
+  EarlyParams = (AMD_EARLY_PARAMS *)DataPtr;
+  return IdsSubProbeFilter (&EarlyParams->PlatformConfig, StdHeader, IdsNvPtr);
+}
+
+
+/**
+ *  IDS Backend Function for Probe Filter Late before
+ *
+ *  This function is used to Enable or Disable Probe Filter.
+ *
+ *  @param[in,out]   DataPtr  The Pointer of PLATFORM_CONFIGURATION.
+ *  @param[in,out]   StdHeader       The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]       IdsNvPtr        The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubProbeFilterLateBefore (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  AMD_LATE_PARAMS * LateParams;
+
+  LateParams = (AMD_LATE_PARAMS *)DataPtr;
+  return IdsSubProbeFilter (&LateParams->PlatformConfig, StdHeader, IdsNvPtr);
+}
+
+CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockPlatformCfg =
+{
+  IDS_FEAT_PROBE_FILTER,
+  IDS_ALL_CORES,
+  IDS_PLATFORMCFG_OVERRIDE,
+  AMD_FAMILY_10_HY,
+  IdsSubProbeFilter
+};
+
+CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockEarlyBefore =
+{
+  IDS_FEAT_PROBE_FILTER,
+  IDS_ALL_CORES,
+  IDS_INIT_EARLY_BEFORE,
+  AMD_FAMILY_10_HY,
+  IdsSubProbeFilterEarlyBefore
+};
+
+CONST IDS_FEAT_STRUCT ROMDATA IdsFeatProbeFilterBlockLateBefore =
+{
+  IDS_FEAT_PROBE_FILTER,
+  IDS_ALL_CORES,
+  IDS_INIT_LATE_BEFORE,
+  AMD_FAMILY_10_HY,
+  IdsSubProbeFilterLateBefore
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.h
new file mode 100755
index 0000000000..668a71afcf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/HY/IdsF10HYService.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _IDS_F10_HYSERVICE_H_
+#define _IDS_F10_HYSERVICE_H_
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.c
new file mode 100755
index 0000000000..422084fe33
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.c
@@ -0,0 +1,132 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for common F10
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "cpuFamilyTranslation.h"
+#include "IdsF10AllService.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE
+
+
+/**
+ *  IDS F10 Backend Function for ECC Controls
+ *
+ *  This function is used to override ECC control Parameter.
+ *
+ *  @param[in,out]   DataPtr      The Pointer of AMD_POST_PARAMS.
+ *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS.
+ *  @param[in]     IdsNvPtr     The Pointer of NV Table.
+ *
+ *  @retval IDS_SUCCESS         Backend function is called successfully.
+ *  @retval IDS_UNSUPPORTED     No Backend function is found.
+ *
+ **/
+IDS_STATUS
+IdsSubEccControlF10 (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  )
+{
+  ECC_OVERRIDE_STRUCT * PeccOverStruct;
+  IDS_STATUS ids_value;
+
+  PeccOverStruct = (ECC_OVERRIDE_STRUCT *)DataPtr;
+
+  IDS_NV_READ_SKIP (ids_value, AGESA_IDS_NV_SCRUB_REDIRECTION, IdsNvPtr) {
+    PeccOverStruct->CfgEccRedirection = (BOOLEAN) ids_value;
+  }
+
+  IDS_NV_READ_SKIP (ids_value, AGESA_IDS_NV_SYNC_ON_ECC_ERROR, IdsNvPtr) {
+    PeccOverStruct->CfgEccSyncFlood = (BOOLEAN) ids_value;
+  }
+
+  IDS_NV_READ_SKIP (ids_value, AGESA_IDS_NV_DRAM_SCRUB, IdsNvPtr) {
+    if (ids_value == IDS_F10_SCRUB_DIS) {
+      PeccOverStruct->CfgScrubDramRate = 0;
+    } else if ((ids_value <= IDS_F10_SCRUB_84MS) && (ids_value >= IDS_F10_SCRUB_40NS)) {
+      PeccOverStruct->CfgScrubDramRate = (UINT16) (ids_value - 1);
+    }
+  }
+
+  IDS_NV_READ_SKIP (ids_value, AGESA_IDS_NV_L2_SCRUB, IdsNvPtr) {
+    if (ids_value == IDS_F10_SCRUB_DIS) {
+      PeccOverStruct->CfgScrubL2Rate = 0;
+    } else if ((ids_value <= IDS_F10_SCRUB_84MS) && (ids_value >= IDS_F10_SCRUB_40NS)) {
+      PeccOverStruct->CfgScrubL2Rate = (UINT16) (ids_value - 1);
+    }
+  }
+
+  IDS_NV_READ_SKIP (ids_value, AGESA_IDS_NV_L3_SCRUB, IdsNvPtr) {
+    if (ids_value == IDS_F10_SCRUB_DIS) {
+      PeccOverStruct->CfgScrubL3Rate = 0;
+    } else if ((ids_value <= IDS_F10_SCRUB_84MS) && (ids_value >= IDS_F10_SCRUB_40NS)) {
+      PeccOverStruct->CfgScrubL3Rate = (UINT16) (ids_value - 1);
+    }
+  }
+
+  IDS_NV_READ_SKIP (ids_value, AGESA_IDS_NV_DCACHE_SCRUB, IdsNvPtr) {
+    if (ids_value == IDS_F10_SCRUB_DIS) {
+      PeccOverStruct->CfgScrubDcRate = 0;
+    } else if ((ids_value <= IDS_F10_SCRUB_84MS) && (ids_value >= IDS_F10_SCRUB_40NS)) {
+      PeccOverStruct->CfgScrubDcRate = (UINT16) (ids_value - 1);
+    }
+  }
+  return IDS_SUCCESS;
+}
+
+
+
+CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10 =
+{
+  IDS_FEAT_ECC_CTRL,
+  IDS_BSP_ONLY,
+  IDS_ECC,
+  AMD_FAMILY_10,
+  IdsSubEccControlF10
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h
new file mode 100755
index 0000000000..454431ee4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/IdsF10AllService.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _IDS_F10_ALLSERVICE_H_
+#define _IDS_F10_ALLSERVICE_H_
+#ifdef __IDS_EXTENDED__
+  #include IDS_EXT_INCLUDE_F10 (IdsIntF10AllService)
+#endif
+
+/// enum for ids scrub option
+typedef enum {
+  IDS_F10_SCRUB_DIS = 0, ///< 0x00 Disable sequential scrubbing
+
+  IDS_F10_SCRUB_RESERVED,     ///< 0x01 reserved
+  IDS_F10_SCRUB_40NS,     ///< 0x02 40ns
+  IDS_F10_SCRUB_80NS,     ///< 0x03 80ns
+  IDS_F10_SCRUB_160NS,     ///< 0x04 160ns
+  IDS_F10_SCRUB_320NS,     ///< 0x05 320ns
+  IDS_F10_SCRUB_640NS,     ///< 0x06 640ns
+  IDS_F10_SCRUB_1_28US,     ///< 0x07 1.28 us
+  IDS_F10_SCRUB_2_56US,     ///< 0x08 2.56 us
+  IDS_F10_SCRUB_5_12US,     ///< 0x09 5.12 us
+  IDS_F10_SCRUB_10_2US,     ///< 0x0A 10.2 us
+  IDS_F10_SCRUB_20_5US,     ///< 0x0B 20.5 us
+  IDS_F10_SCRUB_41_0US,     ///< 0x0C 41.0 us
+  IDS_F10_SCRUB_81_9US,     ///< 0x0D 81.9 us
+  IDS_F10_SCRUB_163_8US,     ///< 0x0E 163.8 us
+  IDS_F10_SCRUB_327_7US,     ///< 0x0F 327.7 us
+  IDS_F10_SCRUB_655_4US,     ///< 0x10 655.4 us
+  IDS_F10_SCRUB_1_31MS,     ///< 0x11 1.31 ms
+  IDS_F10_SCRUB_2_62MS,     ///< 0x12 2.62 ms
+  IDS_F10_SCRUB_5_24MS,     ///< 0x13 5.24 ms
+  IDS_F10_SCRUB_10_49MS,     ///< 0x14 10.49 ms
+  IDS_F10_SCRUB_20_97MS,     ///< 0x15 20.97 ms
+  IDS_F10_SCRUB_42MS,     ///< 0x16 42ms
+  IDS_F10_SCRUB_84MS,     ///< 0x17 84ms
+
+  IDS_F10_SCRUB_AUTO = 0x1F       ///< Auto
+} IDS_SCRUB_OPTIONS;
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c
new file mode 100755
index 0000000000..27b2fd4eee
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.c
@@ -0,0 +1,52 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Option Specific Routines for RB
+ *
+ * Contains AMD AGESA debug macros and library functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "IdsF10RBService.h"
+#include "Filecode.h"
+#define FILECODE PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.h
new file mode 100755
index 0000000000..51d5190ce9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Family/0x10/RB/IdsF10RBService.h
@@ -0,0 +1,45 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _IDS_F10_RBSERVICE_H_
+#define _IDS_F10_RBSERVICE_H_
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h
new file mode 100755
index 0000000000..590e6c9e40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsLib.h
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision:  $   @e \$Date: 2008-04-07 15:08:45 -0500 (Mon, 07 Apr 2008) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_LIB_H_
+#define _IDS_LIB_H_
+#include "OptionsIds.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+
+///Specific time stamp performance analysis which need ids control support
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define PERF_SPEC_TS_ANALYSE(StdHeader)  IdsPerfSpecTsAnalyse(StdHeader)
+#else
+  #define PERF_SPEC_TS_ANALYSE(StdHeader)
+#endif
+
+
+#define IDS_NV_READ_SKIP(NvValue, Nvid, NvPtr)\
+  if (((NvValue) = AmdIdsNvReader ((Nvid), (NvPtr))) != IDS_UNSUPPORTED)
+
+
+#define IDS_MAX_MEM_ITEMS   80     ///< Maximum IDS Mem Table Size in Heap.
+
+
+// TYPEDEFS, STRUCTURES, ENUMS
+//
+
+
+///Structure define for MSR register
+typedef struct _REG_MSR {
+  UINT32 msraddr;                      ///< Address of MSR Register
+  UINT32 andmaskhi;                   ///< And Mask Bit63:32
+  UINT32 andmasklo;                   ///< And Mask Bit31:0
+  UINT32 ormaskhi;                    ///< Or Mask Bit63:32
+  UINT32 ormasklo;                    ///< Or Mask Bit31:0
+} REG_MSR;
+
+typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader);
+
+///Structure define for IdsAgesaRunFcnOnApLate
+typedef struct _IDSAPLATETASK {
+  PF_IDS_AP_TASK  ApTask; ///< Point function which AP need to do
+  VOID *ApTaskPara; ///< Point to Ap function parameter1
+} IDSAPLATETASK;
+
+/// Data Structure defining IDS Data in HEAP
+/// This data structure contains information that is stored in HEAP and will be
+/// used in IDS backend function. It includes the size of memory to be allocated
+/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA
+/// table and the register table to override mem setting. It also includes a base
+/// address of IDS override image which will be used to control the behavior of
+/// AGESA testpoint if this feature is enabled.
+typedef struct {
+  UINT64 IdsImageBase;                 ///< IDS Override Image Base Address
+  UINT32 IdsHeapMemSize;              ///< IDS Total Memory Size in Heap
+  UINT32 IdsNvTableOffset;            ///< Offset of IDS NV Table
+  UINT32 IdsMemTableOffset;           ///< Offset of IDS Mem Table
+  UINT32 IdsExtendOffset;                ///< Offset of Ids extend heap
+} IDS_CONTROL_STRUCT;
+
+
+/// Data Structure of Parameters for TestPoint_TSC.
+typedef struct {
+  UINT8 TestPoint;                    ///< The TestPoint of TestPoint_TSC
+  UINT64 StartTsc;                  ///< The StartTimer of TestPoint_TSC
+} TestPoint_TSC;
+
+/// Data Structure of Parameters for TP_Perf_STRUCT.
+typedef struct {
+  UINT8 Index;                    ///< The Index of TP_Perf_STRUCT
+  UINT32 TscInMhz;            ///< Tsc counter in 1 mhz
+  TestPoint_TSC TP[EndAgesaTps];       ///< The TP of TP_Perf_STRUCT
+} TP_Perf_STRUCT;
+
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+IDS_STATUS
+IdsSubUCode (
+  IN OUT  VOID *DataPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader,
+  IN      IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubEccSymbolSize (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubGangingMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubPowerDownMode (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubBurstLength32 (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+
+IDS_STATUS
+IdsSubAllMemClkEn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubDllShutDownSR (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubHtLinkControl (
+     OUT   VOID  *Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubPostPState (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubProbeFilter (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+AGESA_STATUS
+AmdIdsCtrlInitialize (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+AmdIdsNvReader (
+  IN      UINT16 IdsNvId,
+  IN      IDS_NV_ITEM *NvTablePtr
+  );
+
+AGESA_STATUS
+AmdGetIdsNvTable (
+  IN OUT   VOID  **IdsNvTable,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  );
+
+
+AGESA_STATUS
+IdsPerfTimestamp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       AGESA_TP TestPoint
+   );
+
+IDS_STATUS
+IdsCommonReturn (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+AGESA_STATUS
+AMDSetAPMsr (
+  IN       REG_MSR  *PRegMsr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsAgesaRunFcnOnApLate  (
+  IN       UINTN               ApicIdOfCore,
+  IN         IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsAgesaRunFcnOnAllCoresLate  (
+  IN         IDSAPLATETASK  *ApLateTaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsParseFeatTbl (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN       CONST IDS_FEAT_STRUCT * PIdsFeatTbl[],
+  IN OUT   VOID *DataPtr,
+  IN       IDS_NV_ITEM *IdsNvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsSubPowerDownCtrl (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+IDS_STATUS
+IdsSubHdtOut (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+UINT8
+IdsGetNumPstatesFamCommon (
+  IN OUT   AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+IdsApRunCodeOnAllLocalCores (
+  IN       AP_TASK *TaskPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+IDS_STATUS
+IdsSubTargetPstate (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+#endif //_IDS_LIB_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsPage.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsPage.h
new file mode 100755
index 0000000000..716913a0bb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/IdsPage.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * Create outline and references for Integrated Debug Support Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision 7990 $   @e \$Date 2008-09-06 00:10:51 +0800 (Sat, 06 Sep 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page idsmain Integrated Debug Support Component Documentation
+ *
+ * Additional documentation for the Integrated Debug Support component consists of
+ *
+ * - Maintenance Guides:
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/OptionsIds.h b/src/vendorcode/amd/agesa/f10/Proc/IDS/OptionsIds.h
new file mode 100755
index 0000000000..992bcabf3c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/OptionsIds.h
@@ -0,0 +1,63 @@
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 12067 $   @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ *  This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *    IDSOPT_TRACING_ENABLED
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c b/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c
new file mode 100755
index 0000000000..6196f2dc5d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/IDS/Perf/IdsPerf.c
@@ -0,0 +1,241 @@
+/**
+ * @file
+ *
+ * AMD Integrated Debug Routines for performance analysis
+ *
+ * Contains AMD AGESA debug macros and functions for performance analysis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision  $   @e \$Date  $
+ */
+/*****************************************************************************
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "IdsLib.h"
+#include "heapManager.h"
+#include "cpuFamilyTranslation.h"
+#include "amdlib.h"
+
+#define FILECODE PROC_IDS_PERF_IDSPERF_FILECODE
+/**
+ *
+ *  IDS Performance function for Output to HDT.
+ *
+ *  Invoke communications with the HDT environment to allow the user to issue
+ *  debug commands. If the sign = 0x0, HDT Control Register will be initialized to
+ *  catch the special I/O for HDT_OUT. Otherwise, it will inform HDT script
+ *  function what is meaning for the value to output to HDT.
+ *
+ *  @param[in] Command    HDT_OUT Command.
+ *  @param[in] Data       The Data to output to HDT.
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *
+ **/
+STATIC VOID
+IdsPerfHdtOut (
+  IN       UINT16 Command,
+  IN       UINT32 Data,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+    IdsOutPort (((UINT32)Command << 16) | 0x8899, Data, 0);
+}
+
+AGESA_TP IdsPerfExcludeTp[] = {
+  TpIfBeforeLocateHeapBuffer,
+  TpIfAfterLocateHeapBuffer,
+  TpIfBeforeAllocateHeapBuffer,
+  TpIfAfterAllocateHeapBuffer
+};
+/**
+ *
+ *  Get Ids Performance analysis table pointer in the AGESA Heap.
+ *
+ *  @param[in,out] StdHeader    The Pointer of AGESA Header
+ *  @param[in] TestPoint  Progress indicator value, see @ref AGESA_TP
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of Performance analysis Table.
+ *  @retval AGESA_ERROR         Fail to get the pointer of Performance analysis Table.
+ *  @retval AGESA_UNSUPPORTED   Get an exclude testpoint
+ *
+ **/
+AGESA_STATUS
+IdsPerfTimestamp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       AGESA_TP TestPoint
+   )
+{
+  AGESA_STATUS status;
+  UINT8 Index;
+  UINT8 i;
+  TP_Perf_STRUCT *PerfTableEntry;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  UINT64 CurrentTsc;
+
+
+  // Exclude some testpoint which may cause deadloop
+  for (i = 0; i < (sizeof (IdsPerfExcludeTp) / sizeof (AGESA_TP)); i++) {
+    if (TestPoint == IdsPerfExcludeTp[i]) {
+      return AGESA_UNSUPPORTED;
+    }
+  }
+  //if heap is not ready yet, don't invoke locate buffer, or else will cause event log & locate heap dead loop
+  if (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET ) {
+    LibAmdMsrRead (TSC, &CurrentTsc, StdHeader);
+
+    LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
+    LocateHeapStructPtr.BufferPtr = NULL;
+
+    status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+    if (status == AGESA_SUCCESS) {
+      PerfTableEntry = (TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr);
+    } else {
+      AllocHeapParams.RequestedBufferSize = sizeof (TP_Perf_STRUCT);
+      AllocHeapParams.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
+      AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+      status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+      if (status != AGESA_SUCCESS) {
+        return status;
+      }
+      PerfTableEntry = (TP_Perf_STRUCT *) (AllocHeapParams.BufferPtr);
+      LibAmdMemFill (PerfTableEntry, 0, sizeof (TP_Perf_STRUCT), StdHeader);
+    }
+
+    Index = PerfTableEntry ->Index;
+//TPPerfUnit doesn't need to check, it may used for multiple time, used to check the time
+// consumption of each perf measure routine.
+    if ((TestPoint != TpPerfUnit)) {
+      for (i = 0; i < Index; i++) {
+        if ((UINT8) TestPoint == PerfTableEntry ->TP[i].TestPoint) {
+          return AGESA_SUCCESS;
+        }
+      }
+    }
+    PerfTableEntry ->TP[Index].TestPoint = (UINT8) TestPoint;
+    PerfTableEntry ->TP[Index].StartTsc = CurrentTsc;
+    PerfTableEntry ->Index = ++Index;
+  }
+  return AGESA_SUCCESS;
+}
+
+typedef struct _PERFREGBACKUP {
+  UINT64 SMsr;
+  UINT32 Dr0Reg;
+  UINT32 Dr7Reg;
+  UINT32 Cr4Reg;
+} PERFREGBACKUP;
+
+STATIC VOID
+IdsPerfSaveReg (
+  IN OUT   PERFREGBACKUP * perfreg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdMsrRead (0xC001100A, &perfreg->SMsr, StdHeader);
+
+  LibAmdReadCpuReg (DR0_REG, &perfreg->Dr0Reg);
+
+  LibAmdReadCpuReg (DR7_REG, &perfreg->Dr7Reg);
+
+  LibAmdReadCpuReg (CR4_REG, &perfreg->Cr4Reg);
+}
+
+STATIC VOID
+IdsPerfRestoreReg (
+  IN       PERFREGBACKUP * perfreg,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LibAmdMsrWrite (0xC001100A, &perfreg->SMsr, StdHeader);
+
+  LibAmdWriteCpuReg (DR0_REG, perfreg->Dr0Reg);
+
+  LibAmdWriteCpuReg (DR7_REG, perfreg->Dr7Reg);
+
+  LibAmdWriteCpuReg (CR4_REG, perfreg->Cr4Reg);
+}
+/**
+ * Output Test Point function .
+ *
+ *  @param[in,out] StdHeader    The Pointer of Standard Header.
+ *
+ *  @retval AGESA_SUCCESS       Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
+ *  @retval AGESA_ERROR         Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
+ *
+ **/
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS status;
+  LOCATE_HEAP_PTR LocateHeapStructPtr;
+  UINT32 TscRateInMhz;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PERFREGBACKUP PerfReg;
+  UINT32 CR4reg;
+  UINT64 SMsr;
+
+  LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
+  LocateHeapStructPtr.BufferPtr = NULL;
+  status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
+  if (status != AGESA_SUCCESS) {
+    return status;
+  }
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
+  ((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
+//Init break point
+  IdsPerfSaveReg (&PerfReg, StdHeader);
+
+  LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
+  SMsr |= 1;
+  LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
+
+  LibAmdWriteCpuReg (DR0_REG, 0x8899);
+  LibAmdWriteCpuReg (DR7_REG, 0x00020402);
+
+  LibAmdReadCpuReg (CR4_REG, &CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
+
+  IdsPerfHdtOut (1, (UINT32) LocateHeapStructPtr.BufferPtr, StdHeader);
+  IdsPerfRestoreReg (&PerfReg, StdHeader);
+  return status;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
new file mode 100755
index 0000000000..73e3c06121
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/marc32_3.c
@@ -0,0 +1,577 @@
+/**
+ * @file
+ *
+ * marc32_3.c
+ *
+ * Memory Controller, registered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_C32_MARC32_3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA C32RDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
+
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA C32RDdr3CKETri[] = {0x55, 0xAA};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for C32 DDR3 L1 system
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID        Socket number
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to C32 MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to C32 CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to C32 ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to C32 CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  //
+  // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
+  //
+  // Code searches table for matching speed, then matches the current dimm
+  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+  //
+  // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
+  //                 in SPD Byte 63.
+  //                 Bits 15-12       RC2 if One register
+  //                 Bits 11-8        RC8 if One register
+  //                 Bits 7-4         RC2 for more than one register
+  //                 Bits 3-0         RC8 for more than one register
+  //
+  // Frequency, Dimm Config ,
+  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
+     {DDR667_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x00000000, 0x4004, 2},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00000000, 0x0000, 1},
+     {DDR800_FREQUENCY, QR_DIMM1, \
+       0x00000000, 0x0040, 1},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00000000, 0x4004, 2},
+     {DDR800_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
+       0x00000000, 0x4004, 2},
+     {DDR800_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
+       0x00000000, 0x4004, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003C3C3C, 0x0000,1},
+     {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x003C3C3C, 0x0040, 1},
+     {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003A3A3A, 0x0000, 1},
+     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x003A3A3A, 0x0040, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00383A38, 0x4040, 2},
+  };
+  //
+  // Address Timings and Drive Strengths for 3 DIMMs per channel
+  //
+  // Code searches table for matching speed, then matches the current dimm
+  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+  //
+  // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
+  //                 in SPD Byte 63.
+  //                 Bits 15-12       RC2 if One register
+  //                 Bits 11-8        RC8 if One register
+  //                 Bits 7-4         RC2 for more than one register
+  //                 Bits 3-0         RC8 for more than one register
+  //
+  // Frequency, Dimm Config ,
+  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
+     {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x0000, 1},
+     {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4040, 2},
+     {DDR667_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4004, 2},
+     {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00380038, 0x4004, 3},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x0000, 1},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4040, 2},
+     {DDR800_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4004, 2},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00380038, 0x4004, 3},
+     {DDR800_FREQUENCY, QR_DIMM1, \
+       0x00000000, 0x0040, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003C3C3C, 0x0000, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3C3A, 0x4040, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1 + SR_DIMM2, \
+       0x00373C37, 0x4040, 3},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3A3A, 0x0000, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+       0x00383A38, 0x4040, 2},
+  };
+
+  //
+  // DIMM ODT Pattern (1 or 2 DIMMs per channel)
+  //
+  // Dimm Config ,
+  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+  //
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+    {SR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+    {DR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+    {QR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
+    {SR_DIMM1, \
+      0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
+    {DR_DIMM1, \
+      0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
+    {QR_DIMM1, \
+      0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+      0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+      0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
+    {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+      0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
+    {QR_DIMM0 + QR_DIMM1, \
+      0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
+  };
+  // DIMM ODT Pattern (3 DIMMs per channel)
+  //
+  // Dimm Config ,
+  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+  //
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+    {SR_DIMM2 + DR_DIMM2, \
+      0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+    {SR_DIMM0 + DR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+      0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+      0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+    {QR_DIMM1, \
+      0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
+    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+      0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+      0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+      0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
+  };
+  //
+  // DIMM ODT Pattern (4 DIMMs per channel)
+  //
+  // Dimm Config ,
+  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+  //
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
+    {ANY_DIMM3, \
+      0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
+    {ANY_DIMM2 + ANY_DIMM3, \
+      0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
+    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+      0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
+    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+      0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
+  };
+  //
+  // DIMM Write Leveling ODT Pattern 1 or 2 Dimms Per Channel
+  //
+  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {QR_DIMM0,            {0x05, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {QR_DIMM1,            {0x00, 0x0A, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
+    {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+    {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+    {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
+  };
+  //
+  // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
+  //
+  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+    {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
+    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
+  };
+  //
+  // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
+  //
+  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
+    {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
+    {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
+    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
+    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
+  };
+
+
+  UINT16 i;
+  UINT16 j;
+  UINT8  MaxDimmPerCH;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT8 DimmTpMatch;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT16 RC2RC8;
+  UINT32 PhyRODTCSLow;
+  UINT32 PhyRODTCSHigh;
+  UINT32 PhyWODTCSLow;
+  UINT32 PhyWODTCSHigh;
+  BOOLEAN SlowMode;
+  UINT8 PSCfgSize;
+  UINT8 PSCfgODTSize;
+  UINT8 PSCfgWlODTSize;
+  UINT8 PhyWLODT[4];
+
+  CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
+  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+  UINT8 *DimmsPerChPtr;
+
+  ASSERT (MemData != NULL);
+  ASSERT (CurrentChannel != NULL);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  RC2RC8 = 0;
+  PhyRODTCSLow = 0;
+  PhyRODTCSHigh = 0;
+  PhyWODTCSLow = 0;
+  PhyWODTCSHigh = 0;
+  SlowMode = FALSE;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+  // Prepare inputs
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if (MaxDimmPerCH == 4) {
+    PSCfgPtr = NULL;
+    PSCfgSize = NULL;
+    PSCfgODTPtr = PSCfg4DIMMsODT;
+    PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else if (MaxDimmPerCH == 3) {
+    PSCfgPtr = PSCfg3DIMMs;
+    PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+    PSCfgODTPtr = PSCfg3DIMMsODT;
+    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else {
+    PSCfgPtr = PSCfg2DIMMs;
+    PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+    PSCfgODTPtr = PSCfg2DIMMsODT;
+    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  }
+
+  // AddrTmgCTL and DctOdcCtl
+  if (MaxDimmPerCH != 4) {
+    for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
+      if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
+        continue;
+      }
+      DimmTpMatch = 0;
+      _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
+      for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+        if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+          DimmTpMatch++;
+        }
+      }
+      if (DimmTpMatch == PSCfgPtr->Dimms) {
+        AddrTmgCTL = PSCfgPtr->AddrTmg;
+        DctOdcCtl = 0x00223222;
+        RC2RC8 = PSCfgPtr->RC2RC8;
+        break;
+      }
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  //
+  // Count slots with SR/DR poulated.
+  //
+  DimmTpMatch = 0;
+  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+    if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
+      DimmTpMatch++;
+    }
+  }
+  //
+  // DimmTpMatch is equal to the count of  slot that have either an SR or DR
+  // installed.
+  //
+  if (MaxDimmPerCH == 4) {
+    //
+    // Any SR/DR in 4 DPCH
+    //
+    if (DimmTpMatch > 0) {
+      DctOdcCtl = 0x00223222;
+      if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
+        DctOdcCtl = 0x00113222;
+      }
+    }
+    //
+    // At Least 3 SR/DR in 4 DPCH
+    //
+    if (DimmTpMatch >= 3) {
+      AddrTmgCTL |= 0x002F0000;
+    }
+    // At Least 2 SR/DR in 4 DPCH
+    if (DimmTpMatch >= 2) {
+      RC2RC8 = 0x4040;
+    }
+  } else {
+    //
+    // Less than 4 DPCH
+    //
+    //
+    // Only 1 Dimm Populated and its a SR or DR OR
+    //   3 Dimms Populated and Frequency is 800 MHz
+    //
+    if (((Dimms == 1) && (DimmTpMatch == 1)) ||
+      ((Dimms == 3) && ((Speed == DDR800_FREQUENCY) || 
+       (Speed == DDR1066_FREQUENCY)))) {
+        DctOdcCtl = 0x00113222;
+    }
+  }
+
+  //RC2 and RC8
+  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+    // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
+    if (CurrentChannel->CtrlWrd02[j] > 0) {
+      if (CurrentChannel->CtrlWrd02[j] == 1) {
+        // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
+        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
+        CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
+      } else {
+        // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
+        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
+        CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
+      }
+    }
+  }
+
+  //Programmable ODT
+  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
+    if (Dimms != PSCfgODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+      break;
+    }
+  }
+
+  //WLODT
+  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+    if (Dimms != PSCfgWlODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  // Set ProcODT
+  DctOdcCtl |= 0x20000000;
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) C32RDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) C32RDdr3CKETri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) C32RDdr3CSTri;
+
+  switch (MaxDimmPerCH) {
+  case 3:
+    CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri3D;
+    break;
+  case 4:
+    CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri4D;
+    break;
+  default:
+    CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri2D;  // Most conservative
+  }
+
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
+  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
+  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
new file mode 100755
index 0000000000..720b3df559
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/C32/mauc32_3.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * mauc32_3.c
+ *
+ * Platform specific settings for C32 DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_C32_MAUC32_3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA C32UDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA C32UDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to C32 MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to C32 CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to C32 ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to C32 CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+  };
+
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+    {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+    {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+    {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
+    {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+    {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+    //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+    //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8  MaxDimmPerCH;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT32 PhyRODTCSLow;
+  UINT32 PhyRODTCSHigh;
+  UINT32 PhyWODTCSLow;
+  UINT32 PhyWODTCSHigh;
+  UINT8 PhyWLODT[4];
+  UINT8 PSCfgODTSize;
+  UINT8 PSCfgWlODTSize;
+  BOOLEAN SlowMode;
+  UINT8 DimmTpMatch;
+  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+  UINT8 *DimmsPerChPtr;
+
+  ASSERT (MemData != NULL);
+  ASSERT (CurrentChannel != NULL);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyRODTCSLow = 0;
+  PhyRODTCSHigh = 0;
+  PhyWODTCSLow = 0;
+  PhyWODTCSHigh = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->RegDimmPresent) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+    SlowMode = TRUE;   // 2T
+  } else {
+    SlowMode = FALSE;  // 1T
+  }
+
+  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+    if (Speed == PSCfg[i].Speed) {
+      if (Loads <= PSCfg[i].Loads) {
+        AddrTmgCTL = PSCfg[i].AddrTmg;
+        DctOdcCtl = PSCfg[i].Odc;
+        break;
+      }
+    }
+  }
+
+  ASSERT (i < GET_SIZE_OF (PSCfg));
+
+  if (MaxDimmPerCH == 3) {
+    PSCfgODTPtr = PSCfg3DIMMsODT;
+    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else {
+    PSCfgODTPtr = PSCfg2DIMMsODT;
+    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  }
+
+  // Programmable ODT
+  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
+    if (Dimms != PSCfgODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+      break;
+    }
+  }
+
+  // WL ODT
+  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+    if (Dimms != PSCfgWlODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  if (Dimms == 1) {
+    if (Loads >= 16) {
+      if (Speed == DDR800_FREQUENCY) {
+        AddrTmgCTL = 0x003B0000;
+      } else if (Speed == DDR1066_FREQUENCY) {
+        AddrTmgCTL = 0x00380000;
+      } else if (Speed == DDR1333_FREQUENCY) {
+        AddrTmgCTL = 0x00360000;
+      } else {
+        AddrTmgCTL = 0x00340000;
+        SlowMode = TRUE;
+      }
+    } else {
+      AddrTmgCTL = 0;
+    }
+    DctOdcCtl = 0x20113222;
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) C32UDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) C32UDdr3CKETri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) C32UDdr3CSTri;
+
+  switch (MaxDimmPerCH) {
+  case 3:
+    CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri3D;
+    break;
+  default:
+    CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri2D;  // Most conservative
+  }
+
+  CurrentChannel->DctEccDqsLike = 0x0403;
+  CurrentChannel->DctEccDqsScale = 0x70;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
+  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
+  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
new file mode 100755
index 0000000000..1d19acb7d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda2.c
@@ -0,0 +1,202 @@
+/*
+ * @file
+ *
+ * masda2.c
+ *
+ * Platform specific settings for DA DDR2 SO-dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support S1g3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DA_MASDA2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DASDdr2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DASDdr2CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for DA DDR2 SO-dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgSDA2 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg[] = {
+    {DDR400_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
+    {DDR533_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
+    {DDR667_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
+    {DDR800_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
+  };
+
+  UINT16 i;
+  UINT8 Loads;
+  UINT8 Ranks;
+  UINT16 Speed;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  BOOLEAN SlowMode;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Ranks = CurrentChannel->Ranks;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+  SlowMode = FALSE;  // 1T
+
+  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+    if (Speed == PSCfg[i].Speed) {
+      if (Loads <= PSCfg[i].Loads) {
+        AddrTmgCTL = PSCfg[i].AddrTmg;
+        DctOdcCtl = PSCfg[i].Odc;
+        break;
+      }
+    }
+  }
+  ASSERT (i < GET_SIZE_OF (PSCfg));
+
+  //
+  // Overrides and/or exceptions
+  //
+  if (Loads == 16) {
+    if ((Speed == DDR533_FREQUENCY) && (Ranks == 2)) {
+      AddrTmgCTL = 0x002C2C2C;
+    } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 1)) {
+      AddrTmgCTL = 0x00272727;
+    } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 2)) {
+      AddrTmgCTL = 0x00002828;
+      SlowMode = TRUE;   // 2T
+    } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 1)) {
+      AddrTmgCTL = 0x00292929;
+    } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 2)) {
+      AddrTmgCTL = 0x00002F2F;
+      SlowMode = TRUE;   // 2T
+    }
+  }
+  CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr2CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) DASDdr2CKETri;
+  CurrentChannel->ODTTriMap = (UINT8 *) DASDdr2ODTTri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr2CSTri;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
new file mode 100755
index 0000000000..18faf2653a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/masda3.c
@@ -0,0 +1,256 @@
+/*
+ * @file
+ *
+ * masda3.c
+ *
+ * Platform specific settings for DA DDR3 SO-dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support S1g4 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DA_MASDA3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DASDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DASDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for DA DDR3 SO-dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgSDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
+    {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT8 PhyWLODT[4];
+  BOOLEAN SlowMode;
+  UINT8  MaxDimmPerCH;
+  UINT8 *DimmsPerChPtr;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT8 DimmTpMatch;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+  SlowMode = FALSE;  // 1T
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+    if (Speed == PSCfg[i].Speed) {
+      if (Loads <= PSCfg[i].Loads) {
+        AddrTmgCTL = PSCfg[i].AddrTmg;
+        DctOdcCtl = PSCfg[i].Odc;
+        break;
+      }
+    }
+  }
+
+  // WL ODT
+  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  if (MaxDimmPerCH == 2) {
+    if (Dimms == 2) {
+      DctOdcCtl = 0x20223323;
+      SlowMode = TRUE;
+      if (Speed == DDR800_FREQUENCY) {
+        AddrTmgCTL = 0x00000039;
+      } else if (Speed == DDR1066_FREQUENCY) {
+        AddrTmgCTL = 0x00000037;
+      }
+    } else {
+      DctOdcCtl = 0x20113222;
+    }
+  } else {
+    if (CurrentChannel->DimmSRPresent != 0) {
+      PhyWLODT[0] = 1;
+    } else if (CurrentChannel->DimmDrPresent != 0) {
+      PhyWLODT[0] = 4;
+    }
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) DASDdr3CKETri;
+  CurrentChannel->ODTTriMap = (UINT8 *) DASDdr3ODTTri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr3CSTri;
+
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
new file mode 100755
index 0000000000..046e9b2a19
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DA/mauda3.c
@@ -0,0 +1,255 @@
+/*
+ * @file
+ *
+ * mauda3.c
+ *
+ * Platform specific settings for DA DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DA_MAUDA3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DAUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DAUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
+    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
+    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
+    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
+    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
+  };
+  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT8 PhyWLODT[4];
+  BOOLEAN SlowMode;
+  UINT8 DimmTpMatch;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+    SlowMode = TRUE;   // 2T
+  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
+    SlowMode = TRUE;   // 2T
+  } else {
+    SlowMode = FALSE;  // 1T
+  }
+
+  if (Dimms == 1) {
+    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
+      if (Speed == PSCfg1Dimm[i].Speed) {
+        if (Loads >= PSCfg1Dimm[i].Loads) {
+          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
+          DctOdcCtl = PSCfg1Dimm[i].Odc;
+        } else {
+          DctOdcCtl = 0x20113222;
+        }
+        break;
+      }
+    }
+    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
+  } else {
+    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
+      if (Speed == PSCfg2Dimm[i].Speed) {
+        if (Loads <= PSCfg2Dimm[i].Loads) {
+          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
+          DctOdcCtl = PSCfg2Dimm[i].Odc;
+          break;
+        }
+      }
+    }
+    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
+  }
+
+  // WL ODT
+  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) DAUDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) DAUDdr3CKETri;
+  CurrentChannel->ODTTriMap = (UINT8 *) DAUDdr3ODTTri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) DAUDdr3CSTri;
+
+  CurrentChannel->DctEccDqsLike = 0x0403;
+  CurrentChannel->DctEccDqsScale = 0x70;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
new file mode 100755
index 0000000000..67b1263e02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr2.c
@@ -0,0 +1,269 @@
+/**
+ * @file
+ *
+ * mardr2.c
+ *
+ * Platform specific settings for DR DDR2 L1 system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DR_MARDR2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DrRDdr2CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
+
+// Chip select 0, 1, 4, 5 maps to M[B,A]_CKE[0]
+// Chip select 2, 3, 6, 7 maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DrRDdr2CKETri[] = {0x33, 0xCC};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for DR DDR2 L1 system
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRDr2 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST ADV_PSCFG_ENTRY PSCfg4D[] = {
+    {ANY_, ANY_, 0x00000000, 0x00111222, 1},
+    {ANY_, ANY_, 0x00370000, 0x00111222, 2}
+  };
+
+  STATIC CONST ADV_PSCFG_ENTRY PSCfg8D[] = {
+    {ANY_, ANY_, 0x00000000, 0x00111222, 1},
+    {ANY_, ANY_, 0x00370000, 0x00111222, 2},
+    {ANY_, ANY_, 0x002F0000, 0x00111222, ANY_}
+  };
+
+  CONST ADV_PSCFG_ENTRY *PSCfgPtr;
+  UINT16 i;
+  UINT8  MaxDimmPerCH;
+  UINT16 TabSize;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT16 QRPresent;
+  UINT16 DRx4Present;
+  BOOLEAN SlowMode;
+  UINT8 *DimmsPerChPtr;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+  QRPresent = CurrentChannel->DimmQrPresent;
+  DRx4Present = CurrentChannel->DimmDrPresent & CurrentChannel->Dimmx4Present;
+  if (QRPresent) {
+    Dimms = (Dimms + 1) / 2;
+  }
+
+  // Table look up
+  if (MaxDimmPerCH <= 2) {
+    PSCfgPtr = PSCfg4D;
+    TabSize = GET_SIZE_OF (PSCfg4D);
+  } else {
+    PSCfgPtr = PSCfg8D;
+    TabSize = GET_SIZE_OF (PSCfg8D);
+  }
+  DctOdcCtl = 0;
+  AddrTmgCTL = 0;
+  for (i = 0; i < TabSize; i++) {
+    if ((PSCfgPtr[i].Dimms == ANY_) || (PSCfgPtr[i].Dimms == Dimms)) {
+      if ((PSCfgPtr[i].Speed == ANY_) || (PSCfgPtr[i].Speed == Speed)) {
+        if ((PSCfgPtr[i].Loads == ANY_) || (PSCfgPtr[i].Loads >= Loads)) {
+          AddrTmgCTL = PSCfgPtr[i].AddrTmg;
+          DctOdcCtl = PSCfgPtr[i].Odc;
+          break;
+        }
+      }
+    }
+  }
+  ASSERT (i == TabSize);
+  SlowMode = FALSE;  // 1T
+
+  //
+  // Overrides and/or exceptions
+  //
+
+  if (QRPresent == 0x55) {
+    // QR for 4DIMM case only
+    AddrTmgCTL = 0x002F0000;
+    if (Speed >= DDR667_FREQUENCY) {
+      DctOdcCtl = 0x00331222;
+    }
+  }
+
+  if (Speed >= DDR667_FREQUENCY) {
+    if ((QRPresent != 0) || (DRx4Present != 0)) {
+      AddrTmgCTL |= 0x00002F00;
+    }
+    if (Dimms >= 3) {
+      AddrTmgCTL |= 0x0000002F;
+    }
+    if (Dimms == 3 || Dimms == 4) {
+      DctOdcCtl = 0x00331222;
+    }
+  }
+
+  // Adjust Processor ODT
+  if (Dimms == 1) {
+    DctOdcCtl |= 0x20000000;        // 75ohms
+  } else {
+    DctOdcCtl |= 0x10000000;        // 150ohms
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr2CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) DrRDdr2CKETri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr2CSTri;
+
+  switch (MaxDimmPerCH) {
+  case 3:
+    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri3D;
+    break;
+  case 4:
+    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri4D;
+    break;
+  default:
+    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri2D;
+  }
+
+  CurrentChannel->DctEccDqsLike = 0x0504;
+  CurrentChannel->DctEccDqsScale = 0;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
new file mode 100755
index 0000000000..d6addd6787
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/mardr3.c
@@ -0,0 +1,424 @@
+/**
+ * @file
+ *
+ * mardr3.c
+ *
+ * Memory Controller, registered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DR_MARDR3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DrRDdr3CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
+
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DrRDdr3CKETri[] = {0x55, 0xAA};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for DR DDR3 L1 system
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00000000, 0x0000, 1},
+     {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x00000000, 0x0040, 1},
+     {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x00000000, 0x4004, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003C3C3C, 0x0000,1},
+     {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x003C3C3C, 0x0040, 1},
+     {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003A3A3A, 0x0000, 1},
+     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x003A3A3A, 0x0040, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00383A38, 0x4040, 2},
+     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x00383A38, 0x4004, 2},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00373937, 0x0000, 1},
+     {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x00373937, 0x0040, 1},
+     {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x00353935, 0x4004, 2}
+  };
+
+  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x0000, 1},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4040, 2},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00380038, 0x4004, 3},
+     {DDR800_FREQUENCY, QR_DIMM1, \
+       0x00000000, 0x0040, 1},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4004, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003C3C3C, 0x0000, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3C3A, 0x4040, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00373C37, 0x4040, 3},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00373C37, 0x4004, 3},
+     {DDR1066_FREQUENCY, QR_DIMM1, \
+       0x003C3C3C, 0x0040, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3A3A, 0x0000, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00383A38, 0x4040, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00343A34, 0x4004, 3},
+     {DDR1333_FREQUENCY, QR_DIMM1, \
+       0x003A3A3A, 0x0040, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00383A38, 0x4004, 2},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00393939, 0x0000, 1},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00363936, 0x4040, 2},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00303930, 0x4004, 3},
+     {DDR1600_FREQUENCY, QR_DIMM1, \
+       0x00393939, 0x0040, 1},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00363936, 0x4004, 2}
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {QR_DIMM1,            {0x00, 0x0A, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
+    {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+    {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+    {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+    {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
+    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
+    {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
+    {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
+    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
+    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
+  };
+  UINT16 i;
+  UINT16 j;
+  UINT8  MaxDimmPerCH;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT8 DimmTpMatch;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT16 RC2RC8;
+  BOOLEAN SlowMode;
+  UINT8 PSCfgSize;
+  UINT8 PSCfgWlODTSize;
+  UINT8 PhyWLODT[4];
+  CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
+  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+  UINT8 *DimmsPerChPtr;
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  RC2RC8 = 0;
+  SlowMode = FALSE;
+  ASSERT (MemData != NULL);
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if (MaxDimmPerCH == 4) {
+    PSCfgPtr = NULL;
+    PSCfgSize = NULL;
+    PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
+    PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else if (MaxDimmPerCH == 3) {
+    PSCfgPtr = PSCfg3DIMMs;
+    PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else {
+    PSCfgPtr = PSCfg2DIMMs;
+    PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  }
+
+  // AddrTmgCTL and DctOdcCtl
+  if (MaxDimmPerCH != 4) {
+    for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
+      if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
+        continue;
+      }
+      DimmTpMatch = 0;
+      _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
+      for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+        if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+          DimmTpMatch++;
+        }
+      }
+      if (DimmTpMatch == PSCfgPtr->Dimms) {
+        AddrTmgCTL = PSCfgPtr->AddrTmg;
+        DctOdcCtl = 0x00223222;
+        RC2RC8 = PSCfgPtr->RC2RC8;
+        break;
+      }
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  DimmTpMatch = 0;
+  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+    if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
+      DimmTpMatch++;
+    }
+  }
+  if (MaxDimmPerCH == 4) {
+    if (DimmTpMatch > 0) {
+      DctOdcCtl = 0x00223222;
+      if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
+        DctOdcCtl = 0x00113222;
+      }
+    }
+    if (DimmTpMatch >= 3) {
+      AddrTmgCTL |= 0x002F0000;
+    }
+    if (DimmTpMatch >= 2) {
+      RC2RC8 = 0x4040;
+    }
+  } else {
+    if ((Dimms == 1) && (DimmTpMatch == 1)) {
+      DctOdcCtl = 0x00113222;
+    }
+  }
+
+  //RC2 and RC8
+  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+    // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
+    if (CurrentChannel->CtrlWrd02[j] > 0) {
+      if (CurrentChannel->CtrlWrd02[j] == 1) {
+        // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
+        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
+        CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
+      } else {
+        // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
+        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
+        CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
+      }
+    }
+  }
+
+
+  //WLODT
+  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+    if (Dimms != PSCfgWlODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  // Set ProcODT
+  DctOdcCtl |= 0x20000000;
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) DrRDdr3CKETri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr3CSTri;
+
+  switch (MaxDimmPerCH) {
+  case 3:
+    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri3D;
+    break;
+  case 4:
+    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri4D;
+    break;
+  default:
+    CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri2D;
+  }
+
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
new file mode 100755
index 0000000000..4e4fca27d5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/DR/maudr3.c
@@ -0,0 +1,255 @@
+/*
+ * @file
+ *
+ * maudr3.c
+ *
+ * Platform specific settings for DR DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_DR_MAUDR3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA DrUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA DrUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
+    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
+    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
+    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
+    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
+  };
+  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT8 PhyWLODT[4];
+  BOOLEAN SlowMode;
+  UINT8 DimmTpMatch;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->RegDimmPresent != 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+    SlowMode = TRUE;   // 2T
+  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
+    SlowMode = TRUE;   // 2T
+  } else {
+    SlowMode = FALSE;  // 1T
+  }
+
+  if (Dimms == 1) {
+    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
+      if (Speed == PSCfg1Dimm[i].Speed) {
+        if (Loads >= PSCfg1Dimm[i].Loads) {
+          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
+          DctOdcCtl = PSCfg1Dimm[i].Odc;
+        } else {
+          DctOdcCtl = 0x20113222;
+        }
+        break;
+      }
+    }
+    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
+  } else {
+    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
+      if (Speed == PSCfg2Dimm[i].Speed) {
+        if (Loads <= PSCfg2Dimm[i].Loads) {
+          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
+          DctOdcCtl = PSCfg2Dimm[i].Odc;
+          break;
+        }
+      }
+    }
+    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
+  }
+
+  // WL ODT
+  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) DrUDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) DrUDdr3CKETri;
+  CurrentChannel->ODTTriMap = (UINT8 *) DrUDdr3ODTTri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) DrUDdr3CSTri;
+
+  CurrentChannel->DctEccDqsLike = 0x0403;
+  CurrentChannel->DctEccDqsScale = 0x70;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
new file mode 100755
index 0000000000..cfeb0dceb6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/marhy3.c
@@ -0,0 +1,561 @@
+/**
+ * @file
+ *
+ * marhy3.c
+ *
+ * Memory Controller, registered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_HY_MARHY3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA HyRDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
+
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA HyRDdr3CKETri[] = {0x55, 0xAA};
+
+// 2 dimms per channel
+// Dimm 0: BP_MEMODTx[2,0]
+// Dimm 1: BP_MEMODTx[3,1]
+STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
+// 4 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[1]
+// Dimm 2: BP_MEMODTx[2]
+// Dimm 3: BP_MEMODTx[3]
+STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
+
+// BIOS must not tri-state chip select pin corresponding to the second chip
+// select of a single rank registered dimm
+STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for HY DDR3 L1 system
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID        Socket number
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to HY MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to HY CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to HY ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to HY CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgRHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  //
+  // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
+  //
+  // Code searches table for matching speed, then matches the current dimm
+  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+  //
+  // Frequency, Dimm Config ,
+  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00000000, 0x0000, 1},
+     {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x00000000, 0x0040, 1},
+     {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x00000000, 0x4004, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003C3C3C, 0x0000,1},
+     {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x003C3C3C, 0x0040, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1066_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1066_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x003A3A3A, 0x0000, 1},
+     {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x003A3A3A, 0x0040, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00383A38, 0x4040, 2},
+     {DDR1333_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
+       0x00383A38, 0x4004, 2},
+     {DDR1333_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
+       0x00383A38, 0x4004, 2},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+       0x00373937, 0x0000, 1},
+     {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
+       0x00373937, 0x0040, 1},
+     {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
+       0x00353935, 0x4004, 2}
+  };
+  //
+  // Address Timings and Drive Strengths for 3 DIMMs per channel
+  //
+  // Code searches table for matching speed, then matches the current dimm
+  // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
+  //
+  // Frequency, Dimm Config ,
+  // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x0000, 1},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4040, 2},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00380038, 0x4004, 3},
+     {DDR800_FREQUENCY, QR_DIMM1, \
+       0x00000000, 0x0040, 1},
+     {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00000000, 0x4004, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003C3C3C, 0x0000, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3C3A, 0x4040, 2},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00373C37, 0x4040, 3},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00373C37, 0x4004, 3},
+     {DDR1066_FREQUENCY, QR_DIMM1, \
+       0x003C3C3C, 0x0040, 1},
+     {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3C3A, 0x4004, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x003A3A3A, 0x0000, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00383A38, 0x4040, 2},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00343A34, 0x4004, 3},
+     {DDR1333_FREQUENCY, QR_DIMM1, \
+       0x003A3A3A, 0x0040, 1},
+     {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00383A38, 0x4004, 2},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00393939, 0x0000, 1},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00363936, 0x4040, 2},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00303930, 0x4004, 3},
+     {DDR1600_FREQUENCY, QR_DIMM1, \
+       0x00393939, 0x0040, 1},
+     {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+       0x00363936, 0x4004, 2}
+  };
+  //
+  // DIMM ODT Pattern (1 or 2 DIMMs per channel)
+  //
+  // Dimm Config ,
+  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+  //
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+    {SR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+    {DR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+    {QR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
+    {SR_DIMM1, \
+      0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
+    {DR_DIMM1, \
+      0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
+    {QR_DIMM1, \
+      0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+      0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+      0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
+    {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
+      0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
+    {QR_DIMM0 + QR_DIMM1, \
+      0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
+  };
+  // DIMM ODT Pattern (3 DIMMs per channel)
+  //
+  // Dimm Config ,
+  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+  //
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+    {SR_DIMM2 + DR_DIMM2, \
+      0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+    {SR_DIMM0 + DR_DIMM0, \
+      0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
+      0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+      0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+    {QR_DIMM1, \
+      0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
+    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+      0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
+      0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
+      0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
+  };
+  //
+  // DIMM ODT Pattern (4 DIMMs per channel)
+  //
+  // Dimm Config ,
+  // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
+  //
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
+    {ANY_DIMM3, \
+      0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
+    {ANY_DIMM2 + ANY_DIMM3, \
+      0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
+    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+      0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
+    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
+      0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
+  };
+  //
+  // DIMM Write Leveling ODT Pattern for 1 or 2 Dimms Per Channel
+  //
+  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {QR_DIMM0,            {0x05, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {QR_DIMM1,            {0x00, 0x0A, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
+    {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+    {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
+    {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
+  };
+  //
+  // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
+  //
+  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+    {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
+    {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
+    {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
+  };
+  //
+  // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
+  //
+  // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
+  //
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
+    {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
+    {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
+    {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
+    {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8  MaxDimmPerCH;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT8 DimmTpMatch;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT16 RC2RC8;
+  UINT32 PhyRODTCSLow;
+  UINT32 PhyRODTCSHigh;
+  UINT32 PhyWODTCSLow;
+  UINT32 PhyWODTCSHigh;
+  BOOLEAN SlowMode;
+  UINT8 PSCfgSize;
+  UINT8 PSCfgODTSize;
+  UINT8 PSCfgWlODTSize;
+  UINT8 PhyWLODT[4];
+
+  CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
+  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+  UINT8 *DimmsPerChPtr;
+
+  ASSERT (MemData != NULL);
+  ASSERT (CurrentChannel != NULL);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  RC2RC8 = 0;
+  PhyRODTCSLow = 0;
+  PhyRODTCSHigh = 0;
+  PhyWODTCSLow = 0;
+  PhyWODTCSHigh = 0;
+  SlowMode = FALSE;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+  // Prepare inputs
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if (MaxDimmPerCH == 4) {
+    PSCfgPtr = NULL;
+    PSCfgSize = 0;
+    PSCfgODTPtr = PSCfg4DIMMsODT;
+    PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else if (MaxDimmPerCH == 3) {
+    PSCfgPtr = PSCfg3DIMMs;
+    PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+    PSCfgODTPtr = PSCfg3DIMMsODT;
+    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else {
+    PSCfgPtr = PSCfg2DIMMs;
+    PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
+    PSCfgODTPtr = PSCfg2DIMMsODT;
+    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  }
+
+  // AddrTmgCTL and DctOdcCtl
+  if (MaxDimmPerCH != 4) {
+    for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
+      if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
+        continue;
+      }
+      DimmTpMatch = 0;
+      _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
+      for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+        if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+          DimmTpMatch++;
+        }
+      }
+      if (DimmTpMatch == PSCfgPtr->Dimms) {
+        AddrTmgCTL = PSCfgPtr->AddrTmg;
+        DctOdcCtl = 0x00223222;
+        RC2RC8 = PSCfgPtr->RC2RC8;
+        break;
+      }
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  DimmTpMatch = 0;
+  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+    if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
+      DimmTpMatch++;
+    }
+  }
+  if (MaxDimmPerCH == 4) {
+    if (DimmTpMatch > 0) {
+      DctOdcCtl = 0x00223222;
+      if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
+        DctOdcCtl = 0x00113222;
+      }
+    }
+    if (DimmTpMatch >= 3) {
+      AddrTmgCTL |= 0x002F0000;
+    }
+    if (DimmTpMatch >= 2) {
+      RC2RC8 = 0x4040;
+    }
+  } else if ((MaxDimmPerCH == 3) && (CurrentChannel->Dimms == 3)) {
+    DctOdcCtl = 0x00113222;
+  } else {
+    if ((Dimms == 1) && (DimmTpMatch == 1)) {
+      DctOdcCtl = 0x00113222;
+    }
+  }
+
+  //RC2 and RC8
+  for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+    // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
+    if (CurrentChannel->CtrlWrd02[j] > 0) {
+      if (CurrentChannel->CtrlWrd02[j] == 1) {
+        // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
+        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
+        CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
+      } else {
+        // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
+        CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
+        CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
+      }
+    }
+  }
+
+  //Programmable ODT
+  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
+    if (Dimms != PSCfgODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+      break;
+    }
+  }
+
+  //WLODT
+  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+    if (Dimms != PSCfgWlODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  // Set ProcODT
+  DctOdcCtl |= 0x20000000;
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) HyRDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) HyRDdr3CKETri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) HyRDdr3CSTri;
+
+  switch (MaxDimmPerCH) {
+  case 3:
+    CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri3D;
+    break;
+  case 4:
+    CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri4D;
+    break;
+  default:
+    CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri2D;  // Most conservative
+  }
+
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
+  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
+  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
new file mode 100755
index 0000000000..b9422999a3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/HY/mauhy3.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * mauhy3.c
+ *
+ * Platform specific settings for HY DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_HY_MAUHY3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA HyUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA HyUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
+// 3 dimms per channel
+// Dimm 0: BP_MEMODTx[0]
+// Dimm 1: BP_MEMODTx[3,1]
+// Dimm 2: BP_MEMODTx[2]
+STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for HY DDR3 unbuffered dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to HY MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to HY CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to HY ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to HY CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+  };
+
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
+    {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
+    {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
+    {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
+    {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
+    {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
+    //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
+    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
+    {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
+    //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
+    //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8  MaxDimmPerCH;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT32 PhyRODTCSLow;
+  UINT32 PhyRODTCSHigh;
+  UINT32 PhyWODTCSLow;
+  UINT32 PhyWODTCSHigh;
+  UINT8 PhyWLODT[4];
+  UINT8 PSCfgODTSize;
+  UINT8 PSCfgWlODTSize;
+  BOOLEAN SlowMode;
+  UINT8 DimmTpMatch;
+  CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
+  CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
+  UINT8 *DimmsPerChPtr;
+
+  ASSERT (MemData != NULL);
+  ASSERT (CurrentChannel != NULL);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyRODTCSLow = 0;
+  PhyRODTCSHigh = 0;
+  PhyWODTCSLow = 0;
+  PhyWODTCSHigh = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->RegDimmPresent) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+    SlowMode = TRUE;   // 2T
+  } else {
+    SlowMode = FALSE;  // 1T
+  }
+
+  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+    if (Speed == PSCfg[i].Speed) {
+      if (Loads <= PSCfg[i].Loads) {
+        AddrTmgCTL = PSCfg[i].AddrTmg;
+        DctOdcCtl = PSCfg[i].Odc;
+        break;
+      }
+    }
+  }
+
+  ASSERT (i < GET_SIZE_OF (PSCfg));
+
+  if (MaxDimmPerCH == 3) {
+    PSCfgODTPtr = PSCfg3DIMMsODT;
+    PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  } else {
+    PSCfgODTPtr = PSCfg2DIMMsODT;
+    PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
+    PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
+    PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
+  }
+
+  // Programmable ODT
+  for (i = 0; i  < PSCfgODTSize; i++, PSCfgODTPtr++) {
+    if (Dimms != PSCfgODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgODTPtr->Dimms) {
+      PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
+      PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
+      PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
+      PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
+      break;
+    }
+  }
+
+  // WL ODT
+  for (i = 0; i  < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
+    if (Dimms != PSCfgWlODTPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
+      PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  if (Dimms == 1) {
+    if (Loads >= 16) {
+      if (Speed == DDR800_FREQUENCY) {
+        AddrTmgCTL = 0x003B0000;
+      } else if (Speed == DDR1066_FREQUENCY) {
+        AddrTmgCTL = 0x00380000;
+      } else if (Speed == DDR1333_FREQUENCY) {
+        AddrTmgCTL = 0x00360000;
+      } else {
+        AddrTmgCTL = 0x00340000;
+        SlowMode = TRUE;
+      }
+    } else {
+      AddrTmgCTL = 0;
+    }
+    DctOdcCtl = 0x20113222;
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) HyUDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) HyUDdr3CKETri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) HyUDdr3CSTri;
+
+  switch (MaxDimmPerCH) {
+  case 3:
+    CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri3D;
+    break;
+  default:
+    CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri2D;  // Most conservative
+  }
+
+  CurrentChannel->DctEccDqsLike = 0x0403;
+  CurrentChannel->DctEccDqsScale = 0x70;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  CurrentChannel->PhyRODTCSLow  = PhyRODTCSLow;
+  CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
+  CurrentChannel->PhyWODTCSLow  = PhyWODTCSLow;
+  CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
new file mode 100755
index 0000000000..4af0889a9a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/masNi3.c
@@ -0,0 +1,256 @@
+/*
+ * @file
+ *
+ * masNi3.c
+ *
+ * Platform specific settings for Ni DDR3 SO-dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support ASB2 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "ma.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mu.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_NI_MASNI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA NiSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA NiSDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for Ni DDR3 SO-dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgSNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
+    {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT8 PhyWLODT[4];
+  BOOLEAN SlowMode;
+  UINT8  MaxDimmPerCH;
+  UINT8 *DimmsPerChPtr;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT8 DimmTpMatch;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+  SlowMode = FALSE;  // 1T
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
+    if (Speed == PSCfg[i].Speed) {
+      if (Loads <= PSCfg[i].Loads) {
+        AddrTmgCTL = PSCfg[i].AddrTmg;
+        DctOdcCtl = PSCfg[i].Odc;
+        break;
+      }
+    }
+  }
+
+  // WL ODT
+  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  //
+  // Overrides and/or exceptions
+  //
+  if (MaxDimmPerCH == 2) {
+    if (Dimms == 2) {
+      DctOdcCtl = 0x20223323;
+      SlowMode = TRUE;
+      if (Speed == DDR800_FREQUENCY) {
+        AddrTmgCTL = 0x00000039;
+      } else if (Speed == DDR1066_FREQUENCY) {
+        AddrTmgCTL = 0x00000037;
+      }
+    } else {
+      DctOdcCtl = 0x20113222;
+    }
+  } else {
+    if (CurrentChannel->DimmSRPresent != 0) {
+      PhyWLODT[0] = 1;
+    } else if (CurrentChannel->DimmDrPresent != 0) {
+      PhyWLODT[0] = 4;
+    }
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) NiSDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) NiSDdr3CKETri;
+  CurrentChannel->ODTTriMap = (UINT8 *) NiSDdr3ODTTri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) NiSDdr3CSTri;
+
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
new file mode 100755
index 0000000000..375802923f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/NI/mauNi3.c
@@ -0,0 +1,255 @@
+/*
+ * @file
+ *
+ * mauNi3.c
+ *
+ * Platform specific settings for Ni DDR3 unbuffered dimms
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support AM3 */
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_NI_MAUNI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT8 ROMDATA NiUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+// Even chip select maps to M[B,A]_CKE[0]
+// Odd chip select maps to M[B,A]_CKE[1]
+STATIC CONST UINT8 ROMDATA NiUDdr3CKETri[] = {0x55, 0xAA};
+// Bit 0: M[B,A]0_ODT[0]
+// Bit 1: M[B,A]1_ODT[0]
+// Bit 2: M[B,A]0_ODT[1]
+// Bit 3: M[B,A]1_ODT[1]
+STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
+// Bit 0: M[B,A]0_CS_H/L[0]
+// Bit 1: M[B,A]0_CS_H/L[1]
+// Bit 2: M[B,A]0_CS_H/L[2]
+// Bit 3: M[B,A]0_CS_H/L[3]
+STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
+ *
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID          Socket number
+ *     @param[in,out]   *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_SUCCESS
+ *     @return          CurrentChannel->MemClkDisMap     Points this pointer to RB MemClkDis table
+ *     @return          CurrentChannel->ChipSelTriMap    Points this pointer to RB CS table
+ *     @return          CurrentChannel->CKETriMap        Points this pointer to RB ODT table
+ *     @return          CurrentChannel->ODTTriMap        Points this pointer to RB CKE table
+ *     @return          CurrentChannel->DctEccDQSLike      Indicates the bytes that should be averaged for ECC
+ *     @return          CurrentChannel->DctEccDQSScale     Indicates the scale that should be used for Averaging ECC byte
+ *     @return          CurrentChannel->DctAddrTmg        Address Command Timing Settings for specified channel
+ *     @return          CurrentChannel->DctOdcCtl         Drive Strength settings for specified channel
+ *     @return          CurrentChannel->SlowMode             Slow Mode
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgUNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
+    {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
+    {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
+    {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
+    {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
+  };
+  STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
+    {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
+    {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
+    {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
+    {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
+  };
+
+  STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
+    {SR_DIMM0,            {0x01, 0x00, 0x00, 0x00}, 1},
+    {DR_DIMM0,            {0x04, 0x00, 0x00, 0x00}, 1},
+    {SR_DIMM1,            {0x00, 0x02, 0x00, 0x00}, 1},
+    {DR_DIMM1,            {0x00, 0x08, 0x00, 0x00}, 1},
+    {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
+  };
+
+  UINT16 i;
+  UINT16 j;
+  UINT8 Loads;
+  UINT8 Dimms;
+  UINT16 Speed;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+  UINT32 AddrTmgCTL;
+  UINT32 DctOdcCtl;
+  UINT8 PhyWLODT[4];
+  BOOLEAN SlowMode;
+  UINT8 DimmTpMatch;
+
+  ASSERT (MemData != 0);
+  ASSERT (CurrentChannel != 0);
+
+  AddrTmgCTL = 0;
+  DctOdcCtl = 0;
+  PhyWLODT[0] = 0x0F;
+  PhyWLODT[1] = 0x0F;
+  PhyWLODT[2] = 0x0F;
+  PhyWLODT[3] = 0x0F;
+
+  if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+  // Prepare inputs
+  Loads = CurrentChannel->Loads;
+  Dimms = CurrentChannel->Dimms;
+  Speed = CurrentChannel->DCTPtr->Timings.Speed;
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+
+  if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
+    SlowMode = TRUE;   // 2T
+  } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
+    SlowMode = TRUE;   // 2T
+  } else {
+    SlowMode = FALSE;  // 1T
+  }
+
+  if (Dimms == 1) {
+    for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
+      if (Speed == PSCfg1Dimm[i].Speed) {
+        if (Loads >= PSCfg1Dimm[i].Loads) {
+          AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
+          DctOdcCtl = PSCfg1Dimm[i].Odc;
+        } else {
+          DctOdcCtl = 0x20113222;
+        }
+        break;
+      }
+    }
+    ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
+  } else {
+    for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
+      if (Speed == PSCfg2Dimm[i].Speed) {
+        if (Loads <= PSCfg2Dimm[i].Loads) {
+          AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
+          DctOdcCtl = PSCfg2Dimm[i].Odc;
+          break;
+        }
+      }
+    }
+    ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
+  }
+
+  // WL ODT
+  for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
+    if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
+      PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
+      PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
+      PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
+      PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
+      break;
+    }
+  }
+
+  CurrentChannel->MemClkDisMap = (UINT8 *) NiUDdr3CLKDis;
+  CurrentChannel->CKETriMap = (UINT8 *) NiUDdr3CKETri;
+  CurrentChannel->ODTTriMap = (UINT8 *) NiUDdr3ODTTri;
+  CurrentChannel->ChipSelTriMap = (UINT8 *) NiUDdr3CSTri;
+
+  CurrentChannel->DctEccDqsLike = 0x0403;
+  CurrentChannel->DctEccDqsScale = 0x70;
+  CurrentChannel->DctAddrTmg = AddrTmgCTL;
+  CurrentChannel->DctOdcCtl = DctOdcCtl;
+  for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
+    CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
+  }
+  CurrentChannel->SlowMode = SlowMode;
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
new file mode 100755
index 0000000000..0396ebb06e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ardk/ma.c
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * ma.c
+ *
+ * Initializes ARDK Block
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ardk)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "ma.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_ARDK_MA_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This is the default return function of the ARDK block. The function always
+ *    returns   AGESA_UNSUPPORTED
+ *
+ *     @param[in,out]   *MemData           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       SocketID        Socket number
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          AGESA_UNSUPPORTED  AGESA status indicating that default is unsupported
+ *
+ */
+
+AGESA_STATUS
+MemAGetPsCfgDef (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  return AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function returns the rank type map of a channel.
+ *
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *
+ *     @return          UINT16 - The map of rank type.
+ *
+ */
+UINT16
+MemAGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  )
+{
+  UINT8 i;
+  UINT16 DIMMRankType;
+
+  DIMMRankType = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
+      if (i < 2) {
+        DIMMRankType |= (UINT16) 4 << (i << 2);
+      }
+    } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
+      DIMMRankType |= (UINT16) 2 << (i << 2);
+    } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
+      DIMMRankType |= (UINT16) 1 << (i << 2);
+    }
+  }
+  return DIMMRankType;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
new file mode 100755
index 0000000000..0c04df82d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.c
@@ -0,0 +1,208 @@
+/**
+ * @file
+ *
+ * mfchi.c
+ *
+ * Feature Channel interleaving support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Chintlv)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfchi.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_ (0x10000 >> 10)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   MemFInterleaveChannels:
+ *
+ *  Applies DIMM channel interleaving if enabled, if not ganged mode, and
+ *  there are valid dimms in both channels.  Called once per Node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveChannels (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 DramBase;
+  UINT32 DctSelBase;
+  UINT32 HoleSize;
+  UINT32 HoleBase;
+  UINT32 HoleOffset;
+  UINT32 Dct0Size;
+  UINT32 Dct1Size;
+  UINT32 SmallerDct;
+  UINT8 DctSelIntLvAddr;
+  UINT8 DctSelHi;
+  UINT8 DctSelHiRngEn;
+  UINT32 HoleValid;
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+
+  DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr;
+  if (RefPtr->EnableChannelIntlv) {
+    HoleSize = 0;
+    HoleBase = 0;
+    if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
+      // HoleBase scaled from [47:16] to [47:26]
+      HoleBase = RefPtr->HoleBase >> 10;
+      HoleSize = _4GB_ - HoleBase;
+    }
+
+    MCTPtr = NBPtr->MCTPtr;
+
+    HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid);
+    if ((!MCTPtr->GangedMode) &&
+        (MCTPtr->DctData[0].Timings.DctMemSize != 0) &&
+        (MCTPtr->DctData[1].Timings.DctMemSize != 0)) {
+      // DramBase scaled [47:16] to [47:26]
+      DramBase = MCTPtr->NodeSysBase >> 10;
+      // Scale NodeSysLimit [47:16] to [47:26]
+      Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10;
+      Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset);
+      if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) {
+        Dct0Size -= HoleSize;
+      }
+      if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) {
+        Dct1Size -= HoleSize;
+      }
+      Dct1Size -= Dct0Size;
+      Dct0Size -= DramBase;
+
+       // Select the bigger size DCT to put in DctSelHi
+      DctSelHiRngEn = 1;
+      DctSelHi = 0;
+      SmallerDct = Dct1Size;
+      if (Dct1Size == Dct0Size) {
+        SmallerDct = 0;
+        DctSelHiRngEn = 0;
+      } else if (Dct1Size > Dct0Size) {
+        SmallerDct = Dct0Size;
+        DctSelHi = 1;
+      }
+
+      if (SmallerDct != 0) {
+        DctSelBase = (SmallerDct * 2) + DramBase;
+      } else {
+        DctSelBase = 0;
+      }
+      if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) {
+        DctSelBase += HoleSize;
+      }
+      IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader));
+      NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1);
+      NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn);
+      NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi);
+      NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr);
+      NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1);
+
+       // DctSelBaseOffset = DctSelBaseAddr - Interleaved region
+      NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct);
+
+       // Adjust DramHoleOffset
+      if (HoleValid != 0) {
+        HoleOffset = DramBase;
+        if ((DctSelBase < HoleBase) && (DctSelBase != 0)) {
+          HoleOffset += (DctSelBase - DramBase) >> 1;
+        }
+        HoleOffset += HoleSize;
+        NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3);
+      }
+    } else {
+      //
+      // Channel Interleaving is requested but cannot be enabled
+      //
+      PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, MCTPtr);
+    }
+
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
new file mode 100755
index 0000000000..e8ffe19b97
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CHINTLV/mfchi.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfchi.h
+ *
+ * Feature channel interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCHI_H_
+#define _MFCHI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveChannels (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFCHI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
new file mode 100755
index 0000000000..fb23c4f213
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -0,0 +1,331 @@
+/**
+ * @file
+ *
+ * mfcsi.c
+ *
+ * Feature bank interleaving support (AKA Chip Select Interleaving )
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Csintlv)
+ * @e \$Revision: 55148 $ @e \$Date: 2011-06-16 16:16:12 -0600 (Thu, 16 Jun 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/* This file contains functions for Chip Select interleaving */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mfcsi.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemFDctInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+CsIntSwap (
+  IN OUT   UINT32 *BaseMaskRegPtr,
+  IN       UINT8 EnChipSels,
+  IN       UINT8 LoBit,
+  IN       UINT8 HiBit
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function Applies DIMM bank (chip-select) interleaving if enabled
+ *      and if all criteria are met.  Interleaves chip-selects on page boundaries.
+ *      This function calls subfunctions that sets up CS interleaving on multiple Sockets
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN RetFlag;
+
+  ASSERT (NBPtr != NULL);
+
+  RetFlag = FALSE;
+  if (NBPtr->RefPtr->EnableBankIntlv) {
+    if (NBPtr->MCTPtr->NodeMemSize) {
+      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+        NBPtr->SwitchDCT (NBPtr, Dct);
+        RetFlag |= MemFDctInterleaveBanks (NBPtr);
+      }
+    }
+  }
+  return RetFlag;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function checks if bank interleaving has been enabled or not. If yes, it will
+ *     undo bank interleaving. Otherwise, it does nothing.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Bank interleaving has been enabled.
+ *     @return          FALSE - Bank interleaving has not been enabled.
+ */
+
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Cs;
+  UINT8 Dct;
+  UINT32 CSMask;
+  BOOLEAN CSIntlvEnabled;
+  BOOLEAN RetFlag;
+
+  ASSERT (NBPtr != NULL);
+
+  RetFlag = FALSE;
+
+  if (NBPtr->RefPtr->EnableBankIntlv) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize) {
+        CSIntlvEnabled = FALSE;
+        for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
+          if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
+            CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
+            if (((CSMask >> 5) & 0x1FF) != 0x1FF) {
+              CSIntlvEnabled = TRUE;
+              break;
+            }
+          }
+        }
+        if (CSIntlvEnabled) {
+          MemFDctInterleaveBanks (NBPtr);
+          RetFlag = TRUE;
+        }
+      }
+    }
+  }
+  return RetFlag;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function Applies DIMM bank (chip-select) interleaving if enabled
+ *      and if all criteria are met.  Interleaves chip-selects on page boundaries.
+ *      This function is run once per Socket
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Register bits have been swapped.
+ *     @return          FALSE - Register bits have not been swapped.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemFDctInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Cs;
+  UINT8 EnChipSels;
+  UINT8 BankEncd;
+  UINT8 BankEncd0;
+  UINT8 i;
+  UINT8 j;
+  UINT32 BankAddrReg;
+  UINT32 BaseRegS0;
+  UINT32 BaseRegS1;
+  UINT32 MaskReg;
+
+  ASSERT (NBPtr != NULL);
+
+  // Check if CS interleaving can be enabled
+  EnChipSels = 0;
+  BankEncd0 = 0xFF;
+  for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
+    if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 3) != 0) {
+      BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg);
+      BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF);
+      if (BankEncd0 == 0xFF) {
+        BankEncd0 = BankEncd;
+      } else if (BankEncd0 != BankEncd) {
+        break;
+      }
+      if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
+        EnChipSels++;
+      }
+    }
+  }
+
+  // Swap Dram Base/Mask Addr to enable CS interleaving
+  if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) {
+    NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j);
+    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+      i++;
+      j++;
+    }
+
+    for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) {
+      BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs);
+      BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1);
+      if (((BaseRegS0 | BaseRegS1) & 1) != 0) {
+        // Swap Mask register bits
+        MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
+        CsIntSwap (&MaskReg, EnChipSels, i, j);
+        NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg);
+
+        // Swap Base register bits
+        CsIntSwap (&BaseRegS0, EnChipSels, i, j);
+        NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0);
+        CsIntSwap (&BaseRegS1, EnChipSels, i, j);
+        NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1);
+      }
+    }
+    return TRUE;
+  } else {
+    //
+    // Bank Interleaving is requested but cannot be enabled
+    //
+    PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    NBPtr->MCTPtr->ErrStatus[EsbBkIntDis] = TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This supporting function swaps Chip selects
+ *
+ *     @param[in,out]  *BaseMaskRegPtr   - Pointer to the Mask Register
+ *     @param[in]      *EnChipSels    - Chip Selects to Enable
+ *     @param[in]      *LoBit         - Lowest Bit
+ *     @param[in]      *HiBit         - Highest Bit
+ *
+ *
+ */
+
+VOID
+STATIC
+CsIntSwap (
+  IN OUT   UINT32 *BaseMaskRegPtr,
+  IN       UINT8 EnChipSels,
+  IN       UINT8 LoBit,
+  IN       UINT8 HiBit
+  )
+{
+  UINT8 BitDelta;
+  UINT32 TempHi;
+  UINT32 TempLo;
+  UINT32 AddrLoMask;
+  UINT32 AddrHiMask;
+
+  ASSERT (BaseMaskRegPtr != NULL);
+  ASSERT (HiBit > LoBit);
+
+  BitDelta = HiBit - LoBit;
+  AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit;
+  AddrHiMask = AddrLoMask << BitDelta;
+
+  TempHi = TempLo = *BaseMaskRegPtr;
+  TempLo &= AddrLoMask;
+  TempLo <<= BitDelta;     // move lower bits to upper bit position
+  TempHi &= AddrHiMask;
+  TempHi >>= BitDelta;     // move upper bits to lower bit position
+
+  *BaseMaskRegPtr &= ~AddrLoMask;
+  *BaseMaskRegPtr &= ~AddrHiMask;
+  *BaseMaskRegPtr |= TempLo | TempHi;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
new file mode 100755
index 0000000000..621efb716c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/CSINTLV/mfcsi.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfcsi.h
+ *
+ * Memory Controller
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFCSI_H_
+#define _MFCSI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFCSI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
new file mode 100755
index 0000000000..4a54516aa1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/DMI/mfDMI.c
@@ -0,0 +1,566 @@
+/**
+ * @file
+ *
+ * mfDMI.c
+ *
+ * Memory DMI table support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6529 $ @e \$Date: 2008-06-25 04:19:02 -0500 (Wed, 25 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define MAX_DCTS_PER_DIE 2
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets DDR3 DMI information from SPD buffer and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8  i;
+  UINT8  Dimm;
+  UINT8  Socket;
+  UINT8  NodeId;
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT8  temp;
+  UINT8  MaxDimms;
+  UINT8  DimmIndex;
+  UINT8  MaxChannelsPerSocket;
+  UINT8  MaxDimmsPerChannel;
+  UINT8  FormFactor;
+  UINT16 TotalWidth;
+  UINT16 Speed;
+  UINT16 Capacity;
+  UINT16 Width;
+  UINT16 Rank;
+  UINT16 BusWidth;
+  UINT64 ManufacturerIdCode;
+  UINT32 MaxSockets;
+  UINT32 Address;
+
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DMI_INFO *DmiTable;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SpdDataStructure;
+
+  NBPtr = MemMainPtr->NBPtr;
+  MemPtr = MemMainPtr->MemPtr;
+  SpdDataStructure = MemPtr->SpdDataStructure;
+  MCTPtr = NBPtr->MCTPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Initialize local variables
+  MaxDimms = 0;
+
+  AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader);
+
+  ASSERT (NBPtr != NULL);
+
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
+      temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      MaxDimms = MaxDimms + temp;
+    }
+  }
+
+  // Allocate heap for memory DMI table 16, 17, 19, 20
+  AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 2 + sizeof (DMI_T17_MEMORY_TYPE);
+
+  AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3
+    return FALSE;
+  }
+
+  DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+  *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms;          // Number of memory devices
+  *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr3MemType;  // Memory type
+
+  //
+  // DMI TYPE 17
+  //
+  DimmIndex = 0;
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      //
+      // Get Node number and Dct number for this channel
+      //
+      ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
+      NodeId = ChannelPtr->MCTPtr->NodeId;
+      Dct = ChannelPtr->Dct;
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
+        DmiTable[DimmIndex].TotalWidth = 0xFFFF;
+        DmiTable[DimmIndex].DataWidth = 0xFFFF;
+        DmiTable[DimmIndex].MemorySize = 0xFFFF;
+        DmiTable[DimmIndex].Speed = 0;
+        DmiTable[DimmIndex].ManufacturerIdCode = 0;
+        DmiTable[DimmIndex].Attributes = 0;
+        DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].DimmPresent = 0;
+        DmiTable[DimmIndex].Socket = Socket;
+        DmiTable[DimmIndex].Channel = Channel;
+        DmiTable[DimmIndex].Dimm = Dimm;
+
+        for (i = 0; i < 4; i++) {
+          DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
+        }
+
+        for (i = 0; i < 18; i++) {
+          DmiTable[DimmIndex].PartNumber[i] = 0xFF;
+        }
+
+        if (SpdDataStructure[DimmIndex].DimmPresent) {
+          // Total Width (offset 08h) & Data Width (offset 0Ah)
+          TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8];
+          if ((TotalWidth & 0x18) == 0) {
+            // non ECC
+            if ((TotalWidth & 0x07) == 0) {
+              DmiTable[DimmIndex].TotalWidth = 8;           // 8 bits
+            } else if ((TotalWidth & 0x07) == 1) {
+              DmiTable[DimmIndex].TotalWidth  = 16;         // 16 bits
+            } else if ((TotalWidth & 0x07) == 2) {
+              DmiTable[DimmIndex].TotalWidth  = 32;         // 32 bits
+            } else if ((TotalWidth & 0x07) == 3) {
+              DmiTable[DimmIndex].TotalWidth  = 64;         // 64 bits
+            }
+            DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ;
+          } else {
+            // ECC
+            if ((TotalWidth & 0x07) == 0) {
+              DmiTable[DimmIndex].TotalWidth  = 8 + 8;      // 8 bits
+            } else if ((TotalWidth & 0x07) == 1) {
+              DmiTable[DimmIndex].TotalWidth = 16 + 8;      // 16 bits
+            } else if ((TotalWidth & 0x07) == 2) {
+              DmiTable[DimmIndex].TotalWidth  = 32 + 8;     // 32 bits
+            } else if ((TotalWidth & 0x07) == 3) {
+              DmiTable[DimmIndex].TotalWidth  = 64 + 8;     // 64 bits
+            }
+            DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8;
+          }
+
+          // Memory Size (offset 0Ch)
+          Capacity = 0;
+          BusWidth = 0;
+          Width = 0;
+          Rank = 0;
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[4];
+          if ((temp & 0x0F) == 0) {
+            Capacity = 0x0100;                              // 256M
+          } else if ((temp & 0x0F) == 1) {
+            Capacity = 0x0200;                              // 512M
+          } else if ((temp & 0x0F) == 2) {
+            Capacity = 0x0400;                              // 1G
+          } else if ((temp & 0x0F) == 3) {
+            Capacity = 0x0800;                              // 2G
+          } else if ((temp & 0x0F) == 4) {
+            Capacity = 0x1000;                              // 4G
+          } else if ((temp & 0x0F) == 5) {
+            Capacity = 0x2000;                              // 8G
+          } else if ((temp & 0x0F) == 6) {
+            Capacity = 0x4000;                              // 16G
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[8];
+          if ((temp & 0x07) == 0) {
+            BusWidth = 8;                                   // 8 bits
+          } else if ((temp & 0x07) == 1) {
+            BusWidth = 16;                                  // 16 bits
+          } else if ((temp & 0x07) == 2) {
+            BusWidth = 32;                                  // 32 bits
+          } else if ((temp & 0x07) == 3) {
+            BusWidth = 64;                                  // 64 bits
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
+          if ((temp & 0x07) == 0) {
+            Width = 4;                                      // 4 bits
+          } else if ((temp & 0x07) == 1) {
+            Width = 8;                                      // 8 bits
+          } else if ((temp & 0x07) == 2) {
+            Width = 16;                                     // 16 bits
+          } else if ((temp & 0x07) == 3) {
+            Width = 32;                                     // 32 bits
+          }
+
+          temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
+          if (((temp >> 3) & 0x07) == 0) {
+            Rank = 1;                                       // 4 bits
+            DmiTable[DimmIndex].Attributes = 1;             // Single Rank Dimm
+          } else if (((temp >> 3) & 0x07) == 1) {
+            Rank = 2;                                       // 8 bits
+            DmiTable[DimmIndex].Attributes = 2;             // Dual Rank Dimm
+          } else if (((temp >> 3) & 0x07) == 2) {
+            Rank = 3;                                       // 16 bits
+          } else if (((temp >> 3) & 0x07) == 3) {
+            Rank = 4;                                       // 32 bits
+            DmiTable[DimmIndex].Attributes = 4;             // Quad Rank Dimm
+          }
+
+          DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank);
+
+          // Form Factor (offset 0Eh)
+          FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3];
+          if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) {
+            DmiTable[DimmIndex].FormFactor = 0x09;         // RDIMM or UDIMM
+          } else if ((FormFactor & 0x03) == 0) {
+            DmiTable[DimmIndex].FormFactor = 0x0D;         // SO-DIMM
+          }
+
+          // DIMM Present
+          DmiTable[DimmIndex].DimmPresent = 1;
+
+          // Speed (offset 15h)
+          Speed = (UINT16) SpdDataStructure[DimmIndex].Data[12];
+          if (Speed == 20) {
+            DmiTable[DimmIndex].Speed = 800;                // DDR3-800
+          } else if (Speed == 15) {
+            DmiTable[DimmIndex].Speed = 1066;               // DDR3-1066
+          } else if (Speed == 12) {
+            DmiTable[DimmIndex].Speed = 1333;               // DDR3-1333
+          } else if (Speed == 10) {
+            DmiTable[DimmIndex].Speed = 1600;               // DDR3-1600
+          }
+
+          // Manufacturer (offset 17h)
+          ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118];
+          DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]);
+
+          // Serial Number (offset 18h)
+          for (i = 0; i < 4; i++) {
+            DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122];
+          }
+          // Part Number (offset 1Ah)
+          for (i = 0; i < 18; i++) {
+            DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128];
+          }
+
+          // AGESA does NOT support this feature when bank interleaving is enabled.
+          if (!RefPtr->EnableBankIntlv) {
+          if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
+            Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0;
+              Address = Address >> 2;
+              DmiTable[DimmIndex].StartingAddr = Address;
+              DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
+            }
+          }
+        }  // Dimm present
+      }    // Dimm loop
+    }      // Channel loop
+  }          // Socket loop
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function gets DDR2 DMI information from SPD buffer and stores the info into heap
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8  i;
+  UINT8  Dimm;
+  UINT8  Socket;
+  UINT8  NodeId;
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT8  temp;
+  UINT8  MaxDimms;
+  UINT8  DimmIndex;
+  UINT8  MaxChannelsPerSocket;
+  UINT8  MaxDimmsPerChannel;
+  UINT8  FormFactor;
+  UINT8  Temp;
+  UINT8  Rank;
+  UINT16 TotalWidth;
+  UINT32 Speed;
+  UINT32 MaxSockets;
+  UINT32 Address;
+
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DMI_INFO *DmiTable;
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SpdDataStructure;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  MemPtr = MemMainPtr->MemPtr;
+  SpdDataStructure = MemPtr->SpdDataStructure;
+  MCTPtr = NBPtr->MCTPtr;
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Initialize local variables
+  MaxDimms = 0;
+
+  ASSERT (NBPtr != NULL);
+
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
+      temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      MaxDimms = MaxDimms + temp;
+    }
+  }
+
+  // Allocate heap for memory DMI table 16, 17, 19, 20
+  AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3;
+
+  AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2
+    return FALSE;
+  }
+
+  DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+  *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms;          // Number of memory devices
+  *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType;  // Memory type
+
+  //
+  // DMI TYPE 17
+  //
+  DimmIndex = 0;
+  for (Socket = 0; Socket < MaxSockets; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      //
+      // Get Node number and Dct number for this channel
+      //
+      ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
+      NodeId = ChannelPtr->MCTPtr->NodeId;
+      Dct = ChannelPtr->Dct;
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
+      MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
+      for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
+        DmiTable[DimmIndex].TotalWidth = 0xFFFF;
+        DmiTable[DimmIndex].DataWidth = 0xFFFF;
+        DmiTable[DimmIndex].MemorySize = 0xFFFF;
+        DmiTable[DimmIndex].Speed = 0;
+        DmiTable[DimmIndex].ManufacturerIdCode = 0;
+        DmiTable[DimmIndex].Attributes = 0;
+        DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
+        DmiTable[DimmIndex].DimmPresent = 0;
+
+        for (i = 0; i < 4; i++) {
+          DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
+        }
+
+        for (i = 0; i < 18; i++) {
+          DmiTable[DimmIndex].PartNumber[i] = 0xFF;
+        }
+
+        if (SpdDataStructure[DimmIndex].DimmPresent) {
+          // Total Width (offset 08h) & Data Width (offset 0Ah)
+          TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13];
+          if ((TotalWidth & 0x04) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 4;          // 4 bits
+          } else if ((TotalWidth & 0x08) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 8;          // 8 bits
+          } else if ((TotalWidth & 0x10) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 16;         // 16 bits
+          } else if ((TotalWidth & 0x20) != 0) {
+            DmiTable[DimmIndex].TotalWidth = 32;         // 32 bits
+          }
+          DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth;
+
+          // Memory Size (offset 0Ch), Attributes (offset 1Bh)
+          Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07;
+          if (Rank == 0) {
+            DmiTable[DimmIndex].Attributes = 1;          // Single Rank Dimm
+          } else if (Rank == 1) {
+            DmiTable[DimmIndex].Attributes = 2;          // Dual Rank Dimm
+          } else if (Rank == 3) {
+            DmiTable[DimmIndex].Attributes = 4;          // Quad Rank Dimm
+          }
+
+          Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31];
+          for (i = 0; i < 8; i++) {
+            if ((Temp & 0x01) == 1) {
+              DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1);
+            }
+            Temp = Temp >> 1;
+          }
+
+          // Form Factor (offset 0Eh)
+          FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
+          if ((FormFactor & 0x20) == 4) {
+            DmiTable[DimmIndex].FormFactor = 0x0D;       // SO-DIMM
+          } else {
+            DmiTable[DimmIndex].FormFactor = 0x09;       // RDIMM or UDIMM
+          }
+
+          // DIMM Present
+          DmiTable[DimmIndex].DimmPresent = 1;
+
+          // DIMM Index
+          DmiTable[DimmIndex].Socket = Socket;
+          DmiTable[DimmIndex].Channel = Channel;
+          DmiTable[DimmIndex].Dimm = Dimm;
+
+          // Speed (offset 15h)
+          Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg);
+          Speed = Speed & 0x00000007;
+          if (Speed == 0) {
+            DmiTable[DimmIndex].Speed = 400;              // 400MHz
+          } else if (Speed == 1) {
+            DmiTable[DimmIndex].Speed = 533;              // 533MHz
+          } else if (Speed == 2) {
+            DmiTable[DimmIndex].Speed = 667;              // 667MHz
+          } else if (Speed == 3) {
+            DmiTable[DimmIndex].Speed = 800;              // 800MHz
+          }
+
+          // Manufacturer (offset 17h)
+          DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64];
+
+          // Serial Number (offset 18h)
+          for (i = 0; i < 4; i++) {
+            DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95];
+          }
+
+          // Part Number (offset 1Ah)
+          for (i = 0; i < 18; i++) {
+            DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73];
+          }
+
+          // AGESA does NOT support this feature when bank interleaving is enabled.
+          if (!RefPtr->EnableBankIntlv) {
+            if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
+              Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0;
+              Address = Address >> 2;
+              DmiTable[DimmIndex].StartingAddr = Address;
+              DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
+            }
+          }
+
+        }        // DIMM Present
+      }          // DIMM loop
+    }
+  }
+
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
new file mode 100755
index 0000000000..36d8a63f49
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.c
@@ -0,0 +1,315 @@
+/**
+ * @file
+ *
+ * mfecc.c
+ *
+ * Feature ECC initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/ECC)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfecc.h"
+#include "Filecode.h"
+#include "mfmemclr.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#ifdef UNUSED_CODE
+UINT32
+STATIC
+MemFGetScrubAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+#endif
+
+VOID
+STATIC
+InitECCOverriedeStruct (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   ECC_OVERRIDE_STRUCT *pecc_override_struct
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function checks to see if ECC can be enabled on all nodes
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  MEM_SHARED_DATA *SharedPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  SharedPtr = NBPtr->SharedPtr;
+
+  if (MCTPtr->NodeMemSize != 0) {
+    if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (MCTPtr->ErrCode < AGESA_ERROR)) {
+      // Clear all MCA reports before using scrubber
+      // to initialize ECC check bits
+      //
+      NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg);
+      NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0);
+      NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0);
+      // In unganged mode, set DctDctIntlv
+      if (!NBPtr->Ganged) {
+        NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1);
+      }
+      //
+      // Set Ecc Symbol Size
+      //
+      NBPtr->SetEccSymbolSize (NBPtr);
+      // If ECC can be enabled on this node,
+      // set the master ECCen bit (according to setup)
+      //
+      NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
+      // Do mem clear on current node
+      MemFMctMemClr_Init (NBPtr);
+      return TRUE;
+    } else {
+      if (SharedPtr->AllECC) {
+        SharedPtr->AllECC = FALSE;
+      }
+      // ECC requested but cannot be enabled
+      MCTPtr->Status[SbEccDimms] = FALSE;
+      MCTPtr->ErrStatus[EsbDramECCDis] = TRUE;
+      PutEventLog (AGESA_ERROR, MEM_ERROR_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, MCTPtr);
+    }
+  }
+  return FALSE;
+}
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the ECC on all nodes
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInitECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Node;
+  UINT32 ScrubAddrRJ16;
+  DIE_STRUCT *MCTPtr;
+  ECC_OVERRIDE_STRUCT  ecc_override_struct;
+  InitECCOverriedeStruct (NBPtr, &ecc_override_struct);
+  IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader));
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  Node = MCTPtr->NodeId;
+
+  if (MCTPtr->Status[SbEccDimms]) {
+    // Program scrub address,
+    // let the scrub Addr be the Base of this Node
+    // Only enable Dram scrubber when there is memory on current node
+    //
+    NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0);
+    ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
+    ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24;
+    NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
+    NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
+
+    // Check if the input dram scrub rate is supported or not
+    ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16);
+    NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate);
+  }
+  // Scrub CTL for Dcache, L2, L3
+  // Check if the input L2 scrub rate is supported or not
+  ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16);
+  NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate);
+  // Check if the input Dcache scrub rate is supported or not
+  ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16);
+  NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate);
+  // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[DisableL3] is 1
+  if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFF3X188B8) == 0)) {
+    // Check if input L3 scrub rate is supported or not
+    ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16);
+    NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate);
+  }
+
+  // Check if Dcache scrubber or L2 scrubber is enabled
+  if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) {
+    // If ClkDivisor is deeper than divide-by-16
+    if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) {
+      // Set it to divide-by-16
+      NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4);
+    }
+  }
+
+  NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection);
+  NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood);
+  // Restore MCA reports after scrubber is done
+  // with initializing ECC check bits
+  NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg);
+  return TRUE;
+}
+
+VOID
+STATIC
+InitECCOverriedeStruct (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   ECC_OVERRIDE_STRUCT *pecc_override_struct
+  )
+{
+  pecc_override_struct->CfgEccRedirection = UserOptions.CfgEccRedirection;
+  pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood;
+  pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate;
+
+  if (UserOptions.CfgScrubDramRate != 0xFF) {
+    pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate;
+  } else {
+    if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) {
+      pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) {
+      pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) {
+      pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) {
+      pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB
+    } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) {
+      pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB
+    } else {
+      pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above
+    }
+  }
+
+  pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate;
+  pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate;
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This function gets the current 40-bit Scrub ADDR address, scaled to 32-bits,
+ *                of the specified Node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          Scrubber Address
+ */
+#ifdef UNUSED_CODE
+UINT32
+STATIC
+MemFGetScrubAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 ScrubAddrHi;
+  UINT32 ScrubAddrLo;
+  UINT32 ScrubAddrRJ16;
+
+  ASSERT (NBPtr != NULL);
+
+  ScrubAddrHi = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg);
+  ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg);
+  // Scrub Addr High again, detect 32-bit wrap
+  ScrubAddrRJ16 = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg);
+  if (ScrubAddrRJ16 != ScrubAddrHi) {
+    ScrubAddrHi = ScrubAddrRJ16;
+    ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg);
+  }
+  return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
+}
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
new file mode 100755
index 0000000000..61877dae05
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfecc.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfecc.h
+ *
+ * Feature ECC initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFECC_H_
+#define _MFECC_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInitECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFECC_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
new file mode 100755
index 0000000000..8f7aaccae7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ECC/mfemp.c
@@ -0,0 +1,173 @@
+/**
+ * @file
+ *
+ * mfemp.c
+ *
+ * Feature EMP initialization functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/ECC)
+ * @e \$Revision: 6168 $ @e \$Date: 2008-05-28 22:26:15 -0500 (Wed, 28 May 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN       UINT32 Value
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes EMP (Enhanced Memory Protection)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  if (RefPtr->EnableEccFeature) {
+    if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE;
+    } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPConflict] = TRUE;
+    } else if ((!MCTPtr->GangedMode) &&
+               (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) &&
+                !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      MCTPtr->ErrStatus[EsbEMPDis] = TRUE;
+    } else {
+      // Reduce memory size to 7/8 of the original memory size
+      ASSERT ((MCTPtr->NodeMemSize % 8) == 0);
+      NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0);
+      MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7;
+      NBPtr->HtMemMapInit (NBPtr);
+      NBPtr->CpuMemTyping (NBPtr);
+
+      // Enable EMP
+      NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
+
+      // Scrub CTL settings for Dcache, L2
+      NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate);
+      NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate);
+
+      NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood);
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function checks to see if the input is power of two.
+ *
+ *     @param[in]    Value   - Value to check for power of two
+ *
+ *     @return          TRUE     - is power of two
+ *                      FALSE    - is not power of two
+ */
+BOOLEAN
+STATIC
+IsPowerOfTwo (
+  IN       UINT32 Value
+  )
+{
+  return (BOOLEAN) ((Value & (Value - 1)) == 0);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
new file mode 100755
index 0000000000..3bf0269ce0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * mfdimmexclud.c
+ *
+ * Feature DIMM exclude.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/EXCLUDIMM)
+ * @e \$Revision: 6943 $ @e \$Date: 2008-08-206 20:51:30 +0800 (Sat, 26 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and disable Chip selects that fail training for each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ReserveDCT;
+  UINT8 q;
+  BOOLEAN Flag;
+  BOOLEAN IsCSIntlvEnabled;
+  UINT16 CsTestFail;
+  DIE_STRUCT *MCTPtr;
+  BOOLEAN RetVal;
+
+  ASSERT (NBPtr != NULL);
+  ReserveDCT = NBPtr->Dct;
+  CsTestFail = 0;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.CsTestFail != 0) {
+      // When there is no new failed dimm that needs to be excluded, then no need to go through the process.
+      switch (NBPtr->SharedPtr->DimmExcludeFlag) {
+      case NORMAL:
+        // See there is new dimm that needs to be excluded
+        if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) {
+          CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
+        }
+        break;
+      case TRAINING:
+        // Do not do any dimm excluding during training
+        // Dimm exclude will be done at the end of training
+        break;
+      case END_TRAINING:
+        // Exclude all dimms that have failures during training
+        if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) ||
+            ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) {
+          CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
+        }
+        break;
+      default:
+        IDS_ERROR_TRAP;
+      }
+    }
+  }
+
+  if (CsTestFail != 0) {
+    IsCSIntlvEnabled = FALSE;
+    MCTPtr = NBPtr->MCTPtr;
+    MCTPtr->NodeMemSize = 0;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0;
+    NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+    NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0);
+
+    if (MCTPtr->GangedMode) {
+      // if ganged mode, disable all pairs of CS that fail.
+      NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail;
+    }
+
+    // if chip select interleaving has been enabled, need to undo it before remapping memory
+    if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) {
+      IsCSIntlvEnabled = TRUE;
+    }
+
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          NBPtr->DCTPtr->Timings.DctMemSize = 0;
+
+          NBPtr->DCTPtr->Timings.CsEnabled = 0;
+          for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+            NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
+          }
+
+          Flag = NBPtr->StitchMemory (NBPtr);
+          ASSERT (Flag == TRUE);
+        }
+      }
+    }
+
+    // Re-enable chip select interleaving when remapping is done.
+    if (IsCSIntlvEnabled) {
+      NBPtr->FeatPtr->InterleaveBanks (NBPtr);
+    }
+
+    RetVal = TRUE;
+  } else {
+    RetVal = FALSE;
+  }
+  NBPtr->SwitchDCT (NBPtr, ReserveDCT);
+  return RetVal;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
new file mode 100755
index 0000000000..3beae2bb6a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -0,0 +1,523 @@
+/**
+ * @file
+ *
+ * mfidendimm.c
+ *
+ * Translate physical system address to dimm identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat)
+ * @e \$Revision: 6314 $ @e \$Date: 2008-06-10 06:43:56 -0500 (Tue, 10 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "heapManager.h"
+#include "mfidendimm.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_DIE        2   ///< Max DCTs per die
+#define MAX_CHLS_PER_DCT        1   ///< Max Channels per DCT
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+STATIC
+MemFTransSysAddrToCS (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify,
+  IN       MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+UINT32
+STATIC
+MemFGetPCI (
+  IN   MEM_NB_BLOCK *NBPtr,
+  IN   UINT8 NodeID,
+  IN   UINT8 DctNum,
+  IN   BIT_FIELD_NAME BitFieldName
+  );
+
+UINT8
+STATIC
+MemFUnaryXOR (
+  IN   UINT32 address
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function identifies the dimm on which the given memory address locates.
+*
+*   @param[in, out]   *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
+*
+*   @retval           AGESA_SUCCESS - Successfully translate physical system address
+*                                     to dimm identification.
+*                     AGESA_BOUNDS_CHK - Targeted address is out of bound.
+*
+*/
+
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+  )
+{
+  UINT8 i;
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;             // Main Data block
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT MemData;
+  LOCATE_HEAP_PTR LocHeap;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 Node;
+  UINT8 Dct;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader));
+  mmData.MemPtr = &MemData;
+  RetVal = MemSocketScan (&mmData);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  // Search for AMD_MEM_AUTO_HANDLE on the heap first.
+  // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
+  LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
+    AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) {
+      PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader);
+      ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM
+      return AGESA_FATAL;
+    }
+    NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+    mmData.NBPtr = NBPtr;
+    // Construct each die.
+    for (Die = 0; Die < DieCount; Die ++) {
+      i = 0;
+      while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) {
+        if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) {
+          break;
+        }
+        i++;
+      };
+      if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) {
+        PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader);
+        ASSERT(FALSE); // No Identify DIMM constructor found
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) {
+    // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number.
+    Node = AmdDimmIdentify->SocketId;
+    Dct = AmdDimmIdentify->MemChannelId;
+    AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId;
+    AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0);
+    AmdDimmIdentify->DimmId /= 2;
+  }
+
+  return RetVal;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function translates the given physical system address to
+*   a node, channel select, chip select, bank, row, and column address.
+*
+*   @param[in, out]   *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
+*   @param[in, out]   *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
+*
+*   @retval           AGESA_SUCCESS - The chip select address is found
+*   @retval           AGESA_BOUNDS_CHK - Targeted address is out of bound.
+*
+*/
+AGESA_STATUS
+STATIC
+MemFTransSysAddrToCS (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify,
+  IN       MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  BOOLEAN CSFound;
+  BOOLEAN DctSelHiRngEn;
+  BOOLEAN DctSelIntLvEn;
+  BOOLEAN DctGangEn;
+  BOOLEAN HiRangeSelected;
+  BOOLEAN DramHoleValid;
+  BOOLEAN CSEn;
+  BOOLEAN SwapDone;
+  BOOLEAN IntLvRgnSwapEn;
+  UINT8 DctSelHi;
+  UINT8 DramEn;
+  UINT8 range;
+  UINT8 IntlvEn;
+  UINT8 IntlvSel;
+  UINT8 ILog;
+  UINT8 DctSelIntLvAddr;
+  UINT8 DctNum;
+  UINT8 cs;
+  UINT8 BadDramCs;
+  UINT8 spare;
+  UINT8 IntLvRgnBaseAddr;
+  UINT8 IntLvRgnLmtAddr;
+  UINT8 IntLvRgnSize;
+  UINT32 temp;
+  UINT32 DramHoleOffset;
+  UINT64 DramBase;
+  UINT64 DramLimit;
+  UINT64 DctSelBaseAddr;
+  UINT64 DctSelBaseOffset;
+  UINT64 ChannelAddr;
+  UINT64 CSBase;
+  UINT64 CSMask;
+  UINT64 InputAddr;
+  UINT64 ChannelOffset;
+  MEM_NB_BLOCK *NBPtr;
+
+  UINT64 SysAddr;
+  UINT8 *NodeID;
+  UINT8 *ChannelSelect;
+  UINT8 *ChipSelect;
+
+  SysAddr = AmdDimmIdentify->MemoryAddress;
+  NodeID = &(AmdDimmIdentify->SocketId);
+  ChannelSelect = &(AmdDimmIdentify->MemChannelId);
+  ChipSelect = &(AmdDimmIdentify->DimmId);
+  CSFound = FALSE;
+  ILog = 0;
+  NBPtr = mmPtr->NBPtr;
+
+  // Loop to determine the dram range
+  for (range = 0; range < mmPtr->DieCount; range ++) {
+    // DRAM Base
+    temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range);
+    DramEn = (UINT8) (temp & 0x3);
+    IntlvEn = (UINT8) ((temp >> 8) & 0x7);
+
+    DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) |
+                 (((UINT64) temp & 0xFFFF0000) << 8);
+
+    // DRAM Limit
+    temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range);
+    *NodeID = (UINT8) (temp & 0x7);
+    IntlvSel = (UINT8) ((temp >> 8) & 0x7);
+    DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) |
+                  (((UINT64) temp << 8) | 0xFFFFFF);
+
+
+    if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimit) &&
+        ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) {
+      // Determine the number of bit positions consumed by Node Interleaving
+      switch (IntlvEn) {
+
+      case 0x0:
+        ILog = 0;
+        break;
+
+      case 0x1:
+        ILog = 1;
+        break;
+
+      case 0x3:
+        ILog = 2;
+        break;
+
+      case 0x7:
+        ILog = 3;
+        break;
+
+      default:
+        IDS_ERROR_TRAP;
+      }
+
+      // F2x10C Swapped Interleaved Region
+      IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn);
+      if (IntLvRgnSwapEn) {
+        IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr);
+        IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr);
+        IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize);
+        ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
+        if (((SysAddr >> 34) == 0) &&
+          ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr))
+           || ((SysAddr >> 27) < IntLvRgnSize))) {
+          SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
+        }
+      }
+
+      // Extract variables from F2x110 DRAM Controller Select Low Register
+      DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn);
+      DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi);
+      DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn);
+      DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn);
+      DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr);
+      DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27;
+      DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26;
+
+
+      // Determine if high DCT address range is being selected
+      if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) {
+        HiRangeSelected = TRUE;
+      } else {
+        HiRangeSelected = FALSE;
+      }
+
+      // Determine Channel
+      if (DctGangEn) {
+        *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1);
+      } else if (HiRangeSelected) {
+        *ChannelSelect = DctSelHi;
+      } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) {
+        *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1);
+      } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) {
+        temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F));
+        if ((DctSelIntLvAddr & 0x1) != 0) {
+          *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp);
+        } else {
+          *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp);
+        }
+      } else if (DctSelIntLvEn) {
+        *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1);
+      } else if (DctSelHiRngEn) {
+        *ChannelSelect = ~DctSelHi & 0x1;
+      } else {
+        *ChannelSelect = 0;
+      }
+      ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount);
+
+      DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23;
+      DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid);
+
+      // Determine base address offset
+      if (HiRangeSelected) {
+        if (((DctSelBaseAddr >> 32) == 0) && DramHoleValid && (SysAddr >= 0x100000000ull)) {
+          ChannelOffset = (UINT64) DramHoleOffset;
+        } else {
+          ChannelOffset = DctSelBaseOffset;
+        }
+      } else {
+        if (DramHoleValid && (SysAddr >= 0x100000000ull)) {
+          ChannelOffset = (UINT64) DramHoleOffset;
+        } else {
+          ChannelOffset = DramBase;
+        }
+      }
+
+      // Remove hoisting offset and normalize to DRAM bus addresses
+      ChannelAddr = SysAddr - ChannelOffset;
+
+      // Remove node interleaving
+      if (IntlvEn != 0) {
+        ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF);
+      }
+
+      // Remove channel interleave
+      if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) {
+        if ((DctSelIntLvAddr & 1) != 1) {
+          // A[6] Select or Hash 6
+          ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F);
+        } else if (DctSelIntLvAddr == 1) {
+          // A[12]
+          ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF);
+        } else {
+          // Hash 9
+          ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF);
+        }
+      }
+
+      // Determine the Chip Select
+      for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) {
+        DctNum = DctGangEn ? 0 : *ChannelSelect;
+
+        // Obtain the CS Base
+        temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs);
+        CSEn = (BOOLEAN) (temp & 0x1);
+        CSBase = ((UINT64) temp & CS_REG_MASK) << 8;
+
+        // Obtain the CS Mask
+        CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & CS_REG_MASK) << 8;
+
+        // Adjust the Channel Addr for easy comparison
+        InputAddr = ((ChannelAddr >> 8) & CS_REG_MASK) << 8;
+
+        if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) {
+          CSFound = TRUE;
+
+          *ChipSelect = cs;
+
+          temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl);
+          SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1);
+          BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7);
+          if (SwapDone && (cs == BadDramCs)) {
+            // Find the spare rank for the channel
+            for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) {
+              if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) {
+                *ChipSelect = spare;
+                break;
+              }
+            }
+          }
+          ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL);
+
+          break;
+        }
+      }
+    }
+    if (CSFound) {
+      break;
+    }
+  }
+
+  // last ditch sanity check
+  ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL)));
+  if (CSFound) {
+    return AGESA_SUCCESS;
+  } else {
+    return AGESA_BOUNDS_CHK;
+  }
+
+}
+
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function is the interface to call the PCI register access function
+*   defined in NB block.
+*
+*   @param[in]   *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK
+*   @param[in]   NodeID - Node ID number of the target Northbridge
+*   @param[in]   DctNum - DCT number if applicable, otherwise, put 0
+*   @param[in]   BitFieldName - targeted bitfield
+*
+*   @retval      UINT32 - 32 bits PCI register value
+*
+*/
+UINT32
+STATIC
+MemFGetPCI (
+  IN   MEM_NB_BLOCK *NBPtr,
+  IN   UINT8 NodeID,
+  IN   UINT8 DctNum,
+  IN   BIT_FIELD_NAME BitFieldName
+  )
+{
+  MEM_NB_BLOCK *LocalNBPtr;
+  // Get the northbridge pointer for the targeted node.
+  LocalNBPtr = &NBPtr[NodeID];
+  LocalNBPtr->Dct = DctNum;
+  // The caller of this function will take care of the ganged/unganged situation.
+  // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum.
+  return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+*
+*   This function returns an even parity bit (making the total # of 1's even)
+*   {0, 1} = number of set bits in argument is {even, odd}.
+*
+*   @param[in]   address - the address on which the parity bit will be calculated
+*
+*   @retval      UINT8 - parity bit
+*
+*/
+
+UINT8
+STATIC
+MemFUnaryXOR (
+  IN   UINT32 address
+  )
+{
+  UINT8 parity;
+  UINT8 index;
+  parity = 0;
+  for (index = 0; index < 32; ++ index) {
+    parity = (UINT8) (parity ^ (address & 0x1));
+    address = address >> 1;
+  }
+  return parity;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
new file mode 100755
index 0000000000..7ec7bc79d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
@@ -0,0 +1,108 @@
+/**
+ * @file
+ *
+ * mfidendimm.h
+ *
+ * Header file for address to dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 6609 $ @e \$Date: 2008-07-02 17:11:21 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFIDENDIMM_H_
+#define _MFIDENDIMM_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define CS_REG_MASK 0x1FF83FE0
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemNIdentifyDimmConstructorLN (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+#endif //_MFIDENDIMM_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
new file mode 100755
index 0000000000..e271834562
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
@@ -0,0 +1,148 @@
+/**
+ * @file
+ *
+ * mfrintlv.c
+ *
+ * Feature Region interleaving support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Intlvrgn)
+ * @e \$Revision: 9110 $ @e \$Date: 2008-10-28 01:16:14 +0800 (Tue, 28 Oct 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfintlvrn.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_RJ27 ((UINT32)4 << (30 - 27))
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   MemFInterleaveRegion:
+ *
+ *  Applies region interleaving if both DCTs have different size of memory, and
+ *  the channel interleaving region doesn't have UMA covered.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemFInterleaveRegion (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 TOM;
+  UINT32 TOM2;
+  UINT32 TOMused;
+  UINT32 UmaBase;
+  UINT32 DctSelBase;
+  S_UINT64 SMsr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  MemPtr = NBPtr->MemPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16);
+
+  //TOM scaled from [47:0] to [47:27]
+  LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
+
+  //TOM2 scaled from [47:0] to [47:27]
+  LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
+
+  TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM;
+
+  if (UmaBase != 0) {
+    //Check if channel interleaving is enabled ? if so, go to next step.
+    if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) {
+      DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr);
+      //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1.
+      if (DctSelBase != 0) {
+        //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA.
+        if (DctSelBase < TOMused) {
+          IDS_HDT_CONSOLE ("@\tStarting Interleave Region for Socket %d Die %d\n", NBPtr->MCTPtr->SocketId, NBPtr->Node);
+          NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused);
+        }
+      }
+    }
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
new file mode 100755
index 0000000000..77070f7947
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mfintlvrn.h
+ *
+ * Feature region interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 9110 $ @e \$Date: 2008-10-28 01:16:14 +0800 (Tue, 28 Oct 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFINTLVRN_H_
+#define _MFINTLVRN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemFInterleaveRegion (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFINTLVRN_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
new file mode 100755
index 0000000000..ea1248cd56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.c
@@ -0,0 +1,167 @@
+/**
+ * @file
+ *
+ * lvddr3.c
+ *
+ * Voltage change for DDR3 DIMMs.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/LVDDR3)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE
+/* features */
+#include "mflvddr3.h"
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculate the common lowest voltage supported by all DDR3
+ *   DIMMs in the system. This function only needs to be called on BSP.
+ *
+ *   @param[in, out]    *NBPtr - Pointer to NB block
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFLvDdr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_TECH_BLOCK  *TechPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 Dimm;
+  UINT8 *SpdBufferPtr;
+  UINT8 VDDByte;
+  UINT8 VoltageMap;
+
+  mmSharedPtr = NBPtr->SharedPtr;
+  TechPtr = NBPtr->TechPtr;
+  VoltageMap = 0xFF;
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) {
+          // SPD byte 6: Module Nominal Voltage, VDD
+          // 1.5v - bit 0
+          // 1.35v - bit 1
+          // 1.2v - bit 2
+          VDDByte = SpdBufferPtr[MNVVDD];
+          // Reverse the 1.5V operable bit. So its encoding can be consistent
+          // with that of 1.35V and 1.25V operable bit.
+          VDDByte ^= 1;
+          ASSERT (VDDByte != 0);
+
+          if (mmSharedPtr->VoltageMap != 0) {
+            // Get the common supported voltage map
+            VoltageMap &= VDDByte;
+          } else {
+            // This is the second execution of all the loop as no common voltage is found
+            if (VDDByte == (1 << VOLT1_5)) {
+              // Always exclude 1.5V dimm if no common voltage is found
+              ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm;
+            }
+          }
+        }
+      }
+      if (mmSharedPtr->VoltageMap == 0) {
+        NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude;
+      }
+    }
+  }
+
+  if (mmSharedPtr->VoltageMap != 0) {
+    mmSharedPtr->VoltageMap &= VoltageMap;
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h
new file mode 100755
index 0000000000..0d5428c560
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/LVDDR3/mflvddr3.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * mflvddr3.h
+ *
+ * Header file for DDR3 DIMMs voltage configuration.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 6609 $ @e \$Date: 2008-07-02 17:11:21 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFLVDDR3_H_
+#define _MFLVDDR3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MNVVDD 6
+#define LOWEST_VOLT_BIT 2
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFLvDdr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+);
+
+#endif //_MFLVDDR3_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
new file mode 100755
index 0000000000..8a07406c37
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/MEMCLR/mfmemclr.c
@@ -0,0 +1,147 @@
+/**
+ * @file
+ *
+ * mfmemclr.c
+ *
+ * Feature function for memory clear operation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Memclr)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfmemclr.h"
+#include "Ids.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Initiates memory clear operation on one node with Dram on it.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemFMctMemClr_Init (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader);
+  if (NBPtr->RefPtr->EnableMemClr == TRUE) {
+    if (NBPtr->MCTPtr->NodeMemSize != 0) {
+      if (!NBPtr->MemCleared) {
+        NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE);
+        if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) {
+          NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+          NBPtr->SetBitField (NBPtr, BFMemClrInit, 1);
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Ensures memory clear operation has completed on one node with Dram on it.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemFMctMemClr_Sync (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 MicroSecondToWait;
+
+  MicroSecondToWait = 0;
+  if (NBPtr->RefPtr->EnableMemClr == TRUE) {
+    if (NBPtr->MCTPtr->NodeMemSize != 0) {
+      // Calculate Timeout value:
+      // Timeout (in microsecond) = Memory Size * 1.5 ns / 8 Byte * 4 (Margin) * 1000 (change mini-second to us)
+      // NodeMemSize is system address right shifted by 16, so shift it 4 bits to right to convert it to MB.
+      // 1.5 / 8 * 4 * 1000 = 750
+      MicroSecondToWait = (NBPtr->MCTPtr->NodeMemSize >> 4) * 750;
+
+      if (!NBPtr->MemCleared) {
+        NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, MicroSecondToWait, FALSE);
+        NBPtr->PollBitField (NBPtr, BFMemCleared, 1, MicroSecondToWait, FALSE);
+        NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16));
+        NBPtr->MemCleared = TRUE;
+      }
+    }
+  }
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
new file mode 100755
index 0000000000..c57a74b606
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.c
@@ -0,0 +1,239 @@
+/**
+ * @file
+ *
+ * mfndi.c
+ *
+ * Feature applies Node memory interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Ndintlv)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+  *       its contributors may be used to endorse or promote products derived
+  *       from this software without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mport.h"
+#include "mfndi.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_ (0x10000)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFCheckInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Perform a check to see if node interleaving can be enabled on each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Node interleaving can be enabled.
+ *     @return          FALSE - Node interleaving cannot be enabled.
+ */
+
+BOOLEAN
+MemFCheckInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+
+  if (MCTPtr->NodeMemSize != 0) {
+    if (!NBPtr->SharedPtr->NodeIntlv.IsValid) {
+      NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize;
+      NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize;
+      NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE;
+    } else {
+      if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) ||
+          (NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) {
+        return FALSE;
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Applies Node memory interleaving for each node.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 NodeCnt;
+  UINT8 BitShift;
+  UINT32 MemSize;
+  UINT32 Dct0MemSize;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  UINT32 HoleBase;
+  UINT32 HoleSize;
+  UINT32 HoleOffset;
+  S_UINT64 SMsr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
+    HoleBase = RefPtr->HoleBase;
+    HoleSize = _4GB_ - HoleBase;
+  } else {
+    HoleBase = 0;
+    HoleSize = 0;
+  }
+
+  NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt;
+  Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize;
+  MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize;
+
+  BitShift = LibAmdBitScanForward (NodeCnt);
+  Dct0MemSize <<= BitShift;
+  if (HoleSize != 0) {
+    RefPtr->GStatus[GsbHWHole] = TRUE;
+    HoleOffset = HoleSize;
+    if (Dct0MemSize >= HoleBase) {
+      Dct0MemSize += HoleSize;
+    } else {
+      HoleOffset += Dct0MemSize;
+    }
+  } else {
+    HoleOffset = 0;
+  }
+
+  MemSize = (MemSize << BitShift) + HoleSize;
+
+  MCTPtr->NodeSysBase = 0;
+  MCTPtr->NodeSysLimit = MemSize - 1;
+  RefPtr->SysLimit = MemSize - 1;
+
+  // When node interleaving is enabled with larger than 1012GB memory,
+  // system memory limit will be lowered to fill in HT reserved region.
+  // TOP_MEM2 was set in CpuMemTyping and needs to be updated as well.
+  if (RefPtr->SysLimit >= HT_REGION_BASE_RJ16) {
+    if (RefPtr->LimitMemoryToBelow1Tb) {
+      SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16);
+      SMsr.lo = HT_REGION_BASE_RJ16 << 16;
+    } else {
+      SMsr.hi = MemSize >> (32 - 16);
+      SMsr.lo = MemSize << 16;
+    }
+    LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    IDS_HDT_CONSOLE ("TOP_MEM2: %08lx0000\n", MemSize);
+    RefPtr->Sub1THoleBase =  HT_REGION_BASE_RJ16;
+    RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1;
+  } else {
+    RefPtr->Sub1THoleBase =  RefPtr->SysLimit + 1;
+  }
+
+  NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel);
+  NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
+  NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1);
+  NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16));
+
+  if (HoleSize != 0) {
+    MCTPtr->Status[SbHWHole] = TRUE;
+    // DramHoleBase will be set when sync address map to other nodes.
+    NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16));
+    NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1);
+  }
+
+  if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
+    NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16));
+    NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16));
+  }
+
+  NodeSysBase = NodeCnt - 1;
+  NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel;
+  NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
+  NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
+  NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit;
+
+  NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++;
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
new file mode 100755
index 0000000000..20c1f8dc77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/NDINTLV/mfndi.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * mfndi.h
+ *
+ * Feature node interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+#ifndef _MFNDI_H_
+#define _MFNDI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFInterleaveNodes (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFNDI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
new file mode 100755
index 0000000000..659ba9d776
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
@@ -0,0 +1,168 @@
+/**
+ * @file
+ *
+ * mfodthermal.c
+ *
+ * On Dimm thermal management.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat)
+ * @e \$Revision: 6314 $ @e \$Date: 2008-06-10 06:43:56 -0500 (Tue, 10 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "mfodthermal.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function does On-Dimm thermal management.
+ *
+ *   @param[in, out]   *NBPtr - Pointer to the MEM_NB_BLOCK.
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFOnDimmThermal (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  UINT8 Dct;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_DATA_STRUCT *MemPtr;
+  UINT8 *SpdBufferPtr;
+  UINT8 ThermalOp;
+  BOOLEAN ODTSEn;
+  BOOLEAN ExtendTmp;
+
+  ODTSEn = FALSE;
+  ExtendTmp = FALSE;
+
+  ASSERT (NBPtr != NULL);
+  MemPtr = NBPtr->MemPtr;
+  AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader);
+
+  if (NBPtr->MCTPtr->NodeMemSize != 0) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      // Only go through the DCT if it is not disabled.
+      if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        // If Ganged mode is enabled, need to go through all dram devices on both DCTs.
+        if (!NBPtr->Ganged || (NBPtr->Dct != 1)) {
+          ODTSEn = TRUE;
+          ExtendTmp = TRUE;
+        }
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+          if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) {
+            // Check byte 31: thermal and refresh option.
+            ThermalOp = SpdBufferPtr[THERMAL_OPT];
+            // Bit 3: ODTS readout
+            if (!((ThermalOp >> 3) & 1)) {
+              ODTSEn = FALSE;
+            }
+            // Bit 0: Extended Temperature Range.
+            if (!(ThermalOp & 1)) {
+              ExtendTmp = FALSE;
+            }
+          }
+        }
+
+        if (!NBPtr->Ganged || (NBPtr->Dct == 1)) {
+          // If in ganged mode, need to switch back to DCT0 to set the registers.
+          if (NBPtr->Ganged) {
+            NBPtr->SwitchDCT (NBPtr, 0);
+            ChannelPtr = NBPtr->ChannelPtr;
+          }
+          // If all dram devices on a DCT support ODTS
+          if (ODTSEn) {
+            NBPtr->SetBitField (NBPtr, BFODTSEn, 1);
+          }
+
+          ChannelPtr->ExtendTmp = ExtendTmp;
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
new file mode 100755
index 0000000000..1ea7c2490b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * mfodthermal.h
+ *
+ * Header file for On-Dimm thermal management.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 6609 $ @e \$Date: 2008-07-02 17:11:21 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFODTHERMAL_H_
+#define _MFODTHERMAL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define THERMAL_OPT 31
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFOnDimmThermal (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif //_MFODTHERMAL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
new file mode 100755
index 0000000000..1aac4f44f8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.c
@@ -0,0 +1,166 @@
+/**
+ * @file
+ *
+ * mfspr.c
+ *
+ * Feature enable online spare
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/Olspare)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mfspr.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Enable online spare on current node if it is requested.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+
+BOOLEAN
+MemFOnlineSpare (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 q;
+  UINT8  Value8;
+  BOOLEAN Flag;
+  BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET];
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  RefPtr = NBPtr->RefPtr;
+  Flag = FALSE;
+  if (RefPtr->EnableOnLineSpareCtl != 0) {
+    RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE;
+    MCTPtr = NBPtr->MCTPtr;
+
+    // Check if online spare can be enabled on current node
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      ASSERT (Dct < sizeof (OnlineSprEnabled));
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      OnlineSprEnabled[Dct] = FALSE;
+      if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) {
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          // Make sure at least two chip-selects are available
+          Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled);
+          if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) {
+            OnlineSprEnabled[Dct] = TRUE;
+            Flag = TRUE;
+          } else {
+            PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            MCTPtr->ErrStatus[EsbSpareDis] = TRUE;
+          }
+        }
+      }
+    }
+
+    // If we don't have spared rank on any DCT, we don't run the rest part of the code.
+    if (!Flag) {
+      return FALSE;
+    }
+
+    MCTPtr->NodeMemSize = 0;
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (OnlineSprEnabled[Dct]) {
+        // Only run StitchMemory if we need to set a spare rank.
+        NBPtr->DCTPtr->Timings.DctMemSize = 0;
+        for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+          NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
+        }
+        Flag = NBPtr->StitchMemory (NBPtr);
+        ASSERT (Flag == TRUE);
+      } else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
+        // Otherwise, need to adjust the memory size on the node.
+        MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
+        MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1;
+      }
+    }
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
new file mode 100755
index 0000000000..c6fc4bcbaf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/OLSPARE/mfspr.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * mfspr.h
+ *
+ * Feature enable Online spare
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MFSPR_H_
+#define _MFSPR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFOnlineSpare (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFSPR_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
new file mode 100755
index 0000000000..8f124340e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
@@ -0,0 +1,284 @@
+/**
+ * @file
+ *
+ * mfParallelTraining.c
+ *
+ * This is the parallel training feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/PARTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
+
+/*-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *    This is the main function to perform parallel training on all nodes.
+ *    This is the routine which will run on the remote AP.
+ *
+ *     @param[in,out]   *EnvPtr   - Pointer to the Training Environment Data
+ *     @param[in,out]   *StdHeader   - Pointer to the Standard Header of the AP
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFParallelTraining (
+  IN OUT   REMOTE_TRAINING_ENV *EnvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  MEM_PARAMETER_STRUCT ParameterList;
+  MEM_NB_BLOCK NB;
+  MEM_TECH_BLOCK TB;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  UINT8 p;
+  UINT8 i;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 *BufferPtr;
+  UINT8 DctCount;
+  UINT8 ChannelCount;
+  UINT8 RowCount;
+  UINT8 ColumnCount;
+  UINT16 SizeOfNewBuffer;
+  AP_DATA_TRANSFER ReturnData;
+
+  //
+  // Initialize Parameters
+  //
+  ReturnData.DataPtr = NULL;
+  ReturnData.DataSizeInDwords = 0;
+  ReturnData.DataTransferFlags = 0;
+
+  ASSERT (EnvPtr != NULL);
+  //
+  // Replace Standard header of a AP
+  //
+  LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
+
+  IDS_HDT_CONSOLE_INIT (StdHeader);
+
+  //
+  //  Allocate buffer for training data
+  //
+  BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
+  DctCount = EnvPtr->DieStruct.DctCount;
+  BufferPtr += sizeof (DIE_STRUCT);
+  ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
+  BufferPtr += DctCount * sizeof (DCT_STRUCT);
+  RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
+  ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
+
+  SizeOfNewBuffer = sizeof (DIE_STRUCT) +
+                    DctCount * (
+                      sizeof (DCT_STRUCT) + (
+                        ChannelCount * (
+                          sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
+                            RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
+                            (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                          )
+                        )
+                      )
+                    );
+  AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    BufferPtr = AllocHeapParams.BufferPtr;
+    LibAmdMemCopy ( BufferPtr,
+                    &(EnvPtr->DieStruct),
+                    sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
+                    StdHeader
+                  );
+
+    //
+    //  Fix up pointers
+    //
+    MCTPtr = (DIE_STRUCT *) BufferPtr;
+    BufferPtr += sizeof (DIE_STRUCT);
+    MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
+    BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
+    for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+      MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
+      BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
+      for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
+        MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
+        MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
+      }
+    }
+    NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
+    BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
+
+    ReturnData.DataPtr = AllocHeapParams.BufferPtr;
+    ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
+    ReturnData.DataTransferFlags = 0;
+
+    //
+    // Allocate Memory for the MEM_DATA_STRUCT we will use
+    //
+    AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+    AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+      MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
+
+      LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
+
+      //
+      // Copy Parameters from environment
+      //
+      ParameterList.HoleBase = EnvPtr->HoleBase;
+      ParameterList.BottomIo = EnvPtr->BottomIo;
+      ParameterList.UmaSize = EnvPtr->UmaSize;
+      ParameterList.SysLimit = EnvPtr->SysLimit;
+      ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
+      ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
+      MemPtr->ParameterListPtr = &ParameterList;
+
+      for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+        MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
+      }
+
+      MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
+      //
+      // Create Local NBBlock and Tech Block
+      //
+      EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
+      NB.RefPtr = &ParameterList;
+      NB.MemPtr = MemPtr;
+      i = 0;
+      while (memTechInstalled[i] != NULL) {
+        if (memTechInstalled[i] (&TB, &NB)) {
+          break;
+        }
+        i++;
+      }
+      NB.TechPtr = &TB;
+      NB.TechBlockSwitch (&NB);
+
+      //
+      // Setup CPU Mem Type MSRs on the AP
+      //
+      NB.CpuMemTyping (&NB);
+
+      IDS_HDT_CONSOLE ("!Node %d\n", NB.Node);
+      //
+      // Call Technology Specific Training routine
+      //
+      NB.TrainingFlow (&NB);
+      //
+      // Copy training data to ReturnData buffer
+      //
+      LibAmdMemCopy ( BufferPtr,
+                      MCTPtr->DctData[0].ChData[0].RcvEnDlys,
+                      ((DctCount * ChannelCount) * (
+                         (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
+                         (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                        )
+                      ),
+                      StdHeader);
+
+      HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+      //
+      // Restore pointers
+      //
+      for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+        for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
+          MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
+          MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
+
+          MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
+          MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
+        }
+        MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
+      }
+      MCTPtr->DctData = EnvPtr->DieStruct.DctData;
+    }
+
+    //
+    // Signal to BSP that training is complete and Send Results
+    //
+    ASSERT (ReturnData.DataPtr != NULL);
+    ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
+
+    //
+    // Clean up and exit.
+    //
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
+  } else {
+    MCTPtr = &EnvPtr->DieStruct;
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
+  }
+  IDS_HDT_CONSOLE_EXIT (StdHeader);
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
new file mode 100755
index 0000000000..76941ccb3f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mfStandardTraining.c
+ *
+ * This is the standard training routine which performs all training from the BSP
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/PARTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Ids.h"
+#include "mfStandardTraining.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the main function to perform memory training on all nodes from
+ *       the BSP only.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  This feature is enabled.
+ *     @return          FALSE - This feature is not enabled.
+ */
+BOOLEAN
+MemFStandardTraining (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  ASSERT (NBPtr != NULL);
+
+  NBPtr->TrainingFlow (NBPtr);
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
new file mode 100755
index 0000000000..df154fab4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/S3/mfs3.c
@@ -0,0 +1,753 @@
+/**
+ * @file
+ *
+ * mfs3.c
+ *
+ * Main S3 resume memory Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/FEAT/S3)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "heapManager.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the main memory entry point for the S3 resume sequence
+ *      Requirements:
+ *
+ *      Run-Time Requirements:
+ *      1. Complete Hypertransport Bus Configuration
+ *      4. BSP in Big Real Mode
+ *      5. Stack available
+ *
+ *      @param[in]  *StdHeader - Config handle for library and services
+ *
+ *      @return     AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+AmdMemS3Resume (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  //---------------------------------------------
+  //1. Errata Before resume sequence
+  //2. S3 Resume sequence
+  //3. Errata After resume sequence
+  //---------------------------------------------
+  for (Die = 0; Die < DieCount; Die ++) {
+    if (S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die) == 0) {
+      return AGESA_FATAL;
+    }
+    S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die);
+  }
+
+  HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function deallocates heap space allocated in memory S3 resume.
+ *
+ *      @param[in]  *StdHeader - Config handle for library and services
+ *
+ *      @return     AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3Deallocate (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  AGESA_STATUS tempRetVal;
+
+  RetVal = AGESA_SUCCESS;
+  tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
+  if (tempRetVal > RetVal) {
+    RetVal = tempRetVal;
+  }
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the entrance to get device list for memory registers.
+ *
+ *      @param[in, out]  **DeviceBlockHdrPtr - Pointer to the memory containing the
+ *                                             device descriptor list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetDeviceList (
+  IN OUT   DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  UINT16 BufferSize;
+  UINT32 BufferOffset;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  MEM_MAIN_DATA_BLOCK mmData;
+  UINT8 Die;
+  UINT8 DieCount;
+  AGESA_STATUS RetVal;
+  AGESA_BUFFER_PARAMS AllocBufferParams;
+  DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
+  BufferSize = 0;
+
+  LibAmdMemCopy (&AllocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  // Get the mask bit and the register list for node that presents
+  for (Die = 0; Die < DieCount; Die ++) {
+    S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+    S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+    BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
+  }
+
+  // Base on the size of the device list, apply for a buffer for it.
+  AllocBufferParams.BufferLength = BufferSize + sizeof (DEVICE_BLOCK_HEADER);
+  AllocBufferParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE;
+  AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader);
+  if (AgesaAllocateBuffer (0, &AllocBufferParams) != AGESA_SUCCESS) {
+    return AGESA_FATAL;
+  }
+  AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader);
+
+  *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocBufferParams.BufferPointer;
+  (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocBufferParams.BufferLength;
+
+  // Copy device list on the stack to the heap.
+  BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT32) AllocBufferParams.BufferPointer;
+  for (Die = 0; Die < DieCount; Die ++) {
+    for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+      // Copy PCI device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
+      }
+      // Copy conditional PCI device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+      }
+      // Copy MSR device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
+      }
+      // Copy conditional MSR device descriptor to the heap if it exists.
+      if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+        LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+        (*DeviceBlockHdrPtr)->NumDevices ++;
+        BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+      }
+    }
+  }
+
+  return RetVal;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initialize the northbridge block and apply for heap space
+ *      before any function call is made to memory component during S3 resume.
+ *
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3ResumeInitNB (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  MEM_MAIN_DATA_BLOCK mmData;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  MEM_DATA_STRUCT *MemData;
+  UINT8 Die;
+  UINT8 DieCount;
+  UINT8 SpecialCaseHeapSize;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED];
+
+  SpecialCaseHeapSize = 0;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
+  if (RetVal == AGESA_FATAL) {
+    return RetVal;
+  }
+  DieCount = mmData.DieCount;
+
+  //--------------------------------------------------
+  //  Apply for heap space for special case registers
+  //--------------------------------------------------
+  for (Die = 0; Die < DieCount; Die ++) {
+    // Construct the header for the special case heap.
+    SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node;
+    SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER)));
+    SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize;
+  }
+  AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize;
+  AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr);
+    ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER"
+    return AGESA_FATAL;
+  }
+  LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the PCI device register list according to the register
+ *      list ID.
+ *
+ *      @param[in]       *Device - pointer to the PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetPCI
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetPCI
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AmdMemS3NBHandle" in heap for S3GetPCI
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the conditional PCI device register list according
+ *      to the register list ID.
+ *
+ *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetCPCI
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetCPCI
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AmdMemS3NBHandle" in heap for S3GetCPCI
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the MSR device register list according to the register
+ *      list ID.
+ *
+ *      @param[in]       *Device - pointer to the MSR_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetMsr
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetMsr
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the conditional MSR device register list according
+ *      to the register list ID.
+ *
+ *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
+ *      @param[out]      **RegisterHdr - pointer to the address of the register list
+ *      @param[in]       *StdHeader - Config handle for library and services
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemFS3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                     *StdHeader
+  )
+{
+  AGESA_STATUS RetVal;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  VOID *RegisterHeader;
+  LOCATE_HEAP_PTR LocHeap;
+  AGESA_BUFFER_PARAMS LocBufferParams;
+
+  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  switch (StdHeader->HeapStatus) {
+  case HEAP_LOCAL_CACHE:
+    if (HeapLocateBuffer (&LocHeap, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_LOCAL_CACHE, but could not locate "AmdMemS3NBHandle" in heap for S3GetCMsr
+      return AGESA_FATAL;
+    }
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    break;
+  case HEAP_SYSTEM_MEM:
+    AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader);
+    if (AgesaLocateBuffer (0, &LocBufferParams) != AGESA_SUCCESS) {
+      ASSERT(FALSE) ; // HeapStatus = HEAP_SYSTEM_MEM, but could not locate "AmdMemS3NBHandle" in heap for S3GetCMsr
+      return AGESA_FATAL;
+    }
+    AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader);
+    S3NBPtr = (S3_MEM_NB_BLOCK *)LocBufferParams.BufferPointer;
+    break;
+  default:
+    ASSERT(FALSE) ; // No match for heap status, but could not locate "AmdMemS3NBHandle" in heap for S3GetCMsr
+    return AGESA_FATAL;
+  }
+  // NB block has already been constructed by main block.
+  // No need to construct it here.
+  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
+  *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
+  return RetVal;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initialize needed data structures for S3 resume.
+ *
+ *      @param[in, out]  **S3NBPtr - Pointer to the pointer of northbridge block.
+ *      @param[in, out]  *MemPtr - Pointer to MEM_DATA_STRUCT.
+ *      @param[in, out]  *mmData - Pointer to MEM_MAIN_DATA_BLOCK.
+ *      @param[in]       *StdHeader - Config handle for library and services.
+ *
+ *      @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemS3InitNB (
+  IN OUT   S3_MEM_NB_BLOCK **S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT **MemPtr,
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  AGESA_STATUS RetVal;
+  LOCATE_HEAP_PTR LocHeap;
+  MEM_NB_BLOCK *NBPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 Die;
+  UINT8 DieCount;
+  BOOLEAN SkipScan;
+
+  SkipScan = FALSE;
+  LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr;
+    SkipScan = TRUE;
+  } else {
+    AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
+    AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT
+      return AGESA_FATAL;
+    }
+    *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
+  }
+  LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+  mmData->MemPtr = *MemPtr;
+
+  if (!SkipScan) {
+    RetVal = MemSocketScan (mmData);
+    if (RetVal == AGESA_FATAL) {
+      return RetVal;
+    }
+  } else {
+    // We already have initialize data block, no need to do it again.
+    mmData->DieCount = mmData->MemPtr->DieCount;
+  }
+  DieCount = mmData->DieCount;
+
+  //---------------------------------------------
+  //  Creation of NB Block for S3 resume
+  //---------------------------------------------
+  // Search for AMD_MEM_AUTO_HANDLE on the heap first.
+  // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
+  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+    // NB block has already been constructed by main block.
+    // No need to construct it here.
+    *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
+  } else {
+    AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK)));
+    AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+    AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+    if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+      ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK"
+      return AGESA_FATAL;
+    }
+    *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+
+    LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+    if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+      // NB block has already been constructed by main block.
+      // No need to construct it here.
+      NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    } else {
+      AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
+      AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+      AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+      if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
+        ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK"
+        return AGESA_FATAL;
+      }
+      NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+    }
+    // Construct each die.
+    for (Die = 0; Die < DieCount; Die ++) {
+      i = 0;
+      ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die];
+      while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) {
+        if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) {
+          break;
+        }
+        i++;
+      };
+      if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
+        ASSERT(FALSE); // S3 resume NB constructor not found
+        return AGESA_FATAL;
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of 10ns cycles
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Count - Number of 10ns cycles to wait
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemFS3Wait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  Count *= 16;
+  Count += SMsr.lo;
+  if (Count >= SMsr.lo) {
+    while (SMsr.lo < Count) {
+      LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+  } else {
+    while ((INT32) (SMsr.lo) < (INT32)Count) {
+      LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
new file mode 100755
index 0000000000..ef1326aacc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Feat/TABLE/mftds.c
@@ -0,0 +1,319 @@
+/**
+ * @file
+ *
+ * mftds.c
+ *
+ * Northbridge table drive support file for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/TABLE)
+ * @e \$Revision: 5674 $ @e \$Date: 2008-04-05 02:22:37 +0800 (Sat, 05 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mftds.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MAX_BYTELANES_PER_CHANNEL   (8 + 1)  ///< Max Bytelanes per channel
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+SetTableValues (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS MTPtr
+  );
+
+VOID
+SetTableValuesLoop (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS *MTPtr,
+  IN       UINT8     time
+  );
+
+/*-----------------------------------------------------------------------------
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_TABLE_ALIAS structure
+ *     @param[in]       time     - Indicate the timing for the register which is written.
+ *
+ *     @return          None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemFInitTableDrive (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8     time
+  )
+{
+  MEM_TABLE_ALIAS *MTPtr;
+  MEM_TABLE_ALIAS *IdsMTPtr;
+
+  ASSERT (NBPtr != NULL);
+  IdsMTPtr = NULL;
+
+  MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations;
+
+  IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) {
+    IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader));
+    IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader));
+  }
+
+  SetTableValuesLoop (NBPtr, MTPtr, time);
+  SetTableValuesLoop (NBPtr, IdsMTPtr, time);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MTPtr   - Pointer to the MEM_TABLE_ALIAS structure
+ *     @param[in]       time     - Indicate the timing for the register which is written.
+ *
+ *     @return          None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+SetTableValuesLoop (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS *MTPtr,
+  IN       UINT8     time
+  )
+{
+  UINT8 i;
+  UINT8 CurDct;
+
+  if (MTPtr != NULL) {
+    CurDct = NBPtr->Dct;
+    for (i = 0; MTPtr[i].time != MTEnd; i++) {
+      if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) {
+        SetTableValues (NBPtr, MTPtr[i]);
+      }
+    }
+    NBPtr->SwitchDCT (NBPtr, CurDct);
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *   Engine for setting Table Value.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       MTPtr    - Pointer to the MEM_TABLE_ALIAS structure
+ *
+ *     @return      None
+ * ----------------------------------------------------------------------------
+ */
+VOID
+SetTableValues (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_TABLE_ALIAS MTPtr
+  )
+{
+  UINT8 AccessType;
+  UINT16 ByteLane;
+  UINT8 Dct;
+  UINT8 i;
+  UINT8 j;
+  UINT32 TempVal[36];
+  UINT8 *DqsSavePtr;
+  UINT8  DqsOffset;
+  BOOLEAN SaveDqs;
+
+  AccessType = 0;
+  DqsSavePtr = NULL;
+  SaveDqs = TRUE;
+
+  ASSERT (MTPtr.time <= MTAfterMaxRdLatTrn);
+  ASSERT (MTPtr.attr <= MTAdd);
+  ASSERT (MTPtr.node <= MTNodes);
+  ASSERT (MTPtr.dct <= MTDcts);
+  ASSERT (MTPtr.dimm <= MTDIMMs);
+  ASSERT (MTPtr.data.s.bytelane <= MTBLs);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      switch (MTPtr.bfindex) {
+      case BFRcvEnDly:
+        AccessType = AccessRcvEnDly;
+        DqsSavePtr = NULL;
+        break;
+      case BFWrDatDly:
+        AccessType = AccessWrDatDly;
+        DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys;
+        break;
+      case BFRdDqsDly:
+        AccessType = AccessRdDqsDly;
+        DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys;
+        break;
+      case BFWrDqsDly:
+        AccessType = AccessWrDqsDly;
+        DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys;
+        break;
+      case BFPhRecDly:
+        AccessType = AccessPhRecDly;
+        SaveDqs = FALSE;
+        break;
+      default:
+        AccessType = 0xFF;
+        break;
+      }
+      if (AccessType == 0xFF) {
+        if (MTPtr.attr == MTOverride) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTSubtract) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value);
+        }
+        if (MTPtr.attr == MTAdd) {
+          NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value);
+        }
+      } else {
+        // Store the DQS data first
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+          for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+            TempVal[i * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j));
+          }
+        }
+        //
+        // Single Value with Bytleane mask option
+        //   Indicated by the vtype flag
+        //
+        if (MTPtr.vtype == VT_MSK_VALUE) {
+          // set the value which defined in Memory table.
+          ByteLane = MTPtr.data.s.bytelane;
+          for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+            if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) {
+              for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j);
+                if ((ByteLane & (UINT16)1) != 0) {
+                  if (MTPtr.attr == MTOverride) {
+                    TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value;
+                  }
+                  if (MTPtr.attr == MTSubtract) {
+                    TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value;
+                  }
+                  if (MTPtr.attr == MTAdd) {
+                    TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value;
+                  }
+                  NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]);
+                  if (SaveDqs) {
+                    if (DqsSavePtr == NULL) {
+                      NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
+                    } else {
+                      DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
+                    }
+                  }
+                }
+                ByteLane = ByteLane >> (UINT16)1;
+              }
+            }
+          }
+        } else {
+          // Multiple values specified in a byte array
+          for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+            if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) {
+              for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+                DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j);
+                if (MTPtr.attr == MTOverride) {
+                  TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j];
+                }
+                if (MTPtr.attr == MTSubtract) {
+                  TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j];
+                }
+                if (MTPtr.attr == MTAdd) {
+                  TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j];
+                }
+                NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]);
+                if (SaveDqs) {
+                  if (DqsSavePtr == NULL) {
+                    NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
+                  } else {
+                    DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
+                  }
+                }
+              }
+            }
+          }
+        }
+        // set the DQS value to left DIMMs.
+        i = MTPtr.dimm;
+        while ((i != MTDIMMs) && ((++i) < MAX_DIMMS_PER_CHANNEL)) {
+          for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
+            NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[i * MAX_BYTELANES_PER_CHANNEL + j]);
+          }
+        }
+      }
+    }
+  }
+}
+
+
+
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c
new file mode 100755
index 0000000000..3ad02f3557
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/C32/mmflowC32.c
@@ -0,0 +1,342 @@
+/**
+ * @file
+ *
+ * mmflowC32.c
+ *
+ * Main Memory initialization sequence for C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main/C32)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE
+/* features */
+#include "mftds.h"
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function defines the memory initialization flow for
+ *      systems that only support C32 processors.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemMFlowC32 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  TechPtr = MemMainPtr->TechPtr;
+  NodeCnt = MemMainPtr->DieCount;
+
+
+  //----------------------------------------------------------------
+  // Initialize MCT
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Low voltage DDR3
+  //----------------------------------------------------------------
+  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
+  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Initialize DRAM and DCTs, and Create Memory Map
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    // Initialize Memory Controller and Dram
+    IDS_HDT_CONSOLE ("!Node %d\n", Node);
+    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
+      return AGESA_FATAL; //fatalexit
+    }
+
+    // Create memory map
+    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
+    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------
+  // If there is no dimm on the system, do fatal exit
+  //----------------------------------------------------
+  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
+    ASSERT (FALSE);
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Synchronize DCTs
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // CpuMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Before Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Restore
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemRestore (MemMainPtr)) {
+    // Do DQS training only if memory context restore fails
+
+    //----------------------------------------------------------------
+    // Training
+    //----------------------------------------------------------------
+    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
+    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
+    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
+      if (!MemFeatMain.Training (MemMainPtr)) {
+        return AGESA_FATAL;
+      }
+    }
+    IDS_HDT_CONSOLE ("\nEnd DQS training\n\n");
+  }
+
+  //----------------------------------------------------------------
+  // Disable chipselects that fail training
+  //----------------------------------------------------------------
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
+  MemFeatMain.ExcludeDIMM (MemMainPtr);
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
+
+  //----------------------------------------------------------------
+  // OtherTiming
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // After Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
+  }
+
+  //----------------------------------------------------------------
+  // SetDqsEccTimings
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Online Spare
+  //----------------------------------------------------------------
+  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave banks
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Interleave Nodes
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave channels
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // UMA Allocation & UMAMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  // ECC
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InitEcc (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Memory Clear
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.MemClr (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // OnDimm Thermal
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Finalize MCT
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Save
+  //----------------------------------------------------------------
+  MemFeatMain.MemSave (MemMainPtr);
+
+  //----------------------------------------------------------------
+  // Memory DMI support
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemDmi (MemMainPtr)) {
+    return AGESA_CRITICAL;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c
new file mode 100755
index 0000000000..c22592cc8a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DA/mmflowda.c
@@ -0,0 +1,347 @@
+/**
+ * @file
+ *
+ * mmflowda.c
+ *
+ * Main Memory initialization sequence for DA
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main/DA)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE
+/* features */
+#include "mftds.h"
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function defines the memory initialization flow for
+ *      systems that only support RB processors.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemMFlowDA (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  TechPtr = MemMainPtr->TechPtr;
+  NodeCnt = MemMainPtr->DieCount;
+
+  //----------------------------------------------------------------
+  // Initialize MCT
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Low voltage DDR3
+  //----------------------------------------------------------------
+  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
+  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Initialize DRAM and DCTs, and Create Memory Map
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    // Initialize Memory Controller and Dram
+    IDS_HDT_CONSOLE ("!Node %d\n", Node);
+
+    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
+      return AGESA_FATAL; // fatalexit
+    }
+
+    // Create memory map
+    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
+    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------
+  // If there is no dimm on the system, do fatal exit
+  //----------------------------------------------------
+  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
+    ASSERT (FALSE);
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Synchronize DCTs
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // CpuMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Before Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Restore
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemRestore (MemMainPtr)) {
+    // Do DQS training only if memory context restore fails
+
+    //----------------------------------------------------------------
+    // Training
+    //----------------------------------------------------------------
+    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
+    IDS_OPTION_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader));
+    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
+    if (!MemFeatMain.Training (MemMainPtr)) {
+      return AGESA_FATAL;
+    }
+    IDS_HDT_CONSOLE ("\nEnd DQS training\n\n");
+  }
+
+  //----------------------------------------------------------------
+  // Disable chipselects that fail training
+  //----------------------------------------------------------------
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
+  MemFeatMain.ExcludeDIMM (MemMainPtr);
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
+
+  //----------------------------------------------------------------
+  // OtherTiming
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // After Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
+  }
+
+  //----------------------------------------------------------------
+  // SetDqsEccTimings
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Online Spare
+  //----------------------------------------------------------------
+  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave banks
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Interleave Nodes
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave channels
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // UMA Allocation & UMAMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave region
+  //----------------------------------------------------------------
+  NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
+
+  //----------------------------------------------------------------
+  // ECC
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InitEcc (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Memory Clear
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.MemClr (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // OnDimm Thermal
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Finalize MCT
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Save
+  //----------------------------------------------------------------
+  MemFeatMain.MemSave (MemMainPtr);
+
+  //----------------------------------------------------------------
+  // Memory DMI support
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemDmi (MemMainPtr)) {
+    return AGESA_CRITICAL;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c
new file mode 100755
index 0000000000..308ff90ba7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/DR/mmflowdr.c
@@ -0,0 +1,343 @@
+/**
+ * @file
+ *
+ * mmflowdr.c
+ *
+ * Main Memory initialization sequence for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main/DR)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE
+/* features */
+#include "mftds.h"
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function defines the memory initialization flow for
+ *      systems that only support RB processors.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemMFlowDr (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  TechPtr = MemMainPtr->TechPtr;
+  NodeCnt = MemMainPtr->DieCount;
+
+
+  //----------------------------------------------------------------
+  // Initialize MCT
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Low voltage DDR3
+  //----------------------------------------------------------------
+  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
+  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Initialize DRAM and DCTs, and Create Memory Map
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    // Initialize Memory Controller and Dram
+    IDS_HDT_CONSOLE ("!Node %d\n", Node);
+
+    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
+      return AGESA_FATAL; //fatalexit
+    }
+
+    // Create memory map
+    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
+    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------
+  // If there is no dimm on the system, do fatal exit
+  //----------------------------------------------------
+  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
+    ASSERT (FALSE);
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Synchronize DCTs
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // CpuMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Before Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Restore
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemRestore (MemMainPtr)) {
+    // Do DQS training only if memory context restore fails
+
+    //----------------------------------------------------------------
+    // Training
+    //----------------------------------------------------------------
+    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
+    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
+    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
+      if (!MemFeatMain.Training (MemMainPtr)) {
+        return AGESA_FATAL;
+      }
+    }
+    IDS_HDT_CONSOLE ("\nEnd DQS training\n\n");
+  }
+
+  //----------------------------------------------------------------
+  // Disable chipselects that fail training
+  //----------------------------------------------------------------
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
+  MemFeatMain.ExcludeDIMM (MemMainPtr);
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
+
+  //----------------------------------------------------------------
+  // OtherTiming
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // After Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
+  }
+
+  //----------------------------------------------------------------
+  // SetDqsEccTimings
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Online Spare
+  //----------------------------------------------------------------
+  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave banks
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Interleave Nodes
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave channels
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // UMA Allocation & UMAMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  // ECC
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InitEcc (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Memory Clear
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.MemClr (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // OnDimm Thermal
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Finalize MCT
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Save
+  //----------------------------------------------------------------
+  MemFeatMain.MemSave (MemMainPtr);
+
+  //----------------------------------------------------------------
+  // Memory DMI support
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemDmi (MemMainPtr)) {
+    return AGESA_CRITICAL;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c
new file mode 100755
index 0000000000..b49b2f38e3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/HY/mmflowhy.c
@@ -0,0 +1,347 @@
+/**
+ * @file
+ *
+ * mmflowhy.c
+ *
+ * Main Memory initialization sequence for HY
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main/HY)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE
+/* features */
+#include "mftds.h"
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+MemMFlowHy (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function defines the memory initialization flow for
+ *      systems that only support HY processors.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemMFlowHy (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  TechPtr = MemMainPtr->TechPtr;
+  NodeCnt = MemMainPtr->DieCount;
+
+  //----------------------------------------------------------------
+  // Initialize MCT
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Low voltage DDR3
+  //----------------------------------------------------------------
+  // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
+  AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Initialize DRAM and DCTs, and Create Memory Map
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    // Initialize Memory Controller and Dram
+    IDS_HDT_CONSOLE ("!Node %d\n", Node);
+    printk(BIOS_DEBUG, "Node: %x\n", Node);
+    if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
+      return AGESA_FATAL; //fatalexit
+    }
+
+    // Create memory map
+    AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
+    if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------
+  // If there is no dimm on the system, do fatal exit
+  //----------------------------------------------------
+  if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
+    ASSERT (FALSE);
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Synchronize DCTs
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // CpuMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
+  if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Before Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Restore
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemRestore (MemMainPtr)) {
+    // Do DQS training only if memory context restore fails
+
+    //----------------------------------------------------------------
+    // Training
+    //----------------------------------------------------------------
+    MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
+    AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
+    IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
+      if (!MemFeatMain.Training (MemMainPtr)) {
+        return AGESA_FATAL;
+      }
+    }
+    IDS_HDT_CONSOLE ("\nEnd DQS training\n\n");
+  }
+
+  //----------------------------------------------------------------
+  // Disable chipselects that fail training
+  //----------------------------------------------------------------
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
+  MemFeatMain.ExcludeDIMM (MemMainPtr);
+  MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
+
+  //----------------------------------------------------------------
+  // OtherTiming
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // After Training Table values
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
+  }
+
+  //----------------------------------------------------------------
+  // SetDqsEccTimings
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Online Spare
+  //----------------------------------------------------------------
+  if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave banks
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Interleave Nodes
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Interleave channels
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // UMA Allocation & UMAMemTyping
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  // ECC
+  //----------------------------------------------------------------
+  if (!MemFeatMain.InitEcc (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // Memory Clear
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
+  if (!MemFeatMain.MemClr (MemMainPtr)) {
+    return AGESA_FATAL;
+  }
+
+  //----------------------------------------------------------------
+  // OnDimm Thermal
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
+      if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
+        return AGESA_FATAL;
+      }
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Finalize MCT
+  //----------------------------------------------------------------
+  for (Node = 0; Node < NodeCnt; Node++) {
+    if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
+      return AGESA_FATAL;
+    }
+  }
+
+  //----------------------------------------------------------------
+  // Memory Context Save
+  //----------------------------------------------------------------
+  MemFeatMain.MemSave (MemMainPtr);
+
+  //----------------------------------------------------------------
+  // Memory DMI support
+  //----------------------------------------------------------------
+  if (!MemFeatMain.MemDmi (MemMainPtr)) {
+    return AGESA_CRITICAL;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c
new file mode 100755
index 0000000000..a407451827
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mdef.c
@@ -0,0 +1,90 @@
+/**
+ * @file
+ *
+ * mdef.c
+ *
+ * Memory Controller header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is the default return function
+ */
+
+VOID
+memDefRet (VOID)
+{
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
new file mode 100755
index 0000000000..5627b92a93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/merrhdl.c
@@ -0,0 +1,186 @@
+/**
+ * @file
+ *
+ * merrhdl.c
+ *
+ * Memory error handling
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "heapManager.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function handle errors occur in memory code.
+ *
+ *
+ *     @param[in,out]   *MCTPtr - pointer to DIE_STRUCT.
+ *     @param[in,out]   DCT - DCT that needs to be handled.
+ *     @param[in,out]   ChipSelMask - Chip select mask that needs to be handled
+ *     @param[in,out]   *StdHeader - pointer to AMD_CONFIG_PARAMS
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemErrHandle (
+  IN       DIE_STRUCT *MCTPtr,
+  IN       UINT8  DCT,
+  IN       UINT16  ChipSelMask,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN ErrorRecovery;
+  BOOLEAN IgnoreErr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 CurrentDCT;
+  LOCATE_HEAP_PTR LocHeap;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_MAIN_DATA_BLOCK mmData;
+
+  DCTPtr = MCTPtr->DctData;
+  ErrorRecovery = TRUE;
+  IgnoreErr = FALSE;
+  IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader);
+
+  if (ErrorRecovery) {
+    if (DCT == EXCLUDE_ALL_DCT) {
+      // Exclude all DCTs on a node
+      for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) {
+        DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent;
+      }
+    } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) {
+      // Exclude the specified DCT
+      DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent;
+    } else {
+      // Exclude the chip select that has been marked out
+      DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent;
+      IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader);
+    }
+
+    // Exclude the failed dimm to recovery from error
+    if (MCTPtr->NodeMemSize != 0) {
+      LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
+      if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+        // NB block has already been constructed by main block.
+        // No need to construct it here.
+        NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+        if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) {
+          // Memory map has not been calculated, no need to remap memory across node here.
+          // Only need to remap memory within the node.
+          NBPtr = &NBPtr[MCTPtr->NodeId];
+          NBPtr->FeatPtr->ExcludeDIMM (NBPtr);
+        } else {
+          // Need to remap memory across the whole system.
+          mmData.MemPtr = NBPtr->MemPtr;
+          mmData.mmSharedPtr = NBPtr->SharedPtr;
+          mmData.NBPtr = NBPtr;
+          mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]);
+          mmData.DieCount = NBPtr->MemPtr->DieCount;
+          if (!MemFeatMain.ExcludeDIMM (&mmData)) {
+            return FALSE;
+          }
+        }
+      }
+      // If allocation fails, that means the code is not running at BSP.
+      // Parallel training is in process.
+      // Remap for parallel training will be done when control returns to BSP.
+    }
+    return TRUE;
+  } else {
+    IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader);
+    if (IgnoreErr) {
+      return TRUE;
+    }
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // ErrorRecovery is FALSE
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c
new file mode 100755
index 0000000000..45f04d59e5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/minit.c
@@ -0,0 +1,134 @@
+/**
+ * @file
+ *
+ * minit.c
+ *
+ * Initializer support function
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6529 $ @e \$Date: 2008-06-25 04:19:02 -0500 (Wed, 25 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "Ids.h"
+#include "merrhdl.h"
+#include "AdvancedApi.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function initializes the default parameter, function pointers, build options
+ *   and SPD data for memory configuration
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   *PlatFormConfig -  Platform profile/build option config structure
+ *
+ */
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   PLATFORM_CONFIGURATION   *PlatFormConfig
+  )
+{
+  UINT8 p;
+  UINT8 i;
+  // We need a way of specifying default values for each particular northbridge
+  // family.  We also need to make sure that the IBV knows which parameter struct
+  // is for which northbridge.
+  //----------------------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader);
+
+  MemPtr->PlatFormConfig = PlatFormConfig;
+
+  memNBInstalled[0].MemNInitDefaults (MemPtr);
+
+  //----------------------------------------------------------------------------
+  // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT
+  //----------------------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader);
+  i = 0;
+  for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+    if (memPlatformTypeInstalled[i] != NULL) {
+      MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i];
+      i++;
+    } else {
+      MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef;
+    }
+  }
+  AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader);
+  MemPtr->ErrorHandling = MemErrHandle;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c
new file mode 100755
index 0000000000..00a07cd61b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mm.c
@@ -0,0 +1,238 @@
+/**
+ * @file
+ *
+ * mm.c
+ *
+ * Main Memory Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MM_FILECODE
+/* features */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function deallocates heap buffers that were allocated in AmdMemAuto
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+MemAmdFinalize (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Die;
+
+  IDS_HDT_CONSOLE_EXIT (&MemPtr->StdHeader);
+
+  for (Die = 0; Die < MemPtr->DieCount; Die++ ) {
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader);
+    HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader);
+  }
+
+  HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader);
+  HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader);
+  HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader);
+  HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ * MemSocketScan - Scan all nodes, recording the physical Socket number,
+ * Die Number (relative to the socket), and PCI Device address of each
+ * populated socket.
+ *
+ * This information is used by the northbridge block to map a dram
+ * channel on a particular DCT, on a particular CPU Die, in a particular
+ * socket to a the DRAM SPD Data for the DIMMS physically connected to
+ * that channel.
+ *
+ * Also, the customer socket map is populated with pointers to the
+ * appropriate channel structures, so that the customer can locate the
+ * appropriate channel configuration data.
+ *
+ * This socket scan will always result in Die 0 as the BSP.
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+AGESA_STATUS
+MemSocketScan (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  UINT8 DieIndex;
+  UINT8 DieCount;
+  UINT32 SocketId;
+  UINT32 DieId;
+  UINT8 Die;
+  PCI_ADDR Address;
+  AGESA_STATUS AgesaStatus;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  ASSERT (mmPtr != NULL);
+  ASSERT (mmPtr->MemPtr != NULL);
+  MemPtr = mmPtr->MemPtr;
+
+  //
+  //  Count the number of dies in the system
+  //
+  DieCount = 0;
+  for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {
+    if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {
+      DieCount++;
+    }
+  }
+  MemPtr->DieCount = DieCount;
+  mmPtr->DieCount = DieCount;
+
+  if (DieCount > 0) {
+    //
+    //  Allocate buffer for DIE_STRUCTs
+    //
+    AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT));
+    AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+      MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;
+      //
+      //  Find SocketId, DieId, and PCI address of each node
+      //
+      DieIndex = 0;
+      for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {
+        if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {
+          if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) {
+            MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId;
+            MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId;
+            MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue;
+
+            DieIndex++;
+          }
+        }
+      }
+      AgesaStatus = AGESA_SUCCESS;
+    } else {
+      ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs
+      AgesaStatus = AGESA_FATAL;
+    }
+  } else {
+    ASSERT(FALSE); // No die in the system
+    AgesaStatus = AGESA_FATAL;
+  }
+
+  return AgesaStatus;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function sets memory errors into MemDataStruct
+ *
+ *
+ *     @param[in,out]   *MCTPtr  - Pointer to the DIE_STRUCT
+ *     @param[in]       Errorval - Error value to update
+ */
+
+VOID
+SetMemError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  )
+{
+  if (MCTPtr->ErrCode < Errorval) {
+    MCTPtr->ErrCode = Errorval;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c
new file mode 100755
index 0000000000..0980c3c1c1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmConditionalPso.c
@@ -0,0 +1,693 @@
+/**
+ * @file
+ *
+ * mmConditionalPso.c
+ *
+ * Functions to support conditional entries in the Platform Specific Override Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 20102 $ @e \$Date: 2009-10-06 14:50:57 -0500 (Tue, 06 Oct 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define PSO_TYPE    0
+#define PSO_LENGTH  1
+#define PSO_DATA    2
+
+typedef enum _PSO_STATE {
+  PSO_FIND_CONDITION = 100,  // Searching for initial Condition statement
+  PSO_FIND_ACTION,           // Searching for initial Action Statement
+  PSO_MATCH_ACTION,          // Trying to find an action that matches the caller's request
+  PSO_CHECK_CONDITION,       // Checking the condition that preceded the found action
+  PSO_DO_ACTION,             // Performing Action
+  PSO_COMPLETE               // Completed processing of this request
+} PSO_STATE;
+
+typedef struct _D3_CMP_CAL {
+  UINT32 D3Cmp0NCal   :3;
+  UINT32 Reserved34   :2;
+  UINT32 D3Cmp0PCal   :3;
+  UINT32 Reserved89   :2;
+  UINT32 D3Cmp1NCal   :3;
+  UINT32 Reserved1314 :2;
+  UINT32 D3Cmp1PCal   :3;
+  UINT32 Reserved1819 :2;
+  UINT32 D3Cmp2NCal   :3;
+  UINT32 Reserved2324 :2;
+  UINT32 D3Cmp2PCal   :3;
+  UINT32 Reserved2831 :2;
+} D3_CMP_CAL;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+ STATIC
+ MemPSODoActionODT (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+ BOOLEAN
+ STATIC
+ MemPSODoActionAddrTmg (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+ BOOLEAN
+ STATIC
+ MemPSODoActionODCControl (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+ BOOLEAN
+ STATIC
+ MemPSODoActionSlewRate (
+   IN OUT   MEM_NB_BLOCK *NBPtr,
+   IN       UINT8 *Buffer
+   );
+
+BOOLEAN
+STATIC
+MemPSODoActionGetFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  );
+
+BOOLEAN
+STATIC
+MemCheckRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel,
+  IN       UINT16 RankType
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Process Conditional Platform Specific Overrides
+ *
+ *      @param[in] PlatformMemoryConfiguration - Pointer to Platform config table
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] PsoAction - Action type
+ *      @param[in] Dimm - Dimm Number
+ *
+ *      @return          BOOLEAN -            TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemProcessConditionalOverrides (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 PsoAction,
+  IN       UINT8 Dimm
+  )
+{
+  BOOLEAN Result;
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 *Buffer;
+  UINT8 *ConditionStartPtr;
+  UINT8 *ActionStartPtr;
+  UINT8 *SpdBufferPtr;
+  UINT8 i;
+  UINT8 DimmMask;
+  UINT8 CurDimmMask;
+  BOOLEAN Condition;
+  BOOLEAN TmpCond;
+  PSO_STATE State;
+  ASSERT (PlatformMemoryConfiguration != NULL);
+  ASSERT (NBPtr != NULL);
+  ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX));
+  IDS_HDT_CONSOLE ("    Checking for Conditional Overrides.\n");
+  //
+  // Set up local data
+  //
+  TechPtr = NBPtr->TechPtr;
+  Buffer = PlatformMemoryConfiguration;
+  State = PSO_FIND_CONDITION;
+  ConditionStartPtr = NULL;
+  ActionStartPtr = NULL;
+  Condition = FALSE;
+  DimmMask = 0xFF;
+  CurDimmMask = 0xFF;
+  Result = FALSE;
+
+  if (Dimm != 0xFF) {
+    DimmMask = ( 1 << Dimm);
+  }
+  DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF);
+  if (DimmMask == 0) {
+    return Result;
+  }
+
+  //
+  // Search for Condition Entry
+  //
+  while (State != PSO_COMPLETE) {
+    switch (State) {
+    //
+    // Searching for initial Condition statement
+    //
+    case PSO_FIND_CONDITION:
+      ASSERT (Buffer != NULL);
+      while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) {
+        //
+        // If end of table is reached, Change state to complete and break.
+        //
+        if (Buffer[PSO_TYPE] == PSO_END) {
+          State = PSO_COMPLETE;
+          break;
+        }
+        //
+        // Otherwise, increment Buffer Pointer to the next PSO entry.
+        //
+        Buffer += (Buffer[PSO_LENGTH] + 2);
+      }
+      //
+      // If Condition statement has been found, save the Condition Start Pointer,
+      //  and change to next state
+      //
+      if (State != PSO_COMPLETE) {
+        ASSERT (Buffer != NULL);
+        State = PSO_FIND_ACTION;
+        ConditionStartPtr = Buffer;
+        Buffer += (Buffer[PSO_LENGTH] + 2);
+      }
+      break;
+    //
+    // Searching for an action that matches the caller's request
+    //
+    case PSO_FIND_ACTION:
+      ASSERT (Buffer != NULL);
+      while (Buffer[PSO_TYPE] != PsoAction) {
+        //
+        // If non-conditional entry, change state to complete and break.
+        //
+        if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) {
+          State = PSO_COMPLETE;
+          break;
+        }
+        //
+        // Check for the Start of a new condition block
+        //
+        if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) {
+          ConditionStartPtr = Buffer;
+        }
+        //
+        // Otherwise, increment buffer pointer to the next PSO entry.
+        //
+        Buffer += (Buffer[PSO_LENGTH] + 2);
+      }
+      //
+      // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start
+      //  and Change to next state.
+      //
+      if (State != PSO_COMPLETE) {
+        State = PSO_CHECK_CONDITION;
+        ASSERT (Buffer != NULL);
+        ActionStartPtr = Buffer;
+        Buffer = ConditionStartPtr;
+        Condition = TRUE;
+      }
+      break;
+    //
+    // Checking the condition that preceded the found action
+    //
+    case PSO_CHECK_CONDITION:
+      ASSERT (Buffer != NULL);
+      //
+      // Point to the next Condition
+      //
+      Buffer += (Buffer[PSO_LENGTH] + 2);
+      ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX));
+      //
+      // This section has already been checked for invalid statements so just exit on ACTION_xx
+      //
+      if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) {
+        if (Condition) {
+          ASSERT (Buffer != NULL);
+          State = PSO_DO_ACTION;              // Perform the Action
+        } else {
+          State = PSO_FIND_CONDITION;         // Go back and look for another condition/action
+        }
+        Buffer = ActionStartPtr;              // Restore Action Pointer
+        break;
+      }
+      switch (Buffer[PSO_TYPE]) {
+
+      case PSO_CONDITION_AND:
+        //
+        // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE
+        //  just restore action pointer and perform the action.
+        //
+        if (Condition) {
+          State = PSO_DO_ACTION;
+          Buffer = ActionStartPtr;
+        } else {
+          //
+          // If its false, Start over and evaluate next cond.
+          // reset the Current Dimm Mask
+          //
+          Condition = TRUE;
+          CurDimmMask = 0xFF;
+        }
+        break;
+
+      case PSO_CONDITION_LOC:
+        //
+        // Condition location
+        //
+        CurDimmMask = Buffer[4];
+        Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) &&
+                       ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) &&
+                       ((CurDimmMask & DimmMask) != 0) );
+        break;
+
+      case PSO_CONDITION_SPD:
+        //
+        // Condition SPD
+        //
+        TmpCond = FALSE;
+        for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+          if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) {
+            if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) {
+              TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]);
+            }
+          }
+        }
+        Condition &= TmpCond;
+        break;
+
+      case PSO_CONDITION_REG:
+        //
+        // Condition Register - unsupported at this time
+        //
+        break;
+
+      default:
+        ASSERT (FALSE);
+    } // End Condition Switch
+    break;
+
+    case PSO_DO_ACTION:
+      ASSERT (Buffer != NULL);
+      //
+      // Performing Action
+      //
+      if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) {
+        State = PSO_COMPLETE;
+      }
+      if (Buffer[PSO_TYPE] == PsoAction) {
+        switch (Buffer[PSO_TYPE]) {
+        case PSO_ACTION_ODT:
+          Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_ADDRTMG:
+          Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_ODCCONTROL:
+          Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_SLEWRATE:
+          Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_SPEEDLIMIT:
+          Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]);
+          break;
+        case PSO_ACTION_REG:
+          break;
+        default:
+          ASSERT (FALSE);
+        } // End Action Switch
+        //
+        // If Action was performed, mark complete.
+        //
+        if (Result) {
+          State = PSO_COMPLETE;
+        }
+    }// End Action
+
+      //
+      // Point to the next PSO Entry
+      //
+      Buffer += (Buffer[PSO_LENGTH] + 2);
+      break;
+
+    case PSO_COMPLETE:
+      //
+      // Completed processing of this request
+      //
+      break;
+
+    default:
+      ASSERT (FALSE);
+    } // End State Switch
+
+  } // End While
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *      Perform ODT Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return         BOOLEAN -             TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionODT (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  UINT32 Speed;
+  UINT8 Dimms;
+  UINT8 i;
+  UINT8 QR_Dimms;
+  Result = FALSE;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  Dimms = NBPtr->ChannelPtr->Dimms;
+  QR_Dimms = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) {
+      QR_Dimms ++;
+    }
+  }
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) {
+      if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) ||
+          ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) ||
+           (Buffer[5] == ANY_NUM)) {
+        NBPtr->PsPtr->DramTerm = Buffer[6];
+        NBPtr->PsPtr->QR_DramTerm = Buffer[7];
+        NBPtr->PsPtr->DynamicDramTerm = Buffer[8];
+        Result = TRUE;
+        IDS_HDT_CONSOLE ("      Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]);
+      }
+    }
+  }
+  return Result;
+ }
+
+ /* -----------------------------------------------------------------------------*/
+/**
+ *      Perform Address Timing Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return          BOOLEAN -             TRUE : Action was performed
+ *                                             FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionAddrTmg (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT32 Speed;
+  UINT16 DimmConfig;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  DimmConfig = *(UINT16 *) &(Buffer[4]);
+
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]);
+      Result = TRUE;
+      IDS_HDT_CONSOLE ("      Platform Override: Address Timing:%08lx\n", *(UINT32*) &(Buffer[6]));
+    }
+  }
+  return Result;
+ }
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *      Perform Drive Strength Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return          BOOLEAN -             TRUE : Action was performed
+ *                                             FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionODCControl (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT32 Speed;
+  UINT16 DimmConfig;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  DimmConfig = *(UINT16 *) &(Buffer[4]);
+
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]);
+      Result = TRUE;
+      IDS_HDT_CONSOLE ("      Platform Override: ODC Control:%08lx\n", *(UINT32*)&(Buffer[6]));
+    }
+  }
+  return Result;
+ }
+
+  /* -----------------------------------------------------------------------------*/
+/**
+ *      Perform Slew Rate Platform Override
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *     @return          BOOLEAN -             TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPSODoActionSlewRate (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT32 Speed;
+  UINT16 DimmConfig;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
+  DimmConfig = *(UINT16 *) &(Buffer[4]);
+
+  if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal );
+      MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal );
+      Result = TRUE;
+      IDS_HDT_CONSOLE ("      Platform Override: Slew Rate:%08lx\n", *(UINT32 *) &(Buffer[6]));
+    }
+  }
+  return Result;
+ }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function overrides the  POR supported speed for a specific config
+ *
+ *      @param[in] NBPtr - Pointer to Current NBBlock
+ *      @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
+ *
+ *      @return          BOOLEAN -            TRUE : Action was performed
+ *                                            FALSE: Action was not performed
+ *
+ */
+BOOLEAN
+STATIC
+MemPSODoActionGetFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 *Buffer
+  )
+{
+  BOOLEAN Result;
+  CH_DEF_STRUCT *ChannelPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT16 DimmConfig;
+  UINT16 SpeedLimit;
+
+  Result = FALSE;
+  ChannelPtr = NBPtr->ChannelPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  DimmConfig = *(UINT16*) &(Buffer[0]);
+  SpeedLimit = 0;
+  //
+  // Match number of dimms, then Rank Type
+  //
+  if (ChannelPtr->Dimms == Buffer[2]) {
+    if (MemCheckRankType (ChannelPtr, DimmConfig)) {
+      //
+      // Select speed based on current voltage
+      //
+      if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+        SpeedLimit = *(UINT16*) &(Buffer[3]);
+      } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) {
+        SpeedLimit = *(UINT16*) &(Buffer[7]);
+      } else {
+        SpeedLimit = *(UINT16*) &(Buffer[5]);
+      }
+      //
+      // Set the Speed limit
+      //
+      if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+        DCTPtr->Timings.TargetSpeed = SpeedLimit;
+      }
+      Result = TRUE;
+      IDS_HDT_CONSOLE ("      Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit);
+    }
+  }
+  return Result;
+}
+
+ /* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function matches a particular Rank Type Mask to the installed
+ *    DIMM configuration on the provided channel.
+ *
+ *     @param[in]       *CurrentChannel       Pointer to CH_DEF_STRUCT
+ *     @param[in]       RankType              Mask of rank type to match
+ *
+ *     @return          BOOLEAN -             TRUE : Rank types match
+ *                                            FALSE: Rank types do not match
+ *
+ */
+BOOLEAN
+STATIC
+MemCheckRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel,
+  IN       UINT16 RankType
+  )
+{
+  BOOLEAN Result;
+  UINT8 i;
+  UINT16 DIMMRankType;
+
+  DIMMRankType = MemAGetPsRankType (CurrentChannel);
+  Result = TRUE;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+    if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) {
+      Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0);
+    }
+    if (!Result) {
+      break;
+    }
+  }
+  return Result;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c
new file mode 100755
index 0000000000..9cd15160a1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmEcc.c
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * mmEcc.c
+ *
+ * Main Memory Feature implementation file for ECC Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mfmemclr.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMEcc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMEcc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  UINT8 Die;
+  MEM_SHARED_DATA *SharedPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  BOOLEAN RetVal;
+
+  RetVal = TRUE;
+  RefPtr = mmPtr->MemPtr->ParameterListPtr;
+  SharedPtr = mmPtr->mmSharedPtr;
+  //
+  // Run Northbridge-specific ECC initialization feature for each die.
+  //
+  if (RefPtr->EnableEccFeature) {
+    SharedPtr->AllECC = TRUE;
+    AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader));
+
+    for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
+      mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die]));
+      RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL);
+    }
+    if (SharedPtr->AllECC == TRUE) {
+      RefPtr->GStatus[GsbAllECCDimms] = TRUE;
+      // Sync mem clear before setting scrub rate.
+      for (Die = 0; Die < mmPtr->DieCount; Die++) {
+        MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die]));
+      }
+      for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
+        mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die]));
+      }
+    }
+  }
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c
new file mode 100755
index 0000000000..1e425986a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmExcludeDimm.c
@@ -0,0 +1,235 @@
+/**
+ * @file
+ *
+ * mmExcludeDimm.c
+ *
+ * Main Memory Feature implementation file for RAS DIMM Exclude Feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mport.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMRASExcludeDIMM (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and disable Chip selects that fail training on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMRASExcludeDIMM (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  BOOLEAN IsEnabled;
+  BOOLEAN RetVal;
+  BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED];
+  UINT8   FirstEnabledNode;
+  UINT32  BottomIO;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  S_UINT64 SMsr;
+
+  FirstEnabledNode = 0;
+  IsEnabled = FALSE;
+  RetVal = TRUE;
+  NBPtr = MemMainPtr->NBPtr;
+  RefPtr = NBPtr[BSP_DIE].RefPtr;
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) {
+      if (!IsEnabled) {
+        // Record the first node that has exclude dimm enabled
+        FirstEnabledNode = Node;
+        IsEnabled = TRUE;
+      }
+    }
+  }
+
+  // Force memory address remap when we want to undo 1TB hoisting
+  if (NBPtr->SharedPtr->UndoHoistingAbove1TB) {
+    IsEnabled = TRUE;
+  }
+
+  if (IsEnabled) {
+    // Check if all nodes have all dimms excluded. If yes, fatal exit
+    NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
+    BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
+    // If the first node that has excluded dimms does not have a system base smaller
+    // than bottomIO, then we don't need to reset the GStatus, as we don't need to
+    // remap memory hole.
+    if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
+      RefPtr->GStatus[GsbHWHole] = FALSE;
+      RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
+      RefPtr->GStatus[GsbSoftHole] = FALSE;
+      RefPtr->HoleBase = 0;
+      RefPtr->SysLimit = 0;
+    }
+    // If Node Interleaving has been executed before the remapping then we need to
+    // start from the first node.
+    // There may be a few senarios:
+    // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after
+    //    remap
+    // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after
+    //    remap
+    // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap
+    if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
+      FirstEnabledNode = 0;
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      IsChannelIntlvEnabled [Node] = FALSE;
+      // Check if node interleaving has been enabled on this node
+      // if yes, disable it.
+      if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) {
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0);
+      }
+      if (Node >= FirstEnabledNode) {
+        // Remap memory on nodes with node number larger than the first node that has excluded dimms.
+        // If channel interleaving has already been enabled, need to disable it before remapping memory.
+        if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) {
+          NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0);
+          IsChannelIntlvEnabled [Node] = TRUE;
+        }
+        NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
+        NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
+      } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
+        // No change is needed in the memory map of this node.
+        // Need to adjust the current system base for other nodes processed later.
+        NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
+        RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit;
+        // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
+        // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
+        // and DramMemHoistValid.
+        // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
+        // DramHoleValid.
+        if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
+          NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        }
+      }
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
+    }
+
+    LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+    // Only when TOM is set can CpuMemTyping be re-run
+    if (SMsr.hi == 0 && SMsr.lo == 0) {
+      if (RefPtr->SysLimit != 0) {
+        NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
+
+        // When 1TB hoisting is not supported, TOP_MEM2 cannot exceed HT reserved region base.
+        if ((RefPtr->SysLimit >= HT_REGION_BASE_RJ16) && (NBPtr->SharedPtr->UndoHoistingAbove1TB)) {
+          SMsr.hi = HT_REGION_BASE_RJ16 >> (32 - 16);
+          SMsr.lo = HT_REGION_BASE_RJ16 << 16;
+          LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+          IDS_HDT_CONSOLE ("TOP_MEM2: %08lx0000\n", HT_REGION_BASE_RJ16);
+          RefPtr->Sub1THoleBase = HT_REGION_BASE_RJ16;
+          RefPtr->SysLimit = HT_REGION_BASE_RJ16 - 1;
+        }
+      }
+    }
+
+    // Re-run node interleaving if it has been exeucuted before the remap
+    if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
+      MemFeatMain.InterleaveNodes (MemMainPtr);
+    }
+
+    // Re-enable channel interleaving if it was enabled before remapping memory
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      if (IsChannelIntlvEnabled [Node]) {
+        NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]);
+      }
+    }
+
+    // Reset UndoHoistingAbove1TB if it was previously set
+    NBPtr->SharedPtr->UndoHoistingAbove1TB = FALSE;
+  }
+
+  // if all dimms on all nodes are excluded, do fatal exit
+  if (RefPtr->SysLimit == 0) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
+    ASSERT (FALSE);
+  }
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+  }
+
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c
new file mode 100755
index 0000000000..1c6645a721
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmLvDdr3.c
@@ -0,0 +1,126 @@
+/**
+ * @file
+ *
+ * mmLvDdr3.c
+ *
+ * Main Memory Feature implementation file for low voltage DDR3 support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMLvDdr3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Find the common supported voltage on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMLvDdr3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  BOOLEAN RetVal;
+  BOOLEAN SecondLoop;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *ParameterPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  mmSharedPtr = MemMainPtr->mmSharedPtr;
+  ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
+  mmSharedPtr->VoltageMap = 0xFF;
+  SecondLoop = FALSE;
+  RetVal = TRUE;
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]);
+    // Check if there is no common supported voltage
+    if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) {
+      // restart node loop by setting node to 0xFF
+      Node = 0xFF;
+      SecondLoop = TRUE;
+    }
+  }
+
+  if (mmSharedPtr->VoltageMap == 0) {
+    ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
+  } else {
+    ParameterPtr->DDR3Voltage = (DIMM_VOLTAGE) LibAmdBitScanReverse (mmSharedPtr->VoltageMap);
+  }
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+    // Check if the voltage needs force to 1.5V
+    NBPtr[Node].FamilySpecificHook[ForceLvDimmVoltage] (&NBPtr[Node], MemMainPtr);
+
+    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+  }
+
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c
new file mode 100755
index 0000000000..be328418f4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemClr.c
@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * mmMemclr.c
+ *
+ * Main Memory Feature implementation file for Memory Clear.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "mfmemclr.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMMctMemClr (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Initiates/synchronizes memory clear on all nodes with Dram on it.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMMctMemClr (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  BOOLEAN RetVal;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  NodeCnt = MemMainPtr->DieCount;
+  RetVal = TRUE;
+
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFMctMemClr_Init (&NBPtr[Node]);
+  }
+
+  for (Node = 0; Node < NodeCnt; Node++) {
+    MemFMctMemClr_Sync (&NBPtr[Node]);
+    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+  }
+
+  return RetVal;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c
new file mode 100755
index 0000000000..0c6dc149ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmMemRestore.c
@@ -0,0 +1,581 @@
+/**
+ * @file
+ *
+ * mmMemRestore.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE
+
+#define ST_PRE_ESR  0
+#define ST_POST_ESR 1
+#define ST_DONE     2
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemMRestoreDqsTimings (
+  IN       VOID                *Storage,
+  IN       MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+STATIC
+MemMSetCSRNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       PCI_ADDR PciAddr,
+  IN       UINT32 Value
+  );
+
+VOID
+STATIC
+MemMCreateS3NbBlock (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr,
+     OUT   S3_MEM_NB_BLOCK **S3NBPtr
+  );
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+extern MEM_NB_SUPPORT memNBInstalled[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and save memory context if possible.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+VOID
+MemMContextSave (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8 Node;
+  UINT8 i;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  LOCATE_HEAP_PTR LocHeap;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  DEVICE_BLOCK_HEADER *DeviceList;
+  AMD_CONFIG_PARAMS *StdHeader;
+  UINT32 BufferSize;
+  UINT64 BufferOffset;
+  MEM_NB_BLOCK  *NBArray;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
+
+  NBArray = MemMainPtr->NBPtr;
+  RefPtr = NBArray[BSP_DIE].RefPtr;
+
+  if (RefPtr->SaveMemContextCtl) {
+    RefPtr->MemContext.NvStorage = NULL;
+    RefPtr->MemContext.NvStorageSize = 0;
+
+    // Make sure DQS training has occurred before saving memory context
+    if (!RefPtr->MemRestoreCtl) {
+      StdHeader = &MemMainPtr->MemPtr->StdHeader;
+
+      MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr);
+      if (S3NBPtr != NULL) {
+        // Get the mask bit and the register list for node that presents
+        BufferSize = 0;
+        for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+          S3NBPtr->MemS3GetConPCIMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]);
+          S3NBPtr->MemS3GetConMSRMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]);
+          BufferSize += S3NBPtr->MemS3GetRegLstPtr (&NBArray[Node], (VOID *)&DeviceDescript[Node]);
+        }
+
+        // Base on the size of the device list, apply for a buffer for it.
+        AllocHeapParams.RequestedBufferSize = (UINT16) (BufferSize + sizeof (DEVICE_BLOCK_HEADER));
+        AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+        AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+        if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+          DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr;
+          DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
+
+          // Copy device list on the stack to the heap.
+          BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+          for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+            for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+              // Copy PCI device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
+              }
+              // Copy conditional PCI device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+              }
+              // Copy MSR device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
+              }
+              // Copy conditional MSR device descriptor to the heap if it exists.
+              if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
+                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+                DeviceList->NumDevices ++;
+                BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+              }
+            }
+          }
+
+          // Determine size needed
+          BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader);
+          AllocHeapParams.RequestedBufferSize = (UINT16) BufferSize;
+          AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE;
+          AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+          if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+            // Save memory context
+            SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader);
+            RefPtr->MemContext.NvStorageSize = BufferSize;
+          }
+
+          HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
+        }
+      }
+      HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
+
+      // Locate MemContext since it might have been shifted after deallocating
+      LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE;
+      if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
+        RefPtr->MemContext.NvStorage = LocHeap.BufferPtr;
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and restore memory context if possible.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  DQS timing restore succeeds.
+ *     @return          FALSE - DQS timing restore fails.
+ */
+BOOLEAN
+MemMContextRestore (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  MEM_NB_BLOCK  *NBArray;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+
+  NBArray = MemMainPtr->NBPtr;
+  RefPtr = NBArray[BSP_DIE].RefPtr;
+
+  IDS_HDT_CONSOLE ("!\nStart Mem Restore\n");
+  if (RefPtr->MemRestoreCtl) {
+    if (RefPtr->MemContext.NvStorage != NULL) {
+      MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr);
+      if (S3NBPtr != NULL) {
+        // Check DIMM config and restore DQS timings if possible
+        if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) {
+          RefPtr->MemRestoreCtl = FALSE;
+        }
+      } else {
+        RefPtr->MemRestoreCtl = FALSE;
+      }
+      HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader));
+    } else {
+      RefPtr->MemRestoreCtl = FALSE;
+    }
+  }
+
+  IDS_HDT_CONSOLE (RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n");
+  return RefPtr->MemRestoreCtl;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Restores all devices that contains DQS timings
+ *
+ *     @param[in]     Storage        Beginning of the device list.
+ *     @param[in,out]   MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ *
+ */
+BOOLEAN
+STATIC
+MemMRestoreDqsTimings (
+  IN       VOID                *Storage,
+  IN       MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  UINT8 *OrMask;
+  DEVICE_DESCRIPTORS Device;
+  INT16 i;
+  INT16 j;
+  DEVICE_BLOCK_HEADER *DeviceList;
+  PCI_REGISTER_BLOCK_HEADER *Reg;
+  CPCI_REGISTER_BLOCK_HEADER *CReg;
+  MSR_REGISTER_BLOCK_HEADER *MsrReg;
+  CMSR_REGISTER_BLOCK_HEADER *CMsrReg;
+  PCI_ADDR PciAddress;
+  MEM_NB_BLOCK  *NBArray;
+  UINT8 State;
+  UINT8 Node;
+  UINT8 Dct;
+  UINT8 MaxNode;
+
+  NBArray = MemMainPtr->NBPtr;
+  StdHeader = &(MemMainPtr->MemPtr->StdHeader);
+  DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
+  Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+  OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
+
+  if (DeviceList->NumDevices == 0) {
+    return FALSE;
+  }
+
+  MaxNode = 0;
+  State = ST_PRE_ESR;
+  for (i = 0; State != ST_DONE; i++) {
+    if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) ||
+        ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) {
+      MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader);
+      Node = Device.PciDevice->Node;
+      IDS_HDT_CONSOLE ("!Node %d\n", Node);
+      PciAddress = NBArray[Node].PciAddr;
+      for (j = 0; j < Reg->NumRegisters; j++) {
+        PciAddress.Address.Function = Reg->RegisterList[j].Function;
+        PciAddress.Address.Register = Reg->RegisterList[j].Offset;
+        PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ?
+                                     0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0;
+        if (!MemMSetCSRNb (&NBArray[Node], PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) {
+          return FALSE;   // Restore fails
+        }
+        OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize;
+      }
+
+      if (MaxNode < Node) {
+        MaxNode = Node;
+      }
+
+    } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) ||
+               ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) {
+      MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader);
+      Node = Device.CPciDevice->Node;
+      IDS_HDT_CONSOLE ("!Node %d\n", Node);
+      PciAddress = NBArray[Node].PciAddr;
+      for (j = 0; j < CReg->NumRegisters; j++) {
+        if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) &&
+            ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) {
+          PciAddress.Address.Function = CReg->RegisterList[j].Function;
+          PciAddress.Address.Register = CReg->RegisterList[j].Offset;
+          PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ?
+                                       0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0;
+          if (!MemMSetCSRNb (&NBArray[Node], PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) {
+            return FALSE;   // Restore fails
+          }
+          OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize;
+        }
+      }
+    } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) ||
+               ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) {
+      MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader);
+      for (j = 0; j < MsrReg->NumRegisters; j++) {
+        OrMask += 8;
+      }
+    } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) ||
+               ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) {
+      MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader);
+      for (j = 0; j < CMsrReg->NumRegisters; j++) {
+        if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) &&
+            ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) {
+          OrMask += 8;
+        }
+      }
+    }
+
+    switch (Device.CommonDeviceHeader->Type) {
+    case DEV_TYPE_PCI_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_PCI:
+      Device.PciDevice++;
+      break;
+    case DEV_TYPE_CPCI_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CPCI:
+      Device.CPciDevice++;
+      break;
+    case DEV_TYPE_MSR_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_MSR:
+      Device.MsrDevice++;
+      break;
+    case DEV_TYPE_CMSR_PRE_ESR:
+      // Fall through to advance the pointer after restoring context
+    case DEV_TYPE_CMSR:
+      Device.CMsrDevice++;
+      break;
+    default:
+      ASSERT (FALSE);
+      break;
+    }
+
+    if (i == (DeviceList->NumDevices - 1)) {
+      // Go to next state
+      State++;
+      i = -1;
+      Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
+
+      // Check to see if processor or DIMM population has changed
+      if ((MaxNode + 1) != MemMainPtr->DieCount) {
+        IDS_HDT_CONSOLE ("\tSTOP: Population changed\n");
+        return FALSE;
+      }
+
+      // Perform MemClk frequency change
+      for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+        if (NBArray[Node].MCTPtr->NodeMemSize != 0) {
+          NBArray[Node].BeforeDqsTraining (&NBArray[Node]);
+          if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) {
+            for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) {
+              NBArray[Node].SwitchDCT (&NBArray[Node], Dct);
+              NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed;
+            }
+            IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader));
+            NBArray[Node].ChangeFrequency (&NBArray[Node]);
+          }
+        }
+      }
+    }
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function filters out other settings and only restores DQS timings.
+ *
+ *     @param[in,out]   NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   PciAddr - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   Value - Value to be programmed
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemMSetCSRNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       PCI_ADDR PciAddr,
+  IN       UINT32 Value
+  )
+{
+  UINT32 Offset;
+  UINT8  Dct;
+  UINT32 Temp;
+  BOOLEAN RetVal;
+  UINT32 BOffset;
+
+  RetVal = TRUE;
+  if (PciAddr.Address.Segment != 0) {
+    if (PciAddr.Address.Segment == 0xF) {
+      PciAddr.Address.Segment = 0;
+      Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1);
+      Offset = PciAddr.Address.Register & 0x3FF;
+      BOffset = PciAddr.Address.Register & 0xFF;
+      if ((PciAddr.Address.Register & 0x800) == 0) {
+        if (((BOffset >= 1) && (BOffset <= 3)) ||
+            ((BOffset >= 5) && (BOffset <= 7)) ||
+            ((Offset >= 0x10) && (Offset <= 0x2B)) ||
+            ((Offset >= 0x30) && (Offset <= 0x4A))) {
+          IDS_HDT_CONSOLE ("\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value);
+          MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+        }
+      }
+    }
+  } else {
+    Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1);
+    Offset = PciAddr.Address.Register & 0xFF;
+
+    if (PciAddr.Address.Function == 2) {
+      if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) {
+        // If TestFail bit is set, set CsTestFail
+        NBPtr->SwitchDCT (NBPtr, Dct);
+        NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2);
+        IDS_HDT_CONSOLE ("\tBad CS:%d\n", ((Offset - 0x40) >> 2));
+      } else if (Offset == 0x80) {
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        if (Temp != Value) {
+          IDS_HDT_CONSOLE ("\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+      } else if (Offset == 0x90) {
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        if ((Temp & 0x0001F000) != (Value & 0x0001F000)) {
+          IDS_HDT_CONSOLE ("\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+      } else if (Offset == 0x94) {
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        if ((Temp & 0x00061000) != (Value & 0x00061000)) {
+          IDS_HDT_CONSOLE ("\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+        if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) {
+          IDS_HDT_CONSOLE ("\tSTOP: MemClk has changed\n");
+          RetVal = FALSE;
+        }
+        // Restore ZqcsInterval
+        Temp &= 0xFFFFF3FF;
+        Temp |= (Value & 0x00000C00);
+        LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+      } else if (Offset == 0x78) {
+        // Program MaxRdLat
+        LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+        Temp &= 0x0009BF0F;
+        Temp |= (Value & 0xFFC00000);
+        LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
+      } else if (PciAddr.Address.Register == 0x110) {
+        if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) {
+          IDS_HDT_CONSOLE ("\tSTOP: DIMM config changed\n");
+          RetVal = FALSE;
+        }
+      }
+    }
+  }
+
+  if (RetVal == FALSE) {
+    NBPtr->SwitchDCT (NBPtr, 0);
+    NBPtr->DCTPtr->Timings.CsTrainFail = 0;
+    NBPtr->SwitchDCT (NBPtr, 1);
+    NBPtr->DCTPtr->Timings.CsTrainFail = 0;
+  }
+
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Create S3 NB Block.
+ *
+ *     @param[in,out]   MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *     @param[out]      S3NBPtr   - Pointer to the S3 NB Block pointer
+ *
+ */
+VOID
+STATIC
+MemMCreateS3NbBlock (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr,
+     OUT   S3_MEM_NB_BLOCK **S3NBPtr
+  )
+{
+  UINT8 Node;
+  UINT8 i;
+  MEM_NB_BLOCK  *NBArray;
+  MEM_NB_BLOCK  *DummyNBs;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  NBArray = MemMainPtr->NBPtr;
+
+  *S3NBPtr = NULL;
+
+  // Allocate heap for S3 NB Blocks
+  AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK)));
+  AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
+    *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr;
+    DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK));
+
+    // Initialize S3 NB Blocks
+    for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+      (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node];
+
+      for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) {
+        if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) {
+          break;
+        }
+      };
+      if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
+        *S3NBPtr = NULL;
+        break;
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c
new file mode 100755
index 0000000000..5e39cdca4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmNodeInterleave.c
@@ -0,0 +1,137 @@
+/**
+ * @file
+ *
+ * mmNodeInterleave.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE
+
+extern BOOLEAN MemMMctMemClr (MEM_MAIN_DATA_BLOCK *MemMainPtr);
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMInterleaveNodes (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and enable node interleaving on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMInterleaveNodes (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  UINT8   NodeCnt;
+  BOOLEAN RetVal;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = MemMainPtr->NBPtr;
+  NodeCnt = 0;
+  RetVal = TRUE;
+
+  if (NBPtr->RefPtr->EnableNodeIntlv) {
+    if (!MemMMctMemClr (MemMainPtr)) {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+      return FALSE;
+    }
+
+    MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE;
+    MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0;
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) {
+        break;
+      }
+      if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
+        NodeCnt ++;
+      }
+    }
+
+    if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) {
+      MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt;
+      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+        if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
+          NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]);
+        }
+      }
+      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+        NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
+        RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+      }
+    } else {
+      //
+      // If all nodes cannot be interleaved
+      //
+      PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    }
+  }
+
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c
new file mode 100755
index 0000000000..79519edac1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmOnlineSpare.c
@@ -0,0 +1,157 @@
+/**
+ * @file
+ *
+ * mmOnlineSpare.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMOnlineSpare (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check and enable online spare on all nodes.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMOnlineSpare (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT8   Node;
+  BOOLEAN IsEnabled;
+  UINT8   FirstEnabledNode;
+  UINT32  BottomIO;
+  BOOLEAN RetVal;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader));
+  FirstEnabledNode = 0;
+  IsEnabled = FALSE;
+  RetVal = TRUE;
+  NBPtr = MemMainPtr->NBPtr;
+  RefPtr = NBPtr[BSP_DIE].RefPtr;
+
+  for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+    if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) {
+      if (!IsEnabled) {
+        // Record the first node that has spared dimm enabled
+        FirstEnabledNode = Node;
+        IsEnabled = TRUE;
+      }
+    }
+  }
+
+  if (IsEnabled) {
+    NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
+    BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
+    // If the first node that has spared dimms does not have a system base smaller
+    // than bottomIO, then we don't need to reset the GStatus, as we don't need to
+    // remap memory hole.
+    if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
+      RefPtr->GStatus[GsbHWHole] = FALSE;
+      RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
+      RefPtr->GStatus[GsbSoftHole] = FALSE;
+      RefPtr->HoleBase = 0;
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      if (Node >= FirstEnabledNode) {
+        // Remap memory on nodes with node number larger than the first node that has spared dimms.
+        NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
+        NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
+        NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
+      } else {
+        // No change is needed in the memory map of this node.
+        // Need to adjust the current system base for other nodes processed later.
+        NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
+        // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
+        // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
+        // and DramMemHoistValid.
+        // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
+        // DramHoleValid.
+        if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
+          NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
+        }
+      }
+    }
+
+    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
+      NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
+      RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
+    }
+    NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
+  }
+  return RetVal;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c
new file mode 100755
index 0000000000..2331b6a9da
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmParallelTraining.c
@@ -0,0 +1,272 @@
+/**
+ * @file
+ *
+ * mmNodeInterleave.c
+ *
+ * Main Memory Feature implementation file for Node Interleaving
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "GeneralServices.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mu.h"
+#include "mfParallelTraining.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE
+
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMParallelTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMParallelTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK *NBPtr;
+  DIE_INFO TrainInfo[MAX_NODES_SUPPORTED];
+  AP_DATA_TRANSFER ReturnData;
+  AGESA_STATUS Status;
+  UINT8 ApSts;
+  UINT8 Die;
+  UINT8 Socket;
+  UINT32 Module;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 Time;
+  UINT32 TimeOut;
+  BOOLEAN StillTraining;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT8 *BufferPtr;
+  BOOLEAN TimeoutEn;
+
+  NBPtr = mmPtr->NBPtr;
+  MemPtr = mmPtr->MemPtr;
+  StdHeader = &(mmPtr->MemPtr->StdHeader);
+  Time = 0;
+  TimeOut = PARALLEL_TRAINING_TIMEOUT;
+  TimeoutEn = TRUE;
+  IDS_TIMEOUT_CTL (&TimeoutEn);
+
+  IDS_HDT_CONSOLE ("!\nStart parallel training\n");
+  AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader);
+  //
+  // Initialize Training Info Array
+  //
+  for (Die = 0; Die < mmPtr->DieCount; Die ++) {
+    Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId;
+    Module = NBPtr[Die].MCTPtr->DieId;
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF);
+    IDS_HDT_CONSOLE ("\tLaunch core %lx of socket %x\n", LowCore, Socket);
+    TrainInfo[Die].Training = FALSE;
+  }
+  //
+  // Start Training on Each remote die.
+  //
+  for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
+    if (Die != BSP_DIE) {
+      NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die]));
+      if (NBPtr[Die].MCTPtr->NodeMemSize != 0) {
+        if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) {
+          // Fail to launch code on AP
+          PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr);
+          MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader);
+        } else {
+          TrainInfo[Die].Training = TRUE;
+        }
+      }
+    }
+  }
+  //
+  // Call training on BSP
+  //
+  IDS_HDT_CONSOLE ("!Node %d\n", NBPtr[BSP_DIE].Node);
+  NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE]));
+  NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE]));
+  NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE]));
+
+  //
+  // Get Results from remote processors training
+  //
+  do {
+    StillTraining = FALSE;
+    for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
+      //
+      // For each Die that is training, read the status
+      //
+      if (TrainInfo[Die].Training == TRUE) {
+        ApSts = ApUtilReadRemoteControlByte (TrainInfo[Die].Socket, TrainInfo[Die].Core, StdHeader);
+        if ((ApSts & 0x80) == 0) {
+          //
+          // Allocate buffer for received data
+          //
+          AllocHeapParams.RequestedBufferSize = (
+            sizeof (DIE_STRUCT) +
+            NBPtr[Die].DctCount * (
+              sizeof (DCT_STRUCT) + (
+                NBPtr[Die].ChannelCount * (
+                  sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
+                   (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount *
+                    NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount *
+                    NUMBER_OF_DELAY_TABLES) +
+                    (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                  )
+                )
+              )
+            )
+          ) + 3;
+          AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0);
+          AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+          if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+            //
+            // Receive Training Results
+            //
+
+            ReturnData.DataPtr = AllocHeapParams.BufferPtr;
+            ReturnData.DataSizeInDwords = AllocHeapParams.RequestedBufferSize / 4;
+            ReturnData.DataTransferFlags = 0;
+            Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader);
+            if (Status != AGESA_SUCCESS) {
+              SetMemError (Status, NBPtr[Die].MCTPtr);
+            }
+
+            BufferPtr = AllocHeapParams.BufferPtr;
+            LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader);
+            BufferPtr += sizeof (DIE_STRUCT);
+            LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData,
+                            BufferPtr,
+                            NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)),
+                            StdHeader);
+            BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT));
+            LibAmdMemCopy ( NBPtr[Die].PSBlock,
+                            BufferPtr,
+                            NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK),
+                            StdHeader);
+            BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK);
+            LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys,
+                            BufferPtr,
+                            (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) *
+                            ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount *
+                              NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount *
+                              NUMBER_OF_DELAY_TABLES) +
+                              (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                            ),
+                            StdHeader);
+
+            HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
+
+            NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die]));
+            TrainInfo[Die].Training = FALSE;
+          } else {
+            PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader);
+            SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr);
+            ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer
+          }
+        } else if (ApSts == CORE_IDLE) {
+          // AP does not have buffer to transmit to BSP
+          // AP fails to locate a buffer for data transfer
+          TrainInfo[Die].Training = FALSE;
+        } else {
+          // Signal to loop through again
+          StillTraining = TRUE;
+        }
+      }
+    }
+    // Wait for 1 us
+    MemUWait10ns (100, NBPtr->MemPtr);
+    Time ++;
+  } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished
+                                                // if cannot finish in 1 s, do fatal exit
+
+  if (StillTraining && TimeoutEn) {
+    // Parallel training time out, do fatal exit, as there is at least one AP hangs.
+    PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
+    ASSERT(FALSE); // Timeout occurred while still training
+  }
+
+  for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
+    if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
+      return FALSE;
+    }
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c
new file mode 100755
index 0000000000..fe73ead741
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmStandardTraining.c
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * mmStandardTraining.c
+ *
+ * Main Memory Feature implementation file for Standard Training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+MemMStandardTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * MemMStandardTraining
+ *
+ * This function implements standard memory training whereby training functions
+ * for all nodes are run by the BSP.
+ *
+ *
+ *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemMStandardTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  )
+{
+  UINT8 Die;
+  //
+  // Run Northbridge-specific Standard Training feature for each die.
+  //
+  IDS_HDT_CONSOLE ("!\nStart serial training\n");
+  for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
+    IDS_HDT_CONSOLE ("!Node %d\n", Die);
+    AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
+    mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);
+    mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);
+    mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);
+    if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
+      break;
+    }
+  }
+  return (BOOLEAN) (Die == mmPtr->DieCount);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
new file mode 100755
index 0000000000..b8a6572cc1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmUmaAlloc.c
@@ -0,0 +1,224 @@
+/**
+ * @file
+ *
+ * mmUmaAlloc.c
+ *
+ * Main Memory Feature implementation file for UMA allocation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "heapManager.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "Ids.h"
+#include "mport.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+extern BUILD_OPT_CFG UserOptions;
+
+BOOLEAN
+MemMUmaAlloc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *    UMA allocation mechanism.
+ *
+ *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK
+ *
+ */
+BOOLEAN
+MemMUmaAlloc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  )
+{
+  UINT32 TOM;
+  UINT32 TOM2;
+  UINT32 UmaSize;
+  UINT32 TopOfChIntlv;
+  UINT32 UmaAlignment;
+  UINT32 UmaAbove4GBase;
+  UINT32 UmaBelow4GBase;
+  BOOLEAN DctSelIntLvEn;
+  BOOLEAN UmaAbove4GEn;
+  S_UINT64 SMsr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UMA_INFO *UmaInfoPtr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  MemPtr = MemMainPtr->MemPtr;
+  NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]);
+  RefPtr = NBPtr->RefPtr;
+
+  TOM2 = 0;
+  SMsr.lo = SMsr.hi = 0;
+  UmaAbove4GBase = 0;
+  RefPtr->UmaBase = 0;
+  UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment;
+  UmaAbove4GEn = UserOptions.CfgUmaAbove4G;
+  DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) ? TRUE : FALSE;
+  TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16);
+
+  // Allocate heap for UMA_INFO
+  AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO);
+  AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    ASSERT(FALSE); // Could not allocate heap for Uma information.
+    return FALSE;
+  }
+  UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr;
+  // Default all the fields of UMA_INFO
+  UmaInfoPtr->UmaMode = (UINT8) UMA_NONE;
+  UmaInfoPtr->UmaSize = 0;
+  UmaInfoPtr->UmaBase = 0;
+  UmaInfoPtr->UmaAttributes = 0;
+  UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed;
+
+  switch (RefPtr->UmaMode) {
+  case UMA_NONE:
+    UmaSize = 0;
+    break;
+  case UMA_SPECIFIED:
+    UmaSize = RefPtr->UmaSize;
+    break;
+  case UMA_AUTO:
+    UmaSize = NBPtr->GetUmaSize (NBPtr);
+    break;
+  default:
+    UmaSize = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  if (UmaSize != 0) {
+    //TOM scaled from [47:0] to [47:16]
+    LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16));
+
+    UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment;
+    // Initialize Ref->UmaBase to UmaBelow4GBase
+    RefPtr->UmaBase = UmaBelow4GBase;
+
+    // Uma Above 4G support
+    if (UmaAbove4GEn) {
+      //TOM2 scaled from [47:0] to [47:16]
+      LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+      TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16));
+      if (TOM2 != 0) {
+        UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment;
+        //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB
+        if (UmaAbove4GBase < _4GB_RJ16) {
+          UmaAbove4GBase = 0;
+        }
+        if (UmaAbove4GBase != 0) {
+          RefPtr->UmaBase = UmaAbove4GBase;
+          // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved.
+          // 2. TopOfChIntlv >= TOM tells us :
+          //   -All or portion of Uma region that above 4G is NOT interleaved.
+          //   -Whole Uma region that below 4G is interleaved.
+          if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) {
+            RefPtr->UmaBase = UmaBelow4GBase;
+          }
+        }
+      }
+    }
+
+    UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode);
+    UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16);
+
+    if (RefPtr->UmaBase >= _4GB_RJ16) {
+      // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it.
+      RefPtr->UmaSize = TOM2 - UmaAbove4GBase;
+      // Uma Typing
+      MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2);
+      if (DctSelIntLvEn && (TopOfChIntlv == 0)) {
+        UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE;
+      }
+    } else {
+      // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it.
+      RefPtr->UmaSize = TOM - UmaBelow4GBase;
+      // Uma Typing
+      NBPtr->UMAMemTyping (NBPtr);
+      if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) {
+        UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE;
+      }
+    }
+    UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c
new file mode 100755
index 0000000000..2a183a3e0e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mmflow.c
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * mmflow.c
+ *
+ * Main Memory Flow Entrypoint file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "AdvancedApi.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE
+/* features */
+
+extern MEM_NB_SUPPORT memNBInstalled[];
+extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
+extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
+extern MEM_MAIN_FLOW_CONTROL* MemMainFlowControlPtr;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemSPDDataProcess (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function is the main memory configuration function for DR DDR3
+ *
+ *      Requirements:
+ *
+ *      Run-Time Requirements:
+ *      1. Complete Hypertransport Bus Configuration
+ *      2. AmdMemInitDataStructDef must be run to set default values
+ *      3. MSR bit to allow access to high PCI regs set on all nodes
+ *      4. BSP in Big Real Mode
+ *      5. Stack available
+ *      6. MCG_CTL=-1, MC4_EN=0 for all CPUs
+ *      7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
+ *      8. All var MTRRs reset to zero
+ *      9. State of NB_CFG.DisDatMsk set properly on all CPUs
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  MEM_SHARED_DATA  mmSharedData;
+  MEM_MAIN_DATA_BLOCK mmData;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_TECH_BLOCK *TechPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AGESA_STATUS Retval;
+  UINT8 i;
+  UINT8 Die;
+  UINT8 DieCount;
+
+  AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader);
+  IDS_HDT_CONSOLE_INIT (&MemPtr->StdHeader);
+  ASSERT (MemPtr != NULL);
+
+  //----------------------------------------------------------------------------
+  // Read In SPD Data
+  //----------------------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader);
+  MemSPDDataProcess (MemPtr);
+
+  //----------------------------------------------------------------
+  // Initialize Main Data Block
+  //----------------------------------------------------------------
+  mmData.MemPtr = MemPtr;
+  mmData.mmSharedPtr = &mmSharedData;
+  LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader);
+  mmSharedData.DimmExcludeFlag = NORMAL;
+  mmSharedData.NodeIntlv.IsValid = FALSE;
+  //----------------------------------------------------------------
+  // Discover populated CPUs
+  //
+  //----------------------------------------------------------------
+  Retval = MemSocketScan (&mmData);
+  if (Retval == AGESA_FATAL) {
+    return Retval;
+  }
+  DieCount = mmData.DieCount;
+  //----------------------------------------------------------------
+  //
+  // Allocate Memory for NB and Tech Blocks
+  //
+  //  NBPtr[Die]----+
+  //                |
+  //                V
+  //  +---+---+---+---+---+---+---+---+
+  //  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |   NB Blocks
+  //  +---+---+---+---+---+---+---+---+
+  //    |   |   |   |   |   |   |   |
+  //    |   |   |   |   |   |   |   |
+  //    v   v   v   v   v   v   v   v
+  //  +---+---+---+---+---+---+---+---+
+  //  | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |   Tech Blocks
+  //  +---+---+---+---+---+---+---+---+
+  //
+  //
+  //----------------------------------------------------------------
+  AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK)));
+  AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
+    ASSERT(FALSE); // NB and Tech Block Heap allocate error
+    return AGESA_FATAL;
+  }
+  NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
+  TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]);
+  mmData.NBPtr = NBPtr;
+  mmData.TechPtr = TechPtr;
+
+  //----------------------------------------------------------------
+  // Create NB Blocks
+  //
+  //----------------------------------------------------------------
+  for (Die = 0 ; Die < DieCount ; Die++ ) {
+    i = 0;
+    while (memNBInstalled[i].MemConstructNBBlock != 0) {
+      if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) {
+        break;
+      }
+      i++;
+    }
+    // Couldn't find a NB which supported this family
+    if (memNBInstalled[i].MemConstructNBBlock == 0) {
+      return AGESA_FATAL;
+    }
+  }
+  //----------------------------------------------------------------
+  // Create Technology Blocks
+  //
+  //----------------------------------------------------------------
+  for (Die = 0 ; Die < DieCount ; Die++ ) {
+    i = 0;
+    while (memTechInstalled[i] != NULL) {
+      if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) {
+        NBPtr[Die].TechPtr = &TechPtr[Die];
+        break;
+      }
+      i++;
+    }
+    // Couldn't find a Tech block which supported this family
+    if (memTechInstalled[i] == NULL) {
+      return AGESA_FATAL;
+    }
+  }
+  //----------------------------------------------------------------
+  //
+  //                 MEMORY INITIALIZATION TASKS
+  //
+  //----------------------------------------------------------------
+
+  Retval = MemMainFlowControlPtr (&mmData);
+
+  //----------------------------------------------------------------
+  // Check for errors and return
+  //----------------------------------------------------------------
+  AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader);
+  for (Die = 0; Die < DieCount; Die++) {
+    if (NBPtr[Die].MCTPtr->ErrCode > Retval) {
+      Retval = NBPtr[Die].MCTPtr->ErrCode;
+    }
+  }
+
+  return Retval;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
+ *
+ *    The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms.  At this
+ *  point, the Memory controller type is not known, and the platform BIOS does not know the anything
+ *  about which DIMM is on which DCT.  So the DCT relationship is abstracted from the arrangement
+ *  of SPD information here.  We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(),
+ *  and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs
+ *  are connected to.  The functions rely on either the maximum values in the
+ *  PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H.
+ *
+ *  This mapping is translated in the Northbridge object Constructor and the Technology block constructor.
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+
+VOID
+STATIC
+MemSPDDataProcess (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  UINT8 Dimm;
+  UINT8 DimmIndex;
+  UINT32 AgesaStatus;
+  UINT8 MaxSockets;
+  UINT8 MaxChannelsPerSocket;
+  UINT8 MaxDimmsPerChannel;
+  SPD_DEF_STRUCT *DimmSPDPtr;
+  PSO_TABLE *PsoTable;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AGESA_READ_SPD_PARAMS SpdParam;
+
+  ASSERT (MemPtr != NULL);
+  MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
+  PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration;
+  //
+  // Allocate heap for the table
+  //
+  AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT));
+  AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+    MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    //
+    // Initialize SpdParam Structure
+    //
+    LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader);
+    //
+    // Populate SPDDataBuffer
+    //
+    SpdParam.MemData = MemPtr;
+    DimmIndex = 0;
+    for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) {
+      MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader);
+      SpdParam.SocketId = Socket;
+      for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+        SpdParam.MemChannelId = Channel;
+        MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel);
+        for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) {
+          SpdParam.DimmId = Dimm;
+          DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]);
+          SpdParam.Buffer = DimmSPDPtr->Data;
+          AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader);
+          AgesaStatus = AgesaReadSpd (0, &SpdParam);
+          AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader);
+          if (AgesaStatus == AGESA_SUCCESS) {
+            DimmSPDPtr->DimmPresent = TRUE;
+            printk(BIOS_DEBUG, "Socket %x Channel %x Dimm %x found dimm: %p\n", Socket, Channel, Dimm, SpdParam.Buffer);
+
+          } else {
+            DimmSPDPtr->DimmPresent = FALSE;
+            printk(BIOS_DEBUG, "Socket %x Channel %x Dimm %x not found dimm\n", Socket, Channel, Dimm);
+
+          }
+        }
+      }
+    }
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader);
+    //
+    // Assert here if unable to allocate heap for SPDs
+    //
+    IDS_ERROR_TRAP;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
new file mode 100755
index 0000000000..fe4c86b604
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
@@ -0,0 +1,483 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+;  $Workfile:: mu.asm   $ $Revision:: 443#$  $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; Description: Main memory controller system configuration for AGESA
+;
+;
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+;============================================================================
+
+
+    .XLIST
+    .LIST
+
+    .686p
+    .MODEL FLAT
+    .CODE
+    ASSUME FS: NOTHING
+
+; Define the calling convention used for the C library modules
+;@attention - This should be in a central include file
+CALLCONV    EQU     NEAR C
+
+
+;===============================================================================
+;memUOutPort:
+;
+; Do a 32 Bit IO Out operation using edx.
+; NOTE: This function will be obsolete in the future.
+;
+;             In: Port  - port number
+;                 Value - value to be written
+;
+;            Out:
+;
+; All registers preserved.
+;===============================================================================
+MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
+    pushad
+    mov edx,Port
+    mov eax,Value
+    out dx,al
+    popad
+    ret
+MemUOutPort ENDP
+
+
+;----------------------------------------------------------------------------
+; _SFENCE();
+;
+_SFENCE macro
+    db  0Fh,0AEh,0F8h
+    endm
+
+;----------------------------------------------------------------------------
+; _MFENCE();
+;
+_MFENCE macro
+    db  0Fh,0AEh,0F0h
+    endm
+
+;----------------------------------------------------------------------------
+; _EXECFENCE();
+;
+_EXECFENCE macro
+    out 0EDh,al             ;prevent speculative execution of following instructions
+    endm
+
+;===============================================================================
+;MemUWriteCachelines:
+;   Write a test pattern to DRAM
+;
+;             In: Pattern   - pointer to the write pattern
+;                 Address   - Physical address to be read
+;                 ClCount   - number of cachelines to be read
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
+        pushad
+        push ds
+
+        mov eax,Address
+        push ss
+        pop ds
+        xor edx,edx
+        mov edx, DWORD PTR Pattern
+        mov esi,edx
+        mov edx,16
+        _EXECFENCE
+        xor ecx, ecx
+        mov cx,ClCount
+        shl ecx,2
+        @@:
+        db 66h, 0Fh,6Fh,06           ;MOVDQA xmm0,[esi]
+        db 64h, 66h, 0Fh,0E7h,00      ;MOVNTDQ fs:[eax],xmm0  (xmm0 is 128 bits)
+        add eax,edx
+        add esi,edx
+        loop @B
+
+        pop ds
+        popad
+        ret
+MemUWriteCachelines ENDP
+
+;===============================================================================
+;MemUReadCachelines:
+;
+; Read a pattern of 72 bit times (per DQ), to test dram functionality.  The
+;pattern is a stress pattern which exercises both ISI and crosstalk.  The number
+;of cache lines to fill is dependent on DCT width mode and burstlength.
+;
+;             In: Buffer    - pointer to a buffer where read data will be stored
+;                 Address   - Physical address to be read
+;                 ClCount   - number of cachelines to be read
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
+LOCAL Count:BYTE
+        pushad
+        ; First, issue continuous dummy reads to fill up the cache
+        mov eax,Address
+        .if (ClCount > 18)
+            mov cx,ClCount
+            shr cx,4
+            mov Count,cl
+            .while (Count != 0)
+                push eax
+                mov edi,eax
+                add edi,128                     ;bias value (to account for signed displacement)
+                                                ;clflush opcode=0F AE /7
+                mov esi,edi
+                mov ebx,esi
+                mov ecx,esi
+                mov edx,esi
+                add edi,4*64                    ;TestAddr+4 cache lines
+                add ebx,8*64                    ;TestAddr+8 cache lines
+                add ecx,12*64                   ;TestAddr+12 cache lines
+                add edx,16*64                   ;TestAddr+16 cache lines
+                sub edx,128
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+                mov eax,fs:[edi]                ;TestAddr+6 cache lines
+                _MFENCE
+                mov eax,fs:[edi+64]             ;TestAddr+7 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-128]            ;TestAddr+8 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-64]             ;TestAddr+9 cache lines
+                _MFENCE
+                mov eax,fs:[ebx]                ;TestAddr+10 cache lines
+                _MFENCE
+                mov eax,fs:[ebx+64]             ;TestAddr+11 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-128]            ;TestAddr+12 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-64]             ;TestAddr+13 cache lines
+                _MFENCE
+                mov eax,fs:[ecx]                ;TestAddr+14 cache lines
+                _MFENCE
+                mov eax,fs:[ecx+64]             ;TestAddr+15 cache lines
+                _MFENCE
+                pop eax
+                add eax,(16*64)                 ;Next 16CL
+                dec Count
+            .endw
+        .else
+            mov edi,eax
+            add edi,128                     ;bias value (to account for signed displacement)
+                                            ;clflush opcode=0F AE /7
+            mov esi,edi
+            mov ebx,esi
+            mov ecx,esi
+            mov edx,esi
+            add edi,4*64                    ;TestAddr+4 cache lines
+            add ebx,8*64                    ;TestAddr+8 cache lines
+            add ecx,12*64                   ;TestAddr+12 cache lines
+            add edx,16*64                   ;TestAddr+16 cache lines
+            sub edx,128
+            .if(ClCount == 1)
+                _MFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+            .elseif(ClCount == 3)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+            .elseif(ClCount == 6)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+            .elseif(ClCount == 9)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+                mov eax,fs:[edi]                ;TestAddr+6 cache lines
+                _MFENCE
+                mov eax,fs:[edi+64]             ;TestAddr+7 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-128]            ;TestAddr+8 cache lines
+                _MFENCE
+            .elseif(ClCount == 18)
+                _EXECFENCE
+                mov eax,fs:[esi-128]            ;TestAddr
+                _MFENCE
+                mov eax,fs:[esi-64]             ;TestAddr+1 cache line
+                _MFENCE
+                mov eax,fs:[esi]                ;TestAddr+2 cache lines
+                _MFENCE
+                mov eax,fs:[esi+64]             ;TestAddr+3 cache lines
+                _MFENCE
+                mov eax,fs:[edi-128]            ;TestAddr+4 cache lines
+                _MFENCE
+                mov eax,fs:[edi-64]             ;TestAddr+5 cache lines
+                _MFENCE
+                mov eax,fs:[edi]                ;TestAddr+6 cache lines
+                _MFENCE
+                mov eax,fs:[edi+64]             ;TestAddr+7 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-128]            ;TestAddr+8 cache lines
+                _MFENCE
+                mov eax,fs:[ebx-64]             ;TestAddr+9 cache lines
+                _MFENCE
+                mov eax,fs:[ebx]                ;TestAddr+10 cache lines
+                _MFENCE
+                mov eax,fs:[ebx+64]             ;TestAddr+11 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-128]            ;TestAddr+12 cache lines
+                _MFENCE
+                mov eax,fs:[ecx-64]             ;TestAddr+13 cache lines
+                _MFENCE
+                mov eax,fs:[ecx]                ;TestAddr+14 cache lines
+                _MFENCE
+                mov eax,fs:[ecx+64]             ;TestAddr+15 cache lines
+                _MFENCE
+                mov eax,fs:[edx]                ;TestAddr+16 cache lines
+                _MFENCE
+                mov eax,fs:[edx+64]             ;TestAddr+17 cache lines
+                _MFENCE
+            .endif
+        .endif
+        _MFENCE
+
+        ; Then, copy data to buffer
+        mov esi,Address
+        xor edx,edx
+        mov edx,DWORD PTR Buffer
+        mov edi,edx
+        xor ecx, ecx
+        mov cx,ClCount
+        shl ecx,6
+        @@:
+        mov al,fs:[esi]
+        mov ss:[edi],al
+        inc esi
+        inc edi
+        loop @B
+
+        popad
+        ret
+MemUReadCachelines ENDP
+
+;===============================================================================
+;MemUDummyCLRead:
+;
+;   Perform a single cache line read from a given physical address.
+;
+;             In: Address   - Physical address to be read
+;                 ClCount   - number of cachelines to be read
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
+    _SFENCE
+    pushad
+    mov eax,Address
+    mov dl,fs:[eax]
+    popad
+    ret
+MemUDummyCLRead ENDP
+
+;===============================================================================
+;MemUFlushPattern:
+;
+; Flush a pattern of 72 bit times (per DQ) from cache.  This procedure is used
+;to ensure cache miss on the next read training.
+;
+;             In: Address   - Physical address to be flushed
+;                 ClCount   - number of cachelines to be flushed
+;            Out:
+;
+;All registers preserved.
+;===============================================================================
+MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
+        pushad
+        mov edi,Address
+        movzx ecx,ClCount
+        @@:
+        _MFENCE                     ; Force strong ordering of clflush
+        db  64h,0Fh,0AEh,3Fh        ; MemUClFlush fs:[edi]
+        _MFENCE
+        add edi,64
+        loop @B
+        popad
+        ret
+MemUFlushPattern ENDP
+
+
+;===============================================================================
+;MemUGetWrLvNblErr:
+;   Read ClCount number of cachelines then return the bitmap that indicates
+;   the write leveling result of each byte lane.
+;
+;   IN:     ErrBitmap - pointer to a DWORD that will be assigned with WL result
+;           Address   - Physical address to be sampled
+;           ClCount   - number of cachelines to be read
+;
+;   OUT:    ErrBitmap - WL result
+;
+;All registers preserved
+;===============================================================================
+MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
+LOCAL ZeroCount[32]:WORD
+
+        pushad
+        mov esi,Address
+        _EXECFENCE
+    ;Cache fill
+        movzx ecx,ClCount
+        @@:
+        mov eax,fs:[esi]
+        add esi,64
+        loop @B
+        _MFENCE
+
+    ; Then, count the number of 0's
+        ;push es
+        ;push ss
+        ;pop es
+        lea edi,ZeroCount
+        mov cx,SIZEOF ZeroCount
+        mov al,0
+        rep stosb
+        ;pop es
+
+        mov esi,Address
+        lea edi,ZeroCount
+        mov cx,ClCount
+        shl cx,6
+        .while(cx > 0)
+            mov al,fs:[esi]
+            test al,00Fh        ;check lower nibble
+            .if(ZERO?)
+                inc WORD PTR [edi]
+            .endif
+            add edi,2
+            test al,0F0h        ;check upper nibble
+            .if(ZERO?)
+                inc WORD PTR [edi]
+            .endif
+            add edi,2
+            inc esi
+            dec cx
+            test cx,07h
+            .if(ZERO?)
+                sub edi,(16*2)
+                sub cx,8
+                add esi,8
+            .endif
+        .endw
+
+    ; Then, average and compress data to error bits
+        lea esi,ZeroCount
+        mov dx,ClCount
+        shl dx,1
+        xor eax,eax
+        xor ecx,ecx
+        mov cl,0
+        .while(cl<16)
+            .if(WORD PTR [esi] < dx)
+                bts eax,ecx
+            .endif
+            add esi,2
+            inc cl
+        .endw
+        xor edx,edx
+        mov dx,WORD PTR ErrBitmap
+        mov [edx], ax
+
+        popad
+        ret
+MemUGetWrLvNblErr ENDP
+
+;===============================================================================
+;AlignPointerTo16Byte:
+;   Modifies BufferPtr to be 16 byte aligned
+;
+;             In: BufferPtrPtr - Pointer to buffer pointer
+;            Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
+;
+;All registers preserved.
+;===============================================================================
+AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
+        push edx
+        push eax
+        mov edx, BufferPtrPtr
+        mov eax, [edx]
+        add eax, 16
+        and ax, 0FFF0h
+        mov [edx], eax
+        pop eax
+        pop edx
+        ret
+AlignPointerTo16Byte ENDP
+
+    END
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.c
new file mode 100755
index 0000000000..ff87a811bb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.c
@@ -0,0 +1,253 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 35978 $   @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Filecode.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+VOID 
+MemUWriteCachelines (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+ 
+VOID 
+MemUReadCachelines (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+ 
+VOID
+MemUDummyCLRead (
+  IN       UINT32 Address
+  );
+ 
+VOID 
+MemUMFenceInstr (
+  VOID
+  );
+ 
+VOID
+MemUFlushPattern (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+ 
+VOID
+AlignPointerTo16Byte (
+  IN OUT   UINT8 **BufferPtrPtr
+  );
+ 
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+
+//----------------------------------------------------------------------------
+
+VOID 
+MemUWriteCachelines (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  UINTN Index;
+  CHAR8 *Position;
+  __m128i *Src = (void *) Pattern;
+  __m128i *Dest = (void *) (size_t)Address;
+
+  Position = (void *) Pattern;
+
+  // ssd - important: without this, the src data may get evicted from cache
+  _mm_mfence ();
+
+  for (Index = 0; Index < ClCount * 4; Index++){
+    _mm_stream_si128_fs (Dest, Src);
+    Src++;
+    Dest++;
+  }
+
+  // ssd - might not be required, but no measurable boot time impact
+  _mm_mfence ();
+}
+
+
+//----------------------------------------------------------------------------
+// MemUReadCachelines:
+//
+// Read a pattern of 72 bit times (per DQ), to test dram functionality.  The
+// pattern is a stress pattern which exercises both ISI and crosstalk.  The number
+// of cache lines to fill is dependent on DCT width mode and burstlength.
+//
+//             In: Buffer    - pointer to a buffer where read data will be stored
+//                 Address   - Physical address to be read
+//                 ClCount   - number of cachelines to be read
+
+VOID 
+MemUReadCachelines (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  UINTN Index;
+  UINT32 *Dest;
+
+  for (Index = 0; Index < ClCount * 16; Index++) {
+    Dest = (void *) &Buffer [Index * 4];
+    *Dest = __readfsdword (Address + Index * 4);
+    _mm_mfence ();
+  }
+}
+
+//----------------------------------------------------------------------------
+// MemUDummyCLRead:
+// 
+//    Perform a single cache line read from a given physical address.
+// 
+//              In: Address   - Physical address to be read
+//                  ClCount   - number of cachelines to be read
+
+//FUNC_ATTRIBUTE (noinline) 
+VOID
+MemUDummyCLRead (
+  IN       UINT32 Address
+  )
+{
+  _mm_sfence ();
+  __readfsbyte (Address);
+}
+
+//----------------------------------------------------------------------------
+
+VOID 
+MemUMFenceInstr (
+  VOID
+  )
+{
+  _mm_mfence ();
+}
+
+//----------------------------------------------------------------------------
+// MemUFlushPattern:
+// 
+//  Flush a pattern of 72 bit times (per DQ) from cache.  This procedure is used
+//  to ensure cache miss on the next read training.
+// 
+//              In: Address   - Physical address to be flushed
+//                  ClCount   - number of cachelines to be flushed
+//FUNC_ATTRIBUTE(noinline) 
+VOID
+MemUFlushPattern (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  UINTN Index;
+
+  // ssd - theory: a tlb flush is needed to avoid problems with clflush
+  __writemsr (0x20F, __readmsr (0x20F));
+
+  for (Index = 0; Index < ClCount; Index++) {
+    // mfence prevents speculative execution of the clflush
+    _mm_mfence ();
+    _mm_clflush_fs ((void *) (size_t) (Address + Index * 64));
+  }
+}
+
+//----------------------------------------------------------------------------
+
+//FUNC_ATTRIBUTE(noinline) 
+VOID
+AlignPointerTo16Byte (
+  IN OUT   UINT8 **BufferPtrPtr
+  )
+{
+  size_t Address = (size_t) *BufferPtrPtr;
+  Address += 15;
+  Address -= Address % 16;
+  *BufferPtrPtr = (void *) Address;
+}
+
+//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c
new file mode 100755
index 0000000000..31856ea630
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c
@@ -0,0 +1,685 @@
+/**
+ * @file
+ *
+ * muc.c
+ *
+ * Utility functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "cpuServices.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mu.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCacheInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_MAIN_MUC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+CONST UINT32 Pattern2[16] = {
+  0x12345678, 0x87654321, 0x23456789, 0x98765432,
+  0x59385824, 0x30496724, 0x24490795, 0x99938733,
+  0x40385642, 0x38465245, 0x29432163, 0x05067894,
+  0x12349045, 0x98723467, 0x12387634, 0x34587623
+};
+
+CONST UINT32 MaxLatPat[48] = {
+  0x6E0E3FAC, 0x0C3CFF52,
+  0x4A688181, 0x49C5B613,
+  0x7C780BA6, 0x5C1650E3,
+  0x0C4F9D76, 0x0C6753E6,
+  0x205535A5, 0xBABFB6CA,
+  0x610E6E5F, 0x0C5F1C87,
+  0x488493CE, 0x14C9C383,
+  0xF5B9A5CD, 0x9CE8F615,
+
+  0xAAD714B5, 0xC38F1B4C,
+  0x72ED647C, 0x669F7562,
+  0x5233F802, 0x4A898B30,
+  0x10A40617, 0x3326B465,
+  0x55386E04, 0xC807E3D3,
+  0xAB49E193, 0x14B4E63A,
+  0x67DF2495, 0xEA517C45,
+  0x7624CE51, 0xF8140C51,
+
+  0x4824BD23, 0xB61DD0C9,
+  0x072BCFBE, 0xE8F3807D,
+  0x919EA373, 0x25E30C47,
+  0xFEB12958, 0x4DA80A5A,
+  0xE9A0DDF8, 0x792B0076,
+  0xE81C73DC, 0xF025B496,
+  0x1DB7E627, 0x808594FE,
+  0x82668268, 0x655C7783
+};
+
+CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54};
+
+CONST UINT8 PatternJD_256[256] = {
+  0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
+  0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF,
+  0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF,
+  0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF,
+  0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7,
+  0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF,
+  0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04,
+  0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB,
+  0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB,
+  0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04,
+  0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F,
+  0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F,
+  0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF,
+  0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF,
+  0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF,
+  0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40,
+  0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD,
+  0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF,
+  0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF,
+  0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF,
+  0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE,
+  0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01,
+  0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE,
+  0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF,
+  0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF,
+  0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF,
+  0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF,
+  0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF,
+  0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10,
+  0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10,
+  0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F,
+  0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF
+};
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the (index)th UINT8
+ *   from an indicated test pattern.
+ *
+ *     @param[in] Pattern - encoding of test pattern type
+ *     @param[in] Buffer[] - buffer to be filled
+ *     @param[in] Size - Size of the buffer
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUFillTrainPattern (
+  IN       TRAIN_PATTERN Pattern,
+  IN       UINT8 Buffer[],
+  IN       UINT16 Size
+  )
+{
+  UINT8 Result;
+  UINT8 i;
+  UINT8 Mask;
+  UINT16 Index;
+  UINT16 k;
+
+  for (Index = 0; Index < Size; Index++) {
+    k = Index;
+    // get one byte from Pattern
+    switch (Pattern) {
+    case TestPattern0:
+      Result = 0xAA;
+      break;
+    case TestPattern1:
+      Result = 0x55;
+      break;
+    case TestPattern2:
+      ASSERT (Index < sizeof (Pattern2));
+      Result = ((UINT8 *)Pattern2)[Index];
+      break;
+    case TestPatternML:
+      if (Size != 6 * 64) {
+        Result = ((UINT8 *)MaxLatPat)[Index];
+      } else {
+        Result = ((UINT8 *)MaxLatPat)[Index & 0xF7];
+      }
+      break;
+    case TestPatternJD256B:
+      k >>= 1;
+      // break is not being used here because TestPatternJD256B also need
+      // to run TestPatternJD256A sequence.
+    case TestPatternJD256A:
+      k >>= 3;
+      ASSERT (k < sizeof (PatternJD_256));
+      Result = PatternJD_256[k];
+      break;
+    case TestPatternJD1B:
+      k >>= 1;
+      // break is not being used here because TestPatternJD1B also need
+      // to run TestPatternJD1A sequence.
+    case TestPatternJD1A:
+      k >>= 3;
+      i = (UINT8) (k >> 3);
+      Mask = (UINT8) (0x80 >> (k & 7));
+
+      if (i == 0) {
+        Result = 0;
+      } else {
+        Result = (UINT16)1 << (i - 1);
+      }
+
+      ASSERT (i < sizeof (PatternJD));
+      if (PatternJD[i] & Mask) {
+        Result = ~Result;
+      }
+      break;
+    case TestPattern3:
+      Result = 0x36;
+      break;
+    case TestPattern4:
+      Result = 0xC9;
+      break;
+    default:
+      Result = 0;
+      IDS_ERROR_TRAP;
+    }
+
+    // fill in the Pattern buffer
+    Buffer[Index] = Result;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function flushes cache lines
+ *
+ *     @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *     @param[in] ClCount - Number of cache lines
+ *     @param[in] Address - System Address [47:16]
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUProcIOClFlush (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  MemUSetTargetWTIO (Address, MemPtr);
+  MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount);
+  MemUResetTargetWTIO (MemPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Compares two array of bytes.
+ *
+ *     @param[in] Buffer - Measured data to compare (Data from DRAM)
+ *     @param[in] Pattern - Expected data in Cache/ROM
+ *     @param[in] ByteCount - Number of bytes to compare
+ *
+ *     @return  Pass - bitmap of comparison
+ * ----------------------------------------------------------------------------
+ */
+
+UINT16
+MemUCompareTestPattern (
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  UINT16 i;
+  UINT16 Pass;
+
+  Pass = 0xFFFF;
+  for (i = 0; i < ByteCount; i++) {
+    if (Buffer[i] != Pattern[i]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (i % 16));   // clear bit n
+    }
+    IDS_HDT_CONSOLE ("  %c", (Buffer[i] == Pattern[i]) ? 'P' : '.');
+    IDS_HDT_CONSOLE ("%02x", Buffer[i]);
+    IDS_HDT_CONSOLE ("%02x", Pattern[i]);
+  }
+  return Pass;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Address - System Address [47:16]
+ *
+ *     @return  Address - Lowest 32-bit of physical address
+ * ----------------------------------------------------------------------------
+ */
+
+UINT32
+MemUSetUpperFSbase (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  SMsr.lo = 0;
+  SMsr.hi = Address >> 16;
+  LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  return Address << 16;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function resets the target address space to Write Through IO by disabling IORRs
+ *
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUResetTargetWTIO (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+  SMsr.hi = 0;
+  SMsr.lo = 0;
+  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function sets the target range to WT IO (using an IORR overlapping
+ *       the already existing
+ *
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Address - System Address [47:16]
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUSetTargetWTIO (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  SMsr.lo = Address << 16;
+  SMsr.hi = Address >> 16;
+  LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader);           // IORR0 Base
+  SMsr.hi = 0xFFFF;
+  SMsr.lo = 0xFC000800;
+  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);          // 64MB Mask
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of 10ns cycles
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Count - Number of 10ns cycles to wait
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID
+MemUWait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  Count *= 16;
+  Count += SMsr.lo;
+  if (Count >= SMsr.lo) {
+    while (SMsr.lo < Count) {
+      LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+  } else {
+    while ((INT32) (SMsr.lo) < (INT32)Count) {
+      LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Find the entry of platform specific overriding table.
+ *
+ *      @param[in] PlatformMemoryConfiguration - Platform config table
+ *      @param[in] EntryType - Entry type
+ *      @param[in] SocketID - Physical socket ID
+ *      @param[in] ChannelID - Physical channel ID
+ *
+ *      @return  NULL - entry could not be found.
+ *      @return  Pointer - points to the entry's data.
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+VOID *
+FindPSOverrideEntry (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       PSO_ENTRY EntryType,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  )
+{
+  UINT8 *Buffer;
+
+  Buffer = PlatformMemoryConfiguration;
+  while (Buffer[0] != PSO_END) {
+    if (Buffer[0] == EntryType) {
+      if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) {
+        if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) {
+          return &Buffer[4];
+        }
+      }
+    }
+    Buffer += Buffer[1] + 2;
+  }
+  return NULL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max dimms for a given memory channel on a given
+ *  processor.  It first searches the platform override table for the max dimms
+ *  value.  If it is not provided, the AGESA default value is returned. The target
+ *  socket must be a valid present socket.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID  - ID of the processor that owns the channel
+ *     @param[in] ChannelID - Channel to get max dimms for
+ *
+ *
+ *     @return UINT8 - Max Number of Dimms for that channel
+ */
+UINT8
+GetMaxDimmsPerChannel (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  )
+{
+  UINT8  *DimmsPerChPtr;
+  UINT8  MaxDimmPerCH;
+
+  DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL;
+  }
+  // Maximum number of dimms per channel cannot be larger than its default value.
+  ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL);
+
+  return MaxDimmPerCH;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max memory channels on a given processor.
+ *  It first searches the platform override table for the max channels value.
+ *  If it is not provided, the AGESA default value is returned.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] StdHeader - Header for library and services
+ *
+ *
+ *     @return UINT8 - Max Number of Channels on that Processor
+ */
+UINT8
+GetMaxChannelsPerSocket (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  *ChannelsPerSocketPtr;
+  UINT8  MaxChannelsPerSocket;
+
+  if (IsProcessorPresent (SocketID, StdHeader)) {
+    ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0);
+    if (ChannelsPerSocketPtr != NULL) {
+      MaxChannelsPerSocket = *ChannelsPerSocketPtr;
+    } else {
+      MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET;
+    }
+    // Maximum number of channels per socket cannot be larger than its default value.
+    ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET);
+  } else {
+    MaxChannelsPerSocket = 0;
+  }
+
+  return MaxChannelsPerSocket;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the max number of chip select on a given channel of
+ *  a given processor. It first searches the platform override table for the max
+ *  chip select value. If it is not provided, the AGESA default value is returned.
+ *  The target socket must be a valid present socket.
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] ChannelID - ID of a channel
+ *
+ *
+ *     @return UINT8 - Max Number of chip selects on the channel of the Processor
+ */
+UINT8
+GetMaxCSPerChannel (
+  IN      PSO_TABLE *PlatformMemoryConfiguration,
+  IN      UINT8 SocketID,
+  IN      UINT8 ChannelID
+  )
+{
+  UINT8  *CSPerSocketPtr;
+  UINT8  MaxCSPerChannel;
+
+  CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID);
+  if (CSPerSocketPtr != NULL) {
+    MaxCSPerChannel = *CSPerSocketPtr;
+  } else {
+    MaxCSPerChannel = MAX_CS_PER_CHANNEL;
+  }
+  // Max chip select per channel cannot be larger than its default value
+  ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL);
+
+  return MaxCSPerChannel;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the index of the first Dimm SPD structure for a
+ *  given processor socket. It checks the Max Dimms per channel for every memory
+ *  channel on every processor up to the current one, and adds them together.
+ *
+ *      This function may also be used to calculate the maximum dimms per system
+ *  by passing the total number of dimm sockets
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] StdHeader - Header for library and services
+ *
+ *     @return UINT8 - SPD Index
+ */
+UINT8
+GetSpdSocketIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 SpdSocketIndex;
+  UINT8 Socket;
+  UINT8 Channel;
+  UINT8  MaxChannelsPerSocket;
+
+  SpdSocketIndex = 0;
+  for (Socket = 0; Socket < SocketID; Socket++) {
+    MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader);
+    for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
+      SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel);
+    }
+  }
+  return SpdSocketIndex;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function returns the index of the first Dimm SPD structure for a
+ *  given channel relative to the processor socket. It checks the Max Dimms per
+ *  channel for every memory channel on that processor up to the current one,
+ *  and adds them together.
+ *
+ *      This function may also be used to calculate the maximum dimms per system
+ *  by passing the total number of DIMM sockets
+ *
+ *     @param[in] PlatformMemoryConfiguration - Platform config table
+ *     @param[in] SocketID - ID of the processor
+ *     @param[in] ChannelID - ID of the Channel
+ *     @param[in] StdHeader - Header for library and services
+ *
+ *     @return UINT8 - SPD Index
+ */
+UINT8
+GetSpdChannelIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 SpdChannelIndex;
+  UINT8 Channel;
+
+  SpdChannelIndex = 0;
+  ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader))
+  for (Channel = 0; Channel < ChannelID; Channel++) {
+    SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel);
+  }
+  return SpdChannelIndex;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the upper 32 bits mask for variable MTRR based on
+ *     the CPU_LOGICAL_ID.
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *     @param[in]       StdHeader - Header for library and services
+ *
+ *     @return          UINT32 - MTRR mask for upper 32 bits
+ *
+ */
+UINT32
+GetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempNotCare;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  CACHE_INFO *CacheInfoPtr;
+
+  GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &TempNotCare, StdHeader);
+  return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c
new file mode 100755
index 0000000000..05d2272e66
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -0,0 +1,209 @@
+/**
+ * @file
+ *
+ * mnParTrainc32.c
+ *
+ * Feature which performs Memory DQS training on each node with each node training
+ * its own memory through code running on a core in the associated processor.
+ * This way memory can be trained in parallel by more than one processor.
+ *
+ * This file contains the C32 specific parallel training function.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnc32.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+);
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the training function which set up the environment for remote
+ * training on the ap and launches the remote routine.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Launch training on AP successfully.
+ *     @return          FALSE - Fail to launch training on AP.
+ */
+BOOLEAN
+MemFParallelTrainingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  DIE_STRUCT *MCTPtr;
+  REMOTE_TRAINING_ENV *EnvPtr;
+  AP_TASK TrainingTask;
+  UINT8 Socket;
+  UINT8 Module;
+  UINT8 APCore;
+  UINT8 p;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 BspSocket;
+  UINT32 BspModule;
+  UINT32 BspCore;
+  AGESA_STATUS Status;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT16 MctDataSize;
+  StdHeader = &(NBPtr->MemPtr->StdHeader);
+  MCTPtr = NBPtr->MCTPtr;
+  Socket = MCTPtr->SocketId;
+  Module = MCTPtr->DieId;
+
+  //
+  // Allocate buffer for REMOTE_TRAINING_ENV
+  //
+  MctDataSize = MAX_DCTS_PER_NODE_C32 * (
+                  sizeof (DCT_STRUCT) + (
+                    MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                  )
+                );
+  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
+    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
+
+    //
+    // Setup Remote training environment
+    //
+    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
+    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
+    }
+    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
+    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockC32;
+    EnvPtr->FeatPtr = NBPtr->FeatPtr;
+    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
+    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
+    EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
+    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
+    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
+    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
+
+    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
+
+    //
+    // Get Socket, Core of the BSP
+    //
+    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
+    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
+    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
+
+    //
+    // Set up the remote task structure
+    //
+    TrainingTask.DataTransfer.DataPtr = EnvPtr;
+    TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4;
+    TrainingTask.DataTransfer.DataTransferFlags = 0;
+    TrainingTask.ExeFlags = 0;
+    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
+
+    //
+    // Get Target AP Core
+    //
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    APCore = (UINT8) (LowCore & 0x000000FF);
+
+    //
+    // Launch Remote Training
+    //
+    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
+
+    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
+
+    return TRUE;
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
+    return FALSE;
+  }
+}
+
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+  )
+{
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+
+  MemNInitNBDataC32 (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c
new file mode 100755
index 0000000000..8a32fbcad6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c
@@ -0,0 +1,722 @@
+/**
+ * @file
+ *
+ * mns3c32.c
+ *
+ * C32 memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mnc32.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mnS3c32.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNS3C32_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstC32 (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3SetSpecialPCIRegC32 (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3ExitSelfRefRegC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncC32[] = {
+  {MemNS3GetCSRNb, MemNS3SetCSRNb},
+  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegC32},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorC32[] = {
+  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
+  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
+  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
+  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefC32 = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorC32) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorC32,
+  NULL
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorC32[] = {
+   // DCT 0
+  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA4,  0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 322
+  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 263
+  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+   // DCT 1
+  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 322
+  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 263
+  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore F2x[1,0]94 right before exit self refresh
+  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefC32 = {
+  0,
+  (sizeof (S3CPciPreSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPreSelfDescriptorC32,
+  PciSpecialCaseFuncC32
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorC32[] = {
+  // DCT0
+  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+
+    // DCT1
+  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+
+  // Restore scrubber related registers after restoring training related registers
+  {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefC32 = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorC32,
+  PciSpecialCaseFuncC32
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorC32[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
+  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefC32 = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorC32) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorC32,
+  NULL
+};
+
+VOID *MemS3RegListC32[] = {
+  (VOID *)&S3PciPreSelfRefC32,
+  NULL,
+  (VOID *)&S3CPciPreSelfRefC32,
+  (VOID *)&S3CPciPostSelfRefC32,
+  (VOID *)&S3MSRPreSelfRefC32,
+  NULL,
+  NULL,
+  NULL
+};
+
+CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
+};
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *     @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemS3ResumeConstructNBBlockC32 (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  InitNBRegTableC32 (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for C32
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[PCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_C32 + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CPCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_C32 + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[MSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_C32 + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CMSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_C32 + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      none
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstC32 (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListC32) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListC32[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListC32[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device register list error
+  return AGESA_FATAL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetSpecialPCIRegC32 (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (Address.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_C32);
+    // Save the value in the heap at appropriate offset based on the index
+    // of the target register in the special case array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) {
+        if (SpecialCasePCIRegC32[i] == Address.Address.Register) {
+          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
+        }
+      }
+    }
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
+ *     @param[in,out]  *StdHeader - Config handle for library and services.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3ExitSelfRefRegC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  PCI_ADDR PciAddr;
+  UINT32 Value;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+  PciAddr.Address.Function = 2;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (PciAddr.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_C32);
+    // Restore the value one by one in the sequence of the special case register array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) {
+        PciAddr.Address.Register = SpecialCasePCIRegC32[i];
+        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
+        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h
new file mode 100755
index 0000000000..a42d0033f3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mnS3c32.h
+ *
+ * S3 resume memory related function for C32.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MNS3C32_H_
+#define _MNS3C32_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of C32
+typedef enum {
+  PCI_LST_ESR_C32,  ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_C32,      ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_C32, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_C32,     ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_C32,  ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_C32,      ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_C32, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_C32      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDC32;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3C32_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
new file mode 100755
index 0000000000..e861ad236b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c
@@ -0,0 +1,454 @@
+/**
+ * @file
+ *
+ * mnc32.c
+ *
+ * Common Northbridge  functions for C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 13446 $ @e \$Date: 2009-05-12 04:57:49 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnc32.h"
+#include "mu.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNC32_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @return     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 SpdSocketIndex;
+  UINT8 SpdChannelIndex;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT);
+  }
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
+    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
+    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
+  }
+
+  MemNInitNBDataC32 (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  //
+  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
+  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
+  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
+  // dimm types(QR or not) are known. This is done in the Technology block constructor.
+  //
+  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
+  // This will facilitate modifications due to some processors that might
+  // map the DCT-CHANNEL differently.
+  //
+  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
+  //
+  // Traverse the Dct/Channel structures
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) {
+      //
+      // Calculate the number of Dimms on this channel using the
+      //   die/dct/channel to Socket/channel conversion.
+      //
+      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            NBPtr->MCTPtr->SocketId,
+                                            MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel),
+                                            &MemPtr->StdHeader);
+      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
+    }
+  }
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  InitNBRegTableC32 (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_C32;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_256B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR800_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0x1FF;
+  NBPtr->DefDctSelIntLvAddr = 3;
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
+  NBPtr->InitializeMCT = MemNInitializeMctNb;
+  NBPtr->FinalizeMCT = MemNFinalizeMctC32;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdC32;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternC32;
+  NBPtr->ReadPattern = MemNReadPatternC32;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->StitchMemory = MemNStitchMemoryNb;
+  NBPtr->AutoConfig = MemNAutoConfigC32;
+  NBPtr->PlatformSpec = MemNPlatformSpecNb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->DisableDCT = MemNDisableDCTNb;
+  NBPtr->StartupDCT = MemNStartupDCTNb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
+  NBPtr->ChangeNbFrequency = MemNDefFalseNb;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
+  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
+  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingC32;
+  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->OtherTiming = MemNOtherTimingC32;
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
+  NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
+  NBPtr->TrainingFlow = MemNTrainingFlowNb;
+  MemNInitNBDataNb (NBPtr);
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
+  NBPtr->BrdcstSet = MemNBrdcstSetNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitC32;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
+  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompC32;
+  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecC32;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitC32;
+  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->CSPerChannel = MemNCSPerChannelNb;
+  NBPtr->CSPerDelay = MemNCSPerDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
+  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
+
+  NBPtr->IsSupported[SetSpareEn] = TRUE;
+  NBPtr->IsSupported[CheckSpareEn] = TRUE;
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+  NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
+  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
+  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
+  NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
+  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
+  NBPtr->IsSupported[CheckODTControls] = TRUE;
+  NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
+  NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
+
+  NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+VOID
+MemNInitDefaultsC32 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
+  //
+
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
+      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
+    }
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
+  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
+  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h
new file mode 100755
index 0000000000..803e56a8b4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * mnc32.h
+ *
+ * Northbridge C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNC32_H_
+#define _MNC32_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CHANNELS_PER_SOCKET_C32    2
+#define MAX_DCTS_PER_NODE_C32          2
+#define MAX_CHANNELS_PER_DCT_C32       1
+#define MAX_NODES_SUPPORTED_C32        8
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemConstructNBBlockC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitNBDataC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDefaultsC32 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNFinalizeMctC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSendMrsCmdC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAutoConfigC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNOtherTimingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitPhyCompC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWritePatternC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+InitNBRegTableC32 (
+  IN OUT   TSEFO NBRegTable[]
+  );
+
+UINT8
+MemNGetSocketRelativeChannelC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  );
+
+BOOLEAN
+MemNIsIdSupportedC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+VOID
+MemNBeforeDramInitC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNEnDLLShutDownC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNCmnGetSetFieldC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNBeforePlatformSpecC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNBeforeDQSTrainingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNForceLvDimmVoltageC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *MemMainPtr
+  );
+
+#endif  /* _MNC32_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c
new file mode 100755
index 0000000000..fad96bc06f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c
@@ -0,0 +1,405 @@
+/**
+ * @file
+ *
+ * mndctc32.c
+ *
+ * Northbridge DCT support for C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mnc32.h"
+#include "merrhdl.h"
+#include "cpuFamRegisters.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNDCTC32_FILECODE
+
+extern BUILD_OPT_CFG UserOptions;
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_ERROR may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
+ *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
+ */
+
+BOOLEAN
+MemNAutoConfigC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 PowerDownMode;
+  UINT32 Value32;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  //======================================================================
+  // Build Dram Control Register Value (F2x78)
+  //======================================================================
+  //
+  //It is recommended that these bits remain in the default state.
+  //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5);
+
+  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
+
+  //======================================================================
+  // Build Dram Config Lo Register Value
+  //======================================================================
+  //
+
+  if (MCTPtr->Status[SbParDimms]) {
+    //
+    // SbParDimms should be set for all DDR3 RDIMMS
+    // Cannot turn off ParEn for DDR3
+    //
+    //@attention - add debug option for parity control
+    MemNSetBitFieldNb (NBPtr, BFParEn, 1);
+  }
+
+  if (MCTPtr->GangedMode) {
+    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
+
+  if (!MCTPtr->Status[SbRegistered]) {
+    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
+  }
+
+  if (MCTPtr->Status[SbEccDimms]) {
+    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
+  }
+
+  //======================================================================
+  // Build Dram Config Hi Register Value
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
+
+  if (MCTPtr->Status[SbRegistered]) {
+    if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) {
+      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
+    }
+  }
+
+  if (RefPtr->EnableBankSwizzle) {
+    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
+  }
+
+  if (DCTPtr->Timings.DimmQrPresent) {
+    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
+      MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1);
+    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
+      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
+    }
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
+  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
+  //======================================================================
+  // Build Dram Config Misc Register Value
+  //======================================================================
+  //
+  if (MCTPtr->Status[SbRegistered]) {
+    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
+      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
+    }
+  }
+  //======================================================================
+  // Build Dram Config Misc 2 Register Value
+  //======================================================================
+  //
+  //
+  // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms
+  //
+  if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) {
+    MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1);
+  }
+  //
+  // DTaxTxFifpWrDly
+  //
+  Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
+  if ((Value32 >= 2) && (Value32 <= 5)) {
+    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32));
+  }
+
+  //
+  // ProgOdtEn
+  //
+  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
+    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0);
+  }
+  //
+  // OdtSwizzle
+  //
+  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) {
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode == 1) {
+      MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
+    }
+  }
+
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends an MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendMrsCmdC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSwapBitsNb (NBPtr);
+
+  IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n",
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM init
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDramInitC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      //Set PllLockTime and DllLockTime to default.
+      MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
+      MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
+      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Enable DLL Shut down
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNEnDLLShutDownC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN DllShutDownEn;
+
+  DllShutDownEn = TRUE;
+  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
+
+  if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
+    if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) {
+      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+        MemNSwitchDCTNb (NBPtr, Dct);
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
+          MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
+          MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
+        }
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Workaround for erratum 322 and 263
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNBeforePlatformSpecC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // Errata 263
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
+  }
+
+  // Errata 322
+  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
+  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
+  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
+  //    greater than or equal to 011b (DDR-800 and higher),
+  //    then write 00000080h to F2x[1,0]9C_xD02E001,
+  //    else write 00000090h to F2x[1,0]9C_xD02E001.
+  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    Force LvDimm voltage to 1.5V for D0 part
+ *
+ *     @param[in,out]   *NBPtr       - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemMainPtr  - Pointer to MEM_MAIN_DATA_BLOCK
+ *
+ *     @return    TRUE
+ */
+BOOLEAN
+MemNForceLvDimmVoltageC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *MemMainPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *ParameterPtr;
+  MEM_SHARED_DATA *mmSharedPtr;
+
+  mmSharedPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->mmSharedPtr;
+  ParameterPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->MemPtr->ParameterListPtr;
+
+  if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D0) != 0) {
+    IDS_HDT_CONSOLE ("\n\nC32 D0 on socket %d.\n", NBPtr->MCTPtr->SocketId);
+    if ((1 & mmSharedPtr->VoltageMap) != 0) {
+      IDS_HDT_CONSOLE ("\nDimms are 1.5V capable. Adjust voltage to 1.5V.\n");
+      ParameterPtr->DDR3Voltage = VOLT1_5;
+    } else {
+      if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_LVDIMM_VOLT1_5_SUPPORT, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) {
+        IDS_HDT_CONSOLE ("\nDimms are not 1.5V capable. Adjust voltage to 1.5V based on customer's choice.\n\n");
+        ParameterPtr->DDR3Voltage = VOLT1_5;
+      } else {
+        IDS_HDT_CONSOLE ("\nDimms are not 1.5V capable. Do not adjust voltage based on customer's choice.\n\n");
+        PutEventLog (AGESA_FATAL, MEM_ERROR_VDDIO_UNSUPPORTED, NBPtr->Node, 0, 0, 0, &(NBPtr->MemPtr->StdHeader));
+        SetMemError (AGESA_FATAL, NBPtr->MCTPtr);
+        ASSERT (FALSE);
+      }
+    }
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
new file mode 100755
index 0000000000..e56e2ab37c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * mnflowc32.c
+ *
+ * C32 initializer for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mnc32.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNFLOWC32_FILECODE
+/* features */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the platform specific block
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
+ *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
+ */
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 f;
+  UINT8 ErrUnSuppFFCount;
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
+      ErrUnSuppFFCount = 0;
+      for (f = 0; f < MAX_FF_TYPES; f++) {
+        ASSERT (memPlatSpecFFInstalledC32[f] != NULL);
+        if (memPlatSpecFFInstalledC32[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
+          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
+        } else {
+          break;
+        }
+      }
+      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
+        return FALSE; // No FF types are supported
+      }
+    }
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c
new file mode 100755
index 0000000000..f75ef11389
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c
@@ -0,0 +1,133 @@
+/**
+ * @file
+ *
+ * mnidendimmc32.c
+ *
+ * C32 northbridge constructor for dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnc32.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Ganged = FALSE;
+  InitNBRegTableC32 (NBPtr->NBRegTable);
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32;
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c
new file mode 100755
index 0000000000..1631cca5da
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c
@@ -0,0 +1,150 @@
+/**
+ * @file
+ *
+ * mnmctc32.c
+ *
+ * Northbridge C32 MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnc32.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNMCTC32_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNFinalizeMctC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+  UINT16 Speed;
+  UINT32 ExtMctCfgLoRegVal;
+
+  MemPtr = NBPtr->MemPtr;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);
+
+  ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
+  ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;
+
+  ExtMctCfgLoRegVal &= 0x0FFFFFFF;
+  if (Speed == DDR667_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x40000000;
+  } else if (Speed == DDR800_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x50000000;
+  } else if (Speed == DDR1066_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x60000000;
+  } else if (Speed == DDR1333_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x80000000;
+  } else {
+    ExtMctCfgLoRegVal |= 0x90000000;
+  }
+  MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);
+
+  if (NBPtr->Node == BSP_DIE) {
+    if (!NBPtr->ClToNbFlag) {
+      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
+      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+
+    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
+    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c
new file mode 100755
index 0000000000..22e6bab12e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c
@@ -0,0 +1,235 @@
+/**
+ * @file
+ *
+ * mnotc32.c
+ *
+ * Northbridge Non-SPD timings for C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnc32.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNOTC32_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNSetOtherTimingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+STATIC
+MemNGetODTDelaysC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNOtherTimingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSwitchDCTNb (NBPtr, 0);
+  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
+    MemNSetOtherTimingC32 (NBPtr);
+    MemNPowerDownCtlNb (NBPtr);
+    MemNEnDLLShutDownC32 (NBPtr);
+  }
+
+  MemNSwitchDCTNb (NBPtr, 1);
+  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
+    MemNSetOtherTimingC32 (NBPtr);
+    MemNPowerDownCtlNb (NBPtr);
+    MemNEnDLLShutDownC32 (NBPtr);
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings  in PCI registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNSetOtherTimingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+
+  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the ODT delays
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+UINT32
+STATIC
+MemNGetODTDelaysC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Ld;
+  UINT32 ODTDelays;
+  //
+  // On revision D processors, the BIOS must additionally configure the ODT pattern
+  // and the ODT switching delays.
+  //
+  // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
+  //     -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
+  //     -Value of 2, BL = 4 else assume BL=8.
+  //     -Initialize ODTDelays based on BL value
+  //     -WrOdtOnDuration [14:12] = BL / 2 + 1
+  //     -WrOdtTrnOnDly [10:8] = 0
+  //     -RdOdtOnDuration [6:4] = BL / 2 + 1
+  //
+  ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
+
+  // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
+  // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
+  Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
+  if (Ld < 0) {
+    Ld = 0;
+  }
+  if (Ld > 7) {
+    Ld = 7;
+  }
+  ODTDelays += Ld;
+  return ODTDelays;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNPowerDownCtlC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+
+  // we can't enable powerdown mode when doing WL
+  if (RefPtr->EnablePowerDown) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c
new file mode 100755
index 0000000000..d9d2318f51
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c
@@ -0,0 +1,217 @@
+/**
+ * @file
+ *
+ * mnphyc32.c
+ *
+ * Northbridge Phy support for C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mnc32.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNPHYC32_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
+  CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
+  CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
+  CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
+  UINT8 i;
+  UINT8 j;
+  UINT8 CurrDct;
+  CurrDct = NBPtr->Dct;
+  // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // DisAutoComp will be cleared after Dram init has completed
+  //
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+  MemUWait10ns (500, NBPtr->MemPtr);
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+
+  // 3. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
+  // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
+  //
+  // 4. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
+  // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
+  // D3Cmp2PCal].
+  //
+  j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
+  i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  ASSERT (j <= 3);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
+
+  if ((NBPtr->ChannelPtr->Dimms == 3) &&
+      ((NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) ||
+       (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY))) {
+    //
+    // Special Case for 3 Dimms @ 800MHz or 1066MHz
+    //
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 1);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 1);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 1);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 1);
+  } else {
+    ASSERT (i <= 3);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
+  }
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDQSTrainingC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 TestAddrRJ16;
+  UINT32 RealAddr;
+
+  MemTBeginTraining (NBPtr->TechPtr);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+        if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
+
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
+
+          MemUDummyCLRead (RealAddr);
+
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
+          MemUWait10ns (60, NBPtr->MemPtr);   // Wait 300ns
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
+          MemUWait10ns (400, NBPtr->MemPtr);  // Wait 2us
+          MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
+          break;
+        }
+      }
+    }
+    if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
+      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
+      }
+      if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
+      }
+    }
+  }
+
+  MemTEndTraining (NBPtr->TechPtr);
+
+  MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c
new file mode 100755
index 0000000000..60c5c3f0bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c
@@ -0,0 +1,62 @@
+/**
+ * @file
+ *
+ * mnprotoc32.c
+ *
+ * Northbridge support functions for Errata and early samples
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 7735 $ @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+
+#include "AGESA.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNPROTOC32_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c
new file mode 100755
index 0000000000..6469da7cd7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c
@@ -0,0 +1,571 @@
+/**
+ * @file
+ *
+ * mnregc32.c
+ *
+ * Common Northbridge register related functions for C32
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/C32)
+ * @e \$Revision: 13446 $ @e \$Date: 2009-05-12 04:57:49 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnc32.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_C32_MNREGC32_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemNIsIdSupportedC32
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a C32.
+ *     @return          FALSE - This node is not a C32.
+ *
+ */
+BOOLEAN
+MemNIsIdSupportedC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+  if ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *      This function calculates the memory channel index relative to the
+ *      socket, taking the Die number, the Dct, and the channel.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Dct
+ *     @param[in] Channel
+ *
+ */
+UINT8
+MemNGetSocketRelativeChannelC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  )
+{
+  return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_C32) + Dct);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field to be programmed
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNCmnGetSetFieldC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  TSEFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT8 IsLinked;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = (UINT8) TSEFO_TYPE (Address);
+      IsLinked = (UINT8) TSEFO_LINKED (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
+          Address |= 0x0100;
+        }
+      }
+
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+        IsLinked = 0;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+      if (Type == NB_ACCESS) {
+        PciAddr.AddressValue = Address;
+        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+        Address = PciAddr.AddressValue;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else if (Type == DCT_EXTRA) {
+        MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+        MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        } else if (Type == DCT_EXTRA) {
+          MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+          MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        } else {
+          IDS_ERROR_TRAP;
+        }
+        if (IsLinked) {
+          MemNCmnGetSetFieldC32 (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+        if (IsLinked) {
+          Value |= MemNCmnGetSetFieldC32 (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   NBRegTable[]  - Pointer to the bit field data structure
+ *
+ */
+
+VOID
+InitNBRegTableC32 (
+  IN OUT   TSEFO NBRegTable[]
+  )
+{
+  UINT16 i;
+  for (i = 0; i < BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31,  0, BFDctExtraOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31,  0, BFExtMctCfgLoReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFF3X188B8);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  7,  7, BFProgOdtEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x180, 31, 0, BFPhyRODTCSLow);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x181, 31, 0, BFPhyRODTCSHigh);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x182, 31, 0, BFPhyWODTCSLow);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x183, 31, 0, BFPhyWODTCSHigh);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
+
+  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
+  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
+  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
+
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c
new file mode 100755
index 0000000000..0feabbd9ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -0,0 +1,210 @@
+/**
+ * @file
+ *
+ * mnParTrainDa.c
+ *
+ * Feature which performs Memory DQS training on each node with each node training
+ * its own memory through code running on a core in the associated processor.
+ * This way memory can be trained in parallel by more than one processor.
+ *
+ * This file contains the Deerhound specific parallel training function.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/HCTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+);
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the training function which set up the environment for remote
+ * training on the ap and launches the remote routine.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Launch training on AP successfully.
+ *     @return          FALSE - Fail to launch training on AP.
+ */
+BOOLEAN
+MemFParallelTrainingDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  DIE_STRUCT *MCTPtr;
+  REMOTE_TRAINING_ENV *EnvPtr;
+  AP_TASK TrainingTask;
+  UINT8 Socket;
+  UINT8 Module;
+  UINT8 APCore;
+  UINT8 p;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 BspSocket;
+  UINT32 BspModule;
+  UINT32 BspCore;
+  AGESA_STATUS Status;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT16 MctDataSize;
+  StdHeader = &(NBPtr->MemPtr->StdHeader);
+  MCTPtr = NBPtr->MCTPtr;
+  Socket = MCTPtr->SocketId;
+  Module = MCTPtr->DieId;
+
+  //
+  // Allocate buffer for REMOTE_TRAINING_ENV
+  //
+  MctDataSize = MAX_DCTS_PER_NODE_DA * (
+                  sizeof (DCT_STRUCT) + (
+                    MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                  )
+                );
+  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
+    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
+
+    //
+    // Setup Remote training environment
+    //
+    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
+    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
+    }
+    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
+    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDA;
+    EnvPtr->FeatPtr = NBPtr->FeatPtr;
+    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
+    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
+    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
+    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
+    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
+
+    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
+
+    //
+    // Get Socket, Core of the BSP
+    //
+    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
+    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
+    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
+
+    //
+    // Set up the remote task structure
+    //
+    TrainingTask.DataTransfer.DataPtr = EnvPtr;
+    TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4;
+    TrainingTask.DataTransfer.DataTransferFlags = 0;
+    TrainingTask.ExeFlags = 0;
+    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
+
+    //
+    // Get Target AP Core
+    //
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    APCore = (UINT8) (LowCore & 0x000000FF);
+
+    //
+    // Launch Remote Training
+    //
+    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
+
+    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
+    return TRUE;
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
+    return FALSE;
+  }
+}
+
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+  )
+{
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+
+  MemNInitNBDataDA (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c
new file mode 100755
index 0000000000..1e4e328d32
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c
@@ -0,0 +1,739 @@
+/**
+ * @file
+ *
+ * mns3da.c
+ *
+ * DA memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mnda.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mnS3da.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNS3DA_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstDA (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3SetSpecialPCIRegDA (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3ExitSelfRefRegDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncDA[] = {
+  {MemNS3GetCSRNb, MemNS3SetCSRNb},
+  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDA},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDA[] = {
+  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
+  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
+  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
+  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
+  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDA = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorDA) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorDA,
+  NULL
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDA[] = {
+   // DCT 0
+  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 322
+  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 263
+  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  // Dll regulator disable
+  {{2, 2, 1}, DCT0,   BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+   // DCT 1
+  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 322
+  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 263
+  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Dll regulator disable
+  {{2, 2, 1}, DCT1,   BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore F2x[1,0]94 right before exit self refresh
+  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDA = {
+  0,
+  (sizeof (S3CPciPreSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPreSelfDescriptorDA,
+  PciSpecialCaseFuncDA
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDA[] = {
+  // DCT0
+  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+    // DCT1
+  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // DllShutDown
+  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore scrubber related registers after restoring training related registers
+  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDA = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorDA,
+  PciSpecialCaseFuncDA
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDA[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
+  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDA = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorDA) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorDA,
+  NULL
+};
+
+VOID *MemS3RegListDA[] = {
+  (VOID *)&S3PciPreSelfRefDA,
+  NULL,
+  (VOID *)&S3CPciPreSelfRefDA,
+  (VOID *)&S3CPciPostSelfRefDA,
+  (VOID *)&S3MSRPreSelfRefDA,
+  NULL,
+  NULL,
+  NULL
+};
+
+CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
+};
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *      @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemS3ResumeConstructNBBlockDA (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  InitNBRegTableDA (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDA;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDA;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDA;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)) * sizeof (UINT32);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for DA
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      none
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstDA (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListDA) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListDA[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListDA[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device register list error
+  return AGESA_FATAL;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *      @return         none
+ */
+VOID
+STATIC
+MemNS3SetSpecialPCIRegDA (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (Address.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_DA);
+    // Save the value in the heap at appropriate offset based on the index
+    // of the target register in the special case array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) {
+        if (SpecialCasePCIRegDA[i] == Address.Address.Register) {
+          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
+        }
+      }
+    }
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
+ *     @param[in,out]  *StdHeader - Config handle for library and services.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3ExitSelfRefRegDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  PCI_ADDR PciAddr;
+  UINT32 Value;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+  PciAddr.Address.Function = 2;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (PciAddr.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_DA);
+    // Restore the value one by one in the sequence of the special case register array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) {
+        PciAddr.Address.Register = SpecialCasePCIRegDA[i];
+        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
+        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h
new file mode 100755
index 0000000000..cc65af658f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mnS3da.h
+ *
+ * S3 resume memory related function for DA.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MNS3DA_H_
+#define _MNS3DA_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of DA
+typedef enum {
+  PCI_LST_ESR_DA,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_DA,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_DA,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_DA,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_DA,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_DA,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_DA,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_DA,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDDA;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3DA_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
new file mode 100755
index 0000000000..3c6242b502
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c
@@ -0,0 +1,460 @@
+/**
+ * @file
+ *
+ * mnda.c
+ *
+ * Common Northbridge functions for DA
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "mu.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNDA_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   (UINT32) 0x20000000
+#define CHANNEL_SELECT  (UINT32) 0x10000000
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @return     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 SpdSocketIndex;
+  UINT8 SpdChannelIndex;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
+  }
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
+    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
+  }
+
+  MemNInitNBDataDA (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  //
+  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
+  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
+  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
+  // dimm types(QR or not) are known. This is done in the Technology block constructor.
+  //
+  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
+  // This will facilitate modifications due to some processors that might
+  // map the DCT-CHANNEL differently.
+  //
+  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
+  //
+  // Traverse the Dct/Channel structures
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
+      //
+      // Calculate the number of Dimms on this channel using the
+      //   die/dct/channel to Socket/channel conversion.
+      //
+      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            NBPtr->MCTPtr->SocketId,
+                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
+                                            &MemPtr->StdHeader);
+      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
+    }
+  }
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT32 i;
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  InitNBRegTableDA (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_72B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR800_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0xFF;
+  NBPtr->DefDctSelIntLvAddr = 3;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->InitializeMCT = MemNInitializeMctNb;
+  NBPtr->FinalizeMCT = MemNFinalizeMctDA;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternDA;
+  NBPtr->ReadPattern = MemNReadPatternDA;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->StitchMemory = MemNStitchMemoryNb;
+  NBPtr->AutoConfig = memNAutoConfigDA;
+  NBPtr->PlatformSpec = MemNPlatformSpecNb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->DisableDCT = MemNDisableDCTNb;
+  NBPtr->StartupDCT = MemNStartupDCTNb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
+  NBPtr->ChangeNbFrequency = MemNDefFalseNb;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
+  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
+  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
+  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->OtherTiming = MemNOtherTimingDA;
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
+  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->TrainingFlow = MemNTrainingFlowNb;
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  MemNInitNBDataNb (NBPtr);
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
+  NBPtr->BrdcstSet = MemNBrdcstSetNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA;
+  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
+  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
+  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->CSPerChannel = MemNCSPerChannelNb;
+  NBPtr->CSPerDelay = MemNCSPerDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
+  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
+  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
+
+  NBPtr->IsSupported[SetSpareEn] = TRUE;
+  NBPtr->IsSupported[CheckSpareEn] = TRUE;
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[Check1GAlign] = TRUE;
+  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
+  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
+  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
+  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
+  NBPtr->IsSupported[CheckDllStdBy] = TRUE;
+  NBPtr->IsSupported[CheckDynamicDramTerm] = TRUE;
+  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->IsSupported[CheckDllRegDis] = TRUE;
+  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+VOID
+MemNInitDefaultsDA (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
+      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
+    }
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
+  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
+  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h
new file mode 100755
index 0000000000..3109cdd761
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h
@@ -0,0 +1,193 @@
+/**
+ * @file
+ *
+ * mnda.h
+ *
+ * Northbridge DA
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNDA_H_
+#define _MNDA_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CHANNELS_PER_SOCKET_DA    2
+#define MAX_DCTS_PER_NODE_DA          2
+#define MAX_CHANNELS_PER_DCT_DA       1
+#define MAX_NODES_SUPPORTED_DA        8
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructNBBlockDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitNBDataDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDefaultsDA (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNFinalizeMctDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSendMrsCmdDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+memNAutoConfigDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNOtherTimingDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWritePatternDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemPNodeMemBoundaryDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT32 *NodeSysLimit
+  );
+
+VOID
+InitNBRegTableDA (
+  IN OUT   TSEFO NBRegTable[]
+  );
+
+VOID
+MemNBeforeDramInitDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNBeforePlatformSpecDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNIsIdSupportedDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+BOOLEAN
+MemNChangeAvgValue3DA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNChangeAvgValue8DA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNEnDLLShutDownDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNCmnGetSetFieldDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNCapSpeedBatteryLifeDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+#endif  /* _MNDA_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c
new file mode 100755
index 0000000000..da8ed6c4c6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c
@@ -0,0 +1,459 @@
+/**
+ * @file
+ *
+ * mndctda.c
+ *
+ * Northbridge DA DCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mnda.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuRegisters.h"
+#include "mport.h"
+#include "F10PackageType.h"
+#define FILECODE PROC_MEM_NB_DA_MNDCTDA_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM init
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDramInitDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+
+  //Setting the reset value of Phy DLL standby and shutdown registers.
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      //Set PllLockTime and DllLockTime to default.
+      MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
+      MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
+      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
+
+      //Clear PHY PLL Control Register before doing fence training and reset DLL
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0x00002000);
+      MemNSetBitFieldNb (NBPtr, BFPhyDLLControl, 0);
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
+ */
+
+BOOLEAN
+memNAutoConfigDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  //======================================================================
+  // Build Dram Control Register Value (F2x78)
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
+
+  //======================================================================
+  // Build Dram Config Lo Register Value
+  //======================================================================
+  //
+
+  if (MCTPtr->Status[SbParDimms]) {
+    //
+    // SbParDimms should be set for all DDR3 RDIMMS
+    // Cannot turn off ParEn for DDR3
+    //
+    //@attention - add debug option for parity control
+    MemNSetBitFieldNb (NBPtr, BFParEn, 1);
+  }
+
+
+  if (MCTPtr->GangedMode) {
+    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
+
+  if (!MCTPtr->Status[SbRegistered]) {
+    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
+  }
+
+  if (MCTPtr->Status[SbEccDimms]) {
+    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
+  }
+
+ //======================================================================
+  // Build Dram Config Hi Register Value
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
+
+  if (MCTPtr->Status[SbRegistered]) {
+    if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) {
+      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
+    }
+  }
+
+  if (RefPtr->EnableBankSwizzle) {
+    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
+  }
+
+  if (DCTPtr->Timings.DimmQrPresent) {
+    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
+      MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1);
+    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
+      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
+    }
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
+
+  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
+
+  //======================================================================
+  // Build Dram Config Misc Register Value
+  //======================================================================
+  //
+  MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
+  // For DDR3 Registered Dimms
+  if (MCTPtr->Status[SbRegistered]) {
+    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
+      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
+    }
+  }
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends an MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendMrsCmdDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSwapBitsNb (NBPtr);
+
+  IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n",
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Workaround for erratum 322 and 263
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNBeforePlatformSpecDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // Errata 263
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
+  }
+
+  // Errata 322
+  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
+  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
+  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
+  //    greater than or equal to 011b (DDR-800 and higher),
+  //    then write 00000080h to F2x[1,0]9C_xD02E001,
+  //    else write 00000090h to F2x[1,0]9C_xD02E001.
+  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Change Average Value of 3
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+BOOLEAN
+MemNChangeAvgValue3DA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/**
+ *
+ *
+ *   Change Average Value of 8
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+BOOLEAN
+MemNChangeAvgValue8DA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C1) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Enable DLL Shut down
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNEnDLLShutDownDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN DllShutDownEn;
+
+  DllShutDownEn = TRUE;
+  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
+
+  if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
+        MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
+        MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function caps speed based on batter life check.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+VOID
+MemNCapSpeedBatteryLifeDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT16 SupportedFreq[] = {
+    DDR1600_FREQUENCY,
+    DDR1333_FREQUENCY,
+    DDR1066_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR667_FREQUENCY,
+    DDR533_FREQUENCY,
+    DDR400_FREQUENCY
+  };
+  UINT32 NBFreq;
+  UINT8 j;
+  UINT16 DdrFreq;
+  UINT32         ProcessorPackageType;
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+
+  FamilySpecificServices = NULL;
+  DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
+  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &(NBPtr->MemPtr->StdHeader))) {
+    ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
+    NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100;  // Calculate the Nb P1 frequency (NbFreq / 2)
+    for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
+      if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
+        // Pick Max MEMCLK that is less than or equal to (NCLK_P1 / 2)
+        DdrFreq = SupportedFreq[j];
+        break;
+      }
+    }
+    if ((ProcessorPackageType != PACKAGE_TYPE_S1G3_S1G4) ||
+        (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
+      if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
+        NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
+      }
+    } else {
+      PutEventLog (AGESA_WARNING, MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
+      NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;  // Calculate the Nb P0 frequency
+      for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
+        if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
+          // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2)
+          DdrFreq = SupportedFreq[j];
+          break;
+        }
+      }
+      if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
+        NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
+      }
+    }
+    MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 4);
+    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 1);
+  } else {
+    NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;  // Calculate the Nb P0 frequency
+    for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
+      if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
+        // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2)
+        DdrFreq = SupportedFreq[j];
+        break;
+      }
+    }
+    if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
+      NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
+    }
+    MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
+    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
new file mode 100755
index 0000000000..59b1732e25
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c
@@ -0,0 +1,135 @@
+/**
+ * @file
+ *
+ * mnflowda.c
+ *
+ * Deerhound initializer for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mnda.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNFLOWDA_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the platform specific block
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
+ *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
+ */
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 f;
+  UINT8 ErrUnSuppFFCount;
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
+      ErrUnSuppFFCount = 0;
+      for (f = 0; f < MAX_FF_TYPES; f++) {
+        ASSERT (memPlatSpecFFInstalledDA[f] != NULL);
+        if (memPlatSpecFFInstalledDA[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
+          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
+        } else {
+          break;
+        }
+      }
+      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
+        return FALSE; // No FF types are supported
+      }
+    }
+  }
+  return TRUE;
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c
new file mode 100755
index 0000000000..de9fb85196
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c
@@ -0,0 +1,134 @@
+/**
+ * @file
+ *
+ * mnidendimmda.c
+ *
+ * DA northbridge constructor for dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ *
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Ganged = FALSE;
+  InitNBRegTableDA (NBPtr->NBRegTable);
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c
new file mode 100755
index 0000000000..b2009c3b21
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c
@@ -0,0 +1,154 @@
+/**
+ * @file
+ *
+ * mnmctda.c
+ *
+ * Northbridge DA MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNMCTDA_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNFinalizeMctDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+  MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
+  MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
+  MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
+  MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
+  // Recommended settings for F2x11C
+  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
+  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+  MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
+  MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
+  // For power saving
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      if (NBPtr->ChannelPtr->Dimmx4Present == 0) {
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80));
+      }
+      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0830, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0830) | 0x10));
+      }
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D07812F, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D07812F) | 0x01));
+    }
+  }
+
+  if (NBPtr->Node == BSP_DIE) {
+    if (!NBPtr->ClToNbFlag) {
+      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
+      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+
+    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
+    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
new file mode 100755
index 0000000000..8b701549a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * mnotda.c
+ *
+ * Northbridge Non-SPD timings for DA
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 10082 $ @e \$Date: 2008-12-17 06:21:26 -0600 (Wed, 17 Dec 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNOTDA_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNSetOtherTimingDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNPowerDownCtlDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNOtherTimingDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSwitchDCTNb (NBPtr, 0);
+  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
+    MemNSetOtherTimingDA (NBPtr);        // Set DA Timings
+    MemNPowerDownCtlNb (NBPtr);
+    MemNEnDLLShutDownDA (NBPtr);
+  }
+
+  MemNSwitchDCTNb (NBPtr, 1);
+  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
+    MemNSetOtherTimingDA (NBPtr);                // Set DA Timings
+    MemNPowerDownCtlNb (NBPtr);
+    MemNEnDLLShutDownDA (NBPtr);
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings into the PCI registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNSetOtherTimingDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNPowerDownCtlDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+
+  // we can't enable powerdown mode when doing WL
+  if (RefPtr->EnablePowerDown) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+  }
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
new file mode 100755
index 0000000000..9541374188
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * mnprotoda.c
+ *
+ * Northbridge support functions for Errata and early samples
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes Node memory 1GB boundary alignment.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *NodeSysLimit   - Pointer to the NodeSysLimit
+ *
+ */
+
+VOID
+MemPNodeMemBoundaryDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT32 *NodeSysLimit
+  )
+{
+  if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
+    // only apply to DDR2.
+    if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) {
+      // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node
+      *NodeSysLimit += 1;
+      *NodeSysLimit &= 0xFFFFC000;
+      *NodeSysLimit -= 1;
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c
new file mode 100755
index 0000000000..2ae2b87846
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c
@@ -0,0 +1,554 @@
+/**
+ * @file
+ *
+ * mnregda.c
+ *
+ * Common Northbridge register related functions for DA
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DA)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DA_MNREGDA_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemNIsIdSupportedDA
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a RB.
+ *     @return          FALSE - This node is not a RB.
+ *
+ */
+BOOLEAN
+MemNIsIdSupportedDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+
+  if ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field to be programmed
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNCmnGetSetFieldDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  TSEFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT8 IsLinked;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = (UINT8) TSEFO_TYPE (Address);
+      IsLinked = (UINT8) TSEFO_LINKED (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
+          Address |= 0x0100;
+        }
+      }
+
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+        IsLinked = 0;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+      if (Type == NB_ACCESS) {
+        PciAddr.AddressValue = Address;
+        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+        Address = PciAddr.AddressValue;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        } else {
+          IDS_ERROR_TRAP;
+        }
+        if (IsLinked) {
+          MemNCmnGetSetFieldDA (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+        if (IsLinked) {
+          Value |= MemNCmnGetSetFieldDA (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   NBRegTable[]   - Pointer to the bit field data structure
+ *
+ */
+
+VOID
+InitNBRegTableDA (
+  IN OUT   TSEFO NBRegTable[]
+  )
+{
+  UINT16 i;
+  for (i = 0; i < BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFF3X188B8);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  0,  0, BFIntLvRgnSwapEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  9,  3, BFIntLvRgnBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  17, 11, BFIntLvRgnLmtAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C),  26, 20, BFIntLvRgnSize);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D, 31,  0, BFPhyDLLControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F0C);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D040F3E);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D042F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D042F3E);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D048F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D048F3E);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D04DF3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D04DF3E);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0F13, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0F13);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0830, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0830);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D07812F, _NOT_USED_, _NOT_USED_, BFPhy0x0D07812F);
+
+  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
+  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
+  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
+
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c
new file mode 100755
index 0000000000..6cce298c66
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -0,0 +1,211 @@
+/**
+ * @file
+ *
+ * mnParTrainDr.c
+ *
+ * Feature which performs Memory DQS training on each node with each node training
+ * its own memory through code running on a core in the associated processor.
+ * This way memory can be trained in parallel by more than one processor.
+ *
+ * This file contains the Deerhound specific parallel training function.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/HCTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE
+
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+);
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the training function which set up the environment for remote
+ * training on the ap and launches the remote routine.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Launch training on AP successfully.
+ *     @return          FALSE - Fail to launch training on AP.
+ */
+BOOLEAN
+MemFParallelTrainingDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  DIE_STRUCT *MCTPtr;
+  REMOTE_TRAINING_ENV *EnvPtr;
+  AP_TASK TrainingTask;
+  UINT8 Socket;
+  UINT8 Module;
+  UINT8 APCore;
+  UINT8 p;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 BspSocket;
+  UINT32 BspModule;
+  UINT32 BspCore;
+  AGESA_STATUS Status;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT16 MctDataSize;
+
+  StdHeader = &(NBPtr->MemPtr->StdHeader);
+  MCTPtr = NBPtr->MCTPtr;
+  Socket = MCTPtr->SocketId;
+  Module = MCTPtr->DieId;
+
+  //
+  // Allocate buffer for REMOTE_TRAINING_ENV
+  //
+  MctDataSize = MAX_DCTS_PER_NODE_DR * (
+                  sizeof (DCT_STRUCT) + (
+                    MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                  )
+                );
+  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
+    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
+
+    //
+    // Setup Remote training environment
+    //
+    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
+    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
+    }
+    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
+    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDR;
+    EnvPtr->FeatPtr = NBPtr->FeatPtr;
+    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
+    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
+    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
+    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
+    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
+
+    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
+
+    //
+    // Get Socket, Core of the BSP
+    //
+    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
+    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
+    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
+
+    //
+    // Set up the remote task structure
+    //
+    TrainingTask.DataTransfer.DataPtr = EnvPtr;
+    TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4;
+    TrainingTask.DataTransfer.DataTransferFlags = 0;
+    TrainingTask.ExeFlags = 0;
+    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
+
+    //
+    // Get Target AP Core
+    //
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    APCore = (UINT8) (LowCore & 0x000000FF);
+
+    //
+    // Launch Remote Training
+    //
+    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
+
+    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
+    return TRUE;
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
+    return FALSE;
+  }
+}
+
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+  )
+{
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+
+  MemNInitNBDataDr (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c
new file mode 100755
index 0000000000..ddd4ef38fa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c
@@ -0,0 +1,707 @@
+/**
+ * @file
+ *
+ * mns3dr.c
+ *
+ * DR memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mndr.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mnS3dr.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNS3DR_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstDr (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3SetSpecialPCIRegDr (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3ExitSelfRefRegDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncDr[] = {
+  {MemNS3GetCSRNb, MemNS3SetCSRNb},
+  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDr},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDr[] = {
+  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
+  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
+  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
+  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDr = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorDr) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorDr,
+  NULL
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDr[] = {
+   // DCT 0
+  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  // errata 322
+  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  // errata 263
+  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+   // DCT 1
+  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 322
+  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 263
+  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore F2x[1,0]94 right before exit self refresh
+  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDr = {
+  0,
+  (sizeof (S3CPciPreSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPreSelfDescriptorDr,
+  PciSpecialCaseFuncDr
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDr[] = {
+  // DCT0
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+
+    // DCT1
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+
+  // Restore scrubber related registers after restoring training related registers
+  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDr = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorDr,
+  PciSpecialCaseFuncDr
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDr[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
+  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDr = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorDr) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorDr,
+  NULL
+};
+
+VOID *MemS3RegListDr[] = {
+  (VOID *)&S3PciPreSelfRefDr,
+  NULL,
+  (VOID *)&S3CPciPreSelfRefDr,
+  (VOID *)&S3CPciPostSelfRefDr,
+  (VOID *)&S3MSRPreSelfRefDr,
+  NULL,
+  NULL,
+  NULL
+};
+
+CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
+};
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *      @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemS3ResumeConstructNBBlockDr (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  InitNBRegTableDr (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->IsSupported[CheckDllSpeedUp] = FALSE;
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDr;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDr;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDr;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDr;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)) * sizeof (UINT32);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for DR
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[PCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DR + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CPCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DR + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[MSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DR + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CMSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DR + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      none
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstDr (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListDr) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListDr[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListDr[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device register list error
+  return AGESA_FATAL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *      @return         none
+ */
+VOID
+STATIC
+MemNS3SetSpecialPCIRegDr (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (Address.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_DR);
+    // Save the value in the heap at appropriate offset based on the index
+    // of the target register in the special case array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) {
+        if (SpecialCasePCIRegDr[i] == Address.Address.Register) {
+          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
+        }
+      }
+    }
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
+ *     @param[in,out]  *StdHeader - Config handle for library and services.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3ExitSelfRefRegDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  PCI_ADDR PciAddr;
+  UINT32 Value;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+  PciAddr.Address.Function = 2;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (PciAddr.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_DR);
+    // Restore the value one by one in the sequence of the special case register array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) {
+        PciAddr.Address.Register = SpecialCasePCIRegDr[i];
+        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
+        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h
new file mode 100755
index 0000000000..d2607ca962
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mnS3dr.h
+ *
+ * S3 resume memory related function for DR.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MNS3DR_H_
+#define _MNS3DR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of DR
+typedef enum {
+  PCI_LST_ESR_DR,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_DR,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_DR,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_DR,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_DR,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_DR,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_DR,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_DR,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDDr;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3DR_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
new file mode 100755
index 0000000000..52a589ecb6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c
@@ -0,0 +1,509 @@
+/**
+ * @file
+ *
+ * mndctdr.c
+ *
+ * Northbridge DR DCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mndr.h"
+#include "merrhdl.h"
+#include "OptionMemory.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNDCTDR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTCtlOnDimmMirrorDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BOOLEAN SetFlag
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
+ */
+
+BOOLEAN
+memNAutoConfigDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  //======================================================================
+  // Build Dram Control Register Value (F2x78)
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
+  MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
+
+  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
+
+  //======================================================================
+  // Build Dram Config Lo Register Value
+  //======================================================================
+  //
+
+
+  if (MCTPtr->Status[SbParDimms]) {
+    //
+    // SbParDimms should be set for all DDR3 RDIMMS or DDR2 that support parity
+    // Cannot turn off ParEn for DDR3
+    //
+    //@attention - add debug option for parity control
+    if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) || (RefPtr->EnableParity)) {
+      MemNSetBitFieldNb (NBPtr, BFParEn, 1);
+    }
+  }
+
+  if (MCTPtr->GangedMode) {
+    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
+
+  if (!MCTPtr->Status[SbRegistered]) {
+    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
+  }
+
+  if (MCTPtr->Status[SbEccDimms]) {
+    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
+  }
+
+  //======================================================================
+  // Build Dram Config Hi Register Value
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
+
+  if (MCTPtr->Status[SbRegistered]) {
+    if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) {
+      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
+    }
+  }
+
+  if (RefPtr->EnableBankSwizzle) {
+    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
+  }
+
+  if (DCTPtr->Timings.DimmQrPresent) {
+    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
+      MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1);
+    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
+      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
+    }
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
+
+  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
+
+  //======================================================================
+  // Build Dram Config Misc Register Value
+  //======================================================================
+  //
+  MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
+  // For DDR3 Registered Dimms
+  if (MCTPtr->Status[SbRegistered]) {
+    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
+      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
+    }
+  }
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM init
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDramInitDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends an MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendMrsCmdDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN ClearODM;
+
+  ClearODM = FALSE;
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
+    if (MemNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) {
+      // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS
+      MemTCtlOnDimmMirrorDr (NBPtr, FALSE);
+      ClearODM = TRUE;
+    }
+  }
+
+  MemNSwapBitsNb (NBPtr);
+
+  IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n",
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+
+  if (ClearODM) {
+    // Restore ODM if necessary
+    MemTCtlOnDimmMirrorDr (NBPtr, TRUE);
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Workaround for erratum 322 and 263
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNBeforePlatformSpecDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // Errata 263
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
+  }
+
+  // Errata 322
+  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
+  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
+  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
+  //    greater than or equal to 011b (DDR-800 and higher),
+  //    then write 00000080h to F2x[1,0]9C_xD02E001,
+  //    else write 00000090h to F2x[1,0]9C_xD02E001.
+  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   SetFlag   - Enable or disable flag - TRUE - Enable, FALSE - DISABLE
+ *
+ */
+
+VOID
+STATIC
+MemTCtlOnDimmMirrorDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BOOLEAN SetFlag
+  )
+{
+  UINT8 Chipsel;
+  UINT32 CSBaseAddrReg;
+
+  for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) {
+    CSBaseAddrReg = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel);
+    if ((CSBaseAddrReg & 1) == 1) {
+      if (SetFlag && ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) {
+        CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror);
+      } else {
+        CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror);
+      }
+      MemNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function adjusts Avg PRE value of Phy fence training according to specific CPU family.
+ *
+ *     @param[in,out]   *NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Value16 - Pointer to the value that we want to adjust
+ *
+ */
+
+VOID
+MemNPFenceAdjustDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *Value16
+  )
+{
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
+    *Value16 += 5; //for RB C0, the Avg PRE value is subtracted by 3 only.
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function uses calculated values from DCT.Timings structure to
+ *      program its RB registers.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramCycTimingsDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CTENTRY DDR3TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 4, 12, 4, 2},
+    {BFTrcd, 5, 12, 5, 2},
+    {BFTrp, 5, 12, 5, 2},
+    {BFTrtp, 4, 7, 4, 2},
+    {BFTras, 15, 30, 15, 2},
+    {BFTrc, 11, 42, 11, 2},
+    {BFTwrDDR3, 5, 12, 4, 2},
+    {BFTrrd, 4, 7, 4, 2},
+    {BFTwtr, 4, 7, 4, 2},
+    {BFFourActWindow, 16, 32, 14, 1}
+  };
+
+  CTENTRY DDR2TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 3, 7, 1, 2},
+    {BFTrcd, 3, 6, 3, 2},
+    {BFTrp, 3, 6, 3, 4},
+    {BFTrtp, 2, 3, 2, 4},
+    {BFTras, 5, 18, 3, 2},
+    {BFTrc, 11, 26, 11, 2},
+    {BFTwr, 3, 6, 3, 2},
+    {BFTrrd, 2, 5, 2, 2},
+    {BFTwtr, 5, 8, 4, 2},
+    {BFFourActWindow, 8, 20, 7, 2}
+  };
+
+  CTENTRY *TmgAdjTab;
+  DCT_STRUCT *DCTPtr;
+  UINT8  *MiniMaxTmg;
+  UINT8  *MiniMaxTrfc;
+  UINT8  Value8;
+  UINT8  j;
+  UINT8  BurstMode;
+  BIT_FIELD_NAME BitField;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
+    TmgAdjTab = DDR3TmgAdjTab;
+  } else if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
+    // DDR2-1066 uses DDR3 table but differs in tCL
+    TmgAdjTab = DDR3TmgAdjTab;
+    TmgAdjTab[0].Min = 3;
+    TmgAdjTab[0].Max = 7;
+    TmgAdjTab[0].Bias = 1;
+  } else {
+    TmgAdjTab = DDR2TmgAdjTab;
+  }
+
+  MiniMaxTmg = &DCTPtr->Timings.CasL;
+  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
+    BitField = TmgAdjTab[j].BitField;
+
+    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Min;
+    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Max;
+    }
+
+    Value8 = (UINT8) MiniMaxTmg[j];
+
+    if (BitField == BFTwrDDR3) {
+      Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8;
+    } else if (BitField == BFTrtp) {
+      Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6;
+    }
+
+    Value8 = Value8 - TmgAdjTab[j].Bias;
+    Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
+
+    MemNSetBitFieldNb (NBPtr, BitField, Value8);
+  }
+
+  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
+  for (j = 0; j < 4; j++) {
+    MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // 7.8 us
+
+  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
+    //======================================================================
+    // DDR3 additional settings
+    //======================================================================
+
+    MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ?
+                                       (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0));
+
+    MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF);
+
+    MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
+
+    // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
+    MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
+
+    // burst length control
+    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+      MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2);
+    }
+
+    // ASR=1, auto self refresh; SRT=0
+    MemNSetBitFieldNb (NBPtr, BFASR, 1);
+  } else {
+    //======================================================================
+    // DDR2 additional settings
+    //======================================================================
+
+    MemNSetBitFieldNb (NBPtr, BFNonSPD, 0xFF77);
+
+    BurstMode = UserOptions.CfgUseBurstMode;
+    IDS_OPTION_HOOK (IDS_BURST_LENGTH32, &BurstMode, &(NBPtr->MemPtr->StdHeader));
+    if (BurstMode) {
+      if (!NBPtr->MCTPtr->GangedMode) {
+        NBPtr->SetBitField (NBPtr, BFBurstLength32, 1);
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
new file mode 100755
index 0000000000..af67da104b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c
@@ -0,0 +1,452 @@
+/**
+ * @file
+ *
+ * mndr.c
+ *
+ * Common Northbridge functions for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "mu.h"
+#include "merrhdl.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNDR_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   (UINT32) 0x20000000
+#define CHANNEL_SELECT  (UINT32) 0x10000000
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @return     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 SpdSocketIndex;
+  UINT8 SpdChannelIndex;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT);
+  }
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
+    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
+    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
+  }
+
+  MemNInitNBDataDr (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  //
+  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
+  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
+  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
+  // dimm types(QR or not) are known. This is done in the Technology block constructor.
+  //
+  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
+  // This will facilitate modifications due to some processors that might
+  // map the DCT-CHANNEL differently.
+  //
+  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
+  //
+  // Traverse the Dct/Channel structures
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) {
+      //
+      // Calculate the number of Dimms on this channel using the
+      //   die/dct/channel to Socket/channel conversion.
+      //
+      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            NBPtr->MCTPtr->SocketId,
+                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
+                                            &MemPtr->StdHeader);
+      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
+    }
+  }
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  InitNBRegTableDr (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DR;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_72B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR800_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0xFF;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
+  NBPtr->DefDctSelIntLvAddr = 3;
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
+  NBPtr->InitializeMCT = MemNInitializeMctNb;
+  NBPtr->FinalizeMCT = MemNFinalizeMctDr;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdDr;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternDr;
+  NBPtr->ReadPattern = MemNReadPatternDr;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->StitchMemory = MemNStitchMemoryNb;
+  NBPtr->AutoConfig = memNAutoConfigDr;
+  NBPtr->PlatformSpec = MemNPlatformSpecNb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->DisableDCT = MemNDisableDCTNb;
+  NBPtr->StartupDCT = MemNStartupDCTNb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
+  NBPtr->ChangeNbFrequency = MemNDefFalseNb;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsDr;
+  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
+  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
+  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->OtherTiming = (BOOLEAN (*) (MEM_NB_BLOCK *)) MemMDefRet;    //@attention - due to build issue with MemNOtherTimingDr
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
+  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->TrainingFlow = MemNTrainingFlowNb;
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  MemNInitNBDataNb (NBPtr);
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
+  NBPtr->BrdcstSet = MemNBrdcstSetNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDr;
+  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDr;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
+  NBPtr->MemPPhyFenceTrainingNb = MemPPhyFenceTrainingDr;
+  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDr;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
+  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDr;
+  NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustDr;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->CSPerChannel = MemNCSPerChannelNb;
+  NBPtr->CSPerDelay = MemNCSPerDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
+  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
+
+  NBPtr->IsSupported[SetSpareEn] = TRUE;
+  NBPtr->IsSupported[CheckSpareEn] = TRUE;
+  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[Check1GAlign] = TRUE;
+  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
+  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
+  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
+  NBPtr->IsSupported[CheckDynamicDramTerm] = TRUE;
+  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+VOID
+MemNInitDefaultsDR (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
+  //
+
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
+      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
+    }
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
+  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
+  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h
new file mode 100755
index 0000000000..b630071def
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h
@@ -0,0 +1,188 @@
+/**
+ * @file
+ *
+ * mndr.h
+ *
+ * Northbridge DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNDR_H_
+#define _MNDR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CHANNELS_PER_SOCKET_DR    2
+#define MAX_DCTS_PER_NODE_DR          2
+#define MAX_CHANNELS_PER_DCT_DR       1
+#define MAX_NODES_SUPPORTED_DR        8
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructNBBlockDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitNBDataDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDefaultsDR (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNFinalizeMctDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSendMrsCmdDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+memNAutoConfigDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNOtherTimingDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWritePatternDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemPNodeMemBoundaryDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT32 *NodeSysLimit
+  );
+
+VOID
+InitNBRegTableDr (
+  IN OUT   TSEFO NBRegTable[]
+  );
+
+BOOLEAN
+MemNIsIdSupportedDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+VOID
+MemNBeforeDramInitDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNBeforePlatformSpecDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemPPhyFenceTrainingDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNCmnGetSetFieldDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNPFenceAdjustDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *Value16
+  );
+
+VOID
+MemNProgramCycTimingsDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MNDR_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
new file mode 100755
index 0000000000..b89a8bb312
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c
@@ -0,0 +1,137 @@
+/**
+ * @file
+ *
+ * mnflowdr.c
+ *
+ * Deerhound initializer for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mndr.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNFLOWDR_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the platform specific block
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
+ *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
+ */
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 f;
+  UINT8 ErrUnSuppFFCount;
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
+      ErrUnSuppFFCount = 0;
+      for (f = 0; f < MAX_FF_TYPES; f++) {
+        ASSERT (memPlatSpecFFInstalledDR[f] != NULL);
+        if (memPlatSpecFFInstalledDR[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
+          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
+        } else {
+          break;
+        }
+      }
+      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
+        return FALSE; // No FF types are supported
+      }
+    }
+  }
+  return TRUE;
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c
new file mode 100755
index 0000000000..19df019650
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c
@@ -0,0 +1,134 @@
+/**
+ * @file
+ *
+ * mnidendimmdr.c
+ *
+ * DR northbridge constructor for dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ *
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Ganged = FALSE;
+  InitNBRegTableDr (NBPtr->NBRegTable);
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c
new file mode 100755
index 0000000000..615c005187
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c
@@ -0,0 +1,141 @@
+/**
+ * @file
+ *
+ * mnmctdr.c
+ *
+ * Northbridge DR MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNMCTDR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNFinalizeMctDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+  MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
+  MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
+  MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
+  MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
+  // Recommended settings for F2x11C
+  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
+  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+  MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
+  MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
+
+  if (NBPtr->Node == BSP_DIE) {
+    if (!NBPtr->ClToNbFlag) {
+      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
+      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+
+    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
+    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
new file mode 100755
index 0000000000..7dbcd12f60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * mnotdr.c
+ *
+ * Northbridge Non-SPD timings for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNOTDR_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNSetOtherTimingDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNPowerDownCtlDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNOtherTimingDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
+    MemNSetOtherTimingDR (NBPtr);        // Set DR Timings
+    MemNPowerDownCtlNb (NBPtr);
+  }
+
+  MemNSwitchDCTNb (NBPtr, 1);
+  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
+    MemNSetOtherTimingDR (NBPtr);                // Set DR Timings
+    MemNPowerDownCtlNb (NBPtr);
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings into the PCI registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNSetOtherTimingDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNPowerDownCtlDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+
+  // we can't enable powerdown mode when doing WL
+  if (RefPtr->EnablePowerDown) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+  }
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
new file mode 100755
index 0000000000..ee2ada03f7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c
@@ -0,0 +1,164 @@
+/**
+ * @file
+ *
+ * mnprotodr.c
+ *
+ * Northbridge support functions for Errata and early samples
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+
+#include "AGESA.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNPROTODR_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNTrainFenceWHardCodeValDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function conditionally executes specific Phy fence training function.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemPPhyFenceTrainingDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
+    //DDR2 specific.
+    if (NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) {
+      MemNTrainFenceWHardCodeValDr (NBPtr);
+    } else {
+      MemNTrainPhyFenceNb (NBPtr);
+    }
+  } else {
+    //DDR3 specific.
+    MemNTrainPhyFenceNb (NBPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes hardcoded Phy fence training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNTrainFenceWHardCodeValDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 CurDct;
+  UINT16 Speed;
+
+  CurDct = NBPtr->Dct;
+  if (NBPtr->MCTPtr->NodeMemSize) {
+    for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      Speed = NBPtr->DCTPtr->Timings.Speed;
+      NBPtr->SetBitField (NBPtr, BFPhyFence, ((Speed == DDR800_FREQUENCY) || (Speed == DDR1066_FREQUENCY)) ? 20 : 20);
+      NBPtr->SetBitField (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0);
+      NBPtr->SetBitField (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
+      NBPtr->SetBitField (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
+    }
+  }
+
+  NBPtr->SwitchDCT (NBPtr, CurDct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes Node memory 1GB boundary alignment.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *NodeSysLimit   - Pointer to the NodeSysLimit
+ *
+ */
+
+VOID
+MemPNodeMemBoundaryDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT32 *NodeSysLimit
+  )
+{
+  if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
+    // only apply to DDR2.
+    if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) {
+      // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node
+      *NodeSysLimit += 1;
+      *NodeSysLimit &= 0xFFFFC000;
+      *NodeSysLimit -= 1;
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c
new file mode 100755
index 0000000000..c2fe73ccaa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c
@@ -0,0 +1,530 @@
+/**
+ * @file
+ *
+ * mnregdr.c
+ *
+ * Common Northbridge register related functions for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 13216 $ @e \$Date: 2009-05-06 18:20:12 -0500 (Wed, 06 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mndr.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_DR_MNREGDR_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemNIsIdSupportedDr
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a RB.
+ *     @return          FALSE - This node is not a RB.
+ *
+ */
+BOOLEAN
+MemNIsIdSupportedDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+
+  if ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL
+                               | AMD_F10_BL_ALL
+                               | AMD_F10_DA_ALL )) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field to be programmed
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNCmnGetSetFieldDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  TSEFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT8 IsLinked;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = (UINT8) TSEFO_TYPE (Address);
+      IsLinked = (UINT8) TSEFO_LINKED (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
+          Address |= 0x0100;
+        }
+      }
+
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+        IsLinked = 0;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+      if (Type == NB_ACCESS) {
+        PciAddr.AddressValue = Address;
+        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+        Address = PciAddr.AddressValue;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        } else {
+          IDS_ERROR_TRAP;
+        }
+        if (IsLinked) {
+          MemNCmnGetSetFieldDr (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+        if (IsLinked) {
+          Value |= MemNCmnGetSetFieldDr (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   NBRegTable[]   - Pointer to the bit field data structure
+ *
+ */
+
+VOID
+InitNBRegTableDr (
+  IN OUT   TSEFO NBRegTable[]
+  )
+{
+  UINT16 i;
+  for (i = 0; i < BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFF3X188B8);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
+
+  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
+  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
+  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
+
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c
new file mode 100755
index 0000000000..9ae62d6862
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -0,0 +1,213 @@
+/**
+ * @file
+ *
+ * mnParTrainHy.c
+ *
+ * Feature which performs Memory DQS training on each node with each node training
+ * its own memory through code running on a core in the associated processor.
+ * This way memory can be trained in parallel by more than one processor.
+ *
+ * This file contains the Hydra specific parallel training function.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/HCTRN)
+ * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnhy.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "mfParallelTraining.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE
+/*-----------------------------------------------------------------------------
+*                                EXPORTED FUNCTIONS
+*
+*-----------------------------------------------------------------------------
+*/
+#ifdef UNUSED_CODE
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+);
+#endif
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This is the training function which set up the environment for remote
+ * training on the ap and launches the remote routine.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  Launch training on AP successfully.
+ *     @return          FALSE - Fail to launch training on AP.
+ */
+#ifdef UNUSED_CODE
+STATIC BOOLEAN
+MemFParallelTrainingHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AMD_CONFIG_PARAMS *StdHeader;
+  DIE_STRUCT *MCTPtr;
+  REMOTE_TRAINING_ENV *EnvPtr;
+  AP_TASK TrainingTask;
+  UINT8 Socket;
+  UINT8 Module;
+  UINT8 APCore;
+  UINT8 p;
+  UINT32 LowCore;
+  UINT32 HighCore;
+  UINT32 BspSocket;
+  UINT32 BspModule;
+  UINT32 BspCore;
+  AGESA_STATUS Status;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  UINT16 MctDataSize;
+  StdHeader = &(NBPtr->MemPtr->StdHeader);
+  MCTPtr = NBPtr->MCTPtr;
+  Socket = MCTPtr->SocketId;
+  Module = MCTPtr->DieId;
+
+  //
+  // Allocate buffer for REMOTE_TRAINING_ENV
+  //
+  MctDataSize = MAX_DCTS_PER_NODE_HY * (
+                  sizeof (DCT_STRUCT) + (
+                    MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                  )
+                );
+  AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
+    AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
+
+    //
+    // Setup Remote training environment
+    //
+    LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+    LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
+    for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+      EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
+    }
+    EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
+    EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY;
+    EnvPtr->FeatPtr = NBPtr->FeatPtr;
+    EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
+    EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
+    EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
+    EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
+    EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
+    EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
+
+    LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
+
+    //
+    // Get Socket, Core of the BSP
+    //
+    IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
+    EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
+    EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
+
+    //
+    // Set up the remote task structure
+    //
+    TrainingTask.DataTransfer.DataPtr = EnvPtr;
+    TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4;
+    TrainingTask.DataTransfer.DataTransferFlags = 0;
+    TrainingTask.ExeFlags = 0;
+    TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
+
+    //
+    // Get Target AP Core
+    //
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    APCore = (UINT8) (LowCore & 0x000000FF);
+
+    //
+    // Launch Remote Training
+    //
+    ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
+
+    HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
+
+    return TRUE;
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
+    return FALSE;
+  }
+}
+
+BOOLEAN
+STATIC
+MemConstructRemoteNBBlockHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+  )
+{
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+
+  MemNInitNBDataHy (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c
new file mode 100755
index 0000000000..a4d3377f21
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c
@@ -0,0 +1,738 @@
+/**
+ * @file
+ *
+ * mns3hy.c
+ *
+ * HY memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mnhy.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mnS3hy.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstHy (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3ExitSelfRefRegHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+MemNS3SetSpecialPCIRegHy (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = {
+  {MemNS3GetCSRNb, MemNS3SetCSRNb},
+  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = {
+  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
+  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
+  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
+  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorHy,
+  NULL
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = {
+   // DCT 0
+  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA4,  0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 322
+  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 263
+  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+   // DCT 1
+  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 322
+  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 263
+  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore F2x[1,0]94 right before exit self refresh
+  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = {
+  0,
+  (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPreSelfDescriptorHy,
+  PciSpecialCaseFuncHy
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = {
+  // DCT0
+  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+
+    // DCT1
+  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+
+  // DllShutDown
+  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore scrubber related registers after restoring training related registers
+  {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorHy,
+  PciSpecialCaseFuncHy
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FFull},
+  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000ull},
+  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000ull},
+  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFFull}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorHy,
+  NULL
+};
+
+VOID *MemS3RegListHy[] = {
+  (VOID *)&S3PciPreSelfRefHy,
+  NULL,
+  (VOID *)&S3CPciPreSelfRefHy,
+  (VOID *)&S3CPciPostSelfRefHy,
+  (VOID *)&S3MSRPreSelfRefHy,
+  NULL,
+  NULL,
+  NULL
+};
+
+CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = {
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
+};
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemS3ResumeConstructNBBlockHy (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *     @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemS3ResumeConstructNBBlockHy (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  InitNBRegTableHy (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for HY
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      none
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstHy (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListHy[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListHy[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device register list error
+  return AGESA_FATAL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3SetSpecialPCIRegHy (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (Address.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_HY);
+    // Save the value in the heap at appropriate offset based on the index
+    // of the target register in the special case array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) {
+        if (SpecialCasePCIRegHy[i] == Address.Address.Register) {
+          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
+        }
+      }
+    }
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
+ *     @param[in,out]  *StdHeader - Config handle for library and services.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3ExitSelfRefRegHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  PCI_ADDR PciAddr;
+  UINT32 Value;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+  PciAddr.Address.Function = 2;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (PciAddr.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_HY);
+    // Restore the value one by one in the sequence of the special case register array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) {
+        PciAddr.Address.Register = SpecialCasePCIRegHy[i];
+        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
+        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h
new file mode 100755
index 0000000000..88c293e9d0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mnS3hy.h
+ *
+ * S3 resume memory related function for HY.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MNS3HY_H_
+#define _MNS3HY_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of HY
+typedef enum {
+  PCI_LST_ESR_HY,  ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_HY,      ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_HY,     ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_HY,  ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_HY,      ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_HY      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDHy;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3HY_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c
new file mode 100755
index 0000000000..87b8ed437a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c
@@ -0,0 +1,361 @@
+/**
+ * @file
+ *
+ * mndctHy.c
+ *
+ * Northbridge DCT support for Hydra
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 47176 $ @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mnhy.h"
+#include "merrhdl.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ *     @return          NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
+ */
+
+BOOLEAN
+MemNAutoConfigHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 PowerDownMode;
+  UINT32 Value32;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  //======================================================================
+  // Build Dram Control Register Value (F2x78)
+  //======================================================================
+  //
+  //It is recommended that these bits remain in the default state.
+  //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5);
+
+  MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
+
+  //======================================================================
+  // Build Dram Config Lo Register Value
+  //======================================================================
+  //
+
+  if (MCTPtr->Status[SbParDimms]) {
+    //
+    // SbParDimms should be set for all DDR3 RDIMMS
+    // Cannot turn off ParEn for DDR3
+    //
+    //@attention - add debug option for parity control
+    MemNSetBitFieldNb (NBPtr, BFParEn, 1);
+  }
+
+
+  if (MCTPtr->GangedMode) {
+    MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
+
+  if (!MCTPtr->Status[SbRegistered]) {
+    MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
+  }
+
+  if (MCTPtr->Status[SbEccDimms]) {
+    MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
+  }
+
+  //======================================================================
+  // Build Dram Config Hi Register Value
+  //======================================================================
+  //
+
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
+
+  if (MCTPtr->Status[SbRegistered]) {
+    if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) {
+      MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
+    }
+  }
+
+  if (RefPtr->EnableBankSwizzle) {
+    MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
+  }
+
+  if (DCTPtr->Timings.DimmQrPresent) {
+    if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
+      MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1);
+    } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
+      MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
+    }
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
+  MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
+  //======================================================================
+  // Build Dram Config Misc Register Value
+  //======================================================================
+  //
+  if (MCTPtr->Status[SbRegistered]) {
+    if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
+      MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
+    }
+  }
+  //======================================================================
+  // Build Dram Config Misc 2 Register Value
+  //======================================================================
+  //
+  //
+  // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms
+  //
+  if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) {
+    MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1);
+  }
+  //
+  // DTaxTxFifpWrDly
+  //
+  Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
+  if ((Value32 >= 2) && (Value32 <= 5)) {
+    MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32));
+  }
+
+  //
+  // ProgOdtEn
+  //
+  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
+    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0);
+  }
+  //
+  // OdtSwizzle
+  //
+  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) {
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode == 1) {
+      MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
+    }
+  }
+
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends an MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendMrsCmdHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSwapBitsNb (NBPtr);
+
+  IDS_HDT_CONSOLE ("\t\t\tCS%lx MR%lx %04lx\n",
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
+              (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM init
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDramInitHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      //Set PllLockTime and DllLockTime to default.
+      MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
+      MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
+      MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Enable DLL Shut down
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNEnDLLShutDownHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  BOOLEAN DllShutDownEn;
+
+  DllShutDownEn = TRUE;
+  IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
+
+  if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
+    if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) {
+      for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+        MemNSwitchDCTNb (NBPtr, Dct);
+        if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+          MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
+          MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
+          MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
+        }
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Workaround for erratum 322 and 263
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNBeforePlatformSpecHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // Errata 263
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFErr263, 0);
+  }
+
+  // Errata 322
+  // 1.Write 00000000h to F2x[1,0]9C_xD08E000
+  MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
+  // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
+  //    greater than or equal to 011b (DDR-800 and higher),
+  //    then write 00000080h to F2x[1,0]9C_xD02E001,
+  //    else write 00000090h to F2x[1,0]9C_xD02E001.
+  MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
new file mode 100755
index 0000000000..b21a86121c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c
@@ -0,0 +1,130 @@
+/**
+ * @file
+ *
+ * mnflowhy.c
+ *
+ * Hydra initializer for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Main)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mnhy.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE
+/* features */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function initializes the platform specific block
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_SUCCESS at least one dorm factor was found
+ *     @return          FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
+ */
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 f;
+  UINT8 ErrUnSuppFFCount;
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->ChannelPtr->ChDimmValid != 0) {
+      ErrUnSuppFFCount = 0;
+      for (f = 0; f < MAX_FF_TYPES; f++) {
+        ASSERT (memPlatSpecFFInstalledHy[f] != NULL);
+        if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
+          ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
+        } else {
+          break;
+        }
+      }
+      if (ErrUnSuppFFCount == MAX_FF_TYPES) {
+        return FALSE; // No FF types are supported
+      }
+    }
+  }
+  return TRUE;
+}
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
new file mode 100755
index 0000000000..71d35f0c6b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c
@@ -0,0 +1,453 @@
+/**
+ * @file
+ *
+ * mnhy.c
+ *
+ * Common Northbridge  functions for Hydra
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 47246 $ @e \$Date: 2011-02-16 13:46:56 -0700 (Wed, 16 Feb 2011) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnhy.h"
+#include "mu.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   (UINT32) 0x20000000
+#define CHANNEL_SELECT  (UINT32) 0x10000000
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @return     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 SpdSocketIndex;
+  UINT8 SpdChannelIndex;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT);
+  }
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
+    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
+    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
+  }
+
+  MemNInitNBDataHy (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  //
+  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
+  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
+  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
+  // dimm types(QR or not) are known. This is done in the Technology block constructor.
+  //
+  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
+  // This will facilitate modifications due to some processors that might
+  // map the DCT-CHANNEL differently.
+  //
+  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
+  //
+  // Traverse the Dct/Channel structures
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) {
+      //
+      // Calculate the number of Dimms on this channel using the
+      //   die/dct/channel to Socket/channel conversion.
+      //
+      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            NBPtr->MCTPtr->SocketId,
+                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
+                                            &MemPtr->StdHeader);
+      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
+    }
+  }
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  InitNBRegTableHy (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_256B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR800_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0x1FF;
+  NBPtr->DefDctSelIntLvAddr = 3;
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
+  NBPtr->InitializeMCT = MemNInitializeMctNb;
+  NBPtr->FinalizeMCT = MemNFinalizeMctHy;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdHy;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternHy;
+  NBPtr->ReadPattern = MemNReadPatternHy;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->StitchMemory = MemNStitchMemoryNb;
+  NBPtr->AutoConfig = MemNAutoConfigHy;
+  NBPtr->PlatformSpec = MemNPlatformSpecNb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->DisableDCT = MemNDisableDCTNb;
+  NBPtr->StartupDCT = MemNStartupDCTNb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
+  NBPtr->ChangeNbFrequency = MemNDefFalseNb;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
+  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
+  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingHy;
+  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->OtherTiming = MemNOtherTimingHy;
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
+  NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
+  NBPtr->TrainingFlow = MemNTrainingFlowNb;
+  MemNInitNBDataNb (NBPtr);
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
+  NBPtr->BrdcstSet = MemNBrdcstSetNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
+  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompHy;
+  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy;
+  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->CSPerChannel = MemNCSPerChannelNb;
+  NBPtr->CSPerDelay = MemNCSPerDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
+  NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
+
+  NBPtr->IsSupported[SetSpareEn] = TRUE;
+  NBPtr->IsSupported[CheckSpareEn] = TRUE;
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+  NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
+  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
+  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
+  NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
+  NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
+  NBPtr->IsSupported[CheckODTControls] = TRUE;
+  NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
+  NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+VOID
+MemNInitDefaultsHY (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
+  //
+
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
+      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
+    }
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
+  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
+  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
+}
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h
new file mode 100755
index 0000000000..9e283d4f26
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h
@@ -0,0 +1,189 @@
+/**
+ * @file
+ *
+ * mnhy.h
+ *
+ * Northbridge Hydra
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 47176 $ @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNHY_H_
+#define _MNHY_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CHANNELS_PER_SOCKET_HY    4
+#define MAX_DCTS_PER_NODE_HY          2
+#define MAX_CHANNELS_PER_DCT_HY       1
+#define MAX_NODES_SUPPORTED_HY        8
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "OptionMemory.h"
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemConstructNBBlockHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitNBDataHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDefaultsHY (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNFinalizeMctHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSendMrsCmdHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNAutoConfigHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNOtherTimingHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitPhyCompHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNWritePatternHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+InitNBRegTableHy (
+  IN OUT   TSEFO NBRegTable[]
+  );
+
+UINT8
+MemNGetSocketRelativeChannelHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  );
+
+BOOLEAN
+MemNIsIdSupportedHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+VOID
+MemNBeforeDramInitHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecificFormFactorInitHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNEnDLLShutDownHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNCmnGetSetFieldHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNBeforePlatformSpecHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNBeforeDQSTrainingHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MNHY_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c
new file mode 100755
index 0000000000..2b8758e58a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c
@@ -0,0 +1,134 @@
+/**
+ * @file
+ *
+ * mnidendimmhy.c
+ *
+ * Hy northbridge constructor for dimm identification translator.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnhy.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mfidendimm.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemNIdentifyDimmConstructorHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Ganged = FALSE;
+  InitNBRegTableHy (NBPtr->NBRegTable);
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy;
+
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c
new file mode 100755
index 0000000000..469acae054
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c
@@ -0,0 +1,150 @@
+/**
+ * @file
+ *
+ * mnmcthy.c
+ *
+ * Northbridge Hydra MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnhy.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNFinalizeMctHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+  UINT16 Speed;
+  UINT32 ExtMctCfgLoRegVal;
+
+  MemPtr = NBPtr->MemPtr;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);
+
+  ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
+  ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;
+
+  ExtMctCfgLoRegVal &= 0x0FFFFFFF;
+  if (Speed == DDR667_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x40000000;
+  } else if (Speed == DDR800_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x50000000;
+  } else if (Speed == DDR1066_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x60000000;
+  } else if (Speed == DDR1333_FREQUENCY) {
+    ExtMctCfgLoRegVal |= 0x80000000;
+  } else {
+    ExtMctCfgLoRegVal |= 0x90000000;
+  }
+  MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);
+
+  if (NBPtr->Node == BSP_DIE) {
+    if (!NBPtr->ClToNbFlag) {
+      LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+      SMsr.lo &= ~((UINT32)1 << 15);                // ClLinesToNbDis
+      LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    }
+
+    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    SMsr.hi &= ~((UINT32)1 << (48 - 32));               // WbEnhWsbDis
+    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  }
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c
new file mode 100755
index 0000000000..0f5f37fcd5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c
@@ -0,0 +1,239 @@
+/**
+ * @file
+ *
+ * mnothy.c
+ *
+ * Northbridge Non-SPD timings for Hydra
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnhy.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNSetOtherTimingHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#ifdef UNUSED_CODE
+UINT32
+STATIC
+MemNGetODTDelaysHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+#endif
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNOtherTimingHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSwitchDCTNb (NBPtr, 0);
+  if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
+    MemNSetOtherTimingHY (NBPtr);
+    MemNPowerDownCtlNb (NBPtr);
+    MemNEnDLLShutDownHy (NBPtr);
+  }
+
+  MemNSwitchDCTNb (NBPtr, 1);
+  if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
+    MemNSetOtherTimingHY (NBPtr);
+    MemNPowerDownCtlNb (NBPtr);
+    MemNEnDLLShutDownHy (NBPtr);
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the non-SPD timings  in PCI registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNSetOtherTimingHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+
+  MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
+  MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the ODT delays
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+#ifdef UNUSED_CODE
+UINT32
+STATIC
+MemNGetODTDelaysHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Ld;
+  UINT32 ODTDelays;
+  //
+  // On revision D processors, the BIOS must additionally configure the ODT pattern
+  // and the ODT switching delays.
+  //
+  // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
+  //     -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
+  //     -Value of 2, BL = 4 else assume BL=8.
+  //     -Initialize ODTDelays based on BL value
+  //     -WrOdtOnDuration [14:12] = BL / 2 + 1
+  //     -WrOdtTrnOnDly [10:8] = 0
+  //     -RdOdtOnDuration [6:4] = BL / 2 + 1
+  //
+  ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
+
+  // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
+  // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
+  Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
+  if (Ld < 0) {
+    Ld = 0;
+  }
+  if (Ld > 7) {
+    Ld = 7;
+  }
+  ODTDelays += Ld;
+  return ODTDelays;
+}
+#endif
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+#ifdef UNUSED_CODE
+VOID
+STATIC
+MemNPowerDownCtlHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+
+  // we can't enable powerdown mode when doing WL
+  if (RefPtr->EnablePowerDown) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+  }
+}
+#endif
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c
new file mode 100755
index 0000000000..908263862c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c
@@ -0,0 +1,234 @@
+/**
+ * @file
+ *
+ * mnphyHy.c
+ *
+ * Northbridge Phy support for Hydra
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "ma.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mnhy.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
+  CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
+  CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
+  CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
+  UINT8 i;
+  UINT8 j;
+  UINT8 CurrDct;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+
+  CurrDct = NBPtr->Dct;
+
+  //
+  // Get Platform Information
+  //
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // DisAutoComp will be cleared after Dram init has completed
+  //
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+  MemUWait10ns (500, NBPtr->MemPtr);
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+
+  // 3. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
+  // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
+  //
+  // 4. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
+  // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
+  // D3Cmp2PCal].
+  //
+  j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
+  i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  ASSERT (j <= 3);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
+
+  ASSERT (i <= 3);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
+
+  //
+  // Special Case for certain configs
+  //
+  // 3DPCH Fully populated.
+  if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) {
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5);
+  }
+
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDQSTrainingHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 TestAddrRJ16;
+  UINT32 RealAddr;
+
+  MemTBeginTraining (NBPtr->TechPtr);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+        if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
+
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
+
+          MemUDummyCLRead (RealAddr);
+
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
+          MemUWait10ns (60, NBPtr->MemPtr);   // Wait 300ns
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
+          MemUWait10ns (400, NBPtr->MemPtr);  // Wait 2us
+          MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
+          break;
+        }
+      }
+    }
+    if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
+      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
+      }
+      if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
+      }
+    }
+  }
+
+  MemTEndTraining (NBPtr->TechPtr);
+
+  MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c
new file mode 100755
index 0000000000..dd48661f65
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c
@@ -0,0 +1,62 @@
+/**
+ * @file
+ *
+ * mnprotohy.c
+ *
+ * Northbridge support functions for Errata and early samples
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 7735 $ @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+
+#include "AGESA.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c
new file mode 100755
index 0000000000..dba28799c0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c
@@ -0,0 +1,573 @@
+/**
+ * @file
+ *
+ * mnreghy.c
+ *
+ * Common Northbridge register related functions for Hydra
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/HY)
+ * @e \$Revision: 13632 $ @e \$Date: 2009-05-13 10:10:13 -0500 (Wed, 13 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnhy.h"
+#include "merrhdl.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemNIsIdSupportedHy
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a Hydra.
+ *     @return          FALSE - This node is not a Hydra.
+ *
+ */
+BOOLEAN
+MemNIsIdSupportedHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+  if ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *      This function calculates the memory channel index relative to the
+ *      socket, taking the Die number, the Dct, and the channel.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Dct
+ *     @param[in] Channel
+ *
+ */
+UINT8
+MemNGetSocketRelativeChannelHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  )
+{
+  return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field to be programmed
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNCmnGetSetFieldHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  TSEFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT8 IsLinked;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = (UINT8) TSEFO_TYPE (Address);
+      IsLinked = (UINT8) TSEFO_LINKED (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
+          Address |= 0x0100;
+        }
+      }
+
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+        IsLinked = 0;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+      if (Type == NB_ACCESS) {
+        PciAddr.AddressValue = Address;
+        PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+        PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+        PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+        Address = PciAddr.AddressValue;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else if (Type == DCT_EXTRA) {
+        MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+        MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+          MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        } else if (Type == DCT_EXTRA) {
+          MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+          MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+          MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+        } else {
+          IDS_ERROR_TRAP;
+        }
+        if (IsLinked) {
+          MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+        if (IsLinked) {
+          Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   NBRegTable[]  - Pointer to the bit field data structure
+ *
+ */
+
+VOID
+InitNBRegTableHy (
+  IN OUT   TSEFO NBRegTable[]
+  )
+{
+  UINT16 i;
+  for (i = 0; i < BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  6,  4, BFNodeCnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  1,  1, BFDramMemHoistValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20,  0, BFDramBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20,  0, BFDramLimitAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31,  0, BFDramConfigMiscReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31,  0, BFDramCtrlMiscReg2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31,  0, BFDctExtraOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31,  0, BFDctExtraDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31,  0, BFMctCfgLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31,  0, BFExtMctCfgLoReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31,  0, BFMcaNbCtlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44),  2,  2, BFSyncOnUcEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31,  0, BFMcaNbStatusLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31,  0, BFMcaNbStatusHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58),  4,  0, BFDramScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12,  8, BFL2Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C),  0,  0, BFScrubReDirEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31,  0, BFScrubAddrLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31,  0, BFScrubAddrHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C),  4,  4, BFDisDatMsk);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8,  8, BFF3X188B8);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13,  8, BFNonSPDHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  3,  0, BFRdPtrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78),  9,  8, BFTwrrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFMrsLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  1,  0, BFBurstCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  3,  2, BFDrvImpCtrl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm_DDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  6,  4, BFTwrDDR3);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  3,  0, BFTcl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  6,  4, BFTrcd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88),  9,  7, BFTrp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15,  0, BFNonSPD);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  3,  0, BFTrwtWB);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  7,  4, BFTrwtTO);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C),  9,  8, BFTwtr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  1,  1, BFExitSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  5,  4, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  8,  8, BFParEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  2,  0, BFMemClkFreq);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  3,  3, BFMemClkFreqVal);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4),  8,  8, BFODTSEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  2,  2, BFDdr3FourSocketCh);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  7,  7, BFProgOdtEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15,  8, BFCtrlWordCS);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  0,  0, BFDctSelHiRngEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  1,  1, BFDctSelHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  2,  2, BFDctSelIntLvEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  3,  3, BFMemClrInit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  4,  4, BFDctGangEn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  5,  5, BFDctDatIntLv);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  7,  6, BFDctSelIntLvAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8,  8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  9,  9, BFMemClrBusy);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  1,  0, BFDctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11,  7, BFMctPrefReqLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  1,  0, BFAdapPrefMissRatio);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  3,  2, BFAdapPrefPosStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0),  5,  4, BFAdapPrefNegStep);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10,  8, BFCohPrefPrbLmt);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8),  7, 5, BFDdrMaxRate);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  9,  8, BFAddrCmdDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  3,  3, BFPhyFenceTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53,  8,  0, BFWrtLvErr);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  7,  5, BFD3Cmp0PCal);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A,  2,  0, BFD3Cmp0NCal);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 20, 16, BFPhyFence);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 13, 12, BFCKETri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C, 11,  8, BFODTTri);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0C,  7,  0, BFChipSelTri);
+
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x180, 31, 0, BFPhyRODTCSLow);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x181, 31, 0, BFPhyRODTCSHigh);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x182, 31, 0, BFPhyWODTCSLow);
+  MAKE_TSEFO (NBRegTable, DCT_EXTRA,  0x183, 31, 0, BFPhyWODTCSHigh);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS,  0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime);
+
+  LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
+  LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
+  LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
+
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
new file mode 100755
index 0000000000..3579eb7a81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c
@@ -0,0 +1,462 @@
+/**
+ * @file
+ *
+ * mnNi.c
+ *
+ * Common Northbridge functions for Nile
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/NI)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mnda.h"
+#include "mnNi.h"
+#include "mu.h"
+#include "S3.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_NI_MNNI_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   (UINT32) 0x20000000
+#define CHANNEL_SELECT  (UINT32) 0x10000000
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
+ *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
+ *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
+ *
+ *     @return     Boolean indicating that this is the correct memory
+ *                 controller type for the node number that was passed in.
+ */
+
+BOOLEAN
+MemConstructNBBlockNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 SpdSocketIndex;
+  UINT8 SpdChannelIndex;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->SharedPtr = SharedPtr;
+
+  MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
+  NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
+  }
+  NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+
+  //
+  // Initialize Socket List
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
+    MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
+  }
+
+  MemNInitNBDataDA (NBPtr);
+
+  FeatPtr->InitCPG (NBPtr);
+  NBPtr->FeatPtr = FeatPtr;
+
+  //
+  // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
+  // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
+  // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
+  // dimm types(QR or not) are known. This is done in the Technology block constructor.
+  //
+  // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
+  // This will facilitate modifications due to some processors that might
+  // map the DCT-CHANNEL differently.
+  //
+  SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
+  //
+  // Traverse the Dct/Channel structures
+  //
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
+      //
+      // Calculate the number of Dimms on this channel using the
+      //   die/dct/channel to Socket/channel conversion.
+      //
+      SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                            NBPtr->MCTPtr->SocketId,
+                                            MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
+                                            &MemPtr->StdHeader);
+      NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
+    }
+  }
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT32 i;
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  InitNBRegTableDA (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
+  NBPtr->Ganged = FALSE;
+  NBPtr->PosTrnPattern = POS_PATTERN_72B;
+  NBPtr->MemCleared = FALSE;
+  NBPtr->StartupSpeed = DDR800_FREQUENCY;
+  NBPtr->RcvrEnDlyLimit = 0xFF;
+  NBPtr->DefDctSelIntLvAddr = 3;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
+  NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->InitializeMCT = MemNInitializeMctNb;
+  NBPtr->FinalizeMCT = MemNFinalizeMctDA;
+  NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
+  NBPtr->sendZQCmd = MemNSendZQCmdNb;
+  NBPtr->WritePattern = MemNWritePatternDA;
+  NBPtr->ReadPattern = MemNReadPatternDA;
+  NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
+  NBPtr->StitchMemory = MemNStitchMemoryNb;
+  NBPtr->AutoConfig = memNAutoConfigDA;
+  NBPtr->PlatformSpec = MemNPlatformSpecNb;
+  NBPtr->InitMCT = MemNInitMCTNb;
+  NBPtr->DisableDCT = MemNDisableDCTNb;
+  NBPtr->StartupDCT = MemNStartupDCTNb;
+  NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
+  NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
+  NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
+  NBPtr->ChangeNbFrequency = MemNDefFalseNb;
+  NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
+  NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
+  NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
+  NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
+  NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
+  NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
+  NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
+  NBPtr->OtherTiming = MemNOtherTimingDA;
+  NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
+  NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
+  NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
+  NBPtr->TrainingFlow = MemNTrainingFlowNb;
+  NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
+  MemNInitNBDataNb (NBPtr);
+  NBPtr->PollBitField = MemNPollBitFieldNb;
+  NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
+  NBPtr->BrdcstSet = MemNBrdcstSetNb;
+  NBPtr->GetTrainDly = MemNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemNSetTrainDlyNb;
+  NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
+  NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
+  NBPtr->RankEnabled = MemNRankEnabledNb;
+  NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
+  NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA;
+  NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
+  NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
+  NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
+  NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
+  NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
+  NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
+  NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
+  NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
+  NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
+  NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
+  NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
+  NBPtr->CSPerChannel = MemNCSPerChannelNb;
+  NBPtr->CSPerDelay = MemNCSPerDelayNb;
+  NBPtr->FlushPattern = MemNFlushPatternNb;
+  NBPtr->GetUmaSize = MemNGetUmaSizeNb;
+  NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
+  NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
+  NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
+
+  NBPtr->IsSupported[SetSpareEn] = TRUE;
+  NBPtr->IsSupported[CheckSpareEn] = TRUE;
+  NBPtr->IsSupported[SetDllShutDown] = TRUE;
+  NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
+  NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
+  NBPtr->IsSupported[Check1GAlign] = TRUE;
+  NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
+  NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
+  NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
+  NBPtr->IsSupported[CheckFindPSDct] = TRUE;
+  NBPtr->IsSupported[CheckDllStdBy] = TRUE;
+  NBPtr->IsSupported[CheckDynamicDramTerm] = TRUE;
+  NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->IsSupported[CheckDllRegDis] = TRUE;
+  NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the default values in the MEM_DATA_STRUCT
+ *
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+VOID
+MemNInitDefaultsNi (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Channel;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  ASSERT (MemPtr != NULL);
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xE0;
+  RefPtr->UmaMode = UserOptions.CfgUmaMode;
+  RefPtr->UmaSize = UserOptions.CfgUmaSize;
+  RefPtr->MemHoleRemapping = TRUE;
+  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
+
+  // Dram Timing
+  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
+  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
+      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
+    }
+  }
+
+  // Memory Clear
+  RefPtr->EnableMemClr = TRUE;
+
+  // TableBasedAlterations
+  RefPtr->TableBasedAlterations = NULL;
+
+  // Platform config table
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+
+  // Memory Restore
+  RefPtr->MemRestoreCtl = FALSE;
+  RefPtr->SaveMemContextCtl = FALSE;
+  AmdS3ParamsInitializer (&RefPtr->MemContext);
+
+  // Dram Configuration
+  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
+  RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
+  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
+  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
+  RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
+  RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
+
+  // Dram Power
+  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
+
+  // ECC
+  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Pattern[] - Pattern to write
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNWritePatternNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function reads training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Buffer[] - Buffer to fill
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNReadPatternNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUReadCachelines (Buffer, Address, ClCount);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h
new file mode 100755
index 0000000000..a36d7e1dce
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h
@@ -0,0 +1,109 @@
+/**
+ * @file
+ *
+ * mnNi.h
+ *
+ * Northbridge Ni for Nile
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MNNI_H_
+#define _MNNI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructNBBlockNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *SharedPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNInitNBDataNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDefaultsNi (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemNWritePatternNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemNReadPatternNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+#endif  /* _MNNI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c
new file mode 100755
index 0000000000..fb6af1ed95
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c
@@ -0,0 +1,738 @@
+/**
+ * @file
+ *
+ * mns3Ni.c
+ *
+ * Ni memory specific function to support S3 resume
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/NI)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "mnda.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mnS3Ni.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_NI_MNS3NI_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstNi (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  );
+
+VOID
+STATIC
+MemNS3SetSpecialPCIRegNi (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+STATIC
+MemNS3ExitSelfRefRegNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+PCI_SPECIAL_CASE PciSpecialCaseFuncNi[] = {
+  {MemNS3GetCSRNb, MemNS3SetCSRNb},
+  {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegNi},
+  {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
+};
+
+PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorNi[] = {
+  {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x48,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x50,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x58,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x60,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x68,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x70,  0xFFFF3F03},
+  {{0, 0, 0}, FUNC_1, 0x78,  0xFFFF3F03},
+  {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x4C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x54,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x5C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x64,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x6C,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x74,  0xFFFF07FF},
+  {{0, 0, 0}, FUNC_1, 0x7C,  0xFFFF07FF},
+  {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
+  {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
+  {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
+  {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
+  {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
+  {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
+  {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
+};
+
+CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefNi = {
+  0,
+  (sizeof (S3PciPreSelfRefDescriptorNi) / sizeof (PCI_REG_DESCRIPTOR)),
+  S3PciPreSelfRefDescriptorNi,
+  NULL
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorNi[] = {
+   // DCT 0
+  {{0, 0, 0}, FUNC_2, 0x40,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x44,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x48,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x4C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x50,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x54,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x58,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x5C,  0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x60,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x64,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x68,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x6C,  0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x78,  0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x7C,  0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x80,  0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x84,  0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x88,  0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x8C,  0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x90,  0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0xA8,  0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),  0x30333333, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),  0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),  0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 322
+  {{2, 2, 1}, DCT0,   BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  //errata 263
+  {{2, 2, 1}, DCT0,   BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  // Dll regulator disable
+  {{2, 2, 1}, DCT0,   BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+   // DCT 1
+  {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 322
+  {{2, 2, 1}, DCT1,   BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // errata 263
+  {{2, 2, 1}, DCT1,   BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  // Dll regulator disable
+  {{2, 2, 1}, DCT1,   BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore F2x[1,0]94 right before exit self refresh
+  {{0, 0, 0}, FUNC_2, 0x94,  0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefNi = {
+  0,
+  (sizeof (S3CPciPreSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPreSelfDescriptorNi,
+  PciSpecialCaseFuncNi
+};
+
+CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorNi[] = {
+  // DCT0
+  {{2, 2, 1}, DCT0,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000001FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000001FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000001FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000001FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x01FF01FF, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24),  0x01FF01FF, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27),  0x01FF01FF, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x01FF01FF, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0x7F7F7F7F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x0000007F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3F3F3F3F, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07),  0x0000003F, DCT0_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),  0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D),  0x23772377, DCT0_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_DDR3_MASK, 0x01},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44),  0x00FF00FF, DCT0_DDR3_MASK, 0x04},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47),  0x00FF00FF, DCT0_DDR3_MASK, 0x10},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A),  0x00FF00FF, DCT0_DDR3_MASK, 0x40},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+
+    // DCT1
+  {{2, 2, 1}, DCT1,   BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12),  0x000001FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15),  0x000001FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18),  0x000001FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B),  0x000001FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21),  0x01FF01FF, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24),  0x01FF01FF, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27),  0x01FF01FF, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A),  0x01FF01FF, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02),  0x7F7F7F7F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03),  0x0000007F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102),  0x7F7F7F7F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103),  0x0000007F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202),  0x7F7F7F7F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203),  0x0000007F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302),  0x7F7F7F7F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303),  0x0000007F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06),  0x3F3F3F3F, DCT1_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07),  0x0000003F, DCT1_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106),  0x3F3F3F3F, DCT1_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107),  0x0000003F, DCT1_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206),  0x3F3F3F3F, DCT1_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207),  0x0000003F, DCT1_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306),  0x3F3F3F3F, DCT1_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307),  0x0000003F, DCT1_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D),  0x23772377, DCT1_MASK, ANY_DIMM_MASK},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32),  0x000000FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35),  0x000000FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38),  0x000000FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B),  0x000000FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41),  0x00FF00FF, DCT1_DDR3_MASK, 0x02},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44),  0x00FF00FF, DCT1_DDR3_MASK, 0x08},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47),  0x00FF00FF, DCT1_DDR3_MASK, 0x20},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A),  0x00FF00FF, DCT1_DDR3_MASK, 0x80},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+
+  // DllShutDown
+  {{2, 2, 1}, DCT0,   BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT0,   BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 2, 1}, DCT1,   BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT1,   BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
+
+  // Restore scrubber related registers after restoring training related registers
+  {{0, 0, 0}, FUNC_3, 0x44,  0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_3, 0x58,  0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{2, 1, 1}, DCT0,   BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
+};
+
+CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefNi = {
+  0,
+  (sizeof (S3CPciPostSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  S3CPciPostSelfDescriptorNi,
+  PciSpecialCaseFuncNi
+};
+
+MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorNi[] = {
+  {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
+  {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
+  {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
+};
+
+CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefNi = {
+  0,
+  (sizeof (S3MSRPreSelfRefDescriptorNi) / sizeof (MSR_REG_DESCRIPTOR)),
+  S3MSRPreSelfRefDescriptorNi,
+  NULL
+};
+
+VOID *MemS3RegListNi[] = {
+  (VOID *)&S3PciPreSelfRefNi,
+  NULL,
+  (VOID *)&S3CPciPreSelfRefNi,
+  (VOID *)&S3CPciPostSelfRefNi,
+  (VOID *)&S3MSRPreSelfRefNi,
+  NULL,
+  NULL,
+  NULL
+};
+
+CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = {
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
+  SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
+};
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for S3 resume
+ *
+ *     @param[in,out]   *S3NBPtr   - Pointer to MEM_NB_BLOCK.
+ *     @param[in,out]   *MemPtr  - Pointer to MEM_DATA_STRUCT.
+ *     @param[in]       NodeID   - Node ID of the target node.
+ *
+ *      @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN
+MemS3ResumeConstructNBBlockNi (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  INT32 i;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
+  NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
+  InitNBRegTableDA (NBPtr->NBRegTable);
+  NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->Ganged = FALSE;
+  NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
+  NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
+
+  NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+  NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
+  NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegNi;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrNi;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstNi;
+  ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)) * sizeof (UINT32);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the register list for each device for Ni
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *     @return          UINT16 - size of the device descriptor on the target node.
+ */
+UINT16
+STATIC
+MemNS3GetRegLstPtrNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  UINT8 i;
+  UINT16 Size;
+  Size = 0;
+  for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
+    DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
+    DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
+      Size += sizeof (PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
+    DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
+    DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
+      Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
+    DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
+      Size += sizeof (MSR_DEVICE_DESCRIPTOR);
+    }
+    DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
+    DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
+    if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
+      DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
+      Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
+    }
+  }
+  return Size;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function return the register list according to the register ID.
+ *
+ *     @param[in]   RegisterLstID - value of the Register list ID.
+ *     @param[out]  **RegisterHeader - pointer to the address of the register list.
+ *     @return      none
+ */
+AGESA_STATUS
+STATIC
+MemNS3GetDeviceRegLstNi (
+  IN       UINT32 RegisterLstID,
+     OUT   VOID **RegisterHeader
+  )
+{
+  if (RegisterLstID >= (sizeof (MemS3RegListNi) / sizeof (VOID *))) {
+    ASSERT(FALSE); // RegisterListID exceeded size of Register list
+    return AGESA_FATAL;
+  }
+  if (MemS3RegListNi[RegisterLstID] != NULL) {
+    *RegisterHeader = MemS3RegListNi[RegisterLstID];
+    return AGESA_SUCCESS;
+  }
+  ASSERT(FALSE); // Device register list error
+  return AGESA_FATAL;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *      @return         none
+ */
+VOID
+STATIC
+MemNS3SetSpecialPCIRegNi (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (Address.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_DA);
+    // Save the value in the heap at appropriate offset based on the index
+    // of the target register in the special case array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) {
+        if (SpecialCasePCIRegNi[i] == Address.Address.Register) {
+          *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
+        }
+      }
+    }
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function stores special case register on the heap.
+ *
+ *     @param[in,out]  *NBPtr - Pointer to the northbridge block.
+ *     @param[in,out]  *StdHeader - Config handle for library and services.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3ExitSelfRefRegNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  UINT8 i;
+  PCI_ADDR PciAddr;
+  UINT32 Value;
+  UINT8 NodeID;
+  UINT8 Offset;
+  S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
+
+  Offset = 0;
+  PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
+  PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
+  PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
+  PciAddr.Address.Function = 2;
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
+    SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
+    // Get the node ID of the target die.
+    NodeID = (UINT8) (PciAddr.Address.Device - 24);
+    for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
+      if (SpecialHeapHeader[i].Node == NodeID) {
+        // Get the offset in the heap for the target die.
+        Offset = SpecialHeapHeader[i].Offset;
+        break;
+      }
+    }
+    ASSERT (i < MAX_NODES_SUPPORTED_DA);
+    // Restore the value one by one in the sequence of the special case register array.
+    if (Offset != 0) {
+      for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) {
+        PciAddr.Address.Register = SpecialCasePCIRegNi[i];
+        Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
+        MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h
new file mode 100755
index 0000000000..8b5a3dba2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mnS3Ni.h
+ *
+ * S3 resume memory related function for Ni.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/NI)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MNS3DA_H_
+#define _MNS3DA_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+/// ID for register list of HY
+typedef enum {
+  PCI_LST_ESR_DA,   ///< Assign 0x0000 for PCI register list for pre exit self refresh.
+  PCI_LST_DA,       ///< Assign 0x0001 for PCI register list for post exist self refresh.
+  CPCI_LST_ESR_DA,  ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
+  CPCI_LST_DA,      ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
+  MSR_LST_ESR_DA,   ///< Assign 0x0004 for MSR register list for pre exit self refresh.
+  MSR_LST_DA,       ///< Assign 0x0005 for MSR register list for post exit self refresh.
+  CMSR_LST_ESR_DA,  ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
+  CMSR_LST_DA,      ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
+} RegisterListIDDA;
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif //_MNS3DA_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c
new file mode 100755
index 0000000000..df93fea53d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c
@@ -0,0 +1,538 @@
+/**
+ * @file
+ *
+ * mn.c
+ *
+ * Common Northbridge functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MN_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNDefaultFamilyHookNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes member functions and variables of NB block.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitNBDataNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT32 i;
+  UINT8 *BytePtr;
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+  NBPtr->PsPtr = NBPtr->PSBlock;
+
+  BytePtr = (UINT8 *) (NBPtr->DctCache);
+  for (i = 0; i < sizeof (NBPtr->DctCache); i++) {
+    *BytePtr++ = 0;
+  }
+
+  for (i = 0; i < EnumSize; i++) {
+    NBPtr->IsSupported[i] = FALSE;
+  }
+
+  for (i = 0; i < NumberOfHooks; i++) {
+    NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb;
+  }
+
+  NBPtr->SwitchDCT = MemNSwitchDCTNb;
+  NBPtr->SwitchChannel = MemNSwitchChannelNb;
+  NBPtr->GetBitField = MemNGetBitFieldNb;
+  NBPtr->SetBitField = MemNSetBitFieldNb;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   Get System address of Chipselect RJ 16 bits (Addr[47:16])
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Receiver - Chipselect to be targeted [0-7]
+ *     @param[out]      AddrPtr -  Pointer to System Address [47:16]
+ *
+ *     @return      TRUE  - Address is valid
+ *     @return      FALSE  - Address is not valid
+ */
+
+BOOLEAN
+MemNGetMCTSysAddrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver,
+     OUT   UINT32 *AddrPtr
+  )
+{
+  S_UINT64 SMsr;
+  UINT32 CSBase;
+  UINT32 HoleBase;
+  UINT32 DctSelBaseAddr;
+  UINT32 BottomUma;
+  DIE_STRUCT *MCTPtr;
+  MEM_DATA_STRUCT *MemPtr;
+
+  MCTPtr = NBPtr->MCTPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  ASSERT (Receiver < 8);
+
+  CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
+  if (CSBase & 1) {
+    ASSERT ((CSBase & 0xE0) == 0);   // Should not enable CS interleaving before DQS training.
+
+    // Scale base address from [39:8] to [47:16]
+    CSBase >>= 8;
+
+    HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF;
+
+    if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) {
+      DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16);
+      if (DctSelBaseAddr > HoleBase) {
+        DctSelBaseAddr -= _4GB_RJ16 - HoleBase;
+      }
+      CSBase += DctSelBaseAddr;
+    } else {
+      CSBase += MCTPtr->NodeSysBase;
+    }
+
+    if (CSBase >= HoleBase) {
+      CSBase += _4GB_RJ16 - HoleBase;
+    }
+
+    CSBase += (UINT32)1 << (21 - 16);  // Add 2MB offset to avoid compat area.
+    if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) {
+      CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0;
+    }
+
+    if (MCTPtr->Status[SbHWHole]) {
+      if (MCTPtr->Status[SbSWNodeHole]) {
+        LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+        if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) {
+          return FALSE;
+        }
+      }
+    }
+
+    BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16;
+    if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) {
+      return FALSE;
+    }
+    *AddrPtr = CSBase;
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function determines if a Rank is enabled.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]    Receiver - Receiver to check
+ *     @return - FALSE
+ *
+ */
+
+BOOLEAN
+MemNRankEnabledNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT32 CSBase;
+  CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
+  if (CSBase & 1) {
+    return  TRUE;
+  } else {
+    return  FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     This function sets the EccSymbolSize bit depending upon configurations
+ *     and system override.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSetEccSymbolSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16 X4DimmsOnly;
+  BOOLEAN Size;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+
+  ASSERT (NBPtr != NULL);
+
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  // Determine if this node has only x4 DRAM parts
+  X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present);
+  //
+  // Check if EccSymbolSize BKDG value is overridden
+  //
+  if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) {
+    Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE;
+  } else {
+    if (X4DimmsOnly && MCTPtr->GangedMode) {
+      Size = FALSE;
+    } else {
+      Size = TRUE;
+    }
+  }
+  IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader));
+  MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the training control flow
+ *      The DDR3 mode bit must be set prior to calling this function
+ *
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+BOOLEAN
+MemNTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
+    memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
+  } else {
+    memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is the default NB return function
+ *
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+BOOLEAN
+MemNDefNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is used in place of an un-supported function.
+ *
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+BOOLEAN
+MemNDefFalseNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return FALSE;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function flushes the  training pattern
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+MemNFlushPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  // Due to speculative execution during MemUReadCachelines, we must
+  //  flush one more cache line than we read.
+  MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function compares test pattern with data in buffer and
+ *     return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]   *NBPtr    - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  - Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @return  PASS - Bitmap of results of comparison
+ */
+
+UINT16
+MemNCompareTestPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  UINT16 i;
+  UINT16 Pass;
+  UINT8 ColumnCount;
+  UINT8 FailingBitMask[8];
+
+  ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
+
+  ColumnCount = NBPtr->ChannelPtr->ColumnCount;
+  Pass = 0xFFFF;
+  //
+  // Clear Failing Bit Mask
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    FailingBitMask[i] = 0;
+  }
+
+  if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
+    i = 8;   // DCT 1 in ganged mode
+  } else {
+    i = 0;
+  }
+
+  for (; i < ByteCount; i++) {
+    if (Buffer[i] != Pattern[i]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (i % 8));    // clear bit n
+      FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]);
+    }
+
+    if (NBPtr->Ganged && ((i & 7) == 7)) {
+      i += 8;     // if ganged, skip over other Channel's Data
+    }
+  }
+  //
+  // Accumulate Failing bit data
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
+      FailingBitMask[i];
+  }
+
+  return Pass;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function compares test pattern with data in buffer and
+ *     return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  - Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @retval  PASS - Bitmap of results of comparison
+ * ----------------------------------------------------------------------------
+ */
+UINT16
+MemNInsDlyCompareTestPatternNb (
+  IN       MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  UINT16 i;
+  UINT16 Pass;
+  UINT16 BeatOffset;
+  UINT16 BeatCnt;
+  UINT8 ColumnCount;
+  UINT8 FailingBitMask[8];
+
+  ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
+
+  ColumnCount = NBPtr->ChannelPtr->ColumnCount;
+  Pass = 0xFFFF;
+  //
+  // Clear Failing Bit Mask
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    FailingBitMask[i] = 0;
+  }
+
+  if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
+    i = 8;   // DCT 1 in ganged mode
+  } else {
+    i = 0;
+  }
+
+  if (NBPtr->Ganged) {
+    BeatOffset = 16;
+  } else {
+    BeatOffset = 8;
+  }
+
+  BeatCnt = 0;
+  for (; i < ByteCount; i++) {
+
+    if (Buffer[i] != Pattern[i + BeatOffset]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (i % 8));    // clear bit n
+      FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]);
+    }
+
+    if ((i & 7) == 7) {
+      if (NBPtr->Ganged) {
+        i += 8;     // if ganged, skip over other Channel's Data
+      }
+      BeatCnt++;
+    }
+
+    if ((BeatCnt & 3) == 3) {
+      // Skip last data beat of a 4-beat burst.
+      BeatCnt++;
+      i = i + BeatOffset;
+    }
+  }
+  //
+  // Accumulate Failing bit data
+  //
+  for (i = 0; i < sizeof (FailingBitMask); i++) {
+    NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
+      FailingBitMask[i];
+  }
+
+  return Pass;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     This function is an empty function used to intialize FamilySpecificHook array
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return  TRUE - always
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNDefaultFamilyHookNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  return TRUE;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c
new file mode 100755
index 0000000000..d0dd6bdd3d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c
@@ -0,0 +1,677 @@
+/**
+ * @file
+ *
+ * mnS3.c
+ *
+ * Common Northbridge S3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "S3.h"
+#include "mfs3.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNS3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemNS3GetSetBitField (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       BOOLEAN IsSet,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+BOOLEAN
+STATIC
+MemNS3GetDummyReadAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+     OUT   UINT64 *TestAddr
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes the S3 resume for a node
+ *
+ *     @param[in,out]   *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
+ *     @param[in]       NodeID - The Node id of the target die
+ *
+ *     @return         BOOLEAN
+ *                         TRUE - This is the correct constructor for the targeted node.
+ *                         FALSE - This isn't the correct constructor for the targeted node.
+ */
+
+BOOLEAN
+MemNS3ResumeNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 DCT;
+  BOOLEAN GangedEn;
+  UINT64 TestAddr;
+  MEM_NB_BLOCK *NBPtr;
+  MEM_DATA_STRUCT *MemPtr;
+
+  NBPtr = S3NBPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE;
+
+  // Errata before S3 resume sequence
+
+  // Resume Sequence
+  // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+
+  // Program F2x[1, 0]94[MemClkFreqVal] = 1.
+  // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
+      MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
+      while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {}
+    }
+  }
+
+  // Program F2x9C_x08[DisAutoComp]=0
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+  //    BIOS must wait 750 us for the phy compensation engine
+  //    to reinitialize.
+  MemFS3Wait10ns (75000, NBPtr->MemPtr);
+
+  // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C
+  // 4. Restore F2x[1,0]9C_x04
+  // Get the register value from the heap.
+  S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader);
+
+  // Add a hook here
+  AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+  if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
+  }
+  AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
+
+  // 5. Set F2x[1,0]90[ExitSelfRef]
+  // 6. Wait for F2x[1,0]90[ExitSelfRef]=0
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
+      MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
+      while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
+    }
+    if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
+      MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
+      if (DCT == 0) {
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
+      }
+      // NOTE: wait 512 clocks for DLL-relock
+      MemFS3Wait10ns (50000, NBPtr->MemPtr);  // wait 500us
+    }
+  }
+
+  // Errata After S3 resume sequence
+  // Errata 350
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    MemNSwitchDCTNb (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
+      if (!((DCT == 1) && GangedEn)) {
+        if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) {
+          // Do dummy read
+          Read64Mem8 (TestAddr);
+        }
+      }
+      MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
+      MemFS3Wait10ns (60, NBPtr->MemPtr);   // Wait 300ns
+      MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
+      MemFS3Wait10ns (400, NBPtr->MemPtr);  // Wait 2us
+    }
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function returns the conditional PCI device mask
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in, out]  *DescriptPtr - Pointer to DESCRIPTOR_GROUP
+ *      @return         none
+ */
+VOID
+MemNS3GetConPCIMaskNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  )
+{
+  BIT_FIELD_NAME bitfield;
+  UINT32 RegVal;
+  UINT8 DCT;
+  UINT8 DimmMask;
+  UINT8 BadDimmMask;
+  UINT8 DctGangEn;
+  BOOLEAN IsDDR3;
+
+  IsDDR3 = FALSE;
+  DimmMask = 0;
+  BadDimmMask = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    NBPtr->SwitchDCT (NBPtr, DCT);
+    if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
+      if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
+        IsDDR3 = TRUE;
+      }
+      for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
+        RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
+        if (RegVal & 0x3) {
+          DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
+        } else if (RegVal & 0x4) {
+          BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
+        }
+      }
+    }
+  }
+
+  NBPtr->SwitchDCT (NBPtr, 0);
+  DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn);
+  // Set channel mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
+  for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
+    if (DimmMask & (0x55 << DCT)) {
+      // Set mask before exit self refresh
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
+      // Set mask after exit self refresh
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT;
+      // Set DDR3 mask if Dimms present are DDR3
+      if (IsDDR3) {
+        DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
+      }
+    } else if (BadDimmMask & (0x55 << DCT)) {
+      // Need to save function 2 registers for bad dimm
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
+    }
+  }
+  // Set dimm mask
+  DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
+  DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
+  if (DctGangEn) {
+    // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers
+    // need to be restored on both channels in ganged mode
+    DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2;
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2;
+    if (IsDDR3) {
+      DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4);
+      DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4);
+    }
+    // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored
+    // in that time frame don't care about individual dimm population. We want to
+    // skip registers that are not needed to be restored for DCT1 in ganged mode.
+    //
+    // After exit self refresh, training registers will be restored and will only be
+    // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1.
+    //
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1;
+  }
+
+  // Adjust the mask if there is no dimm on the node
+  if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) &&
+    (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) {
+    DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
+    DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function read the value of CSR register.
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3GetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 ExtendOffset;
+  UINT32 ValueRead;
+  UINT8 DataPort;
+
+  ValueRead = 0;
+  ExtendOffset = Address.Address.Register;
+  if (ExtendOffset & 0x800) {
+    Address.Address.Register = 0xF0;
+    DataPort = 0xF4;
+  } else {
+    Address.Address.Register = 0x98;
+    DataPort = 0x9C;
+  }
+  if (ExtendOffset & 0x400) {
+    Address.Address.Register |= 0x100;
+  }
+  ExtendOffset &= 0x3FF;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
+  while (((ValueRead >> 31) & 1) == 0) {
+    LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
+  }
+  Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort;
+  LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function write to a CSR register
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 ExtendOffset;
+  UINT32 ValueRead;
+  UINT32 ValueWrite;
+  UINT8 DataOffset;
+
+  ValueRead = 0;
+  ExtendOffset = Address.Address.Register;
+  // Check the flag and see the type of the access
+  if (ExtendOffset & 0x800) {
+    Address.Address.Register = 0xF4;
+    DataOffset = 0xF0;
+  } else {
+    Address.Address.Register = 0x9C;
+    DataOffset = 0x98;
+  }
+  if (ExtendOffset & 0x400) {
+    Address.Address.Register |= 0x100;
+  }
+  ExtendOffset &= 0x3FF;
+  ExtendOffset |= 0x40000000;
+  switch (AccessWidth) {
+  case AccessS3SaveWidth8:
+    ValueWrite = *(UINT8 *) Value;
+    break;
+  case AccessS3SaveWidth16:
+    ValueWrite = *(UINT16 *) Value;
+    break;
+  case AccessS3SaveWidth32:
+    ValueWrite = *(UINT32 *) Value;
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr);
+  Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset;
+  LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
+  while (((ValueRead >> 31) & 1) == 0) {
+    LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function reads register bitfield
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value be read.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3GetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function writes register bitfield
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function restores scrubber base register
+ *
+ *     @param[in,out]   *NBPtr - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Node - The Node id of the target die
+ *
+ */
+VOID
+MemNS3RestoreScrubNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Node
+  )
+{
+  UINT32 ScrubAddrRJ16;
+
+  ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
+  ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24;
+  MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
+  MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------*/
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function reads and writes register bitfield
+ *
+ *     @param[in]   AccessWidth - Access width of the register
+ *     @param[in]   Address - address of the CSR register in PCI_ADDR format.
+ *     @param[in]   IsSet - if this is a register read or write
+ *     @param[in, out]  *Value - Pointer to the value be read or  written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+STATIC
+MemNS3GetSetBitField (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       BOOLEAN IsSet,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  BIT_FIELD_NAME BitField;
+  MEM_NB_BLOCK *NBPtr;
+  LOCATE_HEAP_PTR LocateBufferPtr;
+  S3_MEM_NB_BLOCK *S3NBPtr;
+  UINT32 RegValue;
+  UINT8 Die;
+
+  RegValue = 0;
+  // See which Node should be accessed
+  Die = (UINT8) (Address.Address.Device - 24);
+
+  LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
+  if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
+    S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
+    NBPtr = S3NBPtr[Die].NBPtr;
+
+    // Function field contains the DCT number
+    NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
+
+    // Get the bitfield name to be accessed
+    // Register field contains the bitfield name
+    BitField = (BIT_FIELD_NAME) Address.Address.Register;
+
+    if (IsSet) {
+      switch (AccessWidth) {
+      case AccessS3SaveWidth8:
+        RegValue = *(UINT8 *) Value;
+        break;
+      case AccessS3SaveWidth16:
+        RegValue = *(UINT16 *) Value;
+        break;
+      case AccessS3SaveWidth32:
+        RegValue = *(UINT32 *) Value;
+      default:
+        ASSERT (FALSE);
+      }
+      MemNSetBitFieldNb (NBPtr, BitField, RegValue);
+    } else {
+      RegValue = MemNGetBitFieldNb (NBPtr, BitField);
+
+      switch (AccessWidth) {
+      case AccessS3SaveWidth8:
+        *(UINT8 *) Value = (UINT8) RegValue;
+        break;
+      case AccessS3SaveWidth16:
+        *(UINT16 *) Value = (UINT16) RegValue;
+        break;
+      case AccessS3SaveWidth32:
+        *(UINT32 *) Value = RegValue;
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+    }
+  } else {
+    ASSERT (FALSE);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the dummy read address for a channel of a node.
+ *
+ *     @param[in, out]  *NBPtr - Pointer to northbridge block
+ *     @param[out]      *TestAddr - Pointer to the test address
+ *
+ *     @retval           TRUE - Dummy read address can be found
+ *     @retval           FALSE - Dummy read address cannot be found
+ *
+ */
+BOOLEAN
+STATIC
+MemNS3GetDummyReadAddr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+     OUT   UINT64 *TestAddr
+  )
+{
+  BOOLEAN DctSelIntlvEn;
+  UINT8 DramIntlvEn;
+  UINT8 DctSelIntlvAddr;
+  UINT8 IntLvRgnBaseAddr;
+  UINT8 IntLvRgnLmtAddr;
+  UINT8 IntLvRgnSize;
+  UINT32 DctSelBaseAddr;
+  UINT64 TOM;
+  BOOLEAN AddrFound;
+
+  AddrFound = TRUE;
+  // Check if Node interleaving is enabled
+  DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn);
+  if (DramIntlvEn != 0) {
+    // Set the address bits that identify the node
+    *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12;
+  } else {
+    *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27;
+  }
+
+  // Check if channel interleaving is enabled
+  DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn);
+  DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr);
+  if (!DctSelIntlvEn) {
+    if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
+      *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
+    }
+  } else {
+    DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr);
+    // Set the address bits that identify the channel
+    if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) {
+      *TestAddr |= (UINT64) NBPtr->Dct << 6;
+    } else if (DctSelIntlvAddr == 1) {
+      *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1));
+    } else if (DctSelIntlvAddr == 3) {
+      *TestAddr |= (UINT64) NBPtr->Dct << 9;
+    }
+  }
+  // Adding 2M to avoid conflict
+  *TestAddr += 0x200000;
+
+  // If memory hoisting is disabled, the address can fall into MMIO area
+  // Need to find an address out of MMIO area but belongs to the channel
+  // If the whole channel is in MMIO, then do not do dummy read.
+  //
+  LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader);
+  if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) {
+    if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
+      // This is the DCT that goes to high address range
+      if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) {
+        // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr
+        if (DctSelIntlvEn) {
+          *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
+        }
+      } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) {
+        // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as
+        // dummy read address
+        *TestAddr =  ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
+      } else {
+        AddrFound = FALSE;
+      }
+    } else {
+      // This is the DCT that only goes to low address range
+      if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) {
+        // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address
+        // Keep the lower bits for node and channel selection
+        *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
+      } else {
+        AddrFound = FALSE;
+      }
+    }
+  }
+
+  // Interleaved Swap Region handling
+  if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) {
+    IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr);
+    IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr);
+    IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize);
+    ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
+    if (((*TestAddr >> 34) == 0) &&
+      ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr))
+       || ((*TestAddr >> 27) < IntLvRgnSize))) {
+      *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
+    }
+  }
+
+  return AddrFound;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c
new file mode 100755
index 0000000000..76712ff0e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c
@@ -0,0 +1,2053 @@
+/**
+ * @file
+ *
+ * mndct.c
+ *
+ * Common Northbridge DCT support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 11758 $ @e \$Date: 2009-04-03 10:58:22 -0500 (Fri, 03 Apr 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mftds.h"
+#include "merrhdl.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNDCT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemNAfterStitchMemNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGet1KTFawTkNb (
+  IN       UINT8 k
+  );
+
+UINT8
+MemNGet2KTFawTkNb (
+  IN       UINT8 k
+  );
+
+VOID
+STATIC
+MemNQuarterMemClk2NClkNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *SubTotalPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function combines all the memory into a contiguous map.
+ *      Requires that Mask values for each bank be programmed first and that
+ *      the chip-select population indicator is correctly set.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNStitchMemoryNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN DSpareEn;
+  UINT32 NxtCSBase;
+  UINT32 CurCSBase;
+  UINT32 CsSize;
+  UINT32 BiggestBank;
+  UINT8 p;
+  UINT8 q;
+  UINT8 BiggestDimm;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  DSpareEn = FALSE;
+  if (NBPtr->IsSupported[SetSpareEn]) {
+    DSpareEn = FALSE;
+    if (RefPtr->GStatus[GsbEnDIMMSpareNW]) {
+      DSpareEn = TRUE;
+    }
+  }
+
+  DCTPtr->Timings.CsEnabled = 0;
+  NxtCSBase = 0;
+  for (p = 0; p < MAX_CS_PER_CHANNEL; p++) {
+    BiggestBank = 0;
+    BiggestDimm = 0;
+    for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
+      if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) {
+        if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) {
+          // (CSEnable|Spare==1)bank is not enabled yet
+          CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1));
+          if (CsSize != 0) {
+            CsSize += ((UINT32)1 << 19);
+            CsSize &= 0xFFF80000;
+          }
+          if (CsSize > BiggestBank) {
+            BiggestBank = CsSize;
+            BiggestDimm = q;
+          }
+        }
+      }
+    }
+
+    if (BiggestBank != 0) {
+      CurCSBase = NxtCSBase;
+      if (NBPtr->IsSupported[CheckSpareEn]) {
+        if (DSpareEn) {
+          CurCSBase = ((UINT32)1 << BFSpare);
+          DSpareEn = FALSE;
+        } else {
+          CurCSBase |= ((UINT32)1 << BFCSEnable);
+          NxtCSBase += BiggestBank;
+        }
+      } else {
+        CurCSBase |= ((UINT32)1 << BFCSEnable);
+        NxtCSBase += BiggestBank;
+      }
+      if ((BiggestDimm & 1) != 0) {
+        if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) {
+          CurCSBase |= ((UINT32)1 << BFOnDimmMirror);
+        }
+      }
+      MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase);
+      DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm);
+    }
+    if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) {
+      MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail);
+    }
+  }
+
+  if (NxtCSBase != 0) {
+    DCTPtr->Timings.DctMemSize = NxtCSBase >> 8;    // Scale base address from [39:8] to [47:16]
+    MemNAfterStitchMemNb (NBPtr);
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets platform specific config/timing values from the interface layer and
+ *   programs them into DCT.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST BIT_FIELD_NAME ChipletPDRegs[] = {
+  BFPhyClkConfig0,
+  BFPhyClkConfig3,
+  BFPhyClkConfig1,
+  BFPhyClkConfig2
+  };
+  CONST UINT8 ChipletPDClkDisMap[][2] = {
+  //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]]
+  {0, 1},
+  //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]]
+  {6, 7},
+  //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]]
+  {4, 5},
+  //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]]
+  {2, 3},
+  //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]]
+  {2, 5},
+  //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]]
+  {3, 4}
+  };
+
+  UINT8 MemClkDis;
+  UINT8 i;
+  UINT8 MemoryAllClocks;
+  UINT8 *MemClkDisMap;
+  UINT16 CsPresent;
+  UINT8 RegIndex;
+  UINT8 Cs1;
+  UINT8 Cs2;
+
+  if (!MemNGetPlatformCfgNb (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+
+  MemNProgramPlatformSpecNb (NBPtr);
+  if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS);
+
+  if (NBPtr->MCTPtr->GangedMode) {
+    MemNSwitchDCTNb (NBPtr, 1);
+    if (!MemNGetPlatformCfgNb (NBPtr)) {
+      IDS_ERROR_TRAP;
+    }
+    MemNProgramPlatformSpecNb (NBPtr);
+    MemNSwitchDCTNb (NBPtr, 0);
+  }
+
+  //======================================================================
+  // Disable unused MemClk to save power
+  //======================================================================
+  //
+  MemClkDis = 0;
+  MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn;
+  IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader));
+  if (!MemoryAllClocks) {
+    // Special Jedec SPD diagnostic bit - "enable all clocks"
+    if (!NBPtr->MCTPtr->Status[SbDiagClks]) {
+      MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0));
+      if (MemClkDisMap == NULL) {
+        MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap;
+      }
+
+      // Turn off the unused CS clocks
+      CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+      if (NBPtr->IsSupported[CheckMemClkCSPresent]) {
+        if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
+          // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register
+          // regardless of how many Ranks are on the DIMM (Single, Dual or Quad)
+          CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555;
+        }
+      }
+      for (i = 0; i < 8; i++) {
+        if ((CsPresent & MemClkDisMap[i]) == 0) {
+          MemClkDis |= (UINT8) (1 << i);
+        }
+      }
+      //Chiplet power down
+      for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) {
+        if ((NBPtr->Dct == 1) && (RegIndex >= 2)) {
+          Cs1 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]];
+          Cs2 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]];
+        } else {
+          Cs1 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]];
+          Cs2 =  MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]];
+        }
+        if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) {
+          MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10));
+        }
+      }
+    }
+  }
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis);
+
+  AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->MemNInitPhyComp (NBPtr);
+
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
+
+  if (NBPtr->IsSupported[CheckDynamicDramTerm]) {
+    // Program DramTerm for DDR2
+    if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) {
+      MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm);
+    } else {
+      // Dynamic Dynamic DramTerm for DDR3
+      // Dram Term for DDR3 may vary based on chip selects
+      MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm);
+    }
+  }
+  // Program DramTerm for DDR2
+  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) {
+    MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm);
+  } else {
+    // Dynamic Dynamic DramTerm for DDR3
+    // Dram Term for DDR3 may vary based on chip selects
+    MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm);
+  }
+
+  MemFInitTableDrive (NBPtr, MTAfterPlatformSpec);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets platform specific config/timing values from the interface layer and
+ *   programs them into DCT.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNPlatformSpecClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 MemClkDis;
+  UINT8 i;
+  UINT8 MemoryAllClocks;
+  UINT8 *MemClkDisMap;
+  UINT16 CsPresent;
+
+  if (!MemNGetPlatformCfgNb (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+
+  MemNProgramPlatformSpecNb (NBPtr);
+  if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) {
+    IDS_ERROR_TRAP;
+  }
+
+  //======================================================================
+  // Disable unused MemClk to save power
+  //======================================================================
+  //
+  MemClkDis = 0;
+  MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn;
+  IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader));
+  if (!MemoryAllClocks) {
+    // Special Jedec SPD diagnostic bit - "enable all clocks"
+    if (!NBPtr->MCTPtr->Status[SbDiagClks]) {
+      MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct);
+      if (MemClkDisMap == NULL) {
+        MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap;
+      }
+
+      // Turn off unused clocks
+      CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+      for (i = 0; i < 8; i++) {
+        if ((CsPresent & MemClkDisMap[i]) == 0) {
+          MemClkDis |= (UINT8) (1 << i);
+        }
+      }
+
+      // Turn off unused chiplets
+      if ((MemClkDis & 0x3) == 0x3) {
+        MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0, 0x0010);
+      }
+      if ((MemClkDis & 0xC) == 0xC) {
+        MemNSetBitFieldNb (NBPtr, BFPhyClkConfig1, 0x0010);
+      }
+    }
+  }
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis);
+  MemFInitTableDrive (NBPtr, MTAfterPlatformSpec);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disables the DCT and mem clock
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNDisableDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03);
+  MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F);
+  MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF);
+
+  // To maximize power savings when DisDramInterface=1b,
+  // all of the MemClkDis bits should also be set.
+  //
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+
+  MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function disables the DCT and mem clock for client NB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNDisableDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03);
+  MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F);
+  MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF);
+
+  //Wait for 24 MEMCLKs
+  MemUWait10ns (6, NBPtr->MemPtr);
+
+  // To maximize power savings when DisDramInterface=1b,
+  // all of the MemClkDis bits should also be set.
+  //
+  MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
+
+  MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
+
+  MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  This function initializes the DRAM devices on all DCTs at the same time
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1.
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // DisAutoComp is still being set since InitPhyComp
+
+  if (NBPtr->MCTPtr->NodeMemSize != 0) {
+    // Init MemClk frequency
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+
+
+    AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+    NBPtr->MemNBeforeDramInitNb (NBPtr);
+
+    AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
+    NBPtr->FeatPtr->DramInit (NBPtr->TechPtr);
+  }
+
+  // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0.
+  // 8. BIOS must wait 750 us for the phy compensation engine
+  //    to reinitialize.
+  // DisAutoComp will be cleared after DramEnabled turns to 1
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function initializes the DRAM devices on all DCTs at the same time
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNStartupDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+
+  // Update NB frequency for startup DDR speed
+  NBPtr->ChangeNbFrequency (NBPtr);
+
+  // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999.
+  MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000);
+
+  // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #193770.
+  MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118);
+
+  // Phy Voltage Level Programming
+  MemNPhyVoltageLevelClientNb (NBPtr);
+
+  // Run frequency change sequence
+  MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+  MemNProgramNbPstateDependentRegistersClientNb (NBPtr);
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+  MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+
+      // Phy fence programming
+      AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+      NBPtr->PhyFenceTraining (NBPtr);
+
+      // Phy compensation initialization
+      AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+      NBPtr->MemNInitPhyComp (NBPtr);
+    }
+  }
+
+  // Run DramInit sequence
+  AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->FeatPtr->DramInit (NBPtr->TechPtr);
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * MemNChangeFrequencyHy:
+ *
+ *  This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNChangeFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 Dummy;
+
+  TechPtr = NBPtr->TechPtr;
+  if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) {
+    // #107421
+    MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
+  }
+
+  //Program F2x[1,0]90[EnterSelfRefresh]=1.
+  //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
+  MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  //Program F2x9C_x08[DisAutoComp]=1
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+
+  //Program F2x[1, 0]94[MemClkFreqVal] = 0.
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
+
+  //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency.
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+
+  //Program F2x[1, 0]94[MemClkFreqVal] = 1.
+  MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+
+  //Wait until F2x[1, 0]94[FreqChgInProg]=0.
+  MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->IsSupported[CheckPhyFenceTraining]) {
+    //Perform Phy Fence retraining after frequency changed
+    AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+        AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+        MemNPhyFenceTrainingNb (NBPtr);
+      }
+    }
+  }
+
+  //Program F2x9C_x08[DisAutoComp]=0
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+
+  //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
+  //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
+  MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->MCTPtr->Status[SbRegistered]) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        TechPtr->FreqChgCtrlWrd (TechPtr);
+      }
+    }
+  }
+
+  //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns
+  MemUWait10ns (125, NBPtr->MemPtr);
+
+  if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) {
+    // #107421
+    MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
+  }
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+
+      //9.Configure the DCT to send initialization MR commands:
+      //  BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
+      //  Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values.
+      TechPtr->AutoCycTiming (TechPtr);
+      if (!MemNPlatformSpecNb (NBPtr)) {
+        IDS_ERROR_TRAP;
+      }
+
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+        if (NBPtr->IsSupported[CheckGetMCTSysAddr]) {
+          if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) {
+            // if chip select present
+            TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+            // NOTE: wait 512 clocks for DLL-relock
+            MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+          }
+        }
+        if (NBPtr->IsSupported[CheckSendAllMRCmds]) {
+          if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) {
+            // if chip select present
+            TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+          }
+        }
+      }
+      if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
+        MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
+        if (Dct == 0) {
+          MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
+        }
+        // NOTE: wait 512 clocks for DLL-relock
+        MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+      }
+    }
+  }
+  // Re-enable phy compensation since it had been disabled during InitPhyComp
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function ramp up frequency the next level if it have not reached
+ *      its TargetSpeed yet.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNRampUpFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT16 FreqList[] = {
+    DDR400_FREQUENCY,
+    DDR533_FREQUENCY,
+    DDR667_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR1066_FREQUENCY,
+    DDR1333_FREQUENCY,
+    DDR1600_FREQUENCY,
+    DDR1866_FREQUENCY
+  };
+  UINT8 Dct;
+  UINT8 i;
+  UINT16 NewSpeed;
+  DIE_STRUCT *MCTPtr;
+
+  MCTPtr = NBPtr->MCTPtr;
+
+  // Do not change frequency when it is already at TargetSpeed
+  if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
+    return TRUE;
+  }
+
+  // Find the next supported frequency level
+  NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed;
+  for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) {
+    if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) {
+      NewSpeed = FreqList[i + 1];
+      break;
+    }
+  }
+  ASSERT (i < (GET_SIZE_OF (FreqList) - 1));
+  ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed);
+
+  // BIOS must program both DCTs to the same frequency.
+  IDS_HDT_CONSOLE ("\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed);
+  for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.Speed = NewSpeed;
+  }
+  IDS_HDT_CONSOLE (" -> %d MHz", NewSpeed);
+
+  IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->ChangeFrequency (NBPtr);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function uses calculated values from DCT.Timings structure to
+ *      program its registers.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramCycTimingsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST CTENTRY TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 4, 12, 4, 2},
+    {BFTrcd, 5, 12, 5, 2},
+    {BFTrp, 5, 12, 5, 2},
+    {BFTrtp, 4, 7, 4, 2},
+    {BFTras, 15, 30, 15, 2},
+    {BFTrc, 11, 42, 11, 2},
+    {BFTwrDDR3, 5, 12, 4, 2},
+    {BFTrrd, 4, 7, 4, 2},
+    {BFTwtr, 4, 7, 4, 2},
+    {BFFourActWindow, 16, 32, 14, 1}
+  };
+
+  DCT_STRUCT *DCTPtr;
+  UINT8  *MiniMaxTmg;
+  UINT8  *MiniMaxTrfc;
+  UINT8  Value8;
+  UINT8  j;
+  BIT_FIELD_NAME BitField;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //======================================================================
+  // Program turnaround timings to their max during DRAM init and training
+  //======================================================================
+  //
+  MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF);
+
+  MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  MiniMaxTmg = &DCTPtr->Timings.CasL;
+  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
+    BitField = TmgAdjTab[j].BitField;
+
+    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Min;
+    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Max;
+    }
+
+    Value8 = (UINT8) MiniMaxTmg[j];
+
+    if (BitField == BFTwrDDR3) {
+      Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8;
+    } else if (BitField == BFTrtp) {
+      Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6;
+    }
+
+    Value8 = Value8 - TmgAdjTab[j].Bias;
+    Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
+
+    MemNSetBitFieldNb (NBPtr, BitField, Value8);
+  }
+
+  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
+  for (j = 0; j < 4; j++) {
+    MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ?
+                                     (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0));
+
+  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // 7.8 us
+
+  //======================================================================
+  // DRAM MRS Register, set ODT
+  //======================================================================
+  //
+  // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
+  MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
+
+  // burst length control
+  if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+    MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2);
+  }
+
+  // ASR=1, auto self refresh; SRT=0
+  MemNSetBitFieldNb (NBPtr, BFASR, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function uses calculated values from DCT.Timings structure to
+ *      program its registers.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramCycTimingsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST CTENTRY TmgAdjTab[] = {
+    // BitField, Min, Max, Bias, Ratio_x2
+    {BFTcl, 5, 14, 4, 2},
+    {BFTrcd, 5, 14, 5, 2},
+    {BFTrp, 5, 14, 5, 2},
+    {BFTrtp, 4, 8, 4, 2},
+    {BFTras, 15, 36, 15, 2},
+    {BFTrc, 20, 49, 11, 2},
+    {BFTwrDDR3, 5, 16, 4, 2},
+    {BFTrrd, 4, 8, 4, 2},
+    {BFTwtr, 4, 8, 4, 2},
+    {BFFourActWindow, 16, 40, 14, 1}
+  };
+
+  DCT_STRUCT *DCTPtr;
+  UINT8  *MiniMaxTmg;
+  UINT8  *MiniMaxTrfc;
+  UINT8  Value8;
+  UINT8  j;
+  UINT8  Tcwl;
+  BIT_FIELD_NAME BitField;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  MiniMaxTmg = &DCTPtr->Timings.CasL;
+  for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
+    BitField = TmgAdjTab[j].BitField;
+
+    if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Min;
+    } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
+      MiniMaxTmg[j] = TmgAdjTab[j].Max;
+    }
+
+    Value8 = (UINT8) MiniMaxTmg[j];
+
+    if (BitField == BFTwrDDR3) {
+      Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8;
+    }
+
+    Value8 = Value8 - TmgAdjTab[j].Bias;
+    Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
+
+    MemNSetBitFieldNb (NBPtr, BitField, Value8);
+  }
+
+  MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
+  for (j = 0; j < 4; j++) {
+    MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
+  }
+
+  Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2;
+  MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0));
+
+  MemNSetBitFieldNb (NBPtr, BFTref, 2);      // Tref = 7.8 us
+
+  MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (DCTPtr->Timings.Trcd > 10) ? 0 : 1);
+
+  MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0);
+
+  // Set ProcOdtAdv
+  if (DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) {
+    MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) & 0xBFFF));
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x4000));
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets platform specific settings for the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - All platform types defined have initialized successfully
+ *     @return          FALSE - At least one of the platform types gave not been initialized successfully
+ */
+
+BOOLEAN
+MemNGetPlatformCfgNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 p;
+
+  for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
+    ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL);
+    if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) {
+      break;
+    }
+  }
+  return (p < MAX_PLATFORM_TYPES);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retrieves the Max latency parameters
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @param[in]  *MinDlyPtr - Pointer to variable to store the Minimum Delay value
+ *     @param[in]  *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
+ *     @param[in]  *DlyBiasPtr - Pointer to variable to store Delay Bias value
+ *     @param[in]  MaxRcvEnDly - Maximum receiver enable delay value
+ */
+
+VOID
+MemNGetMaxLatParamsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  )
+{
+  *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2;
+  MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr);
+
+  *MaxDlyPtr = 0x3FF;
+
+  *DlyBiasPtr = 4;
+  MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr);   // 1 MEMCLK Margin
+
+  *DlyBiasPtr += 1;  // add 1 NCLK
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function retrieves the Max latency parameters
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @param[in]  *MinDlyPtr - Pointer to variable to store the Minimum Delay value
+ *     @param[in]  *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
+ *     @param[in]  *DlyBiasPtr - Pointer to variable to store Delay Bias value
+ *     @param[in]  MaxDlyForMaxRdLat - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemNGetMaxLatParamsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxDlyForMaxRdLat,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  )
+{
+  UINT32 P;
+  UINT32 T;
+  UINT32 MemClkPeriod;
+
+  T = MemNTotalSyncComponentsClientNb (NBPtr);
+
+  // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime))
+  P = (MaxDlyForMaxRdLat + 31) / 32;
+
+  MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+
+  *MinDlyPtr = (UINT16) (((((P * MemClkPeriod + 1) / 2) + T) * NBPtr->NBClkFreq + 999999) / 1000000);
+
+  *MinDlyPtr += 4;
+
+  *MaxDlyPtr = 0x50;
+
+  *DlyBiasPtr = 3;
+
+  // Need to set ForceCasToSlot0=1 before MaxRdLatency training
+  MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function  sets the maximum round-trip latency in the system from the processor to the DRAM
+ *   devices and back.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     MaxRcvEnDly - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  )
+{
+  UINT16 SubTotal;
+
+  AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
+
+  SubTotal = 0xC8;    // init value for MaxRdLat used in training
+
+
+  if (MaxRcvEnDly != 0xFFFF) {
+    // Get all sync components BKDG steps 1-5
+    SubTotal = MemNTotalSyncComponentsNb (NBPtr);
+
+    // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay
+    // that exists across all DIMMs and byte lanes.
+    //
+    SubTotal += MaxRcvEnDly >> 5;
+
+
+    // Add 14.5 to the sub-total. 14.5 represents part of the processor
+    // specific constant delay value in the DRAM clock domain.
+    //
+    SubTotal <<= 1;             // scale 1/2 MemClk to 1/4 MemClk
+    SubTotal += 29;             // add 14.5 1/2 MemClk
+
+    // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs)
+    // as follows (assuming DDR400 and assuming that no P-state or link speed
+    // changes have occurred).
+    //
+    MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal);
+
+    // Add 2 NCLKs to the sub-total. 2 represents part of the processor
+    // specific constant value in the northbridge clock domain.
+    //
+    SubTotal += 2;
+  }
+
+  NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal;
+  // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value
+  IDS_HDT_CONSOLE ("\t\tMaxRdLat: %03x\n", SubTotal);
+  MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sends the ZQCL command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 1.Program MrsAddress[10]=1
+  MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10);
+
+  // 2.Set SendZQCmd=1
+  MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1);
+
+  // 3.Wait for SendZQCmd=0
+  MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
+
+  // 4.Wait 512 MEMCLKs
+  MemUWait10ns (128, NBPtr->MemPtr);   // 512*2.5ns=1280, wait 1280ns
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function is used to create the DRAM map
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+
+VOID
+STATIC
+MemNAfterStitchMemNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->MCTPtr->GangedMode) {
+    NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize;
+    NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
+    NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+    NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+    NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize;
+  } else {
+    // In unganged mode, add DCT0 and DCT1 to NodeMemSize
+    NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
+    NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This function Return the binary value of tfaw associated with
+ *       the index k
+ *
+ *     @param[in]     k value
+ *
+ *     @return       F[k], in Binary MHz.
+ */
+
+UINT8
+MemNGet1KTFawTkNb (
+  IN       UINT8 k
+  )
+{
+  CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19};
+  ASSERT (k <= 5);
+  return Tab1KTfawTK[k];
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *       This function Return the binary value of the 2KTFaw associated with
+ *       the index k
+ *
+ *     @param[in]     k value
+ *
+ *     @return       2KTFaw converted based on k.
+ */
+
+UINT8
+MemNGet2KTFawTkNb (
+  IN       UINT8 k
+  )
+{
+  CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24};
+  ASSERT (k <= 5);
+  return Tab2KTfawTK[k];
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs)
+ *      (assuming DDR400 and assuming that no P-state or link speed
+ *      changes have occurred).
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *SubTotalPtr - pointer to Sub-Total
+ */
+
+VOID
+STATIC
+MemNQuarterMemClk2NClkNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *SubTotalPtr
+  )
+{
+  UINT32 NBFreq;
+  UINT32 MemFreq;
+
+  // Multiply SubTotal by NB COF
+  NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;
+  // Divide SubTotal by 4 times current MemClk frequency
+  MemFreq = NBPtr->DCTPtr->Timings.Speed * 4;
+  *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq);  // round up
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the total of sync components for Max Read Latency calculation
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Total in 1/2 MEMCLKs
+ */
+
+UINT16
+MemNTotalSyncComponentsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16 SubTotal;
+
+  // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs.
+  SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1;
+  if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) {
+    SubTotal += 3;
+  }
+  SubTotal *= 2;
+
+  // If registered DIMMs are being used then add 1 MEMCLK to the sub-total.
+  if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) {
+    SubTotal += 2;
+  }
+
+  // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1
+  // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2
+  if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
+    SubTotal += 1;
+  } else {
+    SubTotal += 2;
+  }
+
+  // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
+  // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total.
+  //
+  SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit));
+
+  return SubTotal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function swaps bits for OnDimmMirror support
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSwapBitsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT32 MRSReg;
+
+  ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel);
+  if ((ChipSel & 1) != 0) {
+    MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg);
+    if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
+      MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1);
+      MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   Programs Address/command timings, driver strengths, and tri-state fields.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNProgramPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8           PinType[3]  = {PSO_CKE_TRI, PSO_ODT_TRI,   PSO_CS_TRI};
+  CONST UINT8           TabSize[3]  = {          2,           4,            8};
+  CONST BIT_FIELD_NAME  BitField[3] = {   BFCKETri,    BFODTTri, BFChipSelTri};
+  UINT8  *TabPtr;
+  UINT8  i;
+  UINT8  k;
+  UINT8  Value;
+  //===================================================================
+  // Tristate unused CKE, ODT and chip select to save power
+  //===================================================================
+  //
+  TabPtr = NULL;
+  for (k = 0; k < sizeof (PinType); k++) {
+    if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) {
+      TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0));
+    }
+    if (NBPtr->IsSupported[CheckFindPSDct]) {
+      TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct);
+    }
+    if (TabPtr == NULL) {
+      switch (k) {
+      case 0:
+        TabPtr = NBPtr->ChannelPtr->CKETriMap;
+        break;
+      case 1:
+        TabPtr = NBPtr->ChannelPtr->ODTTriMap;
+        break;
+      case 2:
+        TabPtr = NBPtr->ChannelPtr->ChipSelTriMap;
+        break;
+      default:
+        IDS_ERROR_TRAP;
+      }
+    }
+    ASSERT (TabPtr != NULL);
+
+    Value = 0;
+    for (i = 0; i < TabSize[k]; i++) {
+      if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) {
+        Value |= (UINT8) (1 << i);
+      }
+    }
+    MemNSetBitFieldNb (NBPtr, BitField[k], Value);
+  }
+  NBPtr->MemNBeforePlatformSpecNb (NBPtr);
+
+  //===================================================================
+  // Program Address/Command timings and driver strength
+  //===================================================================
+  //
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS);
+  MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS);
+
+  MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0);
+  MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
+  MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
+
+  if (NBPtr->IsSupported[CheckODTControls]) {
+    MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow);
+    MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh);
+    MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow);
+    MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
+  }
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Trdrd value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Trdrd value
+ */
+
+UINT8
+MemNGetTrdrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+  INT8 Cgdd;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the
+  // converted field value. BIOS rounds fractional values down.
+  // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1,
+  // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1,
+  // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM.
+
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly);
+  DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3;
+
+  // Transfer clk to reg definition, 2T is 00b, etc.
+  DCTPtr->Timings.Trdrd -= 2;
+  if (DCTPtr->Timings.Trdrd > 8) {
+    DCTPtr->Timings.Trdrd = 8;
+  }
+
+  return DCTPtr->Timings.Trdrd;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Twrwr value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Twrwr value
+ */
+
+UINT8
+MemNGetTwrwrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+  INT8 Cgdd;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the
+  // converted field value. BIOS rounds fractional values down.
+  // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6,
+  // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1,
+  // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross
+  // Delay Difference (CGDD) for Twrwr.
+
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly);
+  DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3;
+  NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr);
+
+  return DCTPtr->Timings.Twrwr;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs
+ * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional
+ * values down.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return  Value to be programmed to Twrrd field
+ *              pDCT->Timings.Twrrd updated
+ */
+
+UINT8
+MemNGetTwrrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Cgdd;
+  INT8 Ld;
+  INT8 Twrrd;
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  //
+  // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
+  // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
+  // value.
+  // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
+  //
+  Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr);
+
+  // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM
+  // minus the DqsRcvEnGrossDelay delay of any other DIMM is
+  // equal to the Critical Gross Delay Difference (CGDD) for Twrrd.
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly);
+  Twrrd = (Cgdd / 2) - Ld + 3;
+  DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0);
+  NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr);
+
+  return DCTPtr->Timings.Twrrd;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the TrwtTO value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return  pDCT->Timings.TrwtTO updated
+ */
+
+UINT8
+MemNGetTrwtTONb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  INT8 Cgdd;
+  INT8 Ld;
+  INT8 TrwtTO;
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+  //
+  // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
+  // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
+  // value.
+  // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
+  //
+  Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr);
+
+  // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus
+  // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross
+  // Delay Difference (CGDD) for TrwtTO.
+  Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly);
+  TrwtTO = (Cgdd / 2) + Ld + 3;
+  TrwtTO -= 2;
+  DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1);
+
+  return DCTPtr->Timings.TrwtTO;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the TrwtWB value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      TrwtWB value
+ */
+UINT8
+MemNGetTrwtWBNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+
+  // TrwtWB ensures read-to-write data-bus turnaround.
+  // This value should be one more than the programmed TrwtTO.
+  return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts MemClk frequency in MHz to MemClkFreq value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Speed   - MemClk frequency in MHz
+ *
+ *     @return      MemClkFreq value
+ */
+UINT8
+MemNGetMemClkFreqIdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  )
+{
+  return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables swapping interleaved region feature.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Base   - Swap interleaved region base [47:27]
+ *     @param[in]   Limit   - Swap interleaved region limit [47:27]
+ *
+ */
+VOID
+MemNEnableSwapIntlvRgnNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Base,
+  IN       UINT32 Limit
+  )
+{
+  UINT32 Size;
+  UINT32 SizeOfAlign;
+
+  // Swapped interleaving region must be below 16G
+  if (Limit < (1 << (34 - 27))) {
+    // Adjust Base and Size to meet :
+    // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase].
+    // 2. Entire UMA region is swapped with interleaving region.
+    Size = Limit - Base;
+    SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base);
+    while (SizeOfAlign <= Size) {
+      // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB.
+      Base -= 1;
+      Size += 1;
+      SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base);
+    }
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base);
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1));
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size);
+    MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function converts MemClk frequency in MHz to MemClkFreq value
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Speed   - MemClk frequency in MHz
+ *
+ *     @return      MemClkFreq value
+ */
+UINT8
+MemNGetMemClkFreqIdClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  )
+{
+  return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
+ *  for client NB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNChangeFrequencyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 Dummy;
+  BOOLEAN FrequencyChangeSuccess;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // 1. Program D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0190h for Llano
+  // 1. Program D18F2x9C_x0D0F_E006[PllLockTime] = 1838h for Ontario
+  MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
+  MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
+
+  //Program F2x[1,0]90[EnterSelfRefresh]=1.
+  //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
+  MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+
+  if (NBPtr->ChangeNbFrequency (NBPtr)) {
+    // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
+
+    // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+
+    // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
+    // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
+    // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule
+    // Delay Programming].
+    // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
+    //                                                                         THEN 2 ELSE 3 ENDIF (Ontario)
+    MemNProgramNbPstateDependentRegistersClientNb (NBPtr);
+
+    // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
+    MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
+
+    FrequencyChangeSuccess = TRUE;
+  } else {
+    // If NB frequency cannot be updated, use the current speed as the target speed
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed;
+      NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed;
+    }
+    FrequencyChangeSuccess = FALSE;
+  }
+
+  //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
+  //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
+  MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
+  MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
+
+  // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program
+  // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh.
+  // (CsrPhySrPllPdMode is kept 0 before training)
+  MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F);
+
+  if (FrequencyChangeSuccess) {
+    // Perform Phy Fence training and Phy comp init after frequency change
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+
+        // Phy fence programming
+        AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->PhyFenceTraining (NBPtr);
+
+        // Phy compensation initialization
+        AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->MemNInitPhyComp (NBPtr);
+      }
+    }
+
+    //======================================================================
+    // Calculate and program DRAM Timings at new frequency
+    //======================================================================
+    //
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+      MemNSwitchDCTNb (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+
+        //9.Configure the DCT to send initialization MR commands:
+        //  BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
+        TechPtr->AutoCycTiming (TechPtr);
+        if (!MemNPlatformSpecNb (NBPtr)) {
+          IDS_ERROR_TRAP;
+        }
+
+        for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+          if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) {
+            // if chip select present
+            TechPtr->SendAllMRCmds (TechPtr, ChipSel);
+          }
+        }
+        // Wait 512 clocks for DLL-relock
+        MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+      }
+    }
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+CONST UINT16 PllDivTab[10] = {1, 2, 4, 8, 16, 128, 256, 1, 3, 6};
+
+/**
+ *
+ *  This function calculates and programs NB P-state dependent registers
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNProgramNbPstateDependentRegistersClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 i;
+  UINT8 Dct;
+  UINT8 NclkFid;
+  UINT16 MemClkDid;
+  UINT8 PllMult;
+  UINT8 NclkDiv;
+  UINT8 RdPtrInitMin;
+  UINT8 RdPtrInit;
+  UINT32 NclkPeriod;
+  UINT32 MemClkPeriod;
+  INT32 PartialSum2x;
+  INT32 PartialSumSlotI2x;
+
+  NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 10);
+  ASSERT (MemNGetBitFieldNb (NBPtr, BFPllDiv) < 10);
+  MemClkDid = PllDivTab[MemNGetBitFieldNb (NBPtr, BFPllDiv)];
+  PllMult = (UINT8) MemNGetBitFieldNb (NBPtr, BFPllMult);
+  if (MemNGetBitFieldNb (NBPtr, BFNbPs1Act) == 1) {
+    NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv);
+    IDS_HDT_CONSOLE ("\n\tNB P1");
+  } else {
+    NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv);
+    IDS_HDT_CONSOLE ("\n\tNB P0");
+  }
+  NclkPeriod = (2500 * NclkDiv) / NclkFid;
+  MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+  RdPtrInitMin = RdPtrInit = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667;
+  ASSERT (NBPtr->NBClkFreq == (((UINT32) NclkFid * 400) / NclkDiv));
+
+  IDS_HDT_CONSOLE ("  Freq: %lxMHz\n", NBPtr->NBClkFreq);
+  IDS_HDT_CONSOLE ("\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed);
+  // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
+  //                                                                      THEN 2 ELSE 3 ENDIF (Ontario)
+  MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
+  IDS_HDT_CONSOLE ("\t\tRdPtr: %d\n", RdPtrInit);
+
+  // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
+  MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16);
+  MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv);
+  IDS_HDT_CONSOLE ("\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16);
+  IDS_HDT_CONSOLE ("\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv);
+
+  // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
+  // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0].
+  //   PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
+  //   CmdSetup - PtrSeparation - 1. (Llano)
+  //   PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
+  //   CmdSetup - PtrSeparation - 1. (Ontario)
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod;
+      PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod;
+      PartialSum2x += 520 * 2;
+      PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod;  // round-up here
+      PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
+      if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
+        PartialSum2x -= 1;
+      } else {
+        PartialSum2x -= 2;
+      }
+      PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16);
+      PartialSum2x -= 2;
+
+      // If PartialSumSlotN is positive:
+      //   DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN).
+      //   DataTxFifoSchedDlyNegSlotN=0.
+      // Else if PartialSumSlotN is negative:
+      //   DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)).
+      //   DataTxFifoSchedDlyNegSlotN=1.
+      for (i = 0; i < 2; i++) {
+        PartialSumSlotI2x = PartialSum2x;
+        if ((i == 0) && (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 0)) {
+          PartialSumSlotI2x += 2;
+        }
+        if (PartialSumSlotI2x > 0) {
+          ASSERT ((i != 0) && (PartialSumSlotI2x <= 2));  // Real system constrain
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0);
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2);
+          IDS_HDT_CONSOLE ("\t\tDataTxFifoSchedDlySlot%d: %lx\n", i, (PartialSumSlotI2x + 1) / 2);
+        } else {
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1);
+          PartialSumSlotI2x = (((-PartialSumSlotI2x) * MemClkPeriod) + (2 * NclkPeriod - 1)) / (2 * NclkPeriod);
+          MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x);
+          IDS_HDT_CONSOLE ("\t\tDataTxFifoSchedDlySlot%d: -%lx\n", i, PartialSumSlotI2x);
+        }
+      }
+    }
+  }
+
+  MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the total of sync components for Max Read Latency calculation
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      Total in 1/2 MEMCLKs
+ */
+
+UINT32
+MemNTotalSyncComponentsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 P;
+  UINT32 T;
+  UINT8  RdPtrInitMin;
+  UINT8  RdPtrInit;
+  UINT32 AddrTmgCtl;
+  UINT8  DbeGskMemClkAlignMode;
+  UINT32 MemClkPeriod;
+
+  // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)
+  RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667;
+  RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
+  P = (16 + RdPtrInitMin - RdPtrInit) % 16;
+
+  // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1
+  AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl);
+  if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) {
+    P += 1;
+  }
+
+  // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup)))
+  // THEN P = P + 1
+  DbeGskMemClkAlignMode = 2;  // from BKDG recommendation.
+  if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) &&
+      !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) {
+    P += 1;
+  }
+
+  // IF (SlowAccessMode==1) THEN P = P + 2
+  if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) {
+    P += 2;
+  }
+
+  // IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz)
+  // THEN T = T + MemClkPeriod - 786 ps
+  // ELSE T = T + (0.5 * MemClkPeriod) - 786 ps
+  MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
+  if (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) {
+    T = MemClkPeriod - 786;
+  } else {
+    T = (MemClkPeriod / 2) - 786;
+  }
+
+  // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0)
+  // then P = P + 1
+  // else P = P + 2
+  if ((AddrTmgCtl & 0x0202020) == 0) {
+    P += 1;
+  } else {
+    P += 2;
+  }
+
+  // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1))
+  P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1);
+
+  // If (DisCutThroughMode==0)
+  // then P = P + 3
+  // else P = P + 7
+  if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) {
+    P += 3;
+  } else {
+    P += 7;
+  }
+
+  return (((P * MemClkPeriod + 1) / 2) + T);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets up phy power saving for client NB
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNPhyPowerSavingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b.
+  // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b.
+  // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b.
+  MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3);
+  // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins.
+  MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, 0xA1);
+  // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1.
+  MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100);
+  // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <=
+  //    800 MHz) THEN 1 ELSE 0 ENDIF.
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+  // 10. Program D18F2x[1,0]9C_x0000_000D as follows:
+  //    TxMaxDurDllNoLock/RxMaxDurDllNoLock = 9h.
+  MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 9);
+  MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 9);
+  //    TxCPUpdPeriod/RxCPUpdPeriod = 000b.
+  MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 0);
+  MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 0);
+  //    TxDLLWakeupTime/RxDLLWakeupTime = 11b.
+  MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3);
+  MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c
new file mode 100755
index 0000000000..1b462a996d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c
@@ -0,0 +1,560 @@
+/**
+ * @file
+ *
+ * mnfeat.c
+ *
+ * Common Northbridge features
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_CL_CONT_READ  32
+#define MAX_CL_CONT_WRITE 32
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemNContWritePatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNContReadPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNGenHwRcvEnReadsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  );
+
+UINT16
+STATIC
+MemNCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+UINT16
+STATIC
+MemNInsDlyCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+VOID
+STATIC
+MemNContWritePatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNContReadPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+STATIC
+MemNGenHwRcvEnReadsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+MemNInitCPGClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function assigns read/write function pointers to CPG read/write modules.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNInitCPGNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+VOID
+MemNInitCPGNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->WritePattern = MemNContWritePatternNb;
+  NBPtr->ReadPattern = MemNContReadPatternNb;
+  NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes 9 or 18 cache lines continuously using GH CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Pattern - Array of bytes that will be written to DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+VOID
+STATIC
+MemNContWritePatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  UINT16 ClDiff;
+  if (ClCount > MAX_CL_CONT_WRITE) {
+    ClDiff = ClCount - MAX_CL_CONT_WRITE;
+    ClCount = MAX_CL_CONT_WRITE;
+  } else {
+    ClDiff = 0;
+  }
+
+  // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst.
+  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount);
+
+  // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set
+  // again), all the writes are written to DRAM.
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+  MemUWriteCachelines (Address, Pattern, ClCount);
+
+  // Flush out prior writes by setting F2x11C[FlushWr].
+  MemNSetBitFieldNb (NBPtr, BFFlushWr, 1);
+  // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed.
+  while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {}
+
+  // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting.
+  MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F);
+
+  if (ClDiff > 0) {
+    MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function reads 9 or 18 cache lines continuously using GH CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+STATIC
+MemNContReadPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  BOOLEAN DisAutoRefresh;
+  UINT16 ClDiff;
+  if (ClCount > MAX_CL_CONT_READ) {
+    ClDiff = ClCount - MAX_CL_CONT_READ;
+    ClCount = MAX_CL_CONT_READ;
+  } else {
+    ClDiff = 0;
+  }
+
+  Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
+
+  // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads.
+  // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64
+  // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices
+  // to change to an 8-beat burst length and then to restore the desired burst length after training
+  // is complete.
+
+  if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) {
+    DisAutoRefresh = FALSE;
+    // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1.
+    // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description.
+    MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+    // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0);  // ForceAutoPchg is 0 by default.
+    MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+  } else {
+    DisAutoRefresh = TRUE;
+  }
+
+  MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+
+  // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the
+  // training sequence.
+  MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1);
+
+  // 6. BIOS sets F2x11C[PrefDramTrainMode] bit.
+  // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor
+  // table (removing any existing prefetch stride patterns).
+  MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1);
+
+  // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes.
+  // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS
+  // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must
+  // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary.
+  // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to
+  // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears
+  // F2x11C[PrefDramTrainMode].
+  MemUDummyCLRead (Address);
+  MemUDummyCLRead (Address + 0x40);
+  if (NBPtr->IsSupported[CheckDummyCLRead]) {
+    MemUDummyCLRead (Address + 0x80);
+  }
+  // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after
+  // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines
+  // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches
+  // and read the data from the prefetch buffer.
+  while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {}
+  MemUReadCachelines (Buffer, Address, ClCount);
+
+  // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and
+  // F2x[1, 0]90[BurstLength32].
+  if (!DisAutoRefresh) {
+    MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
+    MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
+  }
+
+  if (ClDiff > 0) {
+    MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function generates a continuous burst of reads during HW RcvEn training.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Address - System Address [47:16]
+ *
+ */
+VOID
+STATIC
+MemNGenHwRcvEnReadsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  )
+{
+  UINT8  TempBuffer[12 * 64];
+  UINT8  BurstCount;
+
+  for (BurstCount = 0; BurstCount < 10; BurstCount++) {
+    NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12);
+    NBPtr->FlushPattern (NBPtr, Address, 12);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function writes cache lines continuously using TCB CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Pattern - Array of bytes that will be written to DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+VOID
+STATIC
+MemNContWritePatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  )
+{
+  UINT32 PatternHash;
+  UINT32 *DwordPtr;
+  UINT16 i;
+
+  // 1. Program D18F2x1C0[WrDramTrainMode]=1.
+  MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1);
+
+  PatternHash = (ClCount << 24) | (Pattern[9] << 16) | (Pattern[64 + 9] << 8) | Pattern[2 * 64 + 9];
+  if (NBPtr->CPGInit != PatternHash) {
+    // If write training buffer has not been initialized, initialize it
+    // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
+    MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount);
+
+    // 3. Program D18F2x1D0[WrTrainBufAddr]=000h.
+    MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
+
+    // 4. Successively write each dword of the training pattern to D18F2x1D4.
+    DwordPtr = (UINT32 *) Pattern;
+    for (i = 0; i < (ClCount * 16); i++) {
+      MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]);
+    }
+
+    NBPtr->CPGInit = PatternHash;
+  }
+
+  // 5. Program D18F2x1D0[WrTrainBufAddr]=000h
+  MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
+
+  // 6. Program the DRAM training address
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6));
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3);
+
+  // 7. Program D18F2x1C0[WrTrainGo]=1.
+  MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1);
+
+  // 8. Wait for D18F2x1C0[WrTrainGo]=0.
+  while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {}
+
+  // 9. Program D18F2x1C0[WrDramTrainMode]=0.
+  MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function reads cache lines continuously using TCB CPG engine
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
+ *     @param[in]     Address - System Address [47:16]
+ *     @param[in] ClCount - Number of cache lines
+ *
+ */
+
+VOID
+STATIC
+MemNContReadPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  )
+{
+  // 1. Program D18F2x1C0[RdDramTrainMode]=1.
+  MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1);
+
+  // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
+  MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount);
+
+  // 3. Program the DRAM training address as follows:
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6));
+  MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3);
+
+  // 4. Program D18F2x1D0[WrTrainBufAddr]=000h
+  MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
+
+  // 5. Program D18F2x1C0[RdTrainGo]=1.
+  MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1);
+
+  // 6. Wait for D18F2x1C0[RdTrainGo]=0.
+  while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {}
+
+  // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2].
+  // This step will be accomplished in Compare routine.
+
+  // 8. Program D18F2x1C0[RdDramTrainMode]=0.
+  MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function generates a continuous burst of reads during HW RcvEn training.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Address - System Address [47:16]
+ *
+ */
+VOID
+STATIC
+MemNGenHwRcvEnReadsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address
+  )
+{
+  UINT8  TempBuffer[64];
+  UINT8  Count;
+
+  for (Count = 0; Count < 3; Count++) {
+    NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function assigns read/write function pointers to CPG read/write modules.
+ *
+ *     @param[in,out] NBPtr  - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNInitCPGClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->WritePattern = MemNContWritePatternClientNb;
+  NBPtr->ReadPattern = MemNContReadPatternClientNb;
+  NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb;
+  NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet;
+  NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb;
+  NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb;
+  NBPtr->CPGInit = 0;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and
+ *       return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @return  PASS - Bitmap of results of comparison
+ */
+
+UINT16
+STATIC
+MemNCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and
+ *       return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       ByteCount - Byte count
+ *
+ *     @retval  Bitmap of results of comparison
+ */
+UINT16
+STATIC
+MemNInsDlyCompareTestPatternClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  )
+{
+  return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c
new file mode 100755
index 0000000000..f6af51c50f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c
@@ -0,0 +1,258 @@
+/**
+ * @file
+ *
+ * mnflow.c
+ *
+ * Common Northbridge initializer flow for MCT and DCT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemNInitDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemNCleanupDctRegsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the MCT with initial values
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS)
+ *     @return          FALSE - AGESA_FATAL error occurred
+ */
+
+BOOLEAN
+MemNInitMCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  UINT8 Dct;
+  BOOLEAN Flag;
+
+  TechPtr = NBPtr->TechPtr;
+  // Switch Tech functions for Nb
+  NBPtr->TechBlockSwitch (NBPtr);
+  // Start Memory controller initialization sequence
+  Flag = FALSE;
+  if (TechPtr->DimmPresence (TechPtr)) {
+    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));
+    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {
+      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));
+      if (TechPtr->SpdCalcWidth (TechPtr)) {
+        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));
+        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {
+          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+            NBPtr->SwitchDCT (NBPtr, Dct);
+
+            Flag |= MemNInitDCTNb (NBPtr);
+          }
+
+          if (Flag && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {
+            MemFInitTableDrive (NBPtr, MTBeforeDInit);
+            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+            AgesaHookBeforeDramInit (0, NBPtr->MemPtr);
+            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
+            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));
+            NBPtr->StartupDCT (NBPtr);
+          }
+        }
+      }
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function programs the DCT with initial values
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Error did not occur
+ *     @return          FALSE - Error occurred
+ */
+
+BOOLEAN
+STATIC
+MemNInitDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  TechPtr = NBPtr->TechPtr;
+  TechPtr->SetDramMode (TechPtr);
+
+  if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) {
+    if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) {
+      NBPtr->DisableDCT (NBPtr);
+    } else {
+      MemNCleanupDctRegsNb (NBPtr);
+      if (TechPtr->AutoCycTiming (TechPtr)) {
+        if (TechPtr->SpdSetBanks (TechPtr)) {
+          if (NBPtr->StitchMemory (NBPtr)) {
+            // if all dimms on a DCT are disabled, the DCT needs to be disabled.
+            if (NBPtr->DCTPtr->Timings.CsEnabled != 0) {
+              if (NBPtr->AutoConfig (NBPtr)) {
+                if (NBPtr->PlatformSpec (NBPtr)) {
+                  return TRUE;
+                }
+              }
+            } else {
+              NBPtr->DisableDCT (NBPtr);
+            }
+          }
+        }
+      }
+    }
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function selects appropriate Tech functions for the NB.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNTechBlockSwitchNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+
+  // Specify Dimm-Byte training for Nb
+  MemTDimmByteTrainInit (TechPtr);
+
+  // Filter included for RcvrEn training.
+  // note: If you'd like to drop the filter, you have to comment out these two lines together.
+  TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3;
+  TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter;
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function clears DCT registers
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemNCleanupDctRegsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BIT_FIELD_NAME BitField;
+
+  for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) {
+    MemNSetBitFieldNb (NBPtr, BitField, 0);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
new file mode 100755
index 0000000000..2ad6e1255b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c
@@ -0,0 +1,1043 @@
+/**
+ * @file
+ *
+ * mnmct.c
+ *
+ * Northbridge Common MCT supporting functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 11793 $ @e \$Date: 2009-04-06 15:08:53 -0500 (Mon, 06 Apr 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNMCT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _16MB_RJ16  0x0100
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemNSetMTRRrangeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Base,
+  IN OUT   UINT32 *LimitPtr,
+  IN       UINT32 MtrrAddr,
+  IN       UINT8 MtrrType
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets initial values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNInitializeMctNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+  if (NBPtr->Node == BSP_DIE) {
+    LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    if (SMsr.lo & ((UINT32)1 << 15)) {
+      NBPtr->ClToNbFlag = 1;
+    }
+    SMsr.lo |= (UINT32)1 << 15;                   // ClLinesToNbDis
+    LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+    LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    SMsr.hi |= (UINT32)1 << (48 - 32);              // WbEnhWsbDis
+    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+    LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     Get max frequency from OEM platform definition, from
+ *     any user override (limiting) of max frequency, and
+ *     from any Si Revision Specific information.  Return
+ *     the least of these three in DIE_STRUCT.Timings.TargetSpeed.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSyncTargetSpeedNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT16 DdrMaxRateTab[] = {
+    UNSUPPORTED_DDR_FREQUENCY,
+    DDR1600_FREQUENCY,
+    DDR1333_FREQUENCY,
+    DDR1066_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR667_FREQUENCY,
+    DDR533_FREQUENCY,
+    DDR400_FREQUENCY
+  };
+
+  UINT8  Dct;
+  UINT8  Channel;
+  UINT16 MinSpeed;
+  UINT16 DdrMaxRate;
+  DCT_STRUCT *DCTPtr;
+  USER_MEMORY_TIMING_MODE *ChnlTmgMod;
+  USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET];
+  MEMORY_BUS_SPEED MemClkFreq;
+  MEMORY_BUS_SPEED ProposedFreq;
+
+  ASSERT (NBPtr->DctCount <= sizeof (Mode));
+  MinSpeed = 16000;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    // Check if input user time mode is valid or not
+    ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) ||
+        (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) ||
+        (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO));
+    Mode[Dct] = NBPtr->RefPtr->UserTimingMode;
+    // Check if input clock value is valid or not
+    ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
+      (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) :
+      (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY));
+    MemClkFreq = NBPtr->RefPtr->MemClockValue;
+    if (DCTPtr->Timings.DctDimmValid != 0) {
+      Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0);
+      ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel);
+      if (ChnlTmgMod != NULL) {
+        // Check if input user timing mode is valid or not
+        ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) ||
+          (ChnlTmgMod[0] != TIMING_MODE_AUTO));
+        if (ChnlTmgMod[0] != TIMING_MODE_AUTO) {
+          Mode[Dct] = ChnlTmgMod[0];
+          // Check if input clock value is valid or not
+          ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
+            ((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) :
+            ((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY));
+          MemClkFreq = ChnlTmgMod[1];
+        }
+      }
+
+      ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit;
+      if (Mode[Dct] == TIMING_MODE_LIMITED) {
+        if (MemClkFreq < ProposedFreq) {
+          ProposedFreq = MemClkFreq;
+        }
+      } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
+        ProposedFreq = MemClkFreq;
+      }
+
+      if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
+        DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq;
+      } else {
+        // "limit" mode
+        if (DCTPtr->Timings.TargetSpeed > ProposedFreq) {
+          DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq;
+        }
+      }
+
+      IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) {
+        //
+        //Call Platform POR Frequency Override
+        //
+        if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) {
+          //
+          // Get the POR frequency limit
+          //
+          NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr);
+        }
+      }
+
+      if (MinSpeed > DCTPtr->Timings.TargetSpeed) {
+        MinSpeed = DCTPtr->Timings.TargetSpeed;
+      }
+    }
+  }
+
+  if (NBPtr->IsSupported[CheckMaxDramRate]) {
+    // Check maximum DRAM data rate that the processor is designed to support.
+    DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)];
+    if (MinSpeed > DdrMaxRate) {
+      MinSpeed = DdrMaxRate;
+    }
+  }
+
+  if (MinSpeed == DDR667_FREQUENCY) {
+    NBPtr->StartupSpeed = DDR667_FREQUENCY;
+  }
+
+  // Sync all DCTs to the same speed
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if ((Mode[Dct] == TIMING_MODE_SPECIFIC) && (NBPtr->DCTPtr->Timings.TargetSpeed > MinSpeed)) {
+      PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ALERT, NBPtr->MCTPtr);
+    }
+    NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed;
+    NBPtr->MemNCapSpeedBatteryLife (NBPtr);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function waits for all DCTs to be ready
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNSyncDctsReadyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->MCTPtr->DimmValid) {
+    MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE);
+    // Re-enable phy compensation engine after Dram init has completed
+    MemNSwitchDCTNb (NBPtr, 0);
+    MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+  }
+  // Wait 750 us for the phy compensation engine to reinitialize.
+  MemUWait10ns (75000, NBPtr->MemPtr);
+
+  MemNSyncAddrMapToAllNodesNb (NBPtr);
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function create the HT memory map
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemNHtMemMapInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 BottomIo;
+  UINT32 HoleOffset;
+  UINT32 DctSelBaseAddr;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  //
+  // Physical addresses in this function are right adjusted by 16 bits ([47:16])
+  // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit.
+  //
+
+  // Enforce bottom of IO be be 128MB aligned
+  ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0));
+  BottomIo = (RefPtr->BottomIo & 0xF8) << 8;
+
+  if (!MCTPtr->GangedMode) {
+    DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize;
+  } else {
+    DctSelBaseAddr = 0;
+  }
+
+  if (MCTPtr->NodeMemSize) {
+    NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase;
+    NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1;
+    DctSelBaseAddr += NodeSysBase;
+
+    if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) {
+      if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) {
+        // HW Dram Remap
+        MCTPtr->Status[SbHWHole] = TRUE;
+        RefPtr->GStatus[GsbHWHole] = TRUE;
+        MCTPtr->NodeHoleBase = BottomIo;
+        RefPtr->HoleBase = BottomIo;
+
+        HoleOffset = _4GB_RJ16 - BottomIo;
+
+        NodeSysLimit += HoleOffset;
+
+        if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) {
+          HoleOffset += DctSelBaseAddr;
+        } else {
+          if (DctSelBaseAddr >= BottomIo) {
+            DctSelBaseAddr += HoleOffset;
+          }
+          HoleOffset += NodeSysBase;
+        }
+
+        MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8);
+        MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7);
+        MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1);
+
+      } else if (NodeSysBase == BottomIo) {
+        // SW Node Hoist
+        MCTPtr->Status[SbSWNodeHole] = TRUE;
+        RefPtr->GStatus[GsbSpIntRemapHole] = TRUE;
+        RefPtr->GStatus[GsbSoftHole] = TRUE;
+
+        RefPtr->HoleBase = NodeSysBase;
+        DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase);
+        NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase);
+        NodeSysBase = _4GB_RJ16;
+
+      } else if ((NodeSysBase < HT_REGION_BASE_RJ16) && (NodeSysLimit >= HT_REGION_BASE_RJ16)) {
+        if (!NBPtr->SharedPtr->UndoHoistingAbove1TB) {
+          // SW Hoisting above 1TB to avoid HT Reserved region
+          DctSelBaseAddr = _1TB_RJ16 + (DctSelBaseAddr - NodeSysBase);
+          NodeSysLimit = _1TB_RJ16 + (NodeSysLimit - NodeSysBase);
+          NodeSysBase = _1TB_RJ16;
+
+          if (RefPtr->LimitMemoryToBelow1Tb) {
+            // Flag to undo 1TB hoisting after training
+            NBPtr->SharedPtr->UndoHoistingAbove1TB = TRUE;
+          }
+        }
+
+      } else {
+        // No Remapping.  Normal Contiguous mapping
+      }
+    } else {
+      // No Remapping.  Normal Contiguous mapping
+    }
+
+    if (NBPtr->IsSupported[Check1GAlign]) {
+      if (UserOptions.CfgNodeMem1GBAlign) {
+        NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit);
+      }
+    }
+
+    MCTPtr->NodeSysBase = NodeSysBase;
+    MCTPtr->NodeSysLimit = NodeSysLimit;
+    RefPtr->SysLimit = NodeSysLimit;
+    RefPtr->Sub1THoleBase = (NodeSysLimit < HT_REGION_BASE_RJ16) ? (NodeSysLimit + 1) : RefPtr->Sub1THoleBase;
+    IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader);
+
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
+    NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00;
+
+    MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16));
+    MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16));
+
+    if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
+      MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11);
+      MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1);
+      MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1);
+      MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10);
+    }
+
+    NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0;
+  }
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Program system DRAM map to this node
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNSyncAddrMapToAllNodesNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Node;
+  UINT32 NodeSysBase;
+  UINT32 NodeSysLimit;
+  UINT8  WeReMask;
+  UINT8  Index;
+  UINT32 Value;
+  PCI_ADDR PciAddr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = NBPtr->RefPtr;
+  for (Node = 0; Node < NBPtr->NodeCount; Node++) {
+    NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase;
+    NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit;
+    if (NBPtr->SharedPtr->NodeMap[Node].IsValid) {
+      WeReMask = 3;
+    } else {
+      WeReMask = 0;
+    }
+    // Set the Dram base and set the WE and RE flags in the base.
+    MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask);
+    MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24);
+    // Set the Dram limit and set DstNode.
+    MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node);
+    MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24);
+
+    if (RefPtr->GStatus[GsbHWHole]) {
+      MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1);
+      MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8));
+    }
+  }
+
+  if (RefPtr->SysLimit >= _1TB_RJ16) {
+    // Initialize all indices of F1x114_x2 and F1x114_x3.
+    for (Index = 0; Index < 32; Index++) {
+      PciAddr = NBPtr->PciAddr;
+      PciAddr.Address.Function = 1;
+
+      PciAddr.Address.Register = 0x110;
+      Value = 0x20000000 | Index;
+      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+
+      PciAddr.Address.Register = 0x114;
+      Value = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+
+      PciAddr.Address.Register = 0x110;
+      Value = 0x30000000 | Index;
+      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+
+      PciAddr.Address.Register = 0x114;
+      Value = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function enables power down mode
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPowerDownCtlNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 PowerDownMode;
+
+  RefPtr = NBPtr->RefPtr;
+
+  // we can't enable powerdown mode when doing WL
+  if (RefPtr->EnablePowerDown) {
+    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
+    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
+    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
+    if (PowerDownMode) {
+      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets the Optimal Critical Gross Delay Difference between
+ *   the delay parameters across all Dimms on each bytelane.  Then takes the
+ *   largest of all the bytelanes.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       TrnDly1 - Type of first Gross Delay parameter
+ *     @param[in]       TrnDly2 - Type of second Gross Delay parameter
+ *
+ *     @return  The largest difference between the largest and smallest
+ *               of the two Gross delay types within a single bytelane
+ */
+INT8
+MemNGetOptimalCGDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly1,
+  IN       TRN_DLY_TYPE TrnDly2
+  )
+{
+  INT8  CGDD;
+  INT8  GDD;
+  UINT8  Dimm1;
+  UINT8  Dimm2;
+  UINT8  ByteLane;
+  UINT16 CsEnabled;
+  BOOLEAN CGDDInit;
+  BOOLEAN SameDelayType;
+
+  CGDD = 0;
+  CGDDInit = FALSE;
+  SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2);
+  CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+
+  // If the two delay types compared are the same type, then no need to compare the same
+  // pair twice. Adjustments are made in the upper bound and lower bound of the loop to
+  // handle this.
+  for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) {
+    if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) {
+      for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) {
+        if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) {
+          for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) {
+            // check each byte lane delay pair
+            GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) -
+                  (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5);
+            // If the 2 delay types to be compared are the same, then keep the absolute difference
+            if (SameDelayType && (GDD < 0)) {
+              GDD = (-GDD);
+            }
+
+            // If CGDD is yet to be initialized, initialize it
+            // Otherwise, keep the largest difference so far
+            CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD);
+            if (!CGDDInit) {
+              CGDDInit = TRUE;
+            }
+          }
+        }
+      }
+    }
+  }
+  return CGDD;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the critical delay difference (CDD)
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       TrnDlyType1 - Type of first Gross Delay parameter
+ *     @param[in]       TrnDlyType2 - Type of second Gross Delay parameter
+ *     @param[in]       SameDimm - CDD of same DIMMs
+ *     @param[in]       DiffDimm - CDD of different DIMMs
+ *
+ *     @return      CDD term
+ */
+INT16
+MemNCalcCDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDlyType1,
+  IN       TRN_DLY_TYPE TrnDlyType2,
+  IN       BOOLEAN SameDimm,
+  IN       BOOLEAN DiffDimm
+  )
+{
+  INT16 CDD;
+  INT16 CDDtemp;
+  UINT16 TrnDly1;
+  UINT16 TrnDly2;
+  UINT8 i;
+  UINT8 j;
+  UINT8 ByteLane;
+  UINT16 CsEnabled;
+  BOOLEAN SameDlyType;
+
+  SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2);
+  CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
+  CDD = -32000;
+  // If the two delay types compared are the same type, then no need to compare the same
+  // pair twice. Adjustments are made in the upper bound and lower bound of the loop to
+  // handle this.
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL && (CsEnabled & (UINT16) (3 << (i << 1))); i++) {
+    for (j = SameDlyType ? i : 0; (j < MAX_DIMMS_PER_CHANNEL) && (CsEnabled & (UINT16) (3 << (j << 1))); j++) {
+      if ((SameDimm && (i == j)) || (DiffDimm && (i != j))) {
+        for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+          TrnDly1 = (UINT16) NBPtr->GetTrainDly (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i, ByteLane));
+          TrnDly2 = (UINT16) NBPtr->GetTrainDly (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j, ByteLane));
+
+          CDDtemp = TrnDly1 - TrnDly2;
+          // If the 2 delay types to be compared are the same, then keep the absolute difference
+          if ((SameDlyType) && (CDDtemp < 0)) {
+            CDDtemp = (-CDDtemp);
+          }
+
+          CDD = CDD < CDDtemp ? CDDtemp : CDD;
+        }
+      }
+    }
+  }
+
+  return CDD;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the fixed MTRRs for common legacy ranges.
+ *   It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_FATAL may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
+ */
+
+BOOLEAN
+MemNCPUMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Bottom32bIO;
+  UINT32 Bottom40bIO;
+  UINT32 Cache32bTOP;
+  S_UINT64 SMsr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  RefPtr = NBPtr->RefPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  //
+  //======================================================================
+  // Set temporary top of memory from Node structure data.
+  // Adjust temp top of memory down to accommodate 32-bit IO space.
+  //======================================================================
+  //Bottom40bIO=top of memory, right justified 16 bits  (defines dram versus IO space type)
+  //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type)
+  //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits
+  //
+  if (RefPtr->HoleBase != 0) {
+    Bottom32bIO = RefPtr->HoleBase;
+  } else if (RefPtr->BottomIo != 0) {
+    Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16);
+  } else {
+    Bottom32bIO = (UINT32)1 << (24 - 16);
+  }
+
+  Cache32bTOP = RefPtr->SysLimit + 1;
+  if (Cache32bTOP < _4GB_RJ16) {
+    Bottom40bIO = 0;
+    if (Bottom32bIO >= Cache32bTOP) {
+      Bottom32bIO = Cache32bTOP;
+    }
+  } else {
+    Bottom40bIO = Cache32bTOP;
+  }
+
+  Cache32bTOP = Bottom32bIO;
+
+
+  //
+  //======================================================================
+  // Set default values for CPU registers
+  //======================================================================
+  //
+  LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo |= 0x1C0000;                // turn on modification enable bit and
+                                      // mtrr enable bits
+  LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  SMsr.lo = SMsr.hi = 0x1E1E1E1E;
+  LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // 0 - 512K = WB Mem
+  LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // 512K - 640K = WB Mem
+
+  //
+  //======================================================================
+  // Set variable MTRR values
+  //======================================================================
+  //
+  MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6);
+
+  RefPtr->Sub4GCacheTop = Cache32bTOP << 16;
+
+  //
+  //======================================================================
+  // Set TOP_MEM and TOM2 CPU registers
+  //======================================================================
+  //
+  SMsr.hi = Bottom32bIO >> (32 - 16);
+  SMsr.lo = Bottom32bIO << 16;
+  LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  IDS_HDT_CONSOLE ("TOP_MEM:  %08lx0000\n", Bottom32bIO);
+
+  if (Bottom40bIO) {
+    SMsr.hi = Bottom40bIO >> (32 - 16);
+    SMsr.lo = Bottom40bIO << 16;
+  } else {
+    SMsr.hi = 0;
+    SMsr.lo = 0;
+  }
+  LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (Bottom40bIO) {
+    IDS_HDT_CONSOLE ("TOP_MEM2: %08lx0000\n", Bottom40bIO);
+    IDS_HDT_CONSOLE ("Sub1THoleBase: %08lx0000\n", RefPtr->Sub1THoleBase);
+    // Enable TOM2
+    SMsr.lo |= 0x00600000;
+  } else {
+    // Disable TOM2
+    SMsr.lo &= ~0x00600000;
+  }
+  LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
+ *   It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNUMAMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 Bottom32bIO;
+  UINT32 Bottom32bUMA;
+  UINT32 Cache32bTOP;
+  UINT32 Value32;
+  UINT8 BitCount;
+  UINT8 i;
+
+  MEM_PARAMETER_STRUCT *RefPtr;
+  RefPtr = NBPtr->RefPtr;
+  BitCount = 0;
+  //
+  //======================================================================
+  // Adjust temp top of memory down to accommodate UMA memory start
+  //======================================================================
+  // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type)
+  // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits
+  //
+  Bottom32bIO = RefPtr->Sub4GCacheTop >> 16;
+  Bottom32bUMA = RefPtr->UmaBase;
+
+  if (Bottom32bUMA < Bottom32bIO) {
+    Cache32bTOP = RefPtr->Sub4GCacheTop = Bottom32bUMA;
+    //
+    //======================================================================
+    //Set variable MTRR values
+    //======================================================================
+    //
+    Value32 = Cache32bTOP;
+    //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing.
+    while (Value32 != 0) {
+      i = LibAmdBitScanForward (Value32);
+      Value32 &= ~ (1 << i);
+      BitCount++;
+    }
+
+    if (BitCount > 5) {
+      NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE;
+      MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO);
+    } else {
+      MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *  Program MTRRs to describe given range as given cache type.  Use MTRR pairs
+ *  starting with the given MTRRphys Base address, and use as many as is
+ *  required up to (excluding) MSR 020C, which is reserved for OS.
+ *
+ *  "Limit" in the context of this procedure is not the numerically correct
+ *  limit, but rather the Last address+1, for purposes of coding efficiency
+ *  and readability.  Size of a region is then Limit-Base.
+ *
+ *  1. Size of each range must be a power of two
+ *  2. Each range must be naturally aligned (Base is same as size)
+ *
+ *  There are two code paths: the ascending path and descending path (analogous
+ *  to bsf and bsr), where the next limit is a function of the next set bit in
+ *  a forward or backward sequence of bits (as a function of the Limit).  We
+ *  start with the ascending path, to ensure that regions are naturally aligned,
+ *  then we switch to the descending path to maximize MTRR usage efficiency.
+ *  Base=0 is a special case where we start with the descending path.
+ *  Correct Mask for region is 2comp(Size-1)-1,
+ *  which is 2comp(Limit-Base-1)-1 *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     Base - Base address[47:16] of specified range.
+ *     @param[in]     *LimitPtr - Limit address[47:16] of specified range.
+ *     @param[in]     MtrrAddr - address of var MTRR pair to start using.
+ *     @param[in]     MtrrType - Cache type for the range.
+ *
+ *     @return      TRUE - No failure occurred
+ *     @return      FALSE - Failure occurred because run out of variable-size MTRRs before completion.
+ */
+
+BOOLEAN
+STATIC
+MemNSetMTRRrangeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Base,
+  IN OUT   UINT32 *LimitPtr,
+  IN       UINT32 MtrrAddr,
+  IN       UINT8 MtrrType
+  )
+{
+  S_UINT64 SMsr;
+  UINT32 CurBase;
+  UINT32 CurLimit;
+  UINT32 CurSize;
+  UINT32 CurAddr;
+  UINT32 Value32;
+
+  CurBase = Base;
+  CurLimit = *LimitPtr;
+  CurAddr = MtrrAddr;
+
+  while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) {
+    CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase);
+    CurLimit += CurBase;
+    if ((CurBase == 0) || (*LimitPtr < CurLimit)) {
+      CurLimit = *LimitPtr - CurBase;
+      CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit);
+      CurLimit += CurBase;
+    }
+
+    // prog. MTRR with current region Base
+    SMsr.lo = (CurBase << 16) | (UINT32)MtrrType;
+    SMsr.hi = CurBase >> (32 - 16);
+    LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+    // prog. MTRR with current region Mask
+    CurAddr++;                              // other half of MSR pair
+    Value32 = CurSize - (UINT32)1;
+    Value32 = ~Value32;
+    SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk;
+    SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID);
+    LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+    CurBase = CurLimit;
+    CurAddr++;                              // next MSR pair
+  }
+
+  if (CurLimit < *LimitPtr) {
+    // Announce failure
+    *LimitPtr = CurLimit;
+    IDS_ERROR_TRAP;
+  }
+
+  while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) {
+    SMsr.lo = SMsr.hi = 0;
+    LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+    CurAddr++;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Program one MTRR to describe Uma region as UC cache type if we detect running out of
+ *     Mtrr circumstance.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     *BasePtr - Base address[47:24] of specified range.
+ *     @param[in]     *LimitPtr - Limit address[47:24] of specified range.
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemNSetMTRRUmaRegionUCNb  (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 *BasePtr,
+  IN OUT   UINT32 *LimitPtr
+  )
+{
+  S_UINT64 SMsr;
+  UINT32 Mtrr;
+  UINT32 Size;
+  UINT32 Value32;
+
+  Size = *LimitPtr - *BasePtr;
+  Mtrr = 0x20A; //Reserved pair of MTRR for UMA region.
+
+  // prog. MTRR with current region Base
+  SMsr.lo = *BasePtr  << 16;
+  SMsr.hi = *BasePtr >> (32 - 16);
+  LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+  // prog. MTRR with current region Mask
+  Mtrr++;                              // other half of MSR pair
+  Value32 = Size - (UINT32)1;
+  Value32 = ~Value32;
+  SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk;
+  SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID);
+  LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *     Report the Uma size that is going to be allocated.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          Uma size [31:0] = Addr [47:16]
+ */
+UINT32
+MemNGetUmaSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return 0;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function allocates 16MB of memory for C6 storage when it is requested to be enabled
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+VOID
+MemNAllocateC6StorageNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT32 NodeSysLimit;
+  S_UINT64 SMsr;
+
+  if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
+    NodeSysLimit = NBPtr->MCTPtr->NodeSysLimit;
+    NodeSysLimit -= _16MB_RJ16;
+
+    // Set Dram Limit
+    NBPtr->MCTPtr->NodeSysLimit -= NodeSysLimit;
+    NBPtr->RefPtr->SysLimit -= NodeSysLimit;
+    MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000));
+
+    // Set TOPMEM
+    NodeSysLimit += 1;
+    SMsr.hi = NodeSysLimit >> (32 - 16);
+    SMsr.lo = NodeSysLimit << 16;
+    if (NodeSysLimit < _4GB_RJ16) {
+      LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    } else {
+      LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
+    }
+
+    // Set C6Base and C6DramLock
+    MemNSetBitFieldNb (NBPtr, BFC6Base, NodeSysLimit >> (24 - 16));
+    MemNSetBitFieldNb (NBPtr, BFC6DramLock, 1);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c
new file mode 100755
index 0000000000..7c188e0e28
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c
@@ -0,0 +1,1086 @@
+/**
+ * @file
+ *
+ * mnphy.c
+ *
+ * Common Northbridge Phy support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "PlatformMemoryConfiguration.h"
+#include "heapManager.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNPHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_CLK 4
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Type of an entry for processing phy init compensation for client NB
+typedef struct {
+  BIT_FIELD_NAME IndexBitField;          ///< Bit field on which the value is decided
+  BIT_FIELD_NAME StartTargetBitField;    ///< First bit field to be modified
+  BIT_FIELD_NAME EndTargetBitField;      ///< Last bit field to be modified
+  UINT16 ExtraValue;                     ///< Extra value needed to be written to bit field
+  CONST UINT16 (*TxPrePN)[3][5];         ///< Pointer to slew rate table
+} PHY_COMP_INIT_CLIENTNB;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets a delay value a PCI register during training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *
+ *     @return      Value read
+ */
+
+UINT32
+MemNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  )
+{
+  return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets a delay value a PCI register during training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *
+ */
+
+VOID
+MemNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes prototypical Phy fence training function.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPhyFenceTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  NBPtr->MemPPhyFenceTrainingNb (NBPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes prototypical Phy fence training function.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPhyFenceTrainingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 FenceThresholdTxDll;
+  UINT8 FenceThresholdRxDll;
+  UINT8 FenceThresholdTxPad;
+  UINT16 Fence2Data;
+
+  // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b.
+  // 2. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training].
+  // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll].
+  MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2);
+  MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence);
+  IDS_HDT_CONSOLE ("\t\tFenceThresholdTxDll\n");
+  MemNTrainPhyFenceNb (NBPtr);
+  FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+
+  // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b.
+  MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000);
+
+  // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b.
+  // 6. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training].
+  // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll].
+  MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1);
+  MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence);
+  IDS_HDT_CONSOLE ("\n\t\tFenceThresholdRxDll\n");
+  MemNTrainPhyFenceNb (NBPtr);
+  FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+
+  // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b.
+  MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000);
+
+  // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b.
+  // 10. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training].
+  // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad].
+  MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3);
+  MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
+  IDS_HDT_CONSOLE ("\n\t\tFenceThresholdTxPad\n");
+  MemNTrainPhyFenceNb (NBPtr);
+  FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
+
+  // Program Fence2 threshold for Clk, Cmd, and Addr
+  if (FenceThresholdTxPad < 16) {
+    MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10);
+    MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10);
+    MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10);
+  } else {
+    MemNSetBitFieldNb (NBPtr, BFClkFence2, 0);
+    MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0);
+    MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0);
+  }
+
+  // Program Fence2 threshold for data
+  Fence2Data = 0;
+  if (FenceThresholdTxPad < 16) {
+    Fence2Data |= FenceThresholdTxPad | 0x10;
+  }
+  if (FenceThresholdRxDll < 16) {
+    Fence2Data |= (FenceThresholdRxDll | 0x10) << 10;
+  }
+  if (FenceThresholdTxDll < 16) {
+    Fence2Data |= (FenceThresholdTxDll | 0x10) << 5;
+  }
+  MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data);
+
+  // Reprogram F2x9C_04.
+  MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function executes Phy fence training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNTrainPhyFenceNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Byte;
+  UINT16 Avg;
+  UINT8 PREvalue;
+
+  if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) {
+    return;
+  }
+
+  // 1. BIOS first programs a seed value to the phase recovery
+  //    engine registers.
+  //
+  IDS_HDT_CONSOLE ("\t\tSeeds: ");
+  for (Byte = 0; Byte < 9; Byte++) {
+    // This includes ECC as byte 8
+    MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19);
+    IDS_HDT_CONSOLE ("%02x ", 19);
+  }
+
+  IDS_HDT_CONSOLE ("\n\t\tPhyFenceTrEn = 1");
+  // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1.
+  MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1);
+
+  if (!NBPtr->IsSupported[ClientNbFence]) {
+    // 3. Wait 200 MEMCLKs.
+    MemUWait10ns (500, NBPtr->MemPtr);
+  } else {
+    // 3. Wait 2000 MEMCLKs.
+    MemUWait10ns (5000, NBPtr->MemPtr);
+  }
+
+  // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0.
+  MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0);
+
+  // 5. BIOS reads the phase recovery engine registers
+  //    F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52.
+  // 6. Calculate the average value of the fine delay and subtract 8.
+  //
+  Avg = 0;
+  IDS_HDT_CONSOLE ("\n\t\t  PRE: ");
+  for (Byte = 0; Byte < 9; Byte++) {
+    // This includes ECC as byte 8
+    PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte)));
+    Avg = Avg + ((UINT16) PREvalue);
+    IDS_HDT_CONSOLE ("%02x ", PREvalue);
+  }
+  Avg = ((Avg + 8) / 9);    // round up
+
+  Avg -= 8;
+  NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg);
+
+  IDS_HDT_CONSOLE ("\n\t\tFence: %02x\n", Avg);
+
+  // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence].
+  MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg);
+
+  // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control
+  //    Register delays for both channels. This forces the phy to recompute
+  //    the fence.
+  //
+  MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
+  CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
+  CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
+  CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
+  UINT8 i;
+  UINT8 j;
+  UINT8 CurrDct;
+  UINT8 CurrChannel;
+  BOOLEAN MarginImprv;
+  MarginImprv = FALSE;
+  CurrDct = NBPtr->Dct;
+  CurrChannel = NBPtr->Channel;
+  if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) {
+    if (NBPtr->MCTPtr->GangedMode == FALSE) {
+      for (i = 0; i < NBPtr->DctCount; i++) {
+        MemNSwitchDCTNb (NBPtr, i);
+        for (j = 0; j < NBPtr->ChannelCount; j++) {
+          NBPtr->SwitchChannel (NBPtr, j);
+          if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) {
+            MarginImprv = TRUE;
+          }
+        }
+      }
+      MemNSwitchDCTNb (NBPtr, CurrDct);
+      NBPtr->SwitchChannel (NBPtr, CurrChannel);
+    }
+  }
+
+  // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // DisAutoComp will be cleared after Dram init has completed
+  //
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+  MemUWait10ns (500, NBPtr->MemPtr);
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+
+  // 3. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
+  // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
+  //
+  // 4. For each normalized driver strength code read from
+  // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
+  // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
+  // D3Cmp2PCal].
+  //
+  j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
+  i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
+
+  MemNSwitchDCTNb (NBPtr, 0);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
+  MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
+
+  if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) {
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]);
+  }
+  if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) {
+    ASSERT (i <= 3);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
+    MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
+  }
+  MemNSwitchDCTNb (NBPtr, CurrDct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This is a general purpose function that executes before DRAM training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNBeforeDQSTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 TestAddrRJ16;
+  UINT32 RealAddr;
+
+  MemTBeginTraining (NBPtr->TechPtr);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    MemNSwitchDCTNb (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+        if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
+
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
+
+          MemUDummyCLRead (RealAddr);
+
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
+          MemUWait10ns (60, NBPtr->MemPtr);   // Wait 300ns
+          MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
+          MemUWait10ns (400, NBPtr->MemPtr);  // Wait 2us
+          MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
+          break;
+        }
+      }
+    }
+    if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
+      if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
+      }
+      if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
+        MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
+      }
+    }
+  }
+
+  MemTEndTraining (NBPtr->TechPtr);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     Returns the parameters for a requested delay value to be used in training
+ *     The correct Min, Max and Mask are determined based on the type of Delay,
+ *     and the frequency
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] TrnDly - Type of delay
+ *     @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
+ *
+ */
+
+VOID
+MemNGetTrainDlyParmsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  )
+{
+  Parms->Min = 0;
+
+  if (TrnDly == AccessWrDatDly) {
+    Parms->Max = 0x1F;
+    Parms->Mask = 0x01F;
+  } else if (TrnDly == AccessRdDqsDly) {
+    if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) {
+      Parms->Max = 0x3E;
+      Parms->Mask = 0x03E;
+    } else {
+      Parms->Max = 0x1F;
+      Parms->Mask = 0x01F;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+MemNcmnGetSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Rank;
+  UINT8 Byte;
+  UINT8 Nibble;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Rank = DRBN_RANK (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+  Nibble = DRBN_NBBL (DrbnVar);
+
+  ASSERT (Dimm < 4);
+  ASSERT (Byte <= ECC_DLY);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    if (Byte > 7) {
+      Index += 2;
+    }
+    Offset = 16 * (Byte % 2);
+    Index |= (Rank << 8);
+    Index |= (Nibble << 9);
+    break;
+
+  case AccessRdDqsDly:
+  case AccessWrDatDly:
+
+    if (NBPtr->IsSupported[DimmBasedOnSpeed]) {
+      if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) {
+        // if DDR speed is below 800, use DIMM 0 delays for all DIMMs.
+        Dimm = 0;
+      }
+    }
+
+    Index += (Dimm * 0x100);
+    if (Nibble) {
+      if (Rank) {
+        Index += 0xA0;
+      } else {
+        Index += 0x70;
+      }
+    } else if (Rank) {
+      Index += 0x60;
+    }
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+  Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset)));
+    MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+    MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF);
+  }
+
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+UINT32
+MemNcmnGetSetTrainDlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Byte;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+
+  if ((Dimm > 1) || (Byte > 7)) {
+    // LN only support DIMM 0 and 8 byte lanes.
+    return 0;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    Offset = 16 * (Byte % 2);
+    break;
+
+  case AccessRdDqsDly:
+  case AccessWrDatDly:
+    Index += (Dimm * 0x100);
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
+    MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    Value = (Value >> Offset) & 0xFF;
+  }
+
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function initializes the training pattern.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      AGESA_STATUS - Result
+ *                  AGESA_SUCCESS - Training pattern is ready to use
+ *                  AGESA_ERROR   - Unable to initialize the pattern.
+ */
+
+AGESA_STATUS
+MemNTrainingPatternInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  POS_TRN_PATTERN_TYPE TrainPattern;
+  AGESA_STATUS Status;
+
+  TechPtr = NBPtr->TechPtr;
+  //
+  // Determine pattern to be used
+  //
+  if (NBPtr->PosTrnPattern == POS_PATTERN_256B) {
+    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+      TrainPattern = TestPatternJD256B;
+      TechPtr->PatternLength = 64;
+    } else {
+      TrainPattern = TestPatternJD256A;
+      TechPtr->PatternLength = 32;
+    }
+  } else {
+    //
+    // 72 bit pattern will be used if PosTrnPattern is not specified
+    //
+    if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
+      TrainPattern = TestPatternJD1B;
+      TechPtr->PatternLength = 18;
+    } else {
+      TrainPattern = TestPatternJD1A;
+      TechPtr->PatternLength = 9;
+    }
+  }
+  //
+  // Allocate training buffer
+  //
+  AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16;
+  AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr;
+  AlignPointerTo16Byte (&TechPtr->PatternBufPtr);
+  TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64);
+
+  // Prepare training pattern
+  MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
+
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function finalizes the training pattern.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       Index    - Index of Write Data Delay Value
+ *     @param[in,out]   *Value   - Write Data Delay Value
+ *     @return      BOOLEAN - TRUE - Use the value returned.
+ *                            FALSE - No more values in table.
+ */
+
+BOOLEAN
+MemNGetApproximateWriteDatDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Index,
+  IN OUT   UINT8 *Value
+  )
+{
+  CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F};
+  if (Index < GET_SIZE_OF (WriteDatDelayValue)) {
+    *Value = WriteDatDelayValue[Index];
+    return TRUE;
+  }
+  return FALSE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function finalizes the training pattern.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return      AGESA_STATUS - Result
+ *                  AGESA_SUCCESS - Training pattern has been finalized.
+ *                  AGESA_ERROR   - Unable to initialize the pattern.
+ */
+
+AGESA_STATUS
+MemNTrainingPatternFinalizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AGESA_STATUS Status;
+  //
+  // Deallocate training buffer
+  //
+  Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the number of chipselects per channel.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return
+ */
+
+UINT8
+MemNCSPerChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return MAX_CS_PER_CHANNEL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the number of Chipselects controlled by each set
+ *     of Delay registers under current conditions.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return
+ */
+
+UINT8
+MemNCSPerDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return MAX_CS_PER_DELAY;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the minimum data eye width in 32nds of a UI for
+ *     the type of data eye(Rd/Wr) that is being trained.  This value will
+ *     be the minimum number of consecutive delays that yield valid data.
+ *     Uses TechPtr->Direction to determine read or write.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return
+ */
+
+UINT8
+MemNMinDataEyeWidthNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (NBPtr->TechPtr->Direction == DQS_READ_DIR) {
+    return MIN_RD_DATAEYE_WIDTH_NB;
+  } else {
+    return MIN_WR_DATAEYE_WIDTH_NB;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function programs the phy registers according to the desired phy VDDIO voltage level
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNPhyVoltageLevelClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BIT_FIELD_NAME BitField;
+  UINT16 Value;
+  UINT16 Mask;
+
+  Mask = 0xFFE7;
+  Value = (UINT16) NBPtr->RefPtr->DDR3Voltage << 3;
+
+  /// @todo: Need to verify if the following logic can work on real hardware or not
+  for (BitField = BFDataRxVioLvl; BitField <= BFCmpVioLvl; BitField++) {
+    if (BitField == BFCmpVioLvl) {
+      Mask = 0x3FFF;
+      Value <<= (14 - 3);
+    }
+    MemNBrdcstSetNb (NBPtr, BitField, ((MemNGetBitFieldNb (NBPtr, BitField) & Mask)) | Value);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function adjusts Avg PRE value of Phy fence training according to specific CPU family.
+ *
+ *     @param[in,out]   *NBPtr  - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *Value16 - Pointer to the value that we want to adjust
+ *
+ */
+VOID
+MemNPFenceAdjustClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *Value16
+  )
+{
+  *Value16 += 2; //for LN, the Avg PRE value is subtracted by 6 only.
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the DDR phy compensation logic
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemNInitPhyCompClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // Slew rate table array [x][y][z]
+  // array[0]: slew rate for VDDIO 1.5V
+  // array[1]: slew rate for VDDIO 1.35V
+  // array[x][y]: slew rate for a certain frequency
+  // array[x][y][0]: frequency mask for current entry
+  CONST STATIC UINT16 TxPrePNDataDqs[2][3][5] = {
+    {{ (UINT16) DDR800, 0xFF6, 0xDAD, 0xDAD, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}
+  };
+  CONST STATIC UINT16 TxPrePNCmdAddr[2][3][5] = {
+    {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
+     { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB},
+     { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}},
+    {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
+     { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB},
+     { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}}
+  };
+  CONST STATIC UINT16 TxPrePNClock[2][3][5] = {
+    {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
+    {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924},
+     { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD},
+     { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}}
+  };
+
+  CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = {
+    // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V.
+    //    A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}.
+    //    B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}.
+    {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs},
+    {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs},
+    {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs},
+    // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V.
+    //    A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}.
+    //    B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}.
+    {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr},
+    {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr},
+    {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr},
+    {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr},
+    {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr},
+    // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V.
+    //    A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}.
+    {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock}
+  };
+
+  BIT_FIELD_NAME CurrentBitField;
+  UINT16 SpeedMask;
+  CONST UINT16 (*TxPrePNArray)[5];
+  UINT8 Voltage;
+  UINT8 i;
+  UINT8 j;
+  UINT8 k;
+
+  // 1. Program D18F2x[1,0]9C_x0000_0008[DisAutoComp] = 1.
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+  // 2. Program D18F2x[1,0]9C_x0D0F_E003[DisalbePredriverCal]=1
+  MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, (1 << 13));
+
+  SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66);
+  Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage;
+
+  for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) {
+    i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField);
+    TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage];
+    for (k = 0; k < 3; k ++) {
+      if ((TxPrePNArray[k][0] & SpeedMask) != 0) {
+        for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) {
+          MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1]));
+        }
+        break;
+      }
+    }
+    ASSERT (k < 3);
+  }
+
+  // 6. Program D18F2x[1,0]9C_x0000_0008[DisAutoComp] = 0.
+  MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
new file mode 100755
index 0000000000..39b54d00fe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c
@@ -0,0 +1,396 @@
+/**
+ * @file
+ *
+ * mnreg.c
+ *
+ * Common Northbridge register access functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/)
+ * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#define FILECODE PROC_MEM_NB_MNREG_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemNSwitchDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  ASSERT (NBPtr->DctCount > 1);
+  NBPtr->Dct = Dct ? 1 : 0;
+  NBPtr->MCTPtr->Dct = NBPtr->Dct;
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+  NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]);
+  NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]);
+
+  MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemNSwitchChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = Channel ? 1 : 0;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function gets a bit field from PCI register
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Field name
+ *
+ *     @return      Bit field value
+ */
+
+UINT32
+MemNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  )
+{
+  UINT32 Value;
+
+  ASSERT (FieldName < BFEndOfList);
+  Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0);
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets a bit field from PCI register
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Field name
+ *     @param[in]   Field - Value to be stored in PCT register
+ *
+ */
+
+VOID
+MemNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  ASSERT (FieldName < BFEndOfList);
+  NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
+ *  DCTs that are disabled.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be checked
+ *
+ *     @return          TRUE -  All enabled DCTs have the expected value on the bitfield.
+ *     @return          FALSE - Not all enabled DCTs have the expected value on the bitfield.
+ *
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNBrdcstCheckNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  UINT8 Dct;
+  UINT8 CurrentDCT;
+  Dct = NBPtr->Dct;
+  for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
+    MemNSwitchDCTNb (NBPtr, CurrentDCT);
+    if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) {
+      if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) {
+        MemNSwitchDCTNb (NBPtr, Dct);
+        return FALSE;
+      }
+    }
+  }
+  MemNSwitchDCTNb (NBPtr, Dct);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Set bitfields of all enabled DCTs on a die to a value. Ignore
+ *  DCTs that are disabled.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be set
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNBrdcstSetNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  UINT8 Dct;
+  UINT8 CurrentDCT;
+  Dct = NBPtr->Dct;
+  for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
+    MemNSwitchDCTNb (NBPtr, CurrentDCT);
+    if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) {
+      MemNSetBitFieldNb (NBPtr, FieldName, Field);
+    }
+  }
+  MemNSwitchDCTNb (NBPtr, Dct);
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *      This function calculates the memory channel index relative to the
+ *      socket, taking the Die number, the Dct, and the channel.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in] Dct
+ *     @param[in] Channel
+ *
+ */
+UINT8
+MemNGetSocketRelativeChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  )
+{
+  return ((NBPtr->MCTPtr->DieId *NBPtr->DctCount) + Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Poll a bitfield. If the bitfield does not get set to the target value within
+ *  specified microseconds, it times out.
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Bit Field name
+ *     @param[in]   Field - Value to be set
+ *     @param[in]   MicroSecond - Number of microsecond to wait
+ *     @param[in]   IfBroadCast - Need to broadcast to both DCT or not
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemNPollBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field,
+  IN       UINT32 MicroSecond,
+  IN       BOOLEAN IfBroadCast
+  )
+{
+  UINT8 ExcludeDCT;
+  UINT16 ExcludeChipSelMask;
+  UINT32 EventInfo;
+  UINT64 InitTSC;
+  UINT64 CurrentTSC;
+  UINT64 TimeOut;
+  AGESA_STATUS EventClass;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  BOOLEAN TimeoutEn;
+
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  ExcludeDCT = EXCLUDE_ALL_DCT;
+  ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL;
+  TimeoutEn = TRUE;
+  IDS_TIMEOUT_CTL (&TimeoutEn);
+
+  CurrentTSC = 0;
+  LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader);
+  TimeOut = InitTSC + ((UINT64) MicroSecond * 1600);
+
+  while ((CurrentTSC < TimeOut) || !TimeoutEn) {
+    if (IfBroadCast) {
+      if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) {
+        break;
+      }
+    } else {
+      if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) {
+        break;
+      }
+    }
+    LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader);
+  }
+
+  if ((CurrentTSC >= TimeOut) && TimeoutEn) {
+    // Default event class
+    // If different event class is needed in one entry, override it.
+    EventClass = AGESA_ERROR;
+    switch (FieldName) {
+    case BFDramEnabled:
+      EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT;
+      break;
+    case BFDctAccessDone:
+      EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFSendCtrlWord:
+      EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFPrefDramTrainMode:
+      EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFEnterSelfRef:
+      EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT;
+      break;
+    case BFFreqChgInProg:
+      EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFExitSelfRef:
+      EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT;
+      break;
+    case BFSendMrsCmd:
+      EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFSendZQCmd:
+      EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFDctExtraAccessDone:
+      EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    case BFMemClrBusy:
+      EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT;
+      break;
+    case BFMemCleared:
+      EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT;
+      break;
+    case BFFlushWr:
+      EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT;
+      ExcludeDCT = NBPtr->Dct;
+      break;
+    default:
+      EventClass = 0;
+      EventInfo = 0;
+      IDS_ERROR_TRAP;
+    }
+
+    PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader);
+    SetMemError (EventClass, MCTPtr);
+    MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader);
+  }
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c
new file mode 100755
index 0000000000..85e476c6da
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c
@@ -0,0 +1,127 @@
+/**
+ * @file
+ *
+ * mntrain2.c
+ *
+ * Common Northbridge function for training flow for DDR2
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates DQS training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemNDQSTiming2Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
+    AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
+    AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr);
+    AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
+    //Execute Technology specific training features
+    if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
+      if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
+        MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
+        if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) {
+          if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) {
+            MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
+            if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) {
+              MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
+            }
+          }
+        }
+      }
+    }
+    MemTMarkTrainFail (TechPtr);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c
new file mode 100755
index 0000000000..b3b2075561
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c
@@ -0,0 +1,193 @@
+/**
+ * @file
+ *
+ * mntrain3.c
+ *
+ * Common Northbridge function for training flow for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE
+/* features */
+#include "mftds.h"
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTHwWlPart2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates DQS training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+BOOLEAN
+MemNDQSTiming3Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_TECH_BLOCK *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+  if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
+    AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
+    if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {
+      // Right now we do not have anything to do if the callout is implemented
+    }
+    AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
+    //Execute Technology specific training features
+    if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) {
+      if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) {
+        MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);
+        if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) {
+          MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);
+          if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {
+            MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);
+            // If target speed is higher than start-up speed, do frequency change and second pass of WL
+            if (MemTHwWlPart2 (TechPtr)) {
+              if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) {
+                IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));
+                if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
+                  if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
+                    MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
+                    if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) {
+                      if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) {
+                        MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
+                        do {
+                          if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) {
+                            MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
+                          }
+                        } while (NBPtr->ChangeNbFrequency (NBPtr));
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+    MemTMarkTrainFail (TechPtr);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function executes HW WL at multiple speeds
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @return       TRUE - No errors occurred
+ *                   FALSE - errors occurred
+ */
+
+BOOLEAN
+STATIC
+MemTHwWlPart2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  BOOLEAN retVal;
+  retVal = TRUE;
+  while (TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) {
+    TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
+    if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) {
+      if (!memTechTrainingFeatDDR3.HwBasedWLTrainingPart2 (TechPtr)) {
+        retVal = FALSE;
+        break;
+      }
+      MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2);
+      if (!memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) {
+        retVal = FALSE;
+        break;
+      }
+      MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2);
+    } else {
+      retVal = FALSE;
+      break;
+    }
+  }
+  return retVal;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c
new file mode 100755
index 0000000000..a66e720371
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mprc32_3.c
@@ -0,0 +1,322 @@
+/**
+ * @file
+ *
+ * mprc32_3.c
+ *
+ * Platform specific settings for C32 DDR3 R-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_C32_MPRC32_3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define AMD_FAMILY_10_C32    AMD_FAMILY_10_HY
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsRC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitRC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ * ODT Settings for 1 or 2 Dimms Per Channel
+ *
+ * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
+ */
+STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm2D[] = {
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
+  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
+  {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
+  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
+  {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
+};
+/*
+ * ODT Settings for 3 Dimms Per Channel
+ *
+ * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
+ */
+STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm3D[] = {
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
+  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
+};
+/*
+ * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel
+ *
+ * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
+ */
+STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit1D[] = {
+  {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}
+};
+/*
+ * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel
+ *
+ * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
+ */
+STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit2D[] = {
+  {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0},
+  {SR_DIMM0 + SR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
+  {QR_DIMM0 + ANY_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0},
+  {ANY_DIMM0 + QR_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
+};
+/*
+ * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel
+ *
+ * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
+ */
+STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
+  {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {SR_DIMM0 + SR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
+  {QR_DIMM1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
+  {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0},
+  {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
+
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsRC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsRC32_3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRC32_3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for R-DDR3 C32 DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsRC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) {
+    DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm2D);
+    DramTermPtr = C32RDdr3DramTerm2D;
+  } else if (MaxDimmsPerChannel == 3) {
+    DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm3D);
+    DramTermPtr = C32RDdr3DramTerm3D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+  //
+  // Special Cases for certain configs not covered by the table
+  //
+  // SR-SR-SR 1.5v @1066 (Currently only 3DPCH config at 1066)
+  if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3) &&
+      (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY)) {
+    NBPtr->PsPtr->DramTerm = 5; //30 Ohms
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for R-DDR3 C32 DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitRC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmPerCH;
+  UINT8 FreqLimitSize;
+  UINT16 SpeedLimit;
+  CONST POR_SPEED_LIMIT *FreqLimitPtr;
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (MaxDimmPerCH == 4) {
+    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+    return;
+  } else if (MaxDimmPerCH == 3) {
+    FreqLimitPtr = C32RDdr3PSPorFreqLimit3D;
+    FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit3D);
+  } else if (MaxDimmPerCH == 2) {
+    FreqLimitPtr = C32RDdr3PSPorFreqLimit2D;
+    FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit2D);
+  } else {
+    FreqLimitPtr = C32RDdr3PSPorFreqLimit1D;
+    FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit1D);
+  }
+
+  SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr);
+
+  if (SpeedLimit != 0) {
+    if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+      DCTPtr->Timings.TargetSpeed = SpeedLimit;
+    }
+  } else {
+    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c
new file mode 100755
index 0000000000..b216b6f61b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/C32/mpuc32_3.c
@@ -0,0 +1,200 @@
+/**
+ * @file
+ *
+ * mpuc32_3.c
+ *
+ * Platform specific settings for C32 DDR3 U-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define AMD_FAMILY_10_C32    AMD_FAMILY_10_HY
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsUC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitUC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsUC32_3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for U-DDR3 C32 DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsUC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for SO-DDR3 C32
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitUC32_3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16 MaxSpeed;
+  //
+  // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066
+  //
+  if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) {
+    MaxSpeed = DDR1066_FREQUENCY;
+  } else {
+    //
+    // Highest POR supported speed for Unbuffered dimm is 1333
+    //
+    MaxSpeed = DDR1333_FREQUENCY;
+  }
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
+  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
+    // Unbuffered DDR3 at 333MHz is not supported
+    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
new file mode 100755
index 0000000000..fc93470c9c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda2.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * mpsda2.c
+ *
+ * Platform specific settings for DA DDR2 SO-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support S1g3 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DA_MPSDA2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsSDA2 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
+  {DDR533 + DDR667 + DDR800, ONE_DIMM, ANY_NUM, 2, 0, 0},
+  {DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor the platform specific settings for SO-DIMM DA DDR2
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsSDA2 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PsPtr->MemPDoPs = MemPDoPsSDA2;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for SO-DIMM DA DDR2
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsSDA2 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DaSDdr2DramTerm), DaSDdr2DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c
new file mode 100755
index 0000000000..925887be16
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpsda3.c
@@ -0,0 +1,252 @@
+/**
+ * @file
+ *
+ * mpsda3.c
+ *
+ * Platform specific settings for DA DDR3 SO-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DA_MPSDA3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsSDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitSDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm1D[] = {
+  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
+  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
+};
+
+STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor the platform specific settings for SO-DIMM DA DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsSDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PsPtr->MemPDoPs = MemPDoPsSDA3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSDA3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for SO-DIMM DA DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsSDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if (MaxDimmsPerChannel == 1) {
+    DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm1D);
+    DramTermPtr = DaSDdr3DramTerm1D;
+  } else if (MaxDimmsPerChannel == 2) {
+    DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm2D);
+    DramTermPtr = DaSDdr3DramTerm2D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for SO-DDR3 DA
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitSDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmPerCH;
+  UINT16 SpeedLimit;
+
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (MaxDimmPerCH == 1) {
+    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+      //
+      // Highest POR supported speed for SODimm is 1333
+      //
+      SpeedLimit = DDR1333_FREQUENCY;
+    } else {
+      //
+      // Max LV DDR3 Speed is 1066 for this silicon
+      //
+      SpeedLimit = DDR1066_FREQUENCY;
+    }
+  } else {
+    //
+    // Highest supported speed in 2DPC configuration is 1066
+    //
+    SpeedLimit = DDR1066_FREQUENCY;
+    //
+    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
+    //
+    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
+       (NBPtr->ChannelPtr->Dimms == 2)) {
+      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
+      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    }
+  }
+
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c
new file mode 100755
index 0000000000..ec9fc8b2e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DA/mpuda3.c
@@ -0,0 +1,229 @@
+/**
+ * @file
+ *
+ * mpuda3.c
+ *
+ * Platform specific settings for DA DDR3 U-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DA_MPUDA3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsUDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitUDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PsPtr->MemPDoPs = MemPDoPsUDA3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUDA3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for U-DDR3 DA DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsUDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for U-DDR3 DA
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitUDA3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmPerCH;
+  UINT16 SpeedLimit;
+
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (MaxDimmPerCH == 1) {
+    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+      //
+      // Highest POR supported speed for Unbuffered dimm is 1333
+      //
+      SpeedLimit = DDR1333_FREQUENCY;
+    } else {
+      //
+      // Max LV DDR3 Speed is 1066 for this silicon
+      //
+      SpeedLimit = DDR1066_FREQUENCY;
+    }
+  } else {
+    //
+    // Highest supported speed in 2DPC configuration is 1066
+    //
+    SpeedLimit = DDR1066_FREQUENCY;
+    //
+    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
+    //
+    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
+       (NBPtr->ChannelPtr->Dimms == 2)) {
+      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
+      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    }
+  }
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
+  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
+    // Unbuffered DDR3 at 333MHz is not supported
+    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
new file mode 100755
index 0000000000..6a50aaf936
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr2.c
@@ -0,0 +1,161 @@
+/**
+ * @file
+ *
+ * mprdr2.c
+ *
+ * Platform specific settings for DR DDR2 R-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DR_MPRDR2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsRDr2 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
+  {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
+  {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
+  {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
+};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsRDr2 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsRDr2;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for R-DDR2 DR DDR2
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsRDr2 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
new file mode 100755
index 0000000000..927647f7ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mprdr3.c
@@ -0,0 +1,200 @@
+/**
+ * @file
+ *
+ * mprdr3.c
+ *
+ * Platform specific settings for DR DDR3 R-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DR_MPRDR3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsRDr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm2D[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
+  {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
+  {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
+  {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
+  {DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
+};
+
+STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
+  {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsRDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsRDr3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for R-DDR3 DR DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsRDr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if (MaxDimmsPerChannel == 2) {
+    DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm2D);
+    DramTermPtr = DrRDdr3DramTerm2D;
+  } else if (MaxDimmsPerChannel == 3) {
+    DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm3D);
+    DramTermPtr = DrRDdr3DramTerm3D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
new file mode 100755
index 0000000000..3155825a9f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpsdr3.c
@@ -0,0 +1,187 @@
+/**
+ * @file
+ *
+ * mpsdr3.c
+ *
+ * Platform specific settings for DR DDR3 SO-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DR_MPSDR3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsSDr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm1D[] = {
+  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
+  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
+};
+
+STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsSDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsSDr3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for S-DDR3 DR DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsSDr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if (MaxDimmsPerChannel == 1) {
+    DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm1D);
+    DramTermPtr = DrSDdr3DramTerm1D;
+  } else if (MaxDimmsPerChannel == 2) {
+    DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm2D);
+    DramTermPtr = DrSDdr3DramTerm2D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
new file mode 100755
index 0000000000..a7e1773b28
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr2.c
@@ -0,0 +1,161 @@
+/**
+ * @file
+ *
+ * mpudr2.c
+ *
+ * Platform specific settings for DR DDR2 U-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DR_MPUDR2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsUDr2 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
+  {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
+  {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
+  {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
+  {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
+};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUDr2 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsUDr2;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for U-DDR2 DR DDR2
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsUDr2 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
new file mode 100755
index 0000000000..f7edbb5a78
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/DR/mpudr3.c
@@ -0,0 +1,156 @@
+/**
+ * @file
+ *
+ * mpudr3.c
+ *
+ * Platform specific settings for DR DDR3 U-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "PlatformMemoryConfiguration.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_DR_MPUDR3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsUDr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsUDr3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for U-DDR3 DR DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsUDr3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
new file mode 100755
index 0000000000..ab2c1e3a03
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mprhy3.c
@@ -0,0 +1,325 @@
+/**
+ * @file
+ *
+ * mprhy3.c
+ *
+ * Platform specific settings for HY DDR3 R-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "GeneralServices.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_HY_MPRHY3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsRHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitRHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*
+ * ODT Settings for 1 Dimm or 2 Dimms Per Channel
+ *
+ * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
+ */
+STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm2D[] = {
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
+  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
+  {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
+  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
+  {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
+};
+/*
+ * ODT Settings for 3 Dimms Per Channel
+ *
+ * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
+ */
+STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm3D[] = {
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
+  {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
+  {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
+  {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
+};
+/*
+ * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel
+ *
+ * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
+ */
+STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit1D[] = {
+  {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}
+};
+/*
+ * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel
+ *
+ * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
+ */
+STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit2D[] = {
+  {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {QR_DIMM0 + ANY_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
+  {ANY_DIMM0 + QR_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}
+};
+/*
+ * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel
+ *
+ * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
+ */
+STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
+  {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
+  {QR_DIMM1, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
+  {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
+  {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
+  {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
+};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsRHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsRHy3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRHy3;
+
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for R-DDR3 HY DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsRHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) {
+    DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm2D);
+    DramTermPtr = HyRDdr3DramTerm2D;
+  } else if (MaxDimmsPerChannel == 3) {
+    DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm3D);
+    DramTermPtr = HyRDdr3DramTerm3D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+  //
+  // Special Cases for certain configs not covered by the table
+  //
+  // 3DPCH Fully populated.
+  if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) {
+    NBPtr->PsPtr->DramTerm = 5; //30 Ohms
+    NBPtr->PsPtr->QR_DramTerm = 1; // 60 Ohms
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for R-DDR3 HY
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitRHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmPerCH;
+  UINT8 FreqLimitSize;
+  UINT16 SpeedLimit;
+  CONST POR_SPEED_LIMIT *FreqLimitPtr;
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = NBPtr->DCTPtr;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (MaxDimmPerCH == 4) {
+    printk(BIOS_DEBUG, "MAX 4 Dimms per channel configuration \n");
+    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+    return;
+  } else if (MaxDimmPerCH == 3) {
+    printk(BIOS_DEBUG, "MAX 3 Dimms per channel configuration \n");
+    FreqLimitPtr = HyRDdr3PSPorFreqLimit3D;
+    FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D);
+  } else if (MaxDimmPerCH == 2) {
+    printk(BIOS_DEBUG, "MAX 2 Dimms per channel configuration \n");
+    FreqLimitPtr = HyRDdr3PSPorFreqLimit2D;
+    FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D);
+  } else {
+    printk(BIOS_DEBUG, "MAX 1 Dimms per channel configuration \n");
+    FreqLimitPtr = HyRDdr3PSPorFreqLimit1D;
+    FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D);
+  }
+
+  SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr);
+
+  if (SpeedLimit != 0) {
+    if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+      DCTPtr->Timings.TargetSpeed = SpeedLimit;
+    }
+  } else {
+    DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c
new file mode 100755
index 0000000000..c001dec9cf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpshy3.c
@@ -0,0 +1,216 @@
+/**
+ * @file
+ *
+ * mpshy3.c
+ *
+ * Platform specific settings for HY DDR3 SO-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsSHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitSHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = {
+  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
+  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
+};
+
+STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsSHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsSHy3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for S-DDR3 HY DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsSHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if (MaxDimmsPerChannel == 1) {
+    DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D);
+    DramTermPtr = HySDdr3DramTerm1D;
+  } else if (MaxDimmsPerChannel == 2) {
+    DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D);
+    DramTermPtr = HySDdr3DramTerm2D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for SO-DDR3 HY
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitSHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16  MaxSpeed;
+  //
+  // Highest POR supported speed for SODimm is 1333
+  //
+  MaxSpeed = DDR1333_FREQUENCY;
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c
new file mode 100755
index 0000000000..b93c67c9e0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/HY/mpuhy3.c
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * mpuhy3.c
+ *
+ * Platform specific settings for HY DDR3 U-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsUhy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitUHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+  PsPtr->MemPDoPs = MemPDoPsUhy3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for U-DDR3 HY DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsUhy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for U-DDR3 HY
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitUHy3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT16  MaxSpeed;
+  //
+  // Highest POR supported speed for Unbuffered dimm is 1333
+  //
+  MaxSpeed = DDR1333_FREQUENCY;
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
+  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
+    // Unbuffered DDR3 at 333MHz is not supported
+    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c
new file mode 100755
index 0000000000..0d4ee4151e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpsNi3.c
@@ -0,0 +1,252 @@
+/**
+ * @file
+ *
+ * mpsNi3.c
+ *
+ * Platform specific settings for Ni DDR3 SO-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_NI_MPSNI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsSNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitSNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm1D[] = {
+  {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
+  {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
+};
+
+STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor the platform specific settings for SO-DIMM Ni DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsSNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PsPtr->MemPDoPs = MemPDoPsSNi3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSNi3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for SO-DIMM Ni DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsSNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  CONST DRAM_TERM_ENTRY *DramTermPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 *DimmsPerChPtr;
+  UINT8 DramTermSize;
+
+  DramTermSize = 0;
+  DramTermPtr = NULL;
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmsPerChannel = *DimmsPerChPtr;
+  } else {
+    MaxDimmsPerChannel = 2;
+  }
+
+  if (MaxDimmsPerChannel == 1) {
+    DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm1D);
+    DramTermPtr = NiSDdr3DramTerm1D;
+  } else if (MaxDimmsPerChannel == 2) {
+    DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm2D);
+    DramTermPtr = NiSDdr3DramTerm2D;
+  } else {
+    IDS_ERROR_TRAP;
+  }
+
+  if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for SO-DDR3 Ni
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitSNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmPerCH;
+  UINT16 SpeedLimit;
+
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (MaxDimmPerCH == 1) {
+    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+      //
+      // Highest POR supported speed for SODimm is 1333
+      //
+      SpeedLimit = DDR1333_FREQUENCY;
+    } else {
+      //
+      // Max LV DDR3 Speed is 1066 for this silicon
+      //
+      SpeedLimit = DDR1066_FREQUENCY;
+    }
+  } else {
+    //
+    // Highest supported speed in 2DPC configuration is 1066
+    //
+    SpeedLimit = DDR1066_FREQUENCY;
+    //
+    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
+    //
+    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
+       (NBPtr->ChannelPtr->Dimms == 2)) {
+      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
+      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    }
+  }
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c
new file mode 100755
index 0000000000..cee7a02de6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/NI/mpuNi3.c
@@ -0,0 +1,230 @@
+/**
+ * @file
+ *
+ * mpuNi3.c
+ *
+ * Platform specific settings for Ni DDR3 U-DIMM system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Ps)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/* This file contains routine that add platform specific support L1 */
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "mport.h"
+#include "ma.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mp.h"
+#include "mu.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_NI_MPUNI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemPDoPsUNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+STATIC
+MemPGetPORFreqLimitUNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
+  {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
+  {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
+  {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
+  {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
+};
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in,out]   *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in,out]   *PsPtr       Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  ASSERT (MemPtr != 0);
+  ASSERT (ChannelPtr != 0);
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
+    return AGESA_UNSUPPORTED;
+  }
+  if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PsPtr->MemPDoPs = MemPDoPsUNi3;
+  PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUNi3;
+  return AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function sets the platform specific settings for U-DDR3 Ni DDR3
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *     @return          TRUE - Find settings for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find settings for corresponding platform and dimm population.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemPDoPsUNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
+    return FALSE;
+  }
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This is function gets the POR speed limit for U-DDR3 Ni
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ *
+ */
+VOID
+STATIC
+MemPGetPORFreqLimitUNi3 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmPerCH;
+  UINT16 SpeedLimit;
+
+  DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (MaxDimmPerCH == 1) {
+    if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+      //
+      // Highest POR supported speed for Unbuffered dimm is 1333
+      //
+      SpeedLimit = DDR1333_FREQUENCY;
+    } else {
+      //
+      // Max LV DDR3 Speed is 1066 for this silicon
+      //
+      SpeedLimit = DDR1066_FREQUENCY;
+    }
+  } else {
+    //
+    // Highest supported speed in 2DPC configuration is 1066
+    //
+    SpeedLimit = DDR1066_FREQUENCY;
+    //
+    // VOLT1_35 won't be supported while two DIMMs are populated in a channel
+    //
+    if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
+       (NBPtr->ChannelPtr->Dimms == 2)) {
+      NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
+      PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    }
+  }
+  if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
+    NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
+  } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
+    // Unbuffered DDR3 at 333MHz is not supported
+    NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
+    PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
+    // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
+    NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c
new file mode 100755
index 0000000000..a06971996f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Ps/mp.c
@@ -0,0 +1,231 @@
+/**
+ * @file
+ *
+ * mndr.c
+ *
+ * Common Northbridge functions for DR
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB/DR)
+ * @e \$Revision: 8446 $ @e \$Date: 2008-09-23 10:52:09 -0500 (Tue, 23 Sep 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "mp.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_PS_MP_FILECODE
+
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This is the default return function of the Platform Specific block. The function always
+ *    returns   AGESA_UNSUPPORTED
+ *
+ *     @param[in,out]   *MemPtr           Pointer to MEM_DATA_STRUCTURE
+ *     @param[in]       *ChannelPtr       Pointer to CH_DEF_STRUCT
+ *     @param[in]       *PsPtr            Pointer to MEM_PS_BLOCK
+ *
+ *     @return          AGESA_UNSUPPORTED  AGESA status indicating that default is unsupported
+ *
+ */
+
+AGESA_STATUS
+MemPConstructPsUDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  )
+{
+  return AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function will set the DramTerm and DramTermDyn in the structure of a channel.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *     @param[in]       ArraySize        Size of the array of DramTerm
+ *     @param[in]       *DramTermPtr     Address the array of DramTerm
+ *
+ *     @return          TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population.
+ *     @return          FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population.
+ *
+ */
+BOOLEAN
+MemPGetDramTerm (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ArraySize,
+  IN       CONST DRAM_TERM_ENTRY *DramTermPtr
+  )
+{
+  UINT8 Dimms;
+  UINT8 QR_Dimms;
+  UINT8 i;
+  Dimms = NBPtr->ChannelPtr->Dimms;
+  QR_Dimms = 0;
+  for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
+    if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) {
+      QR_Dimms ++;
+    }
+  }
+
+  for (i = 0; i < ArraySize; i ++) {
+    if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) {
+      if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) {
+        if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) ||
+            ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) ||
+            (DramTermPtr[i].QR_Dimms == ANY_NUM)) {
+          NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm;
+          NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm;
+          NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm;
+          break;
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function gets the highest POR supported speed.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *     @param[in]       FreqLimitSize    Size of the array of Frequency Limit
+ *     @param[in]       *FreqLimitPtr     Address the array of Frequency Limit
+ *
+ *     @return          UINT8 - frequency limit
+ *
+ */
+UINT16
+MemPGetPorFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 FreqLimitSize,
+  IN       CONST POR_SPEED_LIMIT *FreqLimitPtr
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 DimmTpMatch;
+  UINT16 SpeedLimit;
+  UINT16 DIMMRankType;
+  UINT16 _DIMMRankType;
+
+  SpeedLimit = 0;
+  DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr);
+  for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) {
+    if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) {
+      continue;
+    }
+    DimmTpMatch = 0;
+    _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType;
+    for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) {
+      if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
+        DimmTpMatch++;
+      }
+    }
+    if (DimmTpMatch == FreqLimitPtr->Dimms) {
+      if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
+        SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V;
+        break;
+      } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) {
+        SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V;
+        break;
+      } else {
+        SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V;
+        break;
+      }
+    }
+  }
+
+  return SpeedLimit;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *    This function is the default function for getting POR speed limit. When a
+ *    package does not need to cap the speed, it should use this function to initialize
+ *    the corresponding function pointer.
+ *
+ *     @param[in,out]   *NBPtr           Pointer to MEM_NB_BLOCK
+ *
+ */
+VOID
+MemPGetPORFreqLimitDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
new file mode 100755
index 0000000000..f0ef01dde8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.c
@@ -0,0 +1,229 @@
+/**
+ * @file
+ *
+ * mt2.c
+ *
+ * Common Technology  functions for DDR2
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR2)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "AdvancedApi.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt2.h"
+#include "mtspd2.h"
+#include "mtot2.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+/* features */
+#include "mftds.h"
+#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function Constructs the technology block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemConstructTechBlock2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  TECHNOLOGY_TYPE *TechTypePtr;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT8 DimmSlots;
+
+  TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
+  if (TechTypePtr != NULL) {
+    // Ensure the platform override value is valid
+    ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
+    if (*TechTypePtr != DDR2_TECHNOLOGY) {
+      return FALSE;
+    }
+  }
+
+
+  TechPtr->NBPtr = NBPtr;
+  TechPtr->RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  TechPtr->NBPtr = NBPtr;
+  TechPtr->RefPtr = NBPtr->RefPtr;
+
+  TechPtr->SetDramMode = MemTSetDramMode2;
+  TechPtr->DimmPresence = MemTDIMMPresence2;
+  TechPtr->SpdCalcWidth = MemTSPDCalcWidth2;
+  TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2;
+  TechPtr->AutoCycTiming = MemTAutoCycTiming2;
+  TechPtr->SpdSetBanks = MemTSPDSetBanks2;
+  TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
+  TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2;
+  TechPtr->AdjustTwrwr = MemTAdjustTwrwr2;
+  TechPtr->AdjustTwrrd = MemTAdjustTwrrd2;
+  TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2;
+  TechPtr->GetLD = MemTGetLD2;
+  TechPtr->MaxFilterDly = 0;
+
+  //
+  // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
+  // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
+  //
+  //    DIMM Spd Buffer                          Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
+  //    (Number of dimms varies by platform)     (Array size is determined in AGESA.H) Dimm operations loop
+  //                                              on this array only)
+  //    2 DIMMS PER CHANNEL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
+  //                                                         DimmSpdPtr[2]------->NULL
+  //                                                         DimmSpdPtr[3]------->NULL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <---------+----DimmSpdPtr[1]
+  //                                                    |    DimmSpdPtr[2]------->NULL
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //    Socket N  Channel N Dimm 0    QR DIMM <-----+--------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <-----|---+----DimmSpdPtr[1]
+  //                                                +-- | ---DimmSpdPtr[2]
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //    3 DIMMS PER CHANNEL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
+  //                        Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
+  //                                                         DimmSpdPtr[3]------->NULL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <---------+----DimmSpdPtr[1]
+  //                        Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      ChannelPtr->TechType = DDR2_TECHNOLOGY;
+      ChannelPtr->MCTPtr = MCTPtr;
+      ChannelPtr->DCTPtr = DCTPtr;
+
+      DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                         MCTPtr->SocketId,
+                                         NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
+                                        );
+      //
+      // Initialize the SPD pointers for each Dimm
+      //
+      for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
+        ChannelPtr->DimmSpdPtr[i] = NULL;
+      }
+      for (i = 0 ; i < DimmSlots; i++) {
+        ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
+        if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
+          if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
+            if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) {
+              ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
+            }
+          }
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h
new file mode 100755
index 0000000000..eaccafdc30
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mt2.h
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * mt2.h
+ *
+ * Common Technology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR2)
+ * @e \$Revision: 5944 $ @e \$Date: 2008-04-28 15:07:20 -0500 (Mon, 28 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MT2_H_
+#define _MT2_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructTechBlock2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemTSetDramMode2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDIMMPresence2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDCalcWidth2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDGetTargetSpeed2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTAutoCycTiming2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDSetBanks2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTGetCSIntLvAddr2 (
+  IN       UINT8 BankEnc,
+  OUT      UINT8 *LowBit,
+  OUT      UINT8 *HiBit
+  );
+
+BOOLEAN
+MemTGetDimmSpdBuffer2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 **SpdBuffer,
+  IN       UINT8 Dimm
+  );
+
+#endif  /* _MT2_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
new file mode 100755
index 0000000000..c40f1ad8f5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * mtot2.c
+ *
+ * Technology Non-SPD Timings for DDR2
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR2)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mtot2.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function adjusts the Twrwr value for DDR2.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTAdjustTwrwr2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+
+  // For DDR2, 1 clock has encoded value of 0.
+  // Need to transfer clk value to encoded value.
+  if (DCTPtr->Timings.Twrwr >= 1) {
+    DCTPtr->Timings.Twrwr -= 1;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function adjusts the Twrrd value for DDR2.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTAdjustTwrrd2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+
+  // For DDR2, 1 clock has encoded value of 0.
+  // Need to transfer clk value to encoded value.
+  if (DCTPtr->Timings.Twrrd >= 1) {
+    DCTPtr->Timings.Twrrd -= 1;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets the LD value for DDR2
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  value of LD
+ */
+
+INT8
+MemTGetLD2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  INT8 LD;
+
+  // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
+  LD = 1;
+
+  return LD;
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h
new file mode 100755
index 0000000000..16909da202
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtot2.h
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * mtot2.h
+ *
+ * Technology Non-SPD timings for DDR2
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR2)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTOT2_H_
+#define _MTOT2_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+MemTAdjustTwrwr2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTAdjustTwrrd2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+INT8
+MemTGetLD2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTOT2_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c
new file mode 100755
index 0000000000..9e1a8927d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.c
@@ -0,0 +1,1112 @@
+/**
+ * @file
+ *
+ * mtspd2.c
+ *
+ * Technology SPD supporting functions for DDR2
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR2)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mu.h"
+#include "mt2.h"
+#include "mtspd2.h"
+#include "mftds.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR2_MTSPD2_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+UINT8
+STATIC
+MemTSPDGetTCL2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+STATIC
+MemTSysCapability2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 k,
+  IN       UINT16 j
+  );
+
+BOOLEAN
+STATIC
+MemTDimmSupports2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 k,
+  IN       UINT8 j,
+  IN       UINT8 i
+  );
+
+UINT8
+STATIC
+MemTGetTk2 (
+  IN       UINT8 k
+  );
+
+UINT8
+STATIC
+MemTGetBankAddr2 (
+  IN       UINT8 k
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DRAM mode
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that the DRAM mode is set to DDR2
+ */
+
+BOOLEAN
+MemTSetDramMode2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTDIMMPresence2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferPtr;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 Checksum;
+  UINT16 Value16;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  UINT8 ByteNum;
+  UINT8 Devwidth;
+  UINT8 Value8;
+  UINT8 MaxDimms;
+  UINT8 DimmSlots;
+  UINT16 DimmMask;
+  BOOLEAN SPDCtrl;
+
+  NBPtr = TechPtr->NBPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      ChannelPtr->DimmQrPresent = 0;
+
+      //  Get the maximum number of DIMMs
+      DimmSlots = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration,
+                                         MCTPtr->SocketId,
+                                         NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
+                                        );
+      MaxDimms = MAX_DIMMS_PER_CHANNEL;
+      for (i = 0; i < MaxDimms; i++) {
+        //  Bitmask representing dimm #i.
+        DimmMask = (UINT16)1 << i;
+
+        if ((ChannelPtr->DimmQrPresent & DimmMask) || (i < DimmSlots)) {
+          if (MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i)) {
+            MCTPtr->DimmPresent |= DimmMask;
+
+            //  Start by computing checksum for this SPD
+            Checksum = 0;
+            for (ByteNum = 0; ByteNum < SPD_CHECKSUM; ByteNum++) {
+              Checksum = Checksum + (UINT16) SpdBufferPtr[ByteNum];
+            }
+            //  Check for valid checksum value
+            AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
+
+            if (SpdBufferPtr[SPD_TYPE] == JED_DDR2_SDRAM) {
+              ChannelPtr->ChDimmValid |= DimmMask;
+              MCTPtr->DimmValid |= DimmMask;
+            } else {
+              // Current socket is set up to only support DDR2 dimms.
+              IDS_ERROR_TRAP;
+            }
+            if ((SpdBufferPtr[SPD_CHECKSUM] != (UINT8)Checksum) && !SPDCtrl) {
+              //
+              // if NV_SPDCHK_RESTRT is set to 0,
+              // cannot ignore faulty SPD checksum
+              //
+              //  Indicate checksum error
+              ChannelPtr->DimmSpdCse |= DimmMask;
+              PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+              SetMemError (AGESA_ERROR, MCTPtr);
+            }
+
+            //  Check module type information.
+            if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_REG_ADC_MSK) {
+              ChannelPtr->RegDimmPresent |= DimmMask;
+              MCTPtr->RegDimmPresent |= DimmMask;
+            }
+
+            if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_SODIMM) {
+              ChannelPtr->SODimmPresent |= DimmMask;
+            }
+
+            //  Check error correction type
+            if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ECC) {
+              MCTPtr->DimmEccPresent |= DimmMask;  //  Dimm has ECC
+            }
+            if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ADRC_PAR) {
+              MCTPtr->DimmParPresent |= DimmMask;  //  Dimm has parity
+            }
+
+            //  Get the Dimm width data
+            Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0xFE;
+            if (Devwidth == 4) {
+              ChannelPtr->Dimmx4Present |= DimmMask;   //  Dimm has parity
+            } else if (Devwidth == 8) {
+              ChannelPtr->Dimmx8Present |= DimmMask;   //  Dimm has parity
+            } else if (Devwidth == 16) {
+              ChannelPtr->Dimmx16Present |= DimmMask;  //  Dimm has parity
+            }
+
+            //  Determine the page size.
+            //       page_size = 2^COLBITS * Devwidth/8
+            //
+            Value16 = (((UINT16)1 << SpdBufferPtr[SPD_COL_SZ]) * Devwidth) / 8;
+            if (!(Value16 >> 11)) {
+              DCTPtr->Timings.DIMM1KPage |= DimmMask;
+            }
+
+            //  Check for 'analysis probe installed'
+            if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) {
+              MCTPtr->Status[SbDiagClks] = TRUE;
+            }
+
+            //  Determine the geometry of the DIMM module
+            if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) {
+              ChannelPtr->DimmPlPresent |= DimmMask;   //  Dimm is planar
+            }
+
+            //  specify the number of ranks
+            Value8 = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
+            if (Value8 > 2) {
+              if (ChannelPtr->DimmQrPresent == 0) {
+                // if any DIMMs are QR,
+                // we have to make two passes through DIMMs
+                //
+                MaxDimms = MaxDimms << 1;
+              }
+
+              if (i < DimmSlots) {
+                ChannelPtr->DimmQrPresent |= DimmMask;
+                ChannelPtr->DimmQrPresent |= (DimmMask << 2);
+              }
+              Value8 = 2;
+            } else if (Value8 == 2) {
+              ChannelPtr->DimmDrPresent |= DimmMask;   //  Dual rank dimms
+            }
+
+            //  Calculate bus loading per Channel
+            if (Devwidth == 16) {
+              Devwidth = 4;
+            } else if (Devwidth == 4) {
+              Devwidth = 16;
+            }
+            //  double Addr bus load value for dual rank DIMMs
+            if (Value8 == 2) {
+              Devwidth = Devwidth << 1;
+            }
+
+            ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
+            ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
+            ChannelPtr->Dimms++;
+
+            //  Now examine the dimm packaging dates
+            Value8 = SpdBufferPtr[SPD_MAN_DATE_YR];
+            if (Value8 < M_YEAR_06) {
+              ChannelPtr->DimmYr06 |= DimmMask;    //  Built before end of 2006
+              ChannelPtr->DimmWk2406 |= DimmMask;  //  Built before end of week 24,2006
+            } else if (Value8 == M_YEAR_06) {
+              ChannelPtr->DimmYr06 |= DimmMask;    //  Built before end of 2006
+              if (SpdBufferPtr[SPD_MAN_DATE_WK] <= M_WEEK_24) {
+                ChannelPtr->DimmWk2406 |= DimmMask;  //  Built before end of week 24,2006
+              }
+            }
+          } // if DIMM present
+        } // Quadrank
+      } // Dimm loop
+
+      if (Channel == 0) {
+        DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
+        DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
+        DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
+        DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
+        DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
+        DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
+        DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
+      }
+      if ((Channel != 1) || (Dct != 1)) {
+        MCTPtr->DimmPresent <<= 8;
+        MCTPtr->DimmValid <<= 8;
+        MCTPtr->RegDimmPresent <<= 8;
+        MCTPtr->DimmEccPresent <<= 8;
+        MCTPtr->DimmParPresent <<= 8;
+      }
+    } // Channel loop
+  } // DCT loop
+
+
+  //  If we have DIMMs, some further general characteristics checking
+  if (MCTPtr->DimmValid) {
+    //  If there are registered dimms, all the dimms must be registered
+    if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
+      //  All dimms registered
+      MCTPtr->Status[SbRegistered] = TRUE;
+    } else if (MCTPtr->RegDimmPresent) {
+      //  We have an illegal DIMM mismatch
+      PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_FATAL, MCTPtr);
+    }
+
+    //  check the ECC capability of the DIMMs
+    if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
+      MCTPtr->Status[SbEccDimms] = TRUE;  //  All dimms ECC capable
+    }
+
+    //  check the parity capability of the DIMMs
+    if (MCTPtr->DimmParPresent == MCTPtr->DimmValid) {
+      MCTPtr->Status[SbParDimms] = TRUE;  //  All dimms parity capable
+    }
+  } else {
+  }
+
+  NBPtr->SwitchDCT (NBPtr, 0);
+  NBPtr->SwitchChannel (NBPtr, 0);
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
+ *   set of DIMMs, and store into DIE_STRUCT(.Speed and .Casl).
+ *   See "Global relationship between index values and item values" for definition of
+ *   CAS latency index (j) and Frequency index (k).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDGetTargetSpeed2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  CONST UINT16 SpeedCvt[] = {
+    DDR400_FREQUENCY,
+    DDR533_FREQUENCY,
+    DDR667_FREQUENCY,
+    DDR800_FREQUENCY,
+    DDR1066_FREQUENCY
+  };
+  INT8 i;
+  INT8 j;
+  INT8 k;
+  INT8 Dct;
+  INT8 Channel;
+  UINT8 T1min;
+  UINT8 CL1min;
+  BOOLEAN IsSupported;
+  MEM_NB_BLOCK *NBPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = TechPtr->NBPtr->MCTPtr;
+
+  CL1min = 0xFF;
+  T1min = 0xFF;
+
+  // For DDR2, run SyncTargetSpeed first to get frequency limit into DCTPtr->Timings.Speed
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.TargetSpeed = 16;  // initialized with big number
+  }
+  NBPtr->SyncTargetSpeed (NBPtr);
+
+  // Find target frequency and Tcl
+  for (k = K_MAX; k >= K_MIN; k--) {
+    for (j = J_MIN; j <= J_MAX; j++) {
+      if (MemTSysCapability2 (TechPtr, k, j)) {
+        IsSupported = TRUE;
+        for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+          NBPtr->SwitchDCT (NBPtr, Dct);
+          for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+            NBPtr->SwitchChannel (NBPtr, Channel);
+            ChannelPtr = NBPtr->ChannelPtr;
+            for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
+              if (ChannelPtr->ChDimmValid & ((UINT8)1 << i)) {
+                if (!MemTDimmSupports2 (TechPtr, k, j, i)) {
+                  IsSupported = FALSE;
+                  Dct = NBPtr->DctCount;
+                  Channel = NBPtr->ChannelCount;
+                  break;
+                }
+              }
+            }
+          }
+        }
+
+        if (IsSupported) {
+          T1min = k;
+          CL1min = j;
+          //  Kill the loops...
+          k = K_MIN - 1;
+          j = J_MAX + 1;
+        }
+      }
+    }
+  }
+
+  if (T1min == 0xFF) {
+    //  Failsafe values, running in minimum mode
+    PutEventLog (AGESA_FATAL, MEM_ERROR_MISMATCH_DIMM_CLOCKS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    PutEventLog (AGESA_FATAL, MEM_ERROR_MINIMUM_MODE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, MCTPtr);
+
+    T1min = T_DEF;
+    CL1min = CL_DEF;
+  }
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    DCTPtr->Timings.TargetSpeed = SpeedCvt[T1min - 1];
+  }
+
+  // Ensure the target speed can be applied to all channels of the current node
+  NBPtr->SyncTargetSpeed (NBPtr);
+
+  // Set the start-up frequency
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    DCTPtr->Timings.Speed = DCTPtr->Timings.TargetSpeed;
+    DCTPtr->Timings.CasL = CL1min + 2;  // Convert to clocks
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
+ *   DIMM on Channel B), the overall DIMM population, and determine the width mode:
+ *   64-bit, 64-bit muxed, 128-bit.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDCalcWidth2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferAPtr;
+  UINT8 *SpdBufferBPtr;
+  MEM_NB_BLOCK *NBPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 i;
+  UINT16 DimmMask;
+  UINT8 UngangMode;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  UngangMode = UserOptions.CfgMemoryModeUnganged;
+  IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
+
+  //  Check symmetry of channel A and channel B dimms for 128-bit mode
+  //  capability.
+  //
+  AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
+  i = 0;
+  if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
+    for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
+      DimmMask = (UINT16)1 << i;
+      if (DCTPtr->Timings.DctDimmValid & DimmMask) {
+        NBPtr->SwitchDCT (NBPtr, 0);
+        MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferAPtr, i);
+        NBPtr->SwitchDCT (NBPtr, 1);
+        MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferBPtr, i);
+
+        if ((SpdBufferAPtr[SPD_ROW_SZ]&0x1F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x1F)) {
+          break;
+        }
+
+        if ((SpdBufferAPtr[SPD_COL_SZ]&0x1F) != (SpdBufferBPtr[SPD_COL_SZ]&0x1F)) {
+          break;
+        }
+
+        if (SpdBufferAPtr[SPD_BANK_SZ] != SpdBufferBPtr[SPD_BANK_SZ]) {
+          break;
+        }
+
+        if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
+          break;
+        }
+
+        if ((SpdBufferAPtr[SPD_DM_BANKS]&0x07) != (SpdBufferBPtr[SPD_DM_BANKS]&0x07)) {
+          break;
+        }
+      }
+    }
+  }
+  if (i < MAX_DIMMS_PER_CHANNEL) {
+    PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ALERT, MCTPtr);
+  } else if (!UngangMode) {
+    NBPtr->Ganged = TRUE;
+    MCTPtr->GangedMode = TRUE;
+    MCTPtr->Status[Sb128bitmode] = TRUE;
+    NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       Initialize DCT Timing registers as per DIMM SPD.
+ *       For primary timing (T, CL) use best case T value.
+ *       For secondary timing params., use most aggressive settings
+ *           of slowest DIMM.
+ *
+ *   Note:
+ *   There are three components to determining "maximum frequency": SPD component,
+ *   Bus load component, and "Preset" max frequency component.
+ *   The SPD component is a function of the min cycle time specified by each DIMM,
+ *   and the interaction of cycle times from all DIMMs in conjunction with CAS
+ *   latency.  The SPD component only applies when user timing mode is 'Auto'.
+ *
+ *   The Bus load component is a limiting factor determined by electrical
+ *   characteristics on the bus as a result of varying number of device loads.  The
+ *   Bus load component is specific to each platform but may also be a function of
+ *   other factors.  The bus load component only applies when user timing mode is
+ * ' Auto'.
+ *
+ *   The Preset component is subdivided into three items and is the minimum of
+ *   the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
+ *   memclock mode is 'Limit', OEM build specification of the maximum frequency.
+ *   The Preset component only applies when user timing mode is 'Auto'.
+
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTAutoCycTiming2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  CONST UINT8 SpdIndexes[] = {
+    SPD_TRCD,
+    SPD_TRP,
+    SPD_TRTP,
+    SPD_TRAS,
+    SPD_TRC,
+    SPD_TWR,
+    SPD_TRRD,
+    SPD_TWTR
+  };
+  CONST UINT8 Multiples[] = {10, 10, 10, 40, 40, 10, 10, 10};
+
+  CONST UINT8 Tab1KTfawTK[] = {8, 10, 13, 14, 0, 20};
+  CONST UINT8 Tab2KTfawTK[] = {10, 14, 17, 18, 0, 24};
+  CONST UINT8 TabDefTrcK[]  = {0x41, 0x3C, 0x3C, 0x3A, 0, 0x3A};
+
+  UINT8 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
+  UINT8 MiniMaxTrfc[4];
+
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 DimmMask;
+  UINT16 Value16;
+  UINT16 Tk40;
+  UINT8 i;
+  UINT8 j;
+  UINT8 Value8;
+  UINT8 Temp8;
+  UINT8  *StatTmgPtr;
+  UINT16 *StatDimmTmgPtr;
+  BOOLEAN   Is1066;
+  UINT8 *SpdBufferPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  // initialize mini-max arrays
+  for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
+    MiniMaxTmg[j] = 0;
+  }
+  for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
+    MiniMaxTrfc[j] = 0;
+  }
+
+  // ======================================================================
+  //  Get primary timing (CAS Latency and Cycle Time)
+  // ======================================================================
+  //  Get OEM specific load variant max
+  //
+
+  //======================================================================
+  // Gather all DIMM mini-max values for cycle timing data
+  //======================================================================
+  //
+  DimmMask = 1;
+  for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
+    if (DCTPtr->Timings.DctDimmValid & DimmMask) {
+      MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
+      for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
+        Value8 = SpdBufferPtr[SpdIndexes[j]];
+        if (SpdIndexes[j] == SPD_TRC) {
+          if (Value8 == 0 || Value8 == 0xFF) {
+            PutEventLog (AGESA_WARNING, MEM_WARNING_NO_SPDTRC_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, i, &NBPtr->MemPtr->StdHeader);
+            SetMemError (AGESA_WARNING, MCTPtr);
+            Value8 = TabDefTrcK[(DCTPtr->Timings.Speed / 66) - 3];
+          }
+        }
+        if (MiniMaxTmg[j] < Value8) {
+          MiniMaxTmg[j] = Value8;
+        }
+      }
+
+      //  get Trfc0 - Trfc3 values
+      Value8 = SpdBufferPtr[SPD_BANK_SZ];
+      Temp8 = (Value8 << 3) | (Value8 >> 5);
+      Value8 = SpdBufferPtr[SPD_DEV_WIDTH];
+      ASSERT (LibAmdBitScanReverse ((UINT32)Value8) <= 4);
+      Temp8 >>= 4 - LibAmdBitScanReverse ((UINT32)Value8);
+      Value8 = LibAmdBitScanReverse ((UINT32)Temp8);
+      if (MiniMaxTrfc[i] < Value8) {
+        MiniMaxTrfc[i] = Value8;
+      }
+    }
+    DimmMask <<= 1;
+  }
+
+  // ======================================================================
+  //  Convert  DRAM CycleTiming values and store into DCT structure
+  // ======================================================================
+  //
+  Tk40 = 40000 / DCTPtr->Timings.Speed;
+  if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
+    Is1066 = TRUE;
+  } else {
+    Is1066 = FALSE;
+  }
+  //   Notes:
+  //   1. All secondary time values given in SPDs are in binary with UINTs of ns.
+  //   2. Some time values are scaled by four, in order to have least count of 0.25 ns
+  //      (more accuracy).  JEDEC SPD spec. shows which ones are x1 and x4.
+  //   3. Internally to this SW, cycle time, Tk, is scaled by 10 to affect a
+  //      least count of 0.1 ns (more accuracy).
+  //   4. SPD values not scaled are multiplied by 10 and then divided by 10T to find
+  //      equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
+  //   5. SPD values that are prescaled by 4 are multiplied by 10 and then divided by 40T to find
+  //      equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
+  //
+  StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
+  StatTmgPtr = &DCTPtr->Timings.Trcd;
+  for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
+    Value16 = (UINT16)MiniMaxTmg[j] * Multiples[j];
+    StatDimmTmgPtr[j] = Value16;
+
+    MiniMaxTmg[j] = (UINT8) ((Value16 + Tk40 - 1) / Tk40);
+    if (SpdIndexes[j] == SPD_TRTP) {
+      MiniMaxTmg[j] = (DCTPtr->Timings.Speed <= DDR533_FREQUENCY) ? 2 : 3;   // based on BL of 32 bytes
+    }
+
+    StatTmgPtr[j] = MiniMaxTmg[j];
+  }
+  DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
+  DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
+  DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
+  DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
+
+  DCTPtr->Timings.CasL = MemTSPDGetTCL2 (TechPtr);
+
+  if (DCTPtr->Timings.DIMM1KPage) {
+    DCTPtr->Timings.Tfaw = Tab1KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
+  } else {
+    DCTPtr->Timings.Tfaw = Tab2KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
+  }
+  if (Is1066) {
+    DCTPtr->Timings.Tfaw >>= 1;
+  }
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  NBPtr->ProgramCycTimings (NBPtr);
+
+  MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the bank addressing, program Mask values and build a chip-select population map.
+ *   This routine programs PCI 0:24N:2x80 config register.
+ *   This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDSetBanks2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferPtr;
+  UINT8 i;
+  UINT8 ChipSel;
+  UINT8 DimmID;
+  UINT8 Value8;
+  UINT8 Rows;
+  UINT8 Cols;
+  UINT8 Ranks;
+  UINT8 Banks;
+  UINT32 BankAddrReg;
+  UINT32 CsMask;
+  UINT16 CSSpdCSE;
+  UINT16 CSExclude;
+  UINT16 DimmQRDR;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  BankAddrReg = 0;
+  CSSpdCSE = 0;
+  CSExclude = 0;
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    DimmID = ChipSel >> 1;
+
+    DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
+    if (DCTPtr->Timings.DimmSpdCse & (UINT16) 1 << DimmID) {
+      CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
+    }
+    if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
+      CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
+    }
+
+    if (DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) {
+      MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, DimmID);
+
+      //  Get the basic data
+      Rows = SpdBufferPtr[SPD_ROW_SZ] & 0x1F;
+      Cols = SpdBufferPtr[SPD_COL_SZ] & 0x1F;
+      Banks = SpdBufferPtr[SPD_L_BANKS];
+      Ranks = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
+
+      //  Configure the bank encoding
+      Value8 = (Cols - 9) << 3;
+      Value8 |= (Banks == 8) ? 4 : 0;
+      Value8 |= (Rows - 13);
+
+      for (i = 0; i < 12; i++) {
+        if (Value8 == MemTGetBankAddr2 (i)) {
+          break;
+        }
+      }
+
+      if (i < 12) {
+        BankAddrReg |= ((UINT32)i << (ChipSel << 1));
+
+        // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
+        // or 2pow(rows+cols+banks-5)-1
+        //
+        Value8 = Rows + Cols;
+        Value8 -= (Banks == 8) ? 2:3;
+        if (MCTPtr->Status[Sb128bitmode]) {
+          Value8++;
+        }
+        CsMask = ((UINT32)1 << Value8) - 1;
+        DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
+
+        if (Ranks >= 2) {
+          DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
+        }
+
+        //  Update the DRAM CS Mask for this chipselect
+        NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0));
+      }
+    }
+  }
+  // For ranks that need to be excluded, the loading of this rank should be considered
+  // in timing, so need to set CsPresent before setting CsTestFail
+  if ((CSSpdCSE != 0) || (CSExclude != 0)) {
+    NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader);
+  }
+
+  //  If there are no chip selects, we have an error situation.
+  if (DCTPtr->Timings.CsPresent == 0) {
+    PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, MCTPtr);
+  }
+
+  NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the low bit that will be swapped to enable CS interleaving
+ *
+ *     @param[in]   BankEnc - AddrMap Bank encoding from F2x80
+ *     @param[in]   *LowBit - pointer to low bit
+ *     @param[in]   *HiBit  - pointer hight bit
+ *
+ */
+
+VOID
+MemTGetCSIntLvAddr2 (
+  IN       UINT8 BankEnc,
+     OUT   UINT8 *LowBit,
+     OUT   UINT8 *HiBit
+  )
+{
+  CONST UINT8 ArrCodesLo[] = {6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 8, 9};
+  CONST UINT8 ArrCodesHi[] = {19, 20, 21, 21, 21, 22, 22, 23, 23, 24, 24, 25};
+  ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
+  ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
+  //  return ArrCodes[BankEnc];
+  *LowBit = ArrCodesLo[BankEnc];
+  *HiBit = ArrCodesHi[BankEnc];
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function returns the CAS latency of the current frequency.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  CAS Latency
+ */
+UINT8
+STATIC
+MemTSPDGetTCL2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return TechPtr->NBPtr->DCTPtr->Timings.CasL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *               Get max frequency from OEM platform definition, from
+ *               any user override (limiting) of max frequency, and
+ *               from any Si Revision Specific information.  Return
+ *               the least of these three in DIE_STRUCT.PresetmaxFreq.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]   k -  Frequency index
+ *     @param[in]   j - CAS Latency index
+ *
+ *     @return  TRUE  - (k << 8) | j
+ *     @return  FALSE - 0
+ */
+
+BOOLEAN
+STATIC
+MemTSysCapability2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 k,
+  IN       UINT16 j
+  )
+{
+  if ((k > TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed) || (j > J_MAX)) {
+    return FALSE;
+  }
+
+  return TRUE;    //(k << 8) | j;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Determine whether dimm(b,i) supports CL(j) and F(k)
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]   k -  Frequency index
+ *     @param[in]   j - CAS Latency index
+ *     @param[in]   i - DIMM number
+ *
+ *     @return  TRUE  - DIMM supports
+ *     @return  FALSE - DIMM does not support
+ */
+
+BOOLEAN
+STATIC
+MemTDimmSupports2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 k,
+  IN       UINT8 j,
+  IN       UINT8 i
+  )
+{
+  CONST UINT8 SpdBytesForCL[3] = { 9, 23, 25};   // SPD bytes for CL X, CL X-.5, and CL X-1
+  UINT8 CLj;
+  UINT8 CLi;
+  UINT8 T1;
+  UINT8 T2;
+  UINT8 Tk;
+  UINT8 *SpdBufferPtr;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
+  CLj = (UINT8) 1 << (j + 2);
+  CLi = SpdBufferPtr[SPD_CAS_LAT];
+
+  if (CLj & CLi) {
+    //  If this dimm supports the desired CAS latency...
+    //  Determine the SPD location of the dimm speed UINT8 appropriate
+    //  to the CAS latency indicated by Table_CL2_j.
+    //
+    T1 = LibAmdBitScanReverse ((UINT32)CLj);
+    T2 = LibAmdBitScanReverse ((UINT32)CLi);
+    ASSERT ((T2 - T1) < 3);
+    CLi = SpdBufferPtr[SpdBytesForCL[(T2 - T1)]];
+    Tk = MemTGetTk2 (k);
+    if (CLi == 0) {
+      PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CYC_TIME, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
+    } else if (Tk >= CLi) {
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the cycle time
+ *
+ *     @param[in]   k - CAS Latency index
+ *
+ *     @return      Tk as specified by JEDEC SPD byte 9.
+ */
+
+UINT8
+STATIC
+MemTGetTk2 (
+  IN       UINT8 k
+  )
+{
+  CONST UINT8 TableTK[] = {0x00, 0x50, 0x3D, 0x30, 0x25, 0x18};
+  ASSERT (k < GET_SIZE_OF (TableTK));
+  return TableTK[k];
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function returns the encoded value of bank address.
+ *
+ *     @param[in]  k  value
+ *
+ *     @return      RRRBCC, where CC is the number of Columns minus 9,
+ *                  RRR is the number of Rows minus 12, and B is the number of banks
+ *                  minus 3.
+ */
+
+UINT8
+STATIC
+MemTGetBankAddr2 (
+  IN       UINT8 k
+  )
+{
+  CONST UINT8 TabBankAddr[] = {
+    0x00, 0x08, 0x09, 0x10, 0x0C, 0x0D,
+    0x11, 0x0E, 0x15, 0x16, 0x0F, 0x17
+  };
+  ASSERT (k < GET_SIZE_OF (TabBankAddr));
+  return TabBankAddr[k];
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function returns a pointer to the SPD Buffer of a specific dimm on
+ *    the current channel.
+ *
+ *     @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
+ *     @param[in] Dimm - Dimm number
+ *
+ *
+ *     @return BOOLEAN - Value of DimmPresent
+ *                       TRUE = Dimm is present, pointer is valid
+ *                       FALSE = Dimm is not present, pointer has not been modified.
+ */
+
+BOOLEAN
+MemTGetDimmSpdBuffer2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 **SpdBuffer,
+  IN       UINT8 Dimm
+  )
+{
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SPDPtr;
+  BOOLEAN DimmPresent;
+
+  DimmPresent = FALSE;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
+  SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
+
+
+  if (SPDPtr != NULL) {
+    DimmPresent = SPDPtr->DimmPresent;
+    if (DimmPresent) {
+      *SpdBuffer = SPDPtr->Data;
+    }
+  }
+  return DimmPresent;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h
new file mode 100755
index 0000000000..5ed8c32bc8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR2/mtspd2.h
@@ -0,0 +1,182 @@
+/**
+ * @file
+ *
+ * mtspd2.h
+ *
+ * Technology SPD support for DDR2
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR2)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTSPD2_H_
+#define _MTSPD2_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*===============================================================================
+ *   Jedec DDR II
+ *===============================================================================
+ */
+#define SPD_TYPE         2              /* SPD byte read location */
+#define JED_DDR_SDRAM     7              /* Jedec defined bit field */
+#define JED_DDR2_SDRAM    8              /* Jedec defined bit field */
+
+#define SPD_DIMM_TYPE    20
+#define SPD_ATTRIB       21
+#define JED_DIF_CK_MSK   0x20            /* Differential Clock Input */
+#define JED_REG_ADC_MSK  0x11            /* Registered Address/Control */
+#define JED_PROBE_MSK    0x40            /* Analysis Probe installed */
+#define JED_SODIMM       0x04            /* SO-DIMM */
+#define SPD_DEV_ATTRIB   22
+#define SPD_EDC_TYPE     11
+#define JED_ECC          2
+#define JED_ADRC_PAR     4
+#define SPD_ROW_SZ       3
+#define SPD_COL_SZ       4
+#define SPD_L_BANKS      17              /* number of [logical] banks on each device */
+#define SPD_DM_BANKS     5               /* number of physical banks on dimm */
+#define SP_DPL_BIT       4               /*  Dram package bit */
+#define SPD_BANK_SZ      31              /* capacity of physical bank */
+#define SPD_DEV_WIDTH    13
+#define SPD_CAS_LAT      18
+#define SPD_TRP         27
+#define SPD_TRRD        28
+#define SPD_TRCD        29
+#define SPD_TRAS        30
+#define SPD_TWR         36
+#define SPD_TWTR        37
+#define SPD_TRTP        38
+#define SPD_TRC         41
+#define SPD_TRFC        42
+#define SPD_CHECKSUM    63
+#define SPD_MAN_DATE_YR   93             /* Module Manufacturing Year (BCD) */
+
+#define SPD_MAN_DATE_WK   94             /* Module Manufacturing Week (BCD) */
+
+/*-----------------------------
+ * Jedec DDR II related equates
+ *-----------------------------
+ */
+#define M_YEAR_06         0x06           /*  Manufacturing Year BCD encoding of 2006 - 06d */
+#define M_WEEK_24         0x24           /*  Manufacturing Week BCD encoding of June - 24d */
+
+#define J_MIN           0              /* j loop constraint. 1=CL 2.0 T */
+#define J_MAX           5              /* j loop constraint. 5=CL 7.0 T */
+#define K_MIN           1              /* k loop constraint. 1=200 MHz */
+#define K_MAX           5              /* k loop constraint. 5=533 MHz */
+#define CL_DEF          2              /* Default value for failsafe operation. 2=CL 4.0 T */
+#define T_DEF           1              /* Default value for failsafe operation. 1=5ns (cycle time) */
+
+
+#define BIAS_TCL_T       1
+#define BIAS_TRP_T       3              /* bias to convert bus clocks to bit field value */
+#define BIAS_TRRD_T      2
+#define BIAS_TRCD_T      3
+#define BIAS_TRAS_T      3
+#define BIAS_TRC_T       11
+#define BIAS_TRTP_T      1
+#define BIAS_TWR_T       3
+#define BIAS_TWTR_T      0
+#define BIAS_TFAW_T      7
+
+#define MIN_TRP_T        3                   /* min programmable value in busclocks */
+#define MAX_TRP_T        6                   /* max programmable value in busclocks */
+#define MIN_TRRD_T       2
+#define MAX_TRRD_T       5
+#define MIN_TRCD_T       3
+#define MAX_TRCD_T       6
+#define MIN_TRAS_T       5
+#define MAX_TRAS_T       18
+#define MIN_TRC_T        11
+#define MAX_TRC_T        26
+#define MIN_TRTP_T       2
+#define MAX_TRTP_T       4
+#define MIN_TWR_T        3
+#define MAX_TWR_T        6
+#define MIN_TWTR_T       1
+#define MAX_TWTR_T       3
+
+/* DDR2-1066 support */
+#define BIAS_TRCD_T_1066      5
+#define BIAS_TRAS_T_1066      15
+#define BIAS_TRRD_T_1066      4
+#define BIAS_TWR_T_1066       4
+#define BIAS_TRP_T_1066       5
+#define BIAS_TWTR_T_1066      4
+
+#define MIN_TRCD_T_1066       5
+#define MAX_TRCD_T_1066       12
+#define MIN_TRAS_T_1066       15
+#define MAX_TRAS_T_1066       30
+#define MIN_TRC_T_1066        11
+#define MAX_TRC_T_1066        42
+#define MIN_TRRD_T_1066       4
+#define MAX_TRRD_T_1066       7
+#define MIN_TWR_T_1066        5
+#define MAX_TWR_T_1066        8
+#define MIN_TRP_T_1066        5
+#define MAX_TRP_T_1066        12
+#define MIN_TWTR_T_1066       4
+#define MAX_TWTR_T_1066       7
+
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#endif  /* _MTSPD2_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
new file mode 100755
index 0000000000..05962a61af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.c
@@ -0,0 +1,223 @@
+/**
+ * @file
+ *
+ * mt3.c
+ *
+ * Common Technology  functions for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtspd3.h"
+#include "mtot3.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Filecode.h"
+/* features */
+#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function Constructs the technology block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemConstructTechBlock3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  TECHNOLOGY_TYPE *TechTypePtr;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT8 DimmSlots;
+
+
+  TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
+  if (TechTypePtr != NULL) {
+    // Ensure the platform override value is valid
+    ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
+    if (*TechTypePtr != DDR3_TECHNOLOGY) {
+      return FALSE;
+    }
+  }
+
+  TechPtr->NBPtr = NBPtr;
+  TechPtr->RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  TechPtr->SendAllMRCmds = MemTSendAllMRCmds3;
+  TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3;
+  TechPtr->SetDramMode = MemTSetDramMode3;
+  TechPtr->DimmPresence = MemTDIMMPresence3;
+  TechPtr->SpdCalcWidth = MemTSPDCalcWidth3;
+  TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3;
+  TechPtr->AutoCycTiming = MemTAutoCycTiming3;
+  TechPtr->SpdSetBanks = MemTSPDSetBanks3;
+  TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
+  TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3;
+  TechPtr->AdjustTwrwr = MemTAdjustTwrwr3;
+  TechPtr->AdjustTwrrd = MemTAdjustTwrrd3;
+  TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3;
+  TechPtr->GetLD = MemTGetLD3;
+  TechPtr->MaxFilterDly = 0;
+
+  //
+  // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
+  // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
+  //
+  //    DIMM Spd Buffer                          Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
+  //    (Number of dimms varies by platform)     (Array size is determined in AGESA.H) Dimm operations loop
+  //                                              on this array only)
+  //    2 DIMMS PER CHANNEL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
+  //                                                         DimmSpdPtr[2]------->NULL
+  //                                                         DimmSpdPtr[3]------->NULL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <---------+----DimmSpdPtr[1]
+  //                                                    |    DimmSpdPtr[2]------->NULL
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //    Socket N  Channel N Dimm 0    QR DIMM <-----+--------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <-----|---+----DimmSpdPtr[1]
+  //                                                +-- | ---DimmSpdPtr[2]
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //    3 DIMMS PER CHANNEL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
+  //                        Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
+  //                                                         DimmSpdPtr[3]------->NULL
+  //
+  //    Socket N  Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
+  //                        Dimm 1    QR DIMM <---------+----DimmSpdPtr[1]
+  //                        Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
+  //                                                    +----DimmSpdPtr[3]
+  //
+  //
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      ChannelPtr->TechType = DDR3_TECHNOLOGY;
+      ChannelPtr->MCTPtr = MCTPtr;
+      ChannelPtr->DCTPtr = DCTPtr;
+
+      DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                         MCTPtr->SocketId,
+                                         NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
+                                        );
+      //
+      // Initialize the SPD pointers for each Dimm
+      //
+      for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
+        ChannelPtr->DimmSpdPtr[i] = NULL;
+      }
+      for (i = 0 ; i < DimmSlots; i++) {
+        ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
+        if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
+          if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
+            if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
+              ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
+            }
+          }
+        }
+      }
+    }
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
new file mode 100755
index 0000000000..506e380b04
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mt3.h
@@ -0,0 +1,135 @@
+/**
+ * @file
+ *
+ * mt3.h
+ *
+ * Common Technology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 6608 $ @e \$Date: 2008-07-02 17:00:59 -0500 (Wed, 02 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MT3_H_
+#define _MT3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemConstructTechBlock3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+BOOLEAN
+MemTSetDramMode3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDIMMPresence3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDCalcWidth3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDGetTargetSpeed3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTAutoCycTiming3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSPDSetBanks3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTGetCSIntLvAddr3 (
+  IN       UINT8 BankEnc,
+  OUT      UINT8 *LowBit,
+  OUT      UINT8 *HiBit
+  );
+
+VOID
+MemTSendAllMRCmds3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel
+  );
+
+VOID
+FreqChgCtrlWrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+
+BOOLEAN
+MemTGetDimmSpdBuffer3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 **SpdBuffer,
+  IN       UINT8 Dimm
+  );
+
+#endif  /* _MT3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
new file mode 100755
index 0000000000..248334f227
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.c
@@ -0,0 +1,167 @@
+/**
+ * @file
+ *
+ * mtot3.c
+ *
+ * Technology Non-SPD Timings for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mtot3.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function adjusts the Twrwr value for DDR3.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTAdjustTwrwr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+
+  // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved.
+  if (DCTPtr->Timings.Twrwr < 2) {
+    DCTPtr->Timings.Twrwr = 2;
+  } else if (DCTPtr->Timings.Twrwr > 10) {
+    DCTPtr->Timings.Twrwr = 10;
+  }
+  IDS_HDT_CONSOLE ("@\tTwrwr: %d for Socket %d, Die %d, Channel %d\n", DCTPtr->Timings.Twrwr, TechPtr->NBPtr->MCTPtr->SocketId, \
+    TechPtr->NBPtr->Node, TechPtr->NBPtr->Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function adjusts the Twrrd value for DDR3.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTAdjustTwrrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  DCT_STRUCT *DCTPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+
+  // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved.
+  if (DCTPtr->Timings.Twrrd < 2) {
+    DCTPtr->Timings.Twrrd = 2;
+  } else if (DCTPtr->Timings.Twrrd > 10) {
+    DCTPtr->Timings.Twrrd = 10;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets the LD value for DDR3.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  Value of LD
+ */
+
+INT8
+MemTGetLD3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  INT8 LD;
+  MEM_NB_BLOCK *NBPtr;
+  NBPtr = TechPtr->NBPtr;
+  //
+  // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
+  // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
+  // value.
+  //
+  LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5);
+
+  return LD;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
new file mode 100755
index 0000000000..577c06f059
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtot3.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ *
+ * mtot3.h
+ *
+ * Technology Non-SPD timings for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTOT3_H_
+#define _MTOT3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+VOID
+MemTAdjustTwrwr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTAdjustTwrrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+INT8
+MemTGetLD3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTOT3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
new file mode 100755
index 0000000000..77ddfb4f43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -0,0 +1,307 @@
+/**
+ * @file
+ *
+ * mtrci3.c
+ *
+ * Technology Control word initialization for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtrci3.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTSendCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CmdNum,
+  IN       UINT8 Value
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends control words
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTDramControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT8 i;
+  UINT8 RawCard;
+  UINT8 Data;
+  UINT16 CsPresent;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+  MemUWait10ns (800, MemPtr);   // wait 8us TACT must be changed to optimize to 8 MEM CLKs
+
+  // Set EnDramInit to start DRAM initialization
+
+  MemUWait10ns (600, MemPtr);   // wait 6us for PLL LOCK
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    //
+    // If chip select present
+    //
+    if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+
+      // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
+      NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
+
+      RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1];
+
+      for (i = 0; i <= 15; i++) {
+        // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
+        MemUWait10ns (800, MemPtr);
+        if ((i != 6) && (i != 7)) {
+          Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel);
+          MemTSendCtlWord3 (TechPtr, i, Data);
+        }
+      }
+    }
+  }
+  MemUWait10ns (600, MemPtr);   // wait 6us for TSTAB
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the ControlRC value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     CtrlWordNum  -  control Word number.
+ *     @param[in]     RawCard  -  Raw Card
+ *     @param[in]     ChipSel  - Target Chip Select
+ *     @return  Control Word value
+ */
+
+UINT8
+MemTGetCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CtrlWordNum,
+  IN       UINT8 RawCard,
+  IN       UINT8 ChipSel
+  )
+{
+  UINT8  Data;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  DCTPtr = TechPtr->NBPtr->DCTPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Data = 0;  //Default value for all control words is 0
+  switch (CtrlWordNum) {
+  case 0:
+    Data = 0x02;  // DA4=1
+    break;
+  case 1:
+    if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) {
+      Data = 0x0C;  // if single rank, set DBA1 and DBA0
+    }
+    break;
+  case 2:
+    Data = ChannelPtr->CtrlWrd02[ChipSel >> 1];
+    break;
+  case 3:
+    Data = ChannelPtr->CtrlWrd03[ChipSel >> 1];
+    break;
+  case 4:
+    Data = ChannelPtr->CtrlWrd04[ChipSel >> 1];
+    break;
+  case 5:
+    Data = ChannelPtr->CtrlWrd05[ChipSel >> 1];
+    break;
+  case 8:
+    Data = ChannelPtr->CtrlWrd08[ChipSel >> 1];
+    break;
+  case 9:
+    Data = 0x0D;
+    break;
+  default:;
+  }
+
+  return (Data & 0x0F);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends control word command
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     CmdNum  -  control number.
+ *     @param[in]     Value  -  value to send
+ *
+ */
+
+VOID
+STATIC
+MemTSendCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CmdNum,
+  IN       UINT8 Value
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // 1. Program MrsBank and MrsAddress.
+  //    n = [BA2, A2, A1, A0].
+  //    data = [BA1, BA0, A4, A3].
+  //    Set all other bits in MrsAddress to zero.
+  //
+  NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2));
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7));
+  IDS_HDT_CONSOLE ("\t\tCS%lx RC%02lx %04lx\n",
+              (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 15) & 8) |
+              (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) & 7),
+              ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 14) & 0xC) |
+              ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 3) & 3));
+
+  // 2.Set SendCtrlWord=1
+  NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1);
+  // 3.Wait for BFSendCtrlWord=0
+  NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends specific control words commands before frequency change for certain DRAM buffers.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+FreqChgCtrlWrd3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT16 Speed;
+  UINT16 CsPresent;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
+
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    //
+    // If chip select present.
+    //
+    if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
+
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+      // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
+      NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
+
+      //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
+      MemUWait10ns (800, MemPtr);
+      if (Speed == DDR1066_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 1);
+      } else if (Speed == DDR1333_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 2);
+      } else if (Speed == DDR1600_FREQUENCY) {
+        MemTSendCtlWord3 (TechPtr, 0x0A, 3);
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
new file mode 100755
index 0000000000..96eec7e37a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtrci3.h
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * mtrci3.h
+ *
+ * Technology control word init for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTRCI3_H_
+#define _MTRCI3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+UINT8
+MemTGetCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CtrlWordNum,
+  IN       UINT8 RawCard,
+  IN       UINT8 ChipSel
+  );
+
+VOID
+MemTDramControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTRCI3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
new file mode 100755
index 0000000000..e789fcf065
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.c
@@ -0,0 +1,521 @@
+/**
+ * @file
+ *
+ * mtsdi3.c
+ *
+ * Technology Software DRAM Init for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mtsdi3.h"
+#include "mtrci3.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTEMRS33 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+STATIC
+MemTMRS3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates software DRAM init for  both DCTs
+ *   at the same time.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemTDramInitSw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 ChipSel;
+  UINT32 Dummy;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  IDS_HDT_CONSOLE ("!\nStart Dram Init\n");
+  // 3.Program F2x[1,0]7C[EnDramInit]=1
+  IDS_HDT_CONSOLE ("\tEnDramInit = 1 for both DCTs\n");
+  NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1);
+  NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
+
+  // 4.wait 200us
+  MemUWait10ns (20000, MemPtr);
+
+  // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1.
+  NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1);
+
+  // 6.wait 500us
+  MemUWait10ns (50000, MemPtr);
+
+  // Do Phy Fence training before sending MRS commands
+  if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) {
+    AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+        NBPtr->PhyFenceTraining (NBPtr);
+      }
+    }
+  }
+
+  // 7.NOP or deselect & take CKE high
+  NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1);
+
+  // 8.wait 360ns
+  MemUWait10ns (36, MemPtr);
+
+  // The following steps are performed once for each channel with unbuffered DIMMs
+  // and once for each chip select on registered DIMMs:
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+      // The following steps are performed with registered DIMMs only and
+      // must be done for each chip select pair:
+      if (MCTPtr->Status[SbRegistered]) {
+        MemTDramControlRegInit3 (TechPtr);
+      }
+
+      for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+        if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
+          IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
+          // if chip select present
+          MemTSendAllMRCmds3 (TechPtr, ChipSel);
+          // NOTE: wait 512 clocks for DLL-relock
+          MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+          if (!MCTPtr->Status[SbRegistered]) {
+            break;
+          }
+        }
+      }
+
+      // 17.Send two ZQCL commands (to even then odd chip select)
+      NBPtr->sendZQCmd (NBPtr);
+      NBPtr->sendZQCmd (NBPtr);
+    }
+  }
+
+  // 18.Program F2x[1,0]7C[EnDramInit]=0
+  NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0);
+  NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
+  //
+  // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit
+  //
+  if (!MCTPtr->Status[SbRegistered]) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+        for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+          if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
+            IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
+            // if chip select present
+            MemTSendAllMRCmds3 (TechPtr, ChipSel);
+            // NOTE: wait 512 clocks for DLL-relock
+            MemUWait10ns (50000, NBPtr->MemPtr);  // wait 500us
+          }
+        }
+      }
+    }
+  }
+
+
+  IDS_HDT_CONSOLE ("End Dram Init\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS1 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]        Wl - Indicates if WL mode should be enabled
+ *     @param[in]        TargetDIMM - DIMM target for WL
+ */
+
+VOID
+MemTEMRS13 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       BOOLEAN Wl,
+  IN       UINT8 TargetDIMM
+  )
+{
+  UINT16 MrsAddress;
+  UINT8 MaxDimmPerCH;
+  UINT8 ChipSel;
+  UINT8  Value8;
+
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
+                                        NBPtr->MCTPtr->SocketId,
+                                        NBPtr->ChannelPtr->ChannelID);
+  ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
+
+  // BA2=0,BA1=0,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
+
+  MrsAddress = 0;
+
+  // program MrsAddress[5,1]=output driver impedance control (DIC):
+  // based on F2x[1,0]84[DrvImpCtrl]
+  Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl);
+  if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 5);
+  }
+  if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 1);
+  }
+
+  // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
+  // Different CS may have different RTT.
+  //
+  if (NBPtr->MCTPtr->Status[SbRegistered]) {
+    //
+    // Registered Dimms
+    //
+    if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) {
+      Value8 = NBPtr->PsPtr->QR_DramTerm;
+    } else {
+      Value8 = NBPtr->PsPtr->DramTerm;
+    }
+  } else {
+    //
+    // Unbuffered Dimms
+    //
+    Value8 = NBPtr->PsPtr->DramTerm;
+  }
+  //
+  // If Write Leveling this DIMM
+  //
+  if (Wl) {
+    if ((ChipSel >> 1) == TargetDIMM) {
+      // Program MrsAddress[7] = 1 for Write leveling enable
+      MrsAddress |= ((UINT16) 1 << 7);
+      if (ChipSel & 1) {
+        // Output buffer disabled, MrsAddress[7] (Qoff = 1)
+        MrsAddress |= ((UINT16) 1 << 12);
+      }
+      //  Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms
+      if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) {
+        Value8 = NBPtr->PsPtr->DynamicDramTerm;
+      }
+    }
+  }
+  //
+  // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs.
+  //
+  // All odd CS for 4 Dimm Systems
+  if (MaxDimmPerCH == 4) {
+    if (ChipSel & 0x01) {
+      Value8 = 0;
+    }
+  // CS 1 and 5 for 3 Dimm configs
+  } else if (MaxDimmPerCH == 3) {
+    if ((ChipSel == 1) || (ChipSel == 5)) {
+      Value8 = 0;
+    }
+  }
+  // All odd CS of any QR Dimms
+  if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
+    if (ChipSel & 0x01) {
+      Value8 = 0;
+    }
+  }
+  if ((Value8 & ((UINT8) 1 << 2)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 9);
+  }
+  if ((Value8 & ((UINT8) 1 << 1)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 6);
+  }
+  if ((Value8 & ((UINT8) 1 << 0)) != 0) {
+    MrsAddress |= ((UINT16) 1 << 2);
+  }
+
+  // program MrsAddress[12]=output disable (QOFF):
+  // based on F2x[1,0]84[Qoff]
+  if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) {
+    MrsAddress |= ((UINT16) 1 << 12);
+  }
+
+  // program MrsAddress[11]=TDQS:
+  // based on F2x[1,0]94[RDqsEn]
+  if (NBPtr->GetBitField (NBPtr, BFRDqsEn) != 0) {
+    MrsAddress |= ((UINT16) 1 << 11);
+  }
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS2 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTEMRS23 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT32 MrsAddress;
+  UINT8 DramTermDyn;
+  UINT8 MaxDimmPerCH;
+  UINT8 ChipSel;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID );
+  ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
+
+  // BA2=0,BA1=1,BA0=0
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
+
+  // program MrsAddress[5:3]=CAS write latency (CWL):
+  // based on F2x[1,0]84[Tcwl]
+  MrsAddress = NBPtr->GetBitField (NBPtr, BFTcwl) << 3;
+
+  // program MrsAddress[6]=auto self refresh method (ASR):
+  // based on F2x[1,0]84[ASR]
+  // program MrsAddress[7]=self refresh temperature range (SRT):
+  // based on F2x[1,0]84[ASR and SRT]
+  MrsAddress |= NBPtr->GetBitField (NBPtr, BFASR) << 6;
+  MrsAddress |= NBPtr->GetBitField (NBPtr, BFSRT) << 7;
+
+  // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
+  // based on F2x[1,0]84[DramTermDyn]
+  DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn);
+  // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch
+  if (!(NBPtr->MCTPtr->Status[SbRegistered])) {
+    if (MaxDimmPerCH == 3) {
+      if (NBPtr->ChannelPtr->Dimms == 1) {
+        if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
+          DramTermDyn = 1;
+        }
+      }
+    }
+  }
+  MrsAddress |= (UINT16) DramTermDyn << 9;
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS3 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemTEMRS33 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=1,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
+
+  // program MrsAddress[1:0]=multi purpose register address location
+  // (MPR Location):based on F2x[1,0]84[MprLoc]
+  // program MrsAddress[2]=multi purpose register
+  // (MPR):based on F2x[1,0]84[MprEn]
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This sets MRS value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemTMRS3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT32 MrsAddress;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=0,BA0=0
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
+
+  // program MrsAddress[1:0]=burst length and control method
+  // (BL):based on F2x[1,0]84[BurstCtrl]
+  MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl);
+
+  // program MrsAddress[3]=1 (BT):interleaved
+  MrsAddress |= (UINT16) 1 << 3;
+
+  // program MrsAddress[6:4,2]=read CAS latency
+  // (CL):based on F2x[1,0]88[Tcl]
+  // -- F2x88[3:0] to MrsAddress[6:4,2]=xxx0b --
+  MrsAddress |= NBPtr->GetBitField (NBPtr, BFTcl) << 4;
+
+  // program MrsAddress[11:9]=write recovery for auto-precharge
+  // (WR):based on F2x[1,0]84[Twr]
+  MrsAddress |= NBPtr->GetBitField (NBPtr, BFTwrDDR3) << 9;
+
+  // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel]
+  MrsAddress |= NBPtr->GetBitField (NBPtr, BFPchgPDModeSel) << 12;
+
+  // program MrsAddress[8]=1 (DLL):DLL reset
+  MrsAddress |= (UINT32) 1 << 8;
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This send all MR commands to a rank in sequence 2-3-1-0
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       ChipSel    - Target Chip Select
+ */
+
+VOID
+MemTSendAllMRCmds3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+
+  // 13.Send EMRS(2)
+  MemTEMRS23 (TechPtr);
+  NBPtr->SendMrsCmd (NBPtr);
+
+  // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
+  MemTEMRS33 (TechPtr);
+  NBPtr->SendMrsCmd (NBPtr);
+
+  // 15.Send EMRS(1).
+  MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1));
+  NBPtr->SendMrsCmd (NBPtr);
+
+  // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
+  MemTMRS3 (TechPtr);
+  NBPtr->SendMrsCmd (NBPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
new file mode 100755
index 0000000000..fcd98566bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtsdi3.h
@@ -0,0 +1,86 @@
+/**
+ * @file
+ *
+ * mtsdi3.h
+ *
+ * Technology software DRAM init for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTSDI3_H_
+#define _MTSDI3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemTEMRS13 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       BOOLEAN Wl,
+  IN       UINT8 TargetDIMM
+  );
+
+VOID
+MemTEMRS23 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MTSDI3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
new file mode 100755
index 0000000000..4b1f025c9f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.c
@@ -0,0 +1,1089 @@
+/**
+ * @file
+ *
+ * mtspd3.c
+ *
+ * Technology SPD supporting functions for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mt3.h"
+#include "mu.h"
+#include "mtspd3.h"
+#include "mftds.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+MemTCRCCheck3 (
+  IN OUT   UINT8 *SPDPtr
+  );
+
+UINT8
+STATIC
+MemTSPDGetTCL3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+STATIC
+MemTCheckBankAddr3 (
+  IN       UINT8 Encode,
+     OUT   UINT8 *Index
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DRAM mode
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that the DRAM mode is set to DDR3
+ */
+
+BOOLEAN
+MemTSetDramMode3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTDIMMPresence3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  MEM_PARAMETER_STRUCT *RefPtr;
+  UINT8 *SpdBufferPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_NB_BLOCK *NBPtr;
+  BOOLEAN SPDCtrl;
+  UINT8 Devwidth;
+  UINT8 MaxDimms;
+  UINT8 Value8;
+  UINT16  DimmMask;
+
+  NBPtr = TechPtr->NBPtr;
+  RefPtr = NBPtr->RefPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    printk(BIOS_DEBUG, " Dct %x ", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      printk(BIOS_DEBUG, "Channel %x\n", Channel);
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      ChannelPtr->DimmQrPresent = 0;
+      //
+      // Get the maximum number of DIMMs
+      //
+      MaxDimms = MAX_DIMMS_PER_CHANNEL;
+      for (i = 0; i < MaxDimms; i++) {
+        //  Bitmask representing dimm #i.
+        DimmMask = (UINT16)1 << i;
+        //
+        if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) {
+          MCTPtr->DimmPresent |= DimmMask;
+          //
+          //  Check for valid checksum value
+          //
+          AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
+          if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) {
+            ChannelPtr->ChDimmValid |= DimmMask;
+            MCTPtr->DimmValid |= DimmMask;
+          } else {
+            // Current socket is set up to only support DDR3 dimms.
+            IDS_ERROR_TRAP;
+          }
+          if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) {
+            //
+            // NV_SPDCHK_RESTRT is set to 0,
+            // cannot ignore faulty SPD checksum
+            //
+            //  Indicate checksum error
+            ChannelPtr->DimmSpdCse |= DimmMask;
+            PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            SetMemError (AGESA_ERROR, MCTPtr);
+          }
+          //
+          //  Check module type information.
+          //
+          if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) {
+            ChannelPtr->RegDimmPresent |= DimmMask;
+            MCTPtr->RegDimmPresent |= DimmMask;
+            if (!UserOptions.CfgMemoryRDimmCapable) {
+              PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+              IDS_ERROR_TRAP;
+            }
+          }
+          if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) {
+            PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            IDS_ERROR_TRAP;
+          }
+          if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) {
+            ChannelPtr->SODimmPresent |= DimmMask;
+            if (!UserOptions.CfgMemorySODimmCapable) {
+              PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+              IDS_ERROR_TRAP;
+            }
+          }
+          //
+          //  Check error correction type
+          //
+          if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) {
+            MCTPtr->DimmEccPresent |= DimmMask;  //  Dimm has ECC
+          }
+          //
+          //  Get the Dimm width data
+          //
+          Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7;
+          switch (Devwidth) {
+          case 0:
+            ChannelPtr->Dimmx4Present |= DimmMask;
+            Devwidth = 4;
+            break;
+          case 1:
+            ChannelPtr->Dimmx8Present |= DimmMask;
+            Devwidth = 8;
+            break;
+          case 2:
+            ChannelPtr->Dimmx16Present |= DimmMask;
+            Devwidth = 16;
+            break;
+          default:
+            IDS_ERROR_TRAP;
+          }
+          //
+          //  Check for 'analysis probe installed'
+          // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK)
+          //
+          //  Determine the geometry of the DIMM module
+          // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT)
+          //
+          //  specify the number of ranks
+          //
+          Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
+          if (Value8 > 2) {
+            if (!UserOptions.CfgMemoryQuadRankCapable) {
+              PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            }
+            //
+            // Mark this Dimm as Quad Rank
+            //
+            ChannelPtr->DimmQrPresent |= DimmMask;
+            Value8 = 2;
+          } else if (Value8 == 2) {
+            ChannelPtr->DimmDrPresent |= DimmMask;   //  Dual rank dimms
+          } else {
+            ChannelPtr->DimmSRPresent |= DimmMask;   //  Single rank dimms
+          }
+          //
+          //  Calculate bus loading per Channel
+          if (Devwidth == 16) {
+            Devwidth = 4;
+          } else if (Devwidth == 4) {
+            Devwidth = 16;
+          }
+          //
+          //  double Addr bus load value for dual rank DIMMs
+          //
+          if (Value8 == 2) {
+            Devwidth = Devwidth << 1;
+          }
+          //
+          ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
+          ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
+          if ((i < 2) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) {
+            ChannelPtr->Dimms++;
+          }
+          //
+          // Check address mirror support for Unbuffered Dimms only
+          //
+          if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) {
+            if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
+              ChannelPtr->DimmMirrorPresent |= DimmMask;
+            }
+          }
+          //
+          // Get byte62: Reference Raw Card information
+          //
+          ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F;
+          //
+          // Get control word values for RC3, RC4 and RC5
+          //
+          ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4;
+          ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F;
+          ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4;
+          //
+          // Temporarily store info. of SPD byte 63 into CtrlWrd02(s),
+          // and they will be used late to calculate real RC2 and RC8 value
+          //
+          ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
+          //
+        } // if DIMM present
+      } // Dimm loop
+
+      if (Channel == 0) {
+        DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
+        DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent;
+        DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
+        DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
+        DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
+        DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent;
+        DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
+        DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
+        DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
+      }
+      if ((Channel != 1) || (Dct != 1)) {
+        MCTPtr->DimmPresent <<= 8;
+        MCTPtr->DimmValid <<= 8;
+        MCTPtr->RegDimmPresent <<= 8;
+        MCTPtr->DimmEccPresent <<= 8;
+        MCTPtr->DimmParPresent <<= 8;
+      }
+      printk(BIOS_DEBUG, "  RegDimmPresent:    %x\n", ChannelPtr->RegDimmPresent);
+      printk(BIOS_DEBUG, "  SODimmPresent:     %x\n", ChannelPtr->SODimmPresent);
+      printk(BIOS_DEBUG, "  ChDimmValid:       %x\n", ChannelPtr->ChDimmValid);
+      printk(BIOS_DEBUG, "  DimmPlPresent:     %x\n", ChannelPtr->DimmPlPresent);
+      printk(BIOS_DEBUG, "  DimmQrPresent:     %x\n", ChannelPtr->DimmQrPresent);
+      printk(BIOS_DEBUG, "  DimmDrPresent:     %x\n", ChannelPtr->DimmDrPresent);
+      printk(BIOS_DEBUG, "  DimmSRPresent:     %x\n", ChannelPtr->DimmSRPresent);
+      printk(BIOS_DEBUG, "  Dimmx4Present:     %x\n", ChannelPtr->Dimmx4Present);
+      printk(BIOS_DEBUG, "  DimmX8Present:     %x\n", ChannelPtr->Dimmx8Present);
+      printk(BIOS_DEBUG, "  DimmX16Present:    %x\n", ChannelPtr->Dimmx16Present);
+      printk(BIOS_DEBUG, "  DimmMirrorPresent: %x\n", ChannelPtr->DimmMirrorPresent);
+    } // Channel loop
+  } // DCT loop
+
+  //  If we have DIMMs, some further general characteristics checking
+  if (MCTPtr->DimmValid != 0) {
+    //  If there are registered dimms, all the dimms must be registered
+    if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
+      //  All dimms registered
+      MCTPtr->Status[SbRegistered] = TRUE;
+      MCTPtr->Status[SbParDimms] = TRUE;  //  All DDR3 RDIMMs are parity capable
+      TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing
+    } else if (MCTPtr->RegDimmPresent != 0) {
+      //  We have an illegal DIMM mismatch
+      PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_FATAL, MCTPtr);
+    }
+
+    //  check the ECC capability of the DIMMs
+    if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
+      MCTPtr->Status[SbEccDimms] = TRUE;  //  All dimms ECC capable
+    }
+  } else {
+  }
+
+  NBPtr->SwitchDCT (NBPtr, 0);
+  NBPtr->SwitchChannel (NBPtr, 0);
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function finds the maximum frequency that each channel is capable to run at.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDGetTargetSpeed3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferPtr;
+  UINT8 Dimm;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT16 MTB16x;
+  UINT16 TCKmin16x;
+  UINT16 Value16;
+  MEM_NB_BLOCK *NBPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+    TCKmin16x = 0;
+    for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      ChannelPtr = NBPtr->ChannelPtr;
+      for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+        if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
+          MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+
+          // Determine tCKmin(all) which is the largest tCKmin
+          // value for all modules on the memory Channel (SPD byte 12).
+          //
+          MTB16x = ((UINT16)SpdBufferPtr[SPD_DIVIDENT] << 4) / SpdBufferPtr[SPD_DIVISOR];
+          Value16 = SpdBufferPtr[SPD_TCK] * MTB16x;
+          if (TCKmin16x < Value16) {
+            TCKmin16x = Value16;
+          }
+        }
+      }
+    }
+    if (TCKmin16x <= 17) {
+      DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY;
+    } else if (TCKmin16x <= 20) {
+      DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY;
+    } else if (TCKmin16x <= 24) {
+      DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY;
+    } else if (TCKmin16x <= 30) {
+      DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY;
+    } else if (TCKmin16x <= 40) {
+      DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY;
+    } else {
+      DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY;
+    }
+  }
+
+  // Ensure the target speed can be applied to all channels of the current node
+  NBPtr->SyncTargetSpeed (NBPtr);
+
+  // Set the start-up frequency
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed;
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
+ *   DIMM on Channel B), the overall DIMM population, and determine the width mode:
+ *   64-bit, 64-bit muxed, 128-bit.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDCalcWidth3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferAPtr;
+  UINT8 *SpdBufferBPtr;
+  MEM_NB_BLOCK *NBPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 i;
+  UINT16 DimmMask;
+  UINT8 UngangMode;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  UngangMode = UserOptions.CfgMemoryModeUnganged;
+  // Does not support ganged mode for DDR3 dimms
+  ASSERT (UngangMode);
+  IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
+
+  //  Check symmetry of channel A and channel B dimms for 128-bit mode
+  //  capability.
+  //
+  AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
+  i = 0;
+  if (!UngangMode) {
+    if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
+      for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
+        DimmMask = (UINT16)1 << i;
+        if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
+          NBPtr->SwitchDCT (NBPtr, 0);
+          MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i);
+          NBPtr->SwitchDCT (NBPtr, 1);
+          MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i);
+          // compare rows and columns
+          if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) {
+            break;
+          }
+          if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) {
+            break;
+          }
+          // compare ranks and devwidth
+          if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
+            break;
+          }
+        }
+      }
+    }
+    if (i < MAX_DIMMS_PER_CHANNEL) {
+      PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ALERT, MCTPtr);
+    } else {
+      NBPtr->Ganged = TRUE;
+      MCTPtr->GangedMode = TRUE;
+      MCTPtr->Status[Sb128bitmode] = TRUE;
+      NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
+    }
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       Initialize DCT Timing registers as per DIMM SPD.
+ *       For primary timing (T, CL) use best case T value.
+ *       For secondary timing params., use most aggressive settings
+ *           of slowest DIMM.
+ *
+ *   Note:
+ *   There are three components to determining "maximum frequency": SPD component,
+ *   Bus load component, and "Preset" max frequency component.
+ *   The SPD component is a function of the min cycle time specified by each DIMM,
+ *   and the interaction of cycle times from all DIMMs in conjunction with CAS
+ *   latency.  The SPD component only applies when user timing mode is 'Auto'.
+ *
+ *   The Bus load component is a limiting factor determined by electrical
+ *   characteristics on the bus as a result of varying number of device loads.  The
+ *   Bus load component is specific to each platform but may also be a function of
+ *   other factors.  The bus load component only applies when user timing mode is
+ * ' Auto'.
+ *
+ *   The Preset component is subdivided into three items and is the minimum of
+ *   the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
+ *   memclock mode is 'Limit', OEM build specification of the maximum frequency.
+ *   The Preset component only applies when user timing mode is 'Auto'.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTAutoCycTiming3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  CONST UINT8 SpdIndexes[] = {
+    SPD_TRCD,
+    SPD_TRP,
+    SPD_TRTP,
+    SPD_TRAS,
+    SPD_TRC,
+    SPD_TWR,
+    SPD_TRRD,
+    SPD_TWTR,
+    SPD_TFAW
+  };
+
+  UINT8  *SpdBufferPtr;
+  UINT16 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
+  UINT8  MiniMaxTrfc[4];
+
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 DimmMask;
+  UINT16 Value16;
+  UINT16 MTB16x;
+  UINT16 TCK16x;
+  UINT8 i;
+  UINT8 j;
+  UINT8 Value8;
+  UINT8  *StatTmgPtr;
+  UINT16 *StatDimmTmgPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  // initialize mini-max arrays
+  for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
+    MiniMaxTmg[j] = 0;
+  }
+  for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
+    MiniMaxTrfc[j] = 0;
+  }
+
+  // ======================================================================
+  //  Get primary timing (CAS Latency and Cycle Time)
+  // ======================================================================
+  //  Get OEM specific load variant max
+  //
+
+  //======================================================================
+  // Gather all DIMM mini-max values for cycle timing data
+  //======================================================================
+  //
+  DimmMask = 1;
+  for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
+    if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
+      MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i);
+      MTB16x = ((UINT16)SpdBufferPtr[SPD_DIVIDENT] << 4) / SpdBufferPtr[SPD_DIVISOR];
+
+      for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
+        Value16 = (UINT16)SpdBufferPtr[SpdIndexes[j]];
+        if (SpdIndexes[j] == SPD_TRC) {
+          Value16 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4;
+        } else if (SpdIndexes[j] == SPD_TRAS) {
+          Value16 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8;
+        } else if (SpdIndexes[j] == SPD_TFAW) {
+          Value16 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8;
+        }
+        Value16 = Value16 * MTB16x;
+        if (MiniMaxTmg[j] < Value16) {
+          MiniMaxTmg[j] = Value16;
+        }
+      }
+
+      //  get Trfc0 - Trfc3 values
+      Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F;
+      if (MiniMaxTrfc[i] < Value8) {
+        MiniMaxTrfc[i] = Value8;
+      }
+    }
+    DimmMask <<= 1;
+  }
+
+  // ======================================================================
+  //  Convert  DRAM CycleTiming values and store into DCT structure
+  // ======================================================================
+  //
+  TCK16x = (16000 + 16) / DCTPtr->Timings.Speed;   // Offset of 16 is used to round to the nearest integer
+
+  //   Notes:
+  //      1. All secondary time values given in SPDs are in binary with UINTs of ns.
+  //      2. All time values are scaled by 16, in order to have least count of 0.125 ns
+  //         (more accuracy).
+  //      3. Internally to this SW, cycle time, TCK16x, is scaled by 16 to match time values
+  //
+  StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
+  StatTmgPtr = &DCTPtr->Timings.Trcd;
+  for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
+    Value16 = MiniMaxTmg[j];
+
+    MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK16x - 1) / TCK16x;
+
+    StatDimmTmgPtr[j] = Value16;
+    StatTmgPtr[j] = (UINT8)MiniMaxTmg[j];
+  }
+  DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
+  DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
+  DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
+  DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
+
+  DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr);
+
+  //======================================================================
+  // Program DRAM Timing values
+  //======================================================================
+  //
+  NBPtr->ProgramCycTimings (NBPtr);
+
+  MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the bank addressing, program Mask values and build a chip-select population map.
+ *   This routine programs PCI 0:24N:2x80 config register.
+ *   This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE  - indicates that a FATAL error has not occurred
+ *     @return  FALSE - indicates that a FATAL error has occurred
+ */
+
+BOOLEAN
+MemTSPDSetBanks3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 *SpdBufferPtr;
+  UINT8 i;
+  UINT8 ChipSel;
+  UINT8 DimmID;
+  UINT8 Value8;
+  UINT8 Rows;
+  UINT8 Cols;
+  UINT8 Ranks;
+  UINT8 Banks;
+  UINT32 BankAddrReg;
+  UINT32 CsMask;
+  UINT16 CSSpdCSE;
+  UINT16 CSExclude;
+  UINT16 DimmQRDR;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  BankAddrReg = 0;
+  CSSpdCSE = 0;
+  CSExclude = 0;
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
+    DimmID = ChipSel >> 1;
+
+    DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
+    if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) {
+      CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
+    }
+    if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
+      CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
+    }
+
+    if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) {
+      MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID);
+
+      //  Get the basic data
+      Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7;
+      Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7;
+      Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7;
+      Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
+
+      //
+      // Configure the bank encoding
+      // Use a 6-bit key into a lookup table.
+      // Key (index) = RRRBCC, where CC is the number of Columns minus 9,
+      // RRR is the number of Rows minus 12, and B is the number of banks
+      // minus 3.
+      //
+      Value8 = Cols;
+      Value8 |= (Banks == 1) ? 4 : 0;
+      Value8 |= Rows << 3;
+
+      if (MemTCheckBankAddr3 (Value8, &i)) {
+        BankAddrReg |= ((UINT32)i << (ChipSel << 1));
+
+        // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
+        // or 2pow(rows+cols+banks-5)-1
+        //
+        Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8;
+        if (MCTPtr->Status[Sb128bitmode]) {
+          Value8++;
+        }
+        CsMask = ((UINT32)1 << Value8) - 1;
+        DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
+
+        if (Ranks >= 2) {
+          DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
+        }
+
+        //  Update the DRAM CS Mask for this chipselect
+        NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0));
+      } else {
+        // Dimm is not supported, as no address mapping is found.
+        DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
+        DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel;
+        if (Ranks >= 2) {
+          DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
+          DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1);
+        }
+        PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader);
+        SetMemError (AGESA_ERROR, MCTPtr);
+      }
+    }
+  }
+  // For ranks that need to be excluded, the loading of this rank should be considered
+  // in timing, so need to set CsPresent before setting CsTestFail
+  if ((CSSpdCSE != 0) || (CSExclude != 0)) {
+    NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader);
+  }
+
+  //  If there are no chip selects, we have an error situation.
+  if (DCTPtr->Timings.CsPresent == 0) {
+    PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_ERROR, MCTPtr);
+  }
+
+  NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the low bit that will be swapped to enable CS interleaving
+ *
+ *     @param[in]   BankEnc - AddrMap Bank encoding from F2x80
+ *     @param[in]   *LowBit - pointer to low bit
+ *     @param[in]   *HiBit  - pointer hight bit
+ *
+ */
+
+VOID
+MemTGetCSIntLvAddr3 (
+  IN       UINT8 BankEnc,
+     OUT   UINT8 *LowBit,
+     OUT   UINT8 *HiBit
+  )
+{
+  CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9};
+  CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25};
+  ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
+  ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
+  //  return ArrCodes[BankEnc];
+  *LowBit = ArrCodesLo[BankEnc];
+  *HiBit = ArrCodesHi[BankEnc];
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function determines if the checksum is correct
+ *
+ *     @param[in]   *SPDPtr - Pointer to SPD data
+ *
+ *     @return    TRUE  - CRC check passes
+ *     @return    FALSE - CRC check fails
+ */
+
+BOOLEAN
+STATIC
+MemTCRCCheck3 (
+  IN OUT   UINT8 *SPDPtr
+  )
+{
+  UINT16 Crc;
+  INT16 i;
+  INT16 j;
+  INT16 Count;
+
+  if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) {
+    Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126;
+    Crc = 0;
+    for (j = 0; j < Count; j++) {
+      Crc = Crc ^ ((UINT16)SPDPtr[j] << 8);
+      for (i = 0; i < 8; i++) {
+        if (Crc & 0x8000) {
+          Crc = (Crc << 1) ^ 0x1021;
+        } else {
+          Crc = (Crc << 1);
+        }
+      }
+    }
+    if (*(UINT16 *) (SPDPtr + 126) == Crc) {
+      return TRUE;
+    }
+  }
+
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  CAS Latency
+ */
+
+UINT8
+STATIC
+MemTSPDGetTCL3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8  *SpdBufferPtr;
+  UINT8 CLdesired;
+  UINT8 CLactual;
+  UINT8 Dimm;
+  UINT8 Channel;
+  UINT16 CASLat;
+  UINT16 MTB16x;
+  UINT16 TAAmin16x;
+  UINT16 TCKproposed16x;
+  UINT16 Value16;
+  UINT16 Mask16;
+  BOOLEAN CltFail;
+  MEM_NB_BLOCK *NBPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  DCTPtr = NBPtr->DCTPtr;
+
+  CASLat = 0xFFFF;
+  TAAmin16x = 0;
+  CltFail = FALSE;
+
+  for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
+    NBPtr->SwitchChannel (NBPtr, Channel);
+    ChannelPtr = NBPtr->ChannelPtr;
+    for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+      if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
+        MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
+
+        // Step 1: Determine the common set of supported CAS Latency
+        // values for all modules on the memory Channel using the CAS
+        // Latencies Supported in SPD bytes 14 and 15.
+        //
+        CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO];
+
+        // Step 2: Determine tAAmin(all) which is the largest tAAmin
+        // value for all modules on the memory Channel (SPD byte 16).
+        //
+        MTB16x = ((UINT16)SpdBufferPtr[SPD_DIVIDENT] << 4) / SpdBufferPtr[SPD_DIVISOR];
+        Value16 = SpdBufferPtr[SPD_TAA] * MTB16x;
+        if (TAAmin16x < Value16) {
+          TAAmin16x = Value16;
+        }
+
+        // Step 3: Determine tCKmin(all) which is the largest tCKmin
+        // value for all modules on the memory Channel (SPD byte 12).
+        // * This step has been done in SPDGetTargetSpeed
+      }
+    }
+  }
+
+  TCKproposed16x = (16000 + 16) / DCTPtr->Timings.Speed;   // Offset of 16 is used to round to the nearest integer
+
+  // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax,
+  // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC
+  // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the
+  // next lower standard tCK value for calculating CLdesired.
+  // CLdesired = ceiling ( tAAmin(all) / tCKproposed )
+  // where tAAmin is defined in Byte 16. The ceiling function requires that the
+  // quotient be rounded up always.
+  //
+  CLdesired = (UINT8) ((TAAmin16x + TCKproposed16x - 1) / TCKproposed16x);
+
+  // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal
+  // to CLdesired and is supported by all modules on the memory Channel as
+  // determined in step 1. If no such value exists, choose a higher tCKproposed
+  // value and repeat steps 4 and 5 until a solution is found.
+  //
+  CLactual = 4;
+  for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) {
+    if (CASLat & Mask16) {
+      if (CLdesired <= CLactual) {
+        break;
+      }
+    }
+    CLactual++;
+  }
+  if (Mask16 == 0x8000) {
+    CltFail = TRUE;
+  }
+
+  // Step 6: Once the calculation of CLactual is completed, the BIOS must also
+  // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns
+  // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If
+  // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found.
+  //
+  if ((TCKproposed16x * CLactual) > 320) {
+    CltFail = TRUE;
+  }
+
+  if (!CltFail) {
+    DCTPtr->Timings.CasL = CLactual;
+  } else {
+    //  Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin.
+    DCTPtr->Timings.CasL = 6;
+  }
+
+  return DCTPtr->Timings.CasL;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function returns the encoded value of bank address.
+ *
+ *     @param[in]   Encode - RRRBCC, where CC is the number of Columns minus 9,
+ *                           RRR is the number of Rows minus 12, and B is the number of banks
+ *                           minus 3.
+ *     @param[out]  *Index - index in bank address table
+ *     @return      TRUE   - encoded value is found.
+ *                  FALSE  - encoded value is not found.
+ */
+
+BOOLEAN
+STATIC
+MemTCheckBankAddr3 (
+  IN       UINT8 Encode,
+     OUT   UINT8 *Index
+  )
+{
+  UINT8 i;
+  CONST UINT8 TabBankAddr[]  = {
+    0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11,
+    0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22
+  };
+
+  for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) {
+    if (Encode == TabBankAddr[i]) {
+      *Index = i;
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function returns a pointer to the SPD Buffer of a specific dimm on
+ *    the current channel.
+ *
+ *     @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
+ *     @param[in] Dimm - Dimm number
+ *
+ *
+ *     @return BOOLEAN - Value of DimmPresent
+ *                       TRUE = Dimm is present, pointer is valid
+ *                       FALSE = Dimm is not present, pointer has not been modified.
+ */
+
+BOOLEAN
+MemTGetDimmSpdBuffer3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 **SpdBuffer,
+  IN       UINT8 Dimm
+  )
+{
+  CH_DEF_STRUCT *ChannelPtr;
+  SPD_DEF_STRUCT *SPDPtr;
+  BOOLEAN DimmPresent;
+
+  DimmPresent = FALSE;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
+  SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
+
+
+  if (SPDPtr != NULL) {
+    DimmPresent = SPDPtr->DimmPresent;
+    if (DimmPresent) {
+      *SpdBuffer = SPDPtr->Data;
+    }
+  }
+  return DimmPresent;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
new file mode 100755
index 0000000000..44424b64c7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mtspd3.h
@@ -0,0 +1,166 @@
+/**
+ * @file
+ *
+ * mtspd3.h
+ *
+ * Technology SPD support for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTSPD3_H_
+#define _MTSPD3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*===============================================================================
+ *   Jedec DDR III
+ *===============================================================================
+ */
+#define SPD_BYTE_USED     0
+#define SPD_TYPE         2              /* SPD byte read location */
+#define JED_DDR_SDRAM     7              /* Jedec defined bit field */
+#define JED_DDR2_SDRAM    8              /* Jedec defined bit field */
+#define JED_DDR3SDRAM    0xB            /* Jedec defined bit field */
+
+#define SPD_DIMM_TYPE    3
+#define SPD_ATTRIB      21
+#define JED_DIF_CK_MSK    0x20            /* Differential Clock Input */
+#define JED_RDIMM       1
+#define JED_MINIRDIMM   5
+#define JED_UDIMM       2
+#define JED_SODIMM       3
+
+#define SPD_L_BANKS      4               /* [7:4] number of [logical] banks on each device */
+#define SPD_DENSITY     4               /* bit 3:0 */
+#define SPD_ROW_SZ       5               /* bit 5:3 */
+#define SPD_COL_SZ       5               /* bit 2:0 */
+#define SPD_RANKS       7               /* bit 5:3 */
+#define SPD_DEV_WIDTH    7               /* bit 2:0 */
+#define SPD_ECCBITS     8               /* bit 4:3 */
+#define JED_ECC         8
+#define SPD_RAWCARD     62              /* bit 2:0 */
+#define SPD_ADDRMAP     63              /* bit 0 */
+
+#define SPD_CTLWRD03     70              /* bit 7:4 */
+#define SPD_CTLWRD04     71              /* bit 3:0 */
+#define SPD_CTLWRD05     71              /* bit 7:4 */
+
+#define SPD_DIVIDENT    10
+#define SPD_DIVISOR     11
+
+#define SPD_TCK         12
+#define SPD_CASLO       14
+#define SPD_CASHI       15
+#define SPD_TAA         16
+
+#define SPD_TRP         20
+#define SPD_TRRD        19
+#define SPD_TRCD        18
+#define SPD_TRAS        22
+#define SPD_TWR         17
+#define SPD_TWTR        26
+#define SPD_TRTP        27
+#define SPD_TRC         23
+#define SPD_UPPER_TRC   21              /* bit 7:4 */
+#define SPD_UPPER_TRAS  21              /* bit 3:0 */
+#define SPD_TFAW        29
+#define SPD_UPPER_TFAW  28              /* bit 3:0 */
+
+/*-----------------------------
+ * Jedec DDR II related equates
+ *-----------------------------
+ */
+
+#define CL_DEF          4              /* Default value for failsafe operation. 4=CL 6.0 T */
+#define T_DEF           4              /* Default value for failsafe operation. 4=2.5ns (cycle time) */
+
+#define BIAS_TRTP_T      4
+#define BIAS_TRCD_T      5
+#define BIAS_TRAS_T      15
+#define BIAS_TRC_T       11
+#define BIAS_TRRD_T      4
+#define BIAS_TWR_T       4
+#define BIAS_TRP_T       5
+#define BIAS_TWTR_T      4
+#define BIAS_TFAW_T      14
+
+#define MIN_TRTP_T       4
+#define MAX_TRTP_T       7
+#define MIN_TRCD_T       5
+#define MAX_TRCD_T       12
+#define MIN_TRAS_T       15
+#define MAX_TRAS_T       30
+#define MIN_TRC_T        11
+#define MAX_TRC_T        42
+#define MIN_TRRD_T       4
+#define MAX_TRRD_T       7
+#define MIN_TWR_T        5
+#define MAX_TWR_T        12
+#define MIN_TRP_T        5
+#define MAX_TRP_T        12
+#define MIN_TWTR_T       4
+#define MAX_TWTR_T       7
+#define MIN_TFAW_T       16
+#define MAX_TFAW_T       32
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#endif  /* _MTSPD3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
new file mode 100755
index 0000000000..aad773e7d0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttecc3.c
@@ -0,0 +1,161 @@
+/**
+ * @file
+ *
+ * mttecc3.c
+ *
+ * Technology ECC byte support for registered DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 12509 $ @e \$Date: 2009-04-20 21:38:29 -0500 (Mon, 20 Apr 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DQS ECC timings for registered DDR3
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTSetDQSEccTmgsRDdr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Dimm;
+  UINT8 i;
+  UINT8 *WrDqsDly;
+  UINT16 *RcvEnDly;
+  UINT8 *RdDqsDly;
+  UINT8 *WrDatDly;
+  UINT8 EccByte;
+  INT16 TempValue;
+
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  EccByte = TechPtr->MaxByteLanes ();
+  NBPtr = TechPtr->NBPtr;
+
+  if (NBPtr->MCTPtr->NodeMemSize) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+          if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) {
+            i = Dimm * TechPtr->DlyTableWidth ();
+            WrDqsDly = &ChannelPtr->WrDqsDlys[i];
+            RcvEnDly = &ChannelPtr->RcvEnDlys[i];
+            RdDqsDly = &ChannelPtr->RdDqsDlys[i];
+            WrDatDly = &ChannelPtr->WrDatDlys[i];
+            // Receiver DQS Enable:
+            // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 -
+            //                                        [write DQS for bytelane 3 - write DQS for ECC]
+
+            TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]);
+            if (TempValue < 0) {
+              TempValue = 0;
+            }
+            RcvEnDly[EccByte] = (UINT16) TempValue;
+
+            // Read DQS:
+            // Read DQS for ECC bytelane = read DQS of byte lane 3
+            //
+            RdDqsDly[EccByte] = RdDqsDly[3];
+
+            // Write Data:
+            // Write Data for ECC bytelane = Write DQS for ECC +
+            //                               [write data for bytelane 3 - Write DQS for bytelane 3]
+            TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3]));
+            if (TempValue < 0) {
+              TempValue = 0;
+            }
+            WrDatDly[EccByte] = (UINT8) TempValue;
+
+            NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]);
+            NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]);
+            NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]);
+          }
+        }
+      }
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
new file mode 100755
index 0000000000..c276b075c1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/DDR3/mttwl3.c
@@ -0,0 +1,603 @@
+/**
+ * @file
+ *
+ * mttwl3.c
+ *
+ * Technology Phy assisted write levelization for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech/DDR3)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mtsdi3.h"
+#include "merrhdl.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTWriteLevelizationHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTWLPerDimmHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTPrepareDIMMs3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 TargetDIMM,
+  IN       BOOLEAN Wl
+  );
+
+VOID
+STATIC
+MemTProcConfig3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTBeginWLTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of Phy assisted write levelization
+ *      for a specific node (DDR800).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTWriteLevelizationHw3 (TechPtr, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes second pass of Phy assisted write levelization
+ *      for a specific node (DDR1066 and above).
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  // If current speed is higher than start-up speed, do second pass of WL
+  if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
+    return MemTWriteLevelizationHw3 (TechPtr, 2);
+  }
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function prepares for Phy assisted training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTPreparePhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  //  Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1);
+  //  Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0);
+  return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function revert to normal settings when exiting from Phy assisted training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTExitPhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  //  13.Program F2x[1, 0]8C[DisAutoRefresh] = 0.
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 0);
+  //  14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 2);
+  return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executed hardware based write levelization for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+STATIC
+MemTWriteLevelizationHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  DCT_STRUCT *DCTPtr;
+  UINT8 Dct;
+  UINT8 Dimm;
+
+  NBPtr = TechPtr->NBPtr;
+
+  IDS_HDT_CONSOLE ("!\nStart write leveling\n");
+  AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader));
+  // Begin DQS Write timing training
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    //training for each Dimm
+    for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+      if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) {
+
+        IDS_HDT_CONSOLE ("!\t\tCS %d\n", Dimm << 1);
+        MemTWLPerDimmHw3 (TechPtr, Dimm, Pass);
+      }
+    }
+  }
+  IDS_HDT_CONSOLE ("End write leveling\n\n");
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function initializes per DIMM write levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Dimm - DIMM to be trained
+ *     @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
+ *
+ */
+
+VOID
+STATIC
+MemTWLPerDimmHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL);
+
+  // 1. Specify the target Dimm that is to be trained by programming
+  //     F2x[1, 0]9C_x08[TrDimmSel].
+  NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm);
+
+  // 2. Prepare the DIMMs for write levelization using DDR3-defined
+  // MR commands.
+  MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE);
+
+  // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to
+  //     satisfy DDR3-defined internal DRAM timing.
+  MemUWait10ns (10, MemPtr);
+
+  // 4. Configure the processor's DDR phy for write levelization training:
+  MemTProcConfig3 (TechPtr, Dimm, Pass);
+
+  // 5. Begin write levelization training
+  MemTBeginWLTrain3 (TechPtr, Dimm);
+
+  // 7. Program the target Dimm back to normal operation
+  MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function prepares the DIMMS for Write Levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] TargetDIMM - DIMM to be trained
+ *     @param[in] Wl - Indicates if WL mode should be enabled
+ *
+ */
+
+VOID
+STATIC
+MemTPrepareDIMMs3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 TargetDIMM,
+  IN       BOOLEAN Wl
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8 ChipSel;
+
+  NBPtr = TechPtr->NBPtr;
+
+  AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader));
+  ASSERT (TargetDIMM < MAX_DIMMS_PER_CHANNEL);
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+    if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
+      if (Wl) {
+        // Program WrLvOdt
+        NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[ChipSel >> 1]);
+      }
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+      // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
+      MemTEMRS13 (TechPtr, Wl, TargetDIMM);
+      // Send command
+      NBPtr->SendMrsCmd (NBPtr);
+      // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
+      MemTEMRS23 (TechPtr);
+      // Send command
+      NBPtr->SendMrsCmd (NBPtr);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function programs seed values for Write Levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Dimm - DIMM to be trained
+ *     @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz)
+ *
+ */
+
+VOID
+STATIC
+MemTProcConfig3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Pass
+  )
+{
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 WrDqsDly;
+  // Memclk Delay incurred by register.
+  UINT8 MemClkRegDly;
+  UINT8 ByteLane;
+  UINT8 DefaultSeed;
+  UINT8 CurrentSeed;
+  UINT8 *Seed;
+  UINT8 RCW2;
+  UINT16 Speed;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader));
+  RCW2 = ChannelPtr->CtrlWrd02[Dimm];
+  Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
+
+  IDS_HDT_CONSOLE ("\n\t\t\tSeeds: ");
+  //  Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
+  //  the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
+  //  BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
+  //  use an initial total delay value.
+  if (Pass == 1) {
+    // Get the default value of seed
+    DefaultSeed = 0x1A;
+    if (MCTPtr->Status[SbRegistered]) {
+      DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51;
+    }
+
+    if (Speed == DDR667_FREQUENCY) {
+      DefaultSeed = (UINT8) ((DefaultSeed * 333 + 399) / 400); //round up
+    }
+    ASSERT (Speed >= DDR667_FREQUENCY);
+
+    // Get platform override seed
+    Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID);
+
+    for (ByteLane = 0; ByteLane < 9; ByteLane++) {
+      // This includes ECC as byte 8
+      CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
+      NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
+      ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed;
+      IDS_HDT_CONSOLE ("%02x ", CurrentSeed);
+    }
+  } else {
+    //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find
+    //the gross and fine delay initialization values at the target frequency. Use these values as the initial
+    //seed values when executing Pass 2, step #4.
+    for (ByteLane = 0; ByteLane < 9; ByteLane++) {
+      // This includes ECC as byte 8
+      WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane];
+      //
+      // For Registered Dimms
+      //
+      if (MCTPtr->Status[SbRegistered]) {
+        MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30;
+        WrDqsDly = (UINT16) (MemClkRegDly + ((((UINT32) WrDqsDly - MemClkRegDly) * Speed) / TechPtr->PrevSpeed));
+      } else {
+        //
+        // Unbuffered Dimms
+        //
+        WrDqsDly = (UINT16) (((UINT32) WrDqsDly * Speed) / TechPtr->PrevSpeed);
+      }
+
+      ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly;
+
+      if (NBPtr->IsSupported[WLSeedAdjust]) {
+        // Adjust seed to avoid overflowing PRE for the case SeedGross >= 3
+        if (WrDqsDly >= 0x60) {
+          if ((WrDqsDly & 0x20) != 0) {
+            // If (SeedGross is odd) then SeedPreGross = 1
+            WrDqsDly = (WrDqsDly & 0x1F) | 0x20;
+          } else {
+            // If (SeedGross is even) then SeedPreGross = 2
+            WrDqsDly = (WrDqsDly & 0x1F) | 0x40;
+          }
+        }
+      }
+
+      NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly);
+      IDS_HDT_CONSOLE ("%02x ", WrDqsDly);
+    }
+  }
+  IDS_HDT_CONSOLE ("\n");
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function begins WL training for a specific DIMM
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Dimm - DIMM to be trained
+ *
+ */
+
+VOID
+STATIC
+MemTBeginWLTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 ByteLane;
+  UINT8 Seed;
+  UINT8 Delay;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  // Assert ODT pins for write leveling
+  NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1);
+
+  // Wait 10 MEMCLKs to allow for ODT signal settling.
+  MemUWait10ns (3, MemPtr);
+
+  IDS_HDT_CONSOLE ("\t\t\tWrtLvTrEn = 1\n");
+  // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
+  NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
+
+  //  Wait 200 MEMCLKs. If executing pass 2, wait 32 MEMCLKs.
+  MemUWait10ns (50, MemPtr);
+
+  //  Program F2x[1, 0]9C_x08[WrtLlTrEn]=0.
+  NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0);
+
+  //  Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
+  //  for the target Dimm and save these values.
+  IDS_HDT_CONSOLE ("\t\t\t  PRE: ");
+  for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) {
+    // This includes ECC as byte 8
+    Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane];
+    Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
+//    IDS_HDT_CONSOLE ("%v1%02x ", Delay);
+    IDS_HDT_CONSOLE ("%02x ", Delay);
+
+    if ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20))) {
+      //
+      // If PRE comes back with more than Seed +/- 0x20, then this is an
+      //   unexpected condition.  Log the condition.
+      //
+      PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader);
+    }
+    if ((NBPtr->IsSupported[WLSeedAdjust]) && (Seed >= 0x60)) {
+      // Recover WrDqsGrossDly:
+      // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross
+      if ((Seed & 0x20) != 0) {
+        // If (SeedGross is odd) then SeedPreGross = 1
+        Delay += (Seed & 0xE0) - 0x20;
+      } else {
+        // If (SeedGross is even) then SeedPreGross = 2
+        Delay += (Seed & 0xE0) - 0x40;
+      }
+    } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
+      IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader));
+      // If seed has gross delay of 0 and PRE has gross delay of 3,
+      // then round the total delay of TxDqs to 0.
+      Delay = 0;
+    }
+    NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
+    NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay;
+//    IDS_HDT_CONSOLE ("%v2%02x ", Delay);
+  }
+#if 0
+  IDS_HDT_CONSOLE ("%v0");
+  IDS_HDT_CONSOLE ("\t\t\tPRE:   %vh1\n");
+  IDS_HDT_CONSOLE ("\t\t\tWrDqs: %vh2\n\n");
+#endif
+    IDS_HDT_CONSOLE ("\n\t\t\tWrDqs: ");
+    for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
+      IDS_HDT_CONSOLE ("%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]);
+    }
+    IDS_HDT_CONSOLE("\n\n");
+
+  // Disable write leveling ODT pins
+  NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0);
+
+  // Wait 10 MEMCLKs to allow for ODT signal settling.
+  MemUWait10ns (3, MemPtr);
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function programs register after Phy assisted training is finish.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTExitPhyAssistedTrainingClient3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFRxPtrInitReq, 1);
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisDllShutdownSR, 1);
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFEnterSelfRef, 1);
+  TechPtr->NBPtr->PollBitField (TechPtr->NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDbeGskMemClkAlignMode, 2);
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFExitSelfRef, 1);
+  TechPtr->NBPtr->PollBitField (TechPtr->NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisDllShutdownSR, 0);
+  return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c
new file mode 100755
index 0000000000..632c1cb160
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mt.c
@@ -0,0 +1,214 @@
+/**
+ * @file
+ *
+ * mt.c
+ *
+ * Common Technology file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is the default return for non-training technology features
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ */
+BOOLEAN
+MemTFeatDef (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the TestFail bit for all CS that fail training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ */
+VOID
+MemTMarkTrainFail (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 Dct;
+  UINT8 ChipSel;
+
+  NBPtr = TechPtr->NBPtr;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    NBPtr->DCTPtr->Timings.CsEnabled &= ~NBPtr->DCTPtr->Timings.CsTrainFail;
+    for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel ++) {
+      if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << ChipSel)) != 0) {
+        NBPtr->SetBitField (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (UINT32)1 << BFTestFail);
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the initial controller environment before training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  S_UINT64 SMsr;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2
+
+  LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);            // HWCR
+  TechPtr->HwcrLo = SMsr.lo;
+  SMsr.lo |= 0x00020000;                  // turn on HWCR.wrap32dis
+  SMsr.lo &= 0xFFFF7FFF;                  // turn off HWCR.SSEDIS
+  LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
+
+  TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn);
+  NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the final controller environment after training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  S_UINT64 SMsr;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg);
+
+  LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo = TechPtr->HwcrLo;
+  LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets all the bytelanes/nibbles to the same delay value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Dly - Delay value to set
+ *
+ */
+
+VOID
+MemTSetDQSDelayAllCSR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dly
+  )
+{
+  UINT8 i;
+
+  for (i = 0; i < TechPtr->MaxByteLanes (); i++) {
+    TechPtr->SetDQSDelayCSR (TechPtr, i, Dly);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c
new file mode 100755
index 0000000000..77094a2ea9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mthdi.c
@@ -0,0 +1,122 @@
+/**
+ * @file
+ *
+ * mthdi.c
+ *
+ * Common technology hardware dram init support functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTHDI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates Hardware based dram initialization for both DCTs
+ *   at the same time.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTDramInitHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  NBPtr->BrdcstSet (NBPtr, BFInitDram, 1);
+  // Phy fence training
+  AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+      NBPtr->PhyFenceTraining (NBPtr);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
new file mode 100755
index 0000000000..7d4f728040
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.c
@@ -0,0 +1,851 @@
+/**
+ * @file
+ *
+ * mttEdgeDetect.c
+ *
+ * DQS R/W position training utilizing Data Eye Edge Detection for optimization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 7359 $ @e \$Date: 2008-08-13 01:53:23 +0800 (Wed, 13 Aug 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "mport.h"
+#include "mttEdgeDetect.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTEDGEDETECT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#define LAST_DELAY    (-128)
+#define INC_DELAY     1
+#define DEC_DELAY     0
+
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Sweep Table For Byte Training without insertion delay
+ *
+*/
+DQS_POS_SWEEP_TABLE SweepTableByte[] =
+{
+  //     Begin  End   Inc/Dec  Step  EndResult Edge
+  {      0x00,  0x1F, INC_DELAY,  4, 0xFFFF,   LEFT_EDGE},  /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS
+  { LAST_DELAY, 0x00, DEC_DELAY, -1, 0xFF00,   LEFT_EDGE},  ///  Then go back down to 0x00 by 1 until all FAIL
+  {      0x1F,  0x00, DEC_DELAY, -4, 0xFFFF,   RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS.
+  { LAST_DELAY, 0x1F, INC_DELAY,  1, 0xFF00,   RIGHT_EDGE}  ///  Then go back up by 1 until all FAIL.
+};
+/**
+ * Sweep Table For Byte Training with insertion delay
+ *
+*/
+DQS_POS_SWEEP_TABLE InsSweepTableByte[] =
+{
+  //     Begin  End   Inc/Dec  Step  EndResult Edge
+  {      0x00, -0x20, DEC_DELAY, -4, 0xFF00, LEFT_EDGE},  /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL
+  { LAST_DELAY, 0x1F, INC_DELAY,  1, 0xFFFF, LEFT_EDGE},  ///  Then go back up to 0x1F by 1 until all PASS
+  {      0x1F,  0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS.
+  { LAST_DELAY, 0x1F, INC_DELAY,  1, 0xFF00, RIGHT_EDGE}  ///  Then go back up by 1 until all FAIL.
+};
+
+BOOLEAN
+STATIC
+MemTTrainDQSRdWrEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+STATIC
+MemTTrainDQSEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+STATIC
+MemTInitTestPatternAddress (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  );
+
+BOOLEAN
+STATIC
+MemTContinueSweep (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  );
+
+BOOLEAN
+STATIC
+MemTSetNextDelay (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  );
+
+UINT8
+STATIC
+MemTScaleDelayVal (
+  IN OUT MEM_TECH_BLOCK *TechPtr,
+  IN INT8 Delay
+  );
+
+VOID
+STATIC
+MemTDataEyeSave (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr,
+  IN       UINT8 ByteLane
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function executes DQS position training for all a Memory channel using
+ *     the Edge Detection algorithm.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+BOOLEAN
+MemTTrainDQSEdgeDetectSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  BOOLEAN Status;
+
+  Status = FALSE;
+  NBPtr = TechPtr->NBPtr;
+  //
+  // Initialize the Pattern
+  //
+  if (AGESA_SUCCESS == NBPtr->TrainingPatternInit (NBPtr)) {
+    //
+    // Start Edge Detection
+    //
+    Status |= MemTTrainDQSRdWrEdgeDetect (TechPtr);
+    //
+    // Finalize the Pattern
+    //
+    Status &= (AGESA_SUCCESS == NBPtr->TrainingPatternFinalize (NBPtr));
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This Executes Read DQS and Write Data Position training on a chip select pair
+ *  using the Edge Detection algorithm.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - No Errors occurred
+ *     @return  FALSE - Errors occurred
+
+ */
+
+BOOLEAN
+STATIC
+MemTTrainDQSRdWrEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8 WrDqDelay;
+  UINT8 Dct;
+  UINT8 CSPerChannel;
+  UINT8 CsPerDelay;
+  UINT8 ChipSel;
+  UINT8 i;
+  BOOLEAN Status;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+  //
+  // Set environment settings before training
+  //
+  IDS_HDT_CONSOLE ("!\nStart Read/Write Data Eye Edge Detection.\n");
+  MemTBeginTraining (TechPtr);
+  //
+  // Do Rd DQS /Wr Data Position training for all Dcts/Chipselects
+  //
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    //
+    // Chip Select Loop
+    //
+    CSPerChannel = NBPtr->CSPerChannel (NBPtr);
+    CsPerDelay = NBPtr->CSPerDelay (NBPtr);
+    for (ChipSel = 0; ChipSel < CSPerChannel; ChipSel = ChipSel + CsPerDelay ) {
+      //
+      // Init Bit Error Masks
+      //
+      LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
+        0xFF,
+        (MAX_BYTELANES_PER_CHANNEL * CsPerDelay),
+        &MemPtr->StdHeader);
+      if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) {
+        TechPtr->ChipSel = ChipSel;
+        IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
+        IDS_HDT_CONSOLE ("\t\t\tIncrease WrDat, Train RdDqs:\n");
+
+        TechPtr->DqsRdWrPosSaved = 0;
+        //
+        // Use a list of Approximate Write Data delay values and train Read DQS Position for
+        // each until a valid Data eye is found.
+        //
+        Status = FALSE;
+        TimesFail = 0;
+        ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) {
+          i = 0;
+          while (NBPtr->GetApproximateWriteDatDelay (NBPtr, i, &WrDqDelay)) {
+            //
+            // Set Write Delay approximation
+            //
+            TechPtr->Direction = DQS_WRITE_DIR;
+            IDS_HDT_CONSOLE ("\n\t\t\tWrite Delay: %02x", WrDqDelay);
+            MemTSetDQSDelayAllCSR (TechPtr, WrDqDelay);
+            //
+            // Attempt Read Training
+            //
+            TechPtr->Direction = DQS_READ_DIR;
+            if (MemTTrainDQSEdgeDetect (TechPtr)) {
+              //
+              // If Read DQS Training was successful, Train Write Data (DQ) Position
+              //
+              TechPtr->DqsRdWrPosSaved = 0;
+              IDS_HDT_CONSOLE ("\n\t\t\tTrain WrDat:\n\n");
+              TechPtr->Direction = DQS_WRITE_DIR;
+              Status = MemTTrainDQSEdgeDetect (TechPtr);
+              break;
+            }
+            i++;
+          }
+        ERROR_HANDLE_RETRAIN_END ((Status == FALSE), TimesFail)
+        }
+        //
+        // If we went through the table, Fail.
+        //
+        if (Status == FALSE) {
+          NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ChipSel;
+          // If the even chip select failed training always fail the odd, if present.
+          if ((ChipSel & 0x01) == 0) {
+            if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << (ChipSel + 1))) {
+              NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << (ChipSel + 1);
+            }
+          }
+          NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader);
+        }
+      } else {
+      //
+      // Clear Bit Error Masks if these CS will not be trained.
+      //
+      LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
+        0x00,
+        (MAX_BYTELANES_PER_CHANNEL * CsPerDelay),
+        &NBPtr->MemPtr->StdHeader);
+      }
+    }
+  }
+  //
+  // Restore environment settings after training
+  //
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE ("End Read/Write Data Eye Edge Detection\n\n");
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function executes DQS position training for both read and write, using
+ *     the Edge Detection Algorithm.  This method searches for the beginning and end
+ *     of the Data Eye with out scanning every DSQ delay value. The following is a
+ *     detailed description of the algorithm:
+ *
+ *     Four-Stage Data Eye Sweep
+ *
+ *     -Search starts at Delay value of 0.
+ *     -Search left in steps of 4/32UI looking for all Byte lanes Passing. Left from zero rolls over to a negative value.
+ *     -Negative values are translated to the high end of the delay range, but using Insertion delay comparison.
+ *     -For each passing byte lane, freeze delay at first passing value, but set mask so next steps will not compare for byte lanes that previously passed
+ *     -Switch to search right in steps of 1/32UI looking for fail.
+ *     -For each lane, starting delay for 1/32 sweep right is first passing delay from 4/32 sweep left.
+ *     -For each failing byte lane, freeze delay at first failing value, but set mask so next steps will not compare for byte lanes that previously failed
+ *     -Search right until all byte lanes have failed
+ *     -For each lane, right edge used by BIOS will be first failing delay value minus 1/32
+
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+*/
+BOOLEAN
+STATIC
+MemTTrainDQSEdgeDetect (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK         *NBPtr;
+  DQS_POS_SWEEP_TABLE  *SweepTablePtr;
+  UINT8                SweepTableSize;
+  SWEEP_INFO           SweepData;
+  BOOLEAN              Status;
+  UINT16               CurrentResult;
+  UINT16               AlignedResult;
+  UINT16               OffsetResult;
+  UINT8                StageIndex;
+  UINT8                CsIndex;
+  UINT8                CsPerDelay;
+  UINT8                i;
+
+  Status = TRUE;
+  //
+  // Initialize Object Pointers
+  //
+  NBPtr = TechPtr->NBPtr;
+  //
+  /// Get Pointer to Sweep Table
+  //
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    SweepTablePtr = InsSweepTableByte;
+    SweepTableSize = GET_SIZE_OF (InsSweepTableByte);
+  } else {
+    SweepTablePtr = SweepTableByte;
+    SweepTableSize = GET_SIZE_OF (SweepTableByte);
+  }
+  //
+  // Get number of CS to train
+  //
+  CsPerDelay = NBPtr->CSPerDelay (NBPtr);
+  //
+  /// Set up the test Pattern, exit if no Memory
+  //
+  if (MemTInitTestPatternAddress (TechPtr, &SweepData) == FALSE) {
+    LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (TechPtr->ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
+      0,
+      (MAX_BYTELANES_PER_CHANNEL * CsPerDelay),
+      &NBPtr->MemPtr->StdHeader);
+    return FALSE;
+  }
+  //
+  // Clear Error Flag
+  //
+  SweepData.Error = FALSE;
+  //
+  /// Process Sweep table, using entries from the table to determine Starting and Ending Delays
+  /// as well as the Step size and criteria for evaluating whether the correct result is found.
+  ///
+  /// Delay values at this level are an abstract range of values which gets scaled to the actual value
+  /// before it is written to the hardware. This allows NB specific code to handle the scaling as a
+  ///  function of frequency or other conditions.
+  //
+  for (StageIndex = 0; (StageIndex < SweepTableSize) && (SweepData.Error == FALSE); StageIndex++) {
+
+    IDS_HDT_CONSOLE ("\t\t\tSTAGE: %d\t", StageIndex);
+    //
+    /// Initialize SweepData variables
+    //
+    SweepData.BeginDelay = SweepTablePtr->BeginDelay;
+    SweepData.EndDelay = SweepTablePtr->EndDelay;
+    SweepData.Step = 0;                                    /// Step Value will be 0 to start.
+    SweepData.EndResult = SweepTablePtr->EndResult;
+    SweepData.Edge = SweepTablePtr->MinMax;
+    SweepData.InsertionDelayMsk = 0;
+    SweepData.ResultFound = 0x0000;
+    //
+    // Set Training Delays Pointer.
+    //
+    if (TechPtr->Direction == DQS_READ_DIR) {
+      SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->RdDqsMaxDlys : NBPtr->ChannelPtr->RdDqsMinDlys);
+    } else {
+      SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->WrDatMaxDlys : NBPtr->ChannelPtr->WrDatMinDlys);
+    };
+    //
+    /// Set initial TrnDelay Values if necessary
+    //
+    IDS_HDT_CONSOLE ("Sweeping %s DQS, %s from ", (TechPtr->Direction == DQS_READ_DIR) ?"Read":"Write", (SweepTablePtr->ScanDir == INC_DELAY) ? "incrementing":"decrementing");
+    if (SweepData.BeginDelay != LAST_DELAY) {
+      IDS_HDT_CONSOLE ("%02x", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.BeginDelay));
+      for (i = 0; i < TechPtr->MaxByteLanes (); i++) {
+        SweepData.TrnDelays[i] = SweepData.BeginDelay;
+      }
+    } else {
+      IDS_HDT_CONSOLE ("Current Delay");
+      SweepData.Step = SweepTablePtr->Step;
+    }
+    IDS_HDT_CONSOLE (" by %02x, until all bytelanes %s.\n\n", (UINT16) MemTScaleDelayVal (TechPtr, ABS (SweepTablePtr->Step)), (SweepData.EndResult == 0xFFFF)?"PASS":"FAIL");
+
+    //-------------------------------------------------------------------
+    //   Sweep DQS Delays
+    //   MemTContinueSweep function returns false to break out of loop.
+    //   There are no other breaks out of this loop.
+    //-------------------------------------------------------------------
+    while (MemTContinueSweep (TechPtr, &SweepData)) {
+
+      IDS_HDT_CONSOLE ("\t\t\t\tDQS Delays   : %02x %02x %02x %02x %02x %02x %02x %02x\n",
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]),
+      (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0])
+       );
+      //
+      /// Set Step Value
+      //
+      SweepData.Step = SweepTablePtr->Step;
+      CurrentResult = 0xFFFF;
+      //
+      /// Chip Select Loop: Test the Pattern for all populated CS that are controlled by the current delay registers
+      //
+      for (CsIndex = 0; CsIndex < CsPerDelay ; CsIndex++, TechPtr->ChipSel++) {
+        if (SweepData.CsAddrValid[CsIndex] == TRUE) {
+          //
+          /// If this is a Write Dqs sweep, Write the pattern now.
+          //
+          if (TechPtr->Direction == DQS_WRITE_DIR) {
+            NBPtr->WritePattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength);
+          }
+          //
+          /// Read the Pattern Back
+          //
+          NBPtr->ReadPattern (NBPtr, TechPtr->TestBufPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength);
+          //
+          /// Compare the Pattern and Merge the results using InsertionDelayMsk
+          //
+          AlignedResult = NBPtr->CompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
+          CurrentResult &= AlignedResult | SweepData.InsertionDelayMsk;
+          if (SweepData.InsertionDelayMsk != 0) {
+            OffsetResult = NBPtr->InsDlyCompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
+            CurrentResult &= (OffsetResult | (~SweepData.InsertionDelayMsk));
+          }
+          //
+          /// Flush the Test Pattern
+          //
+          NBPtr->FlushPattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength);
+        }
+      } /// End Chip Select Loop
+      TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
+      IDS_HDT_CONSOLE ("\t\t\t\tResult       :  %c  %c  %c  %c  %c  %c  %c  %c \n",
+        (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (4))) ? ' ':(CurrentResult & ((UINT16) 1 << (4))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (3))) ? ' ':(CurrentResult & ((UINT16) 1 << (3))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.',
+        (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.'
+        );
+      //
+      /// Merge current result into cumulative result and make it positive.
+      //
+      SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult);
+
+      IDS_HDT_CONSOLE ("\t\t\t\tResultFound  :  %c  %c  %c  %c  %c  %c  %c  %c \n\n",
+        (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (6))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (5))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (4))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (3))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ',
+        (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' '
+        );
+    } /// End of Delay Sweep
+    //
+    /// Place Final delay values at last passing delay.
+    //
+    if (SweepData.EndResult == 0xFF00) {
+      if (SweepData.ResultFound == 0xFFFF) {
+        if ( ABS (SweepData.Step) == 1) {
+          for (i = 0; i < TechPtr->MaxByteLanes (); i++) {
+            SweepData.TrnDelays[i] = SweepData.TrnDelays[i] - SweepData.Step;
+          }
+        }
+      }
+    }
+    //
+    // Update Pointer to Sweep Table
+    //
+    SweepTablePtr++;
+  }///End of Edge Detect loop
+  //
+  /// If No Errors are detected, Calculate Data Eye Width and Center
+  //
+  if (SweepData.Error == FALSE) {
+    IDS_HDT_CONSOLE ("\t\tData Eye Results:\n\n");
+    IDS_HDT_CONSOLE ("\t\tByte     Left     Right\n");
+    IDS_HDT_CONSOLE ("\t\tLane     Edge     Edge     Width     Center\n");
+    for (i = 0; i < TechPtr->MaxByteLanes (); i++) {
+      IDS_HDT_CONSOLE ("\t\t %0d", i);
+      MemTDataEyeSave (TechPtr, &SweepData, i);
+      IDS_HDT_CONSOLE ("\n");
+      if (SweepData.Error == TRUE) {
+        Status = FALSE;
+      }
+    }
+  } else {
+    Status = FALSE;
+    IDS_HDT_CONSOLE ("\t\t--DATA EYE NOT FOUND--\n\n");
+  }
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     Initialize the Test Pattern Address for two chip selects and, if this
+ *     is a Write Data Eye, write the initial test pattern.
+ *
+ *     Test Address is stored in the Sweep info struct.  If Memory is not present
+ *     then return with False.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *
+ *     @return  BOOLEAN
+ *              TRUE  - Memory is present
+ *              FALSE - No memory present on this Chip Select pair.
+ *
+**
+ */
+BOOLEAN
+STATIC
+MemTInitTestPatternAddress (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT8 ChipSel;
+  UINT8 CsPerDelay;
+  UINT8 CsIndex;
+  BOOLEAN BanksPresent;
+
+  NBPtr = TechPtr->NBPtr;
+  BanksPresent = FALSE;
+  CsPerDelay = NBPtr->CSPerDelay (NBPtr);
+  ChipSel = TechPtr->ChipSel;
+  for (CsIndex = 0; CsIndex < CsPerDelay; ChipSel++, CsIndex++) {
+    ASSERT (CsIndex < MAX_CS_PER_CHANNEL);
+    //
+    /// If memory is present on this cs, get the test addr
+    //
+    if (NBPtr->GetSysAddr (NBPtr, ChipSel, &(SweepPtr->TestAddrRJ16[CsIndex]))) {
+      BanksPresent = TRUE;
+      SweepPtr->CsAddrValid[CsIndex] = TRUE;
+      //
+      /// If this is a Read Dqs sweep, Write the pattern now.
+      //
+      if (TechPtr->Direction == DQS_READ_DIR) {
+        IDS_HDT_CONSOLE ("\tTestAddr: %lx0000\n", SweepPtr->TestAddrRJ16[CsIndex]);
+        NBPtr->WritePattern (NBPtr, SweepPtr->TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength);
+      }
+    } else {
+      SweepPtr->CsAddrValid[CsIndex] = FALSE;
+    }
+  }
+  //
+  /// return FALSE if no ChipSelects present.
+  //
+  return BanksPresent;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *     Test Conditions for exiting the training loop, set the next delay value,
+ *     and return status
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *
+ *     @return  BOOLEAN
+ *              TRUE  - Continue to test with next delay setting
+ *              FALSE - Exit training loop.  Either the result has been found or
+ *                      end of delay range has been reached.
+*/
+BOOLEAN
+STATIC
+MemTContinueSweep (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  )
+{
+  BOOLEAN Status;
+  Status = FALSE;
+  if (SweepPtr->ResultFound != 0xFFFF) {
+    Status = MemTSetNextDelay (TechPtr, SweepPtr);
+  }
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the next delay value for each bytelane that needs to
+ *      be advanced.  It checks the bounds of the delay to see if we are at the
+ *      end of the range.  If we are to close to advance a whole step value, but
+ *      not at the boundary, then we set the delay to the boundary.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *
+ */
+
+BOOLEAN
+STATIC
+MemTSetNextDelay (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr
+  )
+{
+  UINT8 i;
+  //
+  ///< Loop through bytelanes
+  //
+  for (i = 0; i < TechPtr->MaxByteLanes (); i++) {
+    //
+    /// Skip Bytelanes that have already reached the desired result
+    //
+    if ( (SweepPtr->ResultFound  & ((UINT16)1 << i)) == 0) {
+      //
+      /// If a bytelane has reached the end, flag an error and exit
+      //
+      if (SweepPtr->TrnDelays[i] == SweepPtr->EndDelay) {
+        if ((SweepPtr->EndResult & ((UINT16) (1 << i))) != 0) {
+          TechPtr->NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE;
+          SweepPtr->Error = TRUE;
+        }
+        return FALSE;
+      }
+      //
+      /// If the Current delay value is less than a step away from EndDelay,
+      //
+      if ( ABS (SweepPtr->EndDelay - SweepPtr->TrnDelays[i]) < ABS (SweepPtr->Step)) {
+        /// set to EndDelay.
+        //
+        SweepPtr->TrnDelays[i] = SweepPtr->EndDelay;
+      } else {
+        //
+        /// Otherwise, add the step value to it
+        SweepPtr->TrnDelays[i] = SweepPtr->TrnDelays[i] + SweepPtr->Step;
+      }
+      //
+      /// Set InsertionDelayMsk bit if Delay < 0 for this bytelane
+      //
+      if (SweepPtr->TrnDelays[i] < 0) {
+        SweepPtr->InsertionDelayMsk |= ((UINT16) 1 << i);
+      } else {
+        SweepPtr->InsertionDelayMsk &= ~((UINT16) 1 << i);
+      }
+      //
+      /// Write the scaled value to the Delay Register
+      //
+      TechPtr->SetDQSDelayCSR (TechPtr, i, MemTScaleDelayVal (TechPtr, SweepPtr->TrnDelays[i]));
+    }
+  }
+  return TRUE;
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function accepts a delay value in 32nd of a UI and converts it to an
+ *     actual register value, taking into consideration NB type, rd/wr,
+ *     and frequency.
+ *
+ *     Delay = (Min + (Delay * ( (Max - Min) / TRN_DELAY_MAX) )) & Mask
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       *Delay     - INT8 of delay value;
+ *
+ *     @return  UINT8 of the adjusted delay value
+*/
+UINT8
+STATIC
+MemTScaleDelayVal (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       INT8 Delay
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  TRN_DLY_PARMS Parms;
+  TRN_DLY_TYPE DelayType;
+  UINT8 NewDelay;
+  INT8 Factor;
+  INT8 ScaledDelay;
+
+  NBPtr = TechPtr->NBPtr;
+  //
+  // Determine Delay Type, Get Delay Parameters, and return scaled Delay value
+  //
+  DelayType = (TechPtr->Direction == DQS_WRITE_DIR) ? AccessWrDatDly : AccessRdDqsDly;
+  NBPtr->GetTrainDlyParms (NBPtr, DelayType, &Parms);
+  Factor = ((Parms.Max - Parms.Min) / TRN_DELAY_MAX);
+  ScaledDelay = Delay * Factor;
+  NewDelay = (Parms.Min + ScaledDelay) & Parms.Mask;
+  return NewDelay;
+}
+
+
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function calculates the Center of the Data eye for the specified byte lane
+ *       and stores its DQS Delay value for reference.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *SweepPtr -  Pointer to SWEEP_INFO structure.
+ *     @param[in]       ByteLane  -  Bytelane number being targeted
+ *
+ */
+VOID
+STATIC
+MemTDataEyeSave (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   SWEEP_INFO *SweepPtr,
+  IN       UINT8 ByteLane
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 EyeCenter;
+  UINT8 DlyMin;
+  UINT8 DlyMax;
+  UINT8 EyeWidth;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChanPtr;
+
+  ASSERT (ByteLane < TechPtr->MaxByteLanes ());
+  NBPtr = TechPtr->NBPtr;
+  ChanPtr = NBPtr->ChannelPtr;
+
+  //
+  // Calculate Data Eye edges, Width, and Center in real terms.
+  //
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMinDlys[ByteLane]);
+    DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMaxDlys[ByteLane]);
+    EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->RdDqsMaxDlys[ByteLane] - ChanPtr->RdDqsMinDlys[ByteLane]));
+    EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->RdDqsMinDlys[ByteLane] + ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2));
+    ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin;
+    ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax;
+  } else {
+    DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMinDlys[ByteLane]);
+    DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMaxDlys[ByteLane]);
+    EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->WrDatMaxDlys[ByteLane] - ChanPtr->WrDatMinDlys[ByteLane]));
+    EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->WrDatMinDlys[ByteLane] + ChanPtr->WrDatMaxDlys[ByteLane] + 1) / 2));
+    ChanPtr->WrDatMinDlys[ByteLane] = DlyMin;
+    ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax;
+  }
+  //
+  // Flag error for small window.
+  //
+  if (EyeWidth < MemTScaleDelayVal (TechPtr, NBPtr->MinDataEyeWidth (NBPtr))) {
+    NBPtr->MCTPtr->ErrStatus[EsbSmallDqs] = TRUE;
+    SweepPtr->Error = TRUE;
+  }
+
+  IDS_HDT_CONSOLE ("        %02x       %02x       %02x         %02x", DlyMin, DlyMax, EyeWidth, EyeCenter);
+
+  TechPtr->SetDQSDelayCSR (TechPtr, ByteLane, EyeCenter);
+  TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane;
+  TechPtr->DqsRdWrPosSaved |= 0xFF00;
+
+  Dimm = (TechPtr->ChipSel / 2) * TechPtr->DlyTableWidth () + ByteLane;
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    ChanPtr->RdDqsDlys[Dimm] = EyeCenter;
+  } else {
+    ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm];
+  }
+ }
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h
new file mode 100755
index 0000000000..f877d00ae1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttEdgeDetect.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * mttEdgeDetect.h
+ *
+ * Technology Common Training Header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTTEDGEDETECT_H_
+#define _MTTEDGEDETECT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define ABS(X) (((X)<0)?(-(X)):(X))   /// Absolute Value Macro
+
+#define SCAN_LEFT       0            ///<  Scan Down
+#define SCAN_RIGHT      1            ///<  Scan Up
+#define LEFT_EDGE       0            ///<  searching for the left edge
+#define RIGHT_EDGE      1            ///<  searching for the right edge
+
+#define SweepStages     4
+#define TRN_DELAY_MAX   31           ///<  Max Virtual delay value for DQS Position Training
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ *  Sweep Table Structure. ROM based table defining parameters for DQS position
+ *  training delay sweep.
+*/
+typedef struct {
+  INT8    BeginDelay;          ///<  Starting Delay Value
+  INT8    EndDelay;            ///<  Ending Delay Value
+  BOOLEAN ScanDir;             ///<  Scan Direction.  0 = down, 1 = up
+  INT8    Step;                ///<  Amount to increment delay value
+  UINT16  EndResult;           ///<  Result value to stop sweeping (to compare with failure mask)
+  BOOLEAN MinMax;              ///<  Flag indicating lower (left edge) or higher(right edge)
+} DQS_POS_SWEEP_TABLE;
+
+/**
+ * Sweep Information Struct - Used to track data through the DQS Delay Sweep
+ *
+*/
+typedef struct _SWEEP_INFO {
+  BOOLEAN Error;                               ///< Indicates an Error has been found
+  UINT32  TestAddrRJ16[MAX_CS_PER_CHANNEL];    ///< System address of chipselects RJ 16 bits (Addr[47:16])
+  BOOLEAN CsAddrValid[MAX_CS_PER_CHANNEL];     ///< Indicates which chipselects to test
+  INT8    BeginDelay;                          ///< Beginning Delay value (Virtual)
+  INT8    EndDelay;                            ///< Ending Delay value (Virtual)
+  INT8    Step;                                ///< Amount to Inc or Dec Virtual Delay value
+  BOOLEAN Edge;                                ///< Left or right edge (0 = LEFT, 1= RIGHT)
+  UINT16  EndResult;                           ///< Result value that will stop a Dqs Sweep
+  UINT16  InsertionDelayMsk;                   ///< Mask of Byte Lanes that should use ins. dly. comparison
+  UINT16  LaneMsk;                             ///< Mask indicating byte lanes to update
+  UINT16  ResultFound;                         ///< Mask indicating byte lanes where desired result was found on a sweep
+  INT8    *TrnDelays;                          ///< Delay Values for each byte (Virtual).  Points into the delay values
+} SWEEP_INFO;                                  ///< stored in the CH_DEF_STRUCT.
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#endif  /* _MTTEDGEDETECT_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c
new file mode 100755
index 0000000000..c0b787b572
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttdimbt.c
@@ -0,0 +1,1298 @@
+/**
+ * @file
+ *
+ * mttdimmbt.c
+ *
+ * Technology Dimm Based Training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTDIMBT_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_BYTELANES 8   /* 8 byte lanes */
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTInitDqsPos4RcvrEnByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+STATIC
+MemTSetRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  );
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+BOOLEAN
+STATIC
+MemTSaveRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  );
+
+VOID
+STATIC
+MemTResetDctWrPtrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+UINT16
+STATIC
+MemTCompare1ClPatternByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[]
+  );
+
+VOID
+STATIC
+MemTSkipChipSelPass1Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  );
+
+VOID
+STATIC
+MemTSkipChipSelPass2Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  );
+
+UINT8
+STATIC
+MemTMaxByteLanesByte (VOID);
+
+UINT8
+STATIC
+MemTDlyTableWidthByte (VOID);
+
+VOID
+STATIC
+MemTSetDqsDelayCsrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 Dly
+  );
+
+VOID
+STATIC
+MemTDqsWindowSaveByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 DlyMin,
+  IN       UINT8 DlyMax
+  );
+
+BOOLEAN
+STATIC
+MemTFindMaxRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  );
+
+UINT16
+STATIC
+MemTCompare1ClPatternOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT8 Side,
+  IN       UINT8 Receiver,
+  IN       BOOLEAN Side1En
+  );
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+VOID
+STATIC
+MemTSetRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  );
+
+VOID
+STATIC
+MemTLoadInitialRcvEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemTFindMaxRcvrEnDlyRdDqsDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  );
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function enables byte based training if called
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemTDimmByteTrainInit (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 DctCount;
+  UINT8 ChannelCount;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  TechPtr->InitDQSPos4RcvrEn = MemTInitDqsPos4RcvrEnByte;
+  TechPtr->SetRcvrEnDly = MemTSetRcvrEnDlyByte;
+  TechPtr->LoadRcvrEnDly = MemTLoadRcvrEnDlyByte;
+  TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByte;
+  TechPtr->SaveRcvrEnDlyFilter = MemTSaveRcvrEnDlyByteFilterOpt;
+  TechPtr->ResetDCTWrPtr = MemTResetDctWrPtrByte;
+  TechPtr->Compare1ClPattern = MemTCompare1ClPatternByte;
+  TechPtr->SkipChipSelPass1 = MemTSkipChipSelPass1Byte;
+  TechPtr->SkipChipSelPass2 = MemTSkipChipSelPass2Byte;
+  TechPtr->MaxByteLanes = MemTMaxByteLanesByte;
+  TechPtr->DlyTableWidth = MemTDlyTableWidthByte;
+  TechPtr->SetDQSDelayCSR = MemTSetDqsDelayCsrByte;
+  TechPtr->DQSWindowSave = MemTDqsWindowSaveByte;
+  TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyByte;
+  TechPtr->Compare1ClPatternOpt = MemTCompare1ClPatternOptByte;
+  TechPtr->LoadRcvrEnDlyOpt = MemTLoadRcvrEnDlyOptByte;
+  TechPtr->SetRcvrEnDlyOpt = MemTSetRcvrEnDlyOptByte;
+  TechPtr->InitializeVariablesOpt = MemTInitializeVariablesOptByte;
+  TechPtr->GetMaxValueOpt = MemTGetMaxValueOptByte;
+  TechPtr->SetSweepErrorOpt = MemTSetSweepErrorOptByte;
+  TechPtr->CheckRcvrEnDlyLimitOpt = MemTCheckRcvrEnDlyLimitOptByte;
+  TechPtr->LoadInitialRcvrEnDlyOpt = MemTLoadInitialRcvEnDlyOptByte;
+  // Dynamically allocate buffers for storing trained timings.
+  DctCount = MCTPtr->DctCount;
+  ChannelCount = MCTPtr->DctData[0].ChannelCount;
+  AllocHeapParams.RequestedBufferSize = ((DctCount * ChannelCount) *
+                                         ((MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES) +
+                                          (MAX_DELAYS * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
+                                          )
+                                         );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, MCTPtr->NodeId, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader) == AGESA_SUCCESS) {
+    for (Dct = 0; Dct < DctCount; Dct++) {
+      for (Channel = 0; Channel < ChannelCount; Channel++) {
+        MCTPtr->DctData[Dct].ChData[Channel].RowCount = MAX_DIMMS;
+        MCTPtr->DctData[Dct].ChData[Channel].ColumnCount = MAX_DELAYS;
+
+        MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+        MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+        MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = AllocHeapParams.BufferPtr;
+        AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS);
+      }
+    }
+  } else {
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+    SetMemError (AGESA_FATAL, MCTPtr);
+    ASSERT(FALSE);  // Could not dynamically allocate buffers for storing trained timings
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function initializes the DQS Positions in preparation for Receiver Enable Training.
+ *  Write Position is no delay, Read Position is 1/2 Memclock delay
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemTInitDqsPos4RcvrEnByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dimm;
+  UINT8 ByteLane;
+  UINT8 WrDqs;
+
+  for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+    for (ByteLane = 0; ByteLane < MAX_DELAYS; ByteLane++) {
+      WrDqs = TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane];
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs);
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), 0x3F);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ */
+
+VOID
+STATIC
+MemTSetRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  )
+{
+  UINT8 ByteLane;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function loads the DqsRcvEnDly from saved data and program to additional index
+ *  for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *
+ */
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT8 Dimm;
+  UINT16 Saved;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Dimm = Receiver >> 1;
+  Saved = TechPtr->DqsRcvEnSaved;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if (Saved & 1) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
+      ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]);
+    }
+    Saved >>= 1;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function saves passing DqsRcvEnDly values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       CmpResultRank0 - compare result for Rank 0
+ *     @param[in]       CmpResultRank1 - compare result for Rank 1
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+ */
+
+BOOLEAN
+STATIC
+MemTSaveRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Saved;
+  UINT8 Mask;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
+
+  Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@attention - false passes filter (subject to be replaced with a better solution)
+  Dimm = Receiver >> 1;
+  Mask = 1;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if (Passed & Mask) {
+      if (!(Saved & Mask)) {
+        ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20;     // @attention -1 pass only
+        IDS_HDT_CONSOLE ("\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
+      }
+      Saved |= Mask;
+    }
+    Mask <<= 1;
+  }
+  TechPtr->DqsRcvEnSaved = Saved;
+
+  if (Saved == 0xFF) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function performs a filtering functionality and saves passing DqsRcvEnDly
+ *  values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       CmpResultRank0 - compare result for Rank 0
+ *     @param[in]       CmpResultRank1 - compare result for Rank 1
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+ */
+
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilter (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Saved;
+  UINT8 Mask;
+  UINT8 Dimm;
+  UINT8 MaxFilterDly;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_DCT_CACHE *DctCachePtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  DctCachePtr = TechPtr->NBPtr->DctCachePtr;
+
+  MaxFilterDly = TechPtr->MaxFilterDly;
+  Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
+
+  Dimm = Receiver >> 1;
+  Saved = (UINT8) TechPtr->DqsRcvEnSaved;
+  Mask = 1;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if ((Passed & Mask) != 0) {
+      DctCachePtr->RcvEnDlyCounts [i] += 1;
+      if ((Saved & Mask) == 0) {
+        ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20;
+        Saved |= Mask;
+        IDS_HDT_CONSOLE ("\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
+      }
+    } else {
+      if (DctCachePtr->RcvEnDlyCounts [i] <= MaxFilterDly) {
+        DctCachePtr->RcvEnDlyCounts [i] = 0;
+        Saved &= ~Mask;
+      }
+    }
+    Mask <<= 1;
+  }
+
+  //-----------------------
+  TechPtr->DqsRcvEnSaved = (UINT16) Saved;
+
+  Saved = 0;
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    if (DctCachePtr->RcvEnDlyCounts [i] >= MaxFilterDly) {
+      Saved |= (UINT8) 1 << i;
+    }
+  }
+
+  if (Saved == 0xFF) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and return a pass/fail bitmap
+ *       for 8 Bytes
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *
+ *     @return  PASS - Bit map of results of comparison
+ */
+
+UINT16
+STATIC
+MemTCompare1ClPatternByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[]
+  )
+{
+  UINT16 i;
+  UINT16 j;
+  UINT16 Pass;
+  DIE_STRUCT *MCTPtr;
+
+  MCTPtr = TechPtr->NBPtr->MCTPtr;
+  if (MCTPtr->GangedMode && MCTPtr->Dct) {
+    j = 8;
+  } else {
+    j = 0;
+  }
+
+#if 0
+  Pass = 0xFFFF;
+  IDS_HDT_CONSOLE ("%v1 -");
+  IDS_HDT_CONSOLE ("%v2 -");
+  IDS_HDT_CONSOLE ("%v3 -");
+  for (i = 0; i < 8; i++) {
+    if (Buffer[j] != Pattern[j]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (j % 8));    // clear bit n
+    }
+    IDS_HDT_CONSOLE ("%v1  %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
+    IDS_HDT_CONSOLE ("%v2 %02x", Buffer[j]);
+    IDS_HDT_CONSOLE ("%v3 %02x", Pattern[j]);
+    j++;
+  }
+#endif
+    Pass = 0xFFFF;
+    IDS_HDT_CONSOLE ("\n\t\t\tPass/Fail -");
+    for (i = 0; i < 8; i++, j++) { 
+      if (Buffer[j] != Pattern[j]) {
+        // if bytelane n fails 
+        Pass &= ~((UINT16)1 << (j % 8));    // clear bit n
+      }
+      IDS_HDT_CONSOLE ("  %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
+    }
+    IDS_HDT_CONSOLE ("\n\t\t\t Measured -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (" %02x", Buffer[j]);
+    }
+    IDS_HDT_CONSOLE ("\n\t\t\t Expected -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (" %02x", Pattern[j]);
+    }
+    IDS_HDT_CONSOLE ("\n\n");
+
+  return Pass;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       The function resets the DCT input buffer write pointer.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver - Chip select
+ *
+ */
+
+VOID
+STATIC
+MemTResetDctWrPtrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT16 RcvEnDly;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  for (i = 0; i < MAX_BYTELANES; i++) {
+    RcvEnDly = (UINT16) TechPtr->NBPtr->GetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i));
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i), RcvEnDly);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function skips odd chip select if training at 800MT or above.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       *ChipSelPtr - Pointer to variable contains Chip select index
+ *
+ */
+
+VOID
+STATIC
+MemTSkipChipSelPass1Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  // if the even chip select failed training, need to set CsTrainFail for odd chip select if present.
+  if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ((*ChipSelPtr) + 1))) {
+    if (NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << *ChipSelPtr)) {
+      NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((*ChipSelPtr) + 1);
+      NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader);
+    }
+  }
+  (*ChipSelPtr)++;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  MemTSkipChipSelPass2Byte:
+ *
+ *       This function skips odd chip select if training at 800MT or above.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in,out]   *ChipSelPtr - Pointer to variable contains Chip select index
+ *
+ */
+
+VOID
+STATIC
+MemTSkipChipSelPass2Byte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   UINT8 *ChipSelPtr
+  )
+{
+  if (*ChipSelPtr & 1) {
+    *ChipSelPtr = MAX_CS_PER_CHANNEL;    // skip all successions
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function determines the maximum number of byte lanes
+ *
+ *     @return  Max number of Bytelanes
+ */
+
+UINT8
+STATIC
+MemTMaxByteLanesByte (VOID)
+{
+  return MAX_BYTELANES;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
+ *
+ *     @return  Delay table width in bytes
+ */
+
+UINT8
+STATIC
+MemTDlyTableWidthByte (VOID)
+{
+  return MAX_DELAYS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function writes the Delay value to a certain byte lane
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       ByteLane  -  Bytelane number being targeted
+ *     @param[in]       Dly - Delay value
+ *
+ */
+
+VOID
+STATIC
+MemTSetDqsDelayCsrByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 Dly
+  )
+{
+  UINT8 Reg;
+  UINT8 Dimm;
+
+  ASSERT (ByteLane <= MAX_BYTELANES);
+
+  if (!(TechPtr->DqsRdWrPosSaved & ((UINT8)1 << ByteLane))) {
+    Dimm = (TechPtr->ChipSel >> 1);
+
+    if (TechPtr->Direction == DQS_WRITE_DIR) {
+      Dly = Dly + ((UINT8) TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]);
+      Reg = AccessWrDatDly;
+    } else {
+      Reg = AccessRdDqsDly;
+    }
+
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, Reg, DIMM_BYTE_ACCESS (Dimm, ByteLane), Dly);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function programs the trained DQS delay for the specified byte lane
+ *       and stores its DQS window for reference.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       ByteLane  -  Bytelane number being targeted
+ *     @param[in]       DlyMin - Minimum delay value
+ *     @param[in]       DlyMax- Maximum delay value
+ *
+ */
+
+VOID
+STATIC
+MemTDqsWindowSaveByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ByteLane,
+  IN       UINT8 DlyMin,
+  IN       UINT8 DlyMax
+  )
+{
+  UINT8 DqsDelay;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChanPtr;
+
+  ASSERT (ByteLane <= MAX_BYTELANES);
+  ChanPtr = TechPtr->NBPtr->ChannelPtr;
+
+  DqsDelay = ((DlyMin + DlyMax + 1) / 2) & 0x3F;
+  MemTSetDqsDelayCsrByte (TechPtr, ByteLane, DqsDelay);
+  TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane;
+  TechPtr->DqsRdWrPosSaved |= 0xFF00;
+
+  Dimm = (TechPtr->ChipSel / 2) * MAX_DELAYS + ByteLane;
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    ChanPtr->RdDqsDlys[Dimm] = DqsDelay;
+  } else {
+    ChanPtr->WrDatDlys[Dimm] = DqsDelay + ChanPtr->WrDqsDlys[Dimm];
+  }
+
+  if (TechPtr->Direction == DQS_READ_DIR) {
+    ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin;
+    ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax;
+  } else {
+    ChanPtr->WrDatMinDlys[ByteLane] = DlyMin;
+    ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax;
+  }
+
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function finds the DIMM that has the largest receiver enable delay.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[out]      *ChipSel   - Pointer to the Chip select that has the largest receiver enable delay.
+ *
+ *     @return   TRUE - A chip select can be found.
+ *     @return   FALSE - A chip select cannot be found.
+ */
+
+BOOLEAN
+STATIC
+MemTFindMaxRcvrEnDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  )
+{
+  UINT8  Dimm;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 MaxDly;
+  UINT8  MaxDlyDimm;
+  BOOLEAN RetVal;
+
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  RetVal = FALSE;
+  MaxDly = 0;
+  MaxDlyDimm = 0;
+  for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+    if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) {
+      // Only choose the dimm that does not fail training
+      for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+        RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane];
+        if (RcvEnDly > MaxDly) {
+          MaxDly = RcvEnDly;
+          MaxDlyDimm = Dimm;
+          RetVal = TRUE;
+        }
+      }
+    }
+  }
+
+  if (NBPtr->MCTPtr->Status[Sb128bitmode] != 0) {
+    //The RcvrEnDlys of DCT1 DIMMs should also be considered while ganging.
+    NBPtr->SwitchDCT (NBPtr, 1);
+    ChannelPtr = NBPtr->ChannelPtr;
+    for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+      for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+        RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane];
+        if (RcvEnDly > MaxDly) {
+          MaxDly = RcvEnDly;
+          MaxDlyDimm = Dimm;
+        }
+      }
+    }
+    NBPtr->SwitchDCT (NBPtr, 0);
+  }
+
+  TechPtr->MaxDlyForMaxRdLat = MaxDly;
+  *ChipSel = (MaxDlyDimm * 2);
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[out]      *ChipSel   - Pointer to the Chip select that has the largest receiver enable delay
+ *                                   + Read DQS Delay.
+ *
+ *     @return   TRUE - A chip select can be found.
+ *     @return   FALSE - A chip select cannot be found.
+ */
+
+BOOLEAN
+MemTFindMaxRcvrEnDlyRdDqsDlyByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+     OUT   UINT8 *ChipSel
+  )
+{
+  UINT8  Dimm;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 RdDqsDly;
+  UINT16 TotalDly;
+  UINT16 MaxDly;
+  UINT8  MaxDlyDimm;
+  BOOLEAN RetVal;
+
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  RetVal = FALSE;
+  MaxDly = 0;
+  MaxDlyDimm = 0;
+  for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+    if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) {
+      // Only choose the dimm that does not fail training
+      for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
+        RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane];
+        // Before Dqs Position Training, this value is 0. So the maximum value for
+        // RdDqsDly needs to be added later when calculating the MaxRdLatency value
+        // after RcvEnDly training but before DQS Position Training.
+        RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * MAX_DELAYS + ByteLane];
+        TotalDly = RcvEnDly + (RdDqsDly >> 1);
+        if (TotalDly > MaxDly) {
+          MaxDly = TotalDly;
+          MaxDlyDimm = Dimm;
+          RetVal = TRUE;
+        }
+      }
+    }
+  }
+
+  TechPtr->MaxDlyForMaxRdLat = MaxDly;
+  *ChipSel = (MaxDlyDimm * 2);
+  return RetVal;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and return a pass/fail bitmap
+ *       for 8 Bytes for optimized receiver enable training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in]       Side - current side being targeted
+ *     @param[in]       Receiver - Current receiver value
+ *     @param[in]       Side1En - Indicates if the second side of the DIMM is being used
+ *     @return  PASS - Bit map of results of comparison
+ */
+
+UINT16
+STATIC
+MemTCompare1ClPatternOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT8 Side,
+  IN       UINT8 Receiver,
+  IN       BOOLEAN  Side1En
+  )
+{
+  UINT16 i;
+  UINT16 j;
+  UINT16 Pass;
+  DIE_STRUCT *MCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  MCTPtr = TechPtr->NBPtr->MCTPtr;
+
+  if (MCTPtr->GangedMode && MCTPtr->Dct) {
+    j = 8;
+  } else {
+    j = 0;
+  }
+
+  Pass = 0xFFFF;
+#if 0
+  IDS_HDT_CONSOLE ("%v1 -");
+  IDS_HDT_CONSOLE ("%v2 -");
+  IDS_HDT_CONSOLE ("%v3 -");
+  IDS_HDT_CONSOLE ("%v4 -");
+#endif
+  IDS_HDT_CONSOLE ("\t\t\tDelay[BL] -");
+  for (i = 0; i < 8; i++) {
+//    IDS_HDT_CONSOLE ("%v1 %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF);
+//    IDS_HDT_CONSOLE ("%v2  %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
+//    IDS_HDT_CONSOLE ("%v3 %02x", Buffer[j]);
+//    IDS_HDT_CONSOLE ("%v4 %02x", Pattern[j]);
+    IDS_HDT_CONSOLE (" %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF);
+    if (Buffer[j] != Pattern[j]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16)1 << (j % 8));    // clear bit n
+      TechPtr->DqsRcvEnFirstPassValOpt[i] = 0;
+      TechPtr->GetFirstPassValOpt[i] = FALSE;
+      TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
+      TechPtr->DqsRcvEnSavedOpt[i] = FALSE;
+      if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) {
+        if (Side == ((Side1En ? 4 : 2) - 1)) {
+          TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT;
+        }
+      }
+    } else {
+      if (TechPtr->FilterSidePassCountOpt[i] == ((Side1En ? 4 : 2) - 1)) {
+        //Only apply filter if all sides have passed
+        if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) {
+          if (TechPtr->GetFirstPassValOpt[i] == FALSE) {
+            // This is the first Pass, mark the start of filter check
+            TechPtr->DqsRcvEnFirstPassValOpt[i] = TechPtr->RcvrEnDlyOpt[i];
+            TechPtr->GetFirstPassValOpt[i] = TRUE;
+            TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
+            TechPtr->RcvrEnDlyOpt[i]++;
+          } else {
+            if ((TechPtr->RcvrEnDlyOpt[i] - TechPtr->DqsRcvEnFirstPassValOpt[i]) < FILTER_WINDOW_SIZE) {
+              if (TechPtr->IncBy1ForNextCountOpt[i] == FALSE) {
+                TechPtr->RcvrEnDlyOpt[i] += FILTER_SECOND_STAGE_COUNT;
+                TechPtr->IncBy1ForNextCountOpt[i] = TRUE;
+              } else {
+                TechPtr->RcvrEnDlyOpt[i]++;
+                TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
+              }
+            } else {
+              // End sweep and add offset to first pass
+              TechPtr->MaxRcvrEnDlyBlOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i];
+              TechPtr->RcvrEnDlyOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i] + FILTER_OFFSET_VALUE;
+              TechPtr->FilterStatusOpt[i] = DONE_FILTER;
+              TechPtr->FilterCountOpt++;
+            }
+          }
+        } else {
+          TechPtr->FilterSidePassCountOpt[i]++;
+        }
+      } else {
+        if (TechPtr->GetFirstPassValOpt[i] == FALSE) {
+          if (Side == ((Side1En ? 4 : 2) - 1)) {
+            TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT;
+          }
+        }
+        TechPtr->FilterSidePassCountOpt[i]++;
+      }
+      TechPtr->DqsRcvEnSavedOpt[i] = TRUE;
+      ChannelPtr->RcvEnDlys[(Receiver >> 1) * MAX_DELAYS + i] = TechPtr->RcvrEnDlyOpt[i];
+    }
+    if (Side == ((Side1En ? 4 : 2) - 1)) {
+      TechPtr->FilterSidePassCountOpt[i] = 0;
+    }
+    if (TechPtr->RcvrEnDlyOpt[i] >= TechPtr->RcvrEnDlyLimitOpt[i]) {
+      TechPtr->FilterCountOpt++;
+    }
+
+    j++;
+  }
+    IDS_HDT_CONSOLE ("\n\t\t\tPass/Fail -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE ("  %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
+    }
+    IDS_HDT_CONSOLE ("\n\t\t\t Measured -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (" %02x", Buffer[j]);
+    }
+    IDS_HDT_CONSOLE ("\n\t\t\t Expected -");
+    for (i = 0, j -= 8; i < 8; i++, j++) {
+      IDS_HDT_CONSOLE (" %02x", Pattern[j]);
+    }
+    IDS_HDT_CONSOLE ("\n\n");
+
+  return Pass;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *  This function initializes variables for optimized training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID
+MemTInitializeVariablesOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ByteLane;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    TechPtr->RcvrEnDlyLimitOpt[ByteLane] = FILTER_MAX_REC_EN_DLY_VALUE;      // @attention - limit depends on proc type
+    TechPtr->DqsRcvEnSavedOpt[ByteLane] = FALSE;
+    TechPtr->RcvrEnDlyOpt[ByteLane] = FILTER_NEW_RECEIVER_START_VALUE;
+    TechPtr->GetFirstPassValOpt[ByteLane] = FALSE;
+    TechPtr->DqsRcvEnFirstPassValOpt[ByteLane] = 0;
+    TechPtr->RevertPassValOpt[ByteLane] = FALSE;
+    TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] = 0;
+    TechPtr->FilterStatusOpt[ByteLane] = START_FILTER;
+    TechPtr->FilterCountOpt = 0;
+    TechPtr->FilterSidePassCountOpt[ByteLane] = 0;
+    TechPtr->IncBy1ForNextCountOpt[ByteLane] = FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function loads the DqsRcvEnDly from saved data and program to additional index
+ *  for optimized DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *
+ */
+
+VOID
+STATIC
+MemTLoadRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Dimm = Receiver >> 1;
+  for (i = 0; i < 8; i++) {
+    if (TechPtr->DqsRcvEnSavedOpt[i]) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
+      ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ */
+
+VOID
+STATIC
+MemTSetRcvrEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  )
+{
+  UINT8 ByteLane;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    if (TechPtr->FilterStatusOpt[ByteLane] != DONE_FILTER) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), TechPtr->RcvrEnDlyOpt[ByteLane]);
+    }
+  }
+}
+/*-----------------------------------------------------------------------------
+ *
+ *  This sets any Errors generated from Dly sweep
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]   DCT   - current DCT
+ *     @param[in]   Receiver   - current receiver
+ *
+ *     @return     FALSE - Fatal error occurs.
+ *     @return     TRUE  - No fatal error occurs.
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemTSetSweepErrorOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT8 Dct,
+  IN       BOOLEAN ErrorCheck
+  )
+{
+  UINT8 ByteLane;
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  DCTPtr = NBPtr->DCTPtr;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    if (TechPtr->RcvrEnDlyOpt[ByteLane] == TechPtr->RcvrEnDlyLimitOpt[ByteLane]) {
+      // no passing window
+      if (ErrorCheck) {
+        return FALSE;
+      }
+      PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, MCTPtr);
+    }
+    if (TechPtr->RcvrEnDlyOpt[ByteLane] > (TechPtr->RcvrEnDlyLimitOpt[ByteLane] - 1)) {
+      // passing window too narrow, too far delayed
+      if (ErrorCheck) {
+        return FALSE;
+      }
+      PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader);
+      SetMemError (AGESA_ERROR, MCTPtr);
+      DCTPtr->Timings.CsTrainFail |= (UINT16) (3 << Receiver) & DCTPtr->Timings.CsPresent;
+      MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+      if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &MemPtr->StdHeader)) {
+        return FALSE;
+      }
+    }
+  }
+  return TRUE;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *  This function determines the maximum receiver delay value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @retval  MaxRcvrValue - Maximum receiver delay value for all bytelanes
+ * ----------------------------------------------------------------------------
+ */
+
+UINT16
+MemTGetMaxValueOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ByteLane;
+  UINT16 MaxRcvrValue;
+  MaxRcvrValue = 0;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    if (TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] > MaxRcvrValue) {
+      MaxRcvrValue = TechPtr->MaxRcvrEnDlyBlOpt[ByteLane];
+    }
+  }
+  MaxRcvrValue += FILTER_OFFSET_VALUE;
+  return MaxRcvrValue;
+}
+/*-----------------------------------------------------------------------------
+ *
+ *  This function determines if the sweep loop should complete.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @retval  TRUE - All bytelanes pass
+ *              FALSE - Some bytelanes fail
+ * ----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemTCheckRcvrEnDlyLimitOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  if (TechPtr->FilterCountOpt >= (UINT16)MAX_CS_PER_CHANNEL) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function load the result of write levelization training into RcvrEnDlyOpt,
+ *  using it as the initial value for Receiver DQS training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ */
+VOID
+STATIC
+MemTLoadInitialRcvEnDlyOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 ByteLane;
+  MEM_NB_BLOCK *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
+    TechPtr->RcvrEnDlyOpt[ByteLane] = NBPtr->ChannelPtr->WrDqsDlys[((Receiver >> 1) * TechPtr->DlyTableWidth ()) + ByteLane];
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c
new file mode 100755
index 0000000000..d50e53c47d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttecc.c
@@ -0,0 +1,223 @@
+/**
+ * @file
+ *
+ * mttecc.c
+ *
+ * Technology ECC byte support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTECC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTCalcDQSEccTmg (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Type,
+  IN OUT   VOID  *DlyArray
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DQS ECC timings
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTSetDQSEccTmgs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Dimm;
+  UINT8 i;
+
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  if (NBPtr->MCTPtr->NodeMemSize) {
+    for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+        ChannelPtr = NBPtr->ChannelPtr;
+        for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+          if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)1 << (Dimm * 2))) {
+            i = Dimm * TechPtr->DlyTableWidth ();
+            MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRcvEnDly, &ChannelPtr->RcvEnDlys[i]);
+            MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRdDqsDly, &ChannelPtr->RdDqsDlys[i]);
+            MemTCalcDQSEccTmg (TechPtr, Dimm, AccessWrDatDly, &ChannelPtr->WrDatDlys[i]);
+          }
+        }
+      }
+    }
+  }
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the DQS ECC timings
+ *
+ *     @param[in,out]   *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Dimm - Dimm number
+ *     @param[in]       Type - Type of DQS timing
+ *     @param[in,out]   *DlyArray - Pointer to the array of delays per this Dimm
+ *
+ */
+
+VOID
+STATIC
+MemTCalcDQSEccTmg (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dimm,
+  IN       UINT8 Type,
+  IN OUT   VOID  *DlyArray
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 Scale;
+  UINT8 EccByte;
+  UINT16 ByteiDly;
+  UINT16 BytejDly;
+  UINT16 EccDly;
+  UINT8 *WrDqsDly;
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  EccByte = TechPtr->MaxByteLanes ();
+  i = (UINT8) (ChannelPtr->DctEccDqsLike & 0xFF);
+  j = (UINT8) (ChannelPtr->DctEccDqsLike >> 8);
+  Scale = ChannelPtr->DctEccDqsScale;
+  WrDqsDly = &ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth ()];
+
+  if (Type == AccessRcvEnDly) {
+    ByteiDly = ((UINT16 *) DlyArray)[i];
+    BytejDly = ((UINT16 *) DlyArray)[j];
+  } else {
+    ByteiDly = ((UINT8 *) DlyArray)[i];
+    BytejDly = ((UINT8 *) DlyArray)[j];
+  }
+
+  //
+  // For WrDatDly, Subtract TxDqs Delay to get
+  //  TxDq-TxDqs Delta, which is what should be averaged.
+  //
+  if (Type == AccessWrDatDly) {
+    ByteiDly = ByteiDly - WrDqsDly[i];
+    BytejDly = BytejDly - WrDqsDly[j];
+  }
+
+  if (BytejDly > ByteiDly) {
+    EccDly = ByteiDly + (UINT8) (((UINT16) (BytejDly - ByteiDly) * Scale + 0x77) / 0xFF);
+    //                                                            Round up --^
+  } else {
+    EccDly = BytejDly + (UINT8) (((UINT16) (ByteiDly - BytejDly) * (0xFF - Scale) + 0x77) / 0xFF);
+    //                                                                     Round up --^
+  }
+
+  if (Type == AccessRcvEnDly) {
+    ((UINT16 *) DlyArray)[EccByte] = EccDly;
+  } else {
+    ((UINT8 *) DlyArray)[EccByte] = (UINT8) EccDly;
+  }
+
+  //
+  // For WrDatDly, Add back the TxDqs value for ECC bytelane
+  //
+  if (Type == AccessWrDatDly) {
+    EccDly = EccDly + WrDqsDly[EccByte];
+  }
+
+  NBPtr->SetTrainDly (NBPtr, Type, DIMM_BYTE_ACCESS (Dimm, EccByte), EccDly);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c
new file mode 100755
index 0000000000..783d8f5a26
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mtthrc.c
@@ -0,0 +1,377 @@
+/**
+ * @file
+ *
+ * mtthrc.c
+ *
+ * Phy assisted DQS receiver enable training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 7171 $ @e \$Date: 2008-08-05 11:42:14 -0500 (Tue, 05 Aug 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTHRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemTPrepareRcvrEnDlySeed (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 Pass
+  );
+
+VOID
+STATIC
+MemTProgramRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 Pass
+  );
+
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern UINT16 T1minToFreq[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of Phy assisted receiver enable training
+ *      for current node at DDR800 and below.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTDqsTrainRcvrEnHw (TechPtr, 1);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes second pass of Phy assisted receiver enable training
+ *      for current node at DDR1066 and above.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  // If current speed is higher than start-up speed, do second pass of WL
+  if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
+    return MemTDqsTrainRcvrEnHw (TechPtr, 2);
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes Phy assisted receiver enable training for current node.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ *     @pre   Auto refresh and ZQCL must be disabled
+ *
+ */
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  UINT32 TestAddrRJ16;
+  UINT8  Dct;
+  UINT8  ChipSel;
+
+  NBPtr = TechPtr->NBPtr;
+
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader));
+  IDS_HDT_CONSOLE ("!\nStart HW RxEn training\n");
+
+  // Set environment settings before training
+  MemTBeginTraining (TechPtr);
+
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    //training for each rank
+    for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+      if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
+        if ((ChipSel & 1) == 0) {
+          // 1.Prepare the DIMMs for training
+          NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1);
+
+          // 2.Prepare the phy for DQS receiver enable training.
+          MemTPrepareRcvrEnDlySeed (TechPtr, ChipSel, Pass);
+        }
+
+        IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
+        IDS_HDT_CONSOLE ("\t\tTestAddr %lx0000\n", TestAddrRJ16);
+
+        // 3.BIOS initiates the phy assisted receiver enable training
+        NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1);
+
+        // 4.BIOS begins sending out of back-to-back reads to create
+        //   a continuous stream of DQS edges on the DDR interface.
+        NBPtr->GenHwRcvEnReads (NBPtr, TestAddrRJ16);
+
+        // 6.Wait 200 MEMCLKs.
+        MemUWait10ns (200, NBPtr->MemPtr);
+
+        // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training.
+        NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0);
+
+        // 8.Get the gross and fine delay values.
+        // 9.Calculate the corresponding final delay values
+        MemTProgramRcvrEnDly (TechPtr, ChipSel, Pass);
+      }
+    }
+    // Set Max Latency for both channels
+    if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
+      NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat);
+    }
+    TechPtr->ResetDCTWrPtr (TechPtr, 6);
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE ("End HW RxEn training\n\n");
+
+  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function calculates RcvEn seed value for each rank
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  ChipSel - rank to be trained
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ */
+VOID
+STATIC
+MemTPrepareRcvrEnDlySeed (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT16 Seed;
+  UINT16 SeedPass1Remainder;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT16 Speed;
+  UINT8  Dimm;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  Speed = NBPtr->DCTPtr->Timings.Speed;
+  Dimm = ChipSel >> 1;
+
+  IDS_HDT_CONSOLE ("\n\t\t\tSeeds: ");
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    if (Pass == 1) {
+      // For Pass1, BIOS starts with the delay value obtained from the first pass of write
+      // levelization training that was done in DDR3 Training and add a delay value of 3Bh.
+      Seed = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] + 0x3B;
+    } else {
+      // For Pass2, for each byte lane, BIOS uses the results obtained
+      // from Pass 1 substract 1 UI to get back to preamble left edge.
+      RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] - 0x20;
+      // Scale the seed to new speed
+      Seed = (UINT16) (((UINT32) RcvEnDly * Speed) / TechPtr->PrevSpeed);
+    }
+    // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32.
+    // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32.
+    // Use SeedGrossPass1 to determine SeedPreGrossPass1:
+    SeedPass1Remainder = Seed & 0x1E0;
+    if ((Seed & 0x20) != 0) {
+      //SeedPreGrossPass1=1 if SeedGrossPass1 is odd
+      Seed = (Seed & 0x1F) | 0x20;
+      SeedPass1Remainder = SeedPass1Remainder - 0x20;
+    } else {
+      //SeedPreGrossPass1=2 if SeedGrossPass1 is even
+      Seed = (Seed & 0x1F) | 0x40;
+      SeedPass1Remainder = SeedPass1Remainder - 0x40;
+    }
+
+    // The last term that BIOS needs to calculate for the seed is called SeedPass1Remainder.
+    // SeedPass1Remainder=SeedGrossPass1-SeedPreGrossPass1. BIOS saves this value which is
+    // used to determine the final delay value. This is necessary because the phy does not have the full
+    // range of delay adjustment.
+    ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = SeedPass1Remainder << 6;
+
+    //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52) with SeedPreGrossPass1
+    //and SeedFinePass1 from the preceding steps.
+    NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Seed);
+    IDS_HDT_CONSOLE ("%02x ", Seed);
+
+    // 202688: Program seed value to RcvEnDly also.
+    NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Seed);
+  }
+  IDS_HDT_CONSOLE ("\n");
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function calculates final RcvrEnDly for each rank
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  ChipSel - Rank to be trained
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ */
+VOID
+STATIC
+MemTProgramRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 ChipSel,
+  IN       UINT8 Pass
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT16 SeedPass1Remainder;
+  UINT8  ByteLane;
+  UINT16 RcvEnDly;
+  UINT8  Dimm;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+  Dimm = ChipSel >> 1;
+
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    SeedPass1Remainder = (ChannelPtr->RcvEnDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] >> 6) & 0x1E0;
+    RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
+    IDS_HDT_CONSOLE ("%02x ", RcvEnDly);
+
+    // Calculate the corresponding final delay values:
+    // [DqsRcvEnGrossDelay]= SeedPass1Remainder+PhRecGrossDlyByte
+    // [DqsRcvEnFineDelay]=PhRecFineDlyByte.
+    RcvEnDly = RcvEnDly + SeedPass1Remainder;
+
+    // Add 1 UI to get to the midpoint of preamble
+    RcvEnDly += 0x20;
+
+    if ((ChipSel & 1) == 0) {
+      if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16) 1 << (ChipSel + 1))) != 0) {
+        // If dual-rank, save the trained result of the first rank
+        ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] |= RcvEnDly;
+      } else {
+        ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly;
+        NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), RcvEnDly);
+      }
+    } else {
+      // When having the result from second rank, average with first rank's and program to register
+      RcvEnDly = ((ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] & 0x3FF) + RcvEnDly + 1) / 2;
+      ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly;
+      NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), RcvEnDly);
+    }
+    IDS_HDT_CONSOLE ("%02x ", RcvEnDly);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c
new file mode 100755
index 0000000000..ad67120dd4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttml.c
@@ -0,0 +1,211 @@
+/**
+ * @file
+ *
+ * mttml.c
+ *
+ * Technology Max Latency Training support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "merrhdl.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTML_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function trains Max latency for all dies
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainMaxLatency (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT32 TestAddrRJ16;
+  UINT8 Dct;
+  UINT8 ChipSel;
+  _16BYTE_ALIGN  UINT8  PatternBuffer[6 * 64];
+  UINT8  TestBuffer[6 * 64];
+  UINT8  *PatternBufPtr;
+  UINT16 MaxLatDly;
+  UINT16 MaxLatLimit;
+  UINT16 Margin;
+  UINT16 CurTest;
+  UINT8 _CL_;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+  MemPtr = NBPtr->MemPtr;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE ("!\nStart MaxRdLat training\n");
+  // Set environment settings before training
+  AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader));
+  MemTBeginTraining (TechPtr);
+
+  _CL_ = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3;
+  PatternBufPtr = PatternBuffer;
+  MemUFillTrainPattern (TestPatternML, PatternBufPtr, _CL_ * 64);
+
+  // Begin max latency training
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) {
+      break;
+    }
+
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+
+    if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
+      if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
+
+        if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
+          IDS_HDT_CONSOLE ("!\t\tCS %d\n", ChipSel);
+          IDS_HDT_CONSOLE ("\t\t\tWrite to address: %04lx0000\n", TestAddrRJ16);
+
+          // Write the test patterns
+          AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader));
+          NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_);
+
+          // Sweep max latency delays
+          NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &MaxLatDly, &MaxLatLimit, &Margin);
+          AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader));
+
+          TimesFail = 0;
+          ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+          {
+            for (; MaxLatDly < MaxLatLimit; MaxLatDly++) {
+              NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
+              IDS_HDT_CONSOLE ("\t\t\tDly %3x", MaxLatDly);
+              TechPtr->ResetDCTWrPtr (TechPtr, 6);
+
+              AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader));
+              NBPtr->ReadPattern (NBPtr, TestBuffer, TestAddrRJ16, _CL_);
+              AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader));
+              CurTest = NBPtr->CompareTestPattern (NBPtr, TestBuffer, PatternBufPtr, _CL_ * 64);
+              NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_);
+
+	      // Traditional training increments MaxLatDly until the test passes
+	      // and uses it as left edge
+              if (CurTest == 0xFFFF) {
+		      IDS_HDT_CONSOLE ("  P");
+		      IDS_HDT_CONSOLE ("\n");
+                break;
+	      } else {
+		      MaxLatDly++;
+              }
+	      IDS_HDT_CONSOLE ("\n");
+            }// End of delay sweep
+            ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail)
+          }
+
+          AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader));
+
+          if (MaxLatDly >= MaxLatLimit) {
+            PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+            SetMemError (AGESA_ERROR, MCTPtr);
+            NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent;
+            MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+            if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
+              return FALSE;
+            }
+          } else {
+            // set final delays
+            NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly + Margin);
+          }
+        }
+      }
+    }
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE ("End MaxRdLat training\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c
new file mode 100755
index 0000000000..d9f33a1e23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttoptsrc.c
@@ -0,0 +1,420 @@
+/**
+ * @file
+ *
+ * mttoptsrc.c
+ *
+ * New Technology Software based DQS receiver enable training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 7359 $ @e \$Date: 2008-08-13 01:53:23 +0800 (Wed, 13 Aug 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTOPTSRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTDqsTrainOptRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+BOOLEAN
+MemTNewRevTrainingSupport (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of receiver enable training for all dies
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainOptRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTDqsTrainOptRcvrEnSw (TechPtr, 1);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes receiver enable training for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+STATIC
+MemTDqsTrainOptRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  _16BYTE_ALIGN  UINT8  PatternBuffer[6 * 64];
+  UINT8  TestBuffer[256];
+  UINT8  *PatternBufPtr[6];
+  UINT8  *TempPtr;
+  UINT32 TestAddrRJ16[4];
+  UINT32 TempAddrRJ16;
+  UINT32 RealAddr;
+  UINT16 CurTest[4];
+  UINT8 Dct;
+  UINT8 Receiver;
+  UINT8 i;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+  UINT16 RcvrEnDly;
+  UINT16 MaxRcvrEnDly;
+  UINT16 RcvrEnDlyLimit;
+  UINT16 MaxDelayCha;
+  BOOLEAN IsDualRank;
+  BOOLEAN S0En;
+  BOOLEAN S1En;
+
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  TempAddrRJ16 = 0;
+  TempPtr = NULL;
+  MaxDelayCha = 0;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE ("!\nStart Optimized SW RxEn training\n");
+  // Set environment settings before training
+  MemTBeginTraining (TechPtr);
+
+  PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer;
+  // These two patterns used for first Test Address
+  MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64);
+  // Second Cacheline used for Dummy Read is the inverse of
+  //  the first so that is is not mistaken for the real read
+  MemUFillTrainPattern (TestPattern1, PatternBufPtr[0] + 64, 64);
+  PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128;
+  // These two patterns used for second Test Address
+  MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64);
+  // Second Cacheline used for Dummy Read is the inverse of
+  //  the first so that is is not mistaken for the real read
+  MemUFillTrainPattern (TestPattern0, PatternBufPtr[1] +64, 64);
+
+  // Fill pattern for flush after every sweep
+  PatternBufPtr[4] = PatternBufPtr[0] + 256;
+  MemUFillTrainPattern (TestPattern3, PatternBufPtr[4], 64);
+
+  // Fill pattern for initial dummy read
+  PatternBufPtr[5] = PatternBufPtr[0] + 320;
+  MemUFillTrainPattern (TestPattern4, PatternBufPtr[5], 64);
+
+
+  // Begin receiver enable training
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    // Set training bit
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1);
+
+    // Relax Max Latency before training
+    NBPtr->SetMaxLatency (NBPtr, 0xFFFF);
+
+    if (Pass == FIRST_PASS) {
+      TechPtr->InitDQSPos4RcvrEn (TechPtr);
+    }
+
+    // there are four receiver pairs, loosely associated with chipselects.
+    Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8;
+    for (; Receiver < 8; Receiver += 2) {
+      S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]);
+      S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]);
+      if (S0En) {
+        TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16;
+      }
+      if (S1En) {
+        TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16;
+      }
+      if (S0En && S1En) {
+        IsDualRank = TRUE;
+      } else {
+        IsDualRank = FALSE;
+      }
+      if (S0En || S1En) {
+        IDS_HDT_CONSOLE ("!\t\tCS %d\n", Receiver);
+
+        RcvrEnDlyLimit = 0x1FF;      // @attention - limit depends on proc type
+        TechPtr->DqsRcvEnSaved = 0;
+        RcvrEnDly = RcvrEnDlyLimit;
+        RealAddr = 0;
+
+        TechPtr->GetFirstPassVal = FALSE;
+        TechPtr->DqsRcvEnFirstPassVal = 0;
+        TechPtr->RevertPassVal = FALSE;
+        TechPtr->InitializeVariablesOpt (TechPtr);
+
+        // Write the test patterns
+        AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
+        IDS_HDT_CONSOLE ("\t\t\tWrite to addresses: ");
+        for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+          // One cacheline of data to be tested and one of dummy data
+          MemUWriteCachelines (RealAddr, PatternBufPtr[i], 2);
+          // This is dummy data with a different pattern used for the first dummy read.
+          MemUWriteCachelines (RealAddr + 128, PatternBufPtr[5], 1);
+          IDS_HDT_CONSOLE (" %04lx0000 ", TestAddrRJ16[i]);
+        }
+        IDS_HDT_CONSOLE ("\n");
+
+        // Sweep receiver enable delays
+        AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
+        TimesFail = 0;
+        ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+        {
+          TechPtr->LoadInitialRcvrEnDlyOpt (TechPtr, Receiver);
+          while (!TechPtr->CheckRcvrEnDlyLimitOpt (TechPtr)) {
+            AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
+            TechPtr->SetRcvrEnDlyOpt (TechPtr, Receiver, RcvrEnDly);
+            // Read and compare the first beat of data
+            for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+              AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
+              RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+              //
+              // Issue dummy cacheline reads
+              //
+              MemUReadCachelines (TestBuffer + 128, RealAddr + 128, 1);
+              MemUReadCachelines (TestBuffer, RealAddr, 1);
+              MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr);
+              //
+              // Perform actual read which will be compared
+              //
+              MemUReadCachelines (TestBuffer + 64, RealAddr + 64, 1);
+              AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
+              CurTest[i] = TechPtr->Compare1ClPatternOpt (TechPtr, TestBuffer + 64 , PatternBufPtr[i] + 64, i, Receiver, S1En);
+              // Due to speculative execution during MemUReadCachelines, we must
+              //  flush one more cache line than we read.
+              MemUProcIOClFlush (TestAddrRJ16[i], 4, MemPtr);
+              TechPtr->ResetDCTWrPtr (TechPtr, Receiver);
+
+              //
+              // Swap the test pointers such that even and odd steps alternate.
+              //
+              if ((i % 2) == 0) {
+                TempPtr = PatternBufPtr[i];
+                PatternBufPtr[i] = PatternBufPtr[i + 1];
+
+                TempAddrRJ16 = TestAddrRJ16[i];
+                TestAddrRJ16[i] = TestAddrRJ16[i + 1];
+              } else {
+                PatternBufPtr[i] = TempPtr;
+                TestAddrRJ16[i] = TempAddrRJ16;
+              }
+            }
+          }   // End of delay sweep
+          ERROR_HANDLE_RETRAIN_END (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, TRUE), TimesFail)
+        }
+
+        if (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, FALSE)) {
+          return FALSE;
+        }
+
+        TechPtr->LoadRcvrEnDlyOpt (TechPtr, Receiver);     // set final delays
+        //
+        // Flush AA and 55 patterns by reading a dummy pattern to fill in FIFO
+        //
+        // Aquire a new FSBase, based on the last test address that we stored.
+        RealAddr = MemUSetUpperFSbase (TempAddrRJ16, MemPtr);
+        ASSERT (RealAddr != 0);
+        MemUWriteCachelines (RealAddr, PatternBufPtr[4], 1);
+        MemUWriteCachelines (RealAddr + 64, PatternBufPtr[4], 1);
+        MemUReadCachelines (TestBuffer, RealAddr, 2);
+        // Due to speculative execution during MemUReadCachelines, we must
+        //  flush one more cache line than we read.
+        MemUProcIOClFlush (TempAddrRJ16, 3, MemPtr);
+      }
+    }   // End while Receiver < 8
+
+    // Clear training bit when done
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
+
+    // Set Max Latency for both channels
+    MaxRcvrEnDly = TechPtr->GetMaxValueOpt (TechPtr);
+    IDS_HDT_CONSOLE ("\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly);
+    if (MCTPtr->GangedMode) {
+      if (Dct == 0) {
+        MaxDelayCha = MaxRcvrEnDly;
+      } else if (MaxRcvrEnDly > MaxDelayCha) {
+        NBPtr->SwitchDCT (NBPtr, 0);
+        NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+      }
+    } else {
+      NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+    }
+    TechPtr->ResetDCTWrPtr (TechPtr, 6);
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE ("End Optimized SW RxEn training\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ *  This function saves passing DqsRcvEnDly values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       cmpResultRank0 - compare result for Rank 0
+ *     @param[in]       cmpResultRank0 - compare result for Rank 1
+ *
+ *     @retval  TRUE - All bytelanes pass
+ *              FALSE - Some bytelanes fail
+ * ----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilterOpt (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Dimm;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver < MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
+
+  Dimm = Receiver >> 1;
+
+  if (TechPtr->GetFirstPassVal && (RcvEnDly - TechPtr->DqsRcvEnFirstPassVal) >= 0x30) {
+    for (i = 0; i < 8; i++) {
+      ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i] = TechPtr->DqsRcvEnFirstPassVal + NEW_RECEIVER_FINAL_OFFSETVALUE;
+    }
+    TechPtr->DqsRcvEnSaved = 0xFF;
+  }
+
+  if (Passed == 0xFF) {
+    if (!TechPtr->GetFirstPassVal) {
+      TechPtr->DqsRcvEnFirstPassVal = RcvEnDly;
+      TechPtr->GetFirstPassVal = TRUE;
+    }
+    return TRUE;
+  } else {
+    TechPtr->DqsRcvEnFirstPassVal = 0;
+
+    // We have got first passing value, but later, we meet with glitch
+    if (TechPtr->GetFirstPassVal) {
+      TechPtr->DqsRcvEnFirstPassVal = 0xFF;
+      TechPtr->GetFirstPassVal = FALSE;
+    }
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
new file mode 100755
index 0000000000..933ee946e1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/Tech/mttsrc.c
@@ -0,0 +1,339 @@
+/**
+ * @file
+ *
+ * mttsrc.c
+ *
+ * Technology Software based DQS receiver enable training
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Tech)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mu.h"
+#include "mt.h"
+#include "GeneralServices.h"
+#include "merrhdl.h"
+#include "Filecode.h"
+#define FILECODE PROC_MEM_TECH_MTTSRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes first pass of receiver enable training for all dies
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+
+BOOLEAN
+MemTTrainRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  return MemTDqsTrainRcvrEnSw (TechPtr, 1);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes receiver enable training for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]  Pass - Pass of the receiver training
+ *
+ *     @return          TRUE -  No fatal error occurs.
+ *     @return          FALSE - Fatal error occurs.
+ */
+BOOLEAN
+STATIC
+MemTDqsTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  )
+{
+  _16BYTE_ALIGN  UINT8  PatternBuffer[3 * 64];
+  UINT8  TestBuffer[120];
+  UINT8  *PatternBufPtr[4];
+  UINT8  *TempPtr;
+  UINT32 TestAddrRJ16[4];
+  UINT32 TempAddrRJ16;
+  UINT32 RealAddr;
+  UINT16 CurTest[4];
+  UINT8 Dct;
+  UINT8 Receiver;
+  UINT8 i;
+  UINT8 TimesFail;
+  UINT8 TimesRetrain;
+  UINT16 RcvrEnDly;
+  UINT16 MaxRcvrEnDly;
+  UINT16 RcvrEnDlyLimit;
+  UINT16 MaxDelayCha;
+  BOOLEAN IsDualRank;
+  BOOLEAN S0En;
+  BOOLEAN S1En;
+  UINT8 MaxFilterDly;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  TempAddrRJ16 = 0;
+  TempPtr = NULL;
+  MaxDelayCha = 0;
+  MaxFilterDly = TechPtr->MaxFilterDly;
+  RcvrEnDlyLimit = NBPtr->RcvrEnDlyLimit;
+  TimesRetrain = DEFAULT_TRAINING_TIMES;
+  IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
+
+  IDS_HDT_CONSOLE ("!\nStart SW RxEn training\n");
+  // Set environment settings before training
+  MemTBeginTraining (TechPtr);
+
+  PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer;
+  MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64);
+  PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128;
+  MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64);
+
+  // Begin receiver enable training
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
+  MaxRcvrEnDly = 0;
+  for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
+    IDS_HDT_CONSOLE ("!\tDct %d\n", Dct);
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    DCTPtr = NBPtr->DCTPtr;
+
+    // Set training bit
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1);
+
+    // Relax Max Latency before training
+    NBPtr->SetMaxLatency (NBPtr, 0xFFFF);
+
+    if (Pass == FIRST_PASS) {
+      TechPtr->InitDQSPos4RcvrEn (TechPtr);
+    }
+
+    // there are four receiver pairs, loosely associated with chipselects.
+    Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8;
+    for (; Receiver < 8; Receiver += 2) {
+      TechPtr->DqsRcvEnSaved = 0;
+      RcvrEnDly = RcvrEnDlyLimit;
+      S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]);
+      S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]);
+      if (S0En) {
+        TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16;
+      }
+      if (S1En) {
+        TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16;
+      }
+      if (S0En && S1En) {
+        IsDualRank = TRUE;
+      } else {
+        IsDualRank = FALSE;
+      }
+
+      if (S0En || S1En) {
+        IDS_HDT_CONSOLE ("!\t\tCS %d\n", Receiver);
+
+        // Write the test patterns
+        AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
+        IDS_HDT_CONSOLE ("\t\t\tWrite to addresses: ");
+        for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+          RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+          MemUWriteCachelines (RealAddr, PatternBufPtr[i], 1);
+          IDS_HDT_CONSOLE (" %04lx0000 ", TestAddrRJ16[i]);
+        }
+        IDS_HDT_CONSOLE ("\n");
+
+        // Initialize RcvrEnDly value and other DCT stored values
+        //                MCTPtr->DqsRcvEnPass = Pass ? 0xFF : 0;
+
+        // Sweep receiver enable delays
+        AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
+        TimesFail = 0;
+        ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
+        {
+          for (RcvrEnDly = 0; RcvrEnDly < RcvrEnDlyLimit; RcvrEnDly++) {
+            AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
+            TechPtr->SetRcvrEnDly (TechPtr, Receiver, RcvrEnDly);
+            IDS_HDT_CONSOLE ("\t\t\tDly %3x", RcvrEnDly);
+
+            // Read and compare the first beat of data
+            for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
+              AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
+              RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
+              MemUReadCachelines (TestBuffer, RealAddr, 1);
+              AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
+              CurTest[i] = TechPtr->Compare1ClPattern (TechPtr, TestBuffer, PatternBufPtr[i]);
+              // Due to speculative execution during MemUReadCachelines, we must
+              //  flush one more cache line than we read.
+              MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr);
+              TechPtr->ResetDCTWrPtr (TechPtr, Receiver);
+
+              //
+              // Swap the test pointers such that even and odd steps alternate.
+              //
+              if ((i % 2) == 0) {
+                TempPtr = PatternBufPtr[i];
+                PatternBufPtr[i] = PatternBufPtr[i + 1];
+
+                TempAddrRJ16 = TestAddrRJ16[i];
+                TestAddrRJ16[i] = TestAddrRJ16[i + 1];
+              } else {
+                PatternBufPtr[i] = TempPtr;
+                TestAddrRJ16[i] = TempAddrRJ16;
+              }
+            }
+
+            if (TechPtr->SaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, S0En ? (CurTest[0] & CurTest[1]) : 0xFFFF, S1En ? (CurTest[2] & CurTest[3]) : 0xFFFF)) {
+              // if all bytelanes pass
+              if (MaxRcvrEnDly < (RcvrEnDly - MaxFilterDly)) {
+                MaxRcvrEnDly = RcvrEnDly - MaxFilterDly;
+              }
+              break;
+            }
+          } // End of delay sweep
+          ERROR_HANDLE_RETRAIN_END ((RcvrEnDly > (RcvrEnDlyLimit - 1)), TimesFail)
+        }
+
+        if (RcvrEnDly == RcvrEnDlyLimit) {
+          // no passing window
+          PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ERROR, MCTPtr);
+        }
+
+        if (RcvrEnDly > (RcvrEnDlyLimit - 1)) {
+        // passing window too narrow, too far delayed
+          PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
+          SetMemError (AGESA_ERROR, MCTPtr);
+          DCTPtr->Timings.CsTrainFail |= DCTPtr->Timings.CsPresent & (UINT16) (3 << Receiver);
+          MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
+          if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) {
+            return FALSE;
+          }
+        }
+      }
+
+      TechPtr->LoadRcvrEnDly (TechPtr, Receiver);     // set final delays
+    }   // End while Receiver < 8
+
+    // Clear training bit when done
+    NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
+
+    // Set Max Latency for both channels
+    MaxRcvrEnDly += 0x20;  // @attention -
+    IDS_HDT_CONSOLE ("\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly);
+    if (MCTPtr->GangedMode) {
+      if (Dct == 0) {
+        MaxDelayCha = MaxRcvrEnDly;
+      } else if (MaxRcvrEnDly > MaxDelayCha) {
+        NBPtr->SwitchDCT (NBPtr, 0);
+        NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+      }
+    } else {
+      NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
+    }
+    TechPtr->ResetDCTWrPtr (TechPtr, 6);
+  }
+
+  // Restore environment settings after training
+  MemTEndTraining (TechPtr);
+  IDS_HDT_CONSOLE ("End SW RxEn training\n\n");
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/ma.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/ma.h
new file mode 100755
index 0000000000..e6b7acd5b4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/ma.h
@@ -0,0 +1,241 @@
+/**
+ * @file
+ *
+ * ma.h
+ *
+ * ARDK common header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MA_H_
+#define _MA_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+#define MAX_CS_PER_CHANNEL      8   ///< Max CS per channel
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/** MARDK Structure*/
+typedef struct {
+  UINT16   Speed;                  ///< Dram speed in MHz
+  UINT8    Loads;                  ///< Number of Data Loads
+  UINT32   AddrTmg;                ///< Address Timing value
+  UINT32   Odc;                    ///< Output Driver Compensation Value
+} PSCFG_ENTRY;
+
+/** MARDK Structure*/
+typedef struct {
+  UINT16   Speed;                  ///< Dram speed in MHz
+  UINT8    Loads;                  ///< Number of Data Loads
+  UINT32   AddrTmg;                ///< Address Timing value
+  UINT32   Odc;                    ///< Output Driver Compensation Value
+  UINT8    Dimms;                  ///< Number of Dimms
+} ADV_PSCFG_ENTRY;
+
+/** MARDK Structure for RDIMMs*/
+typedef struct {
+  UINT16   Speed;                  ///< Dram speed in MHz
+  UINT16   DIMMRankType;         ///< Bitmap of Ranks   //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
+  UINT32   AddrTmg;                ///< Address Timing value
+  UINT16   RC2RC8;                   ///< RC2 and RC8 value  //High byte: 1st pair value, Low byte: 2nd pair value
+  UINT8    Dimms;                  ///< Number of Dimms
+} ADV_R_PSCFG_ENTRY;
+
+/** MARDK Structure*/
+typedef struct {
+  UINT16   DIMMRankType;         ///< Bitmap of Ranks   //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
+  UINT32   PhyRODTCSLow;          ///< Fn2_9C 180
+  UINT32   PhyRODTCSHigh;         ///< Fn2_9C 181
+  UINT32   PhyWODTCSLow;          ///< Fn2_9C 182
+  UINT32   PhyWODTCSHigh;         ///< Fn2_9C 183
+  UINT8    Dimms;                  ///< Number of Dimms
+} ADV_PSCFG_ODT_ENTRY;
+
+/** MARDK Structure for Write Levelization ODT*/
+typedef struct {
+  UINT16   DIMMRankType;         ///< Bitmap of Ranks   //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
+  UINT8    PhyWrLvOdt[MAX_CS_PER_CHANNEL/2];            ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm
+  UINT8    Dimms;                ///< Number of Dimms
+} ADV_R_PSCFG_WL_ODT_ENTRY;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+MemAGetPsCfgDef (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRDr2 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSDA2 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgRC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSLN3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgULN3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgSON3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+AGESA_STATUS
+MemAGetPsCfgUON3 (
+  IN OUT   MEM_DATA_STRUCT *MemData,
+  IN       UINT8 SocketID,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel
+  );
+
+UINT16
+MemAGetPsRankType (
+  IN       CH_DEF_STRUCT *CurrentChannel
+  );
+
+#endif  /* _MA_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/memPage.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/memPage.h
new file mode 100755
index 0000000000..1dd8a15c3d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/memPage.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * Create outline and references for Memory Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page memmain Memory Component Documentation
+ *
+ * Additional documentation for the Memory component consists of
+ *
+ * - Maintenance Guides:
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/merrhdl.h
new file mode 100755
index 0000000000..bdb199dbaf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/merrhdl.h
@@ -0,0 +1,103 @@
+/**
+ * @file
+ *
+ * mmerrhdl.h
+ *
+ * main error handling
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 11336 $ @e \$Date: 2009-03-13 20:10:06 -0500 (Fri, 13 Mar 2009) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MMERRHDL_H_
+#define _MMERRHDL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define EXCLUDE_ALL_DCT 0xFF
+#define EXCLUDE_ALL_CHIPSEL  0xFF
+
+/// default times of training
+#define DEFAULT_TRAINING_TIMES 1
+
+/// number of us to wait in parallel training
+#define PARALLEL_TRAINING_TIMEOUT 60000000
+
+/// number of us to wait in PCI space access
+#define PCI_ACCESS_TIMEOUT 5000
+/// number of us to wait in special PCI space access which takes much longer than others
+#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000
+
+/// Beginning of retrain handling, must be ended with the ending of the handling
+#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit)
+
+/// Ending of retrain handling
+#define ERROR_HANDLE_RETRAIN_END(condition, counter) \
+if (condition) { \
+  counter ++; \
+} else { \
+  break; \
+}
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemErrHandle (
+  IN       DIE_STRUCT *MCTPtr,
+  IN       UINT8  DCT,
+  IN       UINT16  ChipSelMask,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  /* _MMERRHDL_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h
new file mode 100755
index 0000000000..0edf33f756
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfParallelTraining.h
@@ -0,0 +1,113 @@
+/**
+ * @file
+ *
+ * mfParallelTraining.h
+ *
+ * Header file for the parallel training feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 5655 $ @e \$Date: 2008-04-03 23:29:23 -0500 (Thu, 03 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFPARALLELTRAINING_H_
+#define _MFPARALLELTRAINING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+typedef BOOLEAN (*REMOTE_NBBLOCK_CONSTRUCTOR) (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       DIE_STRUCT *MCTPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr
+);
+
+///< This structure defines the environment on the AP for parallel training
+typedef struct _REMOTE_TRAINING_ENV {
+  IN OUT AMD_CONFIG_PARAMS StdHeader;                ///< Config pointer of BSP
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+  IN REMOTE_NBBLOCK_CONSTRUCTOR NBBlockCtor;         ///< NB Block constructor
+  IN MEM_FEAT_BLOCK_NB *FeatPtr;                     ///< Feature block pointer
+  IN UINT8 *TableBasedAlterations;                   ///< Point to an array of data bytes describing desired modifications to register settings
+  IN PSO_TABLE *PlatformMemoryConfiguration;                 ///< Point to platform config table
+  IN UINT32 HoleBase;                                ///< Used for Memtyping
+  IN UINT32 UmaSize;                               ///< Used for Memtyping
+  IN UINT16 BottomIo;                                ///< Used for Memtyping
+  IN UINT32 SysLimit;                                ///< Used for Memtyping
+  IN UINT8  BspSocket;                               ///< Socket number of BSP
+  IN UINT8  BspCore;                                 ///< Core number of BSP
+  IN DIE_STRUCT DieStruct;                           ///< Remote copy of Die Struct
+} REMOTE_TRAINING_ENV;
+
+///< This structure defines Die information
+typedef struct _DIE_INFO {
+  IN OUT UINT8 Socket;                               ///< Socket number
+  IN OUT UINT8 Core;                                 ///< Core number
+  IN OUT BOOLEAN Training;                           ///< Training Flag, 1 = Training has been started on this core
+} DIE_INFO;
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFParallelTraining (
+  IN OUT   REMOTE_TRAINING_ENV *EnvPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif  /* _MFPARALLELTRAINING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h
new file mode 100755
index 0000000000..d1ae93583f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfStandardTraining.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * mfStandardTraining.h
+ *
+ * Feature implementation of standard function which performs memory training
+ * from the BSP only
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 5655 $ @e \$Date: 2008-04-03 23:29:23 -0500 (Thu, 03 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFSTANDARDTRAINING_H_
+#define _MFSTANDARDTRAINING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemFStandardTraining (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFSTANDARDTRAINING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h
new file mode 100755
index 0000000000..6b926d96be
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfmemclr.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * mfmemclr.h
+ *
+ * Feature Functions For Memory Clear Operation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MFMEMCLR_H_
+#define _MFMEMCLR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemFMctMemClr_Init (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemFMctMemClr_Sync (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MFMEMCLR_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfs3.h
new file mode 100755
index 0000000000..9b36ad0d30
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mfs3.h
@@ -0,0 +1,239 @@
+/**
+ * @file
+ *
+ * mfS3.h
+ *
+ * S3 resume memory related functions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/Feat/S3)
+ * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MFS3_H_
+#define _MFS3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define PRESELFREF 0
+#define POSTSELFREF 1
+#define DCT0 0
+#define DCT1 1
+#define DCT0_MASK 0x1
+#define DCT1_MASK 0x2
+#define DCT0_DDR3_MASK 0x10
+#define DCT1_DDR3_MASK 0x20
+#define NODE_WITHOUT_DIMM_MASK 0x80
+#define DCT0_ANY_DIMM_MASK 0x55
+#define DCT1_ANY_DIMM_MASK 0xAA
+#define ANY_DIMM_MASK 0xFF
+
+#define DCT_PHY_FLAG 0
+#define DCT_EXTRA_FLAG 1
+#define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset)
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Phy register name
+typedef enum {
+  S3BFPhyClkConfig0,          ///< Phy Register PhyClkConfig0
+  S3BFPhyClkConfig1,          ///< Phy Register PhyClkConfig1
+  S3BFPhyClkConfig2,          ///< Phy Register PhyClkConfig2
+  S3BFPhyClkConfig3,          ///< Phy Register PhyClkConfig3
+  S3BFPLLLockTime,            ///< Phy Register PLLLockTime
+  S3BFDLLLockTime,            ///< Phy Register DLLLockTime
+  S3BFEccDLLPwrDnConf,        ///< Phy Register EccDLLPwrDnConf
+  S3BFEccDLLConf,             ///< Phy Register EccDLLConf
+  S3BFErr322I,                ///< Phy Register for Errata 322
+  S3BFErr322II                ///< Phy Register for Errata 322
+} S3_PHY_NAME;
+
+/// struct for all the descriptor for pre exit self refresh and post exit self refresh
+typedef struct _DESCRIPTOR_GROUP {
+  PCI_DEVICE_DESCRIPTOR PCIDevice[2];  ///< PCI device descriptor
+  CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2];  ///< Conditional PCI device descriptor
+  MSR_DEVICE_DESCRIPTOR MSRDevice[2];  ///< MSR device descriptor
+  CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2];  ///< Conditional MSR device descriptor
+} DESCRIPTOR_GROUP;
+
+/// Northbridge block to be used in S3 resume and save.
+typedef struct _S3_MEM_NB_BLOCK {
+  UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap.
+  struct _MEM_NB_BLOCK *NBPtr;    ///< Pointer to the north bridge block.
+  VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register
+  VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting
+  VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting
+  UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register
+  BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh
+  VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base
+  AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device
+} S3_MEM_NB_BLOCK;
+
+/// Header for heap space to store the special case register.
+typedef struct _S3_SPECIAL_CASE_HEAP_HEADER {
+  UINT8 Node;  ///< Node ID for the the header
+  UINT8 Offset;  ///< Offset for the target node
+} S3_SPECIAL_CASE_HEAP_HEADER;
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AmdMemS3Resume (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+MemS3ResumeInitNB (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+MemS3Deallocate (
+  IN   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetPciDeviceRegisterList (
+  IN       PCI_DEVICE_DESCRIPTOR     *Device,
+     OUT   PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetCPciDeviceRegisterList (
+  IN       CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
+     OUT   CPCI_REGISTER_BLOCK_HEADER        **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetMsrDeviceRegisterList (
+  IN       MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetCMsrDeviceRegisterList (
+  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,
+     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,
+  IN       AMD_CONFIG_PARAMS                     *StdHeader
+  );
+
+AGESA_STATUS
+MemFS3GetDeviceList (
+  IN OUT   DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MemFS3Wait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+BOOLEAN
+MemNS3ResumeNb (
+  IN OUT   S3_MEM_NB_BLOCK *S3NBPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemNS3GetConPCIMaskNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   DESCRIPTOR_GROUP *DescriptPtr
+  );
+
+VOID
+MemNS3GetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN       VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetCSRNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3GetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3SetBitFieldNb (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
+VOID
+MemNS3RestoreScrubNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Node
+  );
+
+AGESA_STATUS
+MemS3InitNB (
+  IN OUT   S3_MEM_NB_BLOCK **S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT **MemPtr,
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif //_MFS3_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h
new file mode 100755
index 0000000000..30434bdb49
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mftds.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * mftds.h
+ *
+ * Memory Controller
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 5655 $ @e \$Date: 2008-04-04 12:29:23 +0800 (Fri, 04 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+#ifndef _MFTDS_H_
+#define _MFTDS_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemFInitTableDrive (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8     time
+  );
+#endif  /* _MFTDS_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h
new file mode 100755
index 0000000000..1983a7a1dd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mm.h
@@ -0,0 +1,842 @@
+/**
+ * @file
+ *
+ * mm.h
+ *
+ * Common main functions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 46768 $ @e \$Date: 2011-02-09 16:14:12 -0700 (Wed, 09 Feb 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+  *       its contributors may be used to endorse or promote products derived
+  *       from this software without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MM_H_
+#define _MM_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+#define ALLOC_SOCKET_STRUCT_HANDLE    0
+#define ALLOC_DIE_STRUCT_HANDLE       1
+#define ALLOC_DCT_STRUCT_HANDLE       2
+#define ALLOC_CHL_STRUCT_HANDLE       3
+#define ALLOC_PLATFORM_PTR_HANDLE     4
+#define ALLOC_FORM_FACTOR_HANDLE      5
+#define ALLOC_TRN_DATA_HANDLE         6
+#define ALLOC_DIMM_DATA_HANDLE        7
+#define ALLOC_PAR_TRN_HANDLE          8
+
+#define GENERATE_MEM_HANDLE(type, x, y, z) (\
+  AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \
+)
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Bit field names used in memory initialization
+typedef enum {
+  BFDevVendorIDReg,                     ///< Bit field DevVendorIDReg
+  BFNodeID,                             ///< Bit field NodeID
+  BFNodeCnt,                            ///< Bit field NodeCnt
+
+  BFDramBaseReg0,                       ///< Bit field DramBaseReg0
+  BFDramBaseReg1,                       ///< Bit field DramBaseReg1
+  BFDramBaseReg2,                       ///< Bit field DramBaseReg2
+  BFDramBaseReg3,                       ///< Bit field DramBaseReg3
+  BFDramBaseReg4,                       ///< Bit field DramBaseReg4
+  BFDramBaseReg5,                       ///< Bit field DramBaseReg5
+  BFDramBaseReg6,                       ///< Bit field DramBaseReg6
+  BFDramBaseReg7,                       ///< Bit field DramBaseReg7
+
+  BFDramLimitReg0,                      ///< Bit field DramLimitReg0
+  BFDramLimitReg1,                      ///< Bit field DramLimitReg1
+  BFDramLimitReg2,                      ///< Bit field DramLimitReg2
+  BFDramLimitReg3,                      ///< Bit field DramLimitReg3
+  BFDramLimitReg4,                      ///< Bit field DramLimitReg4
+  BFDramLimitReg5,                      ///< Bit field DramLimitReg5
+  BFDramLimitReg6,                      ///< Bit field DramLimitReg6
+  BFDramLimitReg7,                      ///< Bit field DramLimitReg7
+
+  BFDramBaseHiReg0,                     ///< Bit field DramBaseHiReg0
+  BFDramBaseHiReg1,                     ///< Bit field DramBaseHiReg1
+  BFDramBaseHiReg2,                     ///< Bit field DramBaseHiReg2
+  BFDramBaseHiReg3,                     ///< Bit field DramBaseHiReg3
+  BFDramBaseHiReg4,                     ///< Bit field DramBaseHiReg4
+  BFDramBaseHiReg5,                     ///< Bit field DramBaseHiReg5
+  BFDramBaseHiReg6,                     ///< Bit field DramBaseHiReg6
+  BFDramBaseHiReg7,                     ///< Bit field DramBaseHiReg7
+
+  BFDramLimitHiReg0,                    ///< Bit field DramLimitHiReg0
+  BFDramLimitHiReg1,                    ///< Bit field DramLimitHiReg1
+  BFDramLimitHiReg2,                    ///< Bit field DramLimitHiReg2
+  BFDramLimitHiReg3,                    ///< Bit field DramLimitHiReg3
+  BFDramLimitHiReg4,                    ///< Bit field DramLimitHiReg4
+  BFDramLimitHiReg5,                    ///< Bit field DramLimitHiReg5
+  BFDramLimitHiReg6,                    ///< Bit field DramLimitHiReg6
+  BFDramLimitHiReg7,                    ///< Bit field DramLimitHiReg7
+
+  BFDramHoleAddrReg,                    ///< Bit field DramHoleAddrReg
+
+  BFCSBaseAddr0Reg,                     ///< Bit field CSBaseAddr0Reg
+  BFCSBaseAddr1Reg,                     ///< Bit field CSBaseAddr1Reg
+  BFCSBaseAddr2Reg,                     ///< Bit field CSBaseAddr2Reg
+  BFCSBaseAddr3Reg,                     ///< Bit field CSBaseAddr3Reg
+  BFCSBaseAddr4Reg,                     ///< Bit field CSBaseAddr4Reg
+  BFCSBaseAddr5Reg,                     ///< Bit field CSBaseAddr5Reg
+  BFCSBaseAddr6Reg,                     ///< Bit field CSBaseAddr6Reg
+  BFCSBaseAddr7Reg,                     ///< Bit field CSBaseAddr7Reg
+
+  BFCSMask0Reg,                         ///< Bit field CSMask0Reg
+  BFCSMask1Reg,                         ///< Bit field CSMask1Reg
+  BFCSMask2Reg,                         ///< Bit field CSMask2Reg
+  BFCSMask3Reg,                         ///< Bit field CSMask3Reg
+
+  BFDramControlReg,                     ///< Bit field DramControlReg
+  BFDramInitRegReg,                     ///< Bit field DramInitRegReg
+  BFDramBankAddrReg,                    ///< Bit field DramBankAddrReg
+  BFDramMRSReg,                         ///< Bit field DramMRSReg
+  BFDramTimingLoReg,                    ///< Bit field DramTimingLoReg
+  BFDramTimingHiReg,                    ///< Bit field DramTimingHiReg
+  BFDramConfigLoReg,                    ///< Bit field DramConfigLoReg
+  BFDramConfigHiReg,                    ///< Bit field DramConfigHiReg
+  BFDctAddlOffsetReg,                   ///< Bit field DctAddlOffsetReg
+  BFDctAddlDataReg,                     ///< Bit field DctAddlDataReg
+  BFDctAccessDone,                      ///< Bit field DctAccessDone
+  BFDctAccessError,                     ///< Bit field DctAccessError
+  BFDctExtraOffsetReg,                  ///< Bit field DctExtraOffsetReg
+  BFDctExtraDataReg,                    ///< Bit field DctExtraDataReg
+  BFDctExtraAccessDone,                 ///< Bit field DctExtraAccessDone
+  BFDramConfigMiscReg,                  ///< Bit field DramConfigMiscReg
+  BFDramCtrlMiscReg2,                   ///< Bit field DramCtrlMiscReg2
+  BFMctCfgHiReg,                        ///< Bit field MctCfgHiReg
+  BFMctCfgLoReg,                        ///< Bit field MctCfgLoReg
+  BFExtMctCfgLoReg,                     ///< Bit field ExtMctCfgLoReg
+
+  BFDramHoleBase,                       ///< Bit field DramHoleBase
+  BFDramHoleOffset,                     ///< Bit field DramHoleOffset
+  BFDramMemHoistValid,                  ///< Bit field DramMemHoistValid
+  BFDramHoleValid,                      ///< Bit field DramHoleValid
+  BFDramBaseAddr,                       ///< Bit field DramBaseAddr
+  BFDramIntlvSel,                       ///< Bit field DramIntlvSel
+  BFDramLimitAddr,                      ///< Bit field DramLimitAddr
+  BFDramIntlvEn,                        ///< Bit field DramIntlvEn
+
+  BFMcaNbCtlReg,                        ///< Bit field McaNbCtlReg
+  BFDramEccEn,                          ///< Bit field DramEccEn
+  BFSyncOnUcEccEn,                      ///< Bit field SyncOnUcEccEn
+  BFEccSymbolSize,                      ///< Bit field EccSymbolSize
+  BFMcaNbStatusLoReg,                   ///< Bit field McaNbStatusLoReg
+  BFMcaNbStatusHiReg,                   ///< Bit field McaNbStatusHiReg
+  BFDramScrub,                          ///< Bit field DramScrub
+  BFL2Scrub,                            ///< Bit field L2Scrub
+  BFDcacheScrub,                        ///< Bit field DcacheScrub
+  BFL3Scrub,                            ///< Bit field L3Scrub
+  BFScrubReDirEn,                       ///< Bit field ScrubReDirEn
+  BFScrubAddrLoReg,                     ///< Bit field ScrubAddrLoReg
+  BFScrubAddrHiReg,                     ///< Bit field ScrubAddrHiReg
+  BFC1ClkDivisor,                       ///< Bit field C1ClkDivisor
+  BFDisDatMsk,                          ///< Bit field DisDatMsk
+  BFNbFid,                              ///< Bit field NbFid
+  BFMTC1eEn,                            ///< Bit field MTC1eEn
+  BFL3Capable,                          ///< Bit field L3Capable
+  BFF3X188B8,                           ///<
+  BFEnhMemProtCap,                      ///< Bit field EnhMemProtCap
+  BFNbPsCtrlDis,                        ///< Bit field NbPsCtrlDis
+
+  BFNonSPDHi,                           ///< Bit field NonSPDHi
+  BFRdPtrInit,                          ///< Bit field RdPtrInit
+  BFF2X78B16,                           ///<
+  BFDqsRcvEnTrain,                      ///< Bit field DqsRcvEnTrain
+  BFEarlyArbEn,                         ///< Bit field EarlyArbEn
+  BFMaxLatency,                         ///< Bit field either MaxRdLat or MaxAsyncLat
+
+  BFMrsAddress,                         ///< Bit field MrsAddress
+  BFMrsBank,                            ///< Bit field MrsBank
+  BFMrsChipSel,                         ///< Bit field MrsChipSel
+  BFSendPchgAll,                        ///< Bit field SendPchgAll
+  BFSendAutoRefresh,                    ///< Bit field SendAutoRefresh
+  BFSendMrsCmd,                         ///< Bit field SendMrsCmd
+  BFDeassertMemRstX,                    ///< Bit field DeassertMemRstX
+  BFAssertCke,                          ///< Bit field AssertCke
+  BFSendZQCmd,                          ///< Bit field SendZQCmd
+  BFSendCtrlWord,                       ///< Bit field SendCtrlWord
+  BFEnDramInit,                         ///< Bit field EnDramInit
+  BFMrsLevel,                           ///< Bit field MrsLevel
+  BFMrsQoff,                            ///< Bit field MrsQoff
+
+  BFBurstCtrl,                          ///< Bit field BurstCtrl
+  BFDrvImpCtrl,                         ///< Bit field DrvImpCtrl
+  BFDramTerm_DDR3,                      ///< Bit field DramTerm_DDR3
+  BFDramTermDyn,                        ///< Bit field DramTermDyn
+  BFQoff,                               ///< Bit field Qoff
+  BFASR,                                ///< Bit field ASR
+  BFSRT,                                ///< Bit field SRT
+  BFTcwl,                               ///< Bit field Tcwl
+  BFPchgPDModeSel,                      ///< Bit field PchgPDModeSel
+
+  BFTwrDDR3,                            ///< Bit field TwrDDR3
+  BFTcl,                                ///< Bit field Tcl
+  BFTrcd,                               ///< Bit field Trcd
+  BFTrp,                                ///< Bit field Trp
+  BFTrtp,                               ///< Bit field Trtp
+  BFTras,                               ///< Bit field Tras
+  BFTrc,                                ///< Bit field Trc
+  BFTwr,                                ///< Bit field Twr
+  BFTrrd,                               ///< Bit field Trrd
+  BFMemClkDis,                          ///< Bit field MemClkDis
+  BFDramTiming0,                        ///< Bit field BFDramTiming0
+  BFDramTiming1,                        ///< Bit field BFDramTiming1
+
+  BFNonSPD,                             ///< Bit field NonSPD
+  BFTrwtWB,                             ///< Bit field TrwtWB
+  BFTrwtTO,                             ///< Bit field TrwtTO
+  BFTwtr,                               ///< Bit field Twtr
+  BFTwrrd,                              ///< Bit field Twrrd
+  BFTwrrdHi,                            ///< Bit field TwrrdHi
+  BFTwrwr,                              ///< Bit field Twrwr
+  BFTwrwrHi,                            ///< Bit field TwrwrHi
+  BFTrdrdSD,                            ///< Bit field TrdrdSD
+  BFTwrwrSD,                            ///< Bit field TwrwrSD
+  BFTwrrdSD,                            ///< Bit field TwrrdSD
+  BFRdOdtTrnOnDly,                      ///< Bit field RdOdtTrnOnDly
+  BFRdOdtOnDuration,                    ///< Bit field RdOdtOnDuration
+  BFWrOdtTrnOnDly,                      ///< Bit field WrOdtTrnOnDly
+  BFWrOdtOnDuration,                    ///< Bit field WrOdtOnDuration
+
+  BFTrdrd,                              ///< Bit field Trdrd
+  BFTrdrdHi,                            ///< Bit field TrdrdHi
+  BFTref,                               ///< Bit field Tref
+  BFDisAutoRefresh,                     ///< Bit field DisAutoRefresh
+  BFTrfc0,                              ///< Bit field Trfc0
+  BFTrfc1,                              ///< Bit field Trfc1
+  BFTrfc2,                              ///< Bit field Trfc2
+  BFTrfc3,                              ///< Bit field Trfc3
+
+  BFInitDram,                           ///< Bit field InitDram
+  BFExitSelfRef,                        ///< Bit field ExitSelfRef
+  BFDramTerm,                           ///< Bit field DramTerm
+  BFParEn,                              ///< Bit field ParEn
+  BFBurstLength32,                      ///< Bit field BurstLength32
+  BFWidth128,                           ///< Bit field Width128
+  BFX4Dimm,                             ///< Bit field X4Dimm
+  BFDimmEccEn,                          ///< Bit field DimmEccEn
+  BFUnBuffDimm,                         ///< Bit field UnBuffDimm
+  BFEnterSelfRef,                       ///< Bit field EnterSelfRef
+  BFDynPageCloseEn,                     ///< Bit field DynPageCloseEn
+  BFIdleCycInit,                        ///< Bit field IdleCycInit
+  BFFreqChgInProg,                      ///< Bit field FreqChgInProg
+  BFForceAutoPchg,                      ///< Bit field ForceAutoPchg
+  BFEnDispAutoPrecharge,                ///< Bit field EnDispAutoPrecharge
+  BFDisDllShutdownSR,                   ///< Bit field DisDllShutdownSR
+  BFDisSscClkGateData,                  ///< Bit field DisSscClkGateData
+  BFDisSscClkGateCmdAddr,               ///< Bit field DisSscClkGateCmdAddr
+
+  BFMemClkFreq,                         ///< Bit field MemClkFreq
+  BFMemClkFreqVal,                      ///< Bit field MemClkFreqVal
+  BFDdr3Mode,                           ///< Bit field Ddr3Mode
+  BFLegacyBiosMode,                     ///< Bit field LegacyBiosMode
+  BFZqcsInterval,                       ///< Bit field ZqcsInterval
+  BFRDqsEn,                             ///< Bit field RDqsEn
+  BFDisDramInterface,                   ///< Bit field DisDramInterface
+  BFPowerDownEn,                        ///< Bit field PowerDownEn
+  BFPowerDownMode,                      ///< Bit field PowerDownMode
+  BFF2X98B17,                           ///<
+  BFDcqArbBypassEn,                     ///< Bit field DcqArbBypassEn
+  BFFourRankRDimm,                      ///< Bit field FourRankRDimm
+  BFSlowAccessMode,                     ///< Bit field SlowAccessMode
+  BFBankSwizzleMode,                    ///< Bit field BankSwizzleMode
+  BFDcqBypassMax,                       ///< Bit field DcqBypassMax
+  BFFourActWindow,                      ///< Bit field FourActWindow
+
+  BFODTSEn,                             ///< Bit field ODTSEn
+  BFCmdThrottleMode,                    ///< Bit field CmdThrottleMode
+
+  BFDdr3FourSocketCh,                   ///< Bit field Ddr3FourSocketCh
+  BFSubMemclkRegDly,                    ///< Bit field SubMemclkRegDly
+  BFOdtSwizzle,                         ///< Bit field OdtSwizzle
+  BFProgOdtEn,                          ///< Bit field ProgOdtEn
+  BFCtrlWordCS,                         ///< Bit field CtrlWordCS
+  BFDataTxFifoWrDly,                    ///< Bit field DataTxFifoWrDly
+
+  BFIntLvRgnSwapEn,                     ///< Bit field IntLvRgnSwapEn
+  BFIntLvRgnBaseAddr,                   ///< Bit field IntLvRgnBaseAddr
+  BFIntLvRgnLmtAddr,                    ///< Bit field IntLvRgnLmtAddr
+  BFIntLvRgnSize,                       ///< Bit field IntLvRgnSize
+
+  BFDctSelHiRngEn,                      ///< Bit field DctSelHiRngEn
+  BFDctSelHi,                           ///< Bit field DctSelHi
+  BFDctSelIntLvEn,                      ///< Bit field DctSelIntLvEn
+  BFMemClrInit,                         ///< Bit field MemClrInit
+  BFDctGangEn,                          ///< Bit field DctGangEn
+  BFDctDatIntLv,                        ///< Bit field DctDatIntLv
+  BFDctSelIntLvAddr,                    ///< Bit field DctSelIntLvAddr
+  BFDctSelIntLvAddrHi,                  ///< Bit field DctSelIntLvAddrHi
+  BFDramEnabled,                        ///< Bit field DramEnabled
+  BFMemClrBusy,                         ///< Bit field MemClrBusy
+  BFMemCleared,                         ///< Bit field MemCleared
+  BFDctSelBaseAddr,                     ///< Bit field DctSelBaseAddr
+  BFDctSelBaseOffset,                   ///< Bit field DctSelBaseOffset
+
+  BFAdapPrefMissRatio,                  ///< Bit field AdapPrefMissRatio
+  BFAdapPrefPosStep,                    ///< Bit field AdapPrefPosStep
+  BFAdapPrefNegStep,                    ///< Bit field AdapPrefNegStep
+  BFCohPrefPrbLmt,                      ///< Bit field CohPrefPrbLmt
+
+  BFPrefDramTrainDone,                  ///< Bit field PrefDramTrainDone
+  BFWrDramTrainMode,                    ///< Bit field WrDramTrainMode
+  BFMctPrefReqLimit,                    ///< Bit field MctPrefReqLimit
+  BFPrefDramTrainMode,                  ///< Bit field PrefDramTrainMode
+  BFDctWrLimit,                         ///< Bit field DctWrLimit
+  BFMctWrLimit,                         ///< Bit field MctWrLimit
+  BFDramTrainPdbDis,                    ///< Bit field DramTrainPdbDis
+  BFTrainLength,                        ///< Bit field TrainLength
+  BFRdTrainGo,                          ///< Bit field RdTrainGo
+  BFWrTrainGo,                          ///< Bit field WrTrainGo
+  BFWrTrainAdrPtrLo,                    ///< Bit field WrTrainAdrPtrLo
+  BFWrTrainAdrPtrHi,                    ///< Bit field WrTrainAdrPtrHi
+  BFWrTrainBufAddr,                     ///< Bit field WrTrainBufAddr
+  BFWrTrainBufDat,                      ///< Bit field WrTrainBufDat
+  BFFlushWr,                            ///< Bit field FlushWr
+  BFFlushWrOnStpGnt,                    ///< Bit field FlushWrOnStpGnt
+  BFPrefCpuDis,                         ///< Bit field PrefCpuDis
+  BFPrefIoDis,                          ///< Bit field PrefIoDis
+  BFTrainCmpSts,                        ///< Bit field TrainCmpSts
+  BFTrainCmpSts2,                       ///< Bit field TrainCmpSts2
+
+  BFAddrCmdDrvStren,                    ///< Bit field AddrCmdDrvStren
+  BFDataDrvStren,                       ///< Bit field DataDrvStren
+  BFCkeDrvStren,                        ///< Bit field CkeDrvStren
+  BFCsOdtDrvStren,                      ///< Bit field CsOdtDrvStren
+  BFClkDrvStren,                        ///< Bit field ClkDrvStren
+  BFDqsDrvStren,                        ///< Bit field DqsDrvStren
+  BFODCControl,                         ///< Bit field ODCControl
+  BFAddrTmgControl,                     ///< Bit field AddrTmgControl
+
+  BFWrtLvTrEn,                          ///< Bit field WrtLvTrEn
+  BFWrtLvTrMode,                        ///< Bit field WrtLvTrMode
+  BFPhyFenceTrEn,                       ///< Bit field PhyFenceTrEn
+  BFTrDimmSel,                          ///< Bit field TrDimmSel
+  BFFenceTrSel,                         ///< Bit field FenceTrSel
+  BFWrLvOdt,                            ///< Bit field WrLvOdt
+  BFWrLvOdtEn,                          ///< Bit field WrLvOdtEn
+  BFDqsRcvTrEn,                         ///< Bit field DqsRcvTrEn
+  BFDisAutoComp,                        ///< Bit field DisAutoComp
+  BFWrtLvErr,                           ///< Bit field WrtLvErr
+  BFODTAssertionCtl,                    ///< Bit field ODTAssertionCtl
+  BFNibbleTrainModeEn,                  ///< Bit field NibbleTrainModeEn
+  BFRankTrainModeEn,                    ///< Bit field RankTrainModeEn
+  BFPllMult,                            ///< Bit field PllMult
+  BFPllDiv,                             ///< Bit field PllDiv
+
+  BFDramPhyStatusReg,                   ///< Bit field DramPhyStatusReg
+
+  BFD3Cmp2PCal,                         ///< Bit field D3Cmp2PCal
+  BFD3Cmp2NCal,                         ///< Bit field D3Cmp2NCal
+  BFD3Cmp1PCal,                         ///< Bit field D3Cmp1PCal
+  BFD3Cmp1NCal,                         ///< Bit field D3Cmp1NCal
+  BFD3Cmp0PCal,                         ///< Bit field D3Cmp0PCal
+  BFD3Cmp0NCal,                         ///< Bit field D3Cmp0NCal
+
+  BFPhyFence,                           ///< Bit field PhyFence
+  BFODTTri,                             ///< Bit field ODTTri
+  BFCKETri,                             ///< Bit field CKETri
+  BFChipSelTri,                         ///< Bit field ChipSelTri
+  BFPhyRODTCSLow,                       ///< Bit field PhyRODTCSLow
+  BFPhyRODTCSHigh,                      ///< Bit field PhyRODTCSHigh
+  BFPhyWODTCSLow,                       ///< Bit field PhyWODTCSLow
+  BFPhyWODTCSHigh,                      ///< Bit field PhyWODTCSHigh
+  BFUSPLLCtlAll,                        ///< Bit field USPLLCtlAll
+  BFDSPLLCtlAll,                        ///< Bit field DSPLLCtlAll
+  BFUSNibbleAlignEn,                    ///< Bit field USNibbleAlignEn
+  BFChnLinitClkEn,                      ///< Bit field ChnLinitClkEn
+
+  BFTSLinkSelect,                       ///< Bit field TSLinkSelect
+  BFTS2BitLockEn,                       ///< Bit field TS2BitLockEn
+  BFTS2En,                              ///< Bit field TS2En
+  BFTS1En,                              ///< Bit field TS1En
+  BFTS0LinkStarEn,                      ///< Bit field TS0LinkStarEn
+  BFTS0En,                              ///< Bit field TS0En
+
+  BFLinkTrainData,                      ///< Bit field LinkTrainData
+
+  BFRstRxFifoPtrs,                      ///< Bit field RstRxFifoPtrs
+  BFRxFifoPtrInit,                      ///< Bit field RxFifoPtrInit
+  BFRstTxFifoPtrs,                      ///< Bit field RstTxFifoPtrs
+  BFTxFifoPtrInit,                      ///< Bit field TxFifoPtrInit
+
+  BFLpbkCount,                          ///< Bit field LpbkCount
+  BFLpbkMap,                            ///< Bit field LpbkMap
+  BFSendLpbkMaintCmd,                   ///< Bit field SendLpbkMaintCmd
+  BFLpbkData,                           ///< Bit field LpbkData
+
+  BFMbRdPtrEn,                          ///< Bit field MbRdPtrEn
+  BFLnkLpBkLat,                         ///< Bit field LnkLpBkLat
+  BFLpbkRndTripLatDone,                 ///< Bit field LpbkRndTripLatDone
+  BFLnkLatTrainEn,                      ///< Bit field LnkLatTrainEn
+
+  BFDsPhyReset,                         ///< Bit field DsPhyReset
+  BFLinkReset,                          ///< Bit field LinkReset
+
+  BFPllLockTime,                        ///< Bit field PllLockTime
+  BFPllRegWaitTime,                     ///< Bit field PllRegWaitTime
+  BFNclkFreqDone,                       ///< Bit field NclkFreqDone
+  BFNbPs0NclkDiv,                       ///< Bit field NbPs0NclkDiv
+  BFNbPs1NclkDiv,                       ///< Bit field NbPs1NclkDiv
+  BFNbPs1Act,                           ///< Bit field NbPs1Act
+
+  BFOnLineSpareControl,                 ///< Bit field OnLineSpareControl
+  BFDdrMaxRate,                         ///< Bit field DdrMaxRate
+
+  BFC6Base,                             ///< Bit field C6Base
+  BFC6DramLock,                         ///< Bit field C6DramLock
+
+  BFRxPtrInitReq,                       ///< Bit field RxPtrInitReq
+  BFTxPtrInitReq,                       ///< Bit field TxPtrInitReq
+  BFAddrCmdTriEn,                       ///< Bit field AddrCmdTriEn
+  BFForceCasToSlot0,                    ///< Bit field ForceCasToSlot0
+  BFDisCutThroughMode,                  ///< Bit field DisCutThroughMode
+  BFDbeSkidBufDis,                      ///< Bit field DbeSkidBufDis
+  BFBankSwap,                           ///< Bit field BankSwap
+  BFDbeGskMemClkAlignMode,              ///< Bit field DbeGskMemClkAlignMode
+  BFEnCpuSerRdBehindNpIoWr,             ///< Bit field EnCpuSerRdBehindNpIoWr
+  BFDbeCmdThrottle,                     ///< Bit field DbeCmdThrottle
+  BFRxDLLWakeupTime,                    ///< Bit field RxDllWakeupTime
+  BFRxCPUpdPeriod,                      ///< Bit field RxCPUpdPeriod
+  BFRxMaxDurDllNoLock,                  ///< Bit field RxMaxDurDllNoLock
+  BFTxDLLWakeupTime,                    ///< Bit field TxDllWakeupTime
+  BFTxCPUpdPeriod,                      ///< Bit field TxCPUpdPeriod
+  BFTxMaxDurDllNoLock,                  ///< Bit field TxMaxDurDllNoLock
+  BFEnRxPadStandby,                     ///< Bit field EnRxPadStandby
+
+  BFMemTempHot,                         ///< Bit field MemTempHot
+  BFDoubleTrefRateEn,                   ///< Bit field DoubleTrefRateEn
+
+  BFCpu1En,                             ///< Bit field BFCpu1En
+  BFCpu32En,                            ///< Bit field BFCpu32En
+  BFAcpiPwrStsCtrlHi,                   ///< Bit field BFAcpiPwrStsCtrlHi
+  BFDramSrHysEn,                        ///< Bit field BFDramSrHysEn
+  BFDramSrHys,                          ///< Bit field BFDramSrHys
+  BFMemTriStateEn,                      ///< Bit field BFMemTriStateEn
+  BFDramSrEn,                           ///< Bit field BFDramSrEn
+
+  /* Bit fields for workarounds */
+  BFErr263,                             ///< Bit field Err263
+  BFErr350,                             ///< Bit field Err350
+  BFErr322I,                            ///< Bit field Err322I
+  BFErr322II,                           ///< Bit field Err322II
+
+  /* Bit fields for Phy */
+  BFEccDLLConf,                         ///< Bit field EccDLLConf
+  BFEccDLLPwrDnConf,                    ///< Bit field EccDLLPwrDnConf
+  BFPhyPLLLockTime,                     ///< Bit field PhyPLLLockTime
+  BFPhyDLLLockTime,                     ///< Bit field PhyDLLLockTime
+  BFPhyDLLControl,                      ///< Bit field BFPhyDLLControl
+  BFPhy0x0D080F0C,                      ///< Bit field BFPhy0x0D080F0C
+  BFPhy0x0D080F10,                      ///< Bit field BFPhy0x0D080F10
+  BFPhy0x0D080F11,                      ///< Bit field BFPhy0x0D080F11
+  BFPhy0x0D088F30,                      ///< Bit field BFPhy0x0D088F30
+  BFPhy0x0D08C030,                      ///< Bit field BFPhy0x0D08C030
+  BFPhy0x0D082F30,                      ///< Bit field BFPhy0x0D082F30
+
+  BFPhy0x0D040F3E,                      ///< Bit field BFPhy0x0D040F3E
+  BFPhy0x0D042F3E,                      ///< Bit field BFPhy0x0D042F3E
+  BFPhy0x0D048F3E,                      ///< Bit field BFPhy0x0D048F3E
+  BFPhy0x0D04DF3E,                      ///< Bit field BFPhy0x0D04DF3E
+
+  BFPhyClkConfig0,                    ///< Bit field ClkConfig0
+  BFPhyClkConfig1,                    ///< Bit field ClkConfig1
+  BFPhyClkConfig2,                    ///< Bit field ClkConfig2
+  BFPhyClkConfig3,                    ///< Bit field ClkConfig3
+
+  BFPhy0x0D0F0F13,                      ///< Bit field BFPhy0x0D0F0F13
+  BFPhy0x0D0F0F13Bit0to7,               ///< Bit field BFPhy0x0D0F0F13Bit0to7
+  BFPhy0x0D0F0830,                      ///< Bit field BFPhy0x0D0F0830
+  BFPhy0x0D07812F,                      ///< Bit field BFPhy0x0D0F8108
+
+  BFDataRxVioLvl,                       ///< Bit field DataRxVioLvl
+  BFClkRxVioLvl,                        ///< Bit field ClkRxVioLvl
+  BFCmdRxVioLvl,                        ///< Bit field CmdRxVioLvl
+  BFAddrRxVioLvl,                       ///< Bit field AddrRxVioLvl
+  BFCmpVioLvl,                          ///< Bit field CmpVioLvl
+  BFAlwaysEnDllClks,                    ///< Bit field AlwaysEnDllClks
+  BFPhy0x0D0FE00A,                      ///< Bit field Phy0x0D0FE00A
+
+  BFDataFence2,                         ///< Bit field DataFence2
+  BFClkFence2,                          ///< Bit field ClkFence2
+  BFCmdFence2,                          ///< Bit field CmdFence2
+  BFAddrFence2,                         ///< Bit field AddrFence2
+
+  BFAddrCmdTri,                         ///< Bit field BFAddrCmdTri
+  BFLowPowerDrvStrengthEn,              ///< Bit field BFLowPowerDrvStrengthEn
+  BFLevel,                              ///< Bit field Level
+
+  BFDbeGskFifoNumerator,                ///< Bit field DbeGskFifoNumerator
+  BFDbeGskFifoDenominator,              ///< Bit field DbeGskFifoDenominator
+  BFDataTxFifoSchedDlyNegSlot0,         ///< Bit field DataTxFifoSchedDlyNegSlot0
+  BFDataTxFifoSchedDlyNegSlot1,         ///< Bit field DataTxFifoSchedDlyNegSlot1
+  BFDataTxFifoSchedDlySlot0,            ///< Bit field DataTxFifoSchedDlySlot0
+  BFDataTxFifoSchedDlySlot1,            ///< Bit field DataTxFifoSchedDlySlot1
+
+  BFDisablePredriverCal,                ///< Bit field DisablePredriverCal
+  BFDataByteTxPreDriverCal,             ///< Bit field DataByteTxPreDriverCal
+  BFDataByteTxPreDriverCal2Pad1,        ///< Bit field DataByteTxPreDriverCal2Pad1
+  BFDataByteTxPreDriverCal2Pad2,        ///< Bit field DataByteTxPreDriverCal2Pad2
+  BFCmdAddr0TxPreDriverCal2Pad1,        ///< Bit field CmdAddr0TxPreDriverCal2Pad1
+  BFCmdAddr0TxPreDriverCal2Pad2,        ///< Bit field CmdAddr0TxPreDriverCal2Pad2
+  BFCmdAddr1TxPreDriverCal2Pad1,        ///< Bit field CmdAddr1TxPreDriverCal2Pad1
+  BFCmdAddr1TxPreDriverCal2Pad2,        ///< Bit field CmdAddr1TxPreDriverCal2Pad2
+  BFAddrTxPreDriverCal2Pad1,            ///< Bit field AddrTxPreDriverCal2Pad1
+  BFAddrTxPreDriverCal2Pad2,            ///< Bit field AddrTxPreDriverCal2Pad2
+  BFAddrTxPreDriverCal2Pad3,            ///< Bit field AddrTxPreDriverCal2Pad3
+  BFAddrTxPreDriverCal2Pad4,            ///< Bit field AddrTxPreDriverCal2Pad4
+  BFCmdAddr0TxPreDriverCalPad0,         ///< Bit field CmdAddr0TxPreDriverCalPad0
+  BFCmdAddr1TxPreDriverCalPad0,         ///< Bit field CmdAddr1TxPreDriverCalPad0
+  BFAddrTxPreDriverCalPad0,             ///< Bit field AddrTxPreDriverCalPad0
+  BFClock0TxPreDriverCalPad0,           ///< Bit field Clock0TxPreDriverCalPad0
+  BFClock1TxPreDriverCalPad0,           ///< Bit field Clock1TxPreDriverCalPad0
+
+  // Reserved
+  BFReserved01,                         ///< Reserved 01
+  BFReserved02,                         ///< Reserved 02
+  BFReserved03,                         ///< Reserved 03
+  BFReserved04,                         ///< Reserved 04
+  BFReserved05,                         ///< Reserved 05
+  BFReserved06,                         ///< Reserved 06
+  BFReserved07,                         ///< Reserved 07
+  BFReserved08,                         ///< Reserved 08
+  BFReserved09,                         ///< Reserved 09
+  BFReserved10,                         ///< Reserved 10
+  BFDctSelBaseAddrReg,                  ///< Bit field DctSelBaseAddrReg
+  BFDctSelBaseOffsetReg,                ///< Bit field DctSelBaseOffsetReg
+
+  /* End of accessible list --- entries below this line are for private use ------------*/
+  BFEndOfList,                          ///< End of bit field list
+
+  // Only for Table Drive Support define.
+  BFRcvEnDly,       ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers
+  BFWrDatDly,       ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers
+  BFRdDqsDly,       ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers
+  BFWrDqsDly,       ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers
+  BFPhRecDly,       ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers
+
+  /* Do not define any entries beyond this point */
+  BFAbsLimit                            ///< Beyond this point is reserved for bit field manipulation
+
+} BIT_FIELD_NAME;
+
+/// Bit field aliases
+#define BFMainPllOpFreqId       BFNbFid
+#define BFRdDramTrainMode       BFPrefDramTrainMode
+#define BFThrottleEn            BFCmdThrottleMode
+#define BFIntlvRegionEn         BFIntLvRgnSwapEn
+#define BFIntlvRegionBase       BFIntLvRgnBaseAddr
+#define BFIntlvRegionLimit      BFIntLvRgnLmtAddr
+#define BFRdOdtPatReg           BFPhyRODTCSLow
+#define BFWrOdtPatReg           BFPhyWODTCSLow
+
+/// Bit field names per DRAM CS base address register
+typedef enum {
+  BFCSEnable = 0,               ///< Chip select enable
+  BFSpare = 1,                  ///< Spare rank
+  BFTestFail = 2,               ///< Memory test failed
+  BFOnDimmMirror = 3            ///< on-DIMM mirroring enable
+} CS_BASE_BIT_FIELD;
+
+/// Flag for exclude dimm
+typedef enum {
+  NORMAL,                       ///< Normal mode, exclude the dimm if there is new dimm failure
+  TRAINING,                     ///< Training mode, exclude dimms that fail during training after training is done
+  END_TRAINING                  ///< End training mode, exclude all dimms that failed during training
+} DIMM_EXCLUDE_FLAG;
+
+#define BSP_DIE   0
+#define MAX_NODES_SUPPORTED     8   ///< Maximum number of nodes in the system.
+#define MAX_CS_PER_CHANNEL      8   ///< Max CS per channel
+#define MAX_CS_PER_DELAY        2   ///< Max Chip Select Controlled by a set of delays.
+
+///
+/// MEM_SHARED_DATA
+/// This structure defines the shared data area that is used by the memory
+/// code to share data between different northbridge objects. Each substructure
+/// in the data area defines how this data area is used by a different purpose.
+///
+/// There should only be one instance of this struct created for all of the memory
+/// code to use.
+///
+typedef struct _MEM_SHARED_DATA {
+
+  // System memory map data
+  UINT32  CurrentNodeSysBase;       ///< Base[47:16] (system address) DRAM base address for current node.
+  /// Memory map data for each node
+  BOOLEAN AllECC; ///< ECC support on the system
+  DIMM_EXCLUDE_FLAG DimmExcludeFlag;  ///< Control the exclude dimm behavior
+  UINT8 VoltageMap; ///< The commonly supported voltage map in the system
+
+  /// Data structure for node map
+  struct {
+    BOOLEAN IsValid;                ///< TRUE if this node contains memory.
+    UINT32  SysBase;                ///< Base[47:16] (system address) DRAM base address of this node.
+    UINT32  SysLimit;               ///< Base[47:16] (system address) DRAM limit address of this node.
+  } NodeMap[MAX_NODES_SUPPORTED];
+  BOOLEAN UndoHoistingAbove1TB;     ///< Undo hoisting above 1TB
+
+  /// Data structure for node interleave feature
+  struct {
+    BOOLEAN IsValid;                ///< TRUE if the data in this structure is valid.
+    UINT8   NodeCnt;                ///< Number of nodes in the system.
+    UINT32  NodeMemSize;            ///< Total memory of this node.
+    UINT32  Dct0MemSize;            ///< Total memory of this DCT 0.
+    UINT8   NodeIntlvSel;           ///< Index to each node.
+  } NodeIntlv;
+} MEM_SHARED_DATA;
+
+///
+/// MEM_MAIN_DATA_BLOCK
+///
+typedef struct _MEM_MAIN_DATA_BLOCK {
+  struct _MEM_DATA_STRUCT *MemPtr;          ///< Pointer to customer shared data
+  struct _MEM_NB_BLOCK    *NBPtr;           ///< Pointer to array of NB Blocks
+  struct _MEM_TECH_BLOCK  *TechPtr;         ///< Pointer to array of Tech Blocks
+  struct _MEM_SHARED_DATA *mmSharedPtr;     ///< Pointer to shared data area.
+  UINT8           DieCount;                 ///< Total number of Dies installed
+} MEM_MAIN_DATA_BLOCK;
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+node: Indicates the Node
+- Value ranges from 0-7, 0xF: for all nodes
+- Size - 4 Bits
+
+dct: Indicate the DRAM Controller
+- Value is 0, 1 (0xF: apply setting to all DCTs)
+- Size - 4 Bits
+
+dimm: This values specifies which DIMM register will be applied
+- The value varies from 0 to 3, 0xF: all DIMMs
+- Size - 4 Bits
+
+attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed)
+- 0: Do not change the current value in the register
+- 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined)
+- 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
+- 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
+- Size - 2 Bits
+
+time - Indicate the timing for the register which is written.
+- 0:  Write register value before Dram init
+- 1:  Write register value before memory training
+- 2:  Write register value after memory training
+- Size - 1 Bits
+
+bytelane: bytelane number
+- This determines specifies which bytelane register will be applied
+- Bit0 =1 - set value into Bytelane0
+- Bit1 =1 - set value into Bytelane1
+- Bit2 =1 - set value into Bytelane2
+...
+...
+- 0xFFFF: all bytelane
+- Size - 16 Bits.
+
+bfIndex: Indicate the bitfield index
+- Size - 16 Bits
+
+value - Value to be used
+- This can be an offset (sub or Add) or an override value.
+- Size - DWORD
+*/
+
+// Sample code
+// NBACCESS (MTBeforeDInit, MTNodes,  MTDct0, BFCSBaseAddr5Reg, MTOverride,   0x400001),
+// NBACCESS (MTBeforeTrn,   MTNodes,  MTDct1, BFCSBaseAddr7Reg, MTOverride,   0xFFFFFFFF),
+// DQSACCESS (MTAfterTrn,    MTNodes,  MTDcts, MTDIMM0,  MTBL1+MTBL2,    BFRcvEnDly, MTSubtract,   2),
+// DQSACCESS (MTAfterTrn,    MTNodes,  MTDct1, MTDIMM1,  MTBLNOECC,      BFRcvEnDly, MTAdd,        1),
+
+#define ENDMEMTDS  0, 0, 0, 0, 0, 0, 0xFFFFFFFF, 0
+
+#define NBACCESS(time, node, dct, bitfield, attr, value) \
+{ (time), \
+  ((node) & 0x0F) | ((dct) << 4), \
+  (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \
+  (UINT8)((bitfield) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 8)  & 0x000000FF), \
+  (UINT8)(((bitfield) >> 16) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 24) & 0x000000FF), \
+  0, 0, \
+  (UINT8)((value) & 0x000000FF), \
+  (UINT8)(((value) >> 8)  & 0x000000FF), \
+  (UINT8)(((value) >> 16) & 0x000000FF), \
+  (UINT8)(((value) >> 24) & 0x000000FF), \
+  0, 0, 0 \
+}
+
+#define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \
+{ (time), \
+  ((node) & 0x0F) | ((dct) << 4), \
+  (((dimm) & 0x0F)  | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \
+  (UINT8)((bitfield) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 8)  & 0x000000FF), \
+  (UINT8)(((bitfield) >> 16) & 0x000000FF), \
+  (UINT8)(((bitfield) >> 24) & 0x000000FF), \
+  (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \
+}
+
+/// Type of modification supported by table driven support.
+typedef enum {
+  MTAuto,                       ///<  Do not change the current value in the register
+  MTOverride,                   ///<  Use the value provided in the table to override the current value in the register
+  MTSubtract,                   ///<  Subtract the value provided in the table as an offset to the current value in the register
+  MTAdd                         ///<  Add the value provided in the table as an offset to the current value in the reg
+} MTAttr;
+
+/// Time for table driven support to make modification.
+typedef enum {
+  MTAfterAutoCycTiming,         ///<  After Auto Cycle Timing
+  MTAfterPlatformSpec,          ///<  After Platform Specific Configuration
+  MTBeforeDInit,                ///<  Before Dram init
+  MTBeforeTrn,                  ///<  Before memory training
+  MTAfterTrn,                   ///<  After memory training
+  MTAfterSwWLTrn,               ///<  After SW Based WL Training
+  MTAfterHwWLTrnP1,             ///<  After HW Based WL Training Part 1
+  MTAfterHwRxEnTrnP1,           ///<  After HW Based Receiver Enable Training Part 1
+  MTAfterHwWLTrnP2,             ///<  After HW Based WL Training Part 2
+  MTAfterHwRxEnTrnP2,           ///<  After HW Based Receiver Enable Training Part 2
+  MTAfterSwRxEnTrn,             ///<  After SW Based Receiver Enable Training
+  MTAfterDqsRwPosTrn,           ///<  After DQS Read/Write Position Training
+  MTAfterMaxRdLatTrn,           ///<  After Max Read Latency Training
+  MTAfterNbPstateChange,        ///<  After programming NB Pstate dependent registers
+  MTEnd = 0xFF ///< End of enum define.
+} MTTime;
+
+/// Node on which modification should be made by table driven support.
+typedef enum {
+  MTNode0, ///< Node 0.
+  MTNode1, ///< Node 1.
+  MTNode2, ///< Node 2.
+  MTNode3, ///< Node 3.
+  MTNode4, ///< Node 4.
+  MTNode5, ///< Node 5.
+  MTNode6, ///< Node 6.
+  MTNode7, ///< Node 7.
+  MTNodes = 0xF                   ///<  all nodes
+} MTNode;
+
+/// DCT on which modification should be made by table driven support.
+typedef enum {
+  MTDct0, ///< DCT 0.
+  MTDct1, ///< DCT 1.
+  MTDcts = 0xF,                   ///<  all dcts
+} MTDct;
+
+/// Dimm on which modification should be made by table driven support.
+typedef enum {
+  MTDIMM0, ///< Dimm 0.
+  MTDIMM1, ///< Dimm 1.
+  MTDIMM2, ///< Dimm 2.
+  MTDIMM3, ///< Dimm 3.
+  MTDIMMs = 0xF,                  ///<  all Dimms
+} MTDIMM;
+
+/// Bytelane on which modification should be made by table driven support.
+typedef enum {
+  MTBL0 = 0x1,                    ///<  set the value into Bytelane0
+  MTBL1 = 0x2,                    ///<  set the value into Bytelane1
+  MTBL2 = 0x4,                    ///<  set the value into Bytelane2
+  MTBL3 = 0x8,                    ///<  set the value into Bytelane3
+  MTBL4 = 0x10, ///< set the value into Bytelane4
+  MTBL5 = 0x20, ///< set the value into Bytelane5
+  MTBL6 = 0x40, ///< set the value into Bytelane6
+  MTBL7 = 0x80, ///< set the value into Bytelane7
+  MTBL8 = 0x100,                  ///<  set the value into ECC
+  MTBLNOECC = 0xFF,               ///<  all Bytelanes except ECC
+  MTBLs = 0xFFFF,                 ///<  all Bytelanes
+} MTBL;
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+MemAmdFinalize (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+MemSocketScan (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
+VOID
+SetMemError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  );
+
+VOID
+AmdMemInitDataStructDefRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemRecDefRet (VOID);
+
+VOID
+SetMemRecError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  );
+
+#endif  /* _MM_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
new file mode 100755
index 0000000000..8f636c770a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mn.h
@@ -0,0 +1,1059 @@
+/**
+ * @file
+ *
+ * mn.h
+ *
+ * Common Northbridge
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 46999 $ @e \$Date: 2011-02-12 01:18:16 -0700 (Sat, 12 Feb 2011) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MN_H_
+#define _MN_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define _4GB_RJ16           (((UINT32) 4) << (30 - 16))
+#define _1TB_RJ16           (((UINT32) 1) << (40 - 16))
+#define HT_REGION_BASE_RJ16 ((UINT32)0x00FD0000)
+
+#define DCT_ACCESS_WRITE (UINT32) 0x40000000
+#define MTRR_VALID  11
+
+
+#define NB_ACCESS       0
+#define DCT_PHY_ACCESS  1
+#define DCT_EXTRA       2
+
+#define VT_MSK_VALUE 0
+#define VT_ARRAY     1
+
+/*---------------------------------------------
+ *   TSEFO - Type Start End Function Offset
+ *
+ *   31:30   Type of access      (2-bits)
+ *   29:29   Special             (1-bit)
+ *   29:27   Reserved            (2-bits)
+ *   26:26   Linked              (1-bit)
+ *   25:21   Start bit           (5-bits)
+ *   20:16   End bit             (5-bits)
+ *   15:00   Function_Offset/Index  (16-bits)
+ *---------------------------------------------
+ */
+typedef UINT32 TSEFO;
+
+/**
+  MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex):
+
+  @param[in]    TableName
+  @param[in]    BitFieldIndex
+  @param[in]    a  Type of access.
+  @param[in]    b  Index of register (can be in Function_Offset format).
+  @param[in]    c  Highest bit of the bit field.
+  @param[in]    d  Lowest bit of the bit field.
+
+  @return   TSEFO  Access params encrypted in TSEFO format.
+--*/
+#define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \
+TableName[BitFieldIndex] = ( \
+  (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \
+    (((UINT32) b) >> 16) ? ( \
+      (((UINT32) 1) << 29) \
+    ) : ( \
+      (c >= d) ? ( \
+        (((UINT32) c) << 21) | (((UINT32) d) << 16) \
+      ) : ( \
+        (((UINT32) d) << 21) | (((UINT32) c) << 16) \
+      ) \
+    ) \
+  ) \
+)
+
+/**
+  LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex):
+  This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex,
+                        but NOT the other way around.
+  Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex.
+
+  @param[in]    TableName
+  @param[in]    LowerBitFieldIndex
+  @param[in]    HigherBitFieldIndex
+
+  @return   TSEFO  Access params encrypted in TSEFO format.
+--*/
+#define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \
+  ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \
+  TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \
+}
+
+#define TSEFO_TYPE(x)  ((UINT8) (((UINT32) (x) >> 30) & 0x03))
+#define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F))
+#define TSEFO_END(x)   ((UINT8) (((UINT32) (x) >> 16) & 0x1F))
+#define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF)
+#define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01))
+#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y))
+#define _NOT_USED_ 0
+
+/* */
+#define B0_DLY   0
+#define B1_DLY   1
+#define B2_DLY   2
+#define B3_DLY   3
+#define B4_DLY   4
+#define B5_DLY   5
+#define B6_DLY   6
+#define B7_DLY   7
+#define ECC_DLY  8
+
+#define DDR2_TRAIN_FLOW 0
+#define DDR3_TRAIN_FLOW 1
+
+//
+// Minimum Data Eye width in consecutive 32nds of a UI of
+// valid data
+//
+#define MIN_RD_DATAEYE_WIDTH_NB 4
+#define MIN_WR_DATAEYE_WIDTH_NB 4
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// DQS training related delays
+typedef enum {
+  AccessRcvEnDly,                       ///< Receiver enable delay
+  AccessWrDatDly,                       ///< Write data delay
+  AccessRdDqsDly,                       ///< Read DQS delay
+  AccessWrDqsDly,                       ///< Write DQS delay
+  AccessPhRecDly                        ///< Phase recovery delay
+} TRN_DLY_TYPE;
+
+/// Training patterns for position training
+typedef enum {
+  POS_PATTERN_72B,                      ///< 72 bit pattern
+  POS_PATTERN_256B,                     ///< 256 bit pattern
+} POS_TRN_PATTERN_TYPE;
+
+/// ODT mode
+typedef enum {
+  MISSION_MODE,                         ///< ODT during mission mode
+  WRITE_LEVELING_MODE                   ///< ODT during write leveling
+} ODT_MODE;
+
+/*
+ *   DRBN - Dimm-Rank-Byte-Nibble
+ *   31:12   Reserved
+ *   11:09   Dimm       (3-bits)
+ *   08      Rank       (1-bit)
+ *   07:05   Reserved
+ *   04:01   Byte       (4-bits)
+ *   00      Nibble     (1-bit)
+ */
+typedef UINT32 DRBN;
+#define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \
+(((UINT32) (byte)) << 1) | ((UINT32) (nibble)) )
+#define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1))
+#define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble)))
+#define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07))
+#define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01))
+#define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F))
+#define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01))
+
+/* Dimm Type mask */
+#define DT_X4       0x01
+#define DT_X8       0x02
+#define DT_X16      0x04
+#define DT_SR       0x10
+#define DT_DR       0x20
+#define DT_QR       0x40
+
+#define DT_ANY_X4   0x71
+#define DT_ANY_X8   0x72
+#define DT_ANY_X16  0x74
+#define DT_ANY_SR   0x17
+#define DT_ANY_DR   0x27
+#define DT_ANY_QR   0x47
+#define DT_ANY_SR_DR    (DT_ANY_SR | DT_ANY_DR)
+#define DT_ANY          (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR)
+
+/// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type
+///
+typedef struct _TRN_DLY_PARMS {
+  UINT8  Min;    ///< Minimum Value
+  UINT8  Max;    ///< Maximum Value
+  UINT8  Mask;   ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.)
+} TRN_DLY_PARMS;
+
+/// Structure for certain data saving needed for DCT.
+typedef struct {
+  UINT8  RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts
+  UINT32 PhRecReg[3];     ///< 3 Phase recovery control registers
+} MEM_DCT_CACHE;
+
+/// Structure for table driven support.
+typedef struct _MEM_TBL_ALIAS {
+  UINT8  time;            ///< Modification time.
+  UINT8  node:4;          ///< Node on which to make modification.
+  UINT8  dct:4;           ///< DCT on which to make modification.
+  UINT8  dimm:4;          ///< Dimm on which to make modification.
+  UINT8  attr:3;          ///< Attribute of modification.
+  UINT8  vtype:1;         ///< Flag indicating value type.
+  UINT32 bfindex;         ///< Bit field index that need to be modified.
+  union {                 ///< Union is defined to easy select between single and multiple bytelane cases.
+    struct {              ///< Sub-struct used for one bytelane value.
+      UINT16 bytelane:16; ///< Bytelane on which to make modification.
+      UINT32 value;       ///< Modified value.
+      UINT8 reserved[3];  ///< Reserved for this purpose
+    } s;                  ///< single value to one or multiple bytelanes
+    UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values
+  } data;
+} MEM_TABLE_ALIAS;
+
+/// Structure for Platform Specific Block.
+typedef struct _MEM_PS_BLOCK {
+  UINT8 DramTerm; ///< Dram Term
+  UINT8 QR_DramTerm; ///< Dram Term for QR
+  UINT8 DynamicDramTerm; ///< Dynamic Dram Term
+  /* PUBLIC functions */
+  BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info.
+  VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population.
+} MEM_PS_BLOCK;
+
+/// Structure parameters needed in frequency change of client NB.
+typedef struct _MEM_FREQ_CHANGE_PARAM {
+  UINT16 PllLockTimeDefault; ///< Default PllLockTime
+  UINT8  RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher
+  UINT8  RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz
+  UINT8  NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2
+  UINT8  MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2
+} MEM_FREQ_CHANGE_PARAM;
+
+/// List for NB items that are supported
+typedef enum {
+  SetSpareEn,                      ///< Sets spare enable
+  CheckSpareEn,                    ///< Spare enabled
+  SetDllShutDown,                  ///< Sets DllShutDown
+  CheckEccDLLPwrDnConfig,          ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted
+  DimmBasedOnSpeed,                ///< Checks to determine if Dimm number needs to be adjusted based on speed
+  CheckMaxDramRate,                ///< Checks to determine the maximum rate
+  Check1GAlign,                    ///< Checks to determine if 1 GB alignment is supported
+  DramModeBeforeDimmPres,          ///< Check to determine if DRAM mode needs to be set before dimm presence
+  DramModeAfterDimmPres,           ///< Check to determine if DRAM mode needs to be set after dimm presence
+  CheckClearOnDimmMirror,          ///< Check to determine if we need to clear on DIMM mirror
+  CheckDisDllShutdownSR,           ///< Check to determine if DisDllShutdown needs to be set
+  CheckMemClkCSPresent,            ///< Check to determine if chipselect needs to be set based on disabled memclocks
+  CheckChangeAvgValue,             ///< Check to determine if we need to change average value
+  CheckMaxRdDqsDlyPtr,             ///< Check to determine change Max Rd Dqs Delay
+  CheckPhyFenceTraining,           ///< Check to determine if we need to Phy Fence training
+  CheckGetMCTSysAddr,              ///< Check to determine if we need to GetMCTSysAddr
+  CheckSendAllMRCmds,              ///< Check to determine if we need to SendAllMRCmds
+  CheckFindPSOverideWithSocket,    ///< Check to determine if we need to Find PSOveride With Socket
+  CheckFindPSDct,                  ///< Check to determine if we need to Find PSOveride With DCT
+  CheckODTControls,                ///< Check to determine if we need to set ODT controls
+  CheckDummyCLRead,                ///< Check to determine if an extra dummy read is required
+  CheckDllStdBy,                   ///< Check to determine if setting DLL stand by is required
+  CheckDynamicDramTerm,            ///< Check to determine if setting of Dynamic Dram term is required
+  CheckSlewWithMarginImprv,        ///< Check to determine if setting of Slew With MarginImprv is required
+  CheckSlewWithoutMarginImprv,     ///< Check to determine if setting of Slew Without MarginImprv is required
+  CheckDllSpeedUp,                 ///< Check to determine if setting of Dll SpeedUp is required
+  CheckDllRegDis,                  ///< Check to determine if setting of DLL Regulator Disable is required
+  FenceTrnBeforeDramInit,          ///< Check to determine if fence training has been done before Dram init
+  WLSeedAdjust,                    ///< Check to determine if WL seed needs to be adjusted
+  ClientNbFence,                   ///< Check to determine if Phy fence is of client NB
+  ForceEnMemHoleRemapping,         ///< Check to determine if we need to force enabling memory hole remapping
+  EnumSize                         ///< Size of list
+} NB_SUPPORTED;
+
+/// List for family specific functions that are supported
+typedef enum {
+  ForceLvDimmVoltage,              ///< Force LVDIMM voltage to 1.5V
+
+  NumberOfHooks                    ///< Size of list
+} FAMILY_SPECIFIC_FUNC_INDEX;
+
+///< Entry for SPD Timing
+typedef struct {
+  BIT_FIELD_NAME BitField;  ///< Bit field name of the timing
+  UINT8 Min; ///< Minimum value for timing
+  UINT8 Max; ///< Maximum value for timing
+  UINT8 Bias; ///< Bias from actual value
+  UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2)
+} CTENTRY;
+
+/// Structure for northbridge block.
+typedef struct _MEM_NB_BLOCK {
+  MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT.
+  MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT.
+  DIE_STRUCT *MCTPtr;             ///< point to current Node's MCT struct
+  DCT_STRUCT *DCTPtr;             ///< point to current Node's DCT struct
+  DCT_STRUCT *AllDCTPtr;          ///< point to all Node's DCT structs
+  CH_DEF_STRUCT *ChannelPtr;       ///< point to current channel data
+  SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT.
+  struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block.
+  struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block.
+  struct _MEM_SHARED_DATA *SharedPtr;     ///< Pointer to Memory scratchpad area
+  SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system.
+  DIE_STRUCT *AllNodeMCTPtr;      ///< point to all Node's MCT structs
+  UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode.
+  MEM_PS_BLOCK *PsPtr; ///< point to platform specific block
+  MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node.
+  MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change.
+
+  PCI_ADDR PciAddr;                ///< PCI address for this node
+  TSEFO NBRegTable[BFEndOfList];         ///< contains all bit field definitions
+
+  UINT8 Node; ///< current node.
+  UINT8 Dct; ///< current DCT.
+  UINT8 Channel; ///< current channel.
+  UINT8 DctCount; ///< number of DCTs on the current NB.
+  UINT8 ChannelCount; ///< number of channels per DCT of the current NB.
+  UINT8 NodeCount; ///< number of Nodes supported
+  BOOLEAN Ganged; ///< mode for current MCT controller.
+  POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training.
+  BOOLEAN MemCleared; ///< memory clear flag.
+  UINT32  CPGInit; ///< continuous pattern generation flag.
+  UINT16  StartupSpeed; ///< startup speed for DDR3.
+  UINT16  RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take.
+  UINT32 McaNbCtlReg; ///< reserve MCA reports.
+  UINT32 VarMtrrHiMsk;   ///< variable MTRR mask for upper 32 bits.
+  UINT32 NBClkFreq; ///< Current NB Clock frequency
+  UINT8  DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr
+
+  MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE.
+  MEM_DCT_CACHE *DctCachePtr;    ///< pointer to current Node's Node struct
+
+  /* Temporary storage */
+  BOOLEAN   ClToNbFlag;        ///< is used to restore ClLinesToNbDis bit after memory
+  UINT8  NBPstate;             ///< Current NB Pstate
+
+  ///< Determines if code should be executed on a give NB
+  BOOLEAN IsSupported[EnumSize];
+  BOOLEAN (*FamilySpecificHook[NumberOfHooks]) (struct _MEM_NB_BLOCK *NBPtr, VOID *OptParam);   ///< This array of pointers point to
+                                                                                                ///< family specific functions.
+
+  /* PUBLIC functions */
+  VOID (*SwitchDCT) (struct _MEM_NB_BLOCK *NBPtr, UINT8 DCT); ///< Switch to current DCT.
+  VOID (*SwitchChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Channel); ///< Switch to current channel.
+  VOID (*SetMaxLatency) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxRcvEnDly); ///< Set Max Rd Latency.
+  VOID (*getMaxLatParams) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxDlyForMaxRdLat, UINT16 *MinDly, UINT16 *MaxDly, UINT16 *DlyBias); ///< retrieves the Max latency parameters.
+  BOOLEAN (*GetSysAddr) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver, UINT32 *Addr); ///< Get system address for training dimm.
+  BOOLEAN (*RankEnabled) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver); ///< Check if a rank has been enabled.
+  BOOLEAN (*InitializeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< MCT initialization.
+  BOOLEAN (*FinalizeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< sets final values in BUCFG and BUCFG2.
+  BOOLEAN (*InitMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< main entry call for memory initialization.
+  VOID (*SendMrsCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send MRS command.
+  VOID (*sendZQCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send ZQ command.
+  BOOLEAN (*TrainingFlow) (struct _MEM_NB_BLOCK *NBPtr); ///< Set the training flow control
+  VOID (*WritePattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT8 Pattern[], UINT16 ClCount); ///< Write training pattern.
+  VOID (*ReadPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT32 Address, UINT16 ClCount); ///< Read training pattern.
+  VOID (*GenHwRcvEnReads) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address);  ///< generates a continuous burst of reads during HW RcvEn training.
+  UINT16 (*CompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern.
+  UINT16 (*InsDlyCompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern using 1 beat offset to check for insertion delay
+  BOOLEAN (*StitchMemory) (struct _MEM_NB_BLOCK *NBPtr); ///< combines all the memory into a contiguous map.
+  VOID (*ProgramCycTimings) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with SPD timings.
+  BOOLEAN (*AutoConfig) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with configuration parameters
+  BOOLEAN (*PlatformSpec) (struct _MEM_NB_BLOCK *NBPtr); ///< programs platform specific parameters.
+  VOID (*DisableDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< disable a DCT if no dimm presents.
+  VOID (*StartupDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< start a DCT.
+  VOID (*SyncTargetSpeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Check and sync the target speed of all channels of this node.
+  VOID (*ChangeFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Frequency change sequence.
+  BOOLEAN (*RampUpFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change frequency to the next supported level.
+  BOOLEAN (*ChangeNbFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change NB frequency.
+  VOID (*PhyFenceTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy fence training.
+  BOOLEAN (*SyncDctsReady) (struct _MEM_NB_BLOCK *NBPtr); ///< Synchronize DCTs.
+  BOOLEAN (*HtMemMapInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Memory map initialization.
+  VOID (*SyncAddrMapToAllNodes) (struct _MEM_NB_BLOCK *NBPtr); ///< copies the Node 0 map to all the other nodes.
+  BOOLEAN (*CpuMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting.
+  VOID (*BeforeDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed before DQS training.
+  VOID (*AfterDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed after DQS training.
+  BOOLEAN (*OtherTiming) (struct _MEM_NB_BLOCK *NBPtr); ///< setting non-spd timing.
+  VOID (*UMAMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting needed for UMA platform.
+  VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support.
+  UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket.
+  VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT.
+  UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training.
+  VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node.
+  VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB.
+  VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size.
+  VOID (*GetTrainDlyParms) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, TRN_DLY_PARMS *Parms); ///< Retrieve Specific Delay range info for current NB under current conditions.
+  AGESA_STATUS (*TrainingPatternInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize the training Pattern
+  AGESA_STATUS (*TrainingPatternFinalize) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize the training Pattern
+  BOOLEAN (*GetApproximateWriteDatDelay) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Index, UINT8 *Value); ///< Retrieve the next WrDat Delay Approximation
+  UINT8 (*CSPerChannel) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS per channel.
+  UINT8 (*CSPerDelay) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS controlled per set of delay registers.
+  VOID (*FlushPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT16 ClCount);  ///<Flush the training pattern
+  UINT8 (*MinDataEyeWidth) (struct _MEM_NB_BLOCK *NBPtr);  ///<Get Min Data Eye Width in 32nds of a UI
+  VOID (*MemNCapSpeedBatteryLife) (struct _MEM_NB_BLOCK *NBPtr); ///< Caps speed based on battery life check.
+  UINT32 (*GetUmaSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Get Uma Size
+  UINT8 (*GetMemClkFreqId) (struct _MEM_NB_BLOCK *NBPtr, UINT16 Speed); ///< Translate MemClk frequency in MHz to MemClkFreq value
+  VOID (*EnableSwapIntlvRgn) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Base, UINT32 Limit); ///< Enable swapped interleaving region
+
+  /* PUBLIC Get/Set register field functions */
+  UINT32 (*GetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName); ///< Pci register bit field read.
+  VOID (*SetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field write.
+  BOOLEAN (*BrdcstCheck) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast read.
+  VOID (*BrdcstSet) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast write.
+  VOID (*PollBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Field, UINT32 MicroSecond, BOOLEAN IfBroadCast); ///< Poll a Pci register bitfield.
+  UINT32 (*GetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar); ///< Training register bit field read.
+  VOID (*SetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Value); ///< Training register bit field write.
+  AGESA_STATUS (*InitRecovery) (struct _MEM_NB_BLOCK *NBPtr); ///< Recover mode memory init
+  VOID (*MemRecNFinalizeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize MCT changes
+  VOID (*MemNInitPhyComp) (struct _MEM_NB_BLOCK *NBPtr); ///< Init Phy compensation
+  VOID (*MemNBeforeDramInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Before Dram init
+  BOOLEAN (*MemNIsIdSupportedNb) (struct _MEM_NB_BLOCK *NBPtr, CPU_LOGICAL_ID *LogicalIdPtr); ///< Determines if a given CPU id is supported
+  BOOLEAN (*InitNBRegTableNb) (TSEFO NBRegTable[]); ///< Initializes register table
+  BOOLEAN (*MemNPlatformSpecificFormFactorInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Platform specific functions
+  VOID (*MemNSetOtherTimingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Set non-spd timings
+  VOID (*MemNBeforePlatformSpecNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Apply settings prior to platform specific settings
+  UINT32 (*MemNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< Sets a register value
+  UINT32 (*MemNcmnGetSetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< Sets a training delay field
+  VOID (*MemPPhyFenceTrainingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy Fence training
+  VOID (*MemPNodeMemBoundaryNb) (struct _MEM_NB_BLOCK *NBPtr, UINT32 *NodeSysLimit); ///< Phy Fence training
+  UINT32 (*MemRecNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< This functions sets bit fields in recover mode
+  UINT32 (*MemRecNcmnGetSetTrainDlyNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< This functions sets bit fields in recover mode
+  VOID (*MemRecNSwitchDctNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< S3 Exit self refresh register
+  VOID (*MemNPFenceAdjustNb) (struct _MEM_NB_BLOCK *NBPtr, UINT16 *Value16); ///< Adjust Avg PRE value of Phy fence training
+
+} MEM_NB_BLOCK;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+MemNInitNBDataNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSwitchDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemNSwitchChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+UINT32
+MemNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  );
+
+VOID
+MemNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+BOOLEAN
+MemNBrdcstCheckNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+VOID
+MemNBrdcstSetNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+
+UINT32
+MemNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  );
+
+VOID
+MemNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+MemNRankEnabledNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver
+  );
+
+UINT8 MemNGetSocketRelativeChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct,
+  IN       UINT8 Channel
+  );
+
+VOID
+MemNPhyFenceTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNGetMCTSysAddrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Receiver,
+  OUT      UINT32 *AddrPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNStitchMemoryNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNStartupDCTClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNChangeFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNRampUpFrequencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramCycTimingsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNGetMaxLatParamsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  );
+
+VOID
+MemNGetMaxLatParamsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxDlyForMaxRdLat,
+  IN OUT   UINT16 *MinDlyPtr,
+  IN OUT   UINT16 *MaxDlyPtr,
+  IN OUT   UINT16 *DlyBiasPtr
+  );
+
+UINT16
+MemNTotalSyncComponentsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  );
+
+VOID
+MemNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSwapBitsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNTrainPhyFenceNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitPhyCompNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNGetTrainDlyParmsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN OUT   TRN_DLY_PARMS *Parms
+  );
+
+VOID
+MemNBeforeDQSTrainingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNcmnGetSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+UINT32
+MemNcmnGetSetTrainDlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+MemNInitializeMctNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSyncTargetSpeedNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNSyncDctsReadyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNHtMemMapInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTrdrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTwrwrNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTwrrdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTrwtTONb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNGetTrwtWBNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPowerDownCtlNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNCPUMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNUMAMemTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNSyncAddrMapToAllNodesNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNInitMCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNTechBlockSwitchNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemRecNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  );
+
+VOID
+MemRecNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+MemRecNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  );
+
+VOID
+MemRecNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+MemRecNAutoConfigNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemRecNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  );
+
+VOID
+MemRecNSetDramOdtNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       ODT_MODE OdtMode,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 TargetCS
+  );
+
+VOID
+MemRecNSendMrsCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+
+VOID
+MemRecNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+AGESA_STATUS
+MemRecNMemInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNInitializeMctNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemRecNCPUMemRecTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemRecNGetMCTSysAddrNb (VOID);
+
+UINT32
+MemRecGetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+INT8
+MemNGetOptimalCGDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly1,
+  IN       TRN_DLY_TYPE TrnDly2
+  );
+
+VOID
+MemNPollBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field,
+  IN       UINT32 MicroSecond,
+  IN       BOOLEAN IfBroadCast
+  );
+
+VOID
+MemNSetEccSymbolSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDQSTiming3Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDQSTiming2Nb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNRecTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDefNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNDefFalseNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+AGESA_STATUS
+MemNTrainingPatternInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNGetApproximateWriteDatDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Index,
+  IN OUT   UINT8 *Value
+  );
+
+AGESA_STATUS
+MemNTrainingPatternFinalizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNFlushPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+UINT8
+MemNCSPerChannelNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNCSPerDelayNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT8
+MemNMinDataEyeWidthNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT16
+MemNCompareTestPatternNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+UINT16
+MemNInsDlyCompareTestPatternNb (
+  IN       MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+
+UINT32
+MemNGetUmaSizeNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNSetMTRRUmaRegionUCNb  (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT32 *BasePtr,
+  IN OUT   UINT32 *LimitPtr
+  );
+
+UINT8
+MemNGetMemClkFreqIdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  );
+
+UINT8
+MemNGetMemClkFreqIdClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 Speed
+  );
+
+BOOLEAN
+MemNGetPlatformCfgNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
+MemNPlatformSpecClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramCycTimingsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+INT16
+MemNCalcCDDNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDlyType1,
+  IN       TRN_DLY_TYPE TrnDlyType2,
+  IN       BOOLEAN SameDimm,
+  IN       BOOLEAN DiffDimm
+  );
+
+VOID
+MemNChangeFrequencyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNProgramNbPstateDependentRegistersClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNAllocateC6StorageNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPhyVoltageLevelClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPhyFenceTrainingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNPFenceAdjustClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   UINT16 *Value16
+  );
+
+VOID
+MemNInitPhyCompClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+UINT32
+MemNTotalSyncComponentsClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNEnableSwapIntlvRgnNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN          UINT32 Base,
+  IN          UINT32 Limit
+  );
+
+VOID
+MemNPhyPowerSavingClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MN_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mp.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mp.h
new file mode 100755
index 0000000000..22e09f3a0a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mp.h
@@ -0,0 +1,241 @@
+/**
+ * @file
+ *
+ * mp.h
+ *
+ * Platform Specific common header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 7810 $ @e \$Date: 2008-08-29 10:27:00 -0500 (Fri, 29 Aug 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _MP_H_
+#define _MP_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Type of an entry for Dram Term table
+typedef struct {
+  UINT32 Speed; ///< BitMap for the supported speed
+  UINT8  Dimms; ///< BitMap for supported number of dimm
+  UINT8  QR_Dimms; ///< BitMap for supported number of QR dimm
+  UINT8  DramTerm; ///< DramTerm value
+  UINT8  QR_DramTerm; ///< DramTerm value for QR
+  UINT8  DynamicDramTerm; ///< Dynamic DramTerm
+} DRAM_TERM_ENTRY;
+
+/// Type of an entry for POR speed limit table
+typedef struct {
+  UINT16   DIMMRankType;  ///< Bitmap of Ranks
+  UINT8    Dimms;  ///< Number of dimm
+  UINT16    SpeedLimit_1_5V; ///< POR speed limit for 1.5V
+  UINT16    SpeedLimit_1_35V; ///< POR speed limit for 1.35V
+  UINT16    SpeedLimit_1_25V; ///< POR speed limit for 1.25V
+} POR_SPEED_LIMIT;
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+MemPConstructPsUDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+BOOLEAN
+MemPGetDramTerm (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 ArraySize,
+  IN       CONST DRAM_TERM_ENTRY *DramTermPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRHy3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRC32_3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+
+AGESA_STATUS
+MemPConstructPsSDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRDr3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUNi3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSDA3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSDA2 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSLN3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsULN3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsRLN3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsSON3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+AGESA_STATUS
+MemPConstructPsUON3 (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT   CH_DEF_STRUCT *ChannelPtr,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+UINT16
+MemPGetPorFreqLimit (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 FreqLimitSize,
+  IN       CONST POR_SPEED_LIMIT *FreqLimitPtr
+  );
+
+VOID
+MemPGetPORFreqLimitDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+#endif  /* _MP_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mport.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mport.h
new file mode 100755
index 0000000000..263e8fd1a3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mport.h
@@ -0,0 +1,70 @@
+/**
+ * @file
+ *
+ * mport.h
+ *
+ * API's to support different OS
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+ /*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ *===========================================================================
+ *  AMD Revision History
+ *  Initial Version
+ *
+ */
+#ifndef _MPORT_H_
+#define _MPORT_H_
+
+///< 64 bit data structure
+///< lo - Lower 32 bits
+///< hi - Upper 32 bits
+typedef struct {
+  UINT32 lo; ///< Lower 32 bits
+  UINT32 hi; ///< Upper 32 bits
+} S_UINT64;
+/*
+ *   SBDFO - Segment Bus Device Function Offset
+ *   31:28   Segment (4-bits)
+ *   27:20   Bus     (8-bits)
+ *   19:15   Device  (5-bits)
+ *   14:12   Function(3-bits)
+ *   11:00   Offset  (12-bits)
+ */
+typedef UINT32 SBDFO;
+
+#define GET_SIZE_OF(x)   (sizeof (x) / sizeof (x[0]))
+
+#endif /* _MPORT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mt.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mt.h
new file mode 100755
index 0000000000..2fd0fb755f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mt.h
@@ -0,0 +1,364 @@
+/**
+ * @file
+ *
+ * mt.h
+ *
+ * Common Technology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MT_H_
+#define _MT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define FIRST_PASS      1
+#define SECOND_PASS     2
+#define BIGPAGE_X8_RJ16 0x80
+#define BIGPAGE_X8      0x800000
+#define DQS_FAIL        1
+#define DQS_PASS        0
+#define DQS_WRITE_DIR    1
+#define DQS_READ_DIR     0
+#define MIN_DQS_WNDW    3
+#define ST_UNSTEADY     0
+#define ST_STEADY       1
+#define ST_GROSS_SWEEP  2
+#define ST_FINE_SWEEP   3
+#define ST_FINISH       4
+
+#define MAX_BYTELANES_PER_CHANNEL   (8 + 1)  ///< Max Bytelanes per channel
+
+#define MAX_FILTER_DLY_DDR2 0x20
+#define MAX_FILTER_DLY_DDR3 0x28
+
+#define NEW_RECEIVER_START_VALUE  0x4
+#define NEW_RECEIVER_STEP_1       4
+#define NEW_RECEIVER_STEP_2       7
+
+#define NEW_RECEIVER_FINAL_OFFSETVALUE 5
+
+#define DBG_PRINT_STAGE           18                    // "Stage"
+#define DBG_PRINT_0_TO_64         23                    // "0...64"
+#define DBG_SPACES_4              21                    // 4 spaces
+#define DBG_POS_NEW_LINE          11                    // New Line for POS training
+#define DBG_WR_DLY                24                    // "Write Delay: "
+#define DBG_B_L_R_W_M             22                    // " Bytelane  Left   Right  Width  Middle"
+#define DBG_RX_EN_NEW_LINE        25                    // New Line for Rx En
+#define DBG_RX_EN_STAGE1          6                     // "Receiver Enable Training Stage 1:"
+#define DBG_RX_EN_STAGE2          7                     // "Receiver Enable Training Stage 2:"
+#define DBG_RX_EN_STAGE3          8                     // "Receiver Enable Training Stage 3:"
+#define DBG_DLY_PER_BL            9                     // "Dly per BL   -"
+#define DBG_A_B_DLY               10                    // "ALL BLs have Dly:"
+#define DBG_RCVR_PRT_VALUE        0x0010F               // PORT for RX EN training to print a value
+#define DBG_RX_POS_PRT_VALUE      0x0011F               // PORT for POS training to print a value
+
+#define DONE_FILTER 0           ///<  optimized receiver enable training glitch search complete
+#define START_FILTER 1          ///<  optimized receiver enable training start glitch filter search
+#define FILTER_FIRST_STAGE_COUNT 4 ///<  optimized receiver enable training glitch filter first stage count
+#define FILTER_SECOND_STAGE_COUNT 7  ///<  optimized receiver enable training glitch second stage count
+#define FILTER_OFFSET_VALUE 0x1C ///<  optimized receiver enable training glitch filter offset value int preamble
+#define FILTER_WINDOW_SIZE 0x28  ///< optimized receiver enable training glitch filter search window size
+#define FILTER_MAX_REC_EN_DLY_VALUE 0x1FF ///< optimized receiver enable glitch filter max receiver value
+#define FILTER_NEW_RECEIVER_START_VALUE  0x0    ///< optimized receiver enable glitch filter  Start value
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Structure for Technology block.
+typedef struct _MEM_TECH_BLOCK {
+  MEM_NB_BLOCK  *NBPtr; ///< point to northbridge block.
+  MEM_PARAMETER_STRUCT *RefPtr; ///< point to parameter list.
+
+  /* Temporary storage */
+  UINT32 HwcrLo; ///< value of HWCR.
+  UINT32 CR4reg; ///< CR4 register value.
+  UINT8  DramEcc; ///< value of Dram ECC bit.
+  UINT8  *TestBufPtr; ///< point to buffer to store read-back data.
+  UINT8  *PatternBufPtr; ///< point to pattern buffer.
+  UINT8  PatternLength; ///< the length of pattern buffer in cache lines.
+  UINT8  Direction; ///< direction during training.
+  UINT8  ChipSel; ///< chip select number.
+  UINT16 MaxDlyForMaxRdLat; ///< Largest possible value for Receiver enable delay.
+  UINT16 PrevSpeed; ///< Previous MemClk frequency
+
+  UINT8  Pass; ///< current pass of training.
+  UINT16 DqsRdWrPosSaved;    ///< for position training byte lane saved flag
+  UINT16 DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  UINT16 DqsRcvEnSavedS1; ///< for TrainRcvrEn UINT8 lane saved flag
+  UINT16 DqsRcvEnFirstPassVal; ///< for TrainRcvrEn UINT8 lane saved flag
+  BOOLEAN GetFirstPassVal; ///< If the first passing value has been found.
+  BOOLEAN RevertPassVal; ///< Flag to restart training during training process when glitch is found.
+  UINT8 MaxFilterDly; ///< Maximum filter delay value for RcvrTraining.
+  UINT16 RcvrEnDlyOpt[MAX_BYTELANES_PER_CHANNEL];     ///< Receiver Enable delay for optimized filter
+  UINT16 MaxRcvrEnDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Max Receiver Enable delay for optimized filter
+  UINT16 RcvrEnDlyLimitOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay Limit for optimized filter
+  UINT16 FilterStatusOpt[MAX_BYTELANES_PER_CHANNEL];  ///< Filter status to indicate if a ByteLane is "DONE", "SKIP" or "CONTINUE"
+  UINT16 FilterCountOpt;  ///< Filter count to indicate the total number of ByteLanes completed
+  BOOLEAN DqsRcvEnSavedOpt[MAX_BYTELANES_PER_CHANNEL];      ///< for optimized TrainRcvrEn lane saved flag
+  UINT16 DqsRcvEnFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for TrainRcvrEn UINT8 lane saved flag for optimized
+  BOOLEAN GetFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< If the first passing value has been found for optimized.
+  BOOLEAN RevertPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Flag to restart training during training process when glitch is found for optimized.
+  UINT8 MaxFilterDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Maximum filter delay value for RcvrTraining for optimized.
+  BOOLEAN IncBy1ForNextCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Used to determine when to increment by 1 in second stage of opt. rec. en. training
+  UINT8 FilterSidePassCountOpt[MAX_BYTELANES_PER_CHANNEL];  ///< Indicates that previous side passed
+
+  /* PUBLIC functions */
+  VOID (*SendAllMRCmds) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ChipSel); ///< Send MRS command.
+  VOID (*FreqChgCtrlWrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Frequency change control word.
+  BOOLEAN (*SetDramMode) (struct _MEM_TECH_BLOCK *TechPtr); ///< Set dram mode (DDR2 or DDR3).
+  BOOLEAN (*DimmPresence) (struct _MEM_TECH_BLOCK *TechPtr); ///< determines if DIMMs present.
+  BOOLEAN (*SpdCalcWidth) (struct _MEM_TECH_BLOCK *TechPtr); ///< check the symmetry of DIMM pairs.
+  BOOLEAN (*SpdGetTargetSpeed) (struct _MEM_TECH_BLOCK *TechPtr); ///< get supported frequency.
+  BOOLEAN (*AutoCycTiming) (struct _MEM_TECH_BLOCK *TechPtr); ///< configure timing based on spd data.
+  BOOLEAN (*SpdSetBanks) (struct _MEM_TECH_BLOCK *TechPtr); ///< set bank address.
+  BOOLEAN (*SetDqsEccTmgs) (struct _MEM_TECH_BLOCK *TechPtr); ///< DQS training.
+  VOID (*GetCSIntLvAddr) (UINT8 BankEnc, UINT8 *LowBit, UINT8 *HiBit); ///< Get Chip select interleave address.
+  VOID (*AdjustTwrwr) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrwr for certain dimm technology.
+  VOID (*AdjustTwrrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrrd for certain dimm technology.
+  INT8 (*GetLD) (struct _MEM_TECH_BLOCK *TechPtr); ///< Get LD value for certain dimm technology.
+  VOID (*DramInit) (struct _MEM_TECH_BLOCK *TechPtr); ///< dram initialization.
+
+  /* PRIVATE functions */
+  VOID (*InitDQSPos4RcvrEn) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialize training register before training.
+  VOID (*SetRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
+  VOID (*LoadRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
+  BOOLEAN (*SaveRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< Save receiver enable delay register value.
+  BOOLEAN (*SaveRcvrEnDlyFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< saves passing DqsRcvEnDly values to the stack.
+  VOID (*ResetDCTWrPtr) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< resets the DCT input buffer write pointer.
+  UINT16 (*Compare1ClPattern) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[]); ///< Compare training pattern of 1 cache line.
+  VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
+  VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
+  UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter.
+  UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes.
+  VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR.
+  VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference.
+  BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value.
+  UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
+  UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line.
+  VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
+  VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
+  BOOLEAN (*CheckRcvrEnDlyLimitOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Find limit for all bytelanes
+  UINT16 (*GetMaxValueOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///<  Returns the max value of all bytelanes
+  VOID (*InitializeVariablesOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialized variables for optimized training
+  BOOLEAN (*SetSweepErrorOpt)(struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT8 DCT, BOOLEAN ErrorCheck); ///< records any errors generated from optimized sweep
+  VOID (*LoadInitialRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load the starting value for receiver DQS training.
+  BOOLEAN (*GetDimmSpdBuffer) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 **SpdBuffer, UINT8 Dimm); ///< Gets pointer to spd buffer for a dimm on the current channel, if present
+} MEM_TECH_BLOCK;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemTDimmByteTrainInit (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainMaxLatency (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSetDQSEccTmgs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTSetDQSEccTmgsRDdr3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainDQSEdgeDetectSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+BOOLEAN
+MemTDramInitSw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+VOID
+MemTDramInitHw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+BOOLEAN
+MemTFeatDef (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilter (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  );
+
+BOOLEAN
+MemTSaveRcvrEnDlyByteFilterOpt (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT16 CmpResultRank0,
+  IN       UINT16 CmpResultRank1
+  );
+
+BOOLEAN
+MemTNewRevTrainingSupport (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTTrainOptRcvrEnSwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTWriteLevelizationHw3Pass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTPreparePhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTExitPhyAssistedTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass1 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTDqsTrainRcvrEnHwPass2 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTSetWrDatRdDqs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 WrDatDly
+  );
+
+VOID
+MemRecTTrainDQSPosSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+BOOLEAN
+MemTSetSweepErrorOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT8 Dct,
+  IN       BOOLEAN ErrorCheck
+  );
+
+VOID
+MemTInitializeVariablesOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+UINT16
+MemTGetMaxValueOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemTCheckRcvrEnDlyLimitOptByte (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTMarkTrainFail (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+);
+
+VOID
+MemTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemTSetDQSDelayAllCSR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Dly
+  );
+
+BOOLEAN
+MemTExitPhyAssistedTrainingClient3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h
new file mode 100755
index 0000000000..fc193147d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/mu.h
@@ -0,0 +1,225 @@
+/**
+ * @file
+ *
+ * mu.h
+ *
+ * Utility support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MU_H_
+#define _MU_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+  #define PSO_ENTRY UINT8
+#endif
+
+#define MAX(X, Y) (((X) < (Y)) ? (Y) : (X))
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Test patterns for DQS training
+typedef enum {
+  TestPattern0,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern1,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern2,             ///< Test pattern used in second pass of receiver enable training
+  TestPatternJD1B,          ///< 72-bit test pattern used in position training (ganged mode)
+  TestPatternJD1A,          ///< 72-bit test pattern used in position training
+  TestPatternJD256B,        ///< 256-bit test pattern used in position training (ganged mode)
+  TestPatternJD256A,        ///< 256-bit test pattern used in position training
+  TestPatternML,            ///< Test pattern used in first pass of max latency training
+  TestPattern3,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern4              ///< Test pattern used in first pass of receiver enable training
+} TRAIN_PATTERN;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemUWriteCachelines (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[],
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemUReadCachelines (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+VOID
+MemUDummyCLRead (
+  IN       UINT32 Address
+  );
+
+VOID
+MemUFlushPattern (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount
+  );
+
+
+VOID
+MemUFillTrainPattern (
+  IN       TRAIN_PATTERN Pattern,
+  IN       UINT8 Buffer[],
+  IN       UINT16 Size
+  );
+
+UINT32
+MemUSetUpperFSbase (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUSetTargetWTIO (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUResetTargetWTIO (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUProcIOClFlush (
+  IN       UINT32 Address,
+  IN       UINT16 ClCount,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+UINT16
+MemUCompareTestPattern (
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN       UINT16 ByteCount
+  );
+
+VOID
+MemUWait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemUGetWrLvNblErr (
+  IN OUT   UINT16 *ErrBitmap,
+  IN       UINT32 TestAddr,
+  IN       UINT16 ClCount
+  );
+
+VOID
+AlignPointerTo16Byte (
+  IN OUT   UINT8 **BufferPtrPtr
+  );
+
+VOID *
+FindPSOverrideEntry (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       PSO_ENTRY EntryType,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  );
+
+UINT8
+GetMaxDimmsPerChannel (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN UINT8 ChannelID
+  );
+
+UINT8
+GetMaxChannelsPerSocket (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+GetMaxCSPerChannel (
+  IN      PSO_TABLE *PlatformMemoryConfiguration,
+  IN      UINT8 SocketID,
+  IN      UINT8 ChannelID
+  );
+
+UINT8
+GetSpdSocketIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+GetSpdChannelIndex (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN UINT8 SocketID,
+  IN UINT8 ChannelID,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+GetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  /* _MU_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
new file mode 100755
index 0000000000..d916b024b2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.c
@@ -0,0 +1,96 @@
+/**
+ * @file
+ *
+ * AMD CPU Recovery API, and related functions.
+ *
+ * Contains code that implements the CPU Recovery functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Recovery/CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ **/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "cpuRecovery.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_CPU_CPURECOVERY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs CPU related initialization at the recovery entry point
+ *
+ * This function processes the MSR and PCI register tables.
+ *
+ * @param[in]  CpuRecoveryParams     Required input parameters for recovery CPU
+ *                                   initialization.
+ *
+ * @retval     AGESA_SUCCESS         Always succeeds.
+ *
+ */
+AGESA_STATUS
+AmdCpuRecovery (
+  IN       AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
+  )
+{
+  SetRegistersFromTables (&CpuRecoveryParams->PlatformConfig, &CpuRecoveryParams->StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h
new file mode 100755
index 0000000000..0b96dec7b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/CPU/cpuRecovery.h
@@ -0,0 +1,75 @@
+/**
+ * @file
+ *
+ * AMD CPU Recovery API, and related function prototypes.
+ *
+ * Contains code that implements the CPU Recovery functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Recovery/CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_RECOVERY_H_
+#define _CPU_RECOVERY_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+//                          These are   P U B L I C   functions
+AGESA_STATUS
+AmdCpuRecovery (
+  IN       AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
+  );
+
+#endif // _CPU_RECOVERY_H_
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
new file mode 100755
index 0000000000..5e268b4aef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitRecovery.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * Init the Socket and Node maps for Recovery mode.
+ *
+ * Create the Socket and Node maps just like normal boot,
+ * except that they only indicate the BSC is present.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 7506 $   @e \$Date: 2008-08-20 17:44:22 -0500 (Wed, 20 Aug 2008) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get new Socket and Node Maps.
+ *
+ * Put the Socket Die Table and the Node Table in heap with known handles.
+ *
+ * @param[out]    SocketDieToNodeMap   The Socket, Module to Node info map
+ * @param[out]    NodeToSocketDieMap   The Node to Socket, Module map.
+ * @param[in]     StdHeader            Header for library and services.
+ */
+VOID
+STATIC
+NewNodeAndSocketTablesRecovery (
+     OUT   SOCKET_DIE_TO_NODE_MAP *SocketDieToNodeMap,
+     OUT   NODE_TO_SOCKET_DIE_MAP *NodeToSocketDieMap,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  // Allocate heap for the table
+  AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM));
+  AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    // HeapAllocateBuffer must set BufferPtr to valid or NULL.
+    *SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr;
+    ASSERT (SocketDieToNodeMap != NULL);
+    // Initialize shared data structures
+    for (i = 0; i < MAX_SOCKETS; i++) {
+      for (j = 0; j < MAX_DIES; j++) {
+        (**SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL;
+        (**SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL;
+        (**SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Allocate heap for the table
+  AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM));
+  AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    // HeapAllocateBuffer must set BufferPtr to valid or NULL.
+    *NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr;
+    ASSERT (NodeToSocketDieMap != NULL);
+    // Initialize shared data structures
+    for (i = 0; i < MAX_NODES; i++) {
+      (**NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL;
+      (**NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map.
+ * The mapping is filled in by reading the AP Mailboxes from PCI config on each node.
+ *
+ * @param[in]    StdHeader    global state, input data
+ *
+ * @retval       AGESA_SUCCESS  Always succeeds.
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AP_MAILBOXES NodeApMailBox;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap;
+  NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap;
+
+  NodeApMailBox.ApMailInfo.Info = 0;
+  NodeApMailBox.ApMailExtInfo.Info = 0;
+
+  // Allocate heap for caching the mailboxes
+  AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES);
+  AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
+    *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = NodeApMailBox;
+  }
+
+  NewNodeAndSocketTablesRecovery (&SocketDieToNodeMap, &NodeToSocketDieMap, StdHeader);
+  // HeapAllocateBuffer must set BufferPtr to valid or NULL, so the checks below are ok.
+
+  // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug.
+  ASSERT (SocketDieToNodeMap != NULL);
+  ASSERT (NodeToSocketDieMap != NULL);
+
+  (*SocketDieToNodeMap)[0][0].Node = 0;
+  (*SocketDieToNodeMap)[0][0].LowCore = 0;
+  (*SocketDieToNodeMap)[0][0].HighCore = 0;
+
+  // We lie about being Socket 0 and Module 0 always, it isn't necessarily true.
+  (*NodeToSocketDieMap)[0].Socket = (UINT8)0;
+  (*NodeToSocketDieMap)[0].Die = (UINT8)0;
+
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c
new file mode 100755
index 0000000000..6240903194
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/HT/htInitReset.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * Recovery HT, a Hypertransport init for Boot Blocks.  For normal
+ * boots, run Recovery HT first in boot block, then run full HT init
+ * in the system BIOS.  Recovery HT moves the devices on the chain with
+ * the southbridge to their assigned device IDS, so that all their PCI
+ * Config space is accessible.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Recovery HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "AdvancedApi.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_HT_HTINITRESET_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_NODES 1
+#define MAX_LINKS 8
+
+extern CONST AMD_HT_RESET_INTERFACE HtOptionResetDefaults;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Our global state data structure.
+ *
+ * Keep track of inputs and outputs, and keep any working state.
+ */
+typedef struct {
+  AMD_HT_RESET_INTERFACE      *HtBlock;       ///< The interface
+  AGESA_STATUS                Status;         ///< Remember the highest severity status event
+  VOID                        *ConfigHandle;  ///< Config Pointer, opaque handle for passing to lib
+} HTR_STATE_DATA;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable Routing Tables.
+ *
+ * Turns routing tables on for a node zero.
+ *
+ * @param[in] State Our State
+ */
+
+VOID
+STATIC
+HtrEnableRoutingTables (
+  IN HTR_STATE_DATA *State
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = 0;
+  Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0x6C);
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, State->ConfigHandle);
+}
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                             Algorithms                              ***
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process the SouthBridge Link.
+ *
+ * Process a non-coherent link, and setting the device ID for all devices found.
+ *
+ * @param[in] State Our State, Inputs
+ */
+VOID
+STATIC
+HtrProcessLink (
+  IN HTR_STATE_DATA *State
+  )
+{
+  UINT32 CurrentBUID;
+  UINT32 Temp;
+  UINT32 UnitIDcnt;
+  PCI_ADDR CurrentPtr;
+  UINT8 Depth;
+  BUID_SWAP_LIST *SwapPtr;
+
+  // No PCI init to run, everything has to be on Bus zero.  This makes fewer
+  // northbridge dependencies.
+  //
+  // Assign BUIDs so that config space for all devices is visible.
+  //
+  if (State->HtBlock->ManualBuidSwapList != NULL) {
+    // Manual non-coherent BUID assignment
+    // Assign BUID's per manual override
+    //
+    SwapPtr = &(State->HtBlock->ManualBuidSwapList->SwapList);
+    Depth = 0;
+    while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
+      CurrentPtr.AddressValue = MAKE_SBDFO (0, 0, SwapPtr->Swaps[Depth].FromId, 0, 0);
+
+      do {
+        LibAmdPciFindNextCap (&CurrentPtr, State->ConfigHandle);
+        ASSERT (CurrentPtr.AddressValue != ILLEGAL_SBDFO);
+        LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
+      } while ((Temp & (UINT32)0xE00000FF) != (UINT32)0x00000008); // HyperTransport Slave Capability
+
+      CurrentBUID = SwapPtr->Swaps[Depth].ToId;
+      // Set the device's BUID
+      LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBUID, State->ConfigHandle);
+      Depth++;
+    }
+  } else {
+    // Automatic non-coherent device detection
+    Depth = 0;
+    CurrentBUID = 1;
+    for (;;) {
+      CurrentPtr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+
+      LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
+      if (Temp == (UINT32)0xFFFFFFFF) {
+        // No device found at currentPtr
+        break;
+      }
+
+      // HyperTransport Slave Capability
+      do {
+        LibAmdPciFindNextCap (&CurrentPtr, State->ConfigHandle);
+        if (CurrentPtr.AddressValue == ILLEGAL_SBDFO) {
+          // There is a device at currentPtr, but it isn't an HT device.
+          return;
+        }
+        LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
+      } while ((Temp & (UINT32)0xE00000FF) != (UINT32)0x00000008); // HyperTransport Slave Capability
+
+      // Get the device's Unit ID Count.
+      LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIDcnt, State->ConfigHandle);
+      if ((UnitIDcnt + CurrentBUID) > 24) {
+        // An error handler for the case where we run out of BUID's on a chain
+        State->Status = AGESA_ERROR;
+        ASSERT (FALSE);
+        return;
+      }
+      // Set the device's BUID
+      LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBUID, State->ConfigHandle);
+
+      CurrentPtr.Address.Device = CurrentBUID;
+      // Get the device's BUID
+      LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
+      if (Temp != CurrentBUID) {
+        // An error handler for this critical error
+        State->Status = AGESA_ERROR;
+        ASSERT (FALSE);
+        return;
+      }
+
+      Depth++;
+      CurrentBUID += UnitIDcnt;
+    }
+    // Provide information on automatic device results
+    State->HtBlock->Depth = Depth;
+  }
+}
+
+/***************************************************************************
+ ***                           HT Reset Initialize                    ***
+ ***************************************************************************/
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in]     StdHeader             Config handle
+ * @param[in,out] AmdHtResetInterface   HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtResetConstructor (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  )
+{
+  AmdHtResetInterface->ManualBuidSwapList = HtOptionResetDefaults.ManualBuidSwapList;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize HT for Reset, Boot Blocks.
+ *
+ * This is the top level external interface for Hypertransport Reset Initialization.
+ * Create our initial internal state and initialize the non-coherent chain to the
+ * southbridge.  This interface must be executed by both normal and recovery boot paths.
+ *
+ * @param[in]  StdHeader                 Interface structure
+ * @param[in]  AmdHtResetInterface       our interface and inputs
+ *
+ * @retval AGESA_SUCCESS Successful init
+ * @retval AGESA_ERROR   Device Error, BUID max exceed error.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  )
+{
+  HTR_STATE_DATA State;
+  AGESA_STATUS IgnoredStatus;
+
+  State.Status = AGESA_SUCCESS;
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    State.ConfigHandle = (AMD_CONFIG_PARAMS *)StdHeader;
+    State.HtBlock = AmdHtResetInterface;
+    HtrEnableRoutingTables (&State);
+
+    HtrProcessLink (&State);
+  }
+  return State.Status;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c
new file mode 100755
index 0000000000..ec7a1e107c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.c
@@ -0,0 +1,700 @@
+/**
+ * @file
+ *
+ * mrnc32.c
+ *
+ * Common Northbridge  functions for C32 Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnc32.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define MAX_DCTS_PER_DIE 2
+#define SPLIT_CHANNEL   0x20000000
+#define CHANNEL_SELECT  0x10000000
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableC32 (
+  IN OUT   TSEFO *NBRegTable
+  );
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+VOID
+STATIC
+MemRecNSwitchNodeC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 NodeID
+  );
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]       NodeID   - Node ID for this NB block
+ *
+ *     @return          TRUE  - This node is a C32 and this NB block has been initialized
+ *     @return          FALSE - This node is not a C32
+ */
+
+BOOLEAN
+MemRecConstructNBBlockC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemRecNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  MCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_C32 * (
+                                              sizeof (CH_DEF_STRUCT) + (
+                                                MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
+                                              )
+                                            )
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  MemPtr->DiesPerSystem[NodeID + 1].DctCount = MAX_DCTS_PER_NODE_C32;
+  MemPtr->DiesPerSystem[NodeID + 1].DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT);
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) {
+      MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+      MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+      MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+    }
+  }
+
+  //
+  //  Initialize NB block's variables
+  //
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->AllNodeMCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+  NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+
+  MemRecNInitNBRegTableC32 (NBPtr->NBRegTable);
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+  LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->InitRecovery = MemRecNMemInitNb;
+
+  NBPtr->SwitchNodeRec = MemRecNSwitchNodeC32;
+  NBPtr->SwitchDCT = MemRecNSwitchDctC32;
+  NBPtr->SwitchChannel = MemRecNSwitchChannelC32;
+  NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
+  NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
+  NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
+  NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
+  NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
+
+  NBPtr->GetBitField = MemRecNGetBitFieldNb;
+  NBPtr->SetBitField = MemRecNSetBitFieldNb;
+  NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
+
+  NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldC32;
+  NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyC32;
+  NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctC32;
+  NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
+  NBPtr->MemRecNFinalizeMctNb =  MemRecNFinalizeMctC32;
+  NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
+  MemRecNSwitchDctC32 (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the current die to work on.
+ *   Should be called before accessing a certain die
+ *   All data structures will be updated to point to the current node
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   NodeID - ID of the target die
+ *
+ */
+
+VOID
+STATIC
+MemRecNSwitchNodeC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 NodeID
+  )
+{
+  NBPtr->MCTPtr = &(NBPtr->AllNodeMCTPtr[NodeID]);
+  NBPtr->Node = NodeID;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  MemRecNSwitchDctC32 (NBPtr, NBPtr->Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemRecNSwitchDctC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  NBPtr->Dct = Dct & 1;
+  NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[(NBPtr->MCTPtr->NodeId * MAX_DCTS_PER_DIE + Dct) * MAX_DIMMS_PER_CHANNEL]);
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+
+  MemRecNSwitchChannelC32 (NBPtr, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemRecNSwitchChannelC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = 0;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[0]);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 index;
+  UINT16 offset;
+  UINT32 value;
+  UINT32 address;
+  UINT8 DIMM;
+  UINT8 Rank;
+  UINT8 Byte;
+  UINT8 Nibble;
+
+  DIMM = DRBN_DIMM (DrbnVar);
+  Rank = DRBN_RANK (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+  Nibble = DRBN_NBBL (DrbnVar);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    index = 0x30;
+    break;
+  case AccessWrDatDly:
+    index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    index = 0x05;
+    break;
+  case AccessPhRecDly:
+    index = 0x50;
+    break;
+  default:
+    index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    index += (DIMM * 3);
+    if ((Byte & 0x04) != 0) {
+      // if byte 4,5,6,7
+      index += 0x10;
+    }
+    if ((Byte & 0x02) != 0) {
+      // if byte 2,3,6,7
+      index++;
+    }
+    if (Byte > 7) {
+      index += 2;
+    }
+    offset = 16 * (Byte % 2);
+    index |= (Rank << 8);
+    index |= (Nibble << 9);
+    break;
+
+  case AccessRdDqsDly:
+    Field &= ~ 0x0001;
+  case AccessWrDatDly:
+    index += (DIMM * 0x100);
+    if (Nibble != 0) {
+      if (Rank != 0) {
+        index += 0xA0;
+      } else {
+        index += 0x70;
+      }
+    } else if (Rank != 0) {
+      index += 0x60;
+    }
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    index += (Byte / 4);
+    offset = 8 * (Byte % 4);
+    break;
+  default:
+    offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  address = index;
+  MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
+  while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+  value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet != 0) {
+    if (TrnDly == AccessPhRecDly) {
+      value = NBPtr->DctCachePtr->PhRecReg[index & 0x03];
+    }
+
+    value = ((UINT32)Field << offset) | (value & (~((UINT32)0xFF << offset)));
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, value);
+    address |= DCT_ACCESS_WRITE;
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
+    while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[index & 0x03] = value;
+    }
+  } else {
+    value = (value >> offset) & 0xFF;
+  }
+
+  return value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Name of Field to be set
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  SBDFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if (FieldName < BFEndOfList) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address != 0) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = TSEFO_TYPE (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if (((Address & 0xF000) == 0x2000) && (NBPtr->Dct != 0)) {
+        Address |= 0x0100;
+      }
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+
+      if (Type == NB_ACCESS) {
+        // Address |= (((UINT32) (24 + 0)) << 15);
+        PciAddr.AddressValue = Address;
+        // Fix for MCM
+        PciAddr.Address.Device = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Device;
+        PciAddr.Address.Bus = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Bus;
+        PciAddr.Address.Segment = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Segment;
+        Address = PciAddr.AddressValue;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+        Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet != 0) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+        } else {
+          IDS_ERROR_TRAP;
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes bit field translation table
+ *
+*     @param[in,out]   *NBRegTable   - Pointer to the NB Table *
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableC32 (
+  IN OUT   TSEFO *NBRegTable
+  )
+{
+  UINT16 i;
+  for (i = 0; i <= BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8, 8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemRecNIsIdSupportedC32
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a C32.
+ *     @return          FALSE - This node is not a C32.
+ *
+ */
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+  if ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h
new file mode 100755
index 0000000000..1866d60e2c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnc32.h
@@ -0,0 +1,103 @@
+/**
+ * @file
+ *
+ * mnc32.h
+ *
+ * Northbridge C32 Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRNC32_H_
+#define _MRNC32_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_NODE_C32          2
+#define MAX_CHANNELS_PER_DCT_C32       1
+
+#define _4GB_RJ8    ((UINT32)4 << (30 - 8))
+#define MTRR_VALID  11
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemRecConstructNBBlockC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemRecNSwitchDctC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemRecNSwitchChannelC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+VOID
+MemRecNFinalizeMctC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MRNC32_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
new file mode 100755
index 0000000000..b7b9f3c884
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
@@ -0,0 +1,126 @@
+/**
+ * @file
+ *
+ * mrnmctc32.c
+ *
+ * Northbridge C32 MCT supporting functions Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnc32.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNFinalizeMctC32 (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+  // Recommended settings for F2x11C
+  MemRecNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x2CE00F60);
+
+  LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (!NBPtr->ClToNbFlag) {
+    SMsr.lo &= ~((UINT32) 1 << 15);                // ClLinesToNbDis
+  }
+  LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.hi &= ~((UINT32) 1 << (48 - 32));               // WbEnhWsbDis
+  LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
new file mode 100755
index 0000000000..cf3dd17249
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * mrnprotoc32.c
+ *
+ * Northbridge support functions for Errata and early samples Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 10082 $ @e \$Date: 2008-12-17 20:21:26 +0800 (Wed, 17 Dec 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+
+#include "AGESA.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c
new file mode 100755
index 0000000000..fa668dc5fa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.c
@@ -0,0 +1,640 @@
+/**
+ * @file
+ *
+ * mrnda.c
+ *
+ * Common Northbridge  functions for Ridgeback Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnda.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   0x20000000
+#define CHANNEL_SELECT  0x10000000
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableDA (
+  IN OUT   TSEFO *NBRegTable
+  );
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]       NodeID   - Node ID for this NB block
+ *
+ *     @return          TRUE  - This node is a RB and this NB block has been initialized
+ *     @return          FALSE - This node is not a RB
+ */
+
+BOOLEAN
+MemRecConstructNBBlockDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemRecNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  MCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_DA * (
+                                              sizeof (CH_DEF_STRUCT) + (
+                                                MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
+                                              )
+                                            )
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
+      MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+      MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+      MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+    }
+  }
+
+  //
+  //  Initialize NB block's variables
+  //
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+  NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+
+  MemRecNInitNBRegTableDA (NBPtr->NBRegTable);
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+  LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->InitRecovery = MemRecNMemInitNb;
+
+  NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
+  NBPtr->SwitchDCT = MemRecNSwitchDctDA;
+  NBPtr->SwitchChannel = MemRecNSwitchChannelDA;
+  NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
+  NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
+  NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
+  NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
+  NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
+
+  NBPtr->GetBitField = MemRecNGetBitFieldNb;
+  NBPtr->SetBitField = MemRecNSetBitFieldNb;
+  NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
+  NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldDA;
+  NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyDA;
+  NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctDA;
+  NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
+  NBPtr->MemRecNFinalizeMctNb =  MemRecNFinalizeMctDA;
+  NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
+  NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
+  MemRecNSwitchDctDA (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemRecNSwitchDctDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  NBPtr->Dct = Dct & 1;
+  NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+
+  MemRecNSwitchChannelDA (NBPtr, NBPtr->Channel);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemRecNSwitchChannelDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = Channel & 1;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Byte;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+
+  ASSERT (Dimm < 4);
+  ASSERT (Byte < 8);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    Offset = 16 * (Byte % 2);
+    break;
+
+  case AccessRdDqsDly:
+    Field &= ~ 0x0001;
+  case AccessWrDatDly:
+    Index += (Dimm * 0x100);
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+  Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+    while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    Value = (Value >> Offset) & 0xFF;
+  }
+
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *     @param[in]   FieldName - Name of field to be set
+ *     @param[in]   Field - Value to be programmed
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  SBDFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if (FieldName < BFEndOfList) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = TSEFO_TYPE (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        Address |= 0x0100;
+      }
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+
+      if (Type == NB_ACCESS) {
+        Address |= (((UINT32) (24 + 0)) << 15);
+        PciAddr.AddressValue = Address;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+        Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+        } else {
+          IDS_ERROR_TRAP;
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBRegTable   - Pointer to the NB Table *
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableDA (
+  IN OUT   TSEFO *NBRegTable
+  )
+{
+  UINT16 i;
+  for (i = 0; i <= BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8, 8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemRecNIsIdSupportedDA
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ */
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+
+  if ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h
new file mode 100755
index 0000000000..bb91de879d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnda.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * mnda.h
+ *
+ * Northbridge Ridgeback Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRNDA_H_
+#define _MRNDA_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_NODE_DA          2
+#define MAX_CHANNELS_PER_DCT_DA       1
+
+#define _4GB_RJ8    ((UINT32)4 << (30 - 8))
+#define MTRR_VALID  11
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemRecConstructNBBlockDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemRecNSwitchDctDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemRecNSwitchChannelDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+VOID
+MemRecNFinalizeMctDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+
+#endif  /* _MRNDA_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c
new file mode 100755
index 0000000000..fef338d71f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DA/mrnmctda.c
@@ -0,0 +1,129 @@
+/**
+ * @file
+ *
+ * mrnmctda.c
+ *
+ * Northbridge DA MCT supporting functions Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnda.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNFinalizeMctDA (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+
+  // Recommended settings for F2x11C
+  MemRecNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
+  MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+  MemRecNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
+  MemRecNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
+
+  LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (!NBPtr->ClToNbFlag) {
+    SMsr.lo &= ~((UINT32) 1 << 15);                // ClLinesToNbDis
+  }
+  LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.hi &= ~((UINT32) 1 << (48 - 32));               // WbEnhWsbDis
+  LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c
new file mode 100755
index 0000000000..e21d498b71
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.c
@@ -0,0 +1,644 @@
+/**
+ * @file
+ *
+ * mrndr.c
+ *
+ * Common Northbridge  functions for Ridgeback Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrndr.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   0x20000000
+#define CHANNEL_SELECT  0x10000000
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableDR (
+  IN OUT   TSEFO *NBRegTable
+  );
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]       NodeID   - Node ID for this NB block
+ *
+ *     @return          TRUE  - This node is a RB and this NB block has been initialized
+ *     @return          FALSE - This node is not a RB
+ */
+
+BOOLEAN
+MemRecConstructNBBlockDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemRecNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  MCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_DR * (
+                                              sizeof (CH_DEF_STRUCT) + (
+                                                MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
+                                              )
+                                            )
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT);
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) {
+      MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+      MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+      MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+    }
+  }
+
+  //
+  //  Initialize NB block's variables
+  //
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+  NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+
+  MemRecNInitNBRegTableDR (NBPtr->NBRegTable);
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+  LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->InitRecovery = MemRecNMemInitNb;
+
+  NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
+  NBPtr->SwitchDCT = MemRecNSwitchDctDR;
+  NBPtr->SwitchChannel = MemRecNSwitchChannelDR;
+  NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
+  NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
+  NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
+  NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
+  NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
+
+  NBPtr->GetBitField = MemRecNGetBitFieldNb;
+  NBPtr->SetBitField = MemRecNSetBitFieldNb;
+  NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
+  NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldDR;
+  NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyDR;
+  NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctDR;
+  NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
+  NBPtr->MemRecNFinalizeMctNb =  MemRecNFinalizeMctDR;
+  NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
+  NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
+  MemRecNSwitchDctDR (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemRecNSwitchDctDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  NBPtr->Dct = Dct & 1;
+  NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+
+  MemRecNSwitchChannelDR (NBPtr, NBPtr->Channel);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemRecNSwitchChannelDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = Channel & 1;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Byte;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+
+  ASSERT (Dimm < 4);
+  ASSERT (Byte < 8);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    Offset = 16 * (Byte % 2);
+    break;
+
+  case AccessRdDqsDly:
+    Field &= ~ 0x0001;
+  case AccessWrDatDly:
+    Index += (Dimm * 0x100);
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+  Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+    while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    Value = (Value >> Offset) & 0xFF;
+  }
+
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *     @param[in]   FieldName - Name of field to be set
+ *     @param[in]   Field - Value to be programmed
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  SBDFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if (FieldName < BFEndOfList) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = TSEFO_TYPE (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        Address |= 0x0100;
+      }
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+
+      if (Type == NB_ACCESS) {
+        Address |= (((UINT32) (24 + 0)) << 15);
+        PciAddr.AddressValue = Address;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+        Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+        } else {
+          IDS_ERROR_TRAP;
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBRegTable   - Pointer to the NB Table *
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableDR (
+  IN OUT   TSEFO *NBRegTable
+  )
+{
+  UINT16 i;
+  for (i = 0; i <= BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8, 8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemRecNIsIdSupportedDr
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ */
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedDr (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+
+  if ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL
+                               | AMD_F10_BL_ALL
+                               | AMD_F10_DA_ALL )) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h
new file mode 100755
index 0000000000..ecc0ac4884
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrndr.h
@@ -0,0 +1,103 @@
+/**
+ * @file
+ *
+ * mndr.h
+ *
+ * Northbridge Ridgeback Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRNDR_H_
+#define _MRNDR_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_NODE_DR          2
+#define MAX_CHANNELS_PER_DCT_DR       1
+
+#define _4GB_RJ8    ((UINT32)4 << (30 - 8))
+#define MTRR_VALID  11
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemRecConstructNBBlockDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemRecNSwitchDctDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemRecNSwitchChannelDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+VOID
+MemRecNFinalizeMctDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MRNDR_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
new file mode 100755
index 0000000000..a6243fd2f5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
@@ -0,0 +1,130 @@
+/**
+ * @file
+ *
+ * mrnmctdr.c
+ *
+ * Northbridge DR MCT supporting functions Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mrndr.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNFinalizeMctDR (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+
+  // Recommended settings for F2x11C
+  MemRecNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
+  MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
+  MemRecNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
+  MemRecNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
+
+  LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (!NBPtr->ClToNbFlag) {
+    SMsr.lo &= ~((UINT32) 1 << 15);                // ClLinesToNbDis
+  }
+  LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.hi &= ~((UINT32) 1 << (48 - 32));               // WbEnhWsbDis
+  LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c
new file mode 100755
index 0000000000..97ad7b37c8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrndcthy.c
@@ -0,0 +1,152 @@
+/**
+ * @file
+ *
+ * mrndctHy.c
+ *
+ * Northbridge DCT support for Hydra Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mru.h"
+#include "mrnhy.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   Set Dram ODT for mission mode and write leveling mode.
+ *
+ *     @param[in,out]   *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       OdtMode    - Mission mode or write leveling mode
+ *     @param[in]       ChipSelect - Chip select number
+ *     @param[in]       TargetCS   - Chip select number that is being trained
+ *
+ */
+
+VOID
+MemRecNSetDramOdtHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       ODT_MODE OdtMode,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 TargetCS
+  )
+{
+  UINT8 Dimms;
+  UINT8 *DimmsPerChPtr;
+  UINT8 MaxDimmsPerChannel;
+  UINT8 DramTerm;
+  UINT8 DramTermDyn;
+  UINT8 WrLvOdt;
+  BOOLEAN IsDualRank;
+
+  Dimms = NBPtr->ChannelPtr->Dimms;
+  IsDualRank = ((NBPtr->ChannelPtr->DimmDrPresent & (UINT8) 1 << (ChipSelect >> 1)) != 0) ? TRUE : FALSE;
+
+  // Dram nominal termination
+  if (Dimms == 1) {
+    DramTerm = 1;   // 60 Ohms
+  } else {
+    DramTerm = 3;   // 40 Ohms
+  }
+
+  // Dram dynamic termination
+  if (Dimms < 2) {
+    DramTermDyn = 0;    // Disabled
+  } else {
+    DramTermDyn = 2;    // 120 Ohms
+  }
+
+  if (OdtMode == WRITE_LEVELING_MODE) {
+    if (ChipSelect == TargetCS) {
+      DramTerm = DramTermDyn;
+
+      // Program WrLvOdt, the target DIMM should be the closest DIMM.
+      DimmsPerChPtr = MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, 0, NBPtr->ChannelPtr->ChannelID);
+      if (DimmsPerChPtr != NULL) {
+        MaxDimmsPerChannel = *DimmsPerChPtr;
+      } else {
+        MaxDimmsPerChannel = 2;
+      }
+
+      if (MaxDimmsPerChannel == 3) {
+        if (NBPtr->ChannelPtr->DimmQrPresent != 0) {
+          WrLvOdt = 0xF;
+        } else {
+          WrLvOdt = 7;
+        }
+      } else {
+        if (NBPtr->ChannelPtr->DimmQrPresent != 0) {
+          WrLvOdt = 0xB;
+        } else if (Dimms == 2) {
+          WrLvOdt = 3;
+        } else if (IsDualRank) {
+          WrLvOdt = 8;
+        } else {
+          WrLvOdt = 2;
+        }
+      }
+      MemRecNSetBitFieldNb (NBPtr, BFWrLvOdt, WrLvOdt);
+    }
+  }
+  MemRecNSetBitFieldNb (NBPtr, BFDramTerm, DramTerm);
+  MemRecNSetBitFieldNb (NBPtr, BFDramTermDyn, DramTermDyn);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c
new file mode 100755
index 0000000000..0541703719
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.c
@@ -0,0 +1,700 @@
+/**
+ * @file
+ *
+ * mrnhy.c
+ *
+ * Common Northbridge  functions for Hydra Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnhy.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define MAX_DCTS_PER_DIE 2
+#define SPLIT_CHANNEL   0x20000000
+#define CHANNEL_SELECT  0x10000000
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableHy (
+  IN OUT   TSEFO *NBRegTable
+  );
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+VOID
+STATIC
+MemRecNSwitchNodeHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 NodeID
+  );
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]       NodeID   - Node ID for this NB block
+ *
+ *     @return          TRUE  - This node is a Hydra and this NB block has been initialized
+ *     @return          FALSE - This node is not a Hydra
+ */
+
+BOOLEAN
+MemRecConstructNBBlockHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemRecNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  MCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_HY * (
+                                              sizeof (CH_DEF_STRUCT) + (
+                                                MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
+                                              )
+                                            )
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  MemPtr->DiesPerSystem[NodeID + 1].DctCount = MAX_DCTS_PER_NODE_HY;
+  MemPtr->DiesPerSystem[NodeID + 1].DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT);
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) {
+      MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+      MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+      MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+    }
+  }
+
+  //
+  //  Initialize NB block's variables
+  //
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->AllNodeMCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+  NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+
+  MemRecNInitNBRegTableHy (NBPtr->NBRegTable);
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+  LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->InitRecovery = MemRecNMemInitNb;
+
+  NBPtr->SwitchNodeRec = MemRecNSwitchNodeHy;
+  NBPtr->SwitchDCT = MemRecNSwitchDctHy;
+  NBPtr->SwitchChannel = MemRecNSwitchChannelHy;
+  NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
+  NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
+  NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
+  NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
+  NBPtr->SetDramOdtRec = MemRecNSetDramOdtHy;
+
+  NBPtr->GetBitField = MemRecNGetBitFieldNb;
+  NBPtr->SetBitField = MemRecNSetBitFieldNb;
+  NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
+
+  NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldHy;
+  NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyHy;
+  NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctHy;
+  NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
+  NBPtr->MemRecNFinalizeMctNb =  MemRecNFinalizeMctHy;
+  NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
+  MemRecNSwitchDctHy (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets the current die to work on.
+ *   Should be called before accessing a certain die
+ *   All data structures will be updated to point to the current node
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   NodeID - ID of the target die
+ *
+ */
+
+VOID
+STATIC
+MemRecNSwitchNodeHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 NodeID
+  )
+{
+  NBPtr->MCTPtr = &(NBPtr->AllNodeMCTPtr[NodeID]);
+  NBPtr->Node = NodeID;
+  NBPtr->MCTPtr->NodeId = NodeID;
+  MemRecNSwitchDctHy (NBPtr, NBPtr->Dct);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemRecNSwitchDctHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  NBPtr->Dct = Dct & 1;
+  NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[(NBPtr->MCTPtr->NodeId * MAX_DCTS_PER_DIE + Dct) * MAX_DIMMS_PER_CHANNEL]);
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+
+  MemRecNSwitchChannelHy (NBPtr, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemRecNSwitchChannelHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = 0;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[0]);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 index;
+  UINT16 offset;
+  UINT32 value;
+  UINT32 address;
+  UINT8 DIMM;
+  UINT8 Rank;
+  UINT8 Byte;
+  UINT8 Nibble;
+
+  DIMM = DRBN_DIMM (DrbnVar);
+  Rank = DRBN_RANK (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+  Nibble = DRBN_NBBL (DrbnVar);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    index = 0x30;
+    break;
+  case AccessWrDatDly:
+    index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    index = 0x05;
+    break;
+  case AccessPhRecDly:
+    index = 0x50;
+    break;
+  default:
+    index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    index += (DIMM * 3);
+    if ((Byte & 0x04) != 0) {
+      // if byte 4,5,6,7
+      index += 0x10;
+    }
+    if ((Byte & 0x02) != 0) {
+      // if byte 2,3,6,7
+      index++;
+    }
+    if (Byte > 7) {
+      index += 2;
+    }
+    offset = 16 * (Byte % 2);
+    index |= (Rank << 8);
+    index |= (Nibble << 9);
+    break;
+
+  case AccessRdDqsDly:
+    Field &= ~ 0x0001;
+  case AccessWrDatDly:
+    index += (DIMM * 0x100);
+    if (Nibble != 0) {
+      if (Rank != 0) {
+        index += 0xA0;
+      } else {
+        index += 0x70;
+      }
+    } else if (Rank != 0) {
+      index += 0x60;
+    }
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    index += (Byte / 4);
+    offset = 8 * (Byte % 4);
+    break;
+  default:
+    offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  address = index;
+  MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
+  while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+  value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet != 0) {
+    if (TrnDly == AccessPhRecDly) {
+      value = NBPtr->DctCachePtr->PhRecReg[index & 0x03];
+    }
+
+    value = ((UINT32)Field << offset) | (value & (~((UINT32)0xFF << offset)));
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, value);
+    address |= DCT_ACCESS_WRITE;
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
+    while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[index & 0x03] = value;
+    }
+  } else {
+    value = (value >> offset) & 0xFF;
+  }
+
+  return value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Name of Field to be set
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  SBDFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if (FieldName < BFEndOfList) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address != 0) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = TSEFO_TYPE (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if (((Address & 0xF000) == 0x2000) && (NBPtr->Dct != 0)) {
+        Address |= 0x0100;
+      }
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+
+      if (Type == NB_ACCESS) {
+        // Address |= (((UINT32) (24 + 0)) << 15);
+        PciAddr.AddressValue = Address;
+        // Fix for MCM
+        PciAddr.Address.Device = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Device;
+        PciAddr.Address.Bus = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Bus;
+        PciAddr.Address.Segment = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Segment;
+        Address = PciAddr.AddressValue;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+        Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet != 0) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+        } else {
+          IDS_ERROR_TRAP;
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes bit field translation table
+ *
+*     @param[in,out]   *NBRegTable   - Pointer to the NB Table *
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableHy (
+  IN OUT   TSEFO *NBRegTable
+  )
+{
+  UINT16 i;
+  for (i = 0; i <= BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  5,  5, BFSubMemclkRegDly);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8, 8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31,  0, BFMctCfgHiReg);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemRecNIsIdSupportedHy
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ *     @return          TRUE -  This node is a Hydra.
+ *     @return          FALSE - This node is not a Hydra.
+ *
+ */
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+  if ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h
new file mode 100755
index 0000000000..ff36edd7bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnhy.h
@@ -0,0 +1,111 @@
+/**
+ * @file
+ *
+ * mnhy.h
+ *
+ * Northbridge Hydra Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRNHY_H_
+#define _MRNHY_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DCTS_PER_NODE_HY          2
+#define MAX_CHANNELS_PER_DCT_HY       1
+
+#define _4GB_RJ8    ((UINT32)4 << (30 - 8))
+#define MTRR_VALID  11
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemRecConstructNBBlockHY (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemRecNSwitchDctHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemRecNSwitchChannelHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+VOID
+MemRecNSetDramOdtHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       ODT_MODE OdtMode,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 TargetCS
+  );
+
+VOID
+MemRecNFinalizeMctHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+#endif  /* _MRNHY_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
new file mode 100755
index 0000000000..5c65d5f96c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
@@ -0,0 +1,126 @@
+/**
+ * @file
+ *
+ * mrnmctdr.c
+ *
+ * Northbridge DR MCT supporting functions Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnhy.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets final values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNFinalizeMctHy (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+  // Recommended settings for F2x11C
+  MemRecNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x2CE00F60);
+
+  LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (!NBPtr->ClToNbFlag) {
+    SMsr.lo &= ~((UINT32) 1 << 15);                // ClLinesToNbDis
+  }
+  LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.hi &= ~((UINT32) 1 << (48 - 32));               // WbEnhWsbDis
+  LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
new file mode 100755
index 0000000000..8dc35f5510
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * mrnproto.c
+ *
+ * Northbridge support functions for Errata and early samples Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+
+#include "AGESA.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE
+/*
+ *-----------------------------------------------------------------------------
+ *                                EXPORTED FUNCTIONS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c
new file mode 100755
index 0000000000..beaf1c6ebc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.c
@@ -0,0 +1,641 @@
+/**
+ * @file
+ *
+ * mrnNi.c
+ *
+ * Common Northbridge  functions for Nile Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mrnda.h"
+#include "mrnNi.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define SPLIT_CHANNEL   0x20000000
+#define CHANNEL_SELECT  0x10000000
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableNi (
+  IN OUT   TSEFO *NBRegTable
+  );
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  );
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes the northbridge block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in]       NodeID   - Node ID for this NB block
+ *
+ *     @return          TRUE  - This node is a RB and this NB block has been initialized
+ *     @return          FALSE - This node is not a RB
+ */
+
+BOOLEAN
+MemRecConstructNBBlockNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  DIE_STRUCT *MCTPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  //
+  // Determine if this is the expected NB Type
+  //
+  GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+  if (!MemRecNIsIdSupportedNi (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
+    return FALSE;
+  }
+
+  //
+  // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
+  //
+  MCTPtr = &MemPtr->DiesPerSystem[NodeID];
+  AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
+                                          sizeof (DCT_STRUCT) + (
+                                            MAX_CHANNELS_PER_DCT_DA * (
+                                              sizeof (CH_DEF_STRUCT) + (
+                                                MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
+                                              )
+                                            )
+                                          )
+                                        );
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    return FALSE;
+  }
+
+  MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
+  MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
+  AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
+  for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
+    MCTPtr->DctData[Dct].Dct = Dct;
+    MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
+    MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+    MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
+    AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
+    for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
+      MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+      MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
+      MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
+      AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
+    }
+  }
+
+  //
+  //  Initialize NB block's variables
+  //
+  NBPtr->MemPtr = MemPtr;
+  NBPtr->RefPtr = MemPtr->ParameterListPtr;
+  NBPtr->MCTPtr = MCTPtr;
+  NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+  NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
+
+  NBPtr->DctCachePtr = NBPtr->DctCache;
+
+  MemRecNInitNBRegTableNi (NBPtr->NBRegTable);
+  NBPtr->Dct = 0;
+  NBPtr->Channel = 0;
+  NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
+
+  LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
+  LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
+
+  NBPtr->InitRecovery = MemRecNMemInitNb;
+
+  NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
+  NBPtr->SwitchDCT = MemRecNSwitchDctNi;
+  NBPtr->SwitchChannel = MemRecNSwitchChannelNi;
+  NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
+  NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
+  NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
+  NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
+  NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
+
+  NBPtr->GetBitField = MemRecNGetBitFieldNb;
+  NBPtr->SetBitField = MemRecNSetBitFieldNb;
+  NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
+  NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
+  NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldNi;
+  NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyNi;
+  NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctNi;
+  NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
+  NBPtr->MemRecNFinalizeMctNb =  MemRecNFinalizeMctDA;
+  NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
+  NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
+  MemRecNSwitchDctNi (NBPtr, 0);
+
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current DCT to work on.
+ *   Should be called before accessing a certain DCT
+ *   All data structures will be updated to point to the current DCT
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Dct - ID of the target DCT
+ *
+ */
+
+VOID
+MemRecNSwitchDctNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  )
+{
+  NBPtr->Dct = Dct & 1;
+  NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
+  NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
+
+  MemRecNSwitchChannelNi (NBPtr, NBPtr->Channel);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the current channel to work on.
+ *   Should be called before accessing a certain channel
+ *   All data structures will be updated to point to the current channel
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   Channel - ID of the target channel
+ *
+ */
+
+VOID
+MemRecNSwitchChannelNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  )
+{
+  NBPtr->Channel = Channel & 1;
+  NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or set DQS timing during training.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNcmnGetSetTrainDlyNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  UINT16 Index;
+  UINT16 Offset;
+  UINT32 Value;
+  UINT32 Address;
+  UINT8 Dimm;
+  UINT8 Byte;
+
+  Dimm = DRBN_DIMM (DrbnVar);
+  Byte = DRBN_BYTE (DrbnVar);
+
+  ASSERT (Dimm < 4);
+  ASSERT (Byte < 8);
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+    Index = 0x10;
+    break;
+  case AccessWrDqsDly:
+    Index = 0x30;
+    break;
+  case AccessWrDatDly:
+    Index = 0x01;
+    break;
+  case AccessRdDqsDly:
+    Index = 0x05;
+    break;
+  case AccessPhRecDly:
+    Index = 0x50;
+    break;
+  default:
+    Index = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  switch (TrnDly) {
+  case AccessRcvEnDly:
+  case AccessWrDqsDly:
+    Index += (Dimm * 3);
+    if (Byte & 0x04) {
+      // if byte 4,5,6,7
+      Index += 0x10;
+    }
+    if (Byte & 0x02) {
+      // if byte 2,3,6,7
+      Index++;
+    }
+    Offset = 16 * (Byte % 2);
+    break;
+
+  case AccessRdDqsDly:
+    Field &= ~ 0x0001;
+  case AccessWrDatDly:
+    Index += (Dimm * 0x100);
+    // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+    // to run AccessPhRecDly sequence.
+  case AccessPhRecDly:
+    Index += (Byte / 4);
+    Offset = 8 * (Byte % 4);
+    break;
+  default:
+    Offset = 0;
+    IDS_ERROR_TRAP;
+  }
+
+  Address = Index;
+  MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+  while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+  Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+
+  if (IsSet) {
+    if (TrnDly == AccessPhRecDly) {
+      Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+    }
+
+    Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+    Address |= DCT_ACCESS_WRITE;
+    MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+    while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+    if (TrnDly == AccessPhRecDly) {
+      NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
+    }
+  } else {
+    Value = (Value >> Offset) & 0xFF;
+  }
+
+  return Value;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets or sets a value to a bit field in a PCI register.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   IsSet - Indicates if the function will set or get
+ *     @param[in]   FieldName - Name of field to be set
+ *     @param[in]   Field - Value to be programmed
+ *
+ *     @return      value read, if the function is used as a "get"
+ */
+
+UINT32
+STATIC
+MemRecNCmnGetSetFieldNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  SBDFO Address;
+  PCI_ADDR PciAddr;
+  UINT8 Type;
+  UINT32 Value;
+  UINT32 Highbit;
+  UINT32 Lowbit;
+  UINT32 Mask;
+
+  Value = 0;
+  if (FieldName < BFEndOfList) {
+    Address = NBPtr->NBRegTable[FieldName];
+    if (Address) {
+      Lowbit = TSEFO_END (Address);
+      Highbit = TSEFO_START (Address);
+      Type = TSEFO_TYPE (Address);
+
+      // If Fn2 and DCT1 selected, set Address to be 1xx
+      if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
+        Address |= 0x0100;
+      }
+      if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
+        // Special DCT Phy access
+        Address &= 0x0FFFFFFF;
+        Lowbit = 0;
+        Highbit = 16;
+      } else {
+        // Normal DCT Phy access
+        Address = TSEFO_OFFSET (Address);
+      }
+
+
+      if (Type == NB_ACCESS) {
+        Address |= (((UINT32) (24 + 0)) << 15);
+        PciAddr.AddressValue = Address;
+        LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+      } else if (Type == DCT_PHY_ACCESS) {
+        MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+        while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+
+        Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+      } else {
+        IDS_ERROR_TRAP;
+      }
+
+      if (IsSet) {
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        } else {
+          Mask = (UINT32)0xFFFFFFFF;
+        }
+        Value &= ~(Mask << Lowbit);
+        Value |= (Field & Mask) << Lowbit;
+
+        if (Type == NB_ACCESS) {
+          PciAddr.AddressValue = Address;
+          LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
+        } else if (Type == DCT_PHY_ACCESS) {
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+          Address |= DCT_ACCESS_WRITE;
+
+          MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+          while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
+        } else {
+          IDS_ERROR_TRAP;
+        }
+      } else {
+        Value = Value >> Lowbit;  // Shift
+        // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+        if ((Highbit - Lowbit) != 31) {
+          Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
+        }
+      }
+    }
+  } else {
+    IDS_ERROR_TRAP;   // Invalid bit field index
+  }
+  return Value;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initializes bit field translation table
+ *
+ *     @param[in,out]   *NBRegTable   - Pointer to the NB Table *
+ */
+
+VOID
+STATIC
+MemRecNInitNBRegTableNi (
+  IN OUT   TSEFO *NBRegTable
+  )
+{
+  UINT16 i;
+  for (i = 0; i <= BFEndOfList; i++) {
+    NBRegTable[i] = 0;
+  }
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31,  0, BFDevVendorIDReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60),  2,  0, BFNodeID);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31,  0, BFCSBaseAddr2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31,  0, BFCSBaseAddr3Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31,  0, BFCSBaseAddr4Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31,  0, BFCSBaseAddr5Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31,  0, BFCSBaseAddr6Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31,  0, BFCSBaseAddr7Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31,  0, BFCSMask0Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31,  0, BFCSMask1Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31,  0, BFCSMask2Reg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31,  0, BFCSMask3Reg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31,  0, BFDramControlReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31,  0, BFDramInitRegReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31,  0, BFDramBankAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31,  0, BFDramMRSReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84),  9,  7, BFDramTerm);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31,  0, BFDramTimingLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31,  0, BFDramTimingHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31,  0, BFDramConfigLoReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31,  0, BFDramConfigHiReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31,  0, BFDctAddlOffsetReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31,  0, BFDctAddlDataReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4),  4,  0, BFNbFid);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15,  0, BFMrsAddress);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C),  7,  7, BFLevel);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90),  0,  0, BFInitDram);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  8,  8, BFDdr3Mode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94),  9,  9, BFLegacyBiosMode);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8),  6,  6, BFOdtSwizzle);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110),  8, 8, BFDramEnabled);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
+
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C),  6,  2, BFMctWrLimit);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31,  0, BFODCControl);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31,  0, BFAddrTmgControl);
+
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  0,  0, BFWrtLvTrEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  1,  1, BFWrtLvTrMode);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08,  5,  4, BFTrDimmSel);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11,  8, BFWrLvOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
+
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *     MemRecNIsIdSupportedNi
+ *      This function matches the CPU_LOGICAL_ID with certain criteria to
+ *      determine if it is supported by this NBBlock.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *
+ */
+BOOLEAN
+STATIC
+MemRecNIsIdSupportedNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       CPU_LOGICAL_ID *LogicalIdPtr
+  )
+{
+
+  if ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h
new file mode 100755
index 0000000000..e3ebc43d54
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/NI/mrnNi.h
@@ -0,0 +1,95 @@
+/**
+ * @file
+ *
+ * mrnNi.h
+ *
+ * Northbridge Ni Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRNNI_H_
+#define _MRNNI_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _4GB_RJ8    ((UINT32)4 << (30 - 8))
+#define MTRR_VALID  11
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemRecConstructNBBlockNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+VOID
+MemRecNSwitchDctNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Dct
+  );
+
+VOID
+MemRecNSwitchChannelNi (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 Channel
+  );
+
+#endif  /* _MRNNI_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
new file mode 100755
index 0000000000..c55243806f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrn.c
@@ -0,0 +1,188 @@
+/**
+ * @file
+ *
+ * mrn.c
+ *
+ * Common Northbridge  functions for Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem/NB)
+ * @e \$Revision: 12594 $ @e \$Date: 2009-04-22 11:04:41 -0500 (Wed, 22 Apr 2009) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "mm.h"
+#include "mn.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_MRN_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define MAX_DCTS_PER_DIE 2
+#define SPLIT_CHANNEL   0x20000000
+#define CHANNEL_SELECT  0x10000000
+#define MAX_DELAYS    9   /* 8 data bytes + 1 ECC byte */
+#define MAX_DIMMS     4   /* 4 DIMMs per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets a bit field from PCI register
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Field name
+ *
+ *     @return      Bit field value
+ */
+
+UINT32
+MemRecNGetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName
+  )
+{
+  return NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0);
+}
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets a bit field from PCI register
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   FieldName - Field name
+ *     @param[in]   Field - Value to be stored in PCT register
+ *
+ */
+
+VOID
+MemRecNSetBitFieldNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BIT_FIELD_NAME FieldName,
+  IN       UINT32 Field
+  )
+{
+  NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets a delay value a PCI register during training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *
+ *     @return      Value read
+ */
+
+UINT32
+MemRecNGetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar
+  )
+{
+  return NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 0, TrnDly, DrbnVar, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets a delay value a PCI register during training
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   TrnDly - type of delay to be set
+ *     @param[in]   DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
+ *                  (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
+ *     @param[in]   Field - Value to be programmed
+ *
+ */
+
+VOID
+MemRecNSetTrainDlyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  )
+{
+  NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 1, TrnDly, DrbnVar, Field);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c
new file mode 100755
index 0000000000..ee0e54a4b4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrndct.c
@@ -0,0 +1,621 @@
+/**
+ * @file
+ *
+ * mrndct.c
+ *
+ * Northbridge common DCT support for Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem/NB)
+ * @e \$Revision: 6781 $ @e \$Date: 2008-07-17 12:11:08 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "cpuFamRegisters.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mru.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define RECDEF_DRAM_CONTROL_REG   0x320C2A06
+#define RECDEF_DRAM_MRSREG        0x000400A4
+#define RECDEF_DRAM_TIMING_LO     0x000A0092
+#define RECDEF_DRAM_TIMING_HI     0xB6D218FF
+#define RECDEF_CSMASK_REG         0x00083FE0
+#define RECDEF_DRAM_CONFIG_LO_REG 0x00000000
+#define RECDEF_DRAM_CONFIG_HI_REG 0x1F48010B
+#define RECDEF_DRAM_BASE_REG      0x00000003
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+MemRecTCtlOnDimmMirrorNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BOOLEAN SetFlag
+  );
+
+VOID
+STATIC
+MemRecNSwapBitsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function programs the memory controller with configuration parameters
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_ERROR may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
+ */
+
+BOOLEAN
+MemRecNAutoConfigNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dimm;
+  UINT8 Dct;
+  UINT32 RegValue;
+  UINT8 ChipSel;
+  UINT32 CSBase;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  Dct = NBPtr->Dct;
+  DCTPtr = NBPtr->DCTPtr;
+  ChannelPtr = NBPtr->ChannelPtr;
+
+  //Prepare variables for future usage.
+  for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+    if ((ChannelPtr->ChDimmValid & (UINT8) 1 << Dimm) != 0) {
+      DCTPtr->Timings.CsPresent |= (UINT16) 1 << (Dimm * 2);
+      if (((ChannelPtr->DimmDrPresent & (UINT8) 1 << Dimm) == 0) && ((ChannelPtr->DimmQrPresent & (UINT8) 1 << Dimm) == 0)) {
+        continue;
+      } else {
+        DCTPtr->Timings.CsPresent |= (UINT16) 1 << (Dimm * 2 + 1);
+      }
+    }
+  }
+
+  Dimm = NBPtr->DimmToBeUsed;
+
+  //Temporarily set all CS Base/Limit registers (corresponding to Dimms exist on a channel) with 256MB size for WL training.
+  CSBase = 0;
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+    if (DCTPtr->Timings.CsPresent & (UINT8) 1 << ChipSel) {
+
+      CSBase &= (UINT32) ~0x08; //Clear OnDimmMirror bit.
+      if (((ChipSel & 1) != 0) && ((ChannelPtr->DimmMirrorPresent & (UINT8) 1 << (ChipSel >> 1)) != 0)) {
+        CSBase |= (UINT32) 0x08; //Set OnDimmMirror bit.
+      }
+      MemRecNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (CSBase | 0x01));
+      CSBase += 0x100000;
+      if ((ChipSel & 1) == 0) {
+        MemRecNSetBitFieldNb (NBPtr, (BFCSMask0Reg + (ChipSel >> 1)), RECDEF_CSMASK_REG);
+      }
+    }
+  }
+  MemRecNSetBitFieldNb (NBPtr, BFDramBaseReg0, RECDEF_DRAM_BASE_REG);
+  MemRecNSetBitFieldNb (NBPtr, BFDramLimitReg0, 0x70000);
+
+  // Disable the other DCT
+  NBPtr->MemRecNSwitchDctNb (NBPtr, Dct ^ 0x01);
+  MemRecNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
+  NBPtr->MemRecNSwitchDctNb (NBPtr, Dct);
+  if (Dct != 0) {
+    // If DCT 1, set DctSelBase registers
+    MemRecNSetBitFieldNb (NBPtr, BFDctSelBaseAddrReg, 0x00000003);
+    MemRecNSetBitFieldNb (NBPtr, BFDctSelBaseOffsetReg, 0x00000000);
+  }
+
+  MemRecNSetBitFieldNb (NBPtr, BFDramBankAddrReg, 0x00001111);
+
+  // Set timing registers
+  MemRecNSetBitFieldNb (NBPtr, BFDramTimingLoReg, RECDEF_DRAM_TIMING_LO);
+  MemRecNSetBitFieldNb (NBPtr, BFDramTimingHiReg, RECDEF_DRAM_TIMING_HI);
+  MemRecNSetBitFieldNb (NBPtr, BFDramMRSReg, RECDEF_DRAM_MRSREG);
+  MemRecNSetBitFieldNb (NBPtr, BFDramControlReg, RECDEF_DRAM_CONTROL_REG);
+
+  // Set DRAM Config Low Register
+  RegValue = RECDEF_DRAM_CONFIG_LO_REG;
+  // Set x4Dimm based on DIMM type
+  if ((NBPtr->ChannelPtr->Dimmx4Present & ((UINT8) 1 << Dimm)) != 0) {
+    RegValue |= ((UINT32) 1 << (Dimm + 12));
+  }
+  // If not registered, set unbuffered DIMM
+  if (!(NBPtr->ChannelPtr->RegDimmPresent & ((UINT8) 1 << Dimm))) {
+    RegValue |= ((UINT32) 1 << 16);
+  }
+  MemRecNSetBitFieldNb (NBPtr, BFDramConfigLoReg, RegValue);
+
+  // Set DRAM Config High Register
+  RegValue = RECDEF_DRAM_CONFIG_HI_REG;
+  MemRecNSetBitFieldNb (NBPtr, BFDramConfigHiReg, RegValue);
+
+  //======================================================================
+  // Build Dram Config Misc Register Value
+  //======================================================================
+  //
+  if ((NBPtr->ChannelPtr->RegDimmPresent != 0) && (NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY)) {
+    MemRecNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
+  }
+  MemRecNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
+
+  return TRUE;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function gets platform specific config/timing values from the interface layer and
+ *   programs them into DCT.
+ *
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          TRUE - An Error value lower than AGESA_ERROR may have occurred
+ *     @return          FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
+ */
+
+BOOLEAN
+MemRecNPlatformSpecNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 MaxDimmPerCH;
+  UINT32 AddrTmgValue;
+  UINT32 DrvStrValue;
+  UINT8 *DimmsPerChPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ChannelPtr = NBPtr->ChannelPtr;
+  DimmsPerChPtr = MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, 0, ChannelPtr->ChannelID);
+  if (DimmsPerChPtr != NULL) {
+    MaxDimmPerCH = *DimmsPerChPtr;
+  } else {
+    MaxDimmPerCH = 2;
+  }
+
+  if (ChannelPtr->RegDimmPresent) {
+    if (MaxDimmPerCH == 2) {
+      DrvStrValue = 0x20223222;
+      AddrTmgValue = 0;
+      if ((ChannelPtr->Dimms == 1) && (ChannelPtr->DimmQrPresent == 0)) {
+        DrvStrValue = 0x20113222;
+      }
+    } else if (MaxDimmPerCH == 3) {
+      DrvStrValue = 0x20223222;
+      AddrTmgValue = 0;
+      if ((ChannelPtr->Dimms == 1) && (ChannelPtr->DimmQrPresent == 0)) {
+        DrvStrValue = 0x20113222;
+      } else if (ChannelPtr->Dimms == 3) {
+        AddrTmgValue = 0x00380038;
+      }
+    } else {
+      DrvStrValue = 0x20223222;
+      AddrTmgValue = 0;
+      if (ChannelPtr->Dimms >= 3) {
+        AddrTmgValue = 0x002F0000;
+      } else if (ChannelPtr->Dimms == 1) {
+        DrvStrValue = 0x20113222;
+      }
+    }
+  } else {
+    if (ChannelPtr->Dimms == 2) {
+      DrvStrValue = 0x20223323;
+      AddrTmgValue = 0x00390039;
+    } else {
+      DrvStrValue = 0x20113222;
+      AddrTmgValue = 0;
+      if ((ChannelPtr->Dimms == 1) && (ChannelPtr->Loads >= 16)) {
+        AddrTmgValue = 0x003B0000;
+      }
+    }
+  }
+  MemRecNSetBitFieldNb (NBPtr, BFODCControl, DrvStrValue);
+  MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrTmgValue);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function  reads MemClkFreqVal bit to see if the DIMMs are present in this node.
+ *  If the DIMMs are present then set the DRAM Enable bit for this node.
+ *
+ *  Setting dram init starts up the DCT state machine, initializes the
+ *  dram devices with MRS commands, and kicks off any
+ *  HW memory clear process that the chip is capable of.  The sooner
+ *  that dram init is set for all nodes, the faster the memory system
+ *  initialization can complete.  Thus, the init loop is unrolled into
+ *  two loops so as to start the processes for non BSP nodes sooner.
+ *  This procedure will not wait for the process to finish.  Synchronization is
+ *  handled elsewhere.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNStartupDCTNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1.
+  // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
+  // ------- Done in InitPhyComp_Nb -------
+  //
+  MemRecNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
+  MemRecUWait10ns (500, NBPtr->MemPtr);
+
+  //MemRecNSetBitFieldNb (NBPtr, BFInitDram, 1);    // HW Dram init
+  AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
+  NBPtr->TechPtr->DramInit (NBPtr->TechPtr);
+
+  // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0.
+  // 8. BIOS must wait 750 us for the phy compensation engine
+  //    to reinitialize.
+  //
+  MemRecNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
+  MemRecUWait10ns (75000, NBPtr->MemPtr);
+
+  while (MemRecNGetBitFieldNb (NBPtr, BFDramEnabled) == 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function  sets the maximum round-trip latency in the system from the processor to the DRAM
+ *   devices and back.
+
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]     MaxRcvEnDly - Maximum receiver enable delay value
+ *
+ */
+
+VOID
+MemRecNSetMaxLatencyNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT16 MaxRcvEnDly
+  )
+{
+  UINT16 SubTotal;
+
+  AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
+
+  // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs.
+  SubTotal = 6 * 2;
+
+  // If registered DIMMs are being used then add 1 MEMCLK to the sub-total.
+  if (MemRecNGetBitFieldNb (NBPtr, BFUnBuffDimm) == 0) {
+    SubTotal += 2;
+  }
+
+  // if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2;
+  SubTotal += 2;
+
+  // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
+  // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total.
+  //
+  SubTotal += 8 - 5;
+
+  // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay
+  // that exists across all DIMMs and byte lanes.
+  //
+  SubTotal += MaxRcvEnDly >> 5;
+
+  // Add 5.5 to the sub-total. 5.5 represents part of the processor
+  // specific constant delay value in the DRAM clock domain.
+  //
+  SubTotal += 5;             // add 5.5 1/2MemClk
+
+  // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs)
+  // as follows (assuming DDR400 and assuming that no P-state or link speed
+  // changes have occurred).
+  //
+  //     Simplified formula:
+  //     SubTotal *= (Fn2xD4[NBFid]+4)/4
+  //
+  SubTotal = SubTotal * ((UINT16) MemRecNGetBitFieldNb (NBPtr, BFNbFid) + 4);
+  SubTotal /= 4;
+
+  // Add 5 NCLKs to the sub-total. 5 represents part of the processor
+  // specific constant value in the northbridge clock domain.
+  //
+  SubTotal += 5;
+
+  // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value
+  MemRecNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   Set Dram ODT for mission mode and write leveling mode.
+ *
+ *     @param[in,out]   *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in]       OdtMode    - Mission mode or write leveling mode
+ *     @param[in]       ChipSelect - Chip select number
+ *     @param[in]       TargetCS   - Chip select number that is being trained
+ *
+ */
+
+VOID
+MemRecNSetDramOdtNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       ODT_MODE OdtMode,
+  IN       UINT8 ChipSelect,
+  IN       UINT8 TargetCS
+  )
+{
+  UINT8 Dimms;
+  UINT8 DramTerm;
+  UINT8 DramTermDyn;
+  BOOLEAN IsDualRank;
+
+  Dimms = NBPtr->ChannelPtr->Dimms;
+  IsDualRank = (NBPtr->DCTPtr->Timings.CsPresent & (ChipSelect + 1)) ? TRUE : FALSE;
+
+  if (OdtMode == WRITE_LEVELING_MODE) {
+    DramTermDyn = 0;  // Disabled
+
+    if (ChipSelect & 1) {
+      DramTerm = 0;   // Disabled
+    } else if (Dimms == 1) {
+      DramTerm = 1;   // 60 Ohms
+    } else {
+      DramTerm = 3;   // 40 Ohms
+    }
+
+    if (ChipSelect == TargetCS) {
+      if (Dimms == 2) {
+        DramTerm = 2;   // 120 Ohms
+      } else if (IsDualRank) {
+        DramTerm = 0;   // Disabled
+      }
+
+      // Program WrLvOdt
+      MemRecNSetBitFieldNb (NBPtr, BFWrLvOdt, 0x0F);
+    } else if (ChipSelect == (TargetCS + 1)) {
+      if (Dimms == 1) {
+        DramTerm = 1;   // 60 Ohms
+      }
+    }
+  } else {
+    // Dram nominal termination
+    if (Dimms == 1) {
+      DramTerm = 1;   // 60 Ohms
+    } else {
+      DramTerm = 3;   // 40 Ohms
+    }
+
+    // Dram dynamic termination
+    if (Dimms < 2) {
+      DramTermDyn = 0;    // Disabled
+    } else {
+      DramTermDyn = 2;    // 120 Ohms
+    }
+  }
+  MemRecNSetBitFieldNb (NBPtr, BFDramTerm, DramTerm);
+  MemRecNSetBitFieldNb (NBPtr, BFDramTermDyn, DramTermDyn);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends an MRS command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNSendMrsCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  BOOLEAN ClearODM;
+  ClearODM = FALSE;
+  if (NBPtr->IsSupported[CheckClearOnDimmMirror]) {
+    ClearODM = FALSE;
+    if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
+      if (NBPtr->IsSupported[CheckClearOnDimmMirror]) {
+        if (MemRecNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) {
+          // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS
+          MemRecTCtlOnDimmMirrorNb (NBPtr, FALSE);
+          ClearODM = TRUE;
+        }
+      }
+    }
+  }
+
+  MemRecNSwapBitsNb (NBPtr);
+
+  IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n",
+              (MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              (MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
+              (MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
+
+  // 1.Set SendMrsCmd=1
+  MemRecNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
+
+  // 2.Wait for SendMrsCmd=0
+  while (MemRecNGetBitFieldNb (NBPtr, BFSendMrsCmd)) {}
+
+  if (NBPtr->IsSupported[CheckClearOnDimmMirror]) {
+    if (ClearODM) {
+      // Restore ODM if necessary
+      MemRecTCtlOnDimmMirrorNb (NBPtr, TRUE);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends the ZQCL command
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNSendZQCmdNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  // 1.Program MrsAddress[10]=1
+  MemRecNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32) 1 << 10);
+
+  // 2.Set SendZQCmd=1
+  MemRecNSetBitFieldNb (NBPtr, BFSendZQCmd, 1);
+
+  // 3.Wait for SendZQCmd=0
+  while (MemRecNGetBitFieldNb (NBPtr, BFSendZQCmd)) {}
+
+  // 4.Wait 512 MEMCLKs
+  MemRecUWait10ns (128, NBPtr->MemPtr);   // 512*2.5ns=1280, wait 1280ns
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in]   SetFlag   - Enable or disable flag - TRUE - Enable, FALSE - DISABLE
+ *
+ */
+
+VOID
+STATIC
+MemRecTCtlOnDimmMirrorNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       BOOLEAN SetFlag
+  )
+{
+  UINT8 Chipsel;
+  UINT32 CSBaseAddrReg;
+
+  for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) {
+    CSBaseAddrReg = MemRecNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel);
+    if ((CSBaseAddrReg & 1) == 1) {
+      if (SetFlag && ((NBPtr->ChannelPtr->DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) {
+        CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror);
+      } else {
+        CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror);
+      }
+      MemRecNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg);
+    }
+  }
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function swaps bits for OnDimmMirror support
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemRecNSwapBitsNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 ChipSel;
+  UINT32 MRSReg;
+
+  ChipSel = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFMrsChipSel);
+  if ((ChipSel & 1) != 0) {
+    MRSReg = MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg);
+    if ((NBPtr->ChannelPtr->DimmMirrorPresent & (UINT8) 1 << (ChipSel >> 1)) != 0) {
+      MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1);
+      MemRecNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c
new file mode 100755
index 0000000000..6c0432a853
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrnmct.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * mrnmct.c
+ *
+ * Northbridge Common MCT supporting functions Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem/NB)
+ * @e \$Revision: 6783 $ @e \$Date: 2008-07-17 13:07:51 -0500 (Thu, 17 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCacheInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is the Recovery memory configuration function for Nb DDR3
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+
+AGESA_STATUS
+MemRecNMemInitNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  AGESA_STATUS Status;
+  MEM_TECH_BLOCK *TechPtr;
+
+  TechPtr = NBPtr->TechPtr;
+
+  MemRecNInitializeMctNb (NBPtr);
+
+  if (NBPtr->IsSupported[DramModeBeforeDimmPres]) {
+    TechPtr->SetDramMode (TechPtr);
+  }
+
+  Status = AGESA_FATAL;
+  if (TechPtr->DimmPresence (TechPtr)) {
+
+    if (NBPtr->IsSupported[DramModeAfterDimmPres]) {
+      TechPtr->SetDramMode (TechPtr);
+    }
+
+    if (MemRecNAutoConfigNb (NBPtr)) {
+
+      AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &(NBPtr->MemPtr->StdHeader));
+      if (MemRecNPlatformSpecNb (NBPtr)) {
+        AGESA_TESTPOINT (TpProcMemStartDcts, &(NBPtr->MemPtr->StdHeader));
+        MemRecNStartupDCTNb (NBPtr);
+
+        AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(NBPtr->MemPtr->StdHeader));
+        MemRecNCPUMemRecTypingNb (NBPtr);
+
+        AGESA_TESTPOINT (TpProcMemDramTraining, &(NBPtr->MemPtr->StdHeader));
+        NBPtr->TrainingFlow (NBPtr);
+
+        Status = AGESA_SUCCESS;
+      }
+    }
+  }
+
+  NBPtr->MemRecNFinalizeMctNb (NBPtr);
+
+  return Status;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets initial values in BUCFG and BUCFG2
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNInitializeMctNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MEM_DATA_STRUCT *MemPtr;
+  S_UINT64 SMsr;
+
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  if (SMsr.lo & ((UINT32) 1 << 15)) {
+    NBPtr->ClToNbFlag = TRUE;
+  }
+  SMsr.lo |= (UINT32) 1 << 15;                   // ClLinesToNbDis
+  LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.hi |= (UINT32) 1 << (48 - 32);              // WbEnhWsbDis
+  LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function returns a physical address of a corresponding Chip select
+ *
+ *     @return      Addr -  System Address
+ */
+
+UINT32
+MemRecNGetMCTSysAddrNb (
+  )
+{
+  UINT32 CSBase;
+
+  CSBase = (UINT32) 1 << 21;       // 1MB offset to avoid compat area from the base address.
+  if ((CSBase >= (MCT_TRNG_KEEPOUT_START << 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END << 8))) {
+    CSBase += (((MCT_TRNG_KEEPOUT_END << 8) - CSBase) + 0x0FFFFF) & 0xFFF00000;
+  }
+
+  return CSBase;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
+ *   It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *
+ */
+
+VOID
+MemRecNCPUMemRecTypingNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  //
+  //======================================================================
+  // Set default values for CPU registers
+  //======================================================================
+  //
+
+  LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo |= 0x1C0000;                // turn on modification enable bit and
+                                      // mtrr enable bits
+  LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  SMsr.lo = SMsr.hi = 0x1E1E1E1E;
+  LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // 0 - 512K = WB Mem
+  LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // 512K - 640K = WB Mem
+
+  //
+  //======================================================================
+  // Set TOP_MEM and TOM2 CPU registers
+  //======================================================================
+  //
+  SMsr.hi = 0;
+  SMsr.lo = 0x08000000;
+  LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);  // TOP_MEM
+
+  // Set FS Base address for later memory accesses
+  SMsr.lo = 0;
+  LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+
+  //
+  //======================================================================
+  // Set variable MTRR values
+  //======================================================================
+  //
+  SMsr.lo = 0x00000006;
+  LibAmdMsrWrite (0x200, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // MTRRPhysBase0
+
+  SMsr.hi = NBPtr->VarMtrrHiMsk;
+  SMsr.lo = 0xF8000800;
+  LibAmdMsrWrite (0x201, (UINT64 *)&SMsr, &MemPtr->StdHeader);      // MTRRPhysMask0
+
+}
+
+/*-----------------------------------------------------------------------------*/
+/**
+ *
+ *     This function returns the upper 32 bits mask for variable MTRR based on
+ *     the CPU_LOGICAL_ID.
+ *     @param[in]       *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
+ *     @param[in]       StdHeader - Header for library and services
+ *
+ *     @return          UINT32 - MTRR mask for upper 32 bits
+ *
+ */
+UINT32
+MemRecGetVarMtrrHiMsk (
+  IN       CPU_LOGICAL_ID *LogicalIdPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempNotCare;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  CACHE_INFO *CacheInfoPtr;
+
+  GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader);
+  return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
+}
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c
new file mode 100755
index 0000000000..9be59a169b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/NB/mrntrain3.c
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * mrntrain3.c
+ *
+ * Common Recovery Northbridge function for training flow for DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem/NB)
+ * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mrt3.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE
+/* features */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the training control flow
+ *      The DDR3 mode bit must be set prior to calling this function
+ *
+ *      @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ */
+VOID
+MemNRecTrainingFlowNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  MemRecTTrainDQSWriteHw3 (NBPtr->TechPtr);
+
+  MemRecTTrainRcvrEnSw (NBPtr->TechPtr);
+
+  MemRecTTrainDQSPosSw (NBPtr->TechPtr);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
new file mode 100755
index 0000000000..88bcc7670d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * mrt3.c
+ *
+ * Common Technology  functions for DDR3  Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mrt3.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function Constructs the technology block
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecConstructTechBlock3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  UINT8 Dct;
+  UINT8 Channel;
+  for (Dct = 0; Dct < NBPtr->MCTPtr->DctCount; Dct++) {
+    NBPtr->SwitchDCT (NBPtr, Dct);
+    for (Channel = 0; Channel < NBPtr->DCTPtr->ChannelCount; Channel++) {
+      NBPtr->SwitchChannel (NBPtr, Channel);
+      NBPtr->ChannelPtr->TechType = DDR3_TECHNOLOGY;
+    }
+  }
+
+  TechPtr->NBPtr = NBPtr;
+  TechPtr->RefPtr = NBPtr->RefPtr;
+
+  TechPtr->DramInit = MemRecTDramInitSw3;
+  TechPtr->SetDramMode = MemRecTSetDramMode3;
+  TechPtr->DimmPresence = MemRecTDIMMPresence3;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
new file mode 100755
index 0000000000..5f2d7e3840
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
@@ -0,0 +1,239 @@
+/**
+ * @file
+ *
+ * mrtrci3.c
+ *
+ * Technology Control word initialization for DDR3 Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mru.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+UINT8
+STATIC
+MemRecTGetCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CtrlWordNum
+  );
+
+VOID
+STATIC
+MemRecTSendCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CmdNum,
+  IN       UINT8 Value
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends control words
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  pDCT->Timings.TrwtTO updated
+ */
+
+VOID
+MemRecTDramControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 RCNum;
+  UINT8 Data;
+
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  // wait 8us TACT must be changed to optimize to 8 MEM CLKs
+  // and wait 6us for PLL LOCK
+  MemRecUWait10ns (80 + 60, MemPtr);
+
+  // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
+  NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (NBPtr->DimmToBeUsed << 1));
+
+  for (RCNum = 0; RCNum <= 15; RCNum++) {
+    // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
+    MemRecUWait10ns (80, MemPtr);
+
+    if ((RCNum != 6) && (RCNum != 7)) {
+      Data = MemRecTGetCtlWord3 (TechPtr, RCNum);
+      MemRecTSendCtlWord3 (TechPtr, RCNum, Data);
+    }
+  }
+
+  MemRecUWait10ns (60, MemPtr);   // wait 6us for TSTAB
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the ControlRC value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     CtrlWordNum  -  control Word number.
+ *
+ *     @return  Control Word value
+ */
+
+UINT8
+STATIC
+MemRecTGetCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CtrlWordNum
+  )
+{
+  UINT8  Data;
+
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Data = 0;  //Default value for all control words is 0
+  switch (CtrlWordNum) {
+  case 0:
+    Data = 0x02;  // DA4=1
+    break;
+  case 1:
+    Data = 0x0C;  // if single rank, set DBA1 and DBA0
+    break;
+  case 3:
+    Data = ChannelPtr->CtrlWrd03[TechPtr->NBPtr->DimmToBeUsed];
+    break;
+  case 4:
+    Data = ChannelPtr->CtrlWrd04[TechPtr->NBPtr->DimmToBeUsed];
+    break;
+  case 5:
+    Data = ChannelPtr->CtrlWrd05[TechPtr->NBPtr->DimmToBeUsed];
+    break;
+  case 9:
+    Data = 0x0D;
+    break;
+  default:;
+  }
+
+  return (Data&0x0F);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sends control word command
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]     CmdNum  -  control number.
+ *     @param[in]     Value  -  value to send
+ *
+ */
+
+VOID
+STATIC
+MemRecTSendCtlWord3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 CmdNum,
+  IN       UINT8 Value
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  ASSERT (CmdNum < 16);
+  ASSERT (Value < 16);
+
+  NBPtr = TechPtr->NBPtr;
+
+  // 1. Program MrsBank and MrsAddress.
+  //    n = [BA2, A2, A1, A0].
+  //    data = [BA1, BA0, A4, A3].
+  //    Set all other bits in MrsAddress to zero.
+  //
+  NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum&8) >> 1) | (Value >> 2));
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value&3) << 3) | (CmdNum&7));
+  IDS_HDT_CONSOLE ("\t\tCS%d RC%02d %04x\n",
+              (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
+              ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 15) & 8) |
+              (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) & 7),
+              ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 14) & 0xC) |
+              ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 3) & 3));
+
+  // 2.Set SendCtrlWord=1
+  NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1);
+  // 3.Wait for BFSendCtrlWord=0
+  while (NBPtr->GetBitField (NBPtr, BFSendCtrlWord) != 0) {}
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
new file mode 100755
index 0000000000..aa5156659d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
@@ -0,0 +1,348 @@
+/**
+ * @file
+ *
+ * mrtsdi3.c
+ *
+ * Technology Software DRAM Init for DDR3 Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "mm.h"
+#include "mn.h"
+#include "mru.h"
+#include "mt.h"
+#include "mrt3.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function initiates software DRAM init
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTDramInitSw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 ChipSel;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  // 3.Program F2x[1,0]7C[EnDramInit]=1
+  NBPtr->SetBitField (NBPtr, BFEnDramInit, 1);
+
+  // 4.wait 200us
+  MemRecUWait10ns (20000, MemPtr);
+
+  NBPtr->SetBitField (NBPtr, BFDeassertMemRstX, 1);
+
+  // 6.wait 500us
+  MemRecUWait10ns (50000, MemPtr);
+
+  // 7.NOP or deselect & take CKE high
+  NBPtr->SetBitField (NBPtr, BFAssertCke, 1);
+
+  // 8.wait 360ns
+  MemRecUWait10ns (36, MemPtr);
+
+  // The following steps are performed with registered DIMMs only and
+  // must be done for each chip select pair:
+  //
+  if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
+    MemRecTDramControlRegInit3 (TechPtr);
+  }
+
+  //
+  // In recovery mode, we only need to initialize one chipsel for UDIMMs.
+  //
+  NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, 0, 0);
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+    if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) {
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+      // 13.Send EMRS(2)
+      MemRecTEMRS23 (TechPtr);
+      NBPtr->SendMrsCmd (NBPtr);
+
+      // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
+      MemRecTEMRS33 (TechPtr);
+      NBPtr->SendMrsCmd (NBPtr);
+
+      // 15.Send EMRS(1).
+      MemRecTEMRS13 (TechPtr);
+      NBPtr->SendMrsCmd (NBPtr);
+
+      // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
+      MemRecTMRS3 (TechPtr);
+      NBPtr->SendMrsCmd (NBPtr);
+
+      //wait 500us
+      MemRecUWait10ns (50000, MemPtr);
+
+      if (NBPtr->ChannelPtr->RegDimmPresent == 0) {
+        break;
+      }
+    }
+  }
+
+  // 17.Send two ZQCL commands (to even then odd chip select)
+  NBPtr->sendZQCmd (NBPtr);
+  NBPtr->sendZQCmd (NBPtr);
+
+  // 18.Program F2x[1,0]7C[EnDramInit]=0
+  NBPtr->SetBitField (NBPtr, BFEnDramInit, 0);
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS1 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTEMRS13 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT16 MrsAddress;
+  UINT8 DramTerm;
+
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=0,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
+
+  MrsAddress = 0;
+
+  // program MrsAddress[5,1]=output driver impedance control (DIC):
+  // based on F2x[1,0]84[DrvImpCtrl], which is 2'b01
+  MrsAddress |= ((UINT16) 1 << 1);
+
+  // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
+  // based on F2x[1,0]84[DramTerm], which is 3'b001 (60 Ohms)
+  DramTerm = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTerm);
+  if ((DramTerm & 1) != 0) {
+    MrsAddress |= ((UINT16) 1 << 2);
+  }
+  if ((DramTerm & 2) != 0) {
+    MrsAddress |= ((UINT16) 1 << 6);
+  }
+  if ((DramTerm & 4) != 0) {
+    MrsAddress |= ((UINT16) 1 << 9);
+  }
+
+  // program MrsAddress[12]=output disable (QOFF):
+  // based on F2x[1,0]84[Qoff], which is 1'b0
+
+  // program MrsAddress[11]=TDQS:
+  // based on F2x[1,0]94[RDqsEn], which is 1'b0
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS2 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTEMRS23 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT16 MrsAddress;
+  UINT8 DramTermDyn;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=1,BA0=0
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
+
+  // program MrsAddress[5:3]=CAS write latency (CWL):
+  // based on F2x[1,0]84[Tcwl], which is 3'b000
+  //
+  MrsAddress = 0;
+
+  // program MrsAddress[6]=auto self refresh method (ASR):
+  // based on F2x[1,0]84[ASR], which is 1'b1
+  // program MrsAddress[7]=self refresh temperature range (SRT):
+  // based on F2x[1,0]84[SRT], which is also 1'b0
+  //
+  MrsAddress |= (UINT16) 1 << 6;
+
+  // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
+  // based on F2x[1,0]84[DramTermDyn]
+  //
+  DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn);
+  MrsAddress |= (UINT16) DramTermDyn << 9;
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function calculates the EMRS3 value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTEMRS33 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=1,BA0=1
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
+
+  // program MrsAddress[1:0]=multi purpose register address location
+  // (MPR Location):based on F2x[1,0]84[MprLoc], which is 0
+  // program MrsAddress[2]=multi purpose register
+  // (MPR):based on F2x[1,0]84[MprEn], which is also 0
+  //
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This sets MSS value
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTMRS3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT16 MrsAddress;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  // BA2=0,BA1=0,BA0=0
+  NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
+
+  // program MrsAddress[1:0]=burst length and control method
+  // (BL):based on F2x[1,0]84[BurstCtrl], which is 1'b0
+  //
+  MrsAddress = 0;
+
+  // program MrsAddress[3]=1 (BT):interleaved
+  MrsAddress |= (UINT16) 1 << 3;
+
+  // program MrsAddress[6:4,2]=read CAS latency
+  // (CL):based on F2x[1,0]88[Tcl], which is 4'b0010
+  MrsAddress |= (UINT16) 2 << 4;
+
+  // program MrsAddress[11:9]=write recovery for auto-precharge
+  // (WR):based on F2x[1,0]84[Twr], which is 3'b010
+  //
+  MrsAddress |= (UINT16) 2 << 9;
+
+  // program MrsAddress[12]=0 (PPD):slow exit
+
+  // program MrsAddress[8]=1 (DLL):DLL reset
+  MrsAddress |= (UINT16) 1 << 8;   // just issue DLL reset at first time
+
+  NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
new file mode 100755
index 0000000000..f39655d701
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
@@ -0,0 +1,269 @@
+/**
+ * @file
+ *
+ * mrtspd3.c
+ *
+ * Technology SPD supporting functions for DDR3 Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "mrtspd3.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define _UNDEF_ 0xFF
+#define MAX_DIES_PER_SOCKET     2   ///< Set to largest of any CPU
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function sets the DRAM mode
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that the DRAM mode is set to DDR2
+ */
+
+BOOLEAN
+MemRecTSetDramMode3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
+  TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1);
+  return TRUE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *   This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ *     @return  TRUE - indicates that a FATAL error has not occurred
+ *     @return  FALL - indicates that a FATAL error has not occurred
+ */
+
+BOOLEAN
+MemRecTDIMMPresence3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  UINT8 Node;
+  UINT8 Dct;
+  UINT8 Channel;
+  UINT8 i;
+  SPD_DEF_STRUCT *SPDPtr;
+  UINT8 *SpdBufferPtr;
+  DIE_STRUCT *MCTPtr;
+  DCT_STRUCT *DCTPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  MEM_NB_BLOCK *NBPtr;
+  UINT16 MaxDimms;
+  UINT16 Value16;
+  UINT8 Devwidth;
+  UINT8 Value8;
+  UINT16 DimmMask;
+
+  NBPtr = TechPtr->NBPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  NBPtr->DimmToBeUsed = _UNDEF_;
+  for (Node = 0; Node < MAX_DIES_PER_SOCKET; Node++) {
+    NBPtr->SwitchNodeRec (NBPtr, Node);
+    for (Dct = 0; Dct < NBPtr->MCTPtr->DctCount; Dct++) {
+      NBPtr->SwitchDCT (NBPtr, Dct);
+      DCTPtr = NBPtr->DCTPtr;
+      for (Channel = 0; Channel < DCTPtr->ChannelCount; Channel++) {
+        NBPtr->SwitchChannel (NBPtr, Channel);
+        ChannelPtr = NBPtr->ChannelPtr;
+        SPDPtr = NBPtr->SPDPtr;
+
+        // Get the maximum number of DIMMs
+        MaxDimms = MAX_DIMMS_PER_CHANNEL;
+        for (i = 0; i < MaxDimms; i++) {
+          //  Bitmask representing dimm #i.
+          DimmMask = (UINT16) 1 << i;
+
+          if (SPDPtr[i].DimmPresent) {
+            SpdBufferPtr = (UINT8 *)&(SPDPtr[i].Data);
+
+            MCTPtr->DimmPresent |= DimmMask;
+            if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) {
+              ChannelPtr->ChDimmValid |= DimmMask;
+              if (NBPtr->DimmToBeUsed == _UNDEF_) {
+                NBPtr->DimmToBeUsed = i;
+              }
+            }
+
+            //  Check module type information.
+            if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) {
+              ChannelPtr->RegDimmPresent |= DimmMask;
+            }
+
+            if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) {
+              ChannelPtr->SODimmPresent |= DimmMask;
+            }
+
+            //  Get the Dimm width data
+            Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7;
+            switch (Devwidth) {
+            case 0:
+              ChannelPtr->Dimmx4Present |= DimmMask;
+              Devwidth = 4;
+              break;
+            case 1:
+              ChannelPtr->Dimmx8Present |= DimmMask;
+              Devwidth = 8;
+              break;
+            case 2:
+              ChannelPtr->Dimmx16Present |= DimmMask;
+              Devwidth = 16;
+              break;
+            default:
+              IDS_ERROR_TRAP;
+            }
+
+            //  Determine the page size.
+            //       page_size = 2^COLBITS * Devwidth/8
+            //
+            Value16 = (((UINT16) 1 << (SpdBufferPtr[SPD_COL_SZ]&7)) * Devwidth) / 8;
+            if ((Value16 >> 11) == 0) {
+              DCTPtr->Timings.DIMM1KPage |= DimmMask;
+            }
+
+            //  Calculate bus loading per Channel
+            if (Devwidth == 16) {
+              Devwidth = 4;
+            } else if (Devwidth == 4) {
+              Devwidth = 16;
+            }
+
+            //  specify the number of ranks
+            Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
+            if (Value8 > 2) {
+              ChannelPtr->DimmQrPresent |= DimmMask;
+              Devwidth = Devwidth << 2;
+            } else if (Value8 == 2) {
+              ChannelPtr->DimmDrPresent |= DimmMask;   //  Dual rank dimms
+              Devwidth = Devwidth << 1;
+            }
+
+            ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
+            ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
+            ChannelPtr->Dimms++;
+
+            // Check address mirror support for Unbuffered Dimms only
+            if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) {
+              if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
+                ChannelPtr->DimmMirrorPresent |= DimmMask;
+              }
+            }
+
+            // Get control word values for RC3, RC4 and RC5
+            ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4;
+            ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F;
+            ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4;
+          } // if DIMM present
+        } // Dimm loop
+
+        if (ChannelPtr->ChDimmValid != 0) {
+          // exit loops
+          Channel = DCTPtr->ChannelCount;
+          Dct = NBPtr->MCTPtr->DctCount;
+          Node = MAX_DIES_PER_SOCKET;
+        }
+      } // Channel loop
+    } // DCT loop
+  }
+
+  //  If we have DIMMs, some further general characteristics checking
+  if (NBPtr->DimmToBeUsed == _UNDEF_) {
+    //  Leave with an error - no dimms on this DCT
+    // LibAmdEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND, 0, NBPtr->Dct, NBPtr->Channel, 0);   //@attention commented out since it is not defined in recovery code
+    SetMemRecError (AGESA_FATAL, MCTPtr);
+  }
+
+  return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
new file mode 100755
index 0000000000..7c003a9d2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
@@ -0,0 +1,129 @@
+/**
+ * @file
+ *
+ * mrtspd3.h
+ *
+ * Technology SPD support for DDR3 Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MTSPD3_H_
+#define _MTSPD3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*===============================================================================
+ *   Jedec DDR III
+ *===============================================================================
+ */
+#define SPD_BYTE_USED     0
+#define SPD_TYPE          2              /* SPD byte read location */
+#define JED_DDR_SDRAM     7              /* Jedec defined bit field */
+#define JED_DDR2_SDRAM    8              /* Jedec defined bit field */
+#define JED_DDR3SDRAM   0xB              /* Jedec defined bit field */
+
+#define SPD_DIMM_TYPE    3
+#define SPD_ATTRIB      21
+#define JED_DIF_CK_MSK    0x20            /* Differential Clock Input */
+#define JED_RDIMM       1
+#define JED_MINIRDIMM   5
+#define JED_UDIMM       2
+#define JED_SODIMM       3
+
+#define SPD_L_BANKS      4               /* [7:4] number of [logical] banks on each device */
+#define SPD_DENSITY     4               /* bit 3:0 */
+#define SPD_ROW_SZ       5               /* bit 5:3 */
+#define SPD_COL_SZ       5               /* bit 2:0 */
+#define SPD_RANKS       7               /* bit 5:3 */
+#define SPD_DEV_WIDTH    7               /* bit 2:0 */
+#define SPD_ECCBITS     8               /* bit 4:3 */
+#define JED_ECC         8
+#define SPD_RAWCARD     62              /* bit 2:0 */
+#define SPD_ADDRMAP     63              /* bit 0 */
+
+#define SPD_CTLWRD03     70              /* bit 7:4 */
+#define SPD_CTLWRD04     71              /* bit 3:0 */
+#define SPD_CTLWRD05     71              /* bit 7:4 */
+
+#define SPD_DIVIDENT    10
+#define SPD_DIVISOR     11
+
+#define SPD_TCK         12
+#define SPD_CASLO       14
+#define SPD_CASHI       15
+#define SPD_TAA         16
+
+#define SPD_TRP         20
+#define SPD_TRRD        19
+#define SPD_TRCD        18
+#define SPD_TRAS        22
+#define SPD_TWR         17
+#define SPD_TWTR        26
+#define SPD_TRTP        27
+#define SPD_TRC         23
+#define SPD_UPPER_TRC   21              /* bit 7:4 */
+#define SPD_UPPER_TRAS  21              /* bit 3:0 */
+#define SPD_TFAW        29
+#define SPD_UPPER_TFAW  28              /* bit 3:0 */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#endif  /* _MTSPD3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
new file mode 100755
index 0000000000..bd9fbb9858
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
@@ -0,0 +1,340 @@
+/**
+ * @file
+ *
+ * mrttwl3.c
+ *
+ * Technology Phy assisted write levelization for recovery DDR3
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 5674 $ @e \$Date: 2008-04-04 13:22:37 -0500 (Fri, 04 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "Ids.h"
+#include "mm.h"
+#include "mn.h"
+#include "mru.h"
+#include "mt.h"
+#include "mrt3.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_BYTELANES 8             /* Max Bytelanes per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecTPrepareDIMMs3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       BOOLEAN Wl
+  );
+
+VOID
+STATIC
+MemRecTProcConfig3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+STATIC
+MemRecTBeginWLTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executed hardware based write levelization for a specific die
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTTrainDQSWriteHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  //  Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
+  NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 1);
+  //  Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
+  NBPtr->SetBitField (NBPtr, BFZqcsInterval, 0);
+
+  // 1. Specify the target Dimm that is to be trained by programming
+  //     F2x[1, 0]9C_x08[TrDimmSel].
+  NBPtr->SetBitField (NBPtr, BFTrDimmSel, NBPtr->DimmToBeUsed);
+
+  // 2. Prepare the DIMMs for write levelization using DDR3-defined
+  // MR commands.
+  MemRecTPrepareDIMMs3 (TechPtr, TRUE);
+
+  // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to
+  //     satisfy DDR3-defined internal DRAM timing.
+  MemRecUWait10ns (10, NBPtr->MemPtr);
+
+  // 4. Configure the processor's DDR phy for write levelization training:
+  MemRecTProcConfig3 (TechPtr);
+
+  // 5. Begin write levelization training
+  MemRecTBeginWLTrain3 (TechPtr);
+
+  // 6. Configure DRAM Phy Control Register so that the phy stops driving write levelization ODT.
+  // Program WrLvOdtEn=0
+  NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0);
+
+  // Wait 10 MEMCLKs to allow for ODT signal settling.
+  MemRecUWait10ns (3, NBPtr->MemPtr);
+
+  // 7. Program the target Dimm back to normal operation
+  MemRecTPrepareDIMMs3 (TechPtr, FALSE);
+
+  //  13.Program F2x[1, 0]8C[DisAutoRefresh] = 0.
+  NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 0);
+  //  14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
+  NBPtr->SetBitField (NBPtr, BFZqcsInterval, 2);
+
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function prepares the DIMMS for Write Levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in] Wl - Indicates if WL mode should be enabled
+ *
+ */
+
+VOID
+STATIC
+MemRecTPrepareDIMMs3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       BOOLEAN Wl
+  )
+{
+  UINT8 ChipSel;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader));
+
+  for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
+    // Set Dram ODT based on current mode.
+    if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) {
+      if (Wl) {
+        NBPtr->SetDramOdtRec (NBPtr, WRITE_LEVELING_MODE, ChipSel, (NBPtr->DimmToBeUsed << 1));
+      } else {
+        NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, 0, 0);
+      }
+
+      NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
+
+      // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
+      MemRecTEMRS13 (TechPtr);
+      // Program Level
+      if (Wl) {
+        if ((ChipSel >> 1) == NBPtr->DimmToBeUsed) {
+          NBPtr->SetBitField (NBPtr, BFLevel, 1);
+          if (ChipSel & 1) {
+            // Output buffer disabled
+            NBPtr->SetBitField (NBPtr, BFMrsQoff, 1);
+          }
+        }
+      }
+      // Send command
+      NBPtr->SendMrsCmd (NBPtr);
+
+      // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
+      MemRecTEMRS23 (TechPtr);
+      // Send command
+      NBPtr->SendMrsCmd (NBPtr);
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function configures the DIMMS for Write Levelization
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemRecTProcConfig3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  CH_DEF_STRUCT *ChannelPtr;
+  UINT8 ByteLane;
+  UINT8 *Seed;
+  UINT8 DefaultSeed;
+  UINT8 CurrentSeed;
+  UINT8 Dimm;
+
+  NBPtr = TechPtr->NBPtr;
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Dimm = NBPtr->DimmToBeUsed;
+
+  // Program WrLvOdtEn=1
+  NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1);
+
+  // Wait 10 MEMCLKs to allow for ODT signal settling.
+  MemRecUWait10ns (3, NBPtr->MemPtr);
+
+  //  Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
+  //  the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
+  //  BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
+  //  use an initial total delay Value of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined
+  //  by design.
+
+  //  Get default seed
+  DefaultSeed = 0x1A;
+  if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
+    DefaultSeed = 0x41;
+  }
+
+  //  Get platform override seed
+  Seed = (UINT8 *) MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, NBPtr->MCTPtr->SocketId, ChannelPtr->ChannelID);
+
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    // This includes ECC as byte 8
+    CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
+    NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
+    ChannelPtr->WrDqsDlys[Dimm * MAX_BYTELANES + ByteLane] = CurrentSeed;
+  }
+
+  // Program F2x[1, 0]9C_x08[WrtLvTrMode]=0 for phy assisted training.
+
+  // Program F2x[1, 0]9C_x08[TrNibbleSel]=0
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function begins WL training for a specific DIMM
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemRecTBeginWLTrain3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  MEM_NB_BLOCK *NBPtr;
+  UINT8 ByteLane;
+  UINT8 Seed;
+  UINT8 Delay;
+  UINT8 Dimm;
+
+  NBPtr = TechPtr->NBPtr;
+
+  Dimm = NBPtr->DimmToBeUsed;
+  // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
+  NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
+
+  //  Wait 200 MEMCLKs. If executing pass 2, wait 32 MEMCLKs.
+  MemRecUWait10ns (50, NBPtr->MemPtr);
+
+  //  Program F2x[1, 0]9C_x08[WrtLlTrEn]=0.
+  NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0);
+
+  //  Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
+  //   for the target Dimm and save these values.
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    // This includes ECC as byte 8
+    Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane];
+    Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
+    if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
+      // If seed has gross delay of 0 and PRE has gross delay of 3,
+      // then round the total delay of TxDqs to 0.
+      Delay = 0;
+    }
+    NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
+    NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane] = Delay;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
new file mode 100755
index 0000000000..3c58bc994a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttpos.c
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * mttpos.c
+ *
+ * Technology DQS R/W position training. Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function hard-codes DQS position delays for all bytes
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTTrainDQSPosSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  //Hard Code Settings
+  MemRecTSetWrDatRdDqs (TechPtr, 0x0F);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c
new file mode 100755
index 0000000000..fc743cd479
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/Tech/mrttsrc.c
@@ -0,0 +1,499 @@
+/**
+ * @file
+ *
+ * mrttsrc.c
+ *
+ * Technology Software based DQS receiver enable training Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mm.h"
+#include "mn.h"
+#include "mru.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_BYTELANES 8             /* Max Bytelanes per channel */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+VOID
+STATIC
+MemRecTSetRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  );
+
+VOID
+STATIC
+MemRecTLoadRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  );
+
+BOOLEAN
+STATIC
+MemRecTSaveRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT8 CmpResult
+  );
+
+UINT8
+STATIC
+MemRecTCompare1ClPattern (
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+MemRecTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+STATIC
+MemRecTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function executes receiver enable training for BSP
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+MemRecTTrainRcvrEnSw (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  _16BYTE_ALIGN  UINT8  PatternBuffer[3 * 64];
+  UINT8  TestBuffer[120];
+  UINT8  *PatternBufPtr[2];
+  UINT32 TestAddr[4];
+  UINT8  TestResult;
+  UINT8 Receiver;
+  UINT8 i;
+  UINT8 j;
+  UINT16 RcvrEnDly;
+
+  MEM_DATA_STRUCT *MemPtr;
+  DIE_STRUCT *MCTPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+  MCTPtr = NBPtr->MCTPtr;
+
+  AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
+
+  // Set environment settings before training
+  MemRecTBeginTraining (TechPtr);
+
+  PatternBufPtr[0] = PatternBuffer;
+  MemRecUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64, &(MemPtr->StdHeader));
+  PatternBufPtr[1] = PatternBufPtr[0] + 128;
+  MemRecUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64, &(MemPtr->StdHeader));
+
+  // Begin receiver enable training
+  MemRecTSetWrDatRdDqs (TechPtr, 0);
+
+  // there are four receiver pairs, loosely associated with chipselects.
+  Receiver = NBPtr->DimmToBeUsed << 1;
+  TechPtr->DqsRcvEnSaved = 0;
+
+  TestAddr[0] = NBPtr->GetSysAddrRec (NBPtr);
+  TestAddr[1] = TestAddr[0] + BIGPAGE_X8;
+
+  IDS_HDT_CONSOLE ("\tDct %d\n", NBPtr->Dct);
+  IDS_HDT_CONSOLE ("\t\tCS %d\n", Receiver);
+  IDS_HDT_CONSOLE ("\t\t\tWrite to addresses:  %04x0000\n", TestAddr[0]);
+
+  // Sweep receiver enable delays
+  AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
+  for (RcvrEnDly = 0; RcvrEnDly < 0xFF; RcvrEnDly++) {
+
+    TestResult = 0xFF;
+    for (i = 0; i < 2; i++) {
+
+      // Set RcvrEn delay for all byte lanes
+      AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
+      MemRecTSetRcvrEnDly (TechPtr, Receiver, RcvrEnDly);
+
+      // Swap the test pointers such that even and odd steps alternate.
+      j = ((RcvrEnDly & 1) != 0) ? (i ^ 1) : i;
+
+      // Write, read and compare the first beat of data
+      AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
+      MemRecUWrite1CL (TestAddr[j], PatternBufPtr[j]);
+      AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
+      MemRecURead1CL (TestBuffer, TestAddr[j]);
+      AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
+      TestResult &= MemRecTCompare1ClPattern (TestBuffer, PatternBufPtr[j], &(MemPtr->StdHeader));
+      MemRecUProcIOClFlush (TestAddr[j], MemPtr);
+    }
+    IDS_HDT_CONSOLE ("%v0");
+    IDS_HDT_CONSOLE ("\t\t\tDly %3x%vh1\n", RcvrEnDly);
+    IDS_HDT_CONSOLE ("\t\t\t       %vh2\n");
+    IDS_HDT_CONSOLE ("\t\t\t       %vh3\n\n");
+
+    if (MemRecTSaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, TestResult)) {
+      // if all bytelanes pass
+      break;
+    }
+  }   // End of delay sweep
+
+  if (RcvrEnDly == 0xFF) {
+    // no passing window
+    // LibAmdEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, 0, NBPtr->Dct, NBPtr->Channel, 0);   //@attention commented out since it is not defined in recovery code
+    SetMemRecError (AGESA_ERROR, MCTPtr);
+  }
+
+  // set final delays
+  MemRecTLoadRcvrEnDly (TechPtr, Receiver);
+
+  // Clear training bit when done
+  NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
+
+  IDS_HDT_CONSOLE ("\t\tMaxRcvrEnDly: %03x\n", RcvrEnDly + 0x20);
+
+  // Set Max Latency for both channels
+  NBPtr->SetMaxLatency (NBPtr, RcvrEnDly + 0x20);
+
+  // Restore environment settings after training
+  MemRecTEndTraining (TechPtr);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      If WrDatDly is 0, this function sets the DQS Positions in preparation
+ *      for Receiver Enable Training. (Write Position is no delay, Read Position is 1.5 Memclock delay).
+ *      Otherwise it will set WrDat and RdDqs to center of data eye.
+ *
+ *     @param[in,out]   *TechPtr - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       WrDatDly - either 0 or 0x0F
+ *
+ */
+
+VOID
+MemRecTSetWrDatRdDqs (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 WrDatDly
+  )
+{
+  UINT8 ByteLane;
+  UINT8 Dimm;
+  UINT8 WrDqs;
+  UINT8 RdDqs;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+
+  Dimm = NBPtr->DimmToBeUsed;
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    WrDqs = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane];
+    NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs + WrDatDly);
+    RdDqs = (WrDatDly == 0) ? 0x2F : 0x0F;
+    NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), RdDqs);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *
+ */
+
+VOID
+STATIC
+MemRecTSetRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly
+  )
+{
+  UINT8 ByteLane;
+
+  ASSERT (Receiver <= MAX_CS_PER_CHANNEL);
+  for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+    TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly);
+  }
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function compares test pattern with data in buffer and return a pass/fail bitmap
+ *       for 8 Bytes
+ *
+ *     @param[in]       Buffer[]  -  Buffer data from DRAM (Measured data from DRAM) to compare
+ *     @param[in]       Pattern[]  - Pattern (Expected data in ROM/CACHE) to compare against
+ *     @param[in,out] StdHeader - The Pointer of AGESA Header.
+ *
+ *     @return  PASS - Bit map of results of comparison
+ */
+
+UINT8
+STATIC
+MemRecTCompare1ClPattern (
+  IN       UINT8 Buffer[],
+  IN       UINT8 Pattern[],
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 i;
+  UINT8 Pass;
+
+  Pass = 0xFF;
+  IDS_HDT_CONSOLE ("%v1 -");
+  IDS_HDT_CONSOLE ("%v2 -");
+  IDS_HDT_CONSOLE ("%v3 -");
+  for (i = 0; i < 8; i++) {
+    if (Buffer[i] != Pattern[i]) {
+      // if bytelane n fails
+      Pass &= ~((UINT16) 1 << (i % 8));    // clear bit n
+    }
+    IDS_HDT_CONSOLE ("%v1  %c", (Buffer[i] == Pattern[i]) ? 'P' : '.');
+    IDS_HDT_CONSOLE ("%v2 %02x", Buffer[i]);
+    IDS_HDT_CONSOLE ("%v3 %02x", Pattern[i]);
+  }
+  return Pass;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function saves passing DqsRcvEnDly values to the stack
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *     @param[in]       RcvEnDly  - receiver enable delay to be saved
+ *     @param[in]       CmpResult - compare result for Rank 0
+ *
+ *     @return  TRUE - All bytelanes pass
+ *     @return  FALSE - Some bytelanes fail
+ */
+
+BOOLEAN
+STATIC
+MemRecTSaveRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver,
+  IN       UINT16 RcvEnDly,
+  IN       UINT8 CmpResult
+  )
+{
+  UINT8 i;
+  UINT8 Passed;
+  UINT8 Saved;
+  UINT8 Mask;
+  UINT8 Dimm;
+
+  ASSERT (Receiver <= MAX_CS_PER_CHANNEL);
+
+  Passed = CmpResult;
+  Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@todo - false passes filter (subject to be replaced with a better solution)
+  Dimm = Receiver >> 1;
+  Mask = 1;
+  for (i = 0; i < 8; i++) {
+    if ((Passed & Mask) != 0) {
+      if ((Saved & Mask) == 0) {
+        TechPtr->NBPtr->ChannelPtr->RcvEnDlys[Dimm * MAX_BYTELANES + i] = (UINT8) (RcvEnDly + 0x20);
+        IDS_HDT_CONSOLE ("\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
+      }
+      Saved |= Mask;
+    }
+    Mask <<= 1;
+  }
+  TechPtr->DqsRcvEnSaved = Saved;
+
+  if (Saved == 0xFF) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function loads the DqsRcvEnDly from saved data and program to additional index
+ *  for DQS receiver enabled training
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *     @param[in]       Receiver  - Current Chip select value
+ *
+ */
+
+VOID
+STATIC
+MemRecTLoadRcvrEnDly (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Receiver
+  )
+{
+  UINT8 i;
+  UINT8 Dimm;
+  UINT16 Saved;
+  CH_DEF_STRUCT *ChannelPtr;
+
+  ASSERT (Receiver <= MAX_CS_PER_CHANNEL);
+  ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+
+  Dimm = Receiver >> 1;
+  Saved = TechPtr->DqsRcvEnSaved;
+  for (i = 0; i < 8; i++) {
+    if ((Saved & 1) != 0) {
+      TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
+      ChannelPtr->RcvEnDlys[Dimm * MAX_BYTELANES + i]);
+    }
+    Saved >>= 1;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the initial controller environment before training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemRecTBeginTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  S_UINT64 SMsr;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
+  LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32) 1 << 9)); // enable SSE2
+
+  LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);            // HWCR
+  TechPtr->HwcrLo = SMsr.lo;
+  SMsr.lo |= 0x00020000;                  // turn on HWCR.wrap32dis
+  SMsr.lo &= 0xFFFF7FFF;                  // turn off HWCR.SSEDIS
+  LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function sets the final controller environment after training.
+ *
+ *     @param[in,out]   *TechPtr   - Pointer to the MEM_TECH_BLOCK
+ *
+ */
+
+VOID
+STATIC
+MemRecTEndTraining (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  )
+{
+  S_UINT64 SMsr;
+  MEM_DATA_STRUCT *MemPtr;
+  MEM_NB_BLOCK  *NBPtr;
+
+  NBPtr = TechPtr->NBPtr;
+  MemPtr = NBPtr->MemPtr;
+
+  LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg);
+
+  LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  SMsr.lo = TechPtr->HwcrLo;
+  LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
new file mode 100755
index 0000000000..55cd0a8507
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrdef.c
@@ -0,0 +1,113 @@
+/**
+ * @file
+ *
+ * mdef.c
+ *
+ * Memory Controller header file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "mm.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_MRDEF_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *         This is the default return function
+ */
+
+VOID
+MemRecDefRet (VOID)
+{
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function programs the DCT with initial values
+ *
+ *
+ *     @param[in,out]   *MCTPtr  - Pointer to the DIE_STRUCT
+ *     @param[in]       Errorval - Error value
+ */
+
+VOID
+SetMemRecError (
+  IN       AGESA_STATUS  Errorval,
+  IN OUT   DIE_STRUCT *MCTPtr
+  )
+{
+  if (MCTPtr->ErrCode < Errorval) {
+    MCTPtr->ErrCode = Errorval;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c
new file mode 100755
index 0000000000..741ab3838e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrinit.c
@@ -0,0 +1,106 @@
+/**
+ * @file
+ *
+ * mrinit.c
+ *
+ * Initializer support functions for Recovery mode
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "mm.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_MRINIT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern PSO_TABLE DefaultPlatformMemoryConfiguration[];
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function initializes the default parameter, function pointers, build options
+ *   and SPD data for memory configuration
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+
+VOID
+AmdMemInitDataStructDefRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  MEM_PARAMETER_STRUCT *RefPtr;
+
+  RefPtr = MemPtr->ParameterListPtr;
+
+  // Memory Map/Mgt.
+  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+  RefPtr->BottomIo = 0xF0;
+
+  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c
new file mode 100755
index 0000000000..4dfd60b819
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrm.c
@@ -0,0 +1,287 @@
+/**
+ * @file
+ *
+ * mrm.c
+ *
+ * Main configuration for Recovery mode
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "OptionMemoryRecovery.h"
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_MRM_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define MAX_DIES_PER_SOCKET     2
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+extern MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[];
+extern MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[];
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecSPDDataProcess (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function is the Recovery memory configuration function for HY DDR3
+ *
+ *      Requirements:
+ *
+ *      Run-Time Requirements:
+ *      1. Complete Hypertransport Bus Configuration
+ *      2. AmdMemInitDataStructDef must be run to set default values
+ *      3. MSR bit to allow access to high PCI regs set on all nodes
+ *      4. BSP in Big Real Mode
+ *      5. Stack available
+ *      6. MCG_CTL=-1, MC4_EN=0 for all CPUs
+ *      7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
+ *      8. All var MTRRs reset to zero
+ *      9. State of NB_CFG.DisDatMsk set properly on all CPUs
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ *     @return          AGESA_STATUS
+ *                          - AGESA_ALERT
+ *                          - AGESA_FATAL
+ *                          - AGESA_SUCCESS
+ *                          - AGESA_WARNING
+ */
+
+AGESA_STATUS
+AmdMemRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  UINT8 Socket;
+  UINT8 Module;
+  UINT8 i;
+  AGESA_STATUS AgesaStatus;
+  PCI_ADDR Address;
+  MEM_NB_BLOCK NBBlock;
+  MEM_TECH_BLOCK TechBlock;
+  LOCATE_HEAP_PTR  SocketWithMem;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  IDS_HDT_CONSOLE_INIT (&MemPtr->StdHeader);
+
+  //
+  // Read SPD data
+  //
+  MemRecSPDDataProcess (MemPtr);
+
+  //
+  // Get the socket id from heap.
+  //
+  SocketWithMem.BufferHandle = AMD_REC_MEM_SOCKET_HANDLE;
+  if (HeapLocateBuffer (&SocketWithMem, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+    Socket = *(UINT8 *) SocketWithMem.BufferPtr;
+  } else {
+    ASSERT(FALSE);  // Socket handle not found
+    return AGESA_FATAL;
+  }
+
+  //
+  // Allocate buffer for memory init structures
+  //
+  AllocHeapParams.RequestedBufferSize = MAX_DIES_PER_SOCKET * sizeof (DIE_STRUCT);
+  AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
+    ASSERT(FALSE); // Heap allocation failed to allocate Die struct
+    return AGESA_FATAL;
+  }
+  MemPtr->DieCount = MAX_DIES_PER_SOCKET;
+  MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;
+
+  //
+  // Discover populated CPUs
+  //
+  for (Module = 0; Module < MAX_DIES_PER_SOCKET; Module++) {
+    if (GetPciAddress ((VOID *)MemPtr, Socket, Module, &Address, &AgesaStatus)) {
+      MemPtr->DiesPerSystem[Module].SocketId = Socket;
+      MemPtr->DiesPerSystem[Module].DieId = Module;
+      MemPtr->DiesPerSystem[Module].PciAddr.AddressValue = Address.AddressValue;
+    }
+  }
+
+  i = 0;
+  while (MemRecNBInstalled[i] != NULL) {
+    if (MemRecNBInstalled[i] (&NBBlock, MemPtr, 0) == TRUE) {
+      break;
+    }
+    i++;
+  };
+  if (MemRecNBInstalled[i] == NULL) {
+    ASSERT(FALSE);    // No NB installed
+    return AGESA_FATAL;
+  }
+  MemRecTechInstalled[0] (&TechBlock, &NBBlock);
+  NBBlock.TechPtr = &TechBlock;
+
+  IDS_HDT_CONSOLE_EXIT (&MemPtr->StdHeader);
+
+  return NBBlock.InitRecovery (&NBBlock);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
+ *
+ *     @param[in,out]   *MemPtr   - Pointer to the MEM_DATA_STRUCT
+ *
+ */
+
+VOID
+STATIC
+MemRecSPDDataProcess (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  BOOLEAN FindSocketWithMem;
+  UINT8 Channel;
+  UINT8 Dimm;
+  UINT8 MaxSockets;
+  UINT8 *SocketWithMem;
+  UINT8 Socket;
+  AGESA_STATUS AgesaStatus;
+  SPD_DEF_STRUCT *DimmSPDPtr;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+  AGESA_READ_SPD_PARAMS SpdParam;
+  ASSERT (MemPtr != NULL);
+  FindSocketWithMem = FALSE;
+  //
+  // Allocate heap to save socket number with memory on it.
+  //
+  AllocHeapParams.RequestedBufferSize = sizeof (UINT8);
+  AllocHeapParams.BufferHandle = AMD_REC_MEM_SOCKET_HANDLE;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+    SocketWithMem = (UINT8 *) AllocHeapParams.BufferPtr;
+    *SocketWithMem = 0;
+
+    //
+    // Allocate heap for the table
+    //
+    MaxSockets = (UINT8) GetPlatformNumberOfSockets ();
+
+    AllocHeapParams.RequestedBufferSize = (MaxSockets * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL * sizeof (SPD_DEF_STRUCT));
+    AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
+      MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr;
+      //
+      // Initialize SpdParam Structure
+      //
+      LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader);
+      //
+      // Populate SPDDataBuffer
+      //
+
+      SpdParam.MemData = MemPtr;
+      for (Socket = 0; Socket < MaxSockets; Socket ++) {
+        SpdParam.SocketId = Socket;
+        for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
+          SpdParam.MemChannelId = Channel;
+          for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
+            SpdParam.DimmId = Dimm;
+            DimmSPDPtr = &(MemPtr->SpdDataStructure[(Socket * MAX_CHANNELS_PER_SOCKET + Channel) * MAX_DIMMS_PER_CHANNEL + Dimm]);
+            SpdParam.Buffer = DimmSPDPtr->Data;
+            AgesaStatus = AgesaReadSpdRecovery (0, &SpdParam);
+            if (AgesaStatus == AGESA_SUCCESS) {
+              DimmSPDPtr->DimmPresent = TRUE;
+              if (!FindSocketWithMem) {
+                FindSocketWithMem = TRUE;
+              }
+            } else {
+              DimmSPDPtr->DimmPresent = FALSE;
+            }
+          }
+        }
+        if (FindSocketWithMem) {
+          *SocketWithMem = Socket;
+          break;
+        }
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrport.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrport.h
new file mode 100755
index 0000000000..dd6b77e198
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrport.h
@@ -0,0 +1,85 @@
+/**
+ * @file
+ *
+ * mport.h
+ *
+ * API's to support different OS
+ *
+ * A detailed description, giving important information about this file.
+ * Omit the detailed description if none is needed.  For other than the
+ * simplest files, there should be one.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Memory
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ *===========================================================================
+ *  AMD Revision History
+ *  Initial Version
+ *
+ */
+#ifndef _MPORT_H_
+#define _MPORT_H_
+
+///< 64 bit data structure
+///< lo - Lower 32 bits
+///< hi - Upper 32 bits
+typedef struct _S_UINT64 {
+  UINT32 lo; ///< Lower 32 bits
+  UINT32 hi; ///< Upper 32 bits
+} S_UINT64;
+/*
+ *   SBDFO - Segment Bus Device Function Offset
+ *   31:28   Segment (4-bits)
+ *   27:20   Bus     (8-bits)
+ *   19:15   Device  (5-bits)
+ *   14:12   Function(3-bits)
+ *   11:00   Offset  (12-bits)
+ */
+typedef UINT32 SBDFO;
+
+//#define MAKE_SBDFO(seg,bus,dev,fun,off) ((((UINT32)(seg))<<28) | (((UINT32)(bus))<<20) | \
+//                   (((UINT32)(dev))<<15) | (((UINT32)(fun))<<12) | ((UINT32)(off)))
+//#define SBDFO_SEG(x) (((UINT32)(x)>>28) & 0x0F)
+//#define SBDFO_BUS(x) (((UINT32)(x)>>20) & 0xFF)
+//#define SBDFO_DEV(x) (((UINT32)(x)>>15) & 0x1F)
+//#define SBDFO_FUN(x) (((UINT32)(x)>>12) & 0x07)
+//#define SBDFO_OFF(x) (((UINT32)(x)) & 0xFFF)
+//#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+
+#define GET_SIZE_OF(x)   (sizeof (x) / sizeof (x[0]))
+
+#endif /* _MPORT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h
new file mode 100755
index 0000000000..588372a6ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mrt3.h
@@ -0,0 +1,119 @@
+/**
+ * @file
+ *
+ * mrt3.h
+ *
+ * Common Technology  Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 5655 $ @e \$Date: 2008-04-03 23:29:23 -0500 (Thu, 03 Apr 2008) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRT3_H_
+#define _MRT3_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+MemRecTTrainDQSWriteHw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTDramInitSw3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemRecTSetDramMode3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+BOOLEAN
+MemRecTDIMMPresence3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTEMRS13 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTEMRS23 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTEMRS33 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTMRS3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+VOID
+MemRecTDramControlRegInit3 (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+#endif  /* _MRT3_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
new file mode 100755
index 0000000000..725bd94261
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
@@ -0,0 +1,187 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+;  $Workfile:: mu.asm   $ $Revision:: 443#$  $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; Description: Main memory controller system configuration for AGESA DDR 2
+;
+;
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+;============================================================================
+
+
+    .XLIST
+    .LIST
+    .686p
+    .MODEL FLAT
+    .CODE
+     ASSUME FS: NOTHING
+
+
+; Define the calling convention used for the C library modules
+;@attention - This should be in a central include file
+CALLCONV    EQU     NEAR C
+
+
+;===============================================================================
+;MemRecUOutPort:
+;
+; Do a 32 Bit IO Out operation using edx.
+; NOTE: This function will be obsolete in the future.
+;
+;             In: Port - port number
+;                 Value - value to be written to port
+;
+;            Out:
+;
+;All registers preserved except for "Out:"
+;===============================================================================
+MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
+    pushad
+    mov edx,Port
+    mov eax,Value
+    out dx,al
+    popad
+    ret
+MemRecUOutPort ENDP
+
+
+
+;----------------------------------------------------------------------------
+; _MFENCE();
+;
+_MFENCE macro
+    db  0Fh,0AEh,0F0h
+    endm
+
+;----------------------------------------------------------------------------
+; _EXECFENCE();
+;
+_EXECFENCE macro
+    out 0EDh,al             ;prevent speculative execution of following instructions
+    endm
+
+;===============================================================================
+;MemRecUWrite1CL:
+;
+;   Write data from buffer to a system address
+;
+;             In: Address - System address to read from
+;                 Pattern - pointer pattern.
+;
+;            Out:
+;
+;All registers preserved except for "Out:"
+;===============================================================================
+MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
+        pushad
+        push ds
+
+        mov eax,Address
+        push ss
+        pop ds
+        xor edx,edx
+        mov edx, DWORD PTR Pattern
+        mov esi,edx
+        mov edx,16
+        _EXECFENCE
+        mov ecx,4
+        @@:
+        db 66h,0Fh,6Fh,06           ;MOVDQA xmm0,[esi]
+        db 64h,66h,0Fh,0E7h,00      ;MOVNTDQ fs:[eax],xmm0  (xmm0 is 128 bits)
+        add eax,edx
+        add esi,edx
+        loop @B
+
+        pop ds
+        popad
+        ret
+MemRecUWrite1CL ENDP
+
+;===============================================================================
+;MemRecURead1CL:
+;
+; Read one cacheline to buffer
+;
+;             In: Buffer - pointer buffer.
+;               : Address - System address to read from
+;
+;            Out:
+;
+;All registers preserved except for "Out:"
+;===============================================================================
+MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
+
+        pushad
+
+        mov esi,Address
+        xor edx,edx
+        mov edx,DWORD PTR Buffer
+        mov edi,edx
+        mov ecx,64
+        @@:
+        mov al,fs:[esi]
+        mov ss:[edi],al
+        inc esi
+        inc edi
+        loop @B
+
+        popad
+        ret
+MemRecURead1CL ENDP
+
+
+;===============================================================================
+;MemRecUFlushPattern:
+;
+; Flush one cache line
+;
+;             In:   Address - System address [31:0]
+;            Out:
+;
+;All registers preserved except for "Out:"
+;===============================================================================
+MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
+        pushad
+        mov eax,Address
+        _EXECFENCE
+                                        ;clflush fs:[eax]
+        db  064h                        ;access relative to FS BASE prefix
+        db  00Fh                        ;opcode
+        db  0AEh                        ;opcode
+        db  038h                        ;eax indirect addressing
+        _MFENCE
+        popad
+        ret
+MemRecUFlushPattern ENDP
+
+
+
+    END
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h
new file mode 100755
index 0000000000..b597fd75cb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.h
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * mru.h
+ *
+ * Utility support Recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+  * Copyright (c) 2011, Advanced Micro Devices, Inc.
+  * All rights reserved.
+  * 
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions are met:
+  *     * Redistributions of source code must retain the above copyright
+  *       notice, this list of conditions and the following disclaimer.
+  *     * Redistributions in binary form must reproduce the above copyright
+  *       notice, this list of conditions and the following disclaimer in the
+  *       documentation and/or other materials provided with the distribution.
+  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+  *       its contributors may be used to endorse or promote products derived 
+  *       from this software without specific prior written permission.
+  * 
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * 
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MRU_H_
+#define _MRU_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+  #define PSO_ENTRY UINT8
+#endif
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/// Test patterns for DQS training
+typedef enum {
+  TestPattern0,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern1,             ///< Test pattern used in first pass of receiver enable training
+  TestPattern2,             ///< Test pattern used in second pass of receiver enable training
+  TestPatternJD1B,          ///< 72-bit test pattern used in position training (ganged mode)
+  TestPatternJD1A,          ///< 72-bit test pattern used in position training
+  TestPatternML             ///< Test pattern used in first pass of max latency training
+} TRAIN_PATTERN;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+MemRecUWrite1CL (
+  IN       UINT32 Address,
+  IN       UINT8 Pattern[]
+  );
+
+VOID
+MemRecURead1CL (
+  IN       UINT8 Buffer[],
+  IN       UINT32 Address
+  );
+
+VOID
+MemRecUFlushPattern (
+  IN       UINT32 Address
+  );
+
+VOID
+MemRecUFillTrainPattern (
+  IN       TRAIN_PATTERN Pattern,
+  IN       UINT8 Buffer[],
+  IN       UINT16 Size,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+MemRecUProcIOClFlush (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+MemRecUWait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID *
+MemRecFindPSOverrideEntry (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       PSO_ENTRY EntryType,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  );
+
+#endif  /* _MRU_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
new file mode 100755
index 0000000000..d2fcaa0ece
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mruc.c
@@ -0,0 +1,262 @@
+/**
+ * @file
+ *
+ * mruc.c
+ *
+ * Utility functions recovery
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Proc/Recovery/Mem)
+ * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+#include "AGESA.h"
+#include "OptionMemory.h"
+#include "PlatformMemoryConfiguration.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "mrport.h"
+#include "mru.h"
+#include "Filecode.h"
+#define FILECODE PROC_RECOVERY_MEM_MRUC_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+MemRecUResetTargetWTIO (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+STATIC
+MemRecUSetTargetWTIO (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function returns the (Index)th UINT8
+ *   from an indicated test Pattern.
+ *
+ *     @param[in] Pattern - encoding of test Pattern type
+ *     @param[in] Buffer[] - buffer to be filled
+ *     @param[in] Size - Size of the bugger
+ *     @param[in] *StdHeader - pointer to AMD_CONFIG_PARAMS
+ *
+ */
+
+VOID
+MemRecUFillTrainPattern (
+  IN       TRAIN_PATTERN Pattern,
+  IN       UINT8 Buffer[],
+  IN       UINT16 Size,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  STATIC UINT8 PatternData[2] = {0x55, 0xAA};
+
+  LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function flushes cache lines
+ *
+ *     @param[in] Address - System Address [39:8]
+ *     @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT
+ *
+ */
+
+VOID
+MemRecUProcIOClFlush (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  MemRecUSetTargetWTIO (Address, MemPtr);
+  MemRecUFlushPattern (Address);
+  MemRecUResetTargetWTIO (MemPtr);
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      This function resets the target address space to Write Through IO by disabling IORRs
+ */
+
+VOID
+STATIC
+MemRecUResetTargetWTIO (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 Smsr;
+  Smsr.hi = 0;
+  Smsr.lo = 0;
+  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *       This function sets the target range to WT IO (using an IORR overlapping
+ *       the already existing
+ *      @param[in,out] *MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Address - System Address
+ *
+ */
+
+VOID
+STATIC
+MemRecUSetTargetWTIO (
+  IN       UINT32 Address,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  SMsr.lo = Address;
+  SMsr.hi = 0;
+  LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader);          // ;IORR0 Base
+  SMsr.hi = 0xFFFF;
+  SMsr.lo = 0xFC000800;
+  LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);          // ;64MB Mask
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  Waits specified number of 10ns cycles
+ *      @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
+ *      @param[in] Count - Number of 10ns cycles to wait
+ *
+ */
+
+VOID
+MemRecUWait10ns (
+  IN       UINT32 Count,
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  )
+{
+  S_UINT64 SMsr;
+
+  LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  Count += SMsr.lo;
+  while (SMsr.lo < Count) {
+    LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *      Find the entry of platform specific overriding table.
+ *
+ *      @param[in] PlatformMemoryConfiguration - Platform config table
+ *      @param[in] EntryType - Entry type
+ *      @param[in] SocketID - Physical socket ID
+ *      @param[in] ChannelID - Physical channel ID
+ *
+ *      @return  NULL - entry could not be found.
+ *      @return  Pointer - points to the entry's data.
+ *
+ * ----------------------------------------------------------------------------
+ */
+VOID *
+MemRecFindPSOverrideEntry (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN       PSO_ENTRY EntryType,
+  IN       UINT8 SocketID,
+  IN       UINT8 ChannelID
+  )
+{
+  UINT8 *Buffer;
+
+  Buffer = PlatformMemoryConfiguration;
+  while (Buffer[0] != PSO_END) {
+    if (Buffer[0] == EntryType) {
+      if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) {
+        if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) {
+          ASSERT ((Buffer[0] == PSO_MAX_DIMMS) ? (Buffer[4] <= MAX_DIMMS_PER_CHANNEL) : TRUE);
+          ASSERT ((Buffer[0] == PSO_MAX_CHIPSELS) ? (Buffer[4] <= MAX_CS_PER_CHANNEL) : TRUE);
+          ASSERT ((Buffer[0] == PSO_MAX_CHNLS) ? (Buffer[4] <= MAX_CHANNELS_PER_SOCKET) : TRUE);
+          return &Buffer[4];
+        }
+      }
+    }
+    Buffer += Buffer[1] + 2;
+  }
+  return NULL;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Recovery/recoveryPage.h b/src/vendorcode/amd/agesa/f10/Proc/Recovery/recoveryPage.h
new file mode 100755
index 0000000000..1d4550f570
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/Recovery/recoveryPage.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * Create outline and references for Recovery Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page recoverymain Recovery Component Documentation
+ *
+ * Additional documentation for the Recovery component consists of
+ *
+ * - Maintenance Guides:
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/cpcar.inc b/src/vendorcode/amd/agesa/f10/cpcar.inc
new file mode 100755
index 0000000000..1a692c4475
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/cpcar.inc
@@ -0,0 +1,477 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+; $Workfile:: cpcar.inc
+;
+; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File
+;
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+CORE0_STACK_BASE_ADDR   EQU 40000h    ;base address for primary cores stack
+CORE1_STACK_BASE_ADDR   EQU 60000h    ;base address for AP cores
+CORE0_STACK_SIZE        EQU 4000h     ;16KB for primary cores
+CORE1_STACK_SIZE        EQU 1000h     ;4KB for each AP cores
+
+AMD_MTRR_FIX64k_00000    EQU 250h
+AMD_MTRR_FIX16k_80000    EQU 258h
+AMD_MTRR_FIX16k_A0000    EQU 259h
+AMD_MTRR_FIX4k_C0000     EQU 268h
+AMD_MTRR_FIX4k_C8000     EQU 269h
+AMD_MTRR_FIX4k_D0000     EQU 26Ah
+AMD_MTRR_FIX4k_D8000     EQU 26Bh
+AMD_MTRR_FIX4k_E0000     EQU 26Ch
+AMD_MTRR_FIX4k_E8000     EQU 26Dh
+AMD_MTRR_FIX4k_F0000     EQU 26Eh
+AMD_MTRR_FIX4k_F8000     EQU 26Fh
+AMD_MTRR_DEFTYPE        EQU 2FFh
+
+AMD_MTRR_VARIABLE_BASE6 EQU 020Ch
+
+TOP_MEM                 EQU 0C001001Ah
+
+MtrrFixDramEn      EQU 18
+MtrrFixDramModEn   EQU 19
+MtrrVarDramEn      EQU 20
+
+WB_DRAM_TYPE       EQU 1Eh
+
+HWCR                   EQU 0C0010015h
+    INVD_WBINVD        EQU 4
+
+LS_CFG                 EQU 0C0011020h
+    DisStreamSt        EQU 28
+
+IC_CFG                 EQU 0C0011021h
+    DIS_SPEC_TLB_RLD   EQU 9
+    DIS_IND            EQU 14
+
+BU_CFG2                EQU 0C001102Ah
+    ClLinesToNbDis     EQU 15
+
+DC_DIS_SPEC_TLB_RLD    EQU  4       ; disable speculative TLB reloads
+DIS_CLR_WBTOL2_SMC_HIT EQU  8       ; self modifying code check buffer bit
+DIS_HW_PF              EQU 13       ; hardware prefetches bit
+IC_DIS_SPEC_TLB_RLD    EQU  9       ; disable speculative TLB reloads
+
+CR0_CD    EQU 40000000h      ; CR0[30] = Cache Disable
+CR0_NW    EQU 20000000h      ; CR0[29] = Not Writethrough
+
+; CPUID Functions
+
+CPUID_MODEL             EQU     1
+AMD_CPUID_FMF           EQU     80000001h   ; Family Model Features information
+
+NB_CFG                  EQU     0C001001Fh
+    bEnableCF8ExtCfg    EQU     00004000h   ; [46]
+    bInitAPICCPUIDLo    EQU     00400000h   ; [54]
+
+MTRR_SYS_CFG        EQU 0C0010010h
+  ChxToDirtyDis     EQU 16
+  SysUcLockEn       EQU 17
+  MtrrFixDramEn     EQU 18
+  MtrrFixDramModEn  EQU 19
+  MtrrVarDramEn     EQU 20
+  MtrrTom2En        EQU 21
+
+PERF_COUNTER3            EQU 0C0010007h ; Performance event counter three
+PERF_CONTROL3            EQU 0C0010003h ; Performance event control three
+PERF_CONTROL3_RESERVE_L  EQU 00200000h  ; Preserve the reserved bits
+PERF_CONTROL3_RESERVE_H  EQU 0FCF0h     ; Preserve the reserved bits
+CONFIG_EVENT_L           EQU 0F0E2h     ; All cores with level detection
+CONFIG_EVENT_H           EQU 4          ; Increment count by number of event
+                                        ; occured in clock cycle
+EVENT_ENABLE             EQU 22         ; Enable the event
+
+;;***************************************************************************
+;;
+;;                      CPU MACROS - PUBLIC
+;;
+;;***************************************************************************
+_WRMSR macro
+  db  0Fh, 30h
+  endm
+_RDMSR macro
+  db  0Fh, 32h
+  endm
+
+;----------------------------------------------
+;
+; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
+;
+;----------------------------------------------
+AMD_DISABLE_STACK_FAMILY_HOOK MACRO
+
+    AMD_DISABLE_STACK_FAMILY_HOOK_F10
+    AMD_DISABLE_STACK_FAMILY_HOOK_F14
+
+ENDM
+
+AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO
+
+    local   cl_line_to_nb_enable_exit
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 01h            ; Is this family 10h?
+    jnz     cl_line_to_nb_enable_exit ; Br if no
+
+    ; For Family 10h, clear BU_CFG2[15] ClLinesToNbDis bit to Re-Enable L3 cache
+    ; Warning: icache for ROM (IO space) is disabled
+    mov     ecx, 0C001102Ah             ; BU_CFG2
+    _RDMSR
+    btr     eax, 15
+    btr     edx, 3
+    _WRMSR
+
+    ; * MSRC001_1021[DIS_IND]=0. Disable indirect branch predictor.
+    mov     ecx, IC_CFG         ; IC_CFG
+    _RDMSR
+    btr     eax, DIS_IND        ; turn off Disable indirect branch predictor
+    _WRMSR
+
+    ;--------------------------------------------------------------------------
+    ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    ;--------------------------------------------------------------------------
+
+    ; Disable INVD_WBINVD across the invd instruction.
+    mov     cx, 0015h           ; HWCR
+    _RDMSR
+    mov     bx, ax              ; save INVD -> WBINVD bit
+    and     al, 0EFh            ; disable INVD -> WBINVD conversion
+    _WRMSR
+
+    invd                        ; Clear the cache tag RAMs
+
+    ; Restore INVD_WBINVD
+    mov     ax, bx              ; restore INVD -> WBINVD bit
+    _WRMSR
+
+    ;--------------------------------------------------------------------------
+    ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    ;--------------------------------------------------------------------------
+
+    mov ecx, PERF_CONTROL3        ; Select the event control three
+    _RDMSR                        ; Retrieve the current value
+    btc eax, EVENT_ENABLE         ; Is event enable, complement it as well
+    jnc cl_line_to_nb_enable_exit ; No
+    cmp ax, CONFIG_EVENT_L        ; Is the lower part of event set to capture the CAR Corruption
+    jne cl_line_to_nb_enable_exit ; No
+    cmp  dl,  CONFIG_EVENT_H      ; Is the upper part of event set to capture the CAR Corruption
+    jne cl_line_to_nb_enable_exit ; No
+    _WRMSR                        ; Disable the event
+
+cl_line_to_nb_enable_exit:
+ENDM
+
+AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO
+
+    local   fam14_enable_stack_hook_exit
+
+    ;
+    ; For Family 14h
+    ;
+    ; Restore the following configuration state:
+    ; * MSRC001_0015[INVD_WBINVD]=1.
+    ; * MSRC001_1020[DisStreamSt]=0.
+    ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.
+    ; * MSRC001_1022[DIS_HW_PF]=0.
+    ;
+    ; When BIOS is done executing from WP-IO the following steps are followed:
+    ; * MSRC001_102A[ClLinesToNbDis]=1.
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 05h            ; Is this family 10h?
+    jnz     fam14_enable_stack_hook_exit ; Br if no
+
+    ; * MSRC001_0015[INVD_WBINVD]=0.
+    mov     ecx, HWCR
+    _RDMSR
+    bts     eax, INVD_WBINVD            ; turn off Convert INVD to WBINVD bit
+    _WRMSR
+    ; * MSRC001_1020[DisStreamSt]=1.
+    mov     ecx, LS_CFG
+    _RDMSR
+    btr     eax, DisStreamSt            ; turn on Streaming store functionality disabled bit
+    _WRMSR
+    ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
+    inc     ecx                         ; mov     ecx, IC_CFG
+    _RDMSR
+    btr     eax, DIS_SPEC_TLB_RLD       ; turn on Disable speculative TLB reloads bit
+    _WRMSR
+    ; * MSRC001_1022[DIS_HW_PF]=1.
+    inc     ecx
+    _RDMSR
+    btr     eax, DIS_HW_PF              ; turn on Disable hardware prefetches bit
+    _WRMSR
+
+fam14_enable_stack_hook_exit:
+ENDM
+
+;---------------------------------------------------
+;
+; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
+;
+;---------------------------------------------------
+AMD_ENABLE_STACK_FAMILY_HOOK MACRO
+
+    AMD_ENABLE_STACK_FAMILY_HOOK_F10
+    AMD_ENABLE_STACK_FAMILY_HOOK_F14
+
+ENDM
+
+AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO
+
+    local   cl_line_to_nb_disable_exit
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 01h            ; Is this family 10h?
+    jnz     cl_line_to_nb_disable_exit ; Br if no
+
+    ; For Family 10h, set BU_CFG2[15] ClLinesToNbDis bit to disable L3 cache
+    ; Allow BIOS ROM to be cached in the IC
+    mov     ecx, 0C001102Ah         ; BU_CFG2
+    _RDMSR
+    bts     eax, 15
+    bts     edx, 3
+    _WRMSR
+
+    mov     cx, 0015h           ; HWCR
+    _RDMSR
+    and     al, 0EFh            ; disable INVD -> WBINVD conversion
+    _WRMSR
+
+    ; * MSRC001_1021[DIS_IND]=1. Disable indirect branch predictor.
+    mov     ecx, IC_CFG         ; IC_CFG
+    _RDMSR
+    bts     eax, DIS_IND        ; turn on Disable indirect branch predictor
+    _WRMSR
+
+    .if (di == 0)    ;core 0
+       mov ecx, PERF_COUNTER3            ; Select performance counter three
+                                         ; to count number of CAR Corruption
+       xor eax, eax                      ; Initialize the lower part of the counter to zero
+       xor edx, edx                      ; Initializa the upper part of the counter to zero
+       _WRMSR                            ; Save it
+       mov ecx, PERF_CONTROL3            ; Select the event control three
+       _RDMSR                            ; Get the current setting
+       and eax, PERF_CONTROL3_RESERVE_L  ; Preserve the reserved bits
+       or eax, CONFIG_EVENT_L            ; Set the lower part of event register to
+                                         ; select CAR Corruption occurred by any cores
+       and dx, PERF_CONTROL3_RESERVE_H   ; Preserve the reserved bits
+       or  dx, CONFIG_EVENT_H            ; Set the upper part of event register
+       _WRMSR                            ; Save it
+       bts eax, EVENT_ENABLE             ; Enable it
+       _WRMSR                            ; Save it
+    .endif
+
+cl_line_to_nb_disable_exit:
+ENDM
+
+AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO
+
+    local   fam14_enable_stack_hook_exit
+
+    ;
+    ; For Family 14h
+    ;
+    ; The following requirements must be satisfied prior to using the cache as general storage:
+    ; * Paging must be disabled.
+    ; * MSRC001_0015[INVD_WBINVD]=0.
+    ; * MSRC001_1020[DisStreamSt]=1.
+    ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
+    ; * MSRC001_1022[DIS_HW_PF]=1.
+    ; * MSRC001_102A[ClLinesToNbDis]=1.
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 05h            ; Is this family 10h?
+    jnz     fam14_enable_stack_hook_exit ; Br if no
+
+    ; * MSRC001_0015[INVD_WBINVD]=0.
+    mov     ecx, HWCR
+    _RDMSR
+    btr     eax, INVD_WBINVD            ; turn off Convert INVD to WBINVD bit
+    _WRMSR
+    ; * MSRC001_1020[DisStreamSt]=1.
+    mov     ecx, LS_CFG
+    _RDMSR
+    bts     eax, DisStreamSt            ; turn on Streaming store functionality disabled bit
+    _WRMSR
+    ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
+    inc     ecx                         ; mov     ecx, IC_CFG
+    _RDMSR
+    bts     eax, DIS_SPEC_TLB_RLD       ; turn on Disable speculative TLB reloads bit
+    _WRMSR
+    ; * MSRC001_1022[DIS_HW_PF]=1.
+    inc     ecx
+    _RDMSR
+    bts     eax, DIS_HW_PF              ; turn on Disable hardware prefetches bit
+    _WRMSR
+    ; * MSRC001_102A[ClLinesToNbDis]=1.
+    mov     ecx, BU_CFG2
+    _RDMSR
+    bts     eax, ClLinesToNbDis         ; turn on DC and IC caches WT/WP-IO, but L2 does not.
+    _WRMSR
+
+fam14_enable_stack_hook_exit:
+ENDM
+
+;---------------------------------------------------
+;
+; GET_NODE_ID_CORE_ID Macro - Stackless
+;
+; Macro returns:
+;  SI= NODE ID
+;  DI= CORE ID
+;---------------------------------------------------
+GET_NODE_ID_CORE_ID MACRO
+
+    GET_NODE_ID_CORE_ID_F10
+    GET_NODE_ID_CORE_ID_F12
+    GET_NODE_ID_CORE_ID_F14
+
+ENDM
+
+GET_NODE_ID_CORE_ID_F10 MACRO
+
+    local   node_core_f10_exit
+
+    cmp     si, -1             ; Has node/core already been discovered?
+    jnz     node_core_f10_exit ; Br if yes
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 01h            ; Is this family 10h?
+    jnz     node_core_f10_exit ; Br if no
+
+    mov     ecx, 1Bh           ; APIC Base MSR
+    _RDMSR
+    xor     si, si             ; Assume BSC
+    xor     di, di
+    test    ah, 1              ; Is this the BSC?
+    jnz     node_core_f10_exit ; Br if yes
+    mov     ecx, 0C0000408h    ; Read the family 10h mailbox
+    _RDMSR
+    mov     si, dx             ; SI = raw mailbox contents
+    shr     ebx, 24            ; BL = Initial APIC ID
+    mov     di, bx             ; DI = Initial APIC ID
+
+    AMD_CPUID   80000008h
+    shr     ch, 4              ; CH = ApicIdSize
+    inc     cl                 ; CL = Number of enabled cores in the socket
+    mov     bx, cx
+
+    mov     ecx, NB_CFG
+    _RDMSR                     ; EDX bit 54-32=26 is InitApicIdCpuIdLo bit
+
+    mov     cl, bh             ; CL = APIC ID size
+    mov     al, 1              ; Convert APIC ID size to an AND mask
+    shl     al, cl             ; AL = 2^APIC ID size
+    dec     al                 ; AL = mask for relative core number
+    xor     ah, ah             ; AX = mask for relative core number
+    bt      edx, 54-32         ; InitApicId == 1?
+    .if (!carry?)              ; Br if yes
+        mov     ch, 8          ; Calculate core number shift count
+        sub     ch, cl         ; CH = core shift count
+        mov     cl, ch
+        shr     di, cl         ; Right justify core number
+    .endif
+    and     di, ax             ; DI = socket-relative core number
+
+    mov     cx, si             ; CX = raw mailbox value
+    shr     cx, 10             ; CL[1:0] = ModuleType
+    and     cl, 3              ; Isolate ModuleType
+    xor     bh, bh             ; BX = Number of enabled cores in the socket
+    shr     bx, cl             ; BX = Number of enabled cores per node
+    xor     dx, dx             ; Clear upper word for div
+    mov     ax, di             ; AX = socket-relative core number
+    div     bx                 ; DX = node-relative core number
+    mov     di, dx             ; DI = node-relative core number
+    and     si, 000Fh          ; SI = node number
+node_core_f10_exit:
+ENDM
+
+GET_NODE_ID_CORE_ID_F12 MACRO
+
+    local   node_core_f12_exit
+
+    cmp     si, -1             ; Has node/core already been discovered?
+    jnz     node_core_f12_exit ; Br if yes
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 03h            ; Is this family 10h?
+    jnz     node_core_f12_exit ; Br if no
+
+    xor     si, si             ; Node must be 0
+    shr     ebx, 24            ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
+    mov     di, bx             ; DI = core number
+node_core_f12_exit:
+ENDM
+
+GET_NODE_ID_CORE_ID_F14 MACRO
+
+    local   node_core_f14_exit
+
+    cmp     si, -1             ; Has node/core already been discovered?
+    jnz     node_core_f14_exit ; Br if yes
+
+    AMD_CPUID   CPUID_MODEL
+    shr     eax, 20            ; AL = cpu extended family
+    cmp     al, 05h            ; Is this family 14h?
+    jnz     node_core_f14_exit ; Br if no
+
+    xor     si, si             ; Node must be 0
+    mov     ecx, 1Bh           ; APIC Base MSR
+    _RDMSR
+    xor     di, di             ; Assume BSC
+    test    ah, 1              ; Is this the BSC?
+    jnz     node_core_f14_exit ; Br if yes
+    inc     di                 ; Set core to 1
+node_core_f14_exit:
+ENDM
+
+
+AMD_CPUID MACRO arg0
+  IFB <arg0>
+    mov   eax, 1
+    db    0Fh, 0A2h   ; Execute instruction
+    bswap eax
+    xchg  al, ah      ; Ext model in al now
+    rol   eax, 8      ; Ext model in ah, model in al
+    and   ax, 0FFCFh  ; Keep 23:16, 7:6, 3:0
+  ELSE
+    mov   eax, arg0
+    db    0Fh, 0A2h
+  ENDIF
+ENDM
+
diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc
new file mode 100755
index 0000000000..f7119d1cf3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/cpcarmac.inc
@@ -0,0 +1,406 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+;  Workfile: cpcarmac.inc    $Revision:: 44323   $    $Date:: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+;
+; Description: Code to setup and break down cache-as-stack
+;
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    INCLUDE cpcar.inc
+    .LIST
+    .586P
+
+;======================================================================
+; AMD_ENABLE_STACK:  Setup a stack
+;
+;   In:
+;       none
+;
+;   Out:
+;       SS:ESP - Our new private stack location
+;       4000:3FFC   - for BSP (16K Stack)
+;       4000:7FFC   - for core0 of node1 (16K Stack)
+;       4000:BFFC   - for core0 of node2 (16K Stack)
+;       4000:FFFC   - for core0 of node3 (16K Stack)
+;       5000:3FFC   - for core0 of node4 (16K Stack)
+;       5000:7FFC   - for core0 of node5 (16K Stack)
+;       5000:BFFC   - for core0 of node6 (16K Stack)
+;       5000:FFFC   - for core0 of node7 (16K Stack)
+;
+;       6000:1FFC   - for core1 node0 (4k stack)
+;       6000:2FFC   - for core2 node0 (4k stack)
+;       ...
+;       9000:8FFC   - for core7 of node7 (4k stack)  ......... max of 64 cores in system
+;
+;       EAX = AGESA_STATUS
+;
+;       ECX = Stack size in bytes
+;
+;   Requirements:
+;       * This routine presently is limited to a max of 64 processors
+;
+;   Preserved:
+;       ebx
+;   Destroyed:
+;       eax, ecx, edx, edi, esi, ds, es
+;
+;======================================================================
+AMD_ENABLE_STACK MACRO
+
+    local   SetupStack
+    local   SetupDramMap
+    local   get_SS_ESP
+    local   r16bmode
+    local   p32mode
+    local   init_stack
+
+;   Note that SS:ESP will be default stack.  Note that this stack
+;   routine will not be used after memory has been initialized.  Because
+;   of its limited lifetime, it will not conflict with typical PCI devices.
+
+    mov     esp, ebx                    ; put return address in a safe place
+
+    ; get node id and core id of current executing core
+    mov si, -1
+    GET_NODE_ID_CORE_ID
+    movzx   edi, di
+
+    ; determine if stack is already enabled.
+    mov     eax, cr0
+    test    eax, 60000000h
+    jnz     SetupStack
+    mov     ecx, AMD_MTRR_DEFTYPE
+    _RDMSR
+    test    ah, 0Ch
+    jz      SetupStack
+    or      edi, 0FFFF0000h             ; indicate stack has already been initialized
+    jmp     get_SS_ESP
+
+SetupStack:
+    ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
+    mov     eax, 8000C06Ch
+    mov     dx, 0CF8h
+    out     dx, eax
+    add     dx, 4
+    in      eax, dx
+    btr     eax, 0
+    out     dx, eax
+
+    ; Setup temporary DRAM map for CAS on all nodes
+    mov     eax, 8000C060h              ; Get NodeCnt from BSP
+    mov     dx, 0CF8h
+    out     dx, eax
+    add     dx, 4
+    in      al, dx
+    shr     ax, 4
+    and     al, 7
+    mov     cl, al
+
+    mov     ebx, 8000C144h
+SetupDramMap:
+    mov     eax, ebx                    ; Set 0000_0000 to 00FF_FFFF as DRAM
+    mov     dx, 0CF8h
+    out     dx, eax
+    add     dx, 4
+    mov     eax, 0
+    out     dx, eax
+
+    mov     eax, ebx
+    sub     eax, 4
+    mov     dx, 0CF8h
+    out     dx, eax
+    add     dx, 4
+    mov     eax, 3
+    out     dx, eax
+
+    add     bh, 8
+    dec     cl
+    jns     SetupDramMap
+
+    ; Disable the self modifying code check buffer and Disable hardware prefetches
+    mov     ecx, 0C0011022h
+    _RDMSR
+    bts     eax, DC_DIS_SPEC_TLB_RLD    ; turn on Disable speculative TLB reloads bit
+    bts     eax, DIS_CLR_WBTOL2_SMC_HIT ; turn on Disable the self modifying code check buffer bit
+    bts     eax, DIS_HW_PF              ; turn on Disable hardware prefetches bit
+    _WRMSR
+    dec     cx                          ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
+    _RDMSR
+    bts     eax, IC_DIS_SPEC_TLB_RLD    ; turn on Disable speculative TLB reloads bit
+    _WRMSR
+
+    AMD_ENABLE_STACK_FAMILY_HOOK        ; Disable L3 cache to accept clear lines
+
+    ; Init CPU MSRs for our init routines
+    mov     ecx, MTRR_SYS_CFG           ; SYS_CFG
+    _RDMSR
+    and     eax, 0FFE3FFFFh             ; turn off MTRR enable bits
+    bts     eax, MtrrFixDramModEn       ; turn on modification enable bit
+    _WRMSR
+
+    ; clear all variable and Fixed MTRRs
+    mov     ecx, 200h
+    xor     eax, eax
+    xor     edx, edx
+    .while (cl != 10h)                  ; MTRRphysBasen and MTRRphysMaskn
+        _WRMSR
+        inc     cl
+    .endw
+    mov     cl, 50h                     ; MTRRfix64K_00000
+    _WRMSR
+    mov     cl, 58h                     ; MTRRfix16K_80000
+    _WRMSR
+    mov     cl, 59h                     ; MTRRfix16K_A0000
+    _WRMSR
+    mov     cl, 68h                     ; MTRRfix4K_C0000 to MTRRfix4K_F8000
+    .while (cl != 70h)
+        _WRMSR
+        inc     cl
+    .endw
+
+    ; setup MTTR for stacks
+    mov ebx, WB_DRAM_TYPE
+    .if (di == 0)    ;core 0
+        .if (si > 3)    ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h
+            shl ebx, 8
+        .endif
+        mov ecx, AMD_MTRR_FIX64k_00000
+        _RDMSR
+        or edx, ebx
+        _WRMSR
+    .else    ;core 1 to core 7 start at 60000h
+        .if (si < 4)    ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTTR
+            shl ebx, 16
+            .if (si > 1)
+                shl ebx, 8
+            .endif
+            mov ecx, AMD_MTRR_FIX64k_00000
+            _RDMSR
+            or edx, ebx
+            _WRMSR
+        .else           ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTTR
+            mov ecx, AMD_MTRR_FIX16k_80000
+            _RDMSR
+            .if (si < 6)   ; node 4 and node 5
+                .if (si == 4)     ; node 4
+                    .if (di >= 4)
+                        shl ebx, 8
+                    .endif
+                .else             ; node 5
+                    shl ebx, 16
+                    .if (di >= 4)
+                        shl ebx, 8
+                    .endif
+                .endif
+                or eax, ebx
+                _WRMSR
+            .else          ; node 6 and node 7
+                .if (si == 6)     ; node 6
+                    .if (di >= 4)
+                        shl ebx, 8
+                    .endif
+                .else             ; node 7
+                    shl ebx, 16
+                    .if (di >= 4)
+                        shl ebx, 8
+                    .endif
+                .endif
+                or edx, ebx
+                _WRMSR
+            .endif
+        .endif
+    .endif
+
+    ; Clear IORRs, TOP_MEM and TOM2
+    xor     eax, eax
+    xor     edx, edx
+
+    mov     ecx, 0C0010016h             ;IORRBase0
+    .while (cl != 1Bh)
+        _WRMSR
+        inc     cl
+    .endw
+    mov     cl, 1Dh
+    _WRMSR
+
+    ; Enable MTRRs
+    mov     ecx, 02FFh                  ; MTRRdefType
+    mov     ah, 0Ch                     ; MtrrDefTypeEn and MtrrDefTypeFixEn
+    _WRMSR
+
+    mov     ecx, MTRR_SYS_CFG           ; SYS_CFG
+    _RDMSR
+    bts     eax, MtrrFixDramEn          ; MtrrFixDramEn
+    btr     eax, MtrrFixDramModEn       ; turn off modification enable bit
+    _WRMSR
+
+    ; Enable caching in CR0
+    mov     eax, CR0                    ; Enable WT/WB cache
+    btr     eax, 31                     ; make sure paging is disabled
+    btr     eax, 30                     ; Clear CR0 NW and CD
+    btr     eax, 29
+    mov     CR0, eax
+
+get_SS_ESP:
+    ; allocate space for stacks
+    xor cx, cx
+    xor edx, edx
+    .if (di == 0)    ;core 0
+        mov eax, CORE0_STACK_BASE_ADDR
+        .while (cx <= si)
+            add eax, 4000h
+            inc cx
+        .endw
+        mov edx, eax
+        sub eax, 4000h
+        and eax, 0F0000h
+        sub edx, 4
+        and edx, 0FFFFh
+        mov bx, CORE0_STACK_SIZE / 4
+    .else    ;core 1 to core 7 start at 60000h
+        mov eax, CORE1_STACK_BASE_ADDR        ; core 1 stack starts at 60000h
+        .while (cx <= si)
+            add eax, 8000h       ; 32k for each node
+            inc cx
+        .endw
+        sub eax, 8000h
+        mov dx, ax
+        and eax, 0F0000h
+        xor cx, cx
+        .while (cx <= di)
+            add edx, 1000h      ; 4k for APs
+            inc cx
+        .endw
+        sub edx, 4
+        mov bx, CORE1_STACK_SIZE / 4
+    .endif
+
+    ; Allocate stack and set ESP
+    mov     ecx, CR0                 ; check for 32-bit protect mode
+    test    ecx, 1                   ; PE bit
+    jz      r16bmode                 ; PE=0, real mode
+    mov     cx, cs                   ; PE=1
+    cmp     cx, 0D000h               ; check for CS
+    jb      p32mode                  ; if CS < D000, it is a selector instead of a segment
+r16bmode:
+    shr     eax, 4                   ; ax = ss, ds, es
+    mov     ss, ax
+    mov     ds, ax
+    mov     es, ax
+    jmp     init_stack
+p32mode:
+    add     edx, eax                 ; linear address of the stack
+init_stack:
+
+    .if ( !(edi & 0FFFF0000h))
+        std
+        xor ecx, ecx
+        mov cx, bx
+        mov esi, edx
+        rep lods DWORD PTR [esi]
+        xor eax, eax
+        mov cx, bx
+        mov edi, edx
+        rep stos DWORD PTR [edi]
+        cld
+        xor eax, eax  ; eax = 0 : no error
+    .else
+        mov eax, 40000001h  ; eax = AGESA_WARNING (Stack has already been set up)
+    .endif
+
+        mov cx, bx    ; ecx = size in dwords
+        shl ecx, 2    ; ecx = size in bytes
+
+    mov     ebx, esp
+    mov     esp, edx
+
+
+ENDM
+
+;======================================================================
+; AMD_DISABLE_STACK:  Destroy the stack inside the cache. This routine
+;                     should only be executed on the BSP
+;
+;   In:
+;       none
+;
+;   Out:
+;       EAX = AGESA_STATUS
+;
+;   Preserved:
+;       ebx
+;   Destroyed:
+;       eax, ecx, edx, esp
+;======================================================================
+AMD_DISABLE_STACK MACRO
+
+    mov     esp, ebx            ; save return address
+
+    ; Turn on modification enable bit
+    mov ecx, MTRR_SYS_CFG
+    _RDMSR
+    bts eax, MtrrFixDramModEn ; Enable
+    _WRMSR
+
+    ; Disable MTRRs and turn on modification enable bit
+    mov ecx,AMD_MTRR_FIX64k_00000
+    mov eax,1E1E1E1Eh
+    mov edx,eax
+    _WRMSR                          ; 0 - 512K = WB Mem
+    mov cl,58h
+    _WRMSR                          ; 512K - 640K = WB Mem
+
+    ; Turn off modification enable bit
+    mov ecx, MTRR_SYS_CFG
+    _RDMSR
+    btr eax, MtrrFixDramModEn ; Disable
+    _WRMSR
+
+    ; Enable the self modifying code check buffer and Enable hardware prefetches
+    mov     ecx, 0C0011022h
+    _RDMSR
+    btr     eax, DC_DIS_SPEC_TLB_RLD    ; Disable speculative TLB reloads bit
+    btr     eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable the self modifying code check buffer bit
+    btr     eax, DIS_HW_PF              ; Disable hardware prefetches bit
+    _WRMSR
+
+    dec     cx                          ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
+    _RDMSR
+    btr     eax, IC_DIS_SPEC_TLB_RLD    ; turn on Disable speculative TLB reloads bit
+    _WRMSR
+
+    AMD_DISABLE_STACK_FAMILY_HOOK   ; Re-Enable L3 cache to accept clear lines
+
+    mov     ebx, esp
+    xor     eax, eax
+
+ENDM
diff --git a/src/vendorcode/amd/agesa/f10/errno.h b/src/vendorcode/amd/agesa/f10/errno.h
new file mode 100755
index 0000000000..40cf072cb5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/errno.h
@@ -0,0 +1,38 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+// this dummy errno.h prevents an agesa  build failure when the gcc
+// cross compiler target is i386-elf. In this case, mm_malloc.h
+// includes errno.h, but the gcc cross compiler does not supply it.
+
+extern int errno;
+#define EINVAL 1
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
new file mode 100755
index 0000000000..a24c0b7abe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -0,0 +1,1612 @@
+/*
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/******************************************************************************
+* AMD Generic Encapsulated Software Architecture
+*
+* $Workfile:: GccCar.inc    $Revision:: 32932   $
+*
+* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier
+*
+******************************************************************************/
+
+.altmacro
+
+BSP_STACK_BASE_ADDR     =       0x30000         /* Base address for primary cores stack   */                             
+BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core                      */                                               
+CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */                             
+CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */                                          
+CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */                                           
+CORE1_STACK_SIZE        =       0x1000          /* 4KB for each AP cores                  */                                               
+                                                                                                             
+APIC_BASE_ADDRESS       =       0x0000001B                                                                       
+  APIC_BSC              =       8               /* Boot Strap Core  */                                                  
+                                                                                                             
+AMD_MTRR_VARIABLE_BASE0  =      0x0200                                                                          
+AMD_MTRR_VARIABLE_BASE6  =      0x020C                                                                          
+AMD_MTRR_FIX64k_00000    =      0x0250                                                                          
+AMD_MTRR_FIX16k_80000    =      0x0258                                                                          
+AMD_MTRR_FIX16k_A0000    =      0x0259                                                                          
+AMD_MTRR_FIX4k_C0000     =      0x0268                                                                          
+AMD_MTRR_FIX4k_C8000     =      0x0269                                                                          
+AMD_MTRR_FIX4k_D0000     =      0x026A                                                                          
+AMD_MTRR_FIX4k_D8000     =      0x026B                                                                          
+AMD_MTRR_FIX4k_E0000     =      0x026C                                                                          
+AMD_MTRR_FIX4k_E8000     =      0x026D                                                                          
+AMD_MTRR_FIX4k_F0000     =      0x026E                                                                          
+AMD_MTRR_FIX4k_F8000     =      0x026F                                                                          
+                                                                                                             
+AMD_MTRR_DEFTYPE         =      0x02FF                                                                            
+    WB_DRAM_TYPE         =      0x1E             /* MemType - memory type */                                           
+    MTRR_DEF_TYPE_EN     =      11               /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */          
+    MTRR_DEF_TYPE_FIX_EN =      10               /* MtrrDefTypeEn - fixed MTRRs default enabled */                        
+                                                                                                             
+HWCR                     =      0x0C0010015      /* Hardware Configuration                                                                                                                                       */                                             
+    INVD_WBINVD          =      0x04             /* INVD to WBINVD conversion */                                         
+                                                                                                             
+IORR_BASE                =      0x0C0010016      /* IO Range Regusters Base/Mask, 2 pairs */                              
+                                                 /*  uses 16h - 19h                                                                                                                                                             */                                                   
+TOP_MEM                  =      0x0C001001A      /* Top of Memory                                                                                                                                                                                */                                                      
+TOP_MEM2                 =      0x0C001001D      /* Top of Memory2                                                                                                                                                                       */                                                    
+                                                                                                             
+LS_CFG                   =      0x0C0011020      /* Load-Store Configuration                                                                                                                             */                                           
+    DIS_SS               =     28                /* Family 10h,12h,15h:Disable Streng Store functionality */         
+    DIS_STREAM_ST        =     28                /* Family 14h:DisStreamSt - Disable Streaming Store functionality */   
+                                                                                                             
+IC_CFG                   =      0x0C0011021      /* Instruction Cache Config Register  */                                 
+    IC_DIS_SPEC_TLB_RLD  =      9                /*   Disable speculative TLB reloads  */                                 
+    DIS_IND              =      14               /*   Family 10-14h:Disable Indirect Branch Predictor */                  
+    DIS_I_CACHE          =      14               /*   Family 15h:DisICache - Disable Indirect Branch Predictor */         
+                                                                                                             
+DC_CFG                   =      0x0C0011022      /* Data Cache Configuration                                                                                                                                   */                                           
+    DC_DIS_SPEC_TLB_RLD      =  4                /*   Disable speculative TLB reloads */                                  
+    DIS_CLR_WBTOL2_SMC_HIT   =  8                /*   self modifying code check buffer bit */                              
+    DIS_HW_PF                =  13               /*   Hardware prefetches bit                                                                                                                                    */                                          
+                                                                                                             
+DE_CFG                   =      0x0C0011029      /* Decode Configuration */                                               
+    CL_FLUSH_SERIALIZE   =      23               /*   Family 12h,15h: CL Flush Serialization */                           
+                                                                                                             
+BU_CFG2                  =      0x0C001102A      /* Family 10h: Bus Unit Configuration 2 */                           
+CU_CFG2                  =      0x0C001102A      /* Family 15h: Combined Unit Configuration 2 */                           
+    F10_CL_LINES_TO_NB_DIS  =   15               /*   ClLinesToNbDis - allows WP code to be cached in L2 */               
+    IC_DIS_SPEC_TLB_WR      =   35               /*   IcDisSpecTlbWr - ITLB speculative writes */                        
+                                                                                                             
+CU_CFG3                  =      0x0C001102B      /* Combined Unit Configuration 3 */                                      
+    COMBINE_CR0_CD       =      49               /*   Combine CR0.CD for both cores of a compute unit */                  
+                                                                                                             
+                                                                                                             
+CR0_PE                  = 1           # Protection Enable
+CR0_NW                  = 29          # Not Write-through
+CR0_CD                  = 30          # Cache Disable
+CR0_PG                  = 31          # Paging Enable
+                                                                                                             
+/* CPUID Functions */                                                                                            
+                                                                                                             
+CPUID_MODEL              =      1                                                                                
+AMD_CPUID_FMF            =      0x80000001       /* Family Model Features information */                                  
+AMD_CPUID_APIC           =      0x80000008       /* Long Mode and APIC info., core count */                         
+                                                                                                           
+NB_CFG                   =      0x0C001001F      /* Northbridge Configuration Register */                            
+    INIT_APIC_ID_CPU_ID_LO    = 54               /*  InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */    
+                                                                                                             
+MTRR_SYS_CFG             =      0x0C0010010      /* System Configuration Register */                                      
+  CHX_TO_DIRTY_DIS       =      16               /*   ChxToDirtyDis    Change to dirty disable  */                        
+  SYS_UC_LOCK_EN         =      17               /*   SysUcLockEn      System lock command enable */                    
+  MTRR_FIX_DRAM_EN       =      18               /*   MtrrFixDramEn    MTRR fixed RdDram and WrDram attributes enable */ 
+  MTRR_FIX_DRAM_MOD_EN   =      19               /*   MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ 
+  MTRR_VAR_DRAM_EN       =      20               /*   MtrrVarDramEn    MTRR variable DRAM enable */                     
+  MTRR_TOM2_EN           =      21               /*   MtrrTom2En       MTRR top of memory 2 enable */                    
+                                                                                                             
+PERF_CONTROL3            =      0x0C0010003      /* Performance event control three */                                    
+    PERF_CONTROL3_RESERVE_L  =  0x00200000       /* Preserve the reserved bits */                                   
+    PERF_CONTROL3_RESERVE_H  =  0x0FCF0          /* Preserve the reserved bits */                                    
+    CONFIG_EVENT_L           =  0x0F0E2          /* All cores with level detection */                                    
+    CONFIG_EVENT_H           =  4                /* Increment count by number of event */                                 
+                                                 /* occured in clock cycle */                                 
+    EVENT_ENABLE             =  22               /* Enable the event */ 
+PERF_COUNTER3            =      0x0C0010007      /* Performance event counter three */                                 
+
+# Local use flags, in upper most byte if ESI
+FLAG_UNKNOWN_FAMILY     = 24          # Signals that the family# of the installed processor is not recognized
+FLAG_STACK_REENTRY      = 25          # Signals that the environment has made a re-entry (2nd) call to set up the stack
+FLAG_IS_PRIMARY         = 26          # Signals that this core is the primary within the comoute unit
+
+CR0_MASK    = ((1 << CR0_CD) | (1 << CR0_NW))
+MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
+
+/****************************************************************************
+ *
+ *                      CPU MACROS - PUBLIC
+ *
+ ****************************************************************************/
+.macro   _WRMSR 
+        .byte 0x0f, 0x30        
+.endm
+
+.macro  _RDMSR  
+        .byte   0x0F, 0x32      
+.endm
+
+.macro AMD_CPUID arg0
+  .ifb \arg0                                             
+    mov   $0x1, %eax    
+    .byte 0x0F, 0x0A2                     /* Execute instruction */
+    bswap %eax                          
+    xchg  %ah, %al                        /* Ext model in al now */
+    rol   $0x08, %eax                     /* Ext model in ah, model in al */
+    and   $0x0FFCF, ax                    /* Keep 23:16, 7:6, 3:0 */
+  .else
+    mov   \arg0, %eax    
+    .byte 0x0F, 0x0A2   
+  .endif
+.endm
+  
+/****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+*   Set any family specific controls needed to enable the use of
+*   cache as general storage before main memory is available.
+*
+* Inputs:
+*       none
+* Outputs:
+*       none
+ ****************************************************************************/
+.macro  AMD_ENABLE_STACK_FAMILY_HOOK
+
+    AMD_ENABLE_STACK_FAMILY_HOOK_F10    
+    AMD_ENABLE_STACK_FAMILY_HOOK_F12    
+    AMD_ENABLE_STACK_FAMILY_HOOK_F14    
+    AMD_ENABLE_STACK_FAMILY_HOOK_F15    
+.endm
+  
+/****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+*   Return any family specific controls to their 'standard'
+*   settings for using cache with main memory.
+*
+* Inputs:
+*       none
+* Outputs:
+*       none
+ ****************************************************************************/
+.macro  AMD_DISABLE_STACK_FAMILY_HOOK
+
+    AMD_DISABLE_STACK_FAMILY_HOOK_F10
+    AMD_DISABLE_STACK_FAMILY_HOOK_F12
+    AMD_DISABLE_STACK_FAMILY_HOOK_F14
+    AMD_DISABLE_STACK_FAMILY_HOOK_F15
+
+.endm
+  
+/****************************************************************************
+*
+* GET_NODE_ID_CORE_ID Macro - Stackless
+*
+*   Read family specific values to determine the node and core
+*   numbers for the core executing this code.
+*
+* Inputs:
+*     none
+* Outputs:
+*     SI[7:0] = Core# (0..N, relative to node)
+*     SI[15:8]= Node# (0..N)
+*     SI[23:16]= reserved
+*     SI[24]=   flag: 1=Family Unrecognized
+*     SI[25]=   flag: 1=Interface re-entry call
+*     SI[26]=   flag: 1=Core is primary of compute unit
+*     SI[31:27]= reserved, =0
+****************************************************************************/
+.macro  GET_NODE_ID_CORE_ID
+    LOCAL  node_core_exit
+
+    mov     $-1, %si
+    GET_NODE_ID_CORE_ID_F10
+    GET_NODE_ID_CORE_ID_F12
+    GET_NODE_ID_CORE_ID_F14
+    GET_NODE_ID_CORE_ID_F15
+    /*
+     * Check for unrecognized Family
+     */
+    cmp     $-1, %si                      # Has family (node/core) already been discovered?
+    jnz     node_core_exit              # Br if yes
+    
+   mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
+	
+    mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
+    _RDMSR
+    bt      $APIC_BSC, %eax               # Is this the BSC?
+    jc      node_core_exit              # Br if yes
+    hlt                                 # Kill APs
+node_core_exit:
+
+.endm
+  
+/****************************************************************************
+##                      Family 10h MACROS
+##***************************************************************************
+#---------------------------------------------------
+#
+# AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
+#
+#   Set any family specific controls needed to enable the use of
+#   cache as general storage before main memory is available.
+#
+# Inputs:
+#       ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+# Outputs:
+#       none
+#
+# Family 10h requirements (BKDG section 2.3.3):
+#   * Paging disabled
+#   * MSRC001_0015[INVDWBINVD]=0
+#   * MSRC001_1021[DIS_IND]=1
+#   * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+#   * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+#   * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
+#   * MSRC001_1022[DIS_HW_PF]=1
+#   * MSRC001_102A[IcDisSpecTlbWr]=1
+#   * MSRC001_102A[ClLinesToNbDis]=1
+#   * No INVD or WBINVD, no exceptions, page faults or interrupts
+****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 
+    LOCAL   fam10_enable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x01, %al                      # Is this family 10h?
+    jnz     fam10_enable_stack_hook_exit # Br if no
+
+    mov     $DC_CFG, %ecx                 # MSR:C001_1022
+    _RDMSR
+    bts     $DC_DIS_SPEC_TLB_RLD, %eax     # Turn on Disable speculative DTLB reloads bit
+    bts     $DIS_CLR_WBTOL2_SMC_HIT, %eax  # Turn on Disable the self modifying code check buffer bit
+    bts     $DIS_HW_PF, %eax               # Turn on Disable hardware prefetches bit
+    _WRMSR
+
+    dec     %cx                          # MSR:C001_1021
+    _RDMSR
+    bts     $IC_DIS_SPEC_TLB_RLD, %eax     # Turn on Disable speculative TLB reloads bit
+    bts     $DIS_IND, %eax                 # Turn on Disable indirect branch predictor
+    _WRMSR
+
+    mov     $BU_CFG2, %ecx                # MSR C001_102A
+    _RDMSR
+    bts     $F10_CL_LINES_TO_NB_DIS, %eax   # Allow BIOS ROM to be cached in the IC
+    bts     $(IC_DIS_SPEC_TLB_WR-32), %edx  #Disable speculative writes to the ITLB
+    _WRMSR
+
+    mov     $HWCR, %ecx                    # MSR C001_0015
+    _RDMSR
+    bt      $FLAG_STACK_REENTRY, %esi                 # Check if stack has already been set
+    jc      fam10_skipClearingBit4
+    btr     $INVD_WBINVD, %eax             # disable INVD -> WBINVD conversion
+    _WRMSR
+    
+fam10_skipClearingBit4:
+    mov %esi, %eax                         # load core#
+    or %al, %al                       # If (BSP)
+    jne  fam10_enable_stack_hook_exit
+    mov     $PERF_COUNTER3, %ecx       #   Select performance counter three
+                                        #   to count number of CAR evictions
+    xor     %eax, %eax                #   Initialize the lower part of the counter to zero
+    xor     %edx, %edx                #   Initializa the upper part of the counter to zero
+    _WRMSR                          #   Save it
+    mov     $PERF_CONTROL3, %ecx      #   Select the event control three
+    _RDMSR                          #   Get the current setting
+    and     $PERF_CONTROL3_RESERVE_L, %eax   # Preserve the reserved bits
+    or      $CONFIG_EVENT_L, %eax      #   Set the lower part of event register to
+                                        #   select CAR Corruption occurred by any cores
+    and     $PERF_CONTROL3_RESERVE_H, %dx   # Preserve the reserved bits
+    or      $CONFIG_EVENT_H, %dx       #   Set the upper part of event register
+    _WRMSR                          #   Save it
+    bts     $EVENT_ENABLE, %eax        #   Enable it
+    _WRMSR                          #   Save it
+
+fam10_enable_stack_hook_exit:
+.endm
+  
+/****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
+*
+*   Return any family specific controls to their 'standard'
+*   settings for using cache with main memory.
+*
+* Inputs:
+*       ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+*       none
+*
+* Family 10h requirements:
+*   * INVD or WBINVD
+*   * MSRC001_0015[INVD_WBINVD]=1
+*   * MSRC001_1021[DIS_IND]=0
+*   * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
+*   * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
+*   * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0
+*   * MSRC001_1022[DIS_HW_PF]=0
+*   * MSRC001_102A[IcDisSpecTlbWr]=0
+*   * MSRC001_102A[ClLinesToNbDis]=0
+*****************************************************************************/
+     
+.macro  AMD_DISABLE_STACK_FAMILY_HOOK_F10
+    LOCAL   fam10_disable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x01, %al                     # Is this family 10h?
+    jnz     fam10_disable_stack_hook_exit # Br if no
+
+    mov     $DC_CFG, %ecx                 # MSR:C001_1022
+    _RDMSR
+    btr     $DC_DIS_SPEC_TLB_RLD, %eax    # Enable speculative TLB reloads
+    btr     $DIS_CLR_WBTOL2_SMC_HIT, %eax # Allow self modifying code check buffer
+    btr     $DIS_HW_PF, %eax              # Allow hardware prefetches
+    _WRMSR
+
+    dec     %cx                          # MSR:C001_1021
+    _RDMSR
+    btr     $DIS_IND, %eax                # Turn on indirect branch predictor
+    btr     $IC_DIS_SPEC_TLB_RLD, %eax    # Turn on speculative TLB reloads
+    _WRMSR
+
+    mov     $BU_CFG2, %ecx                # MSR:C001_102A
+    _RDMSR
+/*
+ * BTS error if SBIOS `allows WP code to be cached', but copying
+ * ramstage/payloads from ROM to RAM will be very slow if disable it here.
+ *
+ * TODO: disable `allows WP code to be cached' after the ROM to RAM copying.
+ */
+//    btr     $F10_CL_LINES_TO_NB_DIS, %eax  # Return L3 to normal mode
+    btr     $(IC_DIS_SPEC_TLB_WR-32), %edx #Re-enable speculative writes to the ITLB
+    _WRMSR
+
+    #--------------------------------------------------------------------------
+    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+    mov     $HWCR, %ecx                    # MSR:0000_0015
+    _RDMSR
+    mov     %ax, %bx                      # Save INVD -> WBINVD bit
+    btr    $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion for the invd instruction.
+    _WRMSR
+    wbinvd                                # Clear the cache tag RAMs
+    mov    %bx, %ax                      # Restore INVD -> WBINVD bit
+    _WRMSR
+
+    #--------------------------------------------------------------------------
+    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+    mov     $PERF_CONTROL3, %ecx          # Select the event control three
+    _RDMSR                              # Retrieve the current value
+    btc     $EVENT_ENABLE, %eax           # Is event enable, complement it as well
+    jnc     fam10_disable_stack_hook_exit # No
+    cmp     $CONFIG_EVENT_L, %ax          # Is the lower part of event set to capture the CAR Corruption
+    jne     fam10_disable_stack_hook_exit # No
+    cmp     $CONFIG_EVENT_H, %dl        # Is the upper part of event set to capture the CAR Corruption
+    jne     fam10_disable_stack_hook_exit # No
+    _WRMSR                              # Disable the event
+
+fam10_disable_stack_hook_exit:
+.endm   
+
+/****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F10 Macro - Stackless
+*
+*   Read family specific values to determine the node and core
+*   numbers for the core executing this code.
+*
+* Inputs:
+*     none
+* Outputs:
+*     SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro  GET_NODE_ID_CORE_ID_F10
+
+    LOCAL   node_core_f10_exit
+    LOCAL   node_core_f10_AP
+
+    cmp     $-1, %si                      # Has node/core already been discovered?
+    jnz     node_core_f10_exit          # Br if yes
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x01, %al                     # Is this family 10h?
+    jnz     node_core_f10_exit          # Br if no
+
+    xor     %esi, %esi                    # Assume BSC, clear flags
+    mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
+    _RDMSR
+    bt      $APIC_BSC, %eax             # Is this the BSC?
+    jnc      node_core_f10_AP            # Br if no
+
+        # This is the BSP.
+    # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
+    mov     $0x8000C06C, %eax             # PCI address for D18F0x6C Link Initialization Control Register
+    mov     $0x0CF8, %dx
+    out     %eax, %dx
+    add     $4, %dx
+    in      %dx, %eax
+    btr     $0, %eax                      # Set LinkInitializationControl[RouteTblDis] = 0
+    out     %eax, %dx
+    jmp     1f          #
+
+node_core_f10_AP:
+    #
+    # This is an AP. Routing tables have been enabled by the HT Init process.
+    # Also, the MailBox register was set by the BSP during early init
+    #   The Mailbox register content is formatted as follows:
+    #         UINT32 Node:4#          // The node id of Core's node.
+    #         UINT32 Socket:4#        // The socket of this Core's node.
+    #         UINT32 Module:2#        // The internal module number for Core's node.
+    #         UINT32 ModuleType:2#    // Single Module = 0, Multi-module = 1.
+    #         UINT32 :20#             // Reserved
+    #
+    mov     $0x0C0000408, %ecx             # Read the family 10h mailbox
+    _RDMSR                              #        MC4_MISC1[63:32]
+    mov     %dx, %si                      # SI = raw mailbox contents (will extract node# from this)
+    shr     $24, %ebx                     # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+    mov     %bx, %di                      # DI = Initial APIC ID (will extract core# from this)
+
+    AMD_CPUID   $AMD_CPUID_APIC          #
+    shr     $4, %ch                       # CH = ApicIdSize, #bits in APIC ID that show core#
+    inc     %cl                          # CL = Number of enabled cores in the socket
+    mov     %cx, %bx
+
+    mov     $NB_CFG, %ecx                 # MSR:C001_001F
+    _RDMSR                              # EDX has InitApicIdCpuIdLo bit
+
+    mov     %bh, %cl                      # CL = APIC ID size
+    mov     $1, %al                       # Convert APIC ID size to an AND mask
+    shl     %cl, %al                      # AL = 2^APIC ID size
+    dec     %al                          # AL = mask for relative core number
+    xor     %ah, %ah                      # AX = mask for relative core number
+    bt      $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
+    #.if (!carry?)                       # Br if yes
+    jc      0f
+        mov     $8, %ch                   # Calculate core number shift count
+        sub     %cl, %ch                  # CH = core shift count
+        mov     %ch, %cl
+        shr     %cl, %di                  # Right justify core number
+    #.endif
+   0:
+    and     %ax, %di                      # DI = socket-relative core number
+
+    mov     %si, %cx                      # CX = raw mailbox value
+    shr     $10, %cx                      # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
+    and     $3, %cl                       # Isolate ModuleType
+    xor     %bh, %bh                      # BX = Number of enabled cores in the socket
+    shr     %cl, %bx                      # BX = Number of enabled cores per node
+    xor     %dx, %dx                      # Clear upper word for div
+    mov     %di, %ax                      # AX = socket-relative core number
+    div     %bx                          # DX = node-relative core number
+    movzx   %si, %eax                     # prepare return value, [23:16]=shared Core# (=0, not shared)
+    and     $0x000F, %ax                   # AX = node number
+    shl     $8, %ax                       # [15:8]=node#
+    mov     %dl, %al                      # [7:0]=core# (relative to node)
+    mov     %eax, %esi                    # ESI = return value
+1:
+ bts     $FLAG_IS_PRIMARY, %esi        # all Family 10h cores are primary
+node_core_f10_exit:
+.endm
+
+
+/*****************************************************************************
+**                      Family 12h MACROS
+*****************************************************************************/
+/*****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless
+*
+*   Set any family specific controls needed to enable the use of
+*   cache as general storage before main memory is available.
+*
+* Inputs:
+*       ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+* Outputs:
+*       none
+*
+* Family 12h requirements (BKDG section 2.3.3):
+*   The following requirements must be satisfied prior to using the cache as general storage:
+*   * Paging must be disabled.
+*   * MSRC001_0015[INVD_WBINVD]=0
+*   * MSRC001_1020[DIS_SS]=1
+*   * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+*   * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+*   * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
+*   * MSRC001_1022[DIS_HW_PF]=1
+*   * MSRC001_1029[ClflushSerialize]=1
+*   * No INVD or WBINVD, no exceptions, page faults or interrupts
+*****************************************************************************/
+.macro  AMD_ENABLE_STACK_FAMILY_HOOK_F12
+    LOCAL   fam12_enable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x03, %al                     # Is this family 12h?
+    jnz     fam12_enable_stack_hook_exit # Br if no
+
+    mov     $DC_CFG, %ecx                 # MSR:C001_1022
+    _RDMSR
+    bts     $DC_DIS_SPEC_TLB_RLD, %eax    # Disable speculative DC-TLB reloads
+    bts     $DIS_CLR_WBTOL2_SMC_HIT, %eax # Disable self modifying code check buffer
+    bts     $DIS_HW_PF, %eax              # Disable hardware prefetches
+    _WRMSR
+
+    dec     %cx   #IC_CFG                # MSR:C001_1021
+    _RDMSR
+    bts     $IC_DIS_SPEC_TLB_RLD, %eax    # Disable speculative IC-TLB reloads
+    _WRMSR
+
+    dec     %cx   #LS_CFG                # MSR:C001_1020
+    _RDMSR
+    bts     $DIS_SS, %eax                 # Disabled Streaming store functionality
+    _WRMSR
+
+    mov     $HWCR, %ecx                   # MSR C001_0015
+    _RDMSR
+    bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
+    jc      fam12_skipClearingBit4
+    btr     $INVD_WBINVD, %eax            # disable INVD -> WBINVD conversion
+    _WRMSR
+    
+fam12_skipClearingBit4:
+    mov     $DE_CFG, %ecx                 # MSR:C001_1029
+    _RDMSR
+    bts     $CL_FLUSH_SERIALIZE, %eax     # Serialize all CL Flush actions
+    _WRMSR
+
+fam12_enable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless
+*
+*   Return any family specific controls to their 'standard'
+*   settings for using cache with main memory.
+*
+* Inputs:
+*       ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+*       none
+*
+* Family 12h requirements:
+*   * INVD or WBINVD
+*   * MSRC001_0015[INVD_WBINVD]=1
+*   * MSRC001_1020[DIS_SS]=0
+*   * MSRC001_1021[IC_DIS_SPEC_TLB_RLD]=0
+*   * MSRC001_1022[DC_DIS_SPEC_TLB_RLD]=0
+*   * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0
+*   * MSRC001_1022[DIS_HW_PF]=0
+*   * MSRC001_1029[ClflushSerialize]=0
+*****************************************************************************/
+.macro  AMD_DISABLE_STACK_FAMILY_HOOK_F12
+    LOCAL   fam12_disable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x03, %al                     # Is this family 12h?
+    jnz     fam12_disable_stack_hook_exit # Br if no
+
+    mov     $DC_CFG, %ecx                 # MSR:C001_1022
+    _RDMSR
+    btr     $DC_DIS_SPEC_TLB_RLD, %eax    # Turn on speculative DC-TLB reloads
+    btr     $DIS_CLR_WBTOL2_SMC_HIT, %eax # Enable self modifying code check buffer
+    btr     $DIS_HW_PF, %eax              # Enable Hardware prefetches
+    _WRMSR
+
+    dec     %cx   #IC_CFG                # MSR:C001_1021
+    _RDMSR
+    btr     $IC_DIS_SPEC_TLB_RLD, %eax    # Turn on speculative IC-TLB reloads
+    _WRMSR
+
+    dec     %cx   #LS_CFG                # MSR:C001_1020
+    _RDMSR
+    btr     $DIS_SS, %eax                 # Turn on Streaming store functionality
+    _WRMSR
+
+    mov     $DE_CFG, %ecx                 # MSR:C001_1029
+    _RDMSR
+    btr     $CL_FLUSH_SERIALIZE, %eax
+    _WRMSR
+
+    #--------------------------------------------------------------------------
+    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+    mov     $HWCR, %ecx                    # MSR:0000_0015h
+    _RDMSR
+    mov     %ax, %bx                      # Save INVD -> WBINVD bit
+    btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
+    _WRMSR
+    invd                                # Clear the cache tag RAMs
+    mov     %bx, %ax                      # Restore INVD -> WBINVD bit
+    _WRMSR
+
+    #--------------------------------------------------------------------------
+    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+fam12_disable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F12 Macro - Stackless
+*
+*   Read family specific values to determine the node and core
+*   numbers for the core executing this code.
+*
+* Inputs:
+*     none
+* Outputs:
+*     SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro  GET_NODE_ID_CORE_ID_F12
+
+    LOCAL   node_core_f12_exit
+
+    cmp     $-1, %si                      # Has node/core already been discovered?
+    jnz     node_core_f12_exit          # Br if yes
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x03, %al                     # Is this family 12h?
+    jnz     node_core_f12_exit          # Br if no
+
+    shr     $24, %ebx                     # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
+    bts     $FLAG_IS_PRIMARY, %ebx        # all family 12h cores are primary
+    mov     %ebx, %esi                    # ESI = Node#=0, core number
+node_core_f12_exit:
+.endm
+
+/*****************************************************************************
+**                      Family 14h MACROS
+*****************************************************************************/
+/*****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
+*
+*   Set any family specific controls needed to enable the use of
+*   cache as general storage before main memory is available.
+*
+* Inputs:
+*       ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+* Outputs:
+*       none
+*
+* Family 14h requirements (BKDG section 2.3.3):
+*   * Paging must be disabled.
+*   * MSRC001_0015[INVD_WBINVD]=0.
+*   * MSRC001_1020[DisStreamSt]=1.
+*   * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
+*   * MSRC001_1022[DIS_HW_PF]=1.
+*   * No INVD or WBINVD, no exceptions, page faults or interrupts
+*****************************************************************************/
+.macro  AMD_ENABLE_STACK_FAMILY_HOOK_F14
+    LOCAL   fam14_enable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x05, %al                     # Is this family 14h?
+    jnz     fam14_enable_stack_hook_exit # Br if no
+
+    mov     $DC_CFG, %ecx                 # MSR:C001_1022
+    _RDMSR
+    bts     $DIS_HW_PF, %eax              # Disable hardware prefetches
+    _WRMSR
+
+    dec     %cx  #IC_CFG                 # MSR:C001_1021
+    _RDMSR
+    bts     $IC_DIS_SPEC_TLB_RLD, %eax    # Disable speculative TLB reloads
+    _WRMSR
+
+    dec     %cx  #LS_CFG                 # MSR:C001_1020
+    _RDMSR
+    bts     $DIS_STREAM_ST, %eax          # Disabled Streaming store functionality
+    _WRMSR
+
+    mov     $HWCR, %ecx                   # MSR C001_0015
+    _RDMSR
+    bt      $FLAG_STACK_REENTRY, %esi     # Check if stack has already been set
+    jc      fam14_skipClearingBit4
+    btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
+    _WRMSR
+fam14_skipClearingBit4:                 # Keeping this label
+
+fam14_enable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
+*
+*   Return any family specific controls to their 'standard'
+*   settings for using cache with main memory.
+*
+* Inputs:
+*       ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+*       none
+*
+* Family 14h requirements:
+*   * INVD or WBINVD
+*   * MSRC001_0015[INVD_WBINVD]=1.
+*   * MSRC001_1020[DisStreamSt]=0.
+*   * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.
+*   * MSRC001_1022[DIS_HW_PF]=0.
+*****************************************************************************/
+.macro  AMD_DISABLE_STACK_FAMILY_HOOK_F14
+    LOCAL   fam14_disable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x05, %al                     # Is this family 14h?
+    jnz     fam14_disable_stack_hook_exit # Br if no
+
+    mov     $LS_CFG, %ecx                 # MSR:C001_1020
+    _RDMSR
+    btr     $DIS_STREAM_ST, %eax          # Turn on Streaming store functionality
+    _WRMSR
+
+    inc     %cx  #IC_CFG                 # MSR:C001_1021
+    _RDMSR
+    btr     $IC_DIS_SPEC_TLB_RLD, %eax    # Turn on speculative DC-TLB reloads
+    _WRMSR
+
+    inc     %cx  #DC_CFG                 # MSR:C001_1022
+    _RDMSR
+    btr     $DIS_HW_PF, %eax              # Turn on hardware prefetches
+    _WRMSR
+
+    #--------------------------------------------------------------------------
+    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+    mov     $HWCR, %ecx                    # MSR:C001_0015h
+    _RDMSR
+    btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
+    _WRMSR
+    invd                                # Clear the cache tag RAMs
+    bts     $INVD_WBINVD, %eax            # Turn on Conversion of INVD to WBINVD
+    _WRMSR
+
+    #--------------------------------------------------------------------------
+    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+fam14_disable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F14 Macro - Stackless
+*
+*   Read family specific values to determine the node and core
+*   numbers for the core executing this code.
+*
+* Inputs:
+*     none
+* Outputs:
+*     SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro  GET_NODE_ID_CORE_ID_F14
+
+    LOCAL   node_core_f14_exit
+
+    cmp     $0x-1, %si                      # Has node/core already been discovered?
+    jnz     node_core_f14_exit          # Br if yes
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x05, %al                     # Is this family 14h?
+    jnz     node_core_f14_exit          # Br if no
+
+    xor     %esi, %esi                    # Node must be 0
+    bts     $FLAG_IS_PRIMARY, %esi        # all family 14h cores are primary
+    mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
+    _RDMSR
+    bt      $APIC_BSC, %eax               # Is this the BSC?
+    jc      node_core_f14_exit          # Br if yes
+    inc     %si                          # Set core to 1
+node_core_f14_exit:
+.endm
+
+
+
+/*****************************************************************************
+**                      Family 15h MACROS
+*****************************************************************************/
+/*****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
+*
+*   Set any family specific controls needed to enable the use of
+*   cache as general storage before main memory is available.
+*
+* Inputs:
+*       ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+* Outputs:
+*       none
+*
+* Family 15h requirements (BKDG #42301 section 2.3.3):
+*   * Paging must be disabled.
+*   * MSRC001_0015[INVD_WBINVD]=0
+*   * MSRC001_1020[DisSS]=1
+*   * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+*   * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+*   * MSRC001_1022[DisHwPf]=1
+*   * No INVD or WBINVD, no exceptions, page faults or interrupts
+*****************************************************************************/
+.macro  AMD_ENABLE_STACK_FAMILY_HOOK_F15
+    LOCAL   fam15_enable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x06, %al                     # Is this family 15h?
+    jnz     fam15_enable_stack_hook_exit # Br if no
+
+    bt      $FLAG_STACK_REENTRY , %esi                 # Check if stack has already been set
+    jc      fam15_skipClearingBit4
+    mov     $HWCR, %ecx                   # MSR C001_0015
+    _RDMSR
+    btr     $INVD_WBINVD, %eax            # disable INVD -> WBINVD conversion
+    _WRMSR
+    
+fam15_skipClearingBit4:
+    mov     $LS_CFG, %ecx                 # MSR:C001_1020
+    _RDMSR
+    bts     $DIS_SS, %eax                 # Turn on Streaming store functionality disabled bit
+    _WRMSR
+
+    inc     %ecx  #IC_CFG                # MSR:C001_1021
+    _RDMSR
+    bts     $IC_DIS_SPEC_TLB_RLD, %eax    # Turn on Disable speculative IC-TLB reloads bit
+    _WRMSR
+
+    inc     %ecx  #DC_CFG                # MSR:C001_1022
+    _RDMSR
+    bts     $DC_DIS_SPEC_TLB_RLD, %eax    # Turn on Disable speculative DC-TLB reloads bit
+    bts     $DIS_HW_PF, %eax              # Turn on Disable hardware prefetches bit
+    _WRMSR
+
+    mov     $CU_CFG3, %ecx                # MSR:C001_102B
+    _RDMSR
+    btr     $(COMBINE_CR0_CD - 32), %edx         # Clear CombineCr0Cd bit
+    _WRMSR
+
+fam15_enable_stack_hook_exit:
+.endm
+
+
+/*****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
+*
+*   Return any family specific controls to their 'standard'
+*   settings for using cache with main memory.
+*
+* Inputs:
+*       ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+*       none
+*
+* Family 15h requirements:
+*   * INVD or WBINVD
+*   * MSRC001_0015[INVD_WBINVD]=1
+*   * MSRC001_1020[DisSS]=0
+*   * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
+*   * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
+*   * MSRC001_1022[DIS_HW_PF]=0
+*****************************************************************************/
+.macro  AMD_DISABLE_STACK_FAMILY_HOOK_F15
+    LOCAL   fam15_disable_stack_hook_exit
+
+    AMD_CPUID   $CPUID_MODEL
+    mov     %eax, %ebx                    # Save revision info to EBX
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $0x06, %al                     # Is this family 15h?
+    jnz     fam15_disable_stack_hook_exit # Br if no
+
+    mov     $LS_CFG, %ecx                 # MSR:C001_1020
+    #.if (ebx != 00600F00h)              ; Is this rev A0?
+    cmp	$0x00600F00, %ebx
+    jz	0f
+    _RDMSR
+    btr     $DIS_SS, %eax                 # Turn on Streaming store functionality
+    _WRMSR
+    #.endif
+    0:                              # End workaround for errata 495 and 496
+
+    inc     %ecx  #IC_CFG                # MSR:C001_1021
+    _RDMSR
+    btr     $IC_DIS_SPEC_TLB_RLD, %eax    # Turn on speculative TLB reloads
+    _WRMSR
+
+    inc     %ecx  #DC_CFG                # MSR:C001_1022
+    _RDMSR
+    btr     $DC_DIS_SPEC_TLB_RLD, %eax    # Turn on speculative TLB reloads
+    #.if (ebx != 00600F00h)              # Is this rev A0?
+    cmp	$0x00600F00, %ebx
+    jz	0f
+    btr     $DIS_HW_PF, %eax              # Turn on hardware prefetches
+    #.endif                              # End workaround for erratum 498
+    0:
+    _WRMSR	
+    #--------------------------------------------------------------------------
+    # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+    bt      $FLAG_IS_PRIMARY, %esi
+    #.if (carry?)                        # Only clear cache from primary core
+    jnc 0f
+    mov     $HWCR, %ecx                    # MSR:C001_0015h
+    _RDMSR
+    btr     $INVD_WBINVD, %eax            # Disable INVD -> WBINVD conversion
+    _WRMSR
+    invd                                # Clear the cache tag RAMs
+    bts     $INVD_WBINVD, %eax            # Turn on Conversion of INVD to WBINVD
+    _WRMSR
+    #.endif                              # end
+    0:
+
+    #--------------------------------------------------------------------------
+    # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+    #--------------------------------------------------------------------------
+
+    mov     $CU_CFG3, %ecx                # MSR:C001_102B
+    _RDMSR
+    bts     $(COMBINE_CR0_CD - 32), %eax         # Set CombineCr0Cd bit
+    _WRMSR
+
+fam15_disable_stack_hook_exit:
+.endm
+
+
+/*****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F15 Macro - Stackless
+*
+*   Read family specific values to determine the node and core
+*   numbers for the core executing this code.
+*
+* Inputs:
+*     none
+* Outputs:
+*     SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro  GET_NODE_ID_CORE_ID_F15
+
+    LOCAL   node_core_f15_exit
+    LOCAL   node_core_f15_AP
+    LOCAL   node_core_f15_shared
+
+    cmp     $-1, %si                      # Has node/core already been discovered?
+    jnz     node_core_f15_exit          # Br if yes
+
+    AMD_CPUID   $CPUID_MODEL
+    shr     $20, %eax                     # AL = cpu extended family
+    cmp     $06, %al                     # Is this family 15h?
+    jnz     node_core_f15_exit          # Br if no
+
+    xor     %esi, %esi                    # Assume BSC, clear local flags
+    mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
+    _RDMSR
+    bt      $APIC_BSC, %eax               # Is this the BSC?
+    jnc      node_core_f15_AP            # Br if no
+
+    # This is the BSP.
+    # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
+    mov     $0x8000C06C, %eax              # PCI address for D18F0x6C Link Initialization Control Register
+    mov     $0x0CF8, %dx
+    out     %eax, %dx
+    add     $4, %dx
+    in      %dx, %eax
+    btr     $0, %eax                      # Set LinkInitializationControl[RouteTblDis] = 0
+    out     %eax, %dx
+    jmp     node_core_f15_shared        #
+
+node_core_f15_AP:
+    #
+    # This is an AP. Routing tables have been enabled by the HT Init process.
+    # Also, the MailBox register was set by the BSP during early init
+    #   The Mailbox register content is formatted as follows:
+    #         UINT32 Node:4;          // The node id of Core's node.
+    #         UINT32 Socket:4;        // The socket of this Core's node.
+    #         UINT32 Module:2;        // The internal module number for Core's node.
+    #         UINT32 ModuleType:2;    // Single Module = 0, Multi-module = 1.
+    #         UINT32 :20;             // Reserved
+    #
+    mov     $0x0C0000408, %ecx             # Read the family 15h mailbox
+    _RDMSR                              #      MC4_MISC1[63:32]
+    mov     %dx, %si                      # SI = raw mailbox contents (will extract node# from this)
+    shr     $24, %ebx                     # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+    mov     %bx, %di                      # DI = Initial APIC ID (will extract core# from this)
+
+    AMD_CPUID   $AMD_CPUID_APIC          #
+    shr     $4, %ch                       # CH = ApicIdSize, #bits in APIC ID that show core#
+    inc     %cl                          # CL = Number of enabled cores in the socket
+    mov     %cx, %bx
+
+    mov     $NB_CFG, %ecx
+    _RDMSR                              # EDX has InitApicIdCpuIdLo bit
+
+    mov     %bh, %cl                      # CL = APIC ID size
+    mov     $1, %al                       # Convert APIC ID size to an AND mask
+    shl     %cl, %al                      # AL = 2^APIC ID size
+    dec     %al                          # AL = mask for relative core number
+    xor     %ah, %ah                      # AX = mask for relative core number
+    bt      $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
+    #.if (!carry?)                       # Br if yes
+    jc      0f
+        mov     $8, %ch                   # Calculate core number shift count
+        sub     %cl, %ch                  # CH = core shift count
+        mov     %ch, %cl
+        shr     %cl, %di                  # Right justify core number
+    #.endif
+    0:
+    and     %ax, %di                      # DI = socket-relative core number
+
+    mov     %si, %cx                      # CX = raw mailbox value
+    shr     $10, %cx                      # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
+    and     $3, %cl                       # Isolate ModuleType
+    xor     %bh, %bh                      # BX = Number of enabled cores in the socket
+    shr     %cl, %bx                      # BX = Number of enabled cores per node
+    xor     %dx, %dx                      # Clear upper word for div
+    mov     %di, %ax                      # AX = socket-relative core number
+    div     %bx                          # DX = node-relative core number
+    movzx   %si, %eax                     # Prepare return value
+    and     $0x000F, %ax                   # AX = node number
+    shl     $8,%ax                       # [15:8]=node#
+    mov     %dl, %al                      # [7:0]=core# (relative to node)
+    mov     %eax, %esi                    # ESI = node-relative core number
+
+      #
+      #   determine if this core shares MTRRs
+      #
+node_core_f15_shared:
+    mov     $0x8000C580, %eax              # Compute Unit Status
+    mov     %si, %bx
+    shl     $3, %bh                       # Move node# to PCI Dev# field
+    add     %bh, %ah                      # Adjust for node number
+    mov     $0x0CF8, %dx
+    out     %eax, %dx
+    add     $4, %dx
+    in      %dx, %eax                     # [3:0]=Enabled# [19:16]=DualCore
+
+                                        # BL is MyCore#
+    mov     $0x06, %cx                     # Use CH as 'first of pair' core#
+    #.while (cl > 0)
+    jmp  0f
+    8:
+        bt      $0, %eax                  # Is pair enabled?
+        #.if (carry?)                    #
+        jnc     1f
+            mov     $0x01, %bh             #   flag core as primary
+            bt      $16, %eax             # Is there a 2nd in the pair?
+            #.if (carry?)                #
+            jnc 4f
+                #.break .if (ch == bl)   # Does 1st match MyCore#?
+                cmp     %bl, %ch
+                je      9f
+                inc     %ch
+                xor     %bh, %bh          #     flag core as NOT primary
+                #.break .if (ch == bl)   # Does 2nd match MyCore#?
+                cmp     %bl, %ch
+                je      9f
+                jmp     2f   
+            #.else                       # No 2nd core
+            4:
+                #.break .if (ch == bl)   # Does 1st match MyCore#?
+                cmp     %bl, %ch
+                je      9f
+            #.endif
+            2:
+            inc     %ch
+        #.endif
+        1:
+        shr     $1, %eax
+        dec     %cl
+    #.endw
+    0:
+    #.if (cl == 0)
+    cmp $0x0, %cl
+    ja	8b
+    9:
+    or	%cl, %cl
+    jne 1f
+        #Error - core# didn't match Compute Unit Status content
+        bts     $FLAG_UNKNOWN_FAMILY, %esi
+        bts     $FLAG_IS_PRIMARY, %esi    #   Set Is_Primary for unknowns
+    #.endif
+    1:
+    #.if (bh != 0)                       # Check state of primary for the matched core
+    or %bh, %bh
+    je 2f
+        bts     $FLAG_IS_PRIMARY, %esi    #   Set shared flag into return value
+    #.endif
+    2:
+
+node_core_f15_exit:
+
+.endm
+
+/*****************************************************************************
+* AMD_ENABLE_STACK:  Setup a stack
+*
+*   In:
+*       EBX  = Return address (preserved)
+*
+*   Out:
+*       SS:ESP - Our new private stack location
+*
+*       EAX = AGESA_STATUS
+*
+*       ECX = Stack size in bytes
+*
+*   Requirements:
+*       * This routine presently is limited to a max of 64 processor cores
+*   Preserved:
+*       ebx ebp
+*   Destroyed:
+*       eax, ecx, edx, edi, esi, ds, es, ss, esp
+*       mmx0, mmx1
+*
+*   Description:
+* Fixed MTRR address allocation to cores:
+* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
+* There is a max of 1 BSP, 7 core0s and 56 other cores.
+* Although each core has it's own cache storage, they share the address space. Each core must
+* be assigned a private and unique address space for its stack. To support legacy systems,
+* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
+* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
+*
+* 80000h                                        40000h                                      00000h
+*     +----------+----------+----------+----------+----------+----------+----------+----------+
+* 64K |          |          |          |          |          |          |          |          |  64K  ea
+*  ea +----------+----------+----------+----------+----------+----------+----------+----------+
+*     |                             MTRR 0000_0250 MTRRfix64K_00000                           |
+*     +----------+----------+----------+----------+----------+----------+----------+----------+
+*     |  7 ,  6  |  5 ,  4  |  3 ,  2  |  1 ,  0  |     0    |          |          |          | <-node
+*     |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 |     0    |          |          |          | <-core
+*     +----------+----------+----------+----------+----------+----------+----------+----------+
+*
+* C0000h                       B0000h                      A0000h                      90000h                      80000h
+*     +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*16K  |      |      |      |      |      |      |      |      |      |      |      |      |      |      |      |      |
+* ea  +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*     |              MTRR 0259 MTRRfix16K_A0000               |             MTRR 0258 MTRRfix16K_80000                |
+*     +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*     | > Dis|play B|uffer |   <  |      |      |      |      |   7  |  6   |  5   |  4   |  3   |  2   |  1   |      | <-node
+*     | >   T| e  m |p o r |a r y |  B u |f f e |r   A |r e a<|   0  |  0   |  0   |  0   |  0   |  0   |  0   |      | <-core
+*     +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*
+* E0000h                                            D0000h                                         C0000h
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* 4K  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  4K  ea
+*  ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*     |  026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000  | 0269 MTRRfix4K_C8000  | 0268 MTRRfix4K_C0000  |
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*     |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | >| V| I| D| E| O|  |B |I |O |S |  |A |r |e |a<|
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*
+* 100000h                                           F0000h                                          E0000h
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*     |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  4K  ea
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*     |  026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000  | 026D MTRRfix4K_E8000  | 026C MTRRfix4K_E0000  |
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*     | >|MA|IN| B|IO|S |RA|NG|E |  |  |  |  |  |  |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE|  |  |  |  |  |< |
+*     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*****************************************************************************/
+.macro  AMD_ENABLE_STACK 
+
+# These are local labels. Declared so linker doesn't cause 'redefined label' errors
+    LOCAL   SetupStack
+    LOCAL   Real16bMode
+    LOCAL   Protected32Mode
+    LOCAL   ClearTheStack
+
+#   Note that SS:ESP will be default stack.  Note that this stack
+#   routine will not be used after memory has been initialized.  Because
+#   of its limited lifetime, it will not conflict with typical PCI devices.
+    movd    %ebx, %mm0                    # Put return address in a safe place
+    movd    %ebp, %mm1                    # Save some other user registers
+
+    # get node id and core id of current executing core
+    GET_NODE_ID_CORE_ID                 # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
+    # Note: ESI[31:24] are used for flags:  Unrecognized Family,  Is_Primary core,  Stack already established
+
+    # determine if stack is already enabled. We are using the DefType MSR for this determination.
+    # It is =0 after reset; CAR setup sets it to enable the MTRRs
+    mov     %cr0, %eax
+    test    $CR0_MASK, %eax              # Is cache disabled? (CD & NW bits)
+    jnz     SetupStack                  # Jump if yes
+    mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
+    _RDMSR
+    test    $MSR_MASK, %eax                     # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
+    jz      SetupStack                  # Jump if no
+    or      $FLAG_STACK_REENTRY, %esi             # Bit25, indicate stack has already been initialized
+
+SetupStack:
+    # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
+    mov     %esi, %ebx                    # Get my Node/Core info
+    xor     %bl, %bl
+    shl     $3, %bh                       # Isolate my node#, match alignment for PCI Dev#
+    mov     $0x8000C144, %eax              # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit
+    add     %bh, %ah
+    mov     %eax, %ebx                    # Save PCI address for Base/Limit pair
+
+    mov     $0x0CF8, %dx
+    out     %eax, %dx
+    add     $4, %dx
+    xor     %eax, %eax                    # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
+    out     %eax, %dx                     # DRAM Limit = node0, no interleave
+
+    mov     %ebx, %eax
+    sub     $4, %eax                      # Now point to the Base register
+    mov     $0x0CF8, %dx
+    out     %eax, %dx
+    add     $4, %dx
+    mov     $0x00000003, %eax              # Set the read and write enable bits
+    out     %eax, %dx                     # DRAM Base = 0x0000, R/W
+
+    AMD_ENABLE_STACK_FAMILY_HOOK
+
+    # Init CPU MSRs for our init routines
+    mov     $MTRR_SYS_CFG, %ecx           # SYS_CFG
+    _RDMSR
+    bts     $MTRR_FIX_DRAM_MOD_EN, %eax   # Turn on modification enable bit
+    _WRMSR
+
+    mov     %esi, %eax
+    bt      $FLAG_STACK_REENTRY, %eax     # Is this a 2nd entry?
+    #.if (!carry?)                       #   On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
+    jc 0f
+        bt      $FLAG_IS_PRIMARY, %eax    #   Is this core the primary in a compute unit?
+        #.if (carry?)                    #     Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
+            #  Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
+            # Clear all variable and Fixed MTRRs for non-shared cores
+        jnc 0f    
+        mov     $AMD_MTRR_VARIABLE_BASE0, %ecx
+        xor     %eax, %eax
+        xor     %edx, %edx
+        #.while (cl != 10h)                  # Variable MTRRphysBase[n] and MTRRphysMask[n]
+        jmp	1f
+        2:
+            _WRMSR
+            inc     %cl
+        #.endw
+        1:
+        cmp	$0x10, %cl
+        jne	2b
+        mov     $AMD_MTRR_FIX64k_00000, %cx   # MSR:0000_0250
+        _WRMSR
+        mov     $AMD_MTRR_FIX16k_80000, %cx   # MSR:0000_0258
+        _WRMSR
+        mov     $AMD_MTRR_FIX16k_A0000, %cx   # MSR:0000_0259
+        _WRMSR
+        mov     $AMD_MTRR_FIX4k_C0000, %cx    # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
+        #.while (cl != 70h)
+        jmp 3f
+        4:
+            _WRMSR
+            inc     %cl
+        #.endw
+        3:
+        cmp $0x70, %cl
+        jne  4b
+        # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
+        #  - not strictly needed since the FixedMTRRs take presedence.
+        mov     $(16 * 1024 * 1024), %eax
+        mov     $TOP_MEM, %ecx            # MSR:C001_001A
+        _WRMSR
+        #.endif                          #   End Is_Primary
+    #.endif                              # End Stack_ReEntry
+    0:    
+    # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
+    xor     %eax, %eax
+    xor     %edx, %edx
+    mov     $IORR_BASE, %ecx              # MSR:C001_0016 - 0019
+    #.while (cl != 1Ah)
+    jmp  1f
+    2:   
+        _WRMSR
+        inc     %cl
+    #.endw
+    1:  
+    cmp $0x1A, %cl
+    jne  2b   
+    mov     $TOP_MEM2, %ecx               # MSR:C001_001D
+    _WRMSR
+
+    # setup MTTRs for stacks
+    #   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
+    #    or due to a data zone being interpreted as code. When a speculative read occurs outside a
+    #    controlled region (intentionally used by software), it could cause an unwanted cache eviction.
+    #   To prevent speculative reads from causing an eviction, the unused cache ranges are set
+    #    to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
+    #    Note: some core stack regions will share an MTRR since the control granularity is much
+    #    larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
+    #    space covered by the MTRR when parseling out cache space for the various uses. In some cases
+    #    this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
+    #
+    # Outcome of this block is that:   (Note the MTRR map at the top of the file)
+    #   ebp - start address of stack block
+    #   ebx - [31:16] - MTRR MSR address
+    #       - [15:8]  - slot# in MTRR register
+    #       - [7:0]   - block size in #4K blocks
+    # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
+    #
+
+    mov     %si, %ax                      # Load node, core
+    #.if (al == 0)                       # Is a core 0?
+    or %al, %al
+    jne 1f
+        #.if (ah == 0)                   # Is Node 0? (BSP)
+        or %ah, %ah
+        jne 2f
+            # Is BSP, assign a 64K stack
+            mov     $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE  / 0x1000)), %ebx
+            mov     $BSP_STACK_BASE_ADDR, %ebp
+            jmp     0f
+        #.else   # node 1 to 7, core0
+        2:
+            # Is a Core0 of secondary node, assign 16K stacks
+            mov     $AMD_MTRR_FIX16k_80000, %bx
+            shl     $16, %ebx             #
+            mov     %ah, %bh              # Node# is used as slot#
+            mov     $(CORE0_STACK_SIZE / 0x1000), %bl
+            mov     %ah, %al              # Base = (Node# * Size)#
+            mul     %bl                  #
+            movzx   %ax, %eax             #
+            shl     $12, %eax             # Expand back to full byte count (* 4K)
+            add     $CORE0_STACK_BASE_ADDR, %eax
+            mov     %eax, %ebp
+        #.endif
+        jmp 0f
+    #.else    #core 1 thru core 7
+    1:
+        # Is core 1-7 of any node, assign 4K stacks
+        mov     $8, %al                   # CoreIndex = ( (Node# * 8) ...
+        mul     %ah                      #
+        mov     %si, %bx                  #
+        add     %bl, %al                  #         ...  + Core#)#
+
+        mov     $AMD_MTRR_FIX64k_00000, %bx
+        shl     $16, %ebx                 #
+        mov     %al, %bh                  # Slot# = (CoreIndex / 16) + 4#
+        shr     $4, %bh                   #
+        add     $4, %bh                   #
+        mov     $(CORE1_STACK_SIZE / 0x1000), %bl
+
+        mul     %bl                      # Base = ( (CoreIndex * Size) ...
+        movzx   %ax, %eax                 #
+        shl     $12, %eax                 # Expand back to full byte count (* 4K)
+        add     $CORE1_STACK_BASE_ADDR, %eax #     ...   + Base_Addr)#
+        mov     %eax, %ebp
+    #.endif
+    0:
+        
+    # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
+    mov     $WB_DRAM_TYPE, %edi           # Load Cache type in 1st slot
+    mov     %bh, %cl                      # ShiftCount =  ((slot#   ...
+    and     $0x03, %cl                     #   ...  % 4)             ...
+    shl     $0x03, %cl                       #   ...  * 8)#
+    shl     %cl, %edi                     # Cache type is now in correct position
+    ror     $16, %ebx                     # Get the MTRR address
+    movzx   %bx, %ecx                     #
+    rol     $16, %ebx                     # Put slot# & size back in BX
+    _RDMSR                              # Read-modify-write the MSR
+    #.if (bh < 4)                        # Is value in lower or upper half of MSR?
+    cmp $4, %bh
+    jae 1f
+        or      %edi, %eax                #
+        jmp     0f
+    #.else
+    1:                               #
+        or      %edi, %edx                #
+    #.endif                              #
+    0:
+    _WRMSR                              #
+
+    # Enable MTRR defaults as UC type
+    mov     $AMD_MTRR_DEFTYPE, %ecx       # MSR:0000_02FF
+    _RDMSR                              # Read-modify-write the MSR
+    bts     $MTRR_DEF_TYPE_EN, %eax       # MtrrDefTypeEn
+    bts     $MTRR_DEF_TYPE_FIX_EN, %eax   # MtrrDefTypeFixEn
+    _WRMSR
+
+    # Close the modification window on the Fixed MTRRs
+    mov     $MTRR_SYS_CFG, %ecx           # MSR:0C001_0010
+    _RDMSR
+    bts     $MTRR_FIX_DRAM_EN, %eax       # MtrrFixDramEn
+    bts     $MTRR_VAR_DRAM_EN, %eax       # variable MTRR enable bit
+    btr     $MTRR_FIX_DRAM_MOD_EN, %eax   # Turn off modification enable bit
+    _WRMSR
+
+    # Enable caching in CR0
+    mov     %cr0, %eax                    # Enable WT/WB cache
+    btr     $CR0_PG, %eax                     # Make sure paging is disabled
+    btr     $CR0_CD, %eax                     # Clear CR0 NW and CD
+    btr     $CR0_NW, %eax
+    mov     %eax, %cr0
+
+    # Use the Stack Base & size to calculate SS and ESP values
+    # review:
+    #       esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+    #       ebp - start address of stack block
+    #       ebx - [31:16] - MTRR MSR address
+    #           - [15:8]  - slot# in MTRR register
+    #           - [7:0]   - block size in #4K blocks
+    #
+    mov     %ebp, %esp                    # Initialize the stack pointer
+    mov     %esp, %edi                    # Copy the stack start to edi
+    movzx   %bl, %bx
+    movzx   %bx, %ebx                     # Clear upper ebx, don't need MSR addr anymore
+    shl     $12, %ebx                     # Make size full byte count (* 4K)
+    add     %ebx, %esp                    # Set the Stack Pointer as full linear address
+    sub     $4, %esp
+    #
+    # review:
+    #       esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+    #       edi - 32b start address of stack block
+    #       ebx - size of stack block
+    #       esp - 32b linear stack pointer
+    #
+
+    # Determine mode for SS base;
+    mov     %cr0, %ecx                    # Check for 32-bit protect mode
+    bt      $CR0_PE, %ecx                 #
+    #.if (!carry?)                       # PE=0 means real mode
+    jc      Protected32Mode
+    mov     %cs, %cx                      # PE=1
+    cmp     $0x0D000, %cx                  # Check for CS
+    jb      Protected32Mode             # If CS < D000, it is a selector instead of a segment
+            # alter SS:ESP for 16b Real Mode:
+Real16bMode:
+    mov     %edi, %eax
+    shr     $4, %eax                      # Create a Real Mode segment for ss, ds, es
+    mov     %ax, %ss
+    mov     %ax, %ds
+    mov     %ax, %es
+    shl     $4, %eax
+    sub     %eax, %edi                    # Adjust the clearing pointer for Seg:Offset mode
+    mov     %ebx, %esp                    # Make SP an offset from SS
+    sub     $4, %esp              #
+    #    .endif                          # endif
+    # #else
+    #   Default is to use Protected 32b Mode
+    #.endif
+    ;
+Protected32Mode:
+    #
+    # Clear The Stack
+    #   Now that we have set the location and the MTRRs, initialize the cache by
+    #   reading then writing to zero all of the stack area.
+    # review:
+    #       ss  - Stack base
+    #       esp - stack pointer
+    #       ebx - size of stack block
+    #       esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+    #       edi -  address of start of stack block
+    #
+
+ClearTheStack:                          # Stack base is in SS, stack pointer is in ESP
+    shr     $2, %ebx                      # ebx = stack block size in dwords
+    mov     %bx, %cx                      #
+    # Check our flags - Don't clear an existing stack
+    #.if ( !(esi & 0FF000000h))          # Check our flags
+    test    $(1 << FLAG_STACK_REENTRY), %esi
+    jne 1f
+        cld
+        mov     %edi, %esi
+        rep     lodsl (%esi)    # Pre-load the range
+        xor     %eax, %eax
+        mov     %bx, %cx
+        mov     %edi, %esi                # Preserve base for push on stack
+        rep     stosl (%edi)    # Clear the range
+        movl     $0x0ABCDDCBA, (%esp) # Put marker in top stack dword
+        shl     $2, %ebx                  # Put stack size and base
+        push    %ebx                     #  in top of stack
+        push    %esi
+
+        mov     %ebx, %ecx                # Return size of stack in bytes
+        xor     %eax, %eax                # eax = 0 : no error return code
+        jmp     0f
+    #.else
+    1:
+        movzx   %cx, %ecx
+        shl     $2, %ecx                  # Return size of stack in bytes
+        mov     %esi, %eax
+        shr     $24, %eax                 # Keep the flags as part of the error report
+        or      $0x40000000, %eax          # eax = AGESA_WARNING (Stack has already been set up)
+    #.endif
+    0:
+
+    movd        %mm0, %ebx                # Restore return address
+    movd        %mm1, %ebp
+.endm
+
+/*****************************************************************************
+* AMD_DISABLE_STACK:  Destroy the stack inside the cache. This routine
+*                     should only be executed on the BSP
+*
+*   In:
+*       none
+*
+*   Out:
+*       EAX = AGESA_SUCCESS
+*
+*   Preserved:
+*       ebx
+*   Destroyed:
+*       eax, ecx, edx, esp
+*****************************************************************************/
+.macro  AMD_DISABLE_STACK 
+
+    mov     %ebx, %esp                    # Save return address
+
+    # get node/core/flags of current executing core
+    GET_NODE_ID_CORE_ID                 # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
+
+    # Turn on modification enable bit
+    mov     $MTRR_SYS_CFG, %ecx           # MSR:C001_0010
+    _RDMSR
+    bts     $MTRR_FIX_DRAM_MOD_EN, %eax   # Enable modifications
+    _WRMSR
+
+    # Set lower 640K MTRRs for Write-Back memory caching
+    mov     $AMD_MTRR_FIX64k_00000, %ecx
+    mov     $0x1E1E1E1E, %eax
+    mov     %eax, %edx
+    _WRMSR                              # 0 - 512K = WB Mem
+    mov     $AMD_MTRR_FIX16k_80000, %ecx
+    _WRMSR                              # 512K - 640K = WB Mem
+
+    # Turn off modification enable bit
+    mov     $MTRR_SYS_CFG, %ecx           # MSR:C001_0010
+    _RDMSR
+    btr     $MTRR_FIX_DRAM_MOD_EN, %eax   # Disable modification
+    _WRMSR
+
+    AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
+
+    mov     %esp, %ebx
+    xor     %eax, %eax
+
+.endm
+