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authorMartin Roth <martinroth@google.com>2017-06-18 13:18:10 -0600
committerMartin Roth <martinroth@google.com>2017-06-22 15:19:05 +0000
commit287f9638af7ab1f0b4bc420a6644591b9cdfd729 (patch)
tree15862e9a4fe013f403af50dda4c41603fe81c0f1
parentbe05f5d7d16b55cd4188da6ae4e4b9977933d057 (diff)
downloadcoreboot-287f9638af7ab1f0b4bc420a6644591b9cdfd729.tar.xz
mainboard/bifferos: remove bifferboard
This board can't be found to be tested, and compiles romstage with romcc. If desired, it can be continued in the 4.6 branch. Change-Id: I4826c277bbb444c2f0573729d76cd492ade95b4c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/bifferos/Kconfig31
-rw-r--r--src/mainboard/bifferos/Kconfig.name2
-rw-r--r--src/mainboard/bifferos/bifferboard/Kconfig16
-rw-r--r--src/mainboard/bifferos/bifferboard/Kconfig.name2
-rw-r--r--src/mainboard/bifferos/bifferboard/board_info.txt1
-rw-r--r--src/mainboard/bifferos/bifferboard/devicetree.cb6
-rw-r--r--src/mainboard/bifferos/bifferboard/romstage.c58
7 files changed, 0 insertions, 116 deletions
diff --git a/src/mainboard/bifferos/Kconfig b/src/mainboard/bifferos/Kconfig
deleted file mode 100644
index 06f0f9f4e5..0000000000
--- a/src/mainboard/bifferos/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if VENDOR_BIFFEROS
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/bifferos/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/bifferos/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Bifferos"
-
-endif # VENDOR_BIFFEROS
diff --git a/src/mainboard/bifferos/Kconfig.name b/src/mainboard/bifferos/Kconfig.name
deleted file mode 100644
index d16063ebcf..0000000000
--- a/src/mainboard/bifferos/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_BIFFEROS
- bool "Bifferos"
diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig
deleted file mode 100644
index c65b02ffa2..0000000000
--- a/src/mainboard/bifferos/bifferboard/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if BOARD_BIFFEROS_BIFFERBOARD
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select BOARD_ROMSIZE_KB_128
- select SOC_RDC_R8610
-
-config MAINBOARD_DIR
- string
- default bifferos/bifferboard
-
-config MAINBOARD_PART_NUMBER
- string
- default "Bifferboard"
-
-endif # BOARD_BIFFEROS_BIFFERBOARD
diff --git a/src/mainboard/bifferos/bifferboard/Kconfig.name b/src/mainboard/bifferos/bifferboard/Kconfig.name
deleted file mode 100644
index c5eeaaa1d8..0000000000
--- a/src/mainboard/bifferos/bifferboard/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_BIFFEROS_BIFFERBOARD
- bool "Bifferboard"
diff --git a/src/mainboard/bifferos/bifferboard/board_info.txt b/src/mainboard/bifferos/bifferboard/board_info.txt
deleted file mode 100644
index 7680e6f854..0000000000
--- a/src/mainboard/bifferos/bifferboard/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: half
diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb
deleted file mode 100644
index a64b138cb0..0000000000
--- a/src/mainboard/bifferos/bifferboard/devicetree.cb
+++ /dev/null
@@ -1,6 +0,0 @@
-chip soc/rdc/r8610
- device domain 0 on
- device pci 0.0 on end
- device pci 7.0 on end # SB
- end
-end
diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c
deleted file mode 100644
index 8c7744d8c2..0000000000
--- a/src/mainboard/bifferos/bifferboard/romstage.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include "arch/x86/romcc_console.c"
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-
-static void main(void)
-{
- uint32_t tmp;
- post_code(0x05);
-
- /* Set timer1 to pulse generator 15us for memory refresh */
- outb(0x54, 0x43);
- outb(0x12, 0x41);
-
- /* CPU setup, romcc pukes on invd() */
- asm volatile ("invd");
- enable_cache();
-
- /* Set serial base */
- pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8);
- /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
- pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012);
-
- console_init();
-
- /* memory init */
- pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f);
- pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451);
- pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003);
-
- /* memory phase/buffer strength for read and writes */
- tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64);
- tmp &= 0x0FF00FFFF;
- tmp |= 0x790000;
- pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp);
- /* Route Cseg, Dseg, Eseg and Fseg to RAM */
- pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0);
-}