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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 18:02:08 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-27 17:29:33 +0000 |
| commit | 298aa98b816e769f4cedd0b2a0e7e7da656aa18b (patch) | |
| tree | 6eb353892a6d728420e6e4e3b4e09750fb14410b | |
| parent | cf39f89fd9bc1177670da55a1432ce0631549f1f (diff) | |
| download | coreboot-298aa98b816e769f4cedd0b2a0e7e7da656aa18b.tar.xz | |
sb/intel/i82801ix: Use common early SPI code
Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| -rw-r--r-- | src/southbridge/intel/i82801ix/bootblock.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 479c5880bd..7a66b47de0 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -2,16 +2,12 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> #include "i82801ix.h" -static void enable_spi_prefetch(void) -{ - pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); -} - void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); i82801ix_early_init(); i82801ix_lpc_setup(); |