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authorAaron Durbin <adurbin@chromium.org>2014-08-01 16:59:32 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-25 22:31:31 +0100
commit29a321dc9706b04f6ca2507a25a5dd85e32f79ac (patch)
tree87fd9e6b76cf976484e61d4d8002e2f772169c47
parentd25ead2589c47ae476975cb6c42354c3a12fb3f9 (diff)
downloadcoreboot-29a321dc9706b04f6ca2507a25a5dd85e32f79ac.tar.xz
rush: switch to padconfig API in romstage
BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran on rush like before. Change-Id: I8182051314bea1ebfed1ce5346eaa1588daa2b59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5ec4e7156ce1315c9a6bc6c5e5426cad9b0ef142 Original-Change-Id: Ied3eb82fc1eb656f92875cf4a508de16fb1bc65b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210839 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/rush/romstage.c72
1 files changed, 26 insertions, 46 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index b4d9714699..dae26efbce 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -21,64 +21,44 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
+#include <soc/padconfig.h>
#include <soc/nvidia/tegra/i2c.h>
-#include <soc/nvidia/tegra132/pinmux.h>
-#include <soc/nvidia/tegra132/gpio.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
-static void configure_tpm_i2c_bus(void)
+static const struct pad_config padcfgs[] = {
+ /* SOC_WARM_RESET_L */
+ PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
+ /* TPM I2C */
+ PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+ /* EC on SPI1: mosi, miso, clk, cs */
+ PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_NXT, PINMUX_INPUT_ENABLE, SPI1),
+ PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
+};
+
+static void configure_clocks(void)
{
- clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
-
- i2c_init(2);
-}
+ /* EC on SPI1 controller. */
+ clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
+ clock_configure_source(sbc1, CLK_M, 500);
-static void mainboard_init_tpm_i2c(void)
-{
+ /* TPM on I2C3 controller */
clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
-
- gpio_output(GPIO(I5), 1);
-
- // I2C3 (cam) clock.
- pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
- PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
- // I2C3 (cam) data.
- pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
- PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
-
-
- configure_tpm_i2c_bus();
+ clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
}
-static void mainboard_init_ec_spi(void)
+void romstage_mainboard_init(void)
{
- clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
-
- // SPI1 MOSI
- pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
- PINMUX_PULL_NONE |
- PINMUX_INPUT_ENABLE);
- // SPI1 MISO
- pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
- PINMUX_PULL_NONE |
- PINMUX_INPUT_ENABLE);
- // SPI1 SCLK
- pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
- PINMUX_PULL_NONE |
- PINMUX_INPUT_ENABLE);
- // SPI1 CS0
- pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
- PINMUX_PULL_NONE |
- PINMUX_INPUT_ENABLE);
+ configure_clocks();
- clock_configure_source(sbc1, CLK_M, 500);
-}
+ /* Bring up controller interfaces for ramstage loading. */
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
-void romstage_mainboard_init(void)
-{
- mainboard_init_tpm_i2c();
- mainboard_init_ec_spi();
+ /* TPM I2C bus */
+ i2c_init(2);
}
void mainboard_configure_pmc(void)