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authorAngel Pons <th3fanbus@gmail.com>2020-01-01 19:32:06 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 10:17:57 +0000
commit2d69d594de86077e4d98b7ffbc29b24e547faaa9 (patch)
tree2103137ebd8c0657dc85435b3e9fc620864a9fe2
parent92e000cfffd36c2d608326653d172fb1886952f2 (diff)
downloadcoreboot-2d69d594de86077e4d98b7ffbc29b24e547faaa9.tar.xz
mb/asus/p5ql-em/devicetree.cb: Do minor fixes
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode. Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/mainboard/asus/p5ql-em/devicetree.cb5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb
index fd0b1034af..ab9860b16a 100644
--- a/src/mainboard/asus/p5ql-em/devicetree.cb
+++ b/src/mainboard/asus/p5ql-em/devicetree.cb
@@ -18,7 +18,7 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0 on end
end
chip cpu/intel/model_1067x # CPU
- device lapic 0xACAC off end
+ device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
@@ -41,10 +41,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
- # Set AHCI mode.
register "sata_port_map" = "0x3f"
- register "sata_clock_request" = "0"
- register "sata_traffic_monitor" = "0"
# Enable PCIe ports 0,1,3,4,5 as slots.
register "pcie_slot_implemented" = "0x3b"