mb/hp: Add HP EliteBook Folio 9480mhp820g1

18 files changed, 512 insertions, 0 deletions

diff --git a/Documentation/mainboard/hp/9480m.md b/Documentation/mainboard/hp/9480m.md
new file mode 100644
index 0000000000..3fe733b91e
--- /dev/null
+++ b/Documentation/mainboard/hp/9480m.md
@@ -0,0 +1,92 @@
+# HP EliteBook Folio 9480m
+
+This page is about the notebook [HP EliteBook Folio 9480m].
+
+## Release status
+
+HP EliteBook Folio 9480m was released in 2013 and is now end of life.
+It can be bought from a secondhand market like Taobao or eBay.
+
+## Required proprietary blobs
+
+The following blobs are required to operate the hardware:
+1. EC firmware
+2. Intel ME firmware
+3. mrc.bin
+
+HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller.
+The EC firmware is stored in the flash chip, but we don't need to touch it,
+and we don't need it when building coreboot.
+
+Intel ME firmware is in the flash chip. It is not needed when building coreboot.
+
+The Haswell memory reference code binary (mrc.bin) is needed when building coreboot.
+We need to extract one from a Haswell Chromebook.
+
+## Programming
+
+HP EliteBook Folio 9480m has two flash chips. According to the strings found in the
+EC firmware, the 16MB chip which stores the BIOS image is called the system flash,
+and the 2MB chip which stores part of the system flash content is called the
+private flash.
+
+Before flashing, remove the battery and the hard drive cover.
+
+(TBD: pictures needed)
+
+To access the system flash. We need to connect the AC adapter to the machine,
+then clip on the flash chip with an SOIC-8 clip. If the programmer still cannot
+find the flash chip, you can first clip on the chip with the flash programmer
+disconnected with the host machine, plug in the AC adapter, then connect the
+programmer with the host machine. An [STM32-based flash programmer] is tested to work.
+
+To access the private flash chip. You can use a ch341a based flash programmer with
+the AC adapter disconnected.
+
+The firmware of this laptop is protected by [HP Sure Start]. We need to bypass
+this protection by doing the following:
+
+1. Erase the private flash, so the IFD protection will be disabled
+2. Modify the IFD to shrink the BIOS region, so that we'll not use or override
+   the protected bootblock and PEI region
+
+It works with the flash chip size set to 12MB in coreboot configuration, and the
+following flash layout in the modified IFD:
+
+  00000000:00000fff fd
+  00600000:00bfffff bios
+  00003000:005fffff me
+  00001000:00002fff gbe
+
+## Debugging
+
+The board can be debugged with EHCI debug. The EHCI debug port is the left USB port.
+
+## Test status
+
+(TBD...)
+
+- libgfxinit
+- SeaBIOS payload
+- SATA and M.2 SATA disk
+- EC firmware version XXX from OEM firmware version XXX
+- mrc.bin version 1.6.1 Build 2
+
+## Technology
+
+```eval_rst
++------------------+-----------------------------+
+| CPU              | Intel Haswell-ULT           |
++------------------+-----------------------------+
+| PCH              | Intel Lynx Point Low Power  |
++------------------+-----------------------------+
+| EC               | SMSC MEC1322                |
++------------------+-----------------------------+
+| Coprocessor      | Intel Management Engine     |
++------------------+-----------------------------+
+```
+
+[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
+[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980
+[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
+[HP Sure Start]: http://h10032.www1.hp.com/ctg/Manual/c05163901
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 0eefee82ab..511da27ba6 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -63,6 +63,7 @@ The boards in this section are not real mainboards, but emulators.
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
+- [EliteBook Folio 9480m](hp/9480m.md)
 
 ## Intel
 
diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig
new file mode 100644
index 0000000000..79267749f1
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/Kconfig
@@ -0,0 +1,39 @@
+if BOARD_HP_FOLIO_9480M
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select EC_HP_KBC1126
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_INT15
+	select INTEL_LYNXPOINT_LP
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM1
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_DIR
+	string
+	default "hp/folio_9480m"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "HP EliteBook Folio 9480m"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0a16.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,0a16"
+
+config USBDEBUG_HCD_INDEX
+	int
+	default 1
+
+endif
diff --git a/src/mainboard/hp/folio_9480m/Kconfig.name b/src/mainboard/hp/folio_9480m/Kconfig.name
new file mode 100644
index 0000000000..67c671d4c2
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_FOLIO_9480M
+	bool "EliteBook Folio 9480m"
diff --git a/src/mainboard/hp/folio_9480m/Makefile.inc b/src/mainboard/hp/folio_9480m/Makefile.inc
new file mode 100644
index 0000000000..fa23791fc1
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/Makefile.inc
@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/folio_9480m/acpi/ec.asl b/src/mainboard/hp/folio_9480m/acpi/ec.asl
new file mode 100644
index 0000000000..f7d06f194b
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/acpi/ec.asl
@@ -0,0 +1,7 @@
+Device(EC)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 0)
+	Name (_GPE, 6)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/hp/folio_9480m/acpi/platform.asl b/src/mainboard/hp/folio_9480m/acpi/platform.asl
new file mode 100644
index 0000000000..6e6cac04f5
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/acpi/platform.asl
@@ -0,0 +1,10 @@
+Method(_WAK, 1)
+{
+	/* FIXME: EC support  */
+	Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+	/* FIXME: EC support  */
+}
diff --git a/src/mainboard/hp/folio_9480m/acpi/superio.asl b/src/mainboard/hp/folio_9480m/acpi/superio.asl
new file mode 100644
index 0000000000..f2b35ba9c1
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/hp/folio_9480m/acpi_tables.c b/src/mainboard/hp/folio_9480m/acpi_tables.c
new file mode 100644
index 0000000000..00963e10b0
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/acpi_tables.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <southbridge/intel/lynxpoint/nvs.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->lids = 1;
+
+	/* Temperature at which OS will shutdown */
+	gnvs->tcrt = 100;
+	/* Temperature at which OS will throttle CPU */
+	gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/hp/folio_9480m/board_info.txt b/src/mainboard/hp/folio_9480m/board_info.txt
new file mode 100644
index 0000000000..cdbf8b838a
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/board_info.txt
@@ -0,0 +1,4 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+FIXME: put ROM package, ROM socketed, Release year
diff --git a/src/mainboard/hp/folio_9480m/bootblock.c b/src/mainboard/hp/folio_9480m/bootblock.c
new file mode 100644
index 0000000000..a51943c3dd
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/bootblock.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/hp/kbc1126/ec.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_superio(void)
+{
+	kbc1126_enter_conf();
+	kbc1126_mailbox_init();
+	kbc1126_kbc_init();
+	kbc1126_ec_init();
+	kbc1126_pm1_init();
+	kbc1126_exit_conf();
+	// kbc1126_disable4e();
+}
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb
new file mode 100644
index 0000000000..72a4564e3c
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/devicetree.cb
@@ -0,0 +1,81 @@
+chip northbridge/intel/haswell # FIXME: usb_xhci_on_resume
+	register "dq_pins_interleaved" = "true"
+	register "ec_present" = "true"
+	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+	register "gpu_ddi_e_connected" = "0"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	register "gpu_panel_power_backlight_off_delay" = "1"
+	register "gpu_panel_power_backlight_on_delay" = "1"
+	register "gpu_panel_power_cycle_delay" = "6"
+	register "gpu_panel_power_down_delay" = "500"
+	register "gpu_panel_power_up_delay" = "2000"
+	register "gpu_pch_backlight_pwm_hz" = "200"
+	register "usb_xhci_on_resume" = "false"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/haswell
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0x0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0x0 on
+		subsystemid 0x103c 0x22da inherit
+		device pci 00.0 on end # Host bridge
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 03.0 on end # Mini-HD audio
+
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "docking_supported" = "0"
+			register "gen1_dec" = "0x007c0201"
+			register "gen2_dec" = "0x000c0101"
+			register "gen4_dec" = "0x000402e9"
+			register "sata_ahci" = "1"
+			register "sata_port_map" = "0xa"
+			device pci 14.0 on  end # xHCI Controller
+			device pci 15.0 off end # Serial I/O DMA
+			device pci 15.1 off end # I2C0
+			device pci 15.2 off end # I2C1
+			device pci 15.3 off end # GSPI0
+			device pci 15.4 off end # GSPI1
+			device pci 15.5 off end # UART0
+			device pci 15.6 off end # UART1
+			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 on  end # Intel Gigabit Ethernet
+			device pci 1b.0 on  end # High Definition Audio
+			device pci 1c.0 on  end # PCIe Port #1
+			device pci 1c.1 on  end # PCIe Port #2, Realtek Card Reader
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 on  end # PCIe Port #4, WLAN
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1d.0 on  end # USB2 EHCI #1
+			device pci 1f.0 on      # LPC bridge
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+				# This laptop uses MEC1322, but it has the same interface
+				# as the KBC1126 laptops
+				chip ec/hp/kbc1126
+					register "ec_data_port" = "0x62"
+					register "ec_cmd_port"  = "0x66"
+					register "ec_ctrl_reg"  = "0x81"
+					register "ec_fan_ctrl_value" = "0x6b"
+					device pnp ff.1 off end
+				end
+			end
+			device pci 1f.2 on  end # SATA Controller (AHCI)
+			device pci 1f.3 on  end # SMBus
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/hp/folio_9480m/dsdt.asl b/src/mainboard/hp/folio_9480m/dsdt.asl
new file mode 100644
index 0000000000..9de1c543e9
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/dsdt.asl
@@ -0,0 +1,27 @@
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI 2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	/* OEM revision */
+)
+{
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/haswell.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/hp/folio_9480m/gma-mainboard.ads b/src/mainboard/hp/folio_9480m/gma-mainboard.ads
new file mode 100644
index 0000000000..8eea59a449
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   -- FIXME: check this
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/folio_9480m/gpio.c b/src/mainboard/hp/folio_9480m/gpio.c
new file mode 100644
index 0000000000..3ad465a78f
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/gpio.c
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
+
+const struct pch_lp_gpio_map mainboard_gpio_map[] = {
+	[0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[2] = LP_GPIO_OUT_LOW,
+	[3] = LP_GPIO_OUT_HIGH,
+	[4] = LP_GPIO_OUT_HIGH,
+	[5] = LP_GPIO_OUT_HIGH,
+	[6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[8] = LP_GPIO_OUT_HIGH,
+	[9] = LP_GPIO_OUT_HIGH,
+	[10] = LP_GPIO_OUT_HIGH,
+	[11] = LP_GPIO_OUT_HIGH,
+	[12] = LP_GPIO_NATIVE,
+	[13] = LP_GPIO_OUT_HIGH,
+	[14] = LP_GPIO_OUT_HIGH,
+	[15] = LP_GPIO_OUT_HIGH,
+	[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI },
+	[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[18] = LP_GPIO_OUT_HIGH,
+	[19] = LP_GPIO_NATIVE,
+	[20] = LP_GPIO_NATIVE,
+	[21] = LP_GPIO_NATIVE,
+	[22] = LP_GPIO_OUT_HIGH,
+	[23] = LP_GPIO_OUT_HIGH,
+	[24] = LP_GPIO_OUT_HIGH,
+	[25] = LP_GPIO_OUT_HIGH,
+	[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[28] = LP_GPIO_OUT_HIGH,
+	[29] = LP_GPIO_OUT_HIGH,
+	[30] = LP_GPIO_NATIVE,
+	[31] = LP_GPIO_NATIVE,
+	[32] = LP_GPIO_NATIVE,
+	[33] = LP_GPIO_NATIVE,
+	[34] = LP_GPIO_OUT_HIGH,
+	[35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI },
+	[37] = LP_GPIO_NATIVE,
+	[38] = LP_GPIO_NATIVE,
+	[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
+		 .route = GPIO_ROUTE_SMI },
+	[40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
+		 .route = GPIO_ROUTE_SMI },
+	[41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[43] = LP_GPIO_OUT_HIGH,
+	[44] = LP_GPIO_OUT_LOW,
+	[45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
+	[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[47] = LP_GPIO_OUT_HIGH,
+	[48] = LP_GPIO_OUT_LOW,
+	[49] = LP_GPIO_OUT_HIGH,
+	[50] = LP_GPIO_OUT_HIGH,
+	[51] = LP_GPIO_OUT_HIGH,
+	[52] = LP_GPIO_OUT_HIGH,
+	[53] = LP_GPIO_OUT_HIGH,
+	[54] = LP_GPIO_OUT_LOW,
+	[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
+		 .pirq = GPIO_PIRQ_APIC_ROUTE },
+	[56] = LP_GPIO_OUT_HIGH,
+	[57] = LP_GPIO_OUT_LOW,
+	[58] = LP_GPIO_OUT_HIGH,
+	[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[60] = LP_GPIO_OUT_HIGH,
+	[61] = LP_GPIO_OUT_LOW,
+	[62] = LP_GPIO_NATIVE,
+	[63] = LP_GPIO_NATIVE,
+	[64] = LP_GPIO_OUT_HIGH,
+	[65] = LP_GPIO_OUT_LOW,
+	[66] = LP_GPIO_OUT_HIGH,
+	[67] = LP_GPIO_OUT_HIGH,
+	[68] = LP_GPIO_OUT_HIGH,
+	[69] = LP_GPIO_OUT_HIGH,
+	[70] = LP_GPIO_OUT_LOW,
+	[71] = LP_GPIO_NATIVE,
+	[72] = LP_GPIO_NATIVE,
+	[73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[74] = LP_GPIO_NATIVE,
+	[75] = LP_GPIO_NATIVE,
+	[76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI },
+	[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[80] = LP_GPIO_OUT_LOW,
+	[81] = LP_GPIO_NATIVE,
+	[82] = LP_GPIO_OUT_HIGH,
+	[83] = LP_GPIO_OUT_HIGH,
+	[84] = LP_GPIO_OUT_HIGH,
+	[85] = LP_GPIO_OUT_HIGH,
+	[86] = LP_GPIO_OUT_HIGH,
+	[87] = LP_GPIO_OUT_HIGH,
+	[88] = LP_GPIO_OUT_HIGH,
+	[89] = LP_GPIO_OUT_HIGH,
+	[90] = LP_GPIO_OUT_HIGH,
+	[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
+	[94] = LP_GPIO_OUT_HIGH,
+	LP_GPIO_END
+};
diff --git a/src/mainboard/hp/folio_9480m/hda_verb.c b/src/mainboard/hp/folio_9480m/hda_verb.c
new file mode 100644
index 0000000000..fee9c3e67f
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0280,	/* Codec Vendor / Device ID: Realtek */
+	0x103c22db,	/* Subsystem ID */
+	13,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c22db),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40738105),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/folio_9480m/mainboard.c b/src/mainboard/hp/folio_9480m/mainboard.c
new file mode 100644
index 0000000000..7c8903efaa
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/mainboard.c
@@ -0,0 +1,13 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
+					GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c
new file mode 100644
index 0000000000..e970100e77
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/romstage.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+	RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA);
+	RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC);
+	RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
+	RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
+	RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
+	RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD);
+	RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+	RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+}
+
+/* FIXME: called after romstage_common, remove it if not used */
+void mb_late_romstage_setup(void)
+{
+}
+
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+	spd_map[0] = 0xa0;
+	spd_map[2] = 0xa4;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
+		/* Length, Enable, OCn#, Location */
+		{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE },
+		{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+		{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+		{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE },
+		{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE },
+		{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE },
+		{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+		{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+	};
+	struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
+		{ 1, USB_OC_PIN_SKIP },
+		{ 1, USB_OC_PIN_SKIP },
+		{ 1, USB_OC_PIN_SKIP },
+		{ 0, USB_OC_PIN_SKIP },
+	};
+	memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
+	memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
+}