diff options
| author | Taniya Das <tdas@codeaurora.org> | 2020-09-03 23:08:31 +0530 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-09-15 01:07:27 +0000 |
| commit | 4236187deaebcd86c675965d1967908e1ebb1d54 (patch) | |
| tree | dbfa50d75a041741506475ca381318bdee090f10 | |
| parent | dcf80ab0251fca4cfd3da1d5850333c64a311e45 (diff) | |
| download | coreboot-4236187deaebcd86c675965d1967908e1ebb1d54.tar.xz | |
sc7180: clock: Remove unwanted QUPv3 Frequency
As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.
Tested: Compile and boot up testing.
Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
| -rw-r--r-- | src/soc/qualcomm/sc7180/clock.c | 8 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/clock.h | 1 |
2 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 3702fa6ed4..919735d7d6 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -12,14 +12,6 @@ struct clock_config qup_cfg[] = { { - .hz = QUPV3_UART_SRC_HZ, - .src = SRC_GPLL0_EVEN_300MHZ, - .div = DIV(1), - .m = 384, - .n = 15625, - .d_2 = 15625, - }, - { .hz = SRC_XO_HZ, /* 19.2KHz */ .src = SRC_XO_19_2MHZ, .div = DIV(1), diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index c9ecfb2a1f..62e2a34174 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -20,7 +20,6 @@ #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) -#define QUPV3_UART_SRC_HZ 7372800 #define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1 |