summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChris Wang <chris.wang@amd.corp-partner.google.com>2020-10-05 13:39:14 +0800
committerEdward O'Callaghan <quasisec@chromium.org>2020-10-08 01:30:36 +0000
commit5ec975e31a2c4f6bc11cdc811811dd58e10b52ac (patch)
tree744bf23511b5aadda51727da6d493640e9fc3a06
parent806554237b819ac548f3206d1864524e81df8378 (diff)
downloadcoreboot-5ec975e31a2c4f6bc11cdc811811dd58e10b52ac.tar.xz
soc/amd/picasso: Remove xhci0_force_gen1 from soc config
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead. The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1. Now variant can use the usb3_port_force_gen1 to customize which port it needs to limit. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb2
-rw-r--r--src/soc/amd/picasso/chip.h3
-rw-r--r--src/soc/amd/picasso/fsp_params.c1
4 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index ae712ee2be..cbb812d220 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -54,8 +54,6 @@ chip soc/amd/picasso
.init_khz_preset = 1,
}"
- register "xhci0_force_gen1" = "0"
-
register "has_usb2_phy_tune_params" = "1"
# Controller0 Port0 Default
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 69179ece13..7288d6e32d 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -54,8 +54,6 @@ chip soc/amd/picasso
.init_khz_preset = 1,
}"
- register "xhci0_force_gen1" = "0"
-
register "has_usb2_phy_tune_params" = "1"
# Controller0 Port0 Default
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index f4233de2ce..3098a817a7 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -201,8 +201,7 @@ struct soc_amd_picasso_config {
*/
uint16_t init_khz_preset;
} emmc_config;
- /* set xhci0 from gen2 to gen1 */
- uint8_t xhci0_force_gen1;
+
/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
union usb3_force_gen1 usb3_port_force_gen1;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 973bb87d49..a08a209bc1 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -110,7 +110,6 @@ static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
/* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */
ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);
- scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en;
if (cfg->has_usb2_phy_tune_params) {