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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-10 22:51:15 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-13 19:39:27 +0000 |
| commit | 651d5214d25641052a757e3f6eec75e4a1af9f9c (patch) | |
| tree | 9b80785417ba0a135c830a3a22b21ba3f196e471 | |
| parent | ec8eef0a6b4d29d5a9bf60476b77ffd05eb32860 (diff) | |
| download | coreboot-651d5214d25641052a757e3f6eec75e4a1af9f9c.tar.xz | |
mb/clevo/cml-u: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entry from clevo/cml-u, which
has been forgotten in commit c5f1dc9.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I05844db4cfe96e6075bd6526ffc242973a2082c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
| -rw-r--r-- | src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 05f2a5670c..59389343b5 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -184,14 +184,12 @@ chip soc/intel/cannonlake device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x80 - 0x8F (Port 80) - register "gen1_dec" = "0x000c0081" # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) - register "gen2_dec" = "0x00040069" + register "gen1_dec" = "0x00040069" # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen3_dec" = "0x00fc0e01" + register "gen2_dec" = "0x00fc0e01" # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen4_dec" = "0x00fc0f01" + register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end |