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authorAshwin Kumar <ashk@codeaurora.org>2019-10-21 11:17:24 +0530
committerJulius Werner <jwerner@chromium.org>2020-09-09 22:08:34 +0000
commit6856ae468e7763026823b59098bb4ec55d165dbb (patch)
tree9b615d496b1036cd465dc9b3f09aad124cc26b33
parent32aed01c6a97d3ef53afbd22a1bff52ee6cc3061 (diff)
downloadcoreboot-6856ae468e7763026823b59098bb4ec55d165dbb.tar.xz
trogdor: Change Memlayout to increase QcLib region from 512 to 596kB
Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/soc/qualcomm/sc7180/memlayout.ld8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld
index 2a0cd8a417..94300e81a5 100644
--- a/src/soc/qualcomm/sc7180/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/memlayout.ld
@@ -40,10 +40,10 @@ SECTIONS
REGION(qclib_serial_log, 0x14852000, 4K, 4K)
REGION(ddr_information, 0x14853000, 1K, 1K)
FMAP_CACHE(0x14853400, 2K)
- REGION(dcb, 0x14870000, 16K, 4K)
- REGION(pmic, 0x14874000, 44K, 4K)
- REGION(limits_cfg, 0x1487F000, 4K, 4K)
- REGION(qclib, 0x14880000, 512K, 4K)
+ REGION(dcb, 0x1485b000, 16K, 4K)
+ REGION(pmic, 0x1485f000, 44K, 4K)
+ REGION(limits_cfg, 0x1486a000, 4K, 4K)
+ REGION(qclib, 0x1486b000, 596K, 4K)
BSRAM_END(0x14900000)
DRAM_START(0x80000000)