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authorStefan Reinauer <stepan@coresystems.de>2009-03-15 10:04:41 +0000
committerStefan Reinauer <stepan@openbios.org>2009-03-15 10:04:41 +0000
commit6d07c932bb5258b10ce76c48ff2a7475da19fd85 (patch)
tree99723557aeb3bd23c6c33c95eb981b5af95c7f4b
parent8f556be7668889d3a7fc2418ffcadbe7af99fb77 (diff)
downloadcoreboot-6d07c932bb5258b10ce76c48ff2a7475da19fd85.tar.xz
Fix all build problems on PPC except the _SDA_BASE issues caused by the
code expecting too old binutils(?). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/arch/ppc/include/arch/pci_ops.h2
-rw-r--r--src/arch/ppc/include/arch/pciconf.h12
-rw-r--r--src/include/boot/elf.h8
-rw-r--r--src/mainboard/totalimpact/briq/Options.lb1
-rw-r--r--src/mainboard/totalimpact/briq/init.c1
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_pci.c2
6 files changed, 15 insertions, 11 deletions
diff --git a/src/arch/ppc/include/arch/pci_ops.h b/src/arch/ppc/include/arch/pci_ops.h
index 95f8941e42..4d40578625 100644
--- a/src/arch/ppc/include/arch/pci_ops.h
+++ b/src/arch/ppc/include/arch/pci_ops.h
@@ -1,6 +1,6 @@
#ifndef ARCH_PPC_PCI_OPS_H
#define ARCH_PPC_PCI_OPS_H
-const struct pci_bus_operations pci_ppc_conf1;
+extern const struct pci_bus_operations pci_ppc_conf1;
#endif /* ARCH_PPC_PCI_OPS_H */
diff --git a/src/arch/ppc/include/arch/pciconf.h b/src/arch/ppc/include/arch/pciconf.h
index d210e3b445..790a6bac65 100644
--- a/src/arch/ppc/include/arch/pciconf.h
+++ b/src/arch/ppc/include/arch/pciconf.h
@@ -4,12 +4,12 @@
/*
* Direct access to PCI hardware...
*/
-extern uint8_t pci_ppc_read_config8(unsigned char, int, int);
-extern uint16_t pci_ppc_read_config16(unsigned char, int, int);
-extern uint32_t pci_ppc_read_config32(unsigned char, int, int);
-extern int pci_ppc_write_config8(unsigned char, int, int, uint8_t);
-extern int pci_ppc_write_config16(unsigned char, int, int, uint16_t);
-extern int pci_ppc_write_config32(unsigned char, int, int, uint32_t);
+uint8_t pci_ppc_read_config8(unsigned char, int, int);
+uint16_t pci_ppc_read_config16(unsigned char, int, int);
+uint32_t pci_ppc_read_config32(unsigned char, int, int);
+int pci_ppc_write_config8(unsigned char, int, int, uint8_t);
+int pci_ppc_write_config16(unsigned char, int, int, uint16_t);
+int pci_ppc_write_config32(unsigned char, int, int, uint32_t);
#define CONFIG_CMD(bus,devfn,where) \
((bus << 16) | (devfn << 8) | (where & ~3) | 0x80000000)
diff --git a/src/include/boot/elf.h b/src/include/boot/elf.h
index 36ad670d4c..98818aee79 100644
--- a/src/include/boot/elf.h
+++ b/src/include/boot/elf.h
@@ -389,10 +389,12 @@ typedef Elf64_Ehdr Elf_ehdr;
typedef Elf64_Phdr Elf_phdr;
#endif
-extern int elf_check_arch(Elf_ehdr *ehdr);
-extern void jmp_to_elf_entry(void *entry, unsigned long buffer);
+int elf_check_arch(Elf_ehdr *ehdr);
+void jmp_to_elf_entry(void *entry, unsigned long buffer);
struct lb_memory;
-extern int elfboot(struct lb_memory *mem);
+int elfboot(struct lb_memory *mem);
+/* Temporary compile fix, FILO should be dropped from coreboot */
+int filo(struct lb_memory *mem);
#define FIRMWARE_TYPE "coreboot"
#define BOOTLOADER "elfboot"
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb
index f3a08afd6b..c8fbfdc0f5 100644
--- a/src/mainboard/totalimpact/briq/Options.lb
+++ b/src/mainboard/totalimpact/briq/Options.lb
@@ -11,7 +11,6 @@ uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses _IO_BASE
-uses CROSS_COMPILE
uses HAVE_OPTION_TABLE
uses CONFIG_COMPRESS
uses DEFAULT_CONSOLE_LOGLEVEL
diff --git a/src/mainboard/totalimpact/briq/init.c b/src/mainboard/totalimpact/briq/init.c
index fcdaba2317..fd9283d37a 100644
--- a/src/mainboard/totalimpact/briq/init.c
+++ b/src/mainboard/totalimpact/briq/init.c
@@ -28,6 +28,7 @@
#include <ppc.h>
#include <arch/io.h>
#include <console/console.h>
+#include <uart8250.h>
void
board_init(void)
diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c
index b9820e5ab3..233e119baf 100644
--- a/src/northbridge/ibm/cpc710/cpc710_pci.c
+++ b/src/northbridge/ibm/cpc710/cpc710_pci.c
@@ -1,5 +1,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <arch/pciconf.h>
+#include <delay.h>
#include "cpc710.h"
#include "cpc710_pci.h"