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authorFurquan Shaikh <furquan@google.com>2020-06-23 11:11:30 -0700
committerFurquan Shaikh <furquan@google.com>2020-07-01 17:54:43 +0000
commit7340efcf1998e4197bb2403657efed16e5e4e620 (patch)
tree1ab71d2b3d600f2799202134400891f73e061c6a
parent1247616304ebf9a8839a6808be2f12912b1d98f8 (diff)
downloadcoreboot-7340efcf1998e4197bb2403657efed16e5e4e620.tar.xz
mb/google/zork: Configure GPIO_40 as drive low in sleep path
This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in sleep path so that the PERST# to NVMe device keeps asserted until coreboot reconfigures it as high on S3 resume path. This is similar to the earlier change for PCIE_RST1_L but helps platforms that use NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain, hence it retains state across S3 entry/exit. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie79e946eee8f393863630226ae2183e653030415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index 1dd2dd5b89..aacf14b7c5 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -36,6 +36,8 @@ static const struct soc_amd_gpio gpio_sleep_table[] = {
PAD_GPO(GPIO_5, LOW),
/* PCIE_RST1_L */
PAD_GPO(GPIO_27, LOW),
+ /* NVME_AUX_RESET_L */
+ PAD_GPO(GPIO_40, LOW),
/* EN_PWR_CAMERA */
PAD_GPO(GPIO_76, LOW),
};