soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO

Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.

Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

5 files changed, 163 insertions, 164 deletions

diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
index 1fa144f580..9df1cf7d42 100644
--- a/src/soc/intel/cannonlake/acpi/gpio.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -80,7 +80,7 @@ Method (GADD, 1, NotSerialized)
 		Subtract (Arg0, GPP_A0, Local1)
 	}
 	/* GPIO Community 1 */
-	If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))
+	If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, vSD3_CD_B)))
 	{
 		Store (PID_GPIOCOM1, Local0)
 		Subtract (Arg0, GPP_D0, Local1)
@@ -92,13 +92,13 @@ Method (GADD, 1, NotSerialized)
 		Subtract (Arg0, GPD0, Local1)
 	}
 	/* GPIO Community 3 */
-	If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))
+	If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38)))
 	{
 		Store (PID_GPIOCOM1, Local0)
 		Subtract (Arg0, HDA_BCLK, Local1)
 	}
 	/* GPIO Community 04*/
-	If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))
+	If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_27)))
 	{
 		Store (PID_GPIOCOM4, Local0)
 		Subtract (Arg0, GPP_C0, Local1)
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index 701eb0bf4e..30ee9398d5 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -56,7 +56,7 @@ static const struct pad_group cnl_community1_groups[] = {
 	INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96),	/* GPP_D */
 	INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128),		/* GPP_F */
 	INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160),		/* GPP_H */
-	INTEL_GPP_BASE(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52, 192),/* VGPIO */
+	INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192),	/* VGPIO */
 };
 
 /* This community is not visible to the OS */
@@ -67,14 +67,14 @@ static const struct pad_group cnl_community2_groups[] = {
 /* This community is not visible to the OS */
 static const struct pad_group cnl_community3_groups[] = {
 	INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD),		/* AZA */
-	INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78),	/* CPU */
+	INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38),	/* CPU */
 };
 
 static const struct pad_group cnl_community4_groups[] = {
 	INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),		/* GPP_C */
 	INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288),		/* GPP_E */
-	INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61),		/* JTAG */
-	INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67),		/* HVMOS */
+	INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21),		/* JTAG */
+	INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27),		/* HVMOS */
 };
 
 static const struct pad_community cnl_communities[] = {
@@ -97,7 +97,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* GPP D, F, H, VGPIO */
 		.port = PID_GPIOCOM1,
 		.first_pad = GPP_D0,
-		.last_pad = GPIO_RSVD_52,
+		.last_pad = vSD3_CD_B,
 		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -129,7 +129,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* AZA, CPU */
 		.port = PID_GPIOCOM3,
 		.first_pad = HDA_BCLK,
-		.last_pad = GPIO_RSVD_78,
+		.last_pad = GPIO_RSVD_38,
 		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -145,7 +145,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* GPP C, E, JTAG, HVMOS */
 		.port = PID_GPIOCOM4,
 		.first_pad = GPP_C0,
-		.last_pad = GPIO_RSVD_67,
+		.last_pad = GPIO_RSVD_27,
 		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
index f0fc79dccb..d59dea5cbc 100644
--- a/src/soc/intel/cannonlake/gpio_cnp_h.c
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -55,8 +55,8 @@ static const struct pad_group cnl_community1_groups[] = {
 	INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96),		/* GPP_D */
 	INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128),		/* GPP_G */
 	INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10),		/* AZA */
-	INTEL_GPP_BASE(GPP_C0, GPIO_RSVD_11, GPIO_RSVD_42, 160),/* VGPIO_0 */
-	INTEL_GPP(GPP_C0, GPIO_RSVD_43, GPIO_RSVD_50),		/* VGPIO_0 */
+	INTEL_GPP_BASE(GPP_C0, CNV_BTEN, vISH_UART1_RTS_B, 160),/* VGPIO_0 */
+	INTEL_GPP(GPP_C0, vCNV_BT_I2S_BCLK, vSSP2_RXD),		/* VGPIO_1 */
 };
 
 /* This community is not visible to the OS */
@@ -69,14 +69,14 @@ static const struct pad_group cnl_community3_groups[] = {
 	INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224),		/* GPP_H */
 	INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256),		/* GPP_E */
 	INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288),		/* GPP_F */
-	INTEL_GPP(GPP_K0, GPIO_RSVD_51, GPIO_RSVD_59),		/* SPI */
+	INTEL_GPP(GPP_K0, GPIO_RSVD_11, GPIO_RSVD_19),		/* SPI */
 };
 
 static const struct pad_group cnl_community4_groups[] = {
-	INTEL_GPP(GPIO_RSVD_60, GPIO_RSVD_60, GPIO_RSVD_70),	/* CPU */
-	INTEL_GPP(GPIO_RSVD_60, GPIO_RSVD_71, GPIO_RSVD_79),	/* JTAG */
-	INTEL_GPP_BASE(GPIO_RSVD_60, GPP_I0, GPP_I14, 320),	/* GPP_I */
-	INTEL_GPP_BASE(GPIO_RSVD_60, GPP_J0, GPP_J11, 352),	/* GPP_J */
+	INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_20, GPIO_RSVD_30),	/* CPU */
+	INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_31, GPIO_RSVD_39),	/* JTAG */
+	INTEL_GPP_BASE(GPIO_RSVD_20, GPP_I0, GPP_I14, 320),	/* GPP_I */
+	INTEL_GPP_BASE(GPIO_RSVD_20, GPP_J0, GPP_J11, 352),	/* GPP_J */
 };
 
 static const struct pad_community cnl_communities[] = {
@@ -99,7 +99,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* GPP C, D, G */
 		.port = PID_GPIOCOM1,
 		.first_pad = GPP_C0,
-		.last_pad = GPIO_RSVD_50,
+		.last_pad = vSSP2_RXD,
 		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -131,7 +131,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* GPP K, H, E, F */
 		.port = PID_GPIOCOM3,
 		.first_pad = GPP_K0,
-		.last_pad = GPIO_RSVD_59,
+		.last_pad = GPIO_RSVD_19,
 		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -146,7 +146,7 @@ static const struct pad_community cnl_communities[] = {
 		.num_groups = ARRAY_SIZE(cnl_community3_groups),
 	}, { /* GPP I, J */
 		.port = PID_GPIOCOM4,
-		.first_pad = GPIO_RSVD_60,
+		.first_pad = GPIO_RSVD_20,
 		.last_pad = GPP_J11,
 		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index cb184c9b0c..5d7c0e884c 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -197,48 +197,48 @@
 #define GPP_H22			139
 #define GPP_H23			140
 /* Group VGPIO */
-#define GPIO_RSVD_13		141
-#define GPIO_RSVD_14		142
-#define GPIO_RSVD_15		143
-#define GPIO_RSVD_16		144
-#define GPIO_RSVD_17		145
-#define GPIO_RSVD_18		146
-#define GPIO_RSVD_19		147
-#define GPIO_RSVD_20		148
-#define GPIO_RSVD_21		149
-#define GPIO_RSVD_22		150
-#define GPIO_RSVD_23		151
-#define GPIO_RSVD_24		152
-#define GPIO_RSVD_25		153
-#define GPIO_RSVD_26		154
-#define GPIO_RSVD_27		155
-#define GPIO_RSVD_28		156
-#define GPIO_RSVD_29		157
-#define GPIO_RSVD_30		158
-#define GPIO_RSVD_31		159
-#define GPIO_RSVD_32		160
-#define GPIO_RSVD_33		161
-#define GPIO_RSVD_34		162
-#define GPIO_RSVD_35		163
-#define GPIO_RSVD_36		164
-#define GPIO_RSVD_37		165
-#define GPIO_RSVD_38		166
-#define GPIO_RSVD_39		167
-#define GPIO_RSVD_40		168
-#define GPIO_RSVD_41		169
-#define GPIO_RSVD_42		170
-#define GPIO_RSVD_43		171
-#define GPIO_RSVD_44		172
-#define GPIO_RSVD_45		173
-#define GPIO_RSVD_46		174
-#define GPIO_RSVD_47		175
-#define GPIO_RSVD_48		176
-#define GPIO_RSVD_49		177
-#define GPIO_RSVD_50		178
-#define GPIO_RSVD_51		179
-#define GPIO_RSVD_52		180
+#define CNV_BTEN		141
+#define CNV_GNEN		142
+#define CNV_WFEN		143
+#define CNV_WCEN		144
+#define CNV_BT_HOST_WAKEB	145
+#define CNV_BT_IF_SELECT	146
+#define vCNV_BT_UART_TXD	147
+#define vCNV_BT_UART_RXD	148
+#define vCNV_BT_UART_CTS_B	149
+#define vCNV_BT_UART_RTS_B	150
+#define vCNV_MFUART1_TXD	151
+#define vCNV_MFUART1_RXD	152
+#define vCNV_MFUART1_CTS_B	153
+#define vCNV_MFUART1_RTS_B	154
+#define vCNV_GNSS_UART_TXD	155
+#define vCNV_GNSS_UART_RXD	156
+#define vCNV_GNSS_UART_CTS_B	157
+#define vCNV_GNSS_UART_RTS_B	158
+#define vUART0_TXD		159
+#define vUART0_RXD		160
+#define vUART0_CTS_B		161
+#define vUART0_RTS_B		162
+#define vISH_UART0_TXD		163
+#define vISH_UART0_RXD		164
+#define vISH_UART0_CTS_B	165
+#define vISH_UART0_RTS_B	166
+#define vISH_UART1_TXD		167
+#define vISH_UART1_RXD		168
+#define vISH_UART1_CTS_B	169
+#define vISH_UART1_RTS_B	170
+#define vCNV_BT_I2S_BCLK	171
+#define vCNV_BT_I2S_WS_SYNC	172
+#define vCNV_BT_I2S_SDO		173
+#define vCNV_BT_I2S_SDI		174
+#define vSSP2_SCLK		175
+#define vSSP2_SFRM		176
+#define vSSP2_TXD		177
+#define vSSP2_RXD		178
+#define vCNV_GNSS_HOST_WAKEB	179
+#define vSD3_CD_B		180
 
-#define NUM_GPIO_COM1_PADS	(GPIO_RSVD_52 - GPP_D0 + 1)
+#define NUM_GPIO_COM1_PADS	(vSD3_CD_B - GPP_D0 + 1)
 
 /* Group C */
 #define GPP_C0			181
@@ -291,24 +291,24 @@
 #define GPP_E22			227
 #define GPP_E23			228
 /* Group Jtag */
-#define GPIO_RSVD_53		229
-#define GPIO_RSVD_54		230
-#define GPIO_RSVD_55		231
-#define GPIO_RSVD_56		232
-#define GPIO_RSVD_57		233
-#define GPIO_RSVD_58		234
-#define GPIO_RSVD_59		235
-#define GPIO_RSVD_60		236
-#define GPIO_RSVD_61		237
+#define GPIO_RSVD_13		229
+#define GPIO_RSVD_14		230
+#define GPIO_RSVD_15		231
+#define GPIO_RSVD_16		232
+#define GPIO_RSVD_17		233
+#define GPIO_RSVD_18		234
+#define GPIO_RSVD_19		235
+#define GPIO_RSVD_20		236
+#define GPIO_RSVD_21		237
 /* Group HVMOS */
-#define GPIO_RSVD_62		238
-#define GPIO_RSVD_63		239
-#define GPIO_RSVD_64		240
-#define GPIO_RSVD_65		241
-#define GPIO_RSVD_66		242
-#define GPIO_RSVD_67		243
+#define GPIO_RSVD_22		238
+#define GPIO_RSVD_23		239
+#define GPIO_RSVD_24		240
+#define GPIO_RSVD_25		241
+#define GPIO_RSVD_26		242
+#define GPIO_RSVD_27		243
 
-#define NUM_GPIO_COM4_PADS	(GPIO_RSVD_67 - GPP_C0 + 1)
+#define NUM_GPIO_COM4_PADS	(GPIO_RSVD_27 - GPP_C0 + 1)
 
 /* Group GPD  */
 #define GPD0			244
@@ -337,19 +337,19 @@
 #define SSP1_SFRM		262
 #define SSP1_TXD		263
 /* Group CPU */
-#define GPIO_RSVD_68		264
-#define GPIO_RSVD_69		265
-#define GPIO_RSVD_70		266
-#define GPIO_RSVD_71		267
-#define GPIO_RSVD_72		268
-#define GPIO_RSVD_73		269
-#define GPIO_RSVD_74		270
-#define GPIO_RSVD_75		271
-#define GPIO_RSVD_76		272
-#define GPIO_RSVD_77		273
-#define GPIO_RSVD_78		274
+#define GPIO_RSVD_28		264
+#define GPIO_RSVD_29		265
+#define GPIO_RSVD_30		266
+#define GPIO_RSVD_31		267
+#define GPIO_RSVD_32		268
+#define GPIO_RSVD_33		269
+#define GPIO_RSVD_34		270
+#define GPIO_RSVD_35		271
+#define GPIO_RSVD_36		272
+#define GPIO_RSVD_37		273
+#define GPIO_RSVD_38		274
 
-#define NUM_GPIO_COM3_PADS	(GPIO_RSVD_78 - HDA_BCLK + 1)
+#define NUM_GPIO_COM3_PADS	(GPIO_RSVD_38 - HDA_BCLK + 1)
 
 #define TOTAL_PADS		275
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
index 95f7e419cf..1788e78989 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -171,50 +171,49 @@
 #define GPIO_RSVD_10		114
 
 /* VGPIO_0 */
-#define GPIO_RSVD_11		115
-#define GPIO_RSVD_12		116
-#define GPIO_RSVD_13		117
-#define GPIO_RSVD_14		118
-#define GPIO_RSVD_15		119
-#define GPIO_RSVD_16		120
-#define GPIO_RSVD_17		121
-#define GPIO_RSVD_18		122
-#define GPIO_RSVD_19		123
-#define GPIO_RSVD_20		124
-#define GPIO_RSVD_21		125
-#define GPIO_RSVD_22		126
-#define GPIO_RSVD_23		127
-#define GPIO_RSVD_24		128
-#define GPIO_RSVD_25		129
-#define GPIO_RSVD_26		130
-#define GPIO_RSVD_27		131
-#define GPIO_RSVD_28		132
-#define GPIO_RSVD_29		133
-#define GPIO_RSVD_30		134
-#define GPIO_RSVD_31		135
-#define GPIO_RSVD_32		136
-#define GPIO_RSVD_33		137
-#define GPIO_RSVD_34		138
-#define GPIO_RSVD_35		139
-#define GPIO_RSVD_36		140
-#define GPIO_RSVD_37		141
-#define GPIO_RSVD_38		142
-#define GPIO_RSVD_39		143
-#define GPIO_RSVD_40		144
-#define GPIO_RSVD_41		145
-#define GPIO_RSVD_42		146
-
+#define CNV_BTEN		115
+#define CNV_GNEN		116
+#define CNV_WFEN		117
+#define CNV_WCEN		118
+#define CNV_BT_HOST_WAKEB	119
+#define vCNV_GNSS_HOST_WAKEB	120
+#define vSD3_CD_B		121
+#define CNV_BT_IF_SELECT	122
+#define vCNV_BT_UART_TXD	123
+#define vCNV_BT_UART_RXD	124
+#define vCNV_BT_UART_CTS_B	125
+#define vCNV_BT_UART_RTS_B	126
+#define vCNV_MFUART1_TXD	127
+#define vCNV_MFUART1_RXD	128
+#define vCNV_MFUART1_CTS_B	129
+#define vCNV_MFUART1_RTS_B	130
+#define vCNV_GNSS_UART_TXD	131
+#define vCNV_GNSS_UART_RXD	132
+#define vCNV_GNSS_UART_CTS_B	133
+#define vCNV_GNSS_UART_RTS_B	134
+#define vUART0_TXD		135
+#define vUART0_RXD		136
+#define vUART0_CTS_B		137
+#define vUART0_RTSB		138
+#define vISH_UART0_TXD		139
+#define vISH_UART0_RXD		140
+#define vISH_UART0_CTS_B	141
+#define vISH_UART0_RTSB		142
+#define vISH_UART1_TXD		143
+#define vISH_UART1_RXD		144
+#define vISH_UART1_CTS_B	145
+#define vISH_UART1_RTS_B	146
 /* VGPIO_1 */
-#define GPIO_RSVD_43		147
-#define GPIO_RSVD_44		148
-#define GPIO_RSVD_45		149
-#define GPIO_RSVD_46		150
-#define GPIO_RSVD_47		151
-#define GPIO_RSVD_48		152
-#define GPIO_RSVD_49		153
-#define GPIO_RSVD_50		154
+#define vCNV_BT_I2S_BCLK	147
+#define vCNV_BT_I2S_WS_SYNC	148
+#define vCNV_BT_I2S_SDO		149
+#define vCNV_BT_I2S_SDI		150
+#define vSSP2_SCLK		151
+#define vSSP2_SFRM		152
+#define vSSP2_TXD		153
+#define vSSP2_RXD		154
 
-#define NUM_GPIO_COM1_PADS	(GPIO_RSVD_50 - GPP_C0 + 1)
+#define NUM_GPIO_COM1_PADS	(vSSP2_RXD - GPP_C0 + 1)
 
 /* Group K */
 #define GPP_K0			155
@@ -310,41 +309,41 @@
 #define GPP_F23			239
 
 /* SPI */
-#define GPIO_RSVD_51		240
-#define GPIO_RSVD_52		241
-#define GPIO_RSVD_53		242
-#define GPIO_RSVD_54		243
-#define GPIO_RSVD_55		244
-#define GPIO_RSVD_56		245
-#define GPIO_RSVD_57		246
-#define GPIO_RSVD_58		247
-#define GPIO_RSVD_59		248
+#define GPIO_RSVD_11		240
+#define GPIO_RSVD_12		241
+#define GPIO_RSVD_13		242
+#define GPIO_RSVD_14		243
+#define GPIO_RSVD_15		244
+#define GPIO_RSVD_16		245
+#define GPIO_RSVD_17		246
+#define GPIO_RSVD_18		247
+#define GPIO_RSVD_19		248
 
-#define NUM_GPIO_COM3_PADS	(GPIO_RSVD_59 - GPP_K0 + 1)
+#define NUM_GPIO_COM3_PADS	(GPIO_RSVD_19 - GPP_K0 + 1)
 
 /* CPU */
-#define GPIO_RSVD_60		249
-#define GPIO_RSVD_61		250
-#define GPIO_RSVD_62		251
-#define GPIO_RSVD_63		252
-#define GPIO_RSVD_64		253
-#define GPIO_RSVD_65		254
-#define GPIO_RSVD_66		255
-#define GPIO_RSVD_67		256
-#define GPIO_RSVD_68		257
-#define GPIO_RSVD_69		258
-#define GPIO_RSVD_70		259
+#define GPIO_RSVD_20		249
+#define GPIO_RSVD_21		250
+#define GPIO_RSVD_22		251
+#define GPIO_RSVD_23		252
+#define GPIO_RSVD_24		253
+#define GPIO_RSVD_25		254
+#define GPIO_RSVD_26		255
+#define GPIO_RSVD_27		256
+#define GPIO_RSVD_28		257
+#define GPIO_RSVD_29		258
+#define GPIO_RSVD_30		259
 
 /* JTAG */
-#define GPIO_RSVD_71		260
-#define GPIO_RSVD_72		261
-#define GPIO_RSVD_73		262
-#define GPIO_RSVD_74		263
-#define GPIO_RSVD_75		264
-#define GPIO_RSVD_76		265
-#define GPIO_RSVD_77		266
-#define GPIO_RSVD_78		267
-#define GPIO_RSVD_79		268
+#define GPIO_RSVD_31		260
+#define GPIO_RSVD_32		261
+#define GPIO_RSVD_33		262
+#define GPIO_RSVD_34		263
+#define GPIO_RSVD_35		264
+#define GPIO_RSVD_36		265
+#define GPIO_RSVD_37		266
+#define GPIO_RSVD_38		267
+#define GPIO_RSVD_39		268
 
 /* Group I */
 #define GPP_I0			269
@@ -362,9 +361,9 @@
 #define GPP_I12			281
 #define GPP_I13			282
 #define GPP_I14			283
-#define GPIO_RSVD_80		284
-#define GPIO_RSVD_81		285
-#define GPIO_RSVD_82		286
+#define GPIO_RSVD_40		284
+#define GPIO_RSVD_41		285
+#define GPIO_RSVD_42		286
 
 /* Group J */
 #define GPP_J0			287