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authorArthur Heymans <arthur@aheymans.xyz>2019-04-24 12:29:44 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-04-25 15:56:28 +0000
commit74f9fe6e58f949001a34866505cecca16aa0de03 (patch)
treea46a7d5f92669425a05f8394918c1b6be1e74c91
parent5417c84f7d525d1db8f4abbf3ef4da527dd52cd6 (diff)
downloadcoreboot-74f9fe6e58f949001a34866505cecca16aa0de03.tar.xz
cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE
CPU's featuring a non eviction mode cache the whole ROM. Therefore XIP stages don't need to follow some alignment constraints. Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/cpu/intel/haswell/Kconfig1
-rw-r--r--src/cpu/intel/model_2065x/Kconfig5
-rw-r--r--src/cpu/intel/model_206ax/Kconfig5
-rw-r--r--src/cpu/intel/socket_FCBGA559/Kconfig1
-rw-r--r--src/soc/intel/broadwell/Kconfig1
5 files changed, 5 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 3fd8bb484a..5936953b52 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select PARALLEL_MP
select CPU_INTEL_COMMON
+ select NO_FIXED_XIP_ROM_SIZE
config SMM_TSEG_SIZE
hex
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 9481917ff8..ba2b7de74d 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
+ select NO_FIXED_XIP_ROM_SIZE
config BOOTBLOCK_CPU_INIT
string
@@ -28,8 +29,4 @@ config SMM_TSEG_SIZE
hex
default 0x800000
-config XIP_ROM_SIZE
- hex
- default 0x20000
-
endif
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 7f73da9ab4..f045e9aac5 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -25,15 +25,12 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select PARALLEL_MP
+ select NO_FIXED_XIP_ROM_SIZE
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"
-config XIP_ROM_SIZE
- hex
- default 0x20000 if USE_NATIVE_RAMINIT
-
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index 6566a01cf8..b1b310d3cc 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
select MMX
select SSE
select CPU_HAS_L2_ENABLE_MSR
+ select NO_FIXED_XIP_ROM_SIZE
config DCACHE_RAM_BASE
hex
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5f503da340..25984f14e2 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select POSTCAR_CONSOLE
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+ select NO_FIXED_XIP_ROM_SIZE
config PCIEXP_ASPM
bool