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authorNico Huber <nico.huber@secunet.com>2019-11-26 18:30:40 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-28 10:46:54 +0000
commit7b3e8730ee0ab81988a8a600701d644c8a014e5f (patch)
tree02149d273065456b9abfdb1664808a432bb6b518
parent693e04f5c661bfe103e42cbf99afded6478a4a4c (diff)
downloadcoreboot-7b3e8730ee0ab81988a8a600701d644c8a014e5f.tar.xz
soc/intel/skl: Drop FSP_CAR remnants
FSP-T support was abandoned long ago for Skylake. With FSP1.1 support also dropped now, it's more visible that this code is unused. Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37251 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/fspcar.c43
3 files changed, 0 insertions, 45 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 032ded4025..528fd4a0bf 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -31,7 +31,6 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_INTEL_COMMON_HYPERTHREADING
select FSP_M_XIP
- select FSP_T_XIP if FSP_CAR
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index b049e84795..c0937385f0 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
-bootblock-$(CONFIG_FSP_CAR) += fspcar.c
bootblock-y += bootblock/cpu.c
bootblock-y += i2c.c
bootblock-y += bootblock/pch.c
diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c
deleted file mode 100644
index 0d27f57698..0000000000
--- a/src/soc/intel/skylake/fspcar.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <bootblock_common.h>
-#include <FsptUpd.h>
-
-const FSPT_UPD temp_ram_init_params = {
- .FspUpdHeader = {
- .Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */
- .Revision = 1,
- .Reserved = {0},
- },
- .FsptCoreUpd = {
- /*
- * It is a requirement for firmware to have Firmware Interface Table
- * (FIT), which contains pointers to each microcode update.
- * The microcode update is loaded for all logical processors before
- * cpu reset vector.
- *
- * All SoC since Gen-4 has above mechanism in place to load microcode
- * even before hitting CPU reset vector. Hence skipping FSP-T loading
- * microcode after CPU reset by passing '0' value to
- * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
- */
- .MicrocodeRegionBase = 0,
- .MicrocodeRegionLength = 0,
- .CodeRegionBase =
- (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
- .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
- },
-};