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authorArthur Heymans <arthur@aheymans.xyz>2020-12-16 11:30:40 +0100
committerMarc Jones <marc@marcjonesconsulting.com>2020-12-16 14:58:44 +0000
commit83463076033f30c2b0693b1f39a01cfb9c679cf9 (patch)
treef879d5c9fe28c283ec8f6d9ea5459311609c15cf
parentc7b63edeb47963ae97aa3478d45aaa8f4fa0cdf0 (diff)
downloadcoreboot-83463076033f30c2b0693b1f39a01cfb9c679cf9.tar.xz
soc/intel/xeon_sp: Move DMICTL lock
On SKX FSP-M does not return if this is set too early. Tested on OCP/Tiogapass, boots. Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/xeon_sp/cpx/chip.c1
-rw-r--r--src/soc/intel/xeon_sp/include/soc/pch.h1
-rw-r--r--src/soc/intel/xeon_sp/pch.c9
-rw-r--r--src/soc/intel/xeon_sp/skx/chip.c1
4 files changed, 9 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 6beebdf925..592a316e06 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -79,6 +79,7 @@ static void chip_init(void *data)
fsp_silicon_init(false);
override_hpet_ioapic_bdf();
pch_enable_ioapic();
+ pch_lock_dmictl();
setup_lapic();
p2sb_unhide();
}
diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h
index 0be14ae966..156a22a2ba 100644
--- a/src/soc/intel/xeon_sp/include/soc/pch.h
+++ b/src/soc/intel/xeon_sp/include/soc/pch.h
@@ -10,5 +10,6 @@ void pch_disable_devfn(struct device *dev);
#endif
void override_hpet_ioapic_bdf(void);
+void pch_lock_dmictl(void);
#endif /* _SOC_PCH_H_ */
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c
index 44824ca651..d2496b12fe 100644
--- a/src/soc/intel/xeon_sp/pch.c
+++ b/src/soc/intel/xeon_sp/pch.c
@@ -40,9 +40,6 @@ static void soc_config_acpibase(void)
reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1;
pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
-
- reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
- pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
}
void bootblock_pch_init(void)
@@ -69,3 +66,9 @@ void override_hpet_ioapic_bdf(void)
p2sb_set_ioapic_bdf(ioapic_bdf);
p2sb_set_hpet_bdf(hpet_bdf);
}
+
+void pch_lock_dmictl(void)
+{
+ uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+ pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK);
+}
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 0505ea7eff..f101973864 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -45,6 +45,7 @@ static void soc_init(void *data)
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
fsp_silicon_init(false);
override_hpet_ioapic_bdf();
+ pch_lock_dmictl();
}
static void soc_final(void *data)