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authorJohn Zhao <john.zhao@intel.com>2020-07-13 09:29:33 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-28 19:24:36 +0000
commit8466ac0bae1f9ac0c1a4ded50a5a3faafd917314 (patch)
tree792e2043e46f676705fd7d11b15883427eee4b60
parent229616419d4165971fefda9a0077041e392fb64a (diff)
downloadcoreboot-8466ac0bae1f9ac0c1a4ded50a5a3faafd917314.tar.xz
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up4
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux. TEST=Built image-tglrvp-up4.bin successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb23
1 files changed, 22 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index b08cd3c119..097ae68f7d 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -254,7 +254,28 @@ chip soc/intel/tigerlake
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
- device pci 1f.2 hidden end # PMC 0xA0A1
+ device pci 1f.2 hidden # PMC 0xA0A1
+ # The pmc_mux chip driver is a placeholder for the
+ # PMC.MUX device in the ACPI hierarchy.
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "6"
+ register "usb3_port_number" = "3"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "5"
+ register "usb3_port_number" = "2"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 1 on end
+ end
+ end
+ end
+ end # PMC
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4