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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-06-27 16:14:49 +0300
committerSven Schnelle <svens@stackframe.org>2012-07-02 15:49:07 +0200
commit9ed1456eff73d1a268eabb84176dd2a2107bf2d7 (patch)
tree9811746255b0c2b168f15b76e1375d91280beb28
parentac6e3172ff7c1c11da59c488b239d08af1248503 (diff)
downloadcoreboot-9ed1456eff73d1a268eabb84176dd2a2107bf2d7.tar.xz
Intel CPUs: execute microcode update only once per core
Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/cpu/intel/hyperthreading/intel_sibling.c21
-rw-r--r--src/cpu/intel/model_f2x/model_f2x_init.c12
-rw-r--r--src/cpu/intel/model_f3x/model_f3x_init.c12
-rw-r--r--src/cpu/intel/model_f4x/model_f4x_init.c12
-rw-r--r--src/include/cpu/intel/hyperthreading.h1
5 files changed, 46 insertions, 12 deletions
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 2d2e105f8d..b9a9ae7bb1 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -14,6 +14,27 @@
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
+/* Return true if running thread does not have the smallest lapic ID
+ * within a CPU core.
+ */
+int intel_ht_sibling(void)
+{
+ unsigned int core_ids, apic_ids, threads;
+
+ apic_ids = 1;
+ if (cpuid_eax(0) >= 1)
+ apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
+ if (apic_ids < 1)
+ apic_ids = 1;
+
+ core_ids = 1;
+ if (cpuid_eax(0) >= 4)
+ core_ids += (cpuid_eax(4) >> 26) & 0x3f;
+
+ threads = (apic_ids / core_ids);
+ return !!(lapicid() & (threads-1));
+}
+
void intel_sibling_init(device_t cpu)
{
unsigned i, siblings;
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index ec78672de6..8fd8abc7bf 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -48,11 +48,15 @@ static void model_f2x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
- x86_mtrr_check();
- /* Update the microcode */
- intel_update_microcode(microcode_updates);
+ if (!intel_ht_sibling()) {
+ /* MTRRs are shared between threads */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+ }
/* Enable the local cpu apics */
setup_lapic();
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index 580c98b4d7..2504ba9423 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,11 +31,15 @@ static void model_f3x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
- x86_mtrr_check();
- /* Update the microcode */
- intel_update_microcode(microcode_updates);
+ if (!intel_ht_sibling()) {
+ /* MTRRs are shared between threads */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+ }
/* Enable the local cpu apics */
setup_lapic();
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index 54edf2e335..f3f0b2af0f 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -39,11 +39,15 @@ static void model_f4x_init(device_t cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
- x86_setup_mtrrs();
- x86_mtrr_check();
- /* Update the microcode */
- intel_update_microcode(microcode_updates);
+ if (!intel_ht_sibling()) {
+ /* MTRRs are shared between threads */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+ }
/* Enable the local cpu apics */
setup_lapic();
diff --git a/src/include/cpu/intel/hyperthreading.h b/src/include/cpu/intel/hyperthreading.h
index 0a1461ceb5..c84a6a7a4a 100644
--- a/src/include/cpu/intel/hyperthreading.h
+++ b/src/include/cpu/intel/hyperthreading.h
@@ -3,5 +3,6 @@
struct device;
void intel_sibling_init(struct device *cpu);
+int intel_ht_sibling(void);
#endif /* CPU_INTEL_HYPERTHREADING_H */