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| author | Aaron Durbin <adurbin@chromium.org> | 2020-05-28 10:19:18 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-08 19:08:11 +0000 |
| commit | a2c045bd404cd5f80dcf4cf7a42353f0685e219f (patch) | |
| tree | 018dbfa391c0b995e0a5ae4cc0e0c48decb18d4b | |
| parent | e80a1b1690d9d70e14cd7aa0b99fa317ac33b4e4 (diff) | |
| download | coreboot-a2c045bd404cd5f80dcf4cf7a42353f0685e219f.tar.xz | |
soc/amd/picasso: solve MTRRs only from 4GiB and below
Use x86_setup_mtrrs_with_detect_no_above_4gb() to only
solve the MTRR solution for memory up to 4GiB. This assumes
4GiB to TOM2 is marked as writeback in sys_cfg MSR.
BUG=b:155426691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41898
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index de9a2fa96d..96edd70c13 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -36,7 +36,7 @@ static struct smm_relocation_params smm_reloc_params; */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect(); + x86_setup_mtrrs_with_detect_no_above_4gb(); x86_mtrr_check(); } |