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authorJohnny Lin <johnny_lin@wiwynn.com>2020-02-19 16:13:15 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-25 10:42:25 +0000
commita956063e5f9c19179e4bacd145e26e159f1982b2 (patch)
tree6b389233957e4af55a648a450130f87ac884597d
parentebb7f54b1a107816e4f83bc31f1631acb85700d1 (diff)
downloadcoreboot-a956063e5f9c19179e4bacd145e26e159f1982b2.tar.xz
mb/ocp/tiogapass: Enable IPMI KCS
A bigger than zero value of bmc_boot_timeout must be set for KCS ipmi_get_bmc_self_test_result() to run, otherwise the self test result will be error and won't write SMBIOS type 38 table. Here we set 60 seconds as the maximal self test timeout. Tested=Check if the BMC IPMI response data and SMBIOS type 38 on OCP Tioga Pass are correct or not. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r--src/mainboard/ocp/tiogapass/Kconfig1
-rw-r--r--src/mainboard/ocp/tiogapass/devicetree.cb10
2 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
index b3b43fb20d..9dbc066f10 100644
--- a/src/mainboard/ocp/tiogapass/Kconfig
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_XEON_SP
select MAINBOARD_USES_FSP2_0
select FSP_CAR
+ select IPMI_KCS
config MAINBOARD_DIR
string
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
index 4a5bb1d3f2..c2eddf270c 100644
--- a/src/mainboard/ocp/tiogapass/devicetree.cb
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -51,6 +51,8 @@ chip soc/intel/xeon_sp
register "coherency_support" = "1"
register "ats_support" = "1"
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
device cpu_cluster 0 on
device lapic 0 on end
end
@@ -81,7 +83,13 @@ chip soc/intel/xeon_sp
device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
- device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+ device pci 1f.0 on
+ chip drivers/ipmi # BMC KCS
+ device pnp ca2.0 on end
+ register "bmc_i2c_address" = "0x20"
+ register "bmc_boot_timeout" = "60"
+ end
+ end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller